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Abstract The Technology behind every electronic fore, there must be alternating circuit model to reduce the
gadgets or device has a rapid growth in the market and amount of leakage power when the technology has a rapid
also in the industry. As all the complex electronic devices growth[4].
are operating at higher frequency and operating in sub Cmos circuits plays a vital role in the designing of memory
threshold region, which leads to delivering higher leakage circuit modeling, as it deals with higher switching speed, a
power at lower operating voltages, and especially when basic circuit to implement all the kind of design. an
the technology is gradually increasing, mostly in cmos implementation of SRAM is done with 8T model. RAM is
design. So there ought to be a reliable mode of circuit or one of the main functional unit and takes maximum power
structure which can be a tradeoff between speed, power especially when it is under dynamic mode of operation The
and area. So the broad side of this work designates the amount of static power is maximum when the circuit is in
analysis of Gate diffused input method (GDI) which can be cutoff state.
an alternative logic for the implementation of SRAM bit This leakage power is dominating the dynamic power when
cell instead of CMOS, and relative, comparative analysis the technology is rapidly growing. SRAM is one of the
of delay & power of CMOS with GDI at 0.4v at 32nm hearts of the processing element and processing read and
Synopsys tools by obtaining the proper characteristics of writes operations simultaneously. For achieving high
ac and dc analysis. performance and more reliable operation, there by changing
Keywords cmos, GDI, Subthreshold operation, Static, the different parameters. Therefore the energy consumption
Dynamic power. per bit is drastically reduced, which will leads to more
efficient design. In order to reduce the power consumption
I. INTRODUCTION of SRAM ,there is relay on different types of process
The demand for portable electronic devices increasing day variations like sensing unit, supply voltage, size reduction.
by day, as the Technology has a rapid growth in the in This paper characterizes SRM is design model staring of
industry. As Most of the electronics gadgets are battery inverter, 8T SRAM In cmos & GDI of different parameters
operated and increasing the demand for portable and static and dynamic power, rise and fall time delay & its
popularity of electronic products, the researchers have characteristics by considering the advantages[3][4]
driven strive to achieve higher speed and longer battery This Paper designated as follows section I clarify operation
life. of cmos inverter, and its characteristics. Section II
There were number of techniques proposed in past decades, enlightens the operation GDI inverter. Performance &
to reduce the power and leakage, by operating the device Implementation of Gate diffused input (GDI) sram in
under sub threshold region. But generously there are drastic section III. In section IV explains the power analysis of 8T
changes in higher leakage power & current. More CMOS SRAM. power analysis of GDI 8T SRAM describes
predominantly this leakage power is dominating the in section V. delay estimation of sram cmos is done in
dynamic and static power. section VI.in section VII GDI delay estimation ids done.[1]
But the problem in the Cmos design is leakage power when
the technology is moving on to higher levels. According to
the survey given by Intel, leakage power is dominating
when the technology is upgrading, as technology has a
rapid growth, the amount of complexity of electronic
circuits is also increasing according to the customer needs
and the relationship is as showed below Fig 1. So there
Delay analysis
8
6
4
2 CMOS
0 GDI
Dynami
Static
Total
VIII. CONCLUSION
Static Power is reduced by a factor 63 % dynamic Power is
reduced by a factor of 46% and Approximately 55 % on
total power but In GDI The Rise Time Is Reduced By 1.5
% And Fall Time Is Decreased By 11%Approximately 6 %
on total delay by maintaining the performance.Tolls used
were Synopsys Designer -implementation & modelling
,Custom Ic Designer performance and Custom Complier
power and delay.
REFERENCES
[1] GDI based full adders for energy efficient arithmetic
applications by Mohan Shoba & Rangaswamy
Nakkeeran,
http://dx.doi.org/10.1016/j.jestch.2015.09.006,2215-
0986/Copyright 2015.
[2] Ref:digital subthreshold logic design motivation and
challenges by Sagi Fisher, The VLSI Systems Center,
Ben-Gurion University, Beer-Sheva, Israel 1-4244-
2482-5/08/$20.00 2008 IEEE 702 IEEEI 2008
[3] Energy-Efficient Subthreshold Processor DesignBo
Zhai, Sanjay Pant, by ieee transactions on very large
scale integration (vlsi) systems, vol. 17, no. 8, august
2009.