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Abstract A new 3-Input XOR gate based upon the pass example in Table1.(a) helps in easily understanding the
transistor design methodology for low voltage, a low-voltage proposed circuit. In example we have assumed input bits to be
high-speed application is proposed to implement parity 1, 0, and 1 and accordingly checked which transistors are
generator. An even parity bit generator generates an output of 0 ON or OFF. The circuit has very short transition path and
if the number of 1s in the input sequence is even and 1 if the full-swing signal at output.
number of 1s in the input sequence is odd. The checker circuit
gives an output of 0 if there is no error in the parity bit P1 P2 P3 P4 P5 P6 N1 N2 N3 N4 N5 N6
generated. Thus it basically checks to see if the parity bit X=1
Y=0 Off On Off On Off On Off On On Off Off On
generator is error free or not. Z=1
The average delay-time is calculated with the input signals The proposed 3-input XOR gate circuit has an excellent
(Gray code) varying from XYZ=000 to XYZ=100. The performance at power-delay product factor at all supply
simulated supply voltages are 5V, 3.3V, 2.5V, 2V, lV, voltages. So, this design proves to be better to generate parity
respectively. The simulation results for supply voltage to be bit and accordingly find if/any error are there or not in a bit
5V and 2V are shown in Table 1.(b). At high supply voltages train.
(5V), the new proposed circuit Fig2.(a) has at least 10-20%
improvement in power-delay product than the CPL structure
and 25-30% improvement than the CMOS structure. At low
supply voltage (2V) the new proposed circuit has at least 40%
improvement in power-delay product than the CPL structure
and 10-15% improvement than the CMOS structure.
Moreover the new proposed circuit could also be operated as
low as 1V. It is clear that although more transistors are used in
the proposed circuit, but it does not mean extra power
dissipation due to its passive transistor switches and full
output voltage swing property. So the proposed circuit can be
a well design for low-power and low-voltage applications.
And when it comes to low-voltage, row-power and high-speed
applications the new proposed circuit seems the best choice. Fig1.(a)
At 5V supply,
Rise Time Delay, tdr = 435.33ps
Fall Time Delay, tdf = 564.65ps
Total Delay (td = (tdr + t df)/2) = 499.99ps
At 2V supply,
Rise Time Delay, tdr = 830.85ps
Fall Time Delay, tdf = 577.46ps
Fig1.(b)
Total Delay (td = (tdr + t df)/2) = 704.09ps
Fig1.(c)
REFERENCES
[5] http://en.wikipedia.org/wiki/Parity_bit.
Fig2.(a) Schematic of proposed Even Parity Bit Generator (made using Tanner S-Edit)