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MUX-2
MUX-1
FF1
FF0 0
0 Combinational DFF
DFF 1
IN 1 Circuit
I nitial State 1 0 0 0
0 1 0 0 capture
0 0 1 0
0 0 0 1
Outline
o Motivation
o Previous Work
o Multi-Cycle Path
o Necessary Conditions for Path Sensitization
o Identification of Multi-Cycle False Paths
o Valid Clock Period
o Experimental Result
o Conclusion
Previous Work
o Define: multi-cycle flip-flop pair
FFi (t ) FFi (t 1) FF j (t 1) FF j (t 2)
o All paths between multi-cycle flip-flop pairs are
then declared as multi-cycle paths
DFF DFF
o Stable state checking
BDD [K. Nakamura, ICCAD-1997]
SAT [K. Nakamura, IEICE-2000]
ATPG [H. Higuchi, DAC-2002]
Multi-Cycle Flip-Flop Pair Example
I nitial State 1 0 0 0
Invalid Clock Calculation
o Stable state checking might not result in correct classification of multi-
cycle flip-flop pairs due the presence of static-hazard [H. Higuchi 2002]
FF1
FF0 0
0 Combinational DFF
DFF Circuit 1
IN 1
FF1
DFF
Combinational
Circuit
FF3
DFF
0 0
Outline
o Motivation
o Previous Work
o Multi-Cycle Path
o Necessary Conditions for Path Sensitization
o Identification of Multi-Cycle False Paths
o Valid Clock Period
o Experimental Result
o Conclusion
Multi-Cycle Path
o Definition: A k-cycle path Px could complete the
propagation of the signal transition from the source to the
destination in k cycles
o Clock period could be shorter than the delay of Px
Target Circuit
Px
clk
Model for Illustration and Analysis
TF-1 TF-2
Px
seg-1
seg-2
Outline
o Motivation
o Previous Work
o Multi-Cycle Path
o Necessary Conditions for Path Sensitization
o Identification of Multi-Cycle False Paths
o Valid Clock Period
o Experimental Result
o Conclusion
Necessary Conditions for Single-Cycle
Sensitizable Path
o Functional sensitization criterion [Cheng]
A path is sensitizable if there exists an input vector
such that all the side-inputs along the path are non-
controlling values when the corresponding on-input
propagates a non-controlling value
1 (ncv) on-input
1 (ncv)
Path
1 (ncv) side-input
Necessary Conditions for Multi-Cycle
Sensitizable Path
o Each segment of a multi-cycle sensitizable path must
satisfy the functional sensitization criterion in its
corresponding timeframe. Otherwise, it is false.
TF-1 TF-2
seg-2
seg-1
Outline
o Motivation
o Previous Work
o Multi-Cycle Path
o Necessary Conditions for Path Sensitization
o Identification of Multi-Cycle False Paths
o Valid Clock Period
o Experimental Result
o Conclusion
Identification of Multi-Cycle False Paths
o Input
A path Px
The multiplicity k
The clock period clk
o Output
The sensitizability of path Px
Segment-Based Checking Algorithm
o Check the sensitizability of each segment of the multi-
cycle path at each timeframe
Target Circuit
Px a=1 d=1
b=1 c=1
Outline
o Motivation
o Previous Work
o Multi-Cycle Path
o Necessary Conditions for Path Sensitization
o Identification of Multi-Cycle False Paths
o Valid Clock Period
o Experimental Result
o Conclusion
Valid Clock Period
o Traditionally, the valid clock period is determined by
the delay of the longest single-cycle sensitizable path
0 0
DFF DFF
1 1
ISCAS85 Circuit
Yes No
Exists path P, which d(P)/k+1 > MAX ?
Outline
o Motivation
o Previous Work
o Multi-Cycle Path
o Necessary Conditions for Path Sensitization
o Identification of Multi-Cycle False Paths
o Valid Clock Period
o Experimental Result
o Conclusion
Experimental Result
Reported Clock Period for exemplar circuit
Outline
o Abstract
o Motivation
o Previous Work
o Multi-Cycle Path
o Necessary Conditions for Path Sensitization
o Identification of Multi-Cycle False Paths
o Valid Clock Period
o Experimental Result
o Conclusion
Conclusion
o Define the multi-cycle false path and the multi-
cycle sensitizable path