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Spartan series dcms have a minimum frequency of 24 MHZ and a maximum of 248
2)Tell me some of constraints you used and their purpose during your design?
There are lot of constraints and will vary for tool to tool ,I am listing some of Xilinx constraints
a) Translate on and Translate off: the Verilog code between Translate on and Translate off is ignored for
synthesis.
b) CLOCK_SIGNAL: is a synthesis constraint. In the case where a clock signal goes through combinatorial logic
before being connected to the clock input of a flip-flop, XST cannot identify what input pin or internal net is the
real clock signal. This constraint allows you to define the clock net.
c) XOR_COLLAPSE: is synthesis constraint. It controls whether cascaded XORs should be collapsed into a single
XOR.
For more constraints detailed description refer to constraint guide.
3) Suppose for a piece of code equivalent gate count is 600 and for another code equivalent gate count is
50,000 will the size of bitmap change?in other words will size of bitmap change it gate count change?
The size of bitmap is irrespective of resource utilization, it is always the same,for Spartan xc3s5000 it is 1.56MB
and will never change.
4) What are different types of FPGA programming modes?what are you currently using ?how to change from
one to another?
Before powering on the FPGA, configuration data is stored externally in a PROM or some other nonvolatile
medium either on or off the board. After applying power, the configuration data is written to the FPGA using any
of five different modes: Master Parallel, Slave Parallel, Master Serial, Slave Serial, and Boundary Scan (JTAG).
The Master and Slave Parallel modes
Mode selecting pins can be set to select the mode, refer data sheet for further details.
7) Can you list out some of synthesizable and non synthesizable constructs?
not synthesizable->>>>
initial
ignored for synthesis.
delays
ignored for synthesis.
events
not supported.
real
Real data type not supported.
time
Time data type not supported.
force and release
Force and release of data types not supported.
fork join
Use nonblocking assignments to get same effect.
user defined primitives
Only gate level primitives are supported.
synthesizable constructs->>
assign,for loop,Gate Level Primitives,repeat with constant value...
These stuck-at problems will appear in ASIC. Some times, the nodes will permanently tie to 1 or 0 because of
some fault. To avoid that, we need to provide testability in RTL. If it is permanently 1 it is called stuck-at-1 If it is
permanently 0 it is called stuck-at-0.
FPGA:
a)SRAM based technology.
b)Segmented connection between elements.
c)Usually used for complex logic circuits.
d)Must be reprogrammed once the power is off.
e)Costly
CPLD:
a)Flash or EPROM based technology.
b)Continuous connection between elements.
c)Usually used for simpler or moderately complex logic circuits.
d)Need not be reprogrammed once the power is off.
e)Cheaper
13)what is slice,clb,lut?
The Configurable Logic Blocks (CLBs) constitute the main logic resource for implementing synchronous as well
as combinatorial circuits.
CLB are configurable logic blocks and can be configured to combo,ram or rom depending on coding style
CLB consist of 4 slices and each slice consist of two 4-input LUT (look up table) F-LUT and G-LUT.
YES.
The memory assignment is a clocked behavioral assignment, Reads from the memory are asynchronous, And all
the address lines are shared by the read and write statements.
The UCF file is an ASCII file specifying constraints on the logical design. You create this file and enter your
constraints in the file with a text editor. You can also use the Xilinx Constraints Editor to create constraints
within a UCF(extention) file. These constraints affect how the logical design is implemented in the target device.
You can use the file to override constraints specified during design entry.
16) What is FPGA you are currently using and some of main reasons for choosing it?
17) Draw a rough diagram of how clock is routed through out FPGA?
18) How many global buffers are there in your current fpga,what is their significance?
Dynamic timing:
a. The design is simulated in full timing mode.
b. Not all possibilities tested as it is dependent on the input test vectors.
c. Simulations in full timing mode are slow and require a lot of memory.
d. Best method to check asynchronous interfaces or interfaces between different timing domains.
Static timing:
a. The delays over all paths are added up.
b. All possibilities, including false paths, verified without the need for test vectors.
c. Much faster than simulations, hours as opposed to days.
d. Not good with asynchronous interfaces or interfaces between different timing domains.
PLL:
PLLs have disadvantages that make their use in high-speed designs problematic, particularly when both high
performance and high reliability are required.
The PLL voltage-controlled oscillator (VCO) is the greatest source of problems. Variations in temperature, supply
voltage, and manufacturing process affect the stability and operating performance of PLLs.
DLLs, however, are immune to these problems. A DLL in its simplest form inserts a variable delay line between
the external clock and the internal clock. The clock tree distributes the clock to all registers and then back to
the feedback pin of the DLL.
The control circuit of the DLL adjusts the delays so that the rising edges of the feedback clock align with the
input clock. Once the edges of the clocks are aligned, the DLL is locked, and both the input buffer delay and the
clock skew are reduced to zero.
Advantages:
precision
stability
power management
noise sensitivity
jitter performance.
24) Given two ASICs. one has setup violation and the other has hold violation. how can they be made to work
together without modifying the design?
DRC is used to check whether the particular schematic and corresponding layout(especially the mask sets
involved) cater to a pre-defined rule set depending on the technology used to design. They are parameters set
aside by the concerned semiconductor manufacturer with respect to how the masks should be placed ,
connected , routed keeping in mind that variations in the fab process does not effect normal functionality. It
usually denotes the minimum allowable configuration.
27)What is LVs and why do we do that. What is the difference between LVS and DRC?
The layout must be drawn according to certain strict design rules. DRC helps in layout of the designs by
checking if the layout is abide by those rules.
After the layout is complete we extract the netlist. LVS compares the netlist extracted from the layout with the
schematic to ensure that the layout is an identical match to the cell schematic.
28)What is DFT ?
DFT means design for testability. 'Design for Test or Testability' - a methodology that ensures a design works
properly after manufacturing, which later facilitates the failure analysis and false product/piece detection
Other than the functional logic,you need to add some DFT logic in your design.This will help you in testing the
chip for manufacturing defects after it come from fab. Scan,MBIST,LBIST,IDDQ testing etc are all part of this.
(this is a hot field and with lots of opportunities)
29) There are two major FPGA companies: Xilinx and Altera. Xilinx tends to promote its hard processor cores
and Altera tends to promote its soft processor cores. What is the difference between a hard processor core and
a soft processor core?
A hard processor core is a pre-designed block that is embedded onto the device. In the Xilinx Virtex II-Pro, some
of the logic blocks have been removed, and the space that was used for these logic blocks is used to implement
a processor. The Altera Nios, on the other hand, is a design that can be compiled to the normal FPGA logic.
DFT:
manufacturing defects like stuck at "0" or "1".
test for set of rules followed during the initial design stage.
Formal verification:
Verification of the operation of the design, i.e, to see if the design follows spec.
gate netlist == RTL ?
using mathematics and statistical analysis to check for equivalence.
32)What is Synthesis?
Synthesis is the stage in the design flow which is concerned with translating your Verilog code into gates - and
that's putting it very simply! First of all, the Verilog must be written in a particular way for the synthesis tool
that you are using. Of course, a synthesis tool doesn't actually produce gates - it will output a netlist of the
design that you have synthesised that represents the chip which can be fabricated through an ASIC or FPGA
vendor.
33)We need to sample an input or output something at different rates, but I need to vary the rate? What's a
clean way to do this?
Many, many problems have this sort of variable rate requirement, yet we are usually constrained with a
constant clock frequency. One trick is to implement a digital NCO (Numerically Controlled Oscillator). An NCO is
actually very simple and, while it is most naturally understood as hardware, it also can be constructed in
software. The NCO, quite simply, is an accumulator where you keep adding a fixed value on every clock (e.g. at
a constant clock frequency). When the NCO "wraps", you sample your input or do your action. By adjusting the
value added to the accumulator each clock, you finely tune the AVERAGE frequency of that wrap event. Now -
you may have realized that the wrapping event may have lots of jitter on it. True, but you may use the wrap to
increment yet another counter where each additional Divide-by-2 bit reduces this jitter. The DDS is a related
technique. I have two examples showing both an NCOs and a DDS in my File Archive. This is tricky to grasp at
first, but tremendously powerful once you have it in your bag of tricks. NCOs also relate to digital PLLs, Timing
Recovery, TDMA and other "variable rate" phenomena.
Implement D flip-flop with a couple of latches? Write a VHDL Code for a D flip-flop?
Differences between Signals and Variables in VHDL? If the same code is written using Signals and Variables
what does it synthesize to?
Explain the concept of a Clock Divider Circuit? Write a VHDL code for the same?
What you would use in RTL a 'boolean' type or a 'std_logic' type and why.
Metastability
What are Async counters, what are advantages of using these over sync counters. and what are the
disadvantages
Sensitivity List:
How does it matter.What will happen
if you dont include a signal in the sensitivity list
and use/read it inside the process
Why does a pass gate requires two transistors(1 N and 1 P type) Can we use a
single transistor N or P type in a pass gate? If not why? and if yes then in what conditions?
Why CMOS why not N-MOS or P-MOS logic, when we know that the number
of gates required in CMOS are grater than in n-mos or p-mos logic.
How much is the max fan out of a typical CMOS gate. Or alternatively,
What are dynamic logic gates? What are their advantages over conventional logic gates
Design a digital circuit to delay the negative edge of the input signal by 2 clock cycles
What is the relation between binary encoding and grey(or gray) encoding.
How you will constraint a combinational logic path through your design
in dc_shell.
Give the truth table for a Half Adder. Give a gate level implementation of it.
What is metastability ?
Design a D and T flip flop using 2:1 mux; use of other components not allowed, just the mux.
You are given a 100 MHz clock. Design a 33.3 MHz clock with and without 50&37; duty cycle.
What are FIFO's? Can you draw the block diagram of FIFO? Could you modify it to make it asynchronous FIFO ?
How can you generate random sequences in digital circuits?
Below questions are asked for senior position in Physical Design domain. The questions are also related to
Static Timing Analysis and Synthesis. Answers to some questions are given as link. Remaining questions will be
answered in coming blogs.
Intel
The resistivity of top metal layers are less and hence less IR drop is seen in power distribution network. If power
stripes are routed in lower metal layers this will use good amount of lower routing resources and therefore it
can create routing congestion.
Answer:
This approach allows routability of the design and better usage of routing resources.
Answer:
Improve the input transition to the cell under consideration by up sizing the driver.
Reduce the load seen by the cell under consideration, either by placement refinement or buffering.
If allowed increase the drive strength or replace with LVT (low threshold voltage) cell.
* How do you compute net delay (interconnect delay) / decode RC values present in tech file?
* What are various ways of timing optimization in synthesis tools?
Answer:
Logic optimization: buffer sizing, cell sizing, level adjustment, dummy buffering etc.
Optimize drive strength of the cell , so it is capable of driving more load and hence reducing the cell delay.
Better selection of design ware component (select timing optimized design ware components).
Use LVT (Low threshold voltage) and SVT (standard threshold voltage) cells if allowed.
* What would you do in order to not use certain cells from the library?
Answer:
Answer:
For a given wireload model the delay are estimated based on the number of fanout of the cell driving the net.
Values of unit resistance R and unit capacitance C are given in technology file.
Once the net length is known delay can be calculated; Sometimes it is again tabulated.
Answer:
Routing and placement congestion all depend upon the connectivity in the netlist , a better floor plan can
reduce the congestion.
* Lets say there enough routing resources available, timing is fine, can you increase clock buffers in clock
network? If so will there be any impact on other parameters?
Answer:
No. You should not increase clock buffers in the clock network. Increase in clock buffers cause more area , more
power. When everything is fine why you want to touch clock tree??
Answer:
Better skew targets and insertion delay values provided while building the clocks.
Choose appropriate tree structure either based on clock buffers or clock inverters or mix of clock buffers or
clock inverters.
For multi clock domain, group the clocks while building the clock tree so that skew is balanced across the
clocks. (Inter clock skew analysis).
* How you go about fixing timing violations for latch- latch paths?
* As an engineer, lets say your manager comes to you and asks for next project die size estimation/projection,
giving data on RTL size, performance requirements. How do you go about the figuring out and come up with die
size considering physical aspects?
* How will you design inserting voltage island scheme between macro pins crossing core and are at different
power wells? What is the optimal resource solution?
* What are various formal verification issues you faced and how did you resolve?
* How do you calculate maximum frequency given setup, hold, clock and clock skew?
* What are effects of metastability?
* Consider a timing path crossing from fast clock domain to slow clock domain. How do you design synchronizer
circuit without knowing the source clock frequency?
* How to solve cross clock timing path?
* How to determine the depth of FIFO/ size of the FIFO?
STmicroelectronics
* What are the challenges you faced in place and route, FV (Formal Verification), ECO (Engineering Change
Order) areas?
* How long the design cycle for your designs?
* What part are your areas of interest in physical design?
* Explain ECO (Engineering Change Order) methodology.
* Explain CTS (Clock Tree Synthesis) flow.
* If there are too many pins of the logic cells in one place within core, what kind of issues would you face and
how will you resolve?
* Define hash/ @array in perl.
* Using TCL (Tool Command Language, Tickle) how do you set variables?
* What is ICC (IC Compiler) command for setting derate factor/ command to perform physical synthesis?
* What are nanoroute options for search and repair?
* What were your design skew/insertion delay targets?
* How is IR drop analysis done? What are various statistics available in reports?
* Explain pin density/ cell density issues, hotspots?
* How will you relate routing grid with manufacturing grid and judge if the routing grid is set correctly?
* What is the command for setting multi cycle path?
* If hold violation exists in design, is it OK to sign off design? If not, why?
Qualcomm
* In building the timing constraints, do you need to constrain all IO (Input-Output) ports?
* Can a single port have multi-clocked? How do you set delays for such ports?
* How is scan DEF (Design Exchange Format) generated?
* What is purpose of lockup latch in scan chain?
* Explain short circuit current.
Answer:
* In DC (Design Compiler), how do you constrain clocks, IO (Input-Output) ports, maxcap, max tran?
* What are differences in clock constraints from pre CTS (Clock Tree Synthesis) to post CTS (Clock Tree
Synthesis)?
Answer:
* What constraints you add in CTS (Clock Tree Synthesis) for clock gates?
Answer:
* What is trade off between dynamic power (current) and leakage power (current)?
Answer:
* Explain top level pin placement flow? What are parameters to decide?
* Given block level netlists, timing constraints, libraries, macro LEFs (Layout Exchange Format/Library Exchange
Format), how will you start floor planning?
* With net length of 1000um how will you compute RC values, using equations/tech file info?
* What do noise reports represent?
* What does glitch reports contain?
* What are CTS (Clock Tree Synthesis) steps in IC compiler?
* What do clock constraints file contain?
* How to analyze clock tree reports?
* What do IR drop Voltagestorm reports represent?
* Where /when do you use DCAP (Decoupling Capacitor) cells?
* What are various power reduction techniques?
Hughes Networks
* What is setup/hold? What are setup and hold time impacts on timing? How will you fix setup and hold
violations?
* Explain function of Muxed FF (Multiplexed Flip Flop) /scan FF (Scal Flip Flop).
* What are tested in DFT (Design for Testability)?
* In equivalence checking, how do you handle scanen signal?
* In terms of CMOS (Complimentary Metal Oxide Semiconductor), explain physical parameters that affect the
propagation delay?
* What are power dissipation components? How do you reduce them?
Hynix Semiconductor
* How do you optimize power at various stages in the physical design flow?
* What timing optimization strategies you employ in pre-layout /post-layout stages?
* What are process technology challenges in physical design?
* Design divide by 2, divide by 3, and divide by 1.5 counters. Draw timing diagrams.
* What are multi-cycle paths, false paths? How to resolve multi-cycle and false paths?
* Given a flop to flop path with combo delay in between and output of the second flop fed back to combo logic.
Which path is fastest path to have hold violation and how will you resolve?
* What are RTL (Register Transfer Level) coding styles to adapt to yield optimal backend design?
* Draw timing diagrams to represent the propagation delay, set up, hold, recovery, removal, minimum pulse
width.
About Contributor
ASIC_diehard has more than 5 years of experience in physical design, timing, netlist to GDS flows of Integrated
Circuit development. ASIC_diehard's fields of interest are backend design, place and route, timing closure,
process technologies.
Readers are encouraged to discuss answers to these questions. Just click on the 'post a comment' option below
and put your comments there. Alternatively you can send your answers/discussions to my mail id:
shavakmm@gmail.com
Physical Design Objective Type of Questions and Answers
a. Useful skew
b. Local skew
c. Global skew
d. Slack
a. Clock nets
b. Signal nets
c. IO nets
d. PG nets
a. Metal1
b. Metal2
c. Metal3
d. Metal4
a. Minimum IR Drop
b. Minimum EM
c. Minimum Skew
d. Minimum Slack
a. Before Placement
b. After Placement
c. Before CTS
d. After CTS
* 10) To achieve better timing ____ cells are placed in the critical path.
a. HVT
b. LVT
c. RVT
d. SVT
a. Frequency
b. Load Capacitance
c. Supply voltage
d. Threshold Voltage
a. Reducing IR Drop
b. Reducing DRC
c. Reducing EM violations
d. None
a. .lib
b. .v
c. .tf
d. .sdc
* 16) The minimum height and width a cell can occupy in the design is called as ___.
a. Max delay is used for launch path and Min delay for capture path
b. Min delay is used for launch path and Max delay for capture path
c. Both Max delay is used for launch and Capture path
d. Both Min delay is used for both Capture and Launch paths
* 19) "Total metal area and(or) perimeter of conducting layer / gate to gate area" is called ___.
a. Utilization
b. Aspect Ratio
c. OCV
d. Antenna Ratio
a. Diode insertion
b. Shielding
c. Buffer insertion
d. Double spacing
* 21) To avoid cross talk, the shielded net is usually connected to ___.
a. VDD
b. VSS
c. Both VDD and VSS
d. Clock
* 22) If the data is faster than the clock in Reg to Reg path ___ violation may come.
a. Setup
b. Hold
c. Both
d. None
a. Before placement
b. After placement
c. Before CTS
d. After CTS
a. Max tran
b. Max cap
c. Max fanout
d. Max current density
* 26) Which of the following is having highest priority at final stage (post routed) of the design ___?
a. Setup violation
b. Hold violation
c. Skew
d. None
a. CLKBUF
b. BUF
c. INV
d. CLKINV
* 28) Max voltage drop will be there at(with out macros) ___.
a. Min width
b. Min spacing
c. Min width - min spacing
d. Min width + min spacing
a. Floorplaning
b. Placement
c. Design Synthesis
d. CTS
* 33) In technology file if 7 metals are there then which metals you will use for power?
* 34) If metal6 and metal7 are used for the power in 7 metal layer process design then which metals you will
use for clock ?
* 35) In a reg to reg timing path Tclocktoq delay is 0.5ns and TCombo delay is 5ns and Tsetup is 0.5ns then the
clock period should be ___.
a. 1ns
b. 3ns
c. 5ns
d. 6ns
* 40) After the final routing the violations in the design ___.
a. Constant
b. Decrease
c. Increase
d. None of the above
a. Power routing
b. Signal routing
c. Power and Signal routing
d. None of the above.
a. Clock buffer
b. Clock Inverter
c. AOI cell
d. None of the above
* Answers:
1)b
2)c
3)b
4)c
5)b
6)d
7)a
8)c
9)d
10)b
11)d
12)d
13)b
14)c
15)b
16)a
17)c
18)a
19)d
20)a
21)b
22)b
23)d
24)d
25)c
26)b
27)a
28)c
29)d
30)c
31)d
32)c
33)d
34)c
35)d
36)c
37)a
38)c
39)b
40)d
41)c
42)a
43)a
44)c
Backend (Physical Design) Interview Questions and Answers
* Below are the sequence of questions asked for a physical design engineer.
* Answer to this question depends on your interest, expertise and to the requirement for which you have been
interviewed.
* Leakage current of a gate is dependant on its inputs also. Hence find the set of inputs which gives least
leakage. By applyig this minimum leakage vector to a circuit it is possible to decrease the leakage current of
the circuit when it is in the standby mode. This method is known as input vector controlled method of leakage
reduction.
If you have both IR drop and congestion how will you fix it?
* -Spread macros
* -Spread standard cells
* -Increase strap width
* -Increase number of straps
* -Use proper blockage
Is increasing power line width and providing more number of straps are the only solution to IR drop?
* -Spread macros
* -Spread standard cells
* -Use proper blockage
In a reg to reg path if you have setup problem where will you insert buffer-near to launching flop or capture
flop? Why?
* (buffers are inserted for fixing fanout voilations and hence they reduce setup voilation; otherwise we try to fix
setup voilation with the sizing of cells; now just assume that you must insert buffer !)
* Because there may be other paths passing through or originating from the flop nearer to lauch flop. Hence
buffer insertion may affect other paths also. It may improve all those paths or degarde. If all those paths have
voilation then you may insert buffer nearer to launch flop provided it improves slack.
* -If it is from seperate clock sources (i.e.asynchronous; from different pads or pins) then balancing skew
between these clock sources becomes challenging.
* Switching of the signal in one net can interfere neigbouring net due to cross coupling capacitance.This affect
is known as cros talk. Cross talk may lead setup or hold voilation.
* -High frequency noise (or glitch)is coupled to VSS (or VDD) since shilded layers are connected to either VDD
or VSS.
* width is more=>more spacing between two conductors=>cross coupling capacitance is less=>less cross talk
Why double spacing and multiple vias are used related to clock?
* Why clock?-- because it is the one signal which chages it state regularly and more compared to any other
signal. If any other signal switches fast then also we can use double space.
* Buffer increase victims signal strength; buffers break the net length=>victims are more tolerant to coupled
signal from aggressor.
* I am getting several emails requesting answers to the questions posted in this blog. But it is very difficult to
provide detailed answer to all questions in my available spare time. Hence i decided to give "short and sweet"
one line answers to the questions so that readers can immediately benefited. Detailed answers will be posted in
later stage.I have given answers to some of the physical design questions here. Enjoy !
What parameters (or aspects) differentiate Chip Design and Block level design?
* Chip design uses all metal layes available; block design may not use all metal layers.
* First check flylines i.e. check net connections from macro to macro and macro to standard cells.
* If there is more connection from macro to macro place those macros nearer to each other preferably nearer to
core boundaries.
* If input pin is connected to macro better to place nearer to that pin or pad.
* If macro has more connection to standard cells spread the macros inside core.
* Hierarchial design has blocks, subblocks in an hierarchy; Flattened design has no subblocks and it has only
leaf cells.
* Hierarchical design takes more run time; Flattened design takes less run time.
Which is more complicated when u have a 48 MHz and 500 MHz clock design?
* 500 MHz; because it is more constrained (i.e.lesser clock period) than 48 MHz design.
If the routing congestion exists between two macros, then what will you do?
* By checking the total area of the design you can decide die size.
If lengthy metal layer is connected to diffusion and poly, then which one will affect by antenna problem?
* Poly
If the full chip design is routed by 7 layer metal, why macros are designed using 5LM instead of using 7LM?
* Because top two metal layers are required for global routing in chip design. If top metal layers are also used in
block level it will create routing blockage.
In your project what is die size, number of metal layers, technology, foundry, number of clocks?
* Die size: tell in mm eg. 1mm x 1mm ; remeber 1mm=1000micron which is a big size !!
* Foundry:Again look into tech files; eg. TSMC, IBM, ARTISAN etc
* You know it well as you have designed it ! A SoC (System On Chip) design may have 100 macros also !!!!
* For Physical design: Netlist, Technology library, Constraints, Standard cell library
* Clock definitions
* Timing exception-multicycle path, false path
How did you do power planning? How to calculate core ring width, macro ring width and strap or trunk width?
How to find number of power pad and IO power pads? How the width of metal and number of straps calculated
for power and ground?
* Get the total core power consumption; get the metal layer current density value from the tech file; Divide
total power by number sides of the chip; Divide the obtained value from the current density to get core power
ring width. Then calculate number of straps using some more equations. Will be explained in detail later.
* Total chip power=standard cell power consumption,Macro power consumption pad power consumption.
* Next lower layer to the top two metal layers(global routing layers). Because it has less resistance hence less
RC delay.
If in your design has reset pin, then itll affect input pin or output pin or both?
* Output pin.
During power analysis, if you are facing IR drop problem, then how did you avoid?
Define antenna problem and how did you resolve these problem?
* Increased net length can accumulate more charges while manufacturing of the device due to ionisation
process. If this net is connected to gate of the MOSFET it can damage dielectric property of the gate and gate
may conduct causing damage to the MOSFET. This is antenna problem.
* Decrease the length of the net by providing more vias and layer jumping.
How delays vary with different PVT conditions? Show the graph.
* P increase->dealy increase
* P decrease->delay decrease
* V increase->delay decrease
* V decrease->delay increase
* T increase->delay increase
* T decrease->delay decrease
Explain the flow of physical design and inputs and outputs for each step in flow.
* Gate delay
* Transistors within a gate take a finite time to switch. This means that a change on the input of a gate takes a
finite time to cause a change on the output.[Magma]
* Cell delay
* For any gate it is measured between 50% of input transition to the corresponding 50% of output transition.
* Intrinsic delay
* Intrinsic delay is the delay internal to the gate. Input pin of the cell to output pin of the cell.
* It is defined as the delay between an input and output pair of a cell, when a near zero slew is applied to the
input pin and the output does not see any load condition.It is predominantly caused by the internal capacitance
associated with its transistor.
* This delay is largely independent of the size of the transistors forming the gate because increasing size of
transistors increase internal capacitors.
* It is due to the finite resistance and capacitance of the net.It is also known as wire delay.
What are delay models and what is the difference between them?
* Wire load model is NLDM which has estimated R and C of the net.
Why higher metal layers are preferred for Vdd and Vss?
* Upsizing
* Downsizing
* Buffer insertion
* Buffer relocation
* IR drop, Electro Migration (EM), Crosstalk, Ground bounce are signal integrity issues.
* There is a resistance associated with each metal layer. This resistance consumes power causing voltage drop
i.e.IR drop.
* Due to high current flow in the metal atoms of the metal can displaced from its origial place. When it happens
in larger amount the metal can open or bulging of metal layer can happen. This effect is known as Electro
Migration.
* Global Routing
* Track Assignment
* Detail Routing
* Source Latency
* It is known as source latency also. It is defined as "the delay from the clock origin point to the clock definition
point in the design".
* Delay from clock source to beginning of clock tree (i.e. clock definition point).
* The time a clock signal takes to propagate from its ideal waveform origin point to the clock definition point in
the design.
* Network latency
* It is also known as Insertion delay or Network latency. It is defined as "the delay from the clock definition point
to the clock pin of the register".
* The time clock signal (rise or fall) takes to propagate from the clock definition point to a register clock pin.
* Second stage of the routing wherein particular metal tracks (or layers) are assigned to the signal nets.
What is congestion?
* If the number of routing tracks available for routing is less than the required tracks then it is known as
congestion.
* Routing
What are clock trees?
* Distribution of clock from the clock source to the sync pin of the registers.
* Cloning is a method of optimization that decreases the load of a heavily loaded cell by replicating the cell.
* Buffering is a method of optimization that is used to insert beffers in high fanout nets to decrease the dealy.
* What is the difference between hard macro, firm macro and soft macro?
or
* Hard macro, firm macro and soft macro are all known as IP (Intellectual property). They are optimized for
power, area and performance. They can be purchased and used in your ASIC or FPGA design implementation
flow. Soft macro is flexible for all type of ASIC implementation. Hard macro can be used in pure ASIC design
flow, not in FPGA flow. Before bying any IP it is very important to evaluate its advantages and disadvantages
over each other, hardware compatibility such as I/O standards with your design blocks, reusability for other
designs.
Soft macros
* Soft macros have the disadvantage of being somewhat unpredictable in terms of performance, timing, area,
or power.
* Soft macros carry greater IP protection risks because RTL source code is more portable and therefore, less
easily protected than either a netlist or physical layout data.
* From the physical design perspective, soft macro is any cell that has been placed and routed in a placement
and routing tool such as Astro. (This is the definition given in Astro Rail user manual !)
* Soft macros are editable and can contain standard cells, hard macros, or other soft macros.
Firm macros
* Firm macros are more flexible and portable than hard macros.
* Firm macros are predictive of performance and area than soft macros.
Hard macro
* Hard macros are generally in the form of hardware IPs (or we termed it as hardwre IPs !).
* Hard macros are block level designs which are silicon tested and proved.
* In physical design you can only access pins of hard macros unlike soft macros which allows us to manipulate
in different way.
* You have freedom to move, rotate, flip but you can't touch anything inside hard macros.
* Very common example of hard macro is memory. It can be any design which carries dedicated single
functionality (in general).. for example it can be a MP4 decoder.
* Be aware of features and characteristics of hard macro before you use it in your design... other than power,
timing and area you also should know pin properties like sync pin, I/O standards etc
* LEF, GDS2 file format allows easy usage of macros in different tools.
* Hard macro is a block that is generated in a methodology other than place and route (i.e. using full custom
design methodology) and is brought into the physical design database (eg. Milkyway in Synopsys; Volcano in
Magma) as a GDS2 file.
Synthesis and placement of macros in modern SoC designs are challenging. EDA tools employ different
algorithms accomplish this task along with the target of power and area. There are several research papers
available on these subjects. Some of them can be downloaded from the given link below.
Answer:
Clock net is one of the High Fanout Net(HFN)s. The clock buffers are designed with some special property like
high drive strength and less delay. Clock buffers have equal rise and fall time. This prevents duty cycle of clock
signal from changing when it passes through a chain of clock buffers.
Normal buffers are designed with W/L ratio such that sum of rise time and fall time is minimum. They too are
designed for higher drive strength.
What is difference between HFN synthesis and CTS?
Answer:
HFNs are synthesized in front end also.... but at that moment no placement information of standard cells are
available... hence backend tool collapses synthesized HFNs. It resenthesizes HFNs based on placement
information and appropriately inserts buffer. Target of this synthesis is to meet delay requirements i.e. setup
and hold.
For clock no synthesis is carried out in front end (why.....????..because no placement information of flip-flops !
So synthesis won't meet true skew targets !!) ... in backend clock tree synthesis tries to meet "skew" targets...It
inserts clock buffers (which have equal rise and fall time, unlike normal buffers !)... There is no skew information
for any HFNs.
Is it possible to have a zero skew in the design?
Answer:
Theoretically it is possible....!
Practically it is impossible....!!
Practically we cant reduce any delay to zero.... delay will exist... hence we try to make skew "equal" (or same)
rather than "zero"......now with this optimization all flops get the clock edge with same delay relative to each
other.... so virtually we can say they are having "zero skew " or skew is "balanced".
Physical Design Interview Questions
Below are the important interview questions for VLSI physical design aspirants. Interview starts with flow of
physical design and goes on.....on....on..... I am trying to make your life easy..... let me prepare answers to all
these if soft form.... as soon as it happens those answers will be posted in coming blogs.
*
What parameters (or aspects) differentiate Chip Design & Block level design??
*
How do you place macros in a full chip design?
*
Differentiate between a Hierarchical Design and flat design?
*
Which is more complicated when u have a 48 MHz and 500 MHz clock design?
*
Name few tools which you used for physical verification?
*
What are the input files will you give for primetime correlation?
*
What are the algorithms used while routing? Will it optimize wire length?
*
How will you decide the Pin location in block level design?
*
If the routing congestion exists between two macros, then what will you do?
*
How will you place the macros?
*
How will you decide the die size?
*
If lengthy metal layer is connected to diffusion and poly, then which one will affect by antenna problem?
*
If the full chip design is routed by 7 layer metal, why macros are designed using 5LM instead of using 7LM?
*
In your project what is die size, number of metal layers, technology, foundry, number of clocks?
*
How many macros in your design?
*
What is each macro size and no. of standard cell count?
*
How did u handle the Clock in your design?
*
What are the Input needs for your design?
*
What is SDC constraint file contains?
*
How did you do power planning?
*
How to find total chip power?
*
How to calculate core ring width, macro ring width and strap or trunk width?
*
How to find number of power pad and IO power pads?
*
What are the problems faced related to timing?
*
How did u resolve the setup and hold problem?
*
If in your design 10000 and more numbers of problems come, then what you will do?
*
In which layer do you prefer for clock routing and why?
*
If in your design has reset pin, then itll affect input pin or output pin or both?
*
During power analysis, if you are facing IR drop problem, then how did u avoid?
*
Define antenna problem and how did u resolve these problem?
*
How delays vary with different PVT conditions? Show the graph.
*
Explain the flow of physical design and inputs and outputs for each step in flow.
*
What is cell delay and net delay?
*
What are delay models and what is the difference between them?
*
What is wire load model?
*
What does SDC constraints has?
*
Why higher metal layers are preferred for Vdd and Vss?
*
What is logic optimization and give some methods of logic optimization.
*
What is the significance of negative slack?
*
What is signal integrity? How it affects Timing?
*
What is IR drop? How to avoid .how it affects timing?
*
What is EM and it effects?
*
What is floor plan and power plan?
*
What are types of routing?
*
What is a grid .why we need and different types of grids?
*
What is core and how u will decide w/h ratio for core?
*
What is effective utilization and chip utilization?
*
What is latency? Give the types?
*
How the width of metal and number of straps calculated for power and ground?
*
What is negative slack ? How it affects timing?
*
What is track assignment?
*
What is grided and gridless routing?
*
What is a macro and standard cell?
*
What is congestion?
*
Whether congestion is related to placement or routing?
*
What are clock trees?
*
What are clock tree types?
*
Which layer is used for clock routing and why?
*
What is cloning and buffering?
*
What are placement blockages?
*
How slow and fast transition at inputs effect timing for gates?
*
What is antenna effect?
*
What are DFM issues?
*
What is .lib, LEF, DEF, .tf?
*
What is the difference between synthesis and simulation?
*
What is metal density, metal slotting rule?
*
What is OPC, PSM?
*
Why clock is not synthesized in DC?
*
What are high-Vt and low-Vt cells?
*
What corner cells contains?
*
What is the difference between core filler cells and metal fillers?
*
How to decide number of pads in chip level design?
*
What is tie-high and tie-low cells and where it is used
*
What is LEF?
*
What is DEF?
*
What are the steps involved in designing an optimal pad ring?
* What are the steps that you have done in the design flow?
* What are the issues in floor plan?
* How can you estimate area of block?
* How much aspect ratio should be kept (or have you kept) and what is the utilization?
* How to calculate core ring and stripe widths?
* What if hot spot found in some area of block? How you tackle this?
* After adding stripes also if you have hot spot what to do?
* What is threshold voltage? How it affect timing?
* What is content of lib, lef, sdc?
* What is meant my 9 track, 12 track standard cells?
* What is scan chain? What if scan chain not detached and reordered? Is it compulsory?
* What is setup and hold? Why there are ? What if setup and hold violates?
* In a circuit, for reg to reg path ...Tclktoq is 50 ps, Tcombo 50ps, Tsetup 50ps, tskew is 100ps. Then what is the
maximum operating frequency?
* How R and C values are affecting time?
* How ohm (R), fared (C) is related to second (T)?
* What is transition? What if transition time is more?
* What is difference between normal buffer and clock buffer?
* What is antenna effect? How it is avoided?
* What is ESD?
* What is cross talk? How can you avoid?
* How double spacing will avoid cross talk?
* What is difference between HFN synthesis and CTS?
* What is hold problem? How can you avoid it?
* For an iteration we have 0.5ns of insertion delay and 0.1 skew and for other iteration 0.29ns insertion delay
and 0.25 skew for the same circuit then which one you will select? Why?
* What is partial floor plan?
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