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SEMICONDUCTOR TECHNICAL DATA by MTW10N100E/D

  
 





 Motorola Preferred Device

!&" 
$ " ##$!"
 &$ #!$ !% $  ! TMOS POWER FET
NChannel EnhancementMode Silicon Gate 10 AMPERES
1000 VOLTS
This high voltage MOSFET uses an advanced termination RDS(on) = 1.3 OHM
scheme to provide enhanced voltageblocking capability without
degrading performance over time. In addition, this advanced TMOS
EFET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a

draintosource diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transient.
Robust High Voltage Termination
Avalanche Energy Specified D
SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature G
CASE 340K01, Style 1
Isolated Mounting Hole Reduces Mounting Hardware
TO247AE
S
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating Symbol Value Unit
DrainSource Voltage VDSS 1000 Vdc
DrainGate Voltage (RGS = 1.0 M) VDGR 1000 Vdc
GateSource Voltage Continuous VGS 20 Vdc
GateSource Voltage NonRepetitive (tp 10 ms) VGSM 40 Vpk
Drain Current Continuous ID 10 Adc
Drain Current Continuous @ 100C ID 6.2
Drain Current Single Pulse (tp 10 s) IDM 30 Apk
Total Power Dissipation PD 250 Watts
Derate above 25C 2.0 W/C
Operating and Storage Temperature Range TJ, Tstg 55 to 150 C
Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C EAS 500 mJ
(VDD = 100 Vdc, VGS = 10 Vdc, IL = 10 Apk, L = 10 mH, RG = 25 )
Thermal Resistance Junction to Case RJC 0.50 C/W
Thermal Resistance Junction to Ambient RJA 40
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds TL 260 C
Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

EFET and Designers are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 3

Motorola TMOS
Motorola, Inc. 1996 Power MOSFET Transistor Device Data 1
MTW10N100E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
DrainSource Breakdown Voltage V(BR)DSS
(VGS = 0 Vdc, ID = 250 Adc) 1000 Vdc
Temperature Coefficient (Positive) 1,254 mV/C
Zero Gate Voltage Drain Current IDSS Adc
(VDS = 1000 Vdc, VGS = 0 Vdc) 10
(VDS = 1000 Vdc, VGS = 0 Vdc, TJ = 125C) 100
GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS 100 nAdc
ON CHARACTERISTICS (1)
Gate Threshold Voltage VGS(th)
(VDS = VGS, ID = 250 Adc) 2.0 3.0 4.0 Vdc
Temperature Coefficient (Negative) 7.0 mV/C
Static DrainSource OnResistance (VGS = 10 Vdc, ID = 5.0 Adc) RDS(on) 1.10 1.3 Ohm
DrainSource OnVoltage (VGS = 10 Vdc) VDS(on) Vdc
(ID = 10 Adc) 11 15
(ID = 5.0 Adc, TJ = 125C) 15.3
Forward Transconductance (VDS = 15 Vdc, ID = 5.0 Adc) gFS 8.0 10 mhos
DYNAMIC CHARACTERISTICS
Input Capacitance Ciss 3500 5600 pF
Output Capacitance (VDS = 25 Vdc,
Vdc VGS = 0 Vdc,
Vdc
Coss 264 530
f = 1.0 MHz)
Reverse Transfer Capacitance Crss 52 90

SWITCHING CHARACTERISTICS (2)

TurnOn Delay Time td(on) 29 60 ns
Rise Time (VDD = 500 Vdc,
Vd ID = 10 Ad
Adc, tr 57 120
VGS = 10 Vdc
Vdc,
TurnOff Delay Time RG = 9.1 )) td(off) 118 240
Fall Time tf 70 140
Gate Charge QT 100 120 nC
(See Figure 8)
(VDS = 400 Vdc,
Vd ID = 10 Adc,
Ad Q1 18.4
VGS = 10 Vdc)
Q2 33
Q3 36.7

SOURCEDRAIN DIODE CHARACTERISTICS

Forward OnVoltage (1) VSD Vdc
(IS = 10 Adc, VGS = 0 Vdc)
0.885 1.1
(IS = 10 Adc, VGS = 0 Vdc, TJ = 125C)
0.8
Reverse Recovery Time trr 885 ns
(See Figure 14)
((IS = 10 Adc,
Ad , VGS = 0 Vdc,
Vd , ta 220
dIS/dt = 100 A/s) tb 667
Reverse Recovery Stored Charge QRR 8.0 C

INTERNAL PACKAGE INDUCTANCE

Internal Drain Inductance LD 4.5 nH
(Measured from the drain lead 0.25 from package to center of die)

Internal Source Inductance LS 13 nH

(Measured from the source lead 0.25 from package to source bond pad)
(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.
(2) Switching characteristics are independent of operating junction temperature.

2 Motorola TMOS Power MOSFET Transistor Device Data

 MTW10N100E
TYPICAL ELECTRICAL CHARACTERISTICS

20 20
TJ = 25C VGS = 10 V VDS 10 V
18 18
6V

I D , DRAIN CURRENT (AMPS)

16
I D , DRAIN CURRENT (AMPS)

16
14 14
12 12
10 10
5V 25C
8 8
6 6
100C
4 4 TJ = 55C
2 4V 2
0 0
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6 6.0
VDS, DRAINTOSOURCE VOLTAGE (VOLTS) VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics Figure 2. Transfer Characteristics

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

2.4 1.56
TJ = 100C TJ = 25C
VGS = 10 V
2.0 1.48

1.40
1.6
1.32
1.2 25C
1.24
VGS = 10 V
0.8
1.16
55C
15 V
0.4 1.08

0 1.00
0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20
ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current Figure 4. OnResistance versus Drain Current
and Temperature and Gate Voltage

2.8 100000
RDS(on) , DRAINTOSOURCE RESISTANCE

VGS = 10 V VGS = 0 V TJ = 125C

2.4 ID = 5 A
10000
2.0
I DSS , LEAKAGE (nA)

100C
(NORMALIZED)

1.6 1000

1.2 100

0.8 25C
10
0.4

0 1
50 25 0 25 50 75 100 125 150 0 100 200 300 400 500 600 700 800 900 1000
TJ, JUNCTION TEMPERATURE (C) VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Figure 6. DrainToSource Leakage

Temperature Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data 3

 MTW10N100E
POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted The capacitance (Ciss) is read from the capacitance curve at
by recognizing that the power MOSFET is charge controlled. a voltage corresponding to the offstate condition when cal-
The lengths of various switching intervals (t) are deter- culating td(on) and is read at a voltage corresponding to the
mined by how fast the FET input capacitance can be charged onstate when calculating td(off).
by current from the generator.
The published capacitance data is difficult to use for calculat- At high switching speeds, parasitic circuit elements com-
ing rise and fall because draingate capacitance varies plicate the analysis. The inductance of the MOSFET source
greatly with applied voltage. Accordingly, gate charge data is lead, inside the package and in the circuit wiring which is
used. In most cases, a satisfactory estimate of average input common to both the drain and gate current paths, produces a
current (IG(AV)) can be made from a rudimentary analysis of voltage at the source which reduces the gate drive current.
the drive circuit so that The voltage is determined by Ldi/dt, but since di/dt is a func-
t = Q/IG(AV) tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
During the rise and fall time interval when switching a resis-
mathematics. And finally, MOSFETs have finite internal gate
tive load, VGS remains virtually constant at a level known as
resistance which effectively adds to the resistance of the
the plateau voltage, VSGP. Therefore, rise and fall times may
driving source, but the internal resistance is difficult to mea-
be approximated by the following:
sure and, consequently, is not specified.
tr = Q2 x RG/(VGG VGSP) The resistive switching time variation versus gate resis-
tf = Q2 x RG/VGSP tance (Figure 9) shows how typical switching performance is
where affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
VGG = the gate drive voltage, which varies from zero to VGG value of unity regardless of the switching speed. The circuit
RG = the gate drive resistance used to obtain the data is constructed to minimize common
and Q2 and VGSP are read from the gate charge curve. inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
During the turnon and turnoff delay times, gate current is
power electronic loads are inductive; the data in the figure is
not constant. The simplest calculation uses appropriate val-
taken with a resistive load, which approximates an optimally
ues from the capacitance curves in a standard equation for
snubbed inductive load. Power MOSFETs may be safely op-
voltage change in an RC network. The equations are:
erated into an inductive load; however, snubbing reduces
td(on) = RG Ciss In [VGG/(VGG VGSP)] switching losses.
td(off) = RG Ciss In (VGG/VGSP)

8000 10000
Ciss VDS = 0 V VGS = 0 V TJ = 25C VGS = 0 V TJ = 25C
7000 Ciss

6000
C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

1000
5000
Crss
4000 Ciss
Coss
3000
100
2000
Crss
1000 Crss
Crss
0 10
10 5 0 5 10 15 20 25 10 100 1000
VGS VDS VDS, DRAINTOSOURCE VOLTAGE (VOLTS)
GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)
Figure 7b. High Voltage Capacitance
Figure 7a. Capacitance Variation Variation

4 Motorola TMOS Power MOSFET Transistor Device Data

 MTW10N100E
14 560 1000

VGS, GATETOSOURCE VOLTAGE (VOLTS)

QT

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VDD = 500 V
12 480 ID = 10 A
VGS = 10 V
10 400 TJ = 25C
VGS

t, TIME (ns)
8 320
100
Q1 Q2
6 240 td(off)
tf
4 ID = 10 A 160
tr
TJ = 25C
2 80 td(on)
Q3 VDS
0 0 10
0 10 20 30 40 50 60 70 80 90 100 1 10 100
QG, TOTAL GATE CHARGE (nC) RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource Figure 9. Resistive Switching Time

Voltage versus Total Charge Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS

10
9 VGS = 0 V
TJ = 25C
I S , SOURCE CURRENT (AMPS)

8
7
6
5
4
3
2
1
0
0.50 0.54 0.58 0.62 0.66 0.70 0.74 0.78 0.82 0.86 0.90
VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define able operation, the stored energy from circuit inductance dis-
the maximum simultaneous draintosource voltage and sipated in the transistor while in avalanche must be less than
drain current that a transistor can handle safely when it is for- the rated limit and adjusted for operating conditions differing
ward biased. Curves are based upon maximum peak junc- from those specified. Although industry practice is to rate in
tion temperature and a case temperature (TC) of 25C. Peak terms of energy, avalanche energy capability is not a con-
repetitive pulsed power limits are determined by using the stant. The energy rating decreases nonlinearly with an in-
thermal response data in conjunction with the procedures crease of peak current in avalanche and peak junction
discussed in AN569, Transient Thermal ResistanceGeneral
temperature.
Data and Its Use.
Although many EFETs can withstand the stress of drain
Switching between the offstate and the onstate may tra-
verse any load line provided neither rated peak current (IDM) tosource avalanche at currents up to rated pulsed current
nor rated voltage (VDSS) is exceeded and the transition time (IDM), the energy rating is specified at rated continuous cur-
(tr,tf) do not exceed 10 s. In addition the total power aver- rent (ID), in accordance with industry custom. The energy rat-
aged over a complete switching cycle must not exceed ing must be derated for temperature as shown in the
(TJ(MAX) TC)/(RJC). accompanying graph (Figure 12). Maximum energy at cur-
A Power MOSFET designated EFET can be safely used rents below rated continuous ID can safely be assumed to
in switching circuits with unclamped inductive loads. For reli- equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data 5

MTW10N100E
SAFE OPERATING AREA

100 500

EAS, SINGLE PULSE DRAINTOSOURCE

VGS = 20 V ID = 10 A
SINGLE PULSE
400

AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

TC = 25C
10

10 s 300
1.0 100 s
1 ms 200
10 ms
0.1 dc
RDS(on) LIMIT 100
THERMAL LIMIT
PACKAGE LIMIT
0.01 0
0.1 1.0 10 100 1000 25 50 75 100 125 150
VDS, DRAINTOSOURCE VOLTAGE (VOLTS) TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased Figure 12. Maximum Avalanche Energy versus
Safe Operating Area Starting Junction Temperature

1.0
D = 0.5
TRANSIENT THERMAL RESISTANCE
r(t), NORMALIZED EFFECTIVE

0.2

0.1

0.1 P(pk)
RJC(t) = r(t) RJC
0.05 D CURVES APPLY FOR POWER
0.02 PULSE TRAIN SHOWN
0.01 t1 READ TIME AT t1
SINGLE PULSE t2 TJ(pk) TC = P(pk) RJC(t)
DUTY CYCLE, D = t1/t2
0.01
1.0E05 1.0E04 1.0E03 1.0E02 1.0E01 1.0E+100 1.0E+01
t, TIME (s)

Figure 13. Thermal Response

di/dt
IS
trr
ta tb
TIME

tp 0.25 IS

IS

Figure 14. Diode Reverse Recovery Waveform

6 Motorola TMOS Power MOSFET Transistor Device Data

 MTW10N100E
PACKAGE DIMENSIONS

T
Q
E
0.25 (0.010) M T B M B NOTES:
C 1. DIMENSIONING AND TOLERANCING PER ANSI
4 Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
U L
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A R A 19.7 20.3 0.776 0.799
B 15.3 15.9 0.602 0.626
C 4.7 5.3 0.185 0.209
1 2 3
D 1.0 1.4 0.039 0.055
E 1.27 REF 0.050 REF
F 2.0 2.4 0.079 0.094
Y G 5.5 BSC 0.216 BSC
P H 2.2 2.6 0.087 0.102
K J 0.4 0.8 0.016 0.031
K 14.2 14.8 0.559 0.583
L 5.5 NOM 0.217 NOM
P 3.7 4.3 0.146 0.169
V H Q 3.55 3.65 0.140 0.144
F J R 5.0 NOM 0.197 NOM
G U 5.5 BSC 0.217 BSC
D V 3.0 3.4 0.118 0.134

0.25 (0.010) M Y Q S STYLE 1:

PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN

CASE 340K01
ISSUE O

Motorola TMOS Power MOSFET Transistor Device Data 7

MTW10N100E

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals
must be validated for each customer application by customers technical experts. Motorola does not convey any license under its patent rights nor the rights of
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*MTW10N100E/D*
8 MTW10N100E/D
Motorola TMOS Power MOSFET Transistor Device Data