EXPERIMENT N0:- 09

AIM:- To Design and Simulate Ring and Johnson counters.

TOOLS USED:- Xilinx 14.7 ISE
THEORY:-
A Ring counter is a type of counter composed of a type of circular shift register. The output
of the last shift register is fed to the input of the first register.
Types of ring counter:-
(i) Straight ring counter connects the output of last shift register to the first shift
register input and circulates a single 1 or 0 around the ring.
(ii) Johnson counter connects the complement of output of last shift register to the
first shift register input and circulates a stream of ones followed by zeros around
the ring.

Circuit Diagram:

Figure 9.1 Circuit Diagram Of 4 Bit Ring Counter.

Figure 9.2 Circuit Diagram Of 4 Bit Johnson Counter.

Truth Table:

Q1 Q2 Q3 Q4
CLK
0 0 0 1

0 0 1 0

0 1 0 0

1 0 0 0

0 0 0 1

0 0 1 0

0 1 0 0

1 0 0 0

Table 9.1 Truth Table 4 Bit Ring Counter

Q1 Q2 Q3 Q4
CLK
1 0 0 0

1 1 0 0

1 1 1 0

1 1 1 1

0 1 1 1

0 0 1 1

0 0 0 1

0 0 0 0

Table 9.2
Truth Table 4 Bit Johnson Counter
Ring Counter:
module Dfflop(clk,reset,d,Q,initialState); endmodule
input clk,reset,d,initialState; module ringCounter(clk,reset,counter);
output reg Q; input clk,reset;
initial output [3:0]counter;
Q<=initialState; wire [3:0]t;
always@(posedge clk)begin Dfflop d1(clk,reset,t[3],t[0],1'd1);
if(reset) Dfflop d2(clk,reset,t[0],t[1],1'd0);
Q<=initialState; Dfflop d3(clk,reset,t[1],t[2],1'd0);
else Dfflop d4(clk,reset,t[2],t[3],1'd0);
Q<=d; assign counter=t;
end endmodule

RTL SCHEMATIC:

Figure 9.3 RTL Schematic Of Ring Counter.

TEST BENCH:
initial begin
clk = 0;
reset = 0;
#100;
reset = 1;
#100;
reset = 0;
#100;
end
always begin
#100 clk<=~clk;
end
always begin
#4000 reset<=~clk;
end

SIMULATION WAVEFORM:

Figure 9.4 Simulation Waveform Of Ring Counter.

JOHNSON COUNTER: end

module Dflipflop(clk,reset,d,Q); endmodule

input clk,reset,d; module johnsonCounter(clk,reset,counter);

output reg Q; input clk,reset;

initial output [3:0]counter;

Q<=0; wire [3:0]t;

always@(posedge clk)begin Dflipflop d1(clk,reset,~t[3],t[0]);

if(reset) Dflipflop d2(clk,reset,t[0],t[1]);

Q<=0; Dflipflop d3(clk,reset,t[1],t[2]);

else Dflipflop d4(clk,reset,t[2],t[3]);

Q<=d; assign counter=t;

endmodule

RTL SCHEMATIC:

Figure 9.5 RTL Schematic Of Johnson Counter.

TEST BENCH:
initial begin
clk = 0;
reset = 0;
#100;
reset = 1;
#100;
reset = 0;
#100;
end
always begin
#100 clk<=~clk;
end
always begin
#2100 reset<=~reset;
end

SIMULATION WAVEFORM:

Figure 9.6 Simulation Waveform Of Johnson Counter.

RESULT: Ring and Johnson counters have been implemented using D Flip Flop module
and output waveform has been observed.
 EXPERIMENT NO: 10
AIM:-Design and simulation of UP, DOWN, UP/DOWN counter.
TOOLS:- Xilinx ISE Design Software.

THEORY:- In a binary or BCD UP counter, the count increases by one for each external
clock pulse from some preset value. In a binary or BCD DOWN counter, the count decreases
by one for each external clock pulse from some preset value. Up counter and down counter
is combined together to obtain an UP/DOWN counter. A mode control (M) input is also
provided to select either up or down mode. A combinational circuit is required to be
designed and used between each pair of flip-flop in order to achieve the up/down operation.

Circuit Diagram:

Figure 10.1 Circuit Diagram Of UP Counter.

Figure 10.2 Circuit Diagram Of DOWN Counter.

 Figure 10.3 Circuit Diagram Of UP- DOWN Counter.

Truth Table:

CLK Q2 Q1 Q0

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

Figure 10.1 Table For UP Counter

CLK Q2 Q1 Q0

1 1 1

1 1 0

1 0 1

1 0 0

0 1 1

0 1 0

0 0 1

0 0 0

Figure 10.2 Table Of DOWN Counter.

 CLK Control Q2 Q1 Q0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
1 0 1 0
1 0 0 1
1 0 0 0
1 1 1 1

Figure 10.3 Table For UP-DOWN Counter.

UP COUNTER:
VERILOG CODE:
module tflipflop(clk,reset,t,Q); endmodule

input clk,reset,t; module upCounter(clk,reset,counter);

output reg Q; input clk,reset;

initial output [3:0]counter;

Q<=0; wire [3:0]t;

always@(posedge clk)begin tflipflop d1(clk,reset,1'd1,t[0]);

if(reset) tflipflop d2(~t[0],reset,1'd1,t[1]);

Q<=0; tflipflop d3(~t[1],reset,1'd1,t[2]);

else if(t==1) tflipflop d4(~t[2],reset,1'd1,t[3]);

Q<=~Q; assign counter=t;

end endmodule
RTL SCHEMATIC:

Figure 10.4 RTL Schematic of Up Counter.

TEST BENCH:
initial begin
clk = 0;
reset = 1;
#100;
reset = 0;
end
always begin
#100 clk<=~clk;
end

SIMULATION WAVEFORM:
 Figure 10.5 Simulation Waveform Of Up Counter.

DOWN COUNTER:
VERILOG CODE:
module tfliflop(clk,reset,t,Q); endmodule
input clk,reset,t; module downCounter(clk,reset,count);
output reg Q; input clk,reset;
initial output [3:0]count;
Q<=1; wire [3:0]t;
always@(posedge clk)begin tflipflop d1(clk,reset,1'd1,t[0]);
if(reset) tflipflop d2(t[0],reset,1'd1,t[1]);
Q<=0; tflipflop d3(t[1],reset,1'd1,t[2]);
else if(t==1) tflipflop d4(t[2],reset,1'd1,t[3]);
Q<=~Q; assign count=t;
end endmodule

RTL SCHEMATIC:

Figure 10.6 RTL Schematic of Down Counter.

TEST BENCH:
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
#100;
reset = 1;
#100;
reset = 0;
end
always begin
#100 clk<=~clk;
end

SIMULATION WAVEFORM:

Figure 10.7 Simulation Waveform Of Down Counter.

UP-DOWN COUNTER:
module tfflop(clk,reset,t,Q); output [3:0]count;

input clk,reset,t; wire [3:0]t;

output reg Q; wire [2:0]t1;
initial
tfflop d1(clk,reset,1'd1,t[0]);
Q<=0;
xor x1(t1[0],control,t[0]);
always@(posedge clk)begin
tfflop d2(t1[0],reset,1'd1,t[1]);
if(reset)
xor x2(t1[1],control,t[1]);
Q<=0;
else if(t==1) tfflop d3(t1[1],reset,1'd1,t[2]);

Q<=~Q; xor x3(t1[2],control,t[2]);

end tfflop d4(t1[2],reset,1'd1,t[3]);
endmodule assign count=t;
module upDown(clk,reset,control,count);
endmodule
input clk,reset,control;

RTL SCHEMATIC:
 Figure 10.8 RTL Schematic of Up-Down Counter.
TEST BENCH:
initial begin
clk = 0;
control = 0;
reset = 1;
#100;
reset = 0;
end
always
#100clk<=~clk;
always
#3000 control<=~control;

SIMULATION WAVEFORM:
 Figure 10.9 Simulation Waveform Of Up-Down Counter.

RESULT: Up, Down and Up-Down counters have been designed and implemented using T
Flip Flop module and simulation waveforms were observed.

EXPERIMENT NO 11
AIM: Design and simulation of 4 bit universal shift register.
TOOLS: Xilinx ISE design software
THEORY:
Universal Shift Register is a register which can be configured to load and/or retrieve the data
in any mode (either serial or parallel) by shifting it either towards right or towards left. In
other words, a combined design of unidirectional (either right- or left-shift of data bits as in
case of SISO, SIPO, PISO, PIPO) and bidirectional shift register along with parallel load
provision is referred to as universal shift register. A shift-right control to enable the shift-right
operation and the serial input and output lines associated with the shift-right. A shift-left
control to enable the shift-left operation and the serial input and output lines associated with
the shift-left.
A parallel-load control to enable a parallel transfer and the n input lines associated with the
parallel transfer.

CIRCUIT DIAGRAM:
 Fig 12.1 4 bit universal shift register

VERILOG CODE:
module muxx m2(q2,p2,q3,q1,s1,s0,w2);
universe(s1,s0,si,p3,p2,p1,p0,clk,rst,q3,q2,
dff d2(w2,clk,rst,q2);
q1,q0);
muxx m3(q1,p1,q2,q0,s1,s0,w3);
input s1,s0;
dff d3(w3,clk,rst,q1);
input si;
muxx m4(q0,p0,q1,q3,s1,s0,w4);
input p3,p2,p1,p0;
dff d4(w4,clk,rst,q0);
input clk, rst,
endmodule
output q3,q2,q1,q0
module dff(input d,input clk1,input
wire w1,w2,w3,w4;
rst1,output reg q);
muxx m1(q3,p3,si,q2,s1,s0,w1);
initial q=1'b0;
dff d1(w1,clk,rst,q3);
always @(posedge clk1,posedge rst1) end
begin endmodule
if(rst1==1) module muxx (input
i0,i1,i2,i3,s1,s0,output y);
begin q=1'b0; end
assign y=((~s1&~s0&i0)|(~s1&s0&i1)|
else
(s1&~s0&i2)|(s1&s0&i3));
begin q=d; end
endmodule
RTL Schematic:

=
Fig 12.2 RTL of 4 bit universal shift register

TEST BENCH:
initial
begin
s1 = 0; s0 = 1; si = 0; p3 = 1; p2 = 0; p1 = 1; p0 = 0; rst = 0;
#500;
s1 = 0; s0 = 1; si = 0; p3 = 0; p2 = 1; p1 = 1; p0 = 0; rst = 0;
#500;
s1 = 1; s0 = 0; si = 1; p3 = 1; p2 = 0; p1 = 1; p0 = 0; rst = 0;
#1500;
s1 = 1; s0 = 0; si = 0; p3 = 1; p2 = 0; p1 = 1; p0 = 0; rst = 0;
#600;
s1 = 1; s0 = 1; si = 0; p3 = 1; p2 = 0; p1 = 1; p0 = 0; rst = 0;
#1500;
end
initial
clk=1'b0;
always
#100 clk=~clk;
endmodule

OUTPUT WAVEFORM:

Fig 12.3 Output waveform of 4 bit universal shift register

RESULT: 4 bit universal shift register is successfully designed and simulated.