The 2010 International Power Electronics Conference

Theoretical Analysis and Control of the Modular Multilevel Cascade Converter

Based on Double-Star Chopper-Cells (MMCC-DSCC)
Makoto Hagiwara, Member, IEEE, Ryo Maeda, and Hirofumi Akagi, Fellow, IEEE
Department of Electrical and Electronic Engineering
Tokyo Institute of Technology, Tokyo, Japan
E-mail: akagi@ee.titech.ac.jp

Abstract This paper presents the modular multilevel cascade
converter based on double-star chopper-cells (MMCC-DSCC),
which is intended for installation on the 6.6-kV Japanese indus-
trial and utility distribution systems without using line-frequency
transformers. The converter is characterized by an arm structure
based on the module consisting of cascade connection of multiple
bidirectional PWM chopper-cells and floating dc capacitors per
arm. This arm structure requires voltage-balancing control for
all the chopper-cells. However, the voltage control combining
averaging- with individual-balancing controls imposes certain
limitations on operating conditions. This paper proposes an arm-
balancing control to achieve voltage balancing in all the operating
conditions. The validity of the arm-balancing control as well as
the theory developed in this paper is confirmed by computer
simulation.
Keywords Modular multilevel cascade converter, grid-
connected converter, voltage balancing control.
I. I NTRODUCTION
The family of modular multilevel cascade converters (MM-
CCs) is expected as the next-generation power converters
suitable for high- or medium-voltage application without using
line-frequency transformers. There are four power converters
in the MMCC family, which have the common concept of
modular arm structure and cascade connection but have
slight differences in circuit configuration [1]. However, this
paper confines a discussion on on the modular multilevel
cascade converter based on double-star chopper-cells (DSCC)
[2]-[10]. In 1981, Alesina and Venturini proposed the modular
arm structure consisting of a cascaded stack of multiple bidi-
rectional chopper-cells [2]. Marquardt and Lesnicar presented
a basic concept of the DSCC using the modular arm structure
in [3], along with the operating principle and performance
under an ideal condition. Siemens has a plan of putting it
into practical use with the trade name HVDC-plus. It was
reported in [9] that the system configuration of the HVDC-
plus has a power rating of 400 MVA, a dc-link voltage of
200 kV, and a stack of 200 cascaded chopper-cells per
leg. Because of easy assembling and flexibility in converter
design, it is especially suitable as grid-connected converters
for medium-voltage applications such as motor drives [11][12],
STATCOMs, back-to-back systems, etc.
The grid-connected converter acts as a rectifier, an inverter,
an inductor, a capacitor, and their combination in accordance
with the phase difference between the ac voltage of the
converter and the supply current. This implies that the DSCC
is required to achieve rigid voltage control of the floating dc
capacitor of each chopper-cell in all the operating conditions
of 0 2. The authors of this paper have proposed
a voltage control that combines averaging and individual-
balancing controls [10]. The averaging control is based on
adjusting the circulating current from the dc link to the
converter leg, while the individual-balancing control relies
on the load (supply) current. The validity and effectiveness
of the voltage control has been confirmed by experimental
results obtained by using a 400-V, 15-kW downscaled model.
However, no paper has been published on theoretical analysis
of the DSCC to utility applications.
The aim of this paper is to accomplish the stable voltage
control of the DSCC in all the operating conditions. Theoret-
ical analysis focuses on the stability of the converter. This
paper proposes the arm-balancing control characterized by
mitigating the average voltage difference between positive and
negative arms. Using the arm-balancing control together with
the averaging and individual-balancing controls enables the
DSCC to realize the stable voltage control in all the operating
conditions. The validity of the control as well as the theory
developed in this paper is confirmed by computer simulation
using the PSCAD/EMTDC software package [13].
II. C IRCUIT C ONFIGURATION AND C ONTROL M ETHOD OF
THE DSCC
A. Circuit Configuration
Fig. 1(a) shows the detailed circuit configuration of the
DSCC for utility applications. The ac side of the converter
is connected to a 6.6-kV, three-phase voltage supply (i.e.
the Japanese utility power distribution system) via ac-link
inductors, while the dc side is connected to a 12-kV dc
voltage supply via a common dc link. Here, p and q represent
instantaneous active and reactive powers [14]. The DSCC acts
as a rectifier when p > 0, an inverter when p < 0, an inductor
when q > 0, and a capacitor when q < 0.
Each leg of the converter consists of a stack of 16 bidirec-
tional chopper-cells shown in Fig. 1(b), and a coupled inductor
in Fig. 1(c). The chopper-cell uses a dc capacitor and two
IGBTs that form a bidirectional chopper. Fig. 1(a) produces
17-level (33-level in line-to-line) PWM waveforms since the
number of chopper-cell per leg is 16. The terminals of the
coupled inductor, a and b are connected to the positive
and negative arms, and the terminal c is directly connected
to the ac-link inductor.
In Fig. 1(a), iP u and iN u are the positive and negative arm
currents, iu is the supply current, and iZu is the circulating

978-1-4244-5393-1/10/$26.00 2010 IEEE 2029

 The 2010 International Power Electronics Conference
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u-phase v-phase w-phase voltage major loop current minor loop

cell 1u cell 1v cell 1w vC iZ
vA
vC1u K1+ K

s
2 K3

vC iP 1 iZ

cell 8u cell 8v cell 8w 2

p iN
vSu q iu iP u (a)
L vuv iN u
vSv Vdc
vC vBIj
iv K4 1
vSw iw

vCj i +1 : j = 9 16
6.6 kV
vC9u cell 9u cell 9v cell 9w (j : 1 16) 1 : j = 1 8
1 MW (b)
50 Hz

vCP vBA
cell 16u cell 16v cell 16w K5 1

vCN i +1 : given by (19)
1 : given by (21)
(a) (c)

a Fig. 2. Block diagram of dc-capacitor voltage control. (a) Averaging control.

(b) Individual-balancing control. (c) Arm-balancing control.
lac
C c lab
to follow its command vC , where vC is given by
lbc
vju
16
1
b vC = vCj . (4)
16 j=1
(b) (c)
Note that the current minor loop adjusts the circulating current
Fig. 1. Circuit configuration of the DSCC for utility applications. (a) Power from the dc link to the converter leg, and produces the voltage
circuit. (b) Chopper-cell. (c) Coupled inductor.
command vA .
Fig. 2(b) shows the block diagram of the individual-
current along the u-phase dc loop [10]. The following equa- balancing control. It forms an active power between the
tions exist among the four currents: voltage at the low-voltage side of each chopper-cell, vj and
the corresponding arm current. The voltage command obtained
iu
from the individual-balancing control, vBIj for j = 1 8 is
iP u = + iZu (1)
2 represented as:
iu
+ iZu
iN u = (2)
2

vBIj = K4 (vC

vCj )i, (5)
1
iZu = (iP u + iN u ). (3)
and vBIj for j = 9 16 as:
2
The coupled inductor presents the inductance lab only to the
vBIj = K4 (vC

vCj )i. (6)
circulating current iZu , and no inductance to the supply current

iu [10]. Note that vBIj contains a line-frequency component of 50 Hz
that forms an active power with a line-frequency component
of iP or iN .
B. Control Method
Fig. 2(c) shows the block diagram of the arm-balancing
The following pays attention to one leg in Fig. 1(a) because control proposed in this paper. It has a function to mitigating
the operating principle is identical among the three legs. Fig. 2 the voltage difference between vCP and vCN zero, where they
shows the block diagram of the dc-capacitor voltage control1 . are given by:
Voltage control of the 16 floating dc capacitors per leg in
8
Fig. 1(a) can be divided into 1
vCP = vCj (7)
averaging control, 8 j=1
individual-balancing control, and 16
arm-balancing control. 1
vCN = vCj . (8)
Fig. 2(a) shows the block diagram of the averaging control. 8 j=9
The voltage major loop forces the u-phase average voltage vC
Hence, vCP and vCN represent the average voltages of the
1 The subscript u is omitted from the following analysis. positive and negative arms. The line-to-neutral voltage of the

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TABLE I
C IRCUIT PARAMETERS USED FOR SIMULATION . vC1 cell 1 v1
Capacity 1 MVA iP
Line-to-line rms voltage V 6.6 kV cell 8 vC1 C
Rated rms current I 87 A v1
Frequency f 50 Hz iP
iZ
DC-link voltage Vdc 12.0 kV i
lab Vdc
Coupled inductor lab 4.2 mH (3%) v (b)
DC-capacitor voltage VC 1.5 kV (= 12.0 kV/8) iN
DC capacitance C 0.8 mF
Unit capacitance constant [15] H 43 ms vC9 cell 9 v9 iN
Carrier frequency fC 1350 Hz vC9 C
AC-link inductance L 7 mH (5.0%) cell 16
v9
Values in () are on a 1-MW, 6.6-kV, and 50-Hz base.

(a) (c)
TABLE II
C ONTROL GAINS USED FOR SIMULATION . Fig. 3. Circuit configuration used for theoretical analysis. (a) one leg of the
K1 K2 K3 K4 K5 DSCC shown in Fig. 1. (b) chopper-cell 1. (c) chopper-cell 9.
0.3 A/V 3 A/(Vs) 1 V/A 0.5 1/kA 0.5 1/kA

C. Simulation Conditions
converter, v and the supply current i are given by
The simulation using the PSCAD/EMTDC software pack-
2 age [13] is carried out, where the circuit parameters and the
v= V sin t
control gains are summarized in Tables I and II. The dc-link
3
i = 2I sin (t ), (9) voltage and the carrier frequency are set as Vdc = 12.0 kV
and fC = 1350 Hz respectively. The dc-voltage command of
where is the phase difference. When is given by (19) to each chopper-cell is set as VC = 1.5 kV (= 12.0 kV/8). This

be discussed below, vBA is given by allows one to use 3.3-kV IGBTs that are currently available
from the market.

vBA = K5 (
vCP vCN )i. (10) The following conditions are considered to confirm consis-
tency between theory and simulation: The controller has no
Here, vBA is the voltage command produced by the arm-
time delay. Each chopper-cell uses ideal IGBTs with no dead
balancing control. When is given by (21), then vBA is given
time.
by

vBA = K5 (
vCP vCN )i. (11)

Similarly to the individual-balancing control, vBA contains a III. S TABILITY A NALYSIS OF THE DSCC
line-frequency component of 50 Hz, which forms an active
power with a line-frequency component of iP or iN .
Finally, the voltage command of positive-arm chopper-cells, A. Without the Arm-Balancing Control
vj for j = 1 8 is given by
The stability analysis without the arm-balancing control (i.e.
v Vdc
vj = vA

+ vBIj

+ vBA

+ , (12)

vBA = 0) is presented. Fig. 3 shows a circuit configuration
8 16 used for the analysis, which corresponds to the one leg of
and vj for j = 9 16 is given by the converter in Fig. 1(a). Attention is paid to the circulating
current iZ because it determines the stability of the converter,
v Vdc acting as a state variable.
vj = vA

+ vBIj

+ vBA

+ + . (13)
8 16 The following relationship comes into existence with respect

Here, v is the line-to-neutral voltage command of the con- to iZ (See the appendix):
verter. The last term of the right-hand side in (12) and (13),
Vdc /16 corresponds to a feedforward control of the dc-link
d5 1 d4 1 cos d3
voltage Vdc . It should be noted that v is determined by the iZ + iZ + + 2
2 iZ
decoupling current control of the supply current i. The voltage dt5 TI dt4 TI TV 1 TB dt3
2 2
command vj is normalized by each dc-capacitor voltage vCj . 1 sin d
+ + iZ
Then, it is compared with a triangular waveform having a TI TI TV 1 TV 2 TB2 dt2
maximal value of unity and a minimal value of zero with a 2 d 2
carrier frequency of fC . + iZ + iZ = 0, (14)
TI TV 1 dt TI TV 1 TV 2

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= /2
where TI , TV 1 , TV 2 , and TB are given by (inductor operation)
lab
TI =
16K3
(10) is applied
2C
TV 1 = =0
K1 (rectifier operation)
K1 =
TV 2 = (inverter operation)
K2
1 given by (20) (11) is applied
3CVC lab 2
TB = . (15)
2K4 V I
Here, TI is the time constant of the current minor loop, TV 1 = 3/2
(capacitor operation) border line
and TV 2 are those of the voltage major loop, and TB is that of
the balancing control. Substituting the circuit parameters and Fig. 4. Relationship between (10), (11), and .
the control gains into (15) yields TI = 0.26 ms, TV 1 = 5.3 ms,
TV 2 = 100 ms, and TB = 3.9 ms.
The so-called Routh-Hurwitz stability criterion is applied Hence, iZ is stable as long as satisfies (19), while it is
to (14), in which each coefficient is expressed as unstable when

a0 = 1 . (21)
1
a1 =
TI
B. With the Arm-Balancing Control
1 cos
a2 = 2 + 2 The arm-balancing control proposed in this paper makes the
TI TV 1 TB
2 1 sin DSCC stable in all the operating conditions of 0 < < 2.
a3 = + Let us focus on the operating condition in which is given by
TI TI TV 1 TV 2 TB2
2
(19). Although the arm-balancing control is unnecessary in this
region because iZ is stable without it, (10) can be applied to
a4 =
TI TV 1 the DSCC. In this case, the only difference with or without the
2 arm-balancing control is the control gain that is equivalently
a5 = . (16)
TI TV 1 TV 2 changed from K4 to K4 + 2K5 in (15). On the other hand, iZ
The following related elements are calculated as is unstable if (11) is applied to the converter because the stable
condition changes from (19) to (21) as referred to hereinafter.
b1 = (a1 a2 a0 a3 )/a1 If is given by (21), then the arm-balancing control of (11)

1 1 1 cos TI sin should be applied, where (14) is changed as follows:
= 2 +
TV 1 TI TV 2 TB TB2
d5 1 d4 1 cos d3
2 1 1 i Z + i Z + 2
+ + iZ
b2 = (a1 a4 a0 a5 )/a1 = dt5 TI dt4 TI TV 1 TB2 dt3
TV 1 TI TV 2 2
1 sin d2
c1 = (b1 a3 a1 b2 )/b1 + + + iZ
TI TI TV 1 TV 2 TB2 dt2
c2 = a5
2 d 2
d1 = (b2 c1 b1 c2 )/c1 + iZ + iZ = 0. (22)
TI TV 1 dt TI TV 1 TV 2
e1 = a5 . (17)
Here, TI , TV 1 , and TV 2 are the same as those in (15), while
The DSCC is stable when the coefficients in (16) as well as TB is changed to
b1 , c1 , d1 in (17) are all positive. The following important 12
assumption is introduced for deriving (19)2 : 3CVC lab
TB = . (23)
2(2K5 K4 )V I
TI TV 1 TB 1/ TV 2 . (18)
The following relationship should come into existence in (23):
If (18) is valid, then a0 to b2 are positive in all the operating
conditions. Substituting the relations of c1 > 0 and d1 > 0 K4
K5 > . (24)
into (17) with the help of (18) produces 2
Applying the Routh-Hurwitz stability criterion into (22) con-
< < 2 , (19)
cludes that iZ is stable when is given by (21) while unstable
where is given by when given by (19). This means the stable condition changes
from (19) to (21) if (11) is applied. On the other hand, iZ is
TV 1
= tan 1
. (20) unstable if (10) is applied because the stable condition does
1 2 TI TV 1 not change from (19).
2 This is one example used for the derivation. Finally, the following conclusions are obtained.

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[kV] vuv
If is given by (19), iZ is stable when (10) or no arm- 12
vuv
balancing control is applied, and unstable when (11) is 0
vvw
applied.
vvw
If is given by (21), iZ is stable when (11) is applied, -12 iu
[A] 150 20 ms
and unstable when (10) is applied, where the relation of
iu
(24) should be satisfied. 0
iv
Fig. 4 shows the relationship between (10), (11), and . iw -150 iu
Substituting the circuit parameters and the control gains into [A] 150 iN u
(20) yields /3. Fig. 4 indicates that (10) should be iu
applied when the converter acts as an inverter (i.e. = ) or iP u 0
a capacitor (i.e. = 3/2), and (11) should be applied when iN u -150 iP u
it acts as a rectifier (i.e. = 0) or an inductor (i.e. = /2). [A] 0

IV. S IMULAION R ESULTS
A. Operating Performance under a Steady-State Condition
Fig. 5 shows simulated waveforms when the DSCC acts as
a rectifier (i.e. p = 1 MW, q = 0 MVA, and = 0). The
line-to-line voltage vuv is a 29-level PWM waveform with a
voltage step of 0.75 kV (=1.5kV /2). As a consequence, vuv
contains much less harmonic voltage as well as much less
common-mode voltage than a traditional two-level voltage-
source PWM inverter, thus resulting in significantly reducing
EMI emissions. Since the carrier frequency of each chopper-
cell is 1350 Hz, the equivalent switching frequency of the
converter is 22 kHz ( 1350 Hz 16).
The waveform of iu is purely sinusoidal with a fundamental
component of 50 Hz. The arm currents iP u and iN u contain
the fundamental component of 50 Hz, the 11 kHz(= 1350 Hz
8) switching-ripple component, and the second-order (100 Hz)
harmonic currents resulting from the balancing control. The
switching-ripple component can be mitigated sufficiently with
the coupled inductor lab having the inductance value of 3%.
No second-order harmonic current appears in iu because those
included in iP u and iN u are in phase and the same in
amplitude.
The waveform of iZ consists of the dominant dc component
1MW
of 28 A(= 312 kV ) together with the switching-ripple com-
ponent and the second-order component. The switching-ripple
component can be suppressed by increasing the inductance
value of lab .
The dc-capacitor voltage vC1u contains both dc and ac
components as shown in Fig. 5, in which the voltage control
regulates the dc component at 1.5 kV. The ac components
consist of a dominant fundamental (50 Hz) component, and a
second-order (100 Hz) harmonic component. The amplitude
of the ac components is proportional to the rms value of
the supply current I, and inversely proportional to the line
frequency f as well as the dc capacitance C [11].
B. Operating Performance under a Transient-State Condition
Fig. 6(a) shows simulated waveforms when the converter
acts as a rectifier (i.e. p = 1 MW, q = 0 MVA, and = 0), in
which the arm-balancing control given by (11) was disabled at
t = t1 . The voltage difference between vC1u and vC9u expands
after t = t1 because iZ is unstable without (11) when is
given by (21). Fig. 6(b) shows simulated waveforms when the
iZu -25
-50
[kV] 2.0 vC9u vC1u
vC1u
1.5
vC9u
1.0
Fig. 5. Simulated waveforms of Fig. 1 at p = 1 MW, q = 0, and = 0.
converter acts as a capacitor (i.e. p = 0 MW, q = 1 MVA,
and = 3/2), in which the arm-balancing control given by
(10) was disabled at t = t1 . No expansion occurs in the voltage
difference between vC1u and vC9u after t = t1 because iZ is
stable without (10) when is given by (19).
Fig. 7(a) shows simulated waveforms when the converter
acts as the rectifier, in which the arm-balancing control was
changed from (11) to (10) at t = t2 . Fig. 7(b) shows simulated
waveforms when the converter acts as the capacitor, in which
the arm-balancing control was changed from (10) to (11) at
t = t2 . The voltage difference in both cases expands after t =
t2 , and therefore the appropriate equation should be applied in
accordance with the phase difference obtained from (19) and
(21).
Fig. 8 shows simulated waveforms when the converter acts
as the rectifier, in which the control gain of the arm-balancing
control was changed at t = t3 . The gain was K5 = K4 /2
before t = t3 , which is the boundary value coming from
(24), and then it was changed to K5 = K4 at t = t3 for
satisfying (24). An amount of the voltage difference exists
before t = t3 since K5 = K4 /2 is the boundary value. The
voltage difference converges on zero after t = t3 because K5
satisfies (24) after t = t3 .
V. C ONCLUSION
This paper has dealt with the modular multilevel cascade
converter based on double-star chopper-cells (MMCC-DSCC),
and focuses on its application to grid-connected converters.
Theoretical analysis developed in this paper has revealed that
the voltage control combining averaging- with individual-
balancing controls imposes certain limitations on operating
conditions. The arm-balancing control proposed in this paper
enables the converter to achieve the voltage control in all the
operating condition. The validity of the control as well as

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t = t1 t = t2
[kV] 2.5 K5 = 0 K5 = 0 [kV] 2.5 (11) is applied changed to (10)
(11) is applied
vC1u vC1u
1.5 1.5
vC9u vC9u
0.5 0.5
[kV] 2.5 [kV] 2.5 0.1 s
0.1 s
vC1v vC1v
1.5 1.5
vC9v vC9v
0.5 0.5
[kV] 2.5 [kV] 2.5
vC1w vC1w
1.5 1.5
vC9w vC9w
0.5 0.5
[A] 150 [A] 150

iZu 0 iZu 0

-150 -150
(a) (a)

t = t1 t = t2
[kV] 2.5 K5 = 0 K5 = 0 [kV] 2.5 (10) is applied changed to (11)
(10) is applied
vC1u vC1u
1.5 1.5
vC9u vC9u
0.5 0.5
[kV] 2.5 [kV] 2.5
0.1 s 0.1 s
vC1v vC1v
1.5 1.5
vC9v vC9v
0.5 0.5
[kV] 2.5 [kV] 2.5
vC1w vC1w
1.5 1.5
vC9w vC9w
0.5 0.5
[A] 150 [A] 150
iZu 0 iZu 0

-150 -150
(b) (b)

Fig. 6. Simulated waveforms where K5 is changed to zero at t = t1 . (a) Fig. 7. Simulated waveforms where arm-balancing control is changed at t =
p = 1 MW, q = 0 MVA, and = 0. (b) p = 0 MW, q = 1 MVA, and t2 . (a) p = 1 MW, q = 0 MVA and = 0. (b) p = 0 MW, q = 1 MVA,
= 3/2. and = 3/2.

the theory developed in this paper is confirmed by computer
simulation using the PSCAD/EMTDC software package.
R EFERENCES
[1] H. Akagi, Classification, Terminology, and Application of the Modular
Multilevel Cascade Converter (MMCC), in Conf. Rec. IPEC-Sapporo
2010.
[2] A. Alesina, and M. Venturini, Solid-state power conversion: A Fourier
analysis approach to generalized transformer synthesis, IEEE Trans.
Circ. Sys., vol. cas-28, no.4, pp.319-330, April 1981.
[3] R. Marquardt, and A. Lesnicar, A new modular voltage source inverter
topology, in Conf. Rec. EPE 2003, CD-ROM.
[4] M. Glinka, and R. Marquardt, A new single-phase ac/ac-multilevel
converter for traction vehicles operating on ac line voltage, in Conf.
Rec. EPE 2003, CD-ROM.
[5] M. Glinka, Prototype of multiphase modular-multilevel-converter with
2 MW power rating and 17-level-output-voltage, in Conf. Rec. IEEE-
PESC 2004, pp. 2572-2576.
[6] M. Glinka, and R. Marquardt, A new ac/ac multilevel converter family,
IEEE Trans. Ind. Electron., vol. 52, no. 3, pp. 662-669, June 2005.
[7] http://www.modernpowersystems.com
[8] S. Allebrod, R. Hamerski, and R. Marquardt, New transformerless,
scalable modular multilevel converters for HVDC-transmission, in
Conf. Rec. IEEE-PESC 2008, pp. 174-179.
[9] B. Gemmell, J. Dorn, D. Retzmann, and D. Soerangr, Prospects of
multilevel VSC technologies for power transmission, in Conf. Rec.
IEEE-TDCE 2008, pp. 1-16.
[10] M. Hagiwara, and H. Akagi, Control and experiment of pulsewidth-
modulated modular multilevel converters, IEEE Trans. Power Electron.,
vol. 24, no. 7, pp. 1737-1746, July 2009.
[11] H. Akagi, Medium-voltage power converters and motor drives, in
Conf. Rec. European Center for Power Electronics, Zurich, March 2009,
CD-ROM.
[12] M. Hagiwara, K. Nishimura, and H. Akagi, A Modular Multilevel PWM
Inverter for Medium-Voltage Motor Drives, in Conf. Rec. IEEE-ECCE
2009, pp. 2557-2564. (to be published in IEEE Trans. Power Electron.
in 2010)
[13] http://www.hvdc.ca/
[14] H. Akagi, Y. Kanazawa, and A. Nabae, Instantaneous Reactive Power
Compensators comprising Switching Devices without Energy Storage
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May/Jun 1984.
[15] H. Fujita, S. Tominaga, and H. Akagi, Analysis and Design of a DC
Voltage-Controlled Static Var Compensator using Quad-Series Voltage-
Source Inverters, IEEE Trans. Ind. Appl., vol. 32, no. 4, pp.970977,

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t = t3
[kV] 2.0 K5 = K4 /2 K5 = K4 Equations (31) and (32) produce
vC1u
dvC v i Vdc iZ
vC9u CVC = + (33)
dt 16 16
1.0 d
v iZ Vdc i
[kV] 2.0 CVC ( vCP vCN ) = . (34)
0.1 s
vC1v dt 4 16
vC9v In Fig. 3(a), iZ is determined by the following circuit
1.0 equation:
[kV] 2.0 16
diZ
vC1w Vdc = vj + lab . (35)
vC9w j=1
dt
1.0
[A]
Substituting (12) and (13) into (35) yields
0 16

iZu diZ
16vA + vBIj + lab = 0, (36)
dt
-100 j=1

where vA and vBIj are voltages obtained from the averaging

Fig. 8. Simulated waveforms at p = 1 MW, q = 0 MVA, and = 0 where and the individual-balancing control (vA = vA
, vBIj =
5
K5 is changed from K5 = K4 /2 to K5 = K4 at t = t3 . vBIj ) . From Fig. 2(a), vA is represented as
v A = vA

= K3 (iZ iZ ) = K3 iZ

Jul./Aug. 1996.
K1 K3 (vC
vC ) K2 K3 (vC
vC )dt. (37)
A PPENDIX
The following equation is obtained from (5) and (6):
A. Derivation of Equation (14)
16
8
16

The following relationships with respect to instantaneous vBIj = vBIj + vBIj
active powers exist in Figs. 3(b) and (c) as: j=1 j=1 j=9
dvC1 dvC1 = 8K4 (
vCP vCN )i. (38)
v1 iP = vC1 C CVC (25)
dt dt
dvC9 dvC9 Equations (33) to (38) produce the differential equation re-
v9 iN = vC9 C CVC , (26) garding iZ as
dt dt
where VC is the dc component of 1.5 kV which is contained in d 2K4 i K4 Vdc i
lab iZ v iZ dt idt
vC1 and vC9 . The reasonable approximation of vC1 = vC9 = dt CVC 2CVC
VC is applied3 . The first and second terms of the right hand in
(12) and (13) are negligible compared to the fourth and fifth +16K3 iZ 16K1 K3 vC
16K2 K3 vC
dt


terms (i.e. vA = vBI1

= vBI9

0)4 . Therefore, v1 and v9 are K1 K 3 K2 K3
approximated as: + v idt + v idtdt
CVC CV C
v Vdc K1 K3 Vdc K2 K3 Vdc
v1 = v1 + (27) + iZ dt + iZ dtdt
8 16 CVC CVC

v9 = v9 + +
v Vdc
. (28) = 0. (39)
8 16
In (39), the terms only related to iZ contribute to the stability.
Substituting (1), (2), (27), and (28) into (25) and (26) yields
Extracting the terms related to iZ from (39) yields

dvC1 v i v iZ Vdc i Vdc iZ d 2K4 i
CVC = + (29) lab iZ v iZ dt + 16K3 iZ
dt 16 8 32 16 dt CV C
dvC9 v i v iZ Vdc i Vdc iZ K1 K3 Vdc K2 K3 Vdc
CVC = + + + . (30) + iZ dt + iZ dtdt
dt 16 8 32 16 CVC CVC
Since the arm current is common in the positive chopper-cells, = 0. (40)
(29) is also valid in those numbered 2 to 8. In the similar way,
The following assumptions are introduced to achieve the
(30) is valid in those numbered 10 to 16. Hence, (29) and (30)
linearization of (40):
can be changed into
i is sinusoidal only including a fundamental component
d
vCP v i v iZ Vdc i Vdc iZ d2
of 50 Hz. Hence, the relation of dt2 i = i comes into
2
CVC = + (31)
dt 16 8 32 16 existence.
d
vCN v i v iZ Vdc i Vdc iZ di
CVC = + + + . (32) Although v i and v dt contain both dc anc ac compo-
dt 16 8 32 16 nents, only the dc components of (v i)dc and (v dt
di
)dc
3 The ac components are as small as 10% of 1.5 kV from Fig. 5.
4 The , v , and v are as small as 1% of 0.75 kV(=12kV /16) 5 The approximation of v = v and v
values of vA B1 B9 A A BIj = vBIj are valid because the
under the steady state condition. time delay coming from PWM control is negligible.

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 The 2010 International Power Electronics Conference
8

are considered because the ac component does not affect

the stability.
Finally, the following equation is obtained:
d5 d4
lab 5 iZ + 16K3 4 iZ
dt dt
K 1 3 Vdc
K 2K4 (v i)dc d3
+ lab +
2
iZ
CVC CVC dt3

K2 K3 Vdc 2K4 (v dt
di
)dc d2
+ 16 2 K3 + iZ
CVC CVC dt2
2 K1 K3 Vdc d 2 K2 K3 Vdc
+ iZ + iZ = 0. (41)
CVC dt CVC
(v i)dc and (v dt
di
)dc are calculated from (9) as follows:
V I cos
(v i)dc =
3
di V I sin
v = . (42)
dt dc 3
Substituting (42) into (41) yields (14), in which the relation
of Vdc = 8VC is utilized.

2036