Microelectronic Engineering 80 (2005) 378385

www.elsevier.com/locate/mee

Multiple gate devices:

advantages and challenges
T. Poiroux, M. Vinet, O. Faynot, J. Widiez1,
J. Lolivier, T. Ernst, B. Previtali, S. Deleonibus
CEA-DRT-LETI, CEA Grenoble, 17 rue des Martyrs, 38054 Grenoble, France
1
also with STMicroelectronics, 850 rue Jean Monnet, 38926 Crolles, France
Tel: 33-438782398 email: thierry.poiroux@cea.fr

Abstract

As device scaling is entering the sub-25nm range, multiple gate device architectures are needed to fulfill the ITRS
requirements, since they offer a greatly improved electrostatic control of the channel. However, practical realization of
multiple gate devices face with technological issues, mainly linked to the use of very thin films or very narrow active areas.
On the other hand, these architectures are very likely to allow the performance improvement trend down to the sub-10nm
regime and can offer new circuit design opportunities.

Keywords: Multiple gate transistors; Double-gate; FinFET; Gate-all-around; MOSFET scaling

1. Introduction dynamic performance that can be expected from

Thin Silicon-On-Insulator (SOI) and multiple
gate devices, such as planar double gate, FinFET,
Trigate, :-FET and surrounding gate transistors are
very attractive options for the 32nm technology node
and beyond. The ITRS roadmap [1] forsees that the
excellent electrostatic control of these devices will be
required for sub-25nm gate lengths, in addition to
enhanced transport properties. In this study, we first
present an overview of the proposed architectures,
discussing their advantages and also their challenges.
In a second part, we focus on the requirements for
low channel doping devices and we discuss about the
0167-9317/$ - see front matter 2005 Published by Elsevier B.V.
doi:10.1016/j.mee.2005.04.095
multiple gate transistors. Then, we present several
technological challenges associated with the use of
ultra-thin silicon films, and we finally highlight some
opportunities for circuit design with separated double
gate transistors.
2. Multiple gate architectures
From the first studies published on multi-gate
devices in the 80s [2-4], many architectures have
been proposed in which the channel is controlled by
two or more gates.
 T. Poiroux et al. / Microelectronic Engineering 80 (2005) 378385
In planar architectures, the structure can be non
self-aligned, i.e. fabricated with one photo-
lithography step for each gate, or self-aligned, using
only one lithography step to define both gates. The
non self-aligned architecture by wafer bonding is the
most straightforward approach to fabricate planar
double gate. The success of this approach depends on
the lithography capability to align very short gates
one to the other. Figure 1 shows a 10nm non self-
aligned planar double gate transistor, fabricated
thanks to the use of wafer bonding and e-beam
lithography. Notice that a quasi-perfect gate
alignment, with an accuracy of a few nanometers,
could be achieved thanks to the self-aligned
regeneration of the alignment marks after the
bonding step [5].
Salicided elevated
source/drain
TiN Front gate
Back gate
6nm thick
mono-Si channel
Fig.1 TEM cross-section of a 10nm planar bonded double
gate transistor with TiN metal gates..
Several approaches have been proposed to
fabricate self-aligned planar double gate MOSFETs.
The first one consisted in patterning a narrow silicon
active area on a SOI substrate, etching a localized
cavity under this active area into the buried oxide,
and filling it by the gate material [6]. After gate
patterning, the silicon active area is surrounded by
the gate.
Another gate-all-around (GAA) architecture,
based on the silicon-on-nothing (SON) process, has
been proposed more recently [7] and demonstrated
down to very short gate lengths. This approach relies
on successive epitaxial growth of cristalline SiGe and
Si layers. The SiGe layer is then selectively etched to
379
form a tunnel below the silicon film, and this tunnel
is filled by the gate material.
In the PAGODA architecture [8], the unpatterned
back gate stack is deposited and encapsulated before
wafer bonding. After initial substrate removal, the
front gate is patterned and silicon spacers
recrystallized from the channel are formed and
salicided. These salicided spacers are used as a hard-
mask for back gate etching and undercut.
The process flow proposed in [9] starts also from
back gate stack deposition and wafer bonding. The
whole stack, comprising the front gate, the channel
and the back gate is then patterned. Insulated layers
are formed besides the gates by use of oxidation rate
difference between the gate and the channel
materials. Source/drain regions are then regenerated
by lateral epitaxial regrowth from the channel edges.
The key technological issues of these planar
architectures are the precise controls of the very thin
film thickness and of the back gate dimension, since
the back gate is not directly accessible from the top
of the wafer.
On the other side, structures with fingered vertical
channel, such as FinFET [10], Trigate [11], :-FET
[12], 3-Gate [13] and nanowire-FET [14] have been
extensively studied. Fabrication of FinFETs relies on
high aspect ratio fin definition and short gate
patterning on this topology (fig. 2). Contrary to
planar devices, the conduction takes place on the
vertical sidewalls of the fin. The conduction width is
thus twice the fin height (hfin). As the fin height is
limited to typically 50 to 100nm, FinFETs are usually
designed as multifinger transistors, with a conduction
width quantified by 2.hfin. In order to obtain the same
drive current per silicon area as planar double gate
transistors, the pitch between the fingers has to be
lower than the fin height.
Drain
n
Fi
Source
Gate
Fig.2 Schematic of a FinFET device.
380 T. Poiroux et al. / Microelectronic Engineering 80 (2005) 378385
Thus, one key technological issue lies in the
multi-fin definition. Dense array of narrow fins have
to be patterned, with a good control of the fin width
and shape. The use of spacers as hard-mask for fin
patterning seems unavoidable, as it allows to double
the fin density and to design sub-10nm wide fins
[15].
Dr
ai
Sou
rce
Gate
Ga
Fin
te
Fig.3 Left: SEM top-view of a 20nm gate length multifinger
Trigate device. Right: Schematic cross-section of one fin.
Another approach consists in designing the fin
with roughly a square cross-section (fig. 3). In that
case, the channel is controlled by the gate on three
sides. This device, called Trigate [11], has a
conduction width given by twice the fin height plus
the fin width. Trigate is still a multifinger device, and
the pitch between fins has to be lower than hfin+wfin/2
to obtain higher drive currents per silicon area than
with planar devices. This limit is far more strict for
Trigate than for FinFET, since the fin height must be
as low as the fin width in order to operate in trigate
mode, and comparable to the gate length to benefit
from a good electrostatic channel control.
The best electrostatic control can be achieved
theoretically in a cylindrical channel completely
surrounded by the gate (fig. 4). The most advanced
practical realization of such a device is the 5nm gate
length nanowire-FET [14].
Drain
Source Gate
Fig.4 Schematic of a cylindrical surrounding-gate device.
:-FET and 3-Gate architectures are basically
similar to Trigate, but their channel control is close to
that of a quadruple-gate device, thanks to the
extension of the gate below the fin into the buried
oxide [16].
3. Design of fully-depleted devices
All these multiple gate devices are designed with
very thin active area. The use of polysilicon gates
would lead to unacceptable channel doping levels,
higher than 1019cm-3, in order to get appropriate
threshold voltages. These devices have thus to be
designed with metal gates and can benefit from the
enhanced transport properties of low doped channels,
their threshold voltage being adjusted thanks to
appropriate gate workfunctions.
The basic and general threshold condition for any
kind of MOSFET is derived from a capacitive point
of view as [17]:
C inv C ox  C dep (1)
with Cox=Hox/tox and Cinv and Cdep respectively the
derivative of the inversion and the depletion charge
with respect to the surface potential. This condition
gives threshold voltages located in the moderate
inversion regime. It corresponds for bulk devices,
where Cdep of the same order of magnitude as Cox, to
a band-bending of 2.If plus a few kT/q. For fully-
depleted devices, condition (1) reduces to:
C inv C ox (2)
In low-doped channel fully-depleted NMOSFETs,
the inversion charge in the subthreshold regime is
given (without confinement effect) by:
q.\
Q inv q.n i .t Si . exp (3)
k.T
with \ the channel potential (uniform in the weak
inversion regime), defined as the potential difference
between the mid-gap level position and the Fermi
potential in the source. ni is the intrinsic carrier
concentration, tSi is the film thickness (or the fin
width for FinFETs). Thus, condition (2) is given for
double gate devices by Qinv=-2.Cox.k.T/q, which
gives the following threshold voltage:
k.T 2.C ox .k.T ! 2 .S 2
Vth 'I mi  ln 2  (4)
q q .n i .t Si 2.q.m * .t Si 2
In equation (4), 'Imi represents the gate
workfunction with respect to that of intrinsic silicon
 T. Poiroux et al. / Microelectronic Engineering 80 (2005) 378385 381

and m* is the carrier confinement mass in the
transverse direction.
Figure 5 gives the dependence of the threshold
voltage with the film thickness. We notice that the
last term of (4), due to the confinement induced by
the quantum well formed by the thin silicon layer
between the two gate dielectrics, becomes significant
for film thickness below 5-7nm.
0,58
0.58
0.56
0,56
Threshold voltage (V)
'Imi=0eV, EOT=1.2nm
With an EOT of 1nm and a film thickness around 5-
10nm, this condition is verified for channel doping
levels lower than a few 1017cm-3.
Low doped channel fully depleted devices are
thus theoretically immune from dopant fluctuation
effects, which is one of the most important limitation
of bulk transistor scaling [18,19].
However, with a channel doping level of 1015cm-3
(i.e. intrinsic channel), a LxW=10x20nm transistor
with a film thickness of 5nm has a probability of
containing a dopant atom equal to 0.1%. In other

0,54
0.54 terms, 1 device over 1000 is likely to contain one
0.52
0,52
0,5
0.50
impurity atom, inducing a doping level of 1018cm-3,
0,48
0.48 while the others are dopant free. The electrostatic
0,46
0.46 effect of this impurity atom has to be simulated and
0,44
0.44
0,42
its impact on the electrical characteristics should be
0.42
0.40
0,4 carefully estimated.
0 5 10
10 15 20
20 Furthermore, from figure 5, we notice that the
Silicon film thickness (nm) threshold voltage becomes very sensitive to the film
thickness below 5nm because of quantum
Fig.5 Threshold voltage dependence with the film thickness confinement. This sensitivity can be estimated for a
in the case of a long low-doped double gate transistor. long channel device from (4). Assuming a 0.5nm
Dots: Quantum mechanical numerical simulations. Plain dispersion on the film thickness (EOT=1nm), a
line: Equation (4). Dashed line: Classical part of (4). tolerable long channel threshold voltage variation of
50mV gives a low-limit for tSi of 3nm.
Since the logarithm term in (4) is typically In addition to the gain linked to the use of low-
between 0.46 and 0.5V for an equivalent oxide doped channels, the mobility at a given inversion
thickness (EOT) of 1nm and a silicon film thickness charge is increased on fully-depleted devices with
in the 5-15nm range, one can estimate the required respect to bulk, since fully-depleted transistors
gate workfunctions for the sub-32nm nodes (table 1). operate at lower transverse electric field. Indeed, the
transverse effective field is given by:
Technology option NMOS PMOS K.Qinv  Qdep
High performance 4.4-4.5 eV 4.7-4.8 eV E eff (6)
HSi
Low operating power 4.5-4.6 eV 4.6-4.7 eV
with K1/2 and 1/3 respectively for electrons and
Low standby power 4.7-4.8 eV 4.4-4.5 eV
holes
While the depletion component is as high as 0.5
Table.1 Gate workfunctions required for the different
MV/cm in a bulk device with a 1018cm-3 doping
technology options with fully-depleted devices.
level, it is negligible in the case of low doped fully-
depleted transistor. The effective field range in strong
It should be noticed from equation (4) that the
inversion regime is then reduced from 0.6-1.5
threshold voltage is independent from the channel
MV/cm for bulk device to 0.1-1.0 MV/cm for fully-
doping level. This is true as long as the depletion
depleted.
charge plays insignificantly on electrostatics in the
Moreover, these devices will benefit from the
channel. This condition corresponds to:
advantages of the Silicon-On-Insulator (SOI)
k.T technologies: reduced junction capacitances (the only
q.N channel .t Si  2.Cox . (5)
q junction is the lateral source or drain to channel
junction), immunity to single event upsets and to
382 T. Poiroux et al. / Microelectronic Engineering 80 (2005) 378385

latch-up phenomenon, potential increase of the layout

5.05

Required drive current ratio DG/SG

density since no well is required to isolate the
channel from the bulk. 4,5
4.5

4.04
4. Multiple-gate devices versus single gate
3,5
3.5
One important issue for multiple gate devices is D=1.6
their dynamic performance with respect to single gate 3.03 D=1.4
D=1.2
transistors. Indeed, if the drive current is multiplied 2.5
2,5
D=1.0
by a factor of 2 in the case of double gate transistors,
2.02
the gate capacitance is also twice that of single gate. 2 2,5 3 3,5 4
2.0 2.5 3.0 3.5 4.0
Thus, the same intrinsic propagation delay
(Cgate.Vdd/Ion) is obtained, but for a doubled intrinsic Supply over threshold voltage ratio
power-delay product (Cgate.Vdd) if both devices are
designed with the same width. To have the same Fig.6 Required drive current ratio between a double gate
power-delay product at a given transistor width, and a single gate device to reach the same propagation
double gate devices have to operate at a supply delay power-delay compromise, as a function of the
voltage 2 times lower than that of single gate. To supply voltage.
reach the same Cgate.Vdd/Ion, the drive current should
be, at Vdd/2, 2 times the drive current obtained Anyway, thanks to their better electrostatics
with single gate device at Vdd (condition (7)). control, multiple gate transistors are likely to allow a
triple drive current with respect to single gate at a
DG
I on 
Vdd 2 ! 2 (7)
given off-state current [20].
I SG Vdd  To illustrate this, we have plotted on figure 7 the
on
From these considerations, if we write the drive
current as a power function of the gate overdrive,
dynamic performance will be better for double gate
MOSFET if the following condition is fulfilled on
the drive current at a given supply voltage:
D
ratio of the drive currents obtained experimentally on
20nm co-integrated single gate and double gate
devices. The drive current of the double gate
transistor is 1230A/m for an off-state current of
1A/m at Vdd=1.2V.
Measured drive current ratio DG/SG

DG
Ion Vdd  Vdd VthDG  1
! 2 . (8)
4,5
4.5

on Vdd 
ISG Vdd 
2 .VthDG  1  4,0
4.0
Same film thickness (10nm)

Figure 6 shows the required ratio as a function of

3,5
3.5
Vdd/Vth for various possible values of the power D.
For a typical supply over threshold voltage ratio of 3 3,0
3.0
and a value of D around 1.2-1.3, we obtain a required
Same electrostatics control (DG:10nm, SG:6nm)
drive current which is three times higher for the 2,5
2.5
double gate MOSFET than for the single gate.
Another approach to maintain the same power- 2,0
2.0
0,4
0.4 0,6
0.6 0,8
0.8 1,0
1.0 1,2
1.2 1,4
1.4
delay product between a single gate and a multiple
gate device is to reduce as far as possible the Supply voltage (V)
conduction width of the multiple-gate device to that
of the single gate. On planar devices, this implies a Fig.7 Experimental drive current ratio between 20nm
more aggressive lithography on the active area. This double gate and single gate devices as a function of Vdd.
is much more difficult for high aspect ratio FinFETs,
and a compromise has to be found on this structure Two cases can be considered:
between the minimum achievable conduction width 1- Both devices have the same film thickness of
and the layout density. 10nm. The single gate transistor suffers from much
 T. Poiroux et al. / Microelectronic Engineering 80 (2005) 378385 383

more electrostatic control loss and the drive current

6 6
10 10
ratio at Ioff=1A/m is between 3.4 and 4.0. 1e18 As 8KeV 4.5nm SiO2
2- Both devices exhibit roughly the same As 3KeV 3nm SiO2 2e14
3e14
electrostatics control (subthreshold swing and DIBL 5
10 1e19 5
10

Rsquare (Ohm/square)
5e14
respectively lower than 100mV/dec and 250mV/V).
The film thickness is reduced to 6nm for the single 4
1e20
4
10 10
gate transistor. The current ratio is still around 3, 1e15
because of the increased access resistances due to a 1e21
3 3
thinner film for the single gate device. 10 10

Furthermore, if we consider loading capacitances

(for example wires and junctions) in addition to 2
10
2
10
0 20 40 60 80 100 120 140 160 180
intrinsic gate capacitance in the previous discussion,
Silicon thickness (Angstr)
the multiple gate device advantage over single gate is
further increased, because of the higher drive
currents delivered by the multiple gate architectures.
Fig.8 Rsquare as a function of silicon thickness for different
Finally, since each added gate allows a better ionic implantation conditions (down triangles As 3keV 3
device scalability [16,21,22], the advantage of 1014, stars As 3keV 5 1014, squares As 3keV 1 1015, up
multiple gate devices is more and more evident as the triangles As 8keV 2 1014).
gate length is reduced.

5. Thin film challenges

Several critical issues are associated with the use
of thin film or narrow fin devices. An intrinsic
limitation is the mobility reduction observed for film
thickness below 5-7nm [23]. This effect is partly due
to an increased phonon scattering mechanisms on
thin films [24] and can be further accentuated by a
more pronounced impact of the surface roughness.
In addition, devices with ultra-thin films are
sensitive to thickness fluctuations through short Fig.9 TEM picture- For this BF2 implantation (1 1015 5keV)
channel effects variations. The scaling length derived a 6.8nm thick amorphized layer lies on top of the
in [25] for low-doped double gate transistors is: crystalline silicon film.

t Si 1 2.H Si .t ox As long as the whole layer is not damaged,

O 
2 2 H ox .t Si
For an EOT of 1nm, GO/O is about 70% of GtSi/tSi. As
short channel effects depends on L/O, a 1nm
fluctuation on a 7nm film thickness is equivalent to a
10% gate length variation.
From a technological point of view, several issues
are linked with the access optimization. As the film
thickness decreases, achieving silicon doping
becomes more and more challengeable, because on
one hand the square resistance of the silicon film
increases in 1/tSi as shown on figure 8, and on the
other hand increasing dose and/or energy leads to
surface silicon amorphization as shown on figure 9.
(9)
activation annealing allows the recrystallization of
the film. However when crystalline silicon layer is
too thin (roughly below 2nm), no post doping
recrystallization occurs and the resistance of the layer
strongly diverges (illustrated on fig. 8 with the 8keV
As implantation). Figure 10 shows that doping
process window is very narrow for a 5nm thick
silicon film. Alternative doping methods such as
plasma doping are likely overcome these difficulties.
Furthermore, the surface evolution velocity
during high thermal processes strongly depends on
temperature and silicon thickness. Thus as silicon
thickness decreases, the film becomes very sensitive
to high temperature treatments [26].
384
15
Dose=10 at.cm
(keV) (keV)
3 introduced to suppress the voiding that occurs in the
Pic dans l'oxyde
Maximum
in oxide
Energieenergy
2
Implantation
1
0 drain are made out of metal. The key issue in this
10 15
Interfacial
Oxyde oxide thickness
d'implantation ()
Fig.10 Allowed energy as a function of interfacial oxide
thickness. Above the dashed line, the 10nm thick silicon
film is totally amorphized, into the hatched region the
maximum of dopant concentration lies in the oxide layer.
Among them epitaxy pre-anneal can lead to a
destabilization which dramatically transforms the
continuous silicon film into silicon solid droplets on
the buried oxide (fig. 11a). Therefore selective
epitaxy of raised source/drain requires technological
developments such as temperature optimization,
modulation of the interface energy between silicon
and buried oxide to ensure that the silicon film will
keep its integrity during the whole fabrication
process. Figure 11b illustrates results obtained with a
pre-anneal temperature lowered to 650C.
Silicon film
Buried oxide
Fig.11 a) SEM cross-section- After H2 anneal, silicon
agglomeration is observed for thin films. b) Pre-anneal
temperature lowering leads to less dramatic consequences
as in this case, only moat recess is observed.
T. Poiroux et al. / Microelectronic Engineering 80 (2005) 378385
Salicidation process also requires technological
-2 optimization. Indeed diffusive metals have been
cran))
cran
silicon films when silicon diffuses into the salicide.
NiSi and PtSi are now replacing TiSi2 and CoSi2.
One way to overcome these technological difficulties
could be to design MOS transistors with metallic
source and drain either based on Schottky barriers
[27] or modified Schottky barrier [28]. In both cases,
selective epitaxy can be suppressed as source and
20 25 30 option is to find metals for N and PMOS with
() adjusted work function to design either adequate
Schottky barrier or low ohmic contacts.
6. How many gates ?
The last point that should be considered carefully
is the possibility to design devices with separated
gates. Several publications have shown the interest of
using two-gate devices (planar or FinFET) with
separated biases from a circuit design point of view.
In [29] and [30], the use of the back gate for a
threshold voltage control purpose is reported. Such a
control can allow to reduce significantly the power
consumption when circuits are idle [30].
Furthermore, in logic applications, double gate
devices with separated gate biases can be used to
replace single gate MOSFETs in parallel, for
example in NOR or NAND gates [31]. Analog
applications on a separated gate FinFET (called
MIGFET) such as signal mixer [32] has also been
demonstrated. These potential applications have to be
a) compared to the better scalability of three or four
gate devices (Trigate, :-FET, 3-Gate, surrounding
gate MOSFET) that allows to relax the constraints on
the film thickness for a given channel length.
7. Conclusions
Moat recess
b) We have discussed in this study the main
advantages and technological challenges associated
with the use of multiple gate devices. In particular,
we have studied the benefit they can bring over
single gate devices in dynamic operations. However,
the choice of one of these multiple gate architectures
is still a matter of discussion, and the circuit design
opportunities brought by separated gate devices
should be carefully considered.
 T. Poiroux et al. / Microelectronic Engineering 80 (2005) 378385
Acknowledgements
This study has been partly funded by the
NESTOR European Project (IST-2001-37114) and
by the Advanced Devices Program of the Alliance
(STMicroelectronics, Philips and Freescale
Semiconductors).
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