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A FULLY DIGITAL FRONT-END ARCHITECTURE FOR ECG ACQUISITION SYSTEM WITH 0.5 V

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LowPowerProjects February13,2017

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A Fully Digital FrontEnd Architecture for ECG Acquisition System With 0.5 V
Supply2016
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Abstract:
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This paper presents a new powereconomical electrocardiogram acquisition
system that uses a totally digital architecture to reduce the power consumption Re: A Fully Digital FrontEnd Architecture for ECG Acquisition System With 0.5 V Supp
and chip space. The proposed architecture is compatible with digital CMOS
Message
technology and is capable of operating with an occasional provide voltage of
0.five V. In this design, no analog block, e.g., lownoise amplifier (LNA), and
filters, and no passive components, like ac coupling capacitors, are used. A
movingaveragevoltagetotimeconverterisemployed,whichbehavesinsteadoftheLNAandantialiasingfilter.Adigitalfeedbackloop
is employed to cancel the impact of the dc offset on the circuit, that eliminates the need for coupling capacitors. The circuit is
implementedinzero.eighteenumCMOSprocess.Thesimulationresultsshowthatthefrontendcircuitconsumes274nWofpower.

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