By J on se n se r Z hao P u ls e

A new calculation for

designing multilayer planar
spiral inductors
A new, simple, and accurate expression lets you calculate
the coupling factor between multilayer PCB inductors.

P
lanar spiral inductors are less expensive than ei- depending on layout (Table 1). Figure 2 defines DIN (inner
ther chip or coil inductors for PCB (printed-cir- diameter) and DOUT.
cuit-board)-based designs. Accuracy in design- A multilayer inductor creates mutual inductance, how-
ing a spiral inductor is important because it is ever, so 3-D-magnetic-simulation software cannot simulate
difficult to modify the inductor once you have a multilayer inductor. Even if it could, the process would take
built it on the PCB. Some formulas are avail- a long time, and the results would be inconsistent. Therefore,
able for calculating the spiral inductor for RF-IC applications you must use the following two equations for the coupling
with inductance of less than 100 nH on a single-layer design. value, KC, to obtain the total inductor value with a mutual in-
For the application of HPNA (Home ductance: LTOTAL=L1+L22M,
Phoneline Networking Alliance) or RF- and M=2KCL1L2.
telecom designs, which need inductances You can obtain another sim-
of more than 10 H, no published paper ple and accurate expression for
or report accurately calculates spiral in- the inductance of a planar spi-
ductors with a large value in multiple ral by approximating the sides
layers. of the spirals using symmetri-
Three options exist for designing large cal current sheets of equiva-
planar spiral inductors on a PCB: In- lent current densities (Refer-
crease the number of turns; increase the ence 1). Although the accu-
inner diameter, DIN; or add layers and racy of Equation 1 decreases
increase the coupling between multilay- as the ratio of space between
ers. The first two options occupy more traces to the trace width in-
area on the PCB, so the third option is creases, it exhibits a maximum
the best way to accommodate a large in- error of 8% for a space less
ductor when there is limited PCB area. than or equal to three times
Multilayer planar spiral inductors of- Figure 1 The traditional formula for calculating inductor the width. Note that design-
fer several advantages over other induc- size is accurate for single-layer planar spiral inductors ers typically build practical in-
tors. They have stable inductance, for ex- but does not calculate the inductance of those that tegrated spiral inductors with
ample, and, if the PCB has a fixed layout, employ multiple layers and connect with via holes. space less than or equal to the
their inductance tolerance is less than width because smaller spacing
2%. Further, spiral inductors cost less than chip inductors and improves the interwinding magnetic coupling and reduces
require a less complex manufacturing process, making them the area the spiral consumes. In PCB design, this practice is
easier to manufacture with low yield loss. not a concern because the intertrace spacing is normally less
The traditional formula for calculating inductor size is ac- than the trace width.
curate for single-layer planar spiral inductors, but it does not Analysis of these equations and experimenting with large
calculate the inductance for planar spiral inductors built on inductors shows that Equation 1 is accurate, and the increas-
multilayers and connected with via holes (Figure 1). ing value of the inductor does not affect the accuracy of these
You can calculate a single-layer inductors value using equations. The result shows an inductance close to the cal-
Equation 1: culated value, with the difference at high frequency due to
the actual distribution of parameters throughout the circuit
L=[(0N2DAVGC1)/2][ln(C2/)+C3+C42)], (1) rather than the lumped-parameter analysis of the model (Fig-
ure 3). Thus, you can use Equation 1 to calculate a large,
where N is the number of turns; 0 is the vacuum permeabil- single-layer inductor.
ity, 4107; is the fill ratio, (DOUTDIN)/(DOUT+DIN); DAVG Calculations for a multilayer coupled planar spiral inductor
is the average diameter, (DIN+DOUT)/2; and C1C2 are factors are more complex than those for a single-layer spiral inductor.

JULY 29, 2010 | EDN 37

 Table 1 Layout- W
S
dependent coefficientS W
S
Layout C1 C2 C3 C4
Square 1.27 2.07 0.18 0.13
Hexagonal 1.09 2.23 0 0.17
DIN DOUT
Octagonal 1.07 2.29 0 0.19 DIN

Circle 1 2.46 0 0.2

DOUT
Table 2 Inductor turns
A B C D
0.184 0.525 1.038 1.001
(a) (b)

The coupling between the inductors W

on each layer is difficult to simulate S
because the coupling value depends
on the number of turns of the induc-
tor and the distance between the two
layers. Experimenting over the range
of inductor turns, N, with N equal to DIN
a 5- to 20-turns ratio, and the distance W
DIN
S
between the inductors on the two lay- DOUT
ers, X, with X equal to a 0.75- to 2-mm
distance, yields Equation 2 to calcu-
late the coupling factor:

KC=[N2/(AX3+BX2+CX+D) DOUT
(1.67N25.84N+65)0.64], (c) (d)
(2)
Figure 2 The C1C4 factors depend on layout: square (a), hexagonal (b), octagonal (c),
where X is the distance in millime- and circle (d).
ters between the inductors on the two
layers and N is the number of inductor turns that Figure 2 spacing, 1.0922-mm (43-mil) DIN, and 0.75-mm inter-
defines. The inductor turns of both layers must be the same layer distance. First, you must analyze the circular lay-
(Table 2). out to find DOUT and DAVG to obtain the single-layer in-
With the coupling factor from Equation 2 and the single ductance, LS, and the coupling factor, KC: DOUT=DIN+2
planar-spiral-inductor calculation from Equation 1, you can W+(W+S)(2N1)=8.9972; DAVG=(DIN+DOUT)/2=5.0927;
figure the total inductance of a two-layer inductor by using =(DIN+DOUT)/(DOUT+DIN)=0.7855; LS=[(N2DAVGC1)/2]
the mutual-inductance formula (Reference 2).
On a two-layer coupled inductor, you can calculate CH1 LS 10.01 H/REF 0H 0 52.772 H
the total inductance with the following layout informa- 113.359120598 MHz
tion: 15.75 turns, 0.127-mm (5-mil) width and trace
COR
1 2 3 4 5 6 7

4.1

3.1 HLD
INDUCTANCE IF BW 300 Hz POWER 0 dBm SWP 12.04 SEC
(H) START 100 kHz STOP 500 MHz
2.1
NO. FREQUENCY VALUE
0 113.359120598 MHz 52.772 H
1.1 1 100 kHz 1.1618 H
2 1 MHz 1.1197 H
3 5 MHz 1.108 H
0.1 4 10 MHz 1.1071 H
0.1 1 10 100
5 15 MHz 1.1137 H
BANDWIDTH (MHz) 6 20 MHz 1.1267 H
MEASURED CALCULATED 7 30 MHz 1.1703 H

Figure 3 An analysis of the equations shows an inductance Figure 4 The measured inductors frequency response is close
close to the calculated value. to the theoretical calculation to a frequency as high as 100 MHz.

38 EDN | JULY 29, 2010

 Table 3 Four-layer-stack structure CH1 Q 20 U/REF 200 U 921.51 m
113.359120598 MHz
Layer 1 Spiral inductor 1 mil 0.025 mm
Layer 2 Substrate 34 mils 0.85 mm COR

Spiral inductor 1 mil 0.025 mm

6 7
Layer 3 Substrate 34 mils 0.85 mm 4 5
3
Spiral inductor 1 mil 0.025 mm 1 2 0
HLD
Layer 4 Substrate 34 mils 0.85 mm IF BW 300 Hz POWER 0 dBm SWP 12.04 SEC
START 100 kHz STOP 500 MHz
Spiral inductor 1 mil 0.025 mm
NO. FREQUENCY VALUE
0 113.359120598 MHz 921.51 m
1 100 kHz 1.1373 m
(ln(C2/)+C3+C42)]=106H=1 H; KC=0.64. Per the mu- 2 1 MHz 10.032 m
tual-inductance connection equations, the total inductance 3 5 MHz 31.196 m
is L1+L2+2KC=L1L2=3.28 H. 4 10 MHz 45.67 m
5 15 MHz 55.195 m
In a design with more than two layers, there are more cou- 6 20 MHz 61.729 m
pling factors between any two layers. You can use the same 7 30 MHz 71.491 m
method to obtain each coupling factor and then use the to- Figure 5 The self-resonant frequency is better than that of a chip
tal inductance per the mutual-inductance connection formu- inductor with the same value.
las. You can also calculate a four-layer spiral inductor with
15.75 turns, a 5-mil-wide trace, a 5-mil trace spacing, and
a 43-mil circular inner diameter. Table 3 shows the stack Several samples with different sizes and structures verify
structure of the PCB. You must first calculate the single-layer the new calculation and measure and compare samples. To
inductance, LS, which is 1 H. It has six coupling factors: perform the verification, you must first increase the size of
KC12, KC13, KC14, KC23, KC24, and KC34. KC12=KC23=KC34=0.618, the single-layer planar inductor and then increase the num-
KC13=KC24=0.459, and KC14=0.294. So the total inductance ber of turns from four or five to 15. You must also increase the
is: L1+L2+L3+L4+(2KC12+2KC13+2KC14+2KC23+2KC24+ track width from 4 to 200 microns and increase DIN from 100
2KC34)L1=10.132 H. The four-layer inductor has a 10.1- to 2400 microns. The inductance calculated using Equation
H inductance. 1 is 1.1 H. Figure 4 shows the measured inductor frequency

JULY 29, 2010 | EDN 39

CH1 LS 10.01 H/REF 0H 29.403 H
0 40 MHz

COR
1 2 3 4 56 7

HLD
IF BW 300 Hz POWER 0 dBm SWP 12.04 SEC
START 100 kHz STOP 500 MHz
NO. FREQUENCY VALUE
0 40 MHz 29.403 H
1 100 kHz 3.8144 H
2 1 MHz 3.7903 H
3 5 MHz 3.7677 H
4 10 MHz 3.8956 H
5 15 MHz 4.1822 H
6 20 MHz 4.6846 H
7 30 MHz 7.1989 H
Figure 8 You can build a fifth-order, lowpass filter with a two-
Figure 6 The frequency response for the spiral inductor is better layer, coupled spiral inductor.
than that of a chip inductor with the same value.

CH2 S21 LOG 20 dB/REF 60 dB 5: 71.551 dB

CH1 Q 5 U/REF 20 U 4 5 160.95 m CH4 MEM LOG 5 dB/REF 15 dB 5: 0.03330 dB
6 50 MHz CH2 MARKERS
3 42.668537658 MHz * 1: .47690 dB
1 3 4 5 30 kHz
COR 7 2: .40430 dB
2 2 MHz
2
3: .45610 dB
2.2 MHz
1 0 4: 67.072 dB
12 MHz
4 5
CH4 MARKERS
IF BW 300 Hz POWER 0 dBm SWP 12.04 SEC PRM 3 1: 30.965 dB
START 100 kHz STOP 500 MHz 30 kHz
COR
NO. FREQUENCY VALUE 2 2: 23.042 dB
0 42.668537658 MHz 160.95 m 1 2 MHz
1 100 kHz 2.0236 m COR 3: 21.310 dB
2 1 MHz 16.411 m 2.2 MHz
3 5 MHz 34.595 m 4: .14550 dB
4 10 MHz 42.162 m 12 MHz
5 15 MHz 42.886 m START .030 MHz STOP 100 MHz
6 20 MHz 38.899 m 2 INSERTION LOSS 4 RETURN LOSS
7 30 MHz 22.878 m
Figure 9 The performance of the filter matches the simulation
Figure 7 Two-layer planar spiral inductors have better Q and result.
self-resonant frequency than does a chip inductor.

response, which is close to the theoretical calculation to a
frequency as high as 100 MHz. The Q value and self-reso-
nant frequency in figures 4 and 5 are better than that of the
same-value chip inductor. Normally, the chip inductors Q
value is only 15 to 20.
To verify the coupling factor, you build two equally sized,
1.1-H planar spiral inductors on a two-layer PCB substrate
with a thickness of 0.8 mm. The calculated inductor value us-
ing Equation 2 is 3.8 H. Figures 6 and 7 show the frequency
ACKNOWLEDGMENT
The author would like to thank Homer Feng, KB Ong, Paul
Doyle, Andrew Zhang, and Bino Zhu for their valuable input and
technical support during this project.
REFERENCES
1 Rosa, Edward B, Calculation of the self-inductances of
single-layer coils, Bulletin of the Bureau of Standards, Vol-
ume 2, No. 2, 1906, pg 161, http://bit.ly/9YpeeX.
2 Nilsson, James W, and Susan A Riedel, Electric Circuits,

response. The two-layer planar spiral inductors Q and self-res-
onant frequency are better than that of a chip inductor with
the same value.
Figure 8 shows a fifth-order lowpass filter with two-layer
coupled planar spiral inductors using the new calculation for
the design of this filter. The performance of the filter match-
es the simulation result and works for HPNA and other tele-
communication applications (Figure 9). The simplicity and
robustness of these calculations simplify circuit design and
optimization applications, which you can incorporate into
the computer-circuit model for spiral inductors.EDN
Seventh Edition, Prentice Hall, May 17, 2004, ISBN
0131465929.
A u t h or s b i ogra p h y
Jonsenser Zhao is a senior design engineer at the
network division of Pulses Chinese development
center, where he is responsible for transformer, fil-
ter, and splitter design. Zhao has a bachelors degree
in electronics from the Air Force Missile College
(Shaanxi, China). His interests include developing
designs for telecommunications applications.

40 EDN | JULY 29, 2010