Course Code & Course Title : 15EC301 Digital System Design

Credits : 3003
Course Designer : Dr. R. Udaiyakumar (r.udaiyakumar@skct.edu.in)
COURSE OVERVIEW
Almost all digital circuits are designed for two-state operation, which means the signal voltages
are either at a low level or a high level. Because they duplicate mental processes, digital circuits are
often called logic circuits. A gate is a digital circuit with 1 or more inputs, but only 1 output. The output is
high only for certain combinations of the input signals.
An inverter is one type of logic circuit, it produces an output that is the complement of the
input. An OR gate has 2 or more input signals; it produces a high output if any input is high. An AND
gate has 2 or more input signals; it produces a high output only when all inputs are high.
Truth tables often use binary 0 for the low state and binary 1 for the high state. The number of
entries in a truth table equals 2n, where n is the number of input signals.
The overbar is the algebraic symbol for the NOT operation, the plus sign is the symbol for the OR
operation, and the times sign is the symbol for the AND operation. Since the Boolean operators are
codes for the OR gate, AND gate, and inverter, we can use Boolean algebra to analyze digital circuits.
An AND-OR circuit always produces a sum-of-products equation, while the OR-AND circuit results in a
product-of-sums equation.
The NOR gate is equivalent to an OR gate followed by an inverter. De Morgans first theorem
tells us that a NOR gate is equivalent to a bubbled AND gate. Because of De Morgans first theorem, a
NOR-NOR circuit is equivalent to an OR-AND circuit.
The NAND gate represents an AND gate followed by an inverter. De Morgans second theorem
says the NAND gate is equivalent to a bubbled OR gate. Furthermore, a NAND-NAND circuit is
equivalent to an AND- OR circuit. The NAND gate is the backbone of the 7400 TTL series because most
devices in this family are derived from the NAND-gate design. The NAND gate is a universal gate since
any logic circuit can be built with NAND gates only.
With positive logic, binary 1 represents high voltage and binary 0 represents low voltage. Also,
positive true stands for high voltage and positive false for low voltage. With negative logic, binary 1
stands for low voltage and binary 0 for high voltage. In this system, negative true is equivalent to low
voltage and negative false to high voltage.
Every Boolean equation has a dual form obtained by changing OR to AND, AND to OR, 0 to 1,
and 1 to 0. With Boolean algebra you may be able to simplify a Boolean equation, which implies a
simplified logic circuit.
Given a truth table, you can identify the fundamental products that produce output 1s. By
ORing these products, you get a sum-of-products equation for the truth table. A sum-of-products
equation always results in an AND-OR circuit or its equivalent NAND-NAND circuit.
The Karnaugh method of simplification starts by converting a truth table into a Karnaugh map.
You encircle all the octets, quads, and pairs. This allows you to write a simplified Boolean equation and
to draw a simplified logic circuit. When a truth table contains dont-cares, you can treat the dont-
cares as 0s or 1s, whichever produces the greatest simplification.
One way to get a product-of-sums circuit is to complement the Karnaugh map and write the
simplified Boolean equation for g. Next, you draw the NAND-NAND circuit for g. Finally, you change
the NAND-NAND circuit into a NOR-NOR circuit by changing all NAND gates to NOR gates and
complementing all signals.
 Entered variable map maps a truth table into lower dimension space compared to Karnaugh
map though the simplification procedure is similar. A Karnaugh map based method of simplifying
multiple-output function is discussed. This identifies reusable terms across various functions and includes
them to reduce overall complexity. Quine- McClusky method provides a step-by-step approach for
logic simplification and is a preferred tool that involves large number of variables. Practical digital
circuit requires finite propagation delay to transfer information from input to output. This often leads to
hazards in the form of unwanted glitches. Hazards are prevented by using additional gates serving as
hazard cover.
A multiplexer is a circuit with many inputs but only one output. The 16-to-1 multiplexer has 16
input bits, 4 control bits, and 1 output bit. The 4 control bits select and steer 1 of the 16 inputs to the
output. The multiplexer is a universal logic circuit because it can generate any truth table.
A demultiplexer has one input and many outputs. By applying control signals, we can steer the
input signal to one of the output lines. A decoder is similar to a demultiplexer, except that there is no
data input. The control bits are the only input. They are decoded by activating one of the output lines.
BCD is an abbreviation for binary-coded decimal. The BCD code expresses each digit in a
decimal number by its nibble equivalent. A BCD-to-decimal decoder converts a BCD input to its
equivalent decimal value. A seven-segment decoder converts a BCD input to an output suitable for
driving a seven-segment indicator.
An encoder converts an input signal into a coded output signal. An example is the decimal-to-
BCD encoder. An exclusive-OR gate has a high output only when an odd number of inputs are high.
Exclusive-OR gates are useful in parity generators-checkers.
Magnitude comparators are useful in comparing two binary numbers. It generates three
outputs that give if one number is greater, equal or less than the other number. Cascading magnitude
comparators we can compare two numbers of any size.
A ROM is a read-only memory. Smaller ROMs are used to implement truth tables. ROMs are
expensive because they require a mask for programming. PROMs are user-programmable and ideal for
small production runs. EPROMs are not only user-programmable, but they are also erasable and
reprogrammable during the design and development cycle. PALs are chips that are programmable
arrays of logic. Unlike the PROM with its fixed AND array and programmable OR array, a PAL has
programmable AND array and a fixed OR array. The PAL has the advantage of having up to 16 inputs
in commercially available devices. In the PLA both the AND array and the OR array are programmable.
The PLA is a much more versatile programmable logic device (PLD) IC than the PROM or the PAL.
Numbers represent physical quantities. As long as you know the number code being used,
those strange-looking answers in other number systems make perfect sense. Subscripts can be used as
a reminder of the base of the number system.
The unsigned 8-bit numbers are from 0000 0000 to 1111 1111, equivalent to decimal 0 to 255.
The unsigned 16-bit numbers are from decimal 0 to 65,535. Overflows occur when a sum exceeds the
range of the number system. With 8-bit arithmetic, an overflow occurs when the unsigned sum exceeds
255.
Sign-magnitude numbers use the MSB as a sign bit, with 0 for the + sign and 1 for the sign. The
rest of the bits are for the magnitude of the number. For this reason, 8-bit numbers cover the decimal
range of 127 to +127, while 16-bit numbers cover 32,767 to +32,767.
The 2s complement representation is the most widespread code for positive and negative
numbers. Positive numbers are coded as sign-magnitude numbers, and negative numbers are coded
as 2s complements. The key feature of this number system is that taking the 2s complement of a
number is equivalent to changing its sign. This characteristic allows us to subtract numbers by adding
the 2s complement of the subtrahend. The advantage is simpler arithmetic hardware.
The half-adder has two inputs and two outputs; it adds 2 bits at a time. The full-adder has three
inputs and two outputs; it adds 3 bits at a time. By connecting a controlled inverter and full-adders, we
can build an adder-subtractor. This circuit can perform addition, subtraction, multiplication, and
division.
A fast adder brings parallelism in addition process, more specifically by generating the carry
using extra hardware through a look ahead logic. An Arithmetic Logic Unit is a versatile device, which
can generate many useful arithmetic and logic functions with appropriate selection of inputs.
Cascading of these devices is usually possible for working with larger sized numbers.
Flip-flop is a basic memory element. This device can be used to store 1 bit of digital information.
There are four types of flip-flops, namely S-R, J-K, T type, and D type. All four flip-flops have been
explained in detail, including their design using logic gates. The triggering systems of flip-flops have also
been incorporated in this chapter. Flip-flops are converted from one type to others. Therefore,
conversions of flip-flops are also discussed here. Applications of flip-flops in registers, frequency division,
counters, memory elements, contact bounce elimination, etc. have been included in this course.
Shift registers are storage devices and used for storing binary data. JK, D and SR flip-flops can
construct shift registers. In shift register, several flip-flops can be cascaded together and are driven by a
common clock. In n bit shift register, n flip-flops are required. In this chapter, four basic types of shift
registers: Serial In-Parallel Out, Serial In- Serial Out, Parallel In-Parallel Out, Serial In- Parallel Out are
discussed with examples and ICs. A bi-directional shift register can move data internally in either left or
right direction. In a universal shift register, data can be entered/loaded in serial and parallel, and data
can also be out in serial and parallel. The bi-directional and universal shift register ICs are also
incorporated in this chapter. The Ring and Johnson shift counters are two specialized shift registers used
to create sequential outputs. The Ring counter has n states in its sequence but the Johnson counter
has 2n states, where n is the number of stages.
Counter is a sequential circuit and it can be developed by using flip-flops. Generally, counter
has a 2n counter states, where n is the number of flip-flops used in the counter. Counter of any value
can be designed by skipping some states from the natural count. For this feedback signals are taken
from some flip-flops and then reset or clear all flip-flops. In this chapter, operations of asynchronous
(ripple) and synchronous counters are explained in detail. The design of synchronous counters, mod-n
counters, and cascade connection of counter are also incorporated. Some asynchronous and
synchronous counters ICs are also included for practical implementation. Cascaded counters,
programmable counters, self-starting and self-correcting counters and applications of counters are also
discussed.
Generally, any sequential circuit consists of a combinational logic circuit and memory
elements. The output of combinational logic circuit is stored in memory elements. Memory elements
output feedback into combinational logic circuit and used as input variables. The output of
combinational logic circuit is function of the external inputs and inputs from memory elements. In this
chapter, the modeling and classification of sequential circuits has been discussed. The operation of
Mealy machines and Moore machines, function of state table, state diagram and state equations are
also incorporated. Designs of synchronous and asynchronous sequential circuits with examples are
discussed elaborately.
 ANALYSIS
Program Outcomes addressed
PO Program Outcome
Engineering knowledge: Apply the knowledge of mathematics, science, engineering
fundamentals, and Electronics and communication engineering specialisation to the solution
PO1
of complex problems in Analog & Digital Electronic Systems, Signal & Image Processing, VLSI &
Embedded systems, wired & wireless communication networks.
Problem analysis: Analyse complex problems in Analog & Digital Electronic Systems, Signal &
Image Processing, VLSI & Embedded systems, wired & wireless communication networks using
PO2
first principles of mathematics, science, and engineering sciences to reach substantiated
conclusions

Program Specific Outcomes addressed

Program Specific Outcome

PSO1 Recognize, adapt and to apply the knowledge of electronics and communication
engineering to optimize analog and digital electronic systems for various applications.

Course Outcomes

Class
CO Course Outcomes POs CL KC Sessions
(approx.)
C301.1 Understand the operations of basic logic
gates and importance of Boolean algebra in
optimizing the circuit complexity and apply PO1,PO2, U
F 9
the Boolean laws and theorems, mapping PSO1 AP
techniques and tabulation techniques in
simplifying the logic expressions
C301.2 Understand the concepts of basic
combinational circuits and apply the learned PO1,PO2, R,U
F,C,P,FDC 9
concepts to design medium complex PSO1 AP
arithmetic circuits
C301.3 Understand the concept of sequential circuits
and constructional details of Flip-flops and PO1,PO2, U
F,C,P,FDC 9
design one flip-flop from any other flip-flop by PSO1 AP
including suitable combinational circuits
C301.4 Understand the concepts of registers and
different types of registers and differentiate
PO1,PO2 R,U F,C 5
between asynchronous and synchronous
counters
C301.5 Design various types of counters by using
PO1,PO2, AP P,FDC 4
registers
C301.6 Understand the design procedure of
designing synchronous and asynchronous PO2, PSO1 U F,C,P,FDC 4
sequential circuits
C301.7 Design both asynchronous and synchronous P,FDC,C&S,
PSO1 AN 5
sequential circuits for any given specification PC
Total Hours of instruction 45
Course Outcomes in Taxonomy Table

Knowledge Categories Cognitive Levels

Remember Understand Apply Analyze Evaluate Create
C301.1, C301.2, C301.1,
C301.2,
Factual C301.3, C301.4, C301.2, X X X
C301.4
C301.6 C301.3
C301.2, C301.2, C301.3, C301.2,
conceptual X X X
C301.4 C301.4,C301.6 C301.3
C301.2,
C301.2,
Procedural C301.2 C301.3, C301.7 X X
C301.3,C301.6
C301.5
Metacognitive X X X X X X
C301.2,
Fundamental Design C301.2,C301.3,
C301.2 C301.3, C301.7 X X
Concepts C301.6
C301.5
Criteria and
X X X C301.7 X X
Specifications
Practical Constraints X X X C301.7 X X
Design
X X X X X X
Instrumentalities

Strength to which POs and PSO are addressed by COs

36 of 45 (80%) classroom sessions are devoted to PO1 Course Level PO1 strength is 3
40 of 45 (89%) classroom sessions are devoted to PO2 Course Level PO2 strength is 3
36 of 45 (80%) classroom sessions are devoted to PSO1 Course Level PSO1 strength is 3

Course PO/PSO Mapping

Course a b c d e f g h i j k l m

15EC301 3 3 0 0 0 0 0 0 0 0 0 3 0

Competencies

At the end of the course the student should be able to

Competency CO CL KC Sessions
(approx.)
Understand the operations of AND,OR & NOT logic
C1 gates and importance of Boolean algebra in C301.1 U F 4
optimizing the circuit complexity
Apply the Boolean laws and theorems, Karnaugh
C2 map techniques and Quine Mc-clusky method in C301.1 AP F 5
simplifying the logic expressions
Understand the concepts of multiplexing,
C3 demultiplexing, decoding, encoding, parity
C301.2 U F,C, 3
generation and checking and magnitude
comparators.
C4 Recall the basic arithmetic operations on binary F,C,P,
C301.2 R 2
numbers in true and complimentary forms FDC
C5 Apply the concepts of basic combinational circuits C301.2 U.AP F,C,P 4
 to design half adder, full adder, adder-subtractor,
fast adders and ALU
C6 Understand the concept of sequential circuits and F,C,P,
C301.3 U 5
constructional details of SR, JK,D and T Flip-flops FDC
C7 Design one flip-flop from any other flip-flop by C,P,
C301.3 AP 4
including suitable combinational circuits FDC
Understand the concepts of registers and different
C8 types of shift registers such as SISO,SIPO,PISO and C301.4 U F,C,P 2
PIPO
C9 Identify the types of counters and differentiate
C301.4 R,U F,C 4
between asynchronous and synchronous counters
Design asynchronous counters, synchronous up
C10 counter, synchronous down counter, synchronous
C301.5 AP P,FDC 3
up-down counter, MOD n counters D, T and JK flip-
flops
C11 Understand the sequential circuit model C301.6 U F,C 1

C12 Prepare state table, state diagram and state C301.6 F,C,P,
U,AP 2
equation for the given specification FDC
C13 Design synchronous sequential circuits for any C301.7 C,P,
AP,AN 2
given specification using design procedure FDC
C14 Understand the design procedure of designing C301.7 P,FDC,
U 2
asynchronous sequential circuits C&S
Design asynchronous sequential circuits for any
C15 C301.7 P,FDC,
given specification by using state transition AP,AN 2
C&S,PC
diagram

DESIGN

Test/Assessment Items for C301.1

Course Outcome POs/PSOs CL KC

C301.1 Understand the operations of basic logic gates and importance

of Boolean algebra in optimizing the circuit complexity and PO1,PO2,
U,AP F
apply the Boolean laws and theorems, mapping techniques PSO1

and tabulation techniques in simplifying the logic expressions

TI1 Work out the truth table for the figure:

Ans. With two input signals (A and B), four input cases are possible: low-low, low-high, high-low, and
high-high. For convenience, let L stand for low and H for high. Then, the input possibilities are
LL, LH, HL, and HH, as listed in Fig. 1.9b. Here is what happens for each input possibility.
CASE 1 A is low and B is low. With both input voltages in the low state, each inverter has a
high output. This means that the OR gate has a high output.
CASE 2 A is low and B is high. With these inputs the upper inverter has a high output, while
the lower inverter has a low output. Since the OR gate still has a high input, the output Y is
high.
 CASE 3 A is high and B is low. Now, the upper inverter has a low output and the lower
inverter has a high output. Again, the OR gate produces a high output, so that Y is high.
CASE 4 A is high and B is high. With both inputs high, each inverter has a low output. This
time, the OR gate has all inputs in the low state, so that Y is low.

Considering all these cases the truth table is derived as

A B Y
0 0 1
0 1 1
1 0 1
1 1 0

TI2 What is the logic circuit whose Boolean equation is Y = ABC + ABC

Ans. This is a sum-of-products equation with some of the inputs in complemented form. Figure
shows an AND-OR circuit with the foregoing Boolean equation. The upper AND gate produces
a logical product of ABC and the lower AND gate produces a logical product of ABC and
these two product terms are driven through an two input OR Gate.

TI3 Derive the simplified Boolean equation for the following logic equation expressed by
minterms? Y = F(A, B, C, D) = m (7, 9, 10, 11, 12, 13, 14, 15)

Ans.

Y = AB + AC + AD + BCD

TI4 Derive the simplified logic equation of given table by Quine-McClusky method?
A B C Y
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
Ans.

Tables that determine prime implicants and selects essential prime implicants are shown in
Figs. a and b respectively. We find both the prime implicants are essential prime implicants.
The simplified logic equation thus is expressed as Y = AB + BC

TI5 Get a minimized expression for Y = F(A, B, C) = A B C + A B C + A BC + A B C using

multiple methods?
We can solve this using Boolean Algebra, Karnaugh Map, Entered Variable Map and QM
Ans.
Algorithm.
In Method-1 We take help of Boolean Algebra for minimization. We see that A B C can be
combined with all three terms using distributive law
Since, in Boolean algebra X = X + X + X we can write
Y = A B C + ( A B C + A B C + A B C) + A BC + A B C
From associative law
Y = ( A B C + A B C) + ( A B C + A BC) + ( A B C + A B C)
From distributive law (Eq. 2.5)
Y = A B ( C + C) + A C( B + B) + B C( A + A)
Since X + X = 1, Y = A B . 1 + A C . 1 + B. C . 1
= AB + AC+BC (since, X . 1 = X)
In Method-2, we use Karnaugh Map for minimization. Fig. shows the solution by this method.

Note how one term is common in three groups formed and the similarity with Method-1 solu-
tion.
In Method-3, we use Entered Variable Map for minimization.
Figure shows the solution by this method. Since 1 = C + C, we need a separate group for AB =
00 as C is not explained by other two groups. We use C embedded in 1 to make other two
groups bigger and reduce the number of literals, and thus minimize the expression.
 In Method-4, we use QM algorithm for minimization. Figure shows prime implicants and
essential prime implicants. The final solution is arrived at by combining essential prime
implicants.

Test/Assessment Items for C301.2

Course Outcome POs/PSOs CL KC

Understand the concepts of basic combinational circuits and PO1,PO2, R,U, F,C,P,FDC
C301.2
apply the learned concepts to design medium complex PSO1 AP
arithmetic circuits

TI1 (a) Realize Y = AB + BC + ABC using an 8-to-1 multiplexer. (b) Can it be realized with a 4-to-1
multiplexer?

Ans. (a) First we express Y as a function of minterms of three variables. Thus

Y = AB + BC + ABC

Y = AB(C + C) + BC(A + A) + ABC [As, X + X = 1]

Y = ABC + ABC + ABC + ABC + ABC

Comparing this with equation of 8 to 1 multiplexer, we find by substituting D0 = D2 = D3 = D4 =

D7 = 1 and D1 = D5 = D6 = 0 we get given logic relation

(b) Let variables A and B be used as selector in 4 to 1 multiplexer and C fed as input. The 4-to-
1 multiplexer generates 4 minterms for different combinations of AB. We rewrite given logic
equation in such a way that all these terms are present in the equation.

Y = AB + BC + ABC

Y = AB + BCA + A) + ABC [As, X + X = 1]

Y = AB.C + AB.1 + AB.C + AB.C

Compare above with equation of a 4-to-1 multiplexer. We see D0 = C, D1 = 1, D2 = C and

D3 = C generate the given logic function.

TI2 Show how using a 3-to-8 decoder and multi-input OR gates following Boolean expressions can
 be realized simultaneously.

F1(A, B, C) = m(0, 4, 6); F2(A, B, C) = m(0, 5); F3(A, B, C) = m(1, 2, 3, 7)

Ans. Since at the decoder output we get all the minterms we use them as shown in Fig. 3.17 to get
the required Boolean functions.

TI3 Design a priority encoder the truth table of which is shown in Fig. The order of priority for three
inputs is X1 > X2 > X3. However, if the encoder is not enabled by S or all the inputs are inactive
the output AB = 00.

Ans. Following figures show the Karnaugh map for output A and B respectively. Note that, we have
used a different notation for input variables in these maps. Compare this with notations
presented in previous chapters. You will find a variable with prime is presented by 0 and if it is
not primed is represented by 1. Then taking groups of 1s we get the design equations as
shown in the figure. The logic circuits for output A and B can be directly drawn from these
equations.

TI4 Show how to connect a 74180 to generate a 9-bit output with odd parity?

Figure shows one solution. The ODD INPUT (pin 4) is connected to +5 V, and the EVEN INPUT
(pin 3) is grounded. Suppose the input data X7 X0 has even parity. Then, the third entry of
table tells us the S ODD OUTPUT (pin 6) is high. Therefore, the 9-bit number X8 X0 coming out
of the circuit has odd parity. On the other hand, suppose X7 X0 has odd parity. Then the
fourth entry of Table 3.8 says that the S odd output is low. Again, the 9-bit number X8 X0
 coming out at the bottom of Fig. has odd parity.

Ans.

The following conclusion may be drawn. Whether the input data has even or odd parity, the 9-
bit number being generated in Fig. always has odd parity.

T15 Show how two IC 7485 can be used to compare magnitude of two 8-bit numbers?

Ans.

Refer to Fig. b for solution. The numbers to compare are X: X7 X6X0 and Y: Y7 Y6Y0. We
need two IC 7485s each one comparing 4 bits. The most significant bits (suffix 7,6,5,4) are
given higher priority and the final output is taken from that IC 7485 which compares them.
Generate the following Boolean functions using PAL
TI6
Y3 = ABCD + ABCD + ABCD + ABCD
Y2 = ABCD + ABCD + ABCD
Y1 = ABC + ABC + ABC + ABC
Y0 = ABCD

Ans.
 How would an 8-bit microcomputer process this:
TI6
18, 357
-12, 618
___________
?

Ans It would use double-precision arithmetic, synonymous with 16-bit arithmetic. This arithmetic is
used with 16-bit numbers in this form:

X15X14X13X12 X11X10X9X8 X7X6X5X4 X3X2X1X0

Numbers like these have an upper byte X15 X8 and a lower byte X7X0. To perform 16-bit
arithmetic, an 8-bit microcomputer has to operate on each byte separately. Here is how it is
done. With Appendix 1, we have

18,357 47B5H 0100 0111 1011 0101

12,618 314AH 0011 0001 0100 1010

The 2s complement of 12,618 is

12,618 CEB6H l100 1110 1011 0110

The addition is carried out in two steps of 8-bit arithmetic. First, the lower bytes are added:

1011 0101

+ 1011 0110

1 0110 1011 X8X7X6X5X4X3X2X1X0

The computer will store X7 X0. The carry X8 is used in the addition of the upper bytes.

Now, the computer adds the upper bytes plus the carry as follows:

0100 0111

+ 1100 1110

1 0001 0110 0001 0110

To obtain the final answer, the two 8-bit answers are combined:

0001 0110 0110 1011

Notice that the MSB is 0, which means that the answer is positive. we can convert this

answer to decimal form:

0001 0110 0110 1011 166BH +5739

TI7 Design a 8 bt adder/subtractor by emplying full adders and EX-OR gates? Summarize your
ideas and present?

Ans
 Here is how an addition appears:

During an addition, the SUB signal is deliberately kept in the low state. Therefore, the binary
number B7B0 passes through the controlled inverter with no change. The full-adders then
produce the correct output sum. They do this by adding the bits in each column, passing
carries to the next higher column, and so on. For instance, starting at the LSB, the full-adder
adds A0, B0, and SUB. This produces a SUM of S0 and a CARRY OUT to the next-higher full-
adder. The next-higher full-adder then adds A1, B1, and the CARRY IN to produce S1 and a
CARRY OUT. A similar addition occurs for each of the remaining full-adders, and the correct
sum appears at the output lines.

During a subtraction, the SUB signal is deliberately put into the high state. Therefore, the
controlled inverter produces the ls complement of B7 B0. When A7 A0 = 0, the circuit
produces the 2s complement of B7B0 because 1 is being added to the ls complement
B7B0. When A7A0 does not equal zero, the effect is equivalent to adding A7A0 and the
2s complement of B7 B0.

TI8 Show how final carry is generated for a parallel adder when two numbers added are A:

1111 and B: 0001.

Ans First it calculates, Gi and Pi parallely.

G0 = 1.1 = 1, G1 = 1.0 = 0, G2 = 1.0 = 0, G3 = 1.0 = 0.

and P0 = 1 + 1 = 1, P1 = 1 + 0 = 1, P2 = 1 + 0 = 1, P3 = 1 + 0 = 1. Note that C1 = 0.

Then substituting these in equation of C3 we get final carry as

C3 = G3 + P3G2 + P3P2.G1 + P3 P2P1.G0 + P3P2P1P0.C1

= 0 + 1.0 + 1.1.0 + 1.1.1.1 + 1.1.1.1.0

=0+0+0+1+0

=1

Test/Assessment Items for C301.3

Course Outcome POs/PSOs CL KC

Understand the concept of sequential circuits and
C301.3 PO1,PO2, U,
constructional details of Flip-flops and design one flip-flop from F,C,P,FDC
PSO1 AP
any other flip-flop by including suitable combinational circuits

TI1 Differentiate between Latch and a flip-flop?

Ans.
Latch
A latch is an electronic sequential logic
circuit used to store information in an
asynchronous arrangement.
One latch can store one bit information, but
output state changes only in response to
data input.
Flip Flop
A flip-flop is an electronic sequential logic
circuit used to store information in an
synchronous arrangement. It has two stable
states and maintains its states for an
indefinite period until a trigger pulse is
applied.
One flip-flop can store one bit data, but
output state changes with trigger pulse only.
 Latch is an asynchronous device and it has Flip-flop has clock input and its output is
no clock input synchronized with clock pulse.
Latch holds a bit value and it remains Flip-flop holds a bit value and it remains
constant until new inputs force it to change. constant until a trigger pulse is received.
Latches are level-sensitive and the output Flip-flops are edge-sensitive. They can store
tracks the input when the level is high. the input only when there is either a rising or
Therefore as long as the level is logic level 1, falling edge of the clock.
the output can change if the input
changes.
Write the output of a clocked S-R flip-flop when the inputs are R = 011001 and S = 101100.
TI2
Assume initially Q is low.

Ans.

The output of S-R flip-flop Qn+1 is shown in Table. Initial output Qn is 0. If S = 1, R = 0, Qn = 0 and
first clock pulse is applied, the next state output Qn+1 will be 1. When S = 0, R = 1, Qn = 1 and
second clock pulse is applied, the next state output will be 0. In the same way, remaining next
state outputs with respect to clock pulse can be justified using truth table of S-R flip-flop.
Draw the output waveform of J-K master slave flip-flop with the following inputs as shown
TI3
below:

Ans.

TI4 Convert T flip-flop into J-K flip-flop

The truth table of conversion from T flip-flop to J-K flip-flop is shown in Table. Using this table,
Ans.
the logical expression of T (J, K, Qn) can be derived from K-map as given in Fig.. Here, T is
T(J,K,Qn) = J Qn + KQn. The implementation conversion of T to J-K flip-flop using logic
expression T(J,K,Qn) = JQn +KQn is shown.
Test/Assessment Items for C301.4

Course Outcome POs/PSOs CL KC

Understand the concepts of registers and different types of PO1,PO2 R,U F,C
C301.4
registers and differentiate between asynchronous and
synchronous counters

TI1 Illustrate the basic sequential circuit representation?

Ans.

TI2 Draw the waveform of 4-bit SIPO register, when input data is 1010?

Ans.

TI3 List few applications of shift registers?

Ans.
Timing circuits to produce time delay,

Shift register counters: Ring counter and Johnson counter,

Serial to parallel converters,

Parallel to serial converters,

Sequence generators

TI4 Differentiate between asynchronous and synchronous counters?

Asynchronous (Ripple) Counters: In asynchronous counter, the external clock pulse clocks the
Ans.
first flip-flop. Then, the output of first flip-flop (Q or Q) is connected as clock of the next flip-
flop. Similarly, each successive flip-flop is clocked by the Q or Q of the previous one. All flip-
flops do not change states in exact synchronism with the applied clock pulses. There is some
propagation delay between responses of successive flip-flops. The asynchronous counter is
also called as ripple counter due to the way of flip-flop response one after another in a kind of
rippling effect. The maximum clock frequency of an asynchronous counter decreases with the
increase of number of flip-flops or bits. Asynchronous counter can generate glitches in
decoding gates due to propagation delays. Therefore, strobing technique should be used for
eliminating the effects of glitches.
Synchronous Counters: In synchronous counter, the clock input terminals of all flip-flops are
commonly connected. Therefore, the same clock pulse simultaneously triggers all flip-flops of
the counters and the problem caused by the flip-flop propagation delay has been eliminated
in these counters. For a synchronous counter, the maximum frequency remains same,
regardless of the number of bits.

Test/Assessment Items for C301.5

Course Outcome POs/PSOs CL KC

Design various types of counters by using registers PO1,PO2 AP P,FDC
C301.5
TI1 Design a 3-bit asynchronous UP-DOWN counter?
In certain applications, a counter must be able to count both up and down. Figure 6. shows
Ans
the 3-bit up-down counter. It counts up or down depending on the status of the control signals
UP and DOWN. When the UP input is at 1 and the DOWN input is at 0, the NAND network
between FF0 and FF1 will gate the non-inverted output (Q) of FF0 into the clock input of FF1.
Similarly, Q of FF1 will be gated through the other NAND network into the clock input of FF2.
Thus, the counter will count in UP direction. The functional table of 3-bit up counter is shown in
Table.

TI2 How a 4-bit asynchronous counter can count 0000 to 1100?

Figure shows the 4-bit asynchronous counter to count 0000 to 1100 and its timing diagram is
Ans.
depicted in other figure. When the counter has reached 1100, the output of AND gate reset
all flip-flops. Therefore, the counter again starts counting from 0000.

TI3 The waveform of 3-bit synchronous binary UP/DOWN counter is shown in Fig. Determine the
sequence of counter?

Ans.

TI4 Enumerate the design steps for a synchronous counter?

Step-1 Define the counting sequence of counter and draw the state diagram of the counter.
Ans.
Step-2 Develop a truth table of the counter with present sate and next state.
 Step-3 The unused state of the counter should be tabulated in the present state and the next
state should be initial count value. But, in practice, the unused states of the counter do not
shown in flip-flop excitation table.
Step-4 Select T or D or J-K or R-S flip-flops for design a counter and find the number of flip-flops
considering the expression 2n m, where n is the number of flip-flops and m is the number of
counting sequence.
Step-5 Draw the K-maps for all flip-flop inputs.
Step-6 Derive the simplified expression for all flip-flop inputs.
Step-7 The implementation circuit diagram of counter with flip-flops and logic gates.

TI5 Design a MOD-5 synchronous counter?

The counting sequence of mod-5 counter is 0, 1, 2, 3, 4,0, 1, 2 and Table shows the counting
Ans.
sequence of mod-5 counter. The state diagram of mod-5 counter is given.

To design this counter, three flip-flops are required and all flip-flops are connected with a
common clock pulse. To generate the counting sequence, flip-flop inputs are given in flip-flop
excitation table as per Table.

The initial state of flip-flop FF0 is 0 and its output will be changed to 1 after applying clock
pulse. For that reason, J0 must be 1 and K0 must be 0 or 1 (X).
The initial state of flip-flop FF1 is 0 and its output will not be unchanged after the clock pulse
and consequently J1 will be 0 and K1 will be 0 or 1 (X).
The state of FF2 does not changed after the first clock pulse and therefore, J2 will be 0 and K2
will be 0 or 1 (X). The other input states of FF0, FF1 and FF2 to develop the sequence are
depicted in Table.
The Karnaugh map for J0, K0, J1, K1, J2, and K2 are shown in Fig. respectively. The simplified
expressions for all flip-flops inputs are J0 = A, K0 =1, J1=C, K1=C, J2=BC, and K2=1.

Figure shows the implementation of mod-5 counter using flip-flops and logic gates.

Test/Assessment Items for C301.6

 Course Outcome POs/PSOs CL KC
Understand the design procedure of designing synchronous PO2,PSO1 U F,C,P,FDC
C301.6
and asynchronous sequential circuits

TI1 Enumerate the design procedure for synchronous sequential circuits?

Step-1 Define the problem with specification.
Ans.
Step 2 Draw a block diagram for the proposed design with all the inputs and the required
outputs.
Step-3 Make a state transition diagram from the specification. Generally, this is the most
difficult part of any sequential circuit design.
Setp-4 Using the state diagram, construct a state table and check for redundant states.
Step-5 Rebuild the state diagram if redundancy has occurred.
Step-6 Make a state assignment.
Step-7 Draw a new state table after removing all redundancies and using the state
assignment.
Step-8 Select the flip-flops D or T or J-K which one will be used in memory elements.
Step-9 Derive the excitation equations for the next state inputs to the selected flip-flops with
the help of the reduced state table. Derive the output equations of sequential circuit.
Step-10 Implement the excitation equations and the output equations with the help of logic
gates and flip-flops.

TI2 Enumerate the design procedure for asynchronous sequential circuits?

Step-1 Define the problem with proper specification.
Ans.
Step-2 Draw a block diagram for the proposed design with mention all the inputs and outputs.
Step-3 Draw a state transition diagram from the specification.
Step-4 Draw state table and state transition table.
Step-5 Plot the K -map for next state variables and outputs using present state variables and
other inputs.
Step-6 Derive the Boolean expressions for the excitation variables and outputs as a function of
the input and secondary variables.
Step-7 Implement the excitation equations and the output equations with the help of logic
gates.

TI3 Explain about state table, state diagram and state equation with suitable illustrations?
The time diagram of inputs, outputs and flip-flops states of sequence circuits may be listed in a
Ans.
state table. For the analysis and design of sequential circuits, it is necessary to describe the
state transitions of a state machine in a present state, next state and output table. In this table
all possible combinations of inputs and present states, and the corresponding next state and
output for each combination are listed in tabular form.

The most convenient method to describe any sequential circuit or finite state machine is a
state transition diagram. This is a graphical approach of representing how the finite state
machine changes from one state to another state. This is also used to depict the output
generated by the finite state machine. When the information available in the state table is
represented by graphical form, the diagram is known as state diagram or state transition
diagram. The state transition diagram contains the same information about the transitions of a
state machine which is represented in tabular form. Each row of the table is directly
represented in the state diagram by considering the inputs and present state to determine the
next state and output.
 The state equation of a sequential circuit is a Boolean expression which represents the
conditions of flip-flop state transition. The state equation can be derived directly from the
state table. For example, to design the sequential circuit as per Table 7.3, the next state of the
flip-flop must be derived from inputs, and present state. From the next state columns of State
Table, we observe that the flip-flop A changes its state four times: when X = 0 and AB = 01 or
10 or 11 and when X = 1 and AB = 10. Assume the state of a sequential circuit is known at a
time t0, and the inputs are known from time t0 to time t1, then the state of the sequential
circuit can be derived at t1. The change of state can be expressed algebraically in a state
equation as follows:

TI4 How state reduction can be achieved in a synchronous sequential circuit?

Ans. Usually synchronous sequential circuits are represented by state table and state diagram.
When the state table is directly used to implement the sequential circuit, more hardware is
required. To reduce the hardware requirement, the sequential circuit must be optimized by
state reduction. There are three different methods of state reduction to find equivalent states
of any specified state table. These methods are inspection, partitioning and implication table.
The method of state reducing using inspection is already explained in Section 7.7. In this
method, the two states Sm and Sn will be equivalent if and only if, each possible input
sequence produces identical output sequence irrespective of initial state whether Sm or Sn.
For this, all possible input sequences are represented in tabular from incorporating all
corresponding output sequences of the sequential circuit. This method will be very tedious
when the circuit consists of large number of input signals and very large number of states.
Consequently, the other two methods, such as partitioning and implication table are used as
these methods are simple and non-tedious for state reduction. In this section, portioning and
implication table methods of state reduction are discussed with examples.
Partitioning

Implication Table
The last method of state reduction is implication table. Table 7.26 shows a state table of a
typical sequential circuit. The implication table may be constructed by listing all the states
vertically except the first one and all the states horizontally except the last one. Figure 7.26
shows the implication table of state Table 7.26. The implication table represents all possible
combinations of state pairs and each cell of implication table is used as the testing ground for
equivalent of a state pair. For example, the first down left-hand cell at the intersection of S0
and S7 is the place where these two states are test for equivalence.
Test/Assessment Items for C301.7

Course Outcome POs/PSOs CL KC

Design both asynchronous and synchronous sequential PSO1 AN P,FDC,C&S,
C301.7
circuits for any given specification PC
Design a sequential circuit (finite state machine) for Table using D flip-flops. Assume two inputs
TI1
are A and B, outputs of the sequential circuit are outputs of D flip-flops, present state =S, Next
State=S*. Consider the four states of the sequential circuit are S0=00, S1=01, S2=10 and S3=11.

After substituting the following four states S000, S101, S210, and S311 in given table, we
Ans.
get the state transition Table.

As the state information is two bits, two flip-flops are required. Q1 and Q0 are the output
signals of two flip-flops. Then present state of flip-flops are Q1 and Q0 and the next state of flip-
flops are Q1* and Q0*. When the memory element of the sequential circuit (finite state
machine) is implemented with D-type flip-flops, then the excitation table of the D flip-flops is
shown in Table.
TI2 Design an asynchronous sequential circuit for the state diagram as shown in Fig? Consider four
states S0=00, S1=01, S2=10 and S3=11. Assume two inputs A and B and one output O.

Ans. The state table of state diagram as shown in Fig. is given in Table.

The K-map the state table is shown in Fig.

Then derive the excitation functions and output equation are as follows
Targets for CO Attainment

CO Course Outcomes Target

(Class
Average
Marks)

Understand the operations of basic logic gates and importance of Boolean

C301.1
algebra in optimizing the circuit complexity and apply the Boolean laws and
70
theorems, mapping techniques and tabulation techniques in simplifying the
logic expressions
Understand the concepts of multiplexing, demultiplexing, decoding,
C301.2
encoding, parity generation and checking and magnitude comparators
65
and apply the concepts of basic combinational circuits to design medium
complex arithmetic circuits
Understand the concept of sequential circuits and constructional details of
C301.3
SR, JK,D and T Flip-flops and design one flip-flop from any other flip-flop by 65
including suitable combinational circuits
Understand the concepts of registers and different types of registers and
C301.4 70
differentiate between asynchronous and synchronous counters
Design various types of counters by using registers
C301.5 65

Understand the design procedure of designing synchronous and

C301.6 65
asynchronous sequential circuits
Design both asynchronous and synchronous sequential circuits for any given
C301.7 65
specification
Assessment Pattern

Assessment Instrument Percentage Weightage

Continuous Internal Assessment 40%

Semester End examination 60%

Continuous Internal Assessment

Assessment Instrument Weightage

CIA test-1 15%

CIA test-2 15%

Term Examination 20%

Assignment 1 12.5%

Quiz 12.5%

Technical Essay writing 12.5%

Mini Project 12.5%

Semester End examination

Assessment Instrument Weightage

Semester End Examination

Part A (10 x 2 marks) 20%

Part B (5 x 16 marks) 80%

Cognitive Term
CIA 1 CIA2 SEE
Level Examination

Remember 30 30 20 20

Understand 40 40 40 40

Apply 30 30 20 20

Analyze - - 20 20

Evaluate - - - -

Create - - - -
Item Bank Structure

CO. CL Class Wt. to CO Items distribution in a 1000 item bank

Sessions
(100*CS/TS)
(approx.) R U AP AN E C

C301.1 U,AP 9 20 0 0 0 0

C301.2 R,U,AP 9 20 0 0 0

C301.3 U,AP 9 20 0 0 0 0

C301.4 R,U 5 11 0 0 0 0

C301.5 AP 4 09 0 0 0 0 0

C301.6 U 4 09 0 0 0 0 0

C301.7 AN 5 11 0 0 0 0 0

Total 45 100 0 0 0

Item Bank structure including the marks distribution

Proposed item distribution as per marks
CO R U AP AN E C

C301.1 0 0 0 0

C301.2 0 0 0

C301.3 0 0 0 0

C301.4 0 0 0

C301.5 0 0 0 0

C301.6 0 0 0 0

C301.7 0 0 0

Total 0 0

Item Bank

Item

Time in Difficulty
CO CL KC Marks
Min. Level
Understand the operations of basic logic gates
and importance of Boolean algebra in
optimizing the circuit complexity and apply the U
F 20 36 2
Boolean laws and theorems, mapping AP
techniques and tabulation techniques in
simplifying the logic expressions
Understand the concepts of basic R,U F,C,P,
20 36 2
combinational circuits and apply the learned AP FDC
 concepts to design medium complex
arithmetic circuits
Understand the concept of sequential circuits
and constructional details of Flip-flops and U F,C,P,
20 36 2
design one flip-flop from any other flip-flop by AP FDC
including suitable combinational circuits
Understand the concepts of registers and
different types of registers and differentiate
R,U F,C 10 18 1
between asynchronous and synchronous
counters
Design various types of counters by using
AP P,FDC 10 18 3
registers
Understand the design procedure of designing
F,C,P,
synchronous and asynchronous sequential U 08 15 1
FDC
circuits
Design both asynchronous and synchronous P,FDC,
AN 12 21 3
sequential circuits for any given specification C&S, PC
*3- Difficult; 2-Moderate; 1-Easy

DEVELOPMENT

Instruction and Learning Material

Delivery Technologies:

S No. Delivery Technology

1. Classroom with LCD Projector and smart board
2. Group activity
3. Annotated lectures
4. Glossary talk
5. Assignment presentation
6. Technical essay Writing

Instructional Plan

No. of hours
S No. IU Competency
of Instruction
Understand the operations of AND,OR & NOT logic gates and
C1 IU1 4
importance of Boolean algebra in optimizing the circuit complexity
Apply the Boolean laws and theorems, Karnaugh map techniques
C2 IU2 5
and Quine Mc-clusky method in simplifying the logic expressions
Understand the concepts of multiplexing, demultiplexing, decoding,
C3
IU3 encoding, parity generation and checking and magnitude 3
comparators.
Recall the basic arithmetic operations on binary numbers in true and
C4 IU4 2
complimentary forms
Apply the concepts of basic combinational circuits to design half
C5 IU5 4
adder, full adder, adder-subtractor, fast adders and ALU
Understand the concept of sequential circuits and constructional
C6 IU6 5
details of SR, JK,D and T Flip-flops
Design one flip-flop from any other flip-flop by including suitable
C7 IU7 4
combinational circuits
Understand the concepts of registers and different types of shift
C8 IU8 2
registers such as SISO,SIPO,PISO and PIPO
 Identify the types of counters and differentiate between
C9 IU9 4
asynchronous and synchronous counters
Design asynchronous counters, synchronous up counter,
C10
IU10 synchronous down counter, synchronous up-down counter, MOD n 3
counters D, T and JK flip-flops
Understand the sequential circuit model
C11 IU11 1

Prepare state table, state diagram and state equation for the given
C12 IU12 2
specification
Design synchronous sequential circuits for any given specification
C13 IU13 2
using design procedure
Understand the design procedure of designing asynchronous
C14 IU14 2
sequential circuits
Design asynchronous sequential circuits for any given specification
C15 IU15 2
by using state transition diagram