178

Switched-Opamp, a Technique for Realising full CMOS

Switched-Capacitor Filters at Very Low Voltages
M. Steyaert, J. Crois and S. Gogaert
K.ULeuven, ESAT-MICAS, Kardinaal Mercierlaan 94, 3001 Heverlee, Belgium

Abstract : Existing design techniques for very low voltage (1.5 V) switched-capacitor
filters need the on-chip generation of clock-signals with a higher voltage to drive the MOS-
switches. Here a novel technique for the realisation of low voltage switched-capacitor
filters in CMOS technologies is introduced which uses clock signals with voltages equal to
the power supply. This new technique is called switched-opamp because it replaces some
critical switches in a classic biquad structure by opamps which are turned on and off. A
2nd order lowpass switched-capacitor filter has been implemented and is discussed. This
filter operates at only 1.5 V power supply and has a total harmonic distortion of -60 dB
with a signal swing of 550 mVptp. It is realised in a 2.4 pm CMOS process with Vt =
0.9 V.
I. Introduction
Devices which are meant to be used in battery operated applications must often be able to
work at very low supply voltages. The use of a switched-capacitor filter is very attractive when
an integrated filter is needed in these devices. Switched-capacitor filters have a very high filter
accuracy and even at low supply voltages the distortion is relatively low. However, the signal
swing that can be applied in these filters reduces dramatically when a very low power supply
voltage is used (< 2.5 V).
At this moment basically two techniques are available for the realisation of switched-
capacitor filters at very low power supply voltages with an acceptable voltage swing. The first
one uses special low voltage technologies with extra low threshold MOS devices [1]. The most
common used technique is however the use of on-chip generation of clock-signals on a higher
voltage [2], [3], [4]. This technique has the advantage that there is no need for a special process,
but the disadvantage is that it needs additional circuitry for the on-chip voltage multiplication
[5], [6]. This circuitry takes a lot of silicon area and has a high power consumption. Both are
indispensable in battery operated applications.
In this paper the realisation of a 2nd order lowpass switched-capacitor filter using a totally
new technique, called switched-opamp, is presented. The switched-opamp technique is suited
for the realisation of low frequency, high performance, switched-capacitor filters at very low
power supply voltages without the need for a special process or on-chip voltage multiplication.
It features low distortion at large voltage swings. Even rail-to-rail operation is possible when
VTn or Vjp is smaler than (Vdd-300 mV)/2. The presented filter is a lowpass biquad clocked at
115 kHz and it has a cut-off frequency of 1.5 kHz. The power supply voltage and the clock
signals are all entirely at 1.5 V. The filter shows a total harmonic distortion of -60 dB when a
voltage swing of 550 mVptp is applied. A 2.4 |m n-well CMOS process with Vt = 0.9 V is
used.
II. The Switched-Opamp Technique
Fig. 1 shows a switched-capacitor inverting integrator, the basic building block of a
switched-capacitor filter. Typically the switches are complementary driven nMOS and pMOS
transistors. In [7] it is shown that at very low power supply voltages it is pointless to use
complementary switches. Therefore single transistor switches are used in switched-capacitor
filters for very low voltage applications. nMOS devices are preferred because they have a better
conductivity than pMOS devices and because in almost all processes Vfn is smaller than, or at
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least equal to, Vjp. The voltage swing (VSw) which can be applied to the integrator in fig. 1 is
limited by the minimal necessary conductivity for the switches (gmin)- This minimal
conductivity is given by speed considerations [7] and must be maintained for all possible input
signals (from Vref-Vsw/2 to Vref+Vsw/2). For switch 1 the lowest conductivity appears when
the input signal is equal to Vref + VSw/2 and this determines the maximum swing :
VV sw =1/Y dd _yV Dsat _i/-ms_
Tn (\)
W \U
KP-
L
n

In this expression VTri is a function of VSw due to the bulk effect VDsat is the lower limit for
the input signal set by the output swing of the OTA and it determines the position of Vref. For
switches 2, 3 and 4 expression (1) does not hold because the source of these devices is always at
least Vref or lower. The result is that the voltage swing can be doubled if switch 1 is eliminated.
Vsw=2-(Vdd-VDsat-VTn-Say)
KP-
(2)
.

n
L
The switched-opamp technique is based on this principle and on the use of nMOS switches
which are not minimum size. The W/L of the switches is chosen such that the last term in (2) is
about as large as a VDsat (150 mV). In this case W/L is chosen to be 10. Not using minimum
size transistors normally results in large clock feedthrough. But because the clock signal
voltages are very low here, this effect is limited.
In a switched-capacitor filter the inputs of all the integrators except the first one are driven
by the outputs of other integrators. The switched-opamp technique starts from the principle that
the switch at the input of an integrator (switch 1) can be eliminated if the OTA from the
preceding integrator can be switched off during the phases in which switch 1 should be open.
When the OTA is switched off it can not drive any current into capacitor Ci and this is equal to
disconnecting the OTA from Ci by means of switch 1. Fig. 2 shows the complete scheme of a
switched-opamp lowpass biquad. A switched-opamp integrator can not integrate a charge on its
capacitor C2 in one phase and drive the succeeding integrator in another phase. Both
integration and driving must be done in the same phase because in the other phase the OTA is
not working. Therefore a switched-opamp non-inverting amplifier must be added everywhere
integrating and driving must be done in a different phase. Amplifier 2 is such an amplifier.
These amplifiers must be non-inverting because an inverting amplifier does not introduce a
delay. In this way it is possible to realise the most common filter structures : cascaded biquads
and ladder; lowpass, bandpass and highpass.
The switch transistor at the input of the filter can not be replaced by a switched-opamp
because it is not preceded by one. Two input structures were implemented. The first one still
uses a switch clocked at a higher voltage and is shown in fig. 2. The second structure is a true
complete very low voltage solution. It is represented in fig. 3. The input switch and capacitor
are replaced by a large external resistor, making the input current driven. The drawback is that
the accuracy of the filter amplification depends on the accuracy of the RC time constant.
III. Design of a Switched-Opamp
In fig. 4 the topology of the switched-opamp is presented. It is a two stage Miller
compensated opamp which can be switched on and off by means of transistors 9 and 10. Both
switches are necessary to obtain the required speed. The bias currents are switched off with
transistor 10. Transistor 9 makes sure that Cc can not be discharged by transistor 6 once the bias
currents are switched off. Recharging Cc when the opamp is turned on again would take to long.
The input transistors (1 and 2) are pMOS. When nMOS switches are used this is a
necessity unless VTn < Vdd/2-Vosat- In the latter case Vref can be put at half the power supply
voltage allowing the use of nMOS input transistors and rail-to-rail operation. The pMOS input
transistors can be used in weak inversion. The reference voltage can then be higher resulting in
a higher voltage swing. Here VgS of transistors 1 and 2 is equal
possible Vref
for to be put Vdd-Vjp, making (2)
at the
Vjp-150 mV. This makes it
boundary for the maximum voltage
swing.
180

IV. Experimental Results

The implemented filter is a lowpass biquad clocked at 115 kHz with a cut-off frequency of
1.5 kHz. It is realised in a 2.4 im n-well CMOS technology with Vt's equal to 0.9 V. Fig. 5
depicts the measured transfer function of the filter. The predicted swing at a power supply
voltage of 1.5 V is, according to (2), 550 mVptp.Fig. 6 is a plot of the measured distortion
versus the signal swing. THD is less then -60 dB when a signal swing of 550
Fig. displays
7 the distortion in function of the clock speed. photograph
A of the
mVptp
is applied.
cnip given in
is
fig. 8. The equivalent input noise is 140|iVrms> a dynamic range of about 69 dB, the power
consumption is 35 |iA per pole and the chip area is 0.57 mm^ per pole.
V. Acknowledgements
The authors wish to thank S. Gierkink for his contribution to the realisation of the chip.
VI. References
1] T. Adachi, A. Ishinawa, A. Barlow and K. Takasuka, "A 1.4 V switched capacitor filter," Proc. CICC
(Boston), pp.8.2.1-8.2.4, May 1990.
2] R. Castello and L. Tomasini, "1.5-V High-performance SC filters in BiCMOS technology," IEEE J. ofSolid-
State Circuits, Vol. SC-26, no. 7, pp.930-936, July 1991.
3] F. Calias, F. H. Salchi and D. Girard, "A set of four IC's in CMOS technology for a programmable hearing
aid," IEEEJ. of Solid-State Circuits, vol. SC-20, no. 2, pp.301-312, April 1989.
4] R. Becker and J. Mulder, "SIGFRED: A low-power DTMF and signalling frequency detector," Proc.
ESSCIRC (Grenoble), pp.5-8, Sept.. 1990.
5] J. Dickson, "On-chip high-voltage generation in MNOS integrated circuits using an improved voltage
multiplier technique," IEEE J. of Solid-State Circuits, Vol. SC-11, pp.374-378, June 1978.
6] B. Gerber, J. C. Martin and J. Fellrath, "A 1.5 V single-supply one-transistor CMOS EEPROM," IEEE J. of
Solid-State Circuits, vol. SC-16, no. 3, p.195,1981.
7] M. Steyaert, J. Crois, S. Gogaert and W. Sansen, "Low-voltage analog CMOS filter design," IEEE Proc.
ISCAS (Chicago), Session 65.3, May 1993.

Fig. 1 : Switched-capacitor inverting integrator

 181

c8

Vin
Hill 4 "
w

Fig. 2 : The structure of a switched-opamp lowpass biquad

MO ipfl >>-|| Ml
|p-4J M7
?
||H.'.? F.
SW
y-
-
Ml Ml
Cc
1
ei'
2
M6

M4 M
Jl Clock

Fig. 3 : Input structure with resistor Fig. 4 : Topology of the switched-opamp

2 3 4 S 6 7 '
2 0.2 0.4 0.6 0.8 1.0
10' 10* 10 Signal swing [Vptp]
Freq (Hz)
Fig. 5 : Frequency response of the filter Fig. 6 : Distortion versus signal swing

25 SO 75 100 125 150 175 200

Clock frequency (kHz]
Fig. 7 : Distortion versus clock speed Fig. 8 : Chip photograph