Universitt Duisburg-Essen

PRACTICAL TRAINING
TO THE LECTURE

FCE 1

Experiment 3

Flip-flops,
Design of a counter

Name: Matriculation-Number:

First Name: Group-Number:

Tutor: Date:

All questions marked with Q1 to Qn must be answered before the lab begins.
All tasks marked with T1 till Tn must be completed to finish the lab.

Prof. Dr.Ing. Axel Hunger

Dipl.Ing. Joachim Zumbrgel
Universitt Duisburg-Essen
Faculty of Engineering, Department Electrical Engineering and Information Technology
Computer Engineering

Copyright (C) Computer Engineering

FCE1 Lab Experiment 3: Flip-flops, Design of a counter

Introduction
In the preceding experiments you learned how to simulate and analyze simple logical circuits.
The most important functions of OrCAD Capture were introduced and applied. The acquired
knowledge should now be used to understand the basics of flip-flops, digital counting and
combinatorial circuits. All the logic circuits we have worked on so far are purely
"combinatorial" circuits, also called switching networks. These kinds of circuits consist only
of pure logic gates without feedback, what means the output signals of switching networks are
always only dependent on the current input signals.
In contrast, "sequential" circuits are circuits whose output signals are no longer exclusively
dependent on the input signals of the circuit, but also on the internal states of the circuit.
These, in turn, depend on the "sequence" of the preceding input signals. But if we want to
keep inner states, this means that we have to be able to "store" states. Memory devices fulfill
this requirement.
Memory devices can be divided into the asynchronous and synchronous elements. The main
difference is that asynchronous memory devices can change their state at any time, while
synchronous memory devices can only change their state at specific time intervals or at
specific times. Synchronous memory devices therefore have a clock line (CLK).

1. Flip-flops (FFs)
Flip-flops are the most common and basic memory devices used for information storage in
sequential circuits. A flip-flop can stay in one of two logical states. To change its state we
need a new input signal. This makes the flip-flop a 1 bit memory device.
In case of clocked FFs, a distinction is made between the clock-state-controlled FF and the
clock-edge-controlled FF. Clock-controlled FFs are also called latches and are distinguished
by the fact that during the active clock phase (eg. high signal), any change in the input
immediately switches to the output. On the other hand, in the case of the clock-edge-controlled
FF, the output is only changed during a clock edge (ie, when switching from 0-> 1 and / or
from 1-> 0).You can find all flip-flops in the 74LS.OLB and 7400.OLB libraries.

1.1 Reset Set (RS) Flip-flop

Before explaining the different types of flip-flops, we will briefly discuss the RS flip-flop and
explain the meaning of state control and the signals preset and clear.
A simple memory flip-flop is the RS FF (a.k.a SR FF). This device has two inputs - S for
setting and R for resetting the flip-flop (hence its name). The RS flip-flop preserves its states
as long as the inputs S and R are 0. If it receives a set signal, it turns to 1, regardless of its
former state. A reset signal enforces a 0 state. This behavior is illustrated by the truth table
below (Qn is the preceding state of Qn+1).

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FCE1 Lab Experiment 3: Flip-flops, Design of a counter

S R Qn Qn+1 Functionality

0 0 0 Both inputs are 0,

0 0 1 1 the state is preserved
0 1 0 0 The reset input is 1,
0 1 1 0 the FF is set to 0
1 0 0 1 The set input is 1,
1 0 1 1 the FF is set to 1
1 1 0 X Both inputs are 1, the FFs
1 1 1 X behavior cannot be predicted

Table 1.1.1: Truth table for RS flip-flop

The most common realizations of RS FFs are based on NOR or NAND gates. Fig. 1.1.1 shows
a typical NOR-gate core circuit of an RS FF and Fig. 1.1.2 shows its gate symbol. Take notice
that flip-flops usually provide the complement of their state as a second output Q n .

Q
S Q

__
R Q
Q

Fig. 1.1.1: Core of a NOR-gate RS FF Fig. 1.1.2

Fig. 1.1.3 and Fig. 1.1.4 respectively, illustrate the gate circuit and gate symbol of a NAND
type RS FF with clock state control.
The signals at S and R only affect the circuit when a positive level is present at the CLK input
(CLK = 1). In order in order to set the FF output in a well defined state the low active inputs
signal CLR (Clear) und PRE (Preset) can be used asynchronous (what means regardless of
the clock signal state).
When CLR = 0, PRE = 1, so Q = 0, when CLR = 1, PRE = 0 so Q = 1. CLR and PRE =
0 has to be avoided because it leads to Q = = 1 , which is, on the one hand, illogical with
regard to the names of the outputs, but can also lead to unpredictable subsequent states. With
CLR = 1 and PRE = 1, the circuit operates as a clock state-controlled RS-FF.

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 FCE1 Lab Experiment 3: Flip-flops, Design of a counter

___
PRE
Q ____
S PRE Q

CLK
__ ___
Q R CLR Q

___
CLR
Fig. 1.1.4
Fig. 1.1.3: clock-state-controlled RS FF with pre-set and clear

1.2 Delay (D) Flip-flop

The RS FF presented in the previous section has a serious disadvantage. For an RS FF one
input combination is not allowed. The JK FF is a modified RS FF (J corresponds to the set and
K to the reset input), which inverts its state when the input J = 1 and K = 1 occurs. Since it has
no forbidden input combinations, the JK FF can be easily used to generate other types of flip-
flops. Table 1.2.1 compares the four most common types of flip-flops. The CLR X in the truth
table means that you have to prevent input states for J and K, which lead to an indeterminate
n+1
state of Q .

Inputs Qn Qn+1

J K JK-FF RS-FF D-FF T-FF

0 0 0 0 0 X 0

0 0 1 1 1 X 1

0 1 0 0 0 0 X

0 1 1 0 0 0 X

1 0 0 1 1 1 X

1 0 1 1 1 1 X

1 1 0 1 X X 1

1 1 1 0 X X 0

Table 1.2.1

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FCE1 Lab Experiment 3: Flip-flops, Design of a counter

n +1 n n
The characteristic equations for the JK FF is Q = K Q + J Q . We can derive from the

truth table (Table 1.2.1) the equations and inputs of other flip-flop types, which can be
construct from JK FF.

1.3 Delay (D) Flip-flop

As the name implies the purpose of a D FF is to temporary store (or delay) a single bit. A
signal of 0 or 1 present at the input D is transferred to the output Q whenever the clock CLK is
set to 1. Fig. 1.3.1 shows the gate symbol of a D flip-flop.
If we look closely at the truth table (Table 1.2.1) again we will see that it is quite simple to
construct a D FF out of a JK FF. A delay flip-flop uses only the situations where the J and K
inputs are different. This would make a D FF truth table only 2 lines. So how can we get rid of
the other two lines in a JK FF truth table? We make sure they do not occur by connecting a
NOT gate between the inputs J and K, as shown in Fig. 1.3.2. This way J and K will always be
different.

D Q D J Q

CLK CLK

Q K Q

Fig. 1.3.1 Fig. 1.3.2

As the construct in Fig. 1.3.2 implies, the equation for a D FF built from JK FF would be:
D=J =K

1.4 Trigger (T) Flip-flop

If we take a look at our truth table (Table 1.2.1) again, we will see that a trigger flip-flop is
just a JK FF in disguise. Fig. 1.4.1 shows the gate symbol of a T FF built from a JK FF merely
by connecting its J and K terminals together.

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FCE1 Lab Experiment 3: Flip-flops, Design of a counter

The characteristic equations for the T FF can be

T J Q n+1 n
obtained form the truth table: Q = T Q .
CLK For a T FF to be built from a JK FF:
n+1 n
T = J = K, if T = 1 the output Q =Q , meaning
K Q
that it will toggle between 0 and 1 with every clock
Fig. 1.4.1 impulse. One of the T FF properties is that its output
signal runs at half the frequency of the input.

Q1: Fig. 1.1 illustrates two flip-flops. Which flip-flop functions as a D FF and why?

Fig. 1.1

Q2: Which state is forbidden for RS FF?

Q3: Which input signals would reset and set an RS FF?

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FCE1 Lab Experiment 3: Flip-flops, Design of a counter

Q4: Some flip-flops have additional inputs, such as clear and pre-set. What function do these
inputs serve?

Q5: What is the characteristic equation of a D flip-flop?

2. Registers
A register is a circuit that can store whole data words. It is constructed by connecting several
flip-flops; hence an n-bit register consists of at least n flip-flops. The following example
shown in Fig. 2.1 illustrates a 4-bit shift register built with D flip-flops.

Fig. 2.1

Q6: Define a series of input impulses D to store the pattern (D3 D2 D1 D0) = (1010) into the
4-bit register illustrated in Fig. 2.1.

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FCE1 Lab Experiment 3: Flip-flops, Design of a counter

Q7: Give two examples of where a register can be applied.

Q8: How would you modify the circuit in Fig. 2.1 in order to turn it into a ring-register?
Explain your answer and add your modifications to the figure.

3. Designing a counter
Before we knew flip-flops we could only design combinatorial circuits. The output of a
combinational circuit depends on the current input signal only. If X n are the inputs of such
circuit at cycle n, the characteristic equation is of the type:
Qn = f ( X n )
The output of a circuit containing flip-flops depends not only on the current input, but on the
previous inputs as well, making it a sequential circuit. Therefore, the according characteristic
equation must match:
Q n = f ( X n , Q n1 )
One of the most typical applications for sequential circuits is counters. In this part of the
experiment we want to design a counter that has no inputs apart from the clock pulse.
Therefore, the circuits state will depend only on the preceding state:
Q n = f (Q n1 )

3.1 5-3-2-1 code counter

We want to design a counter that counts the sequence 0,1,9 (decimal) automatically, thus it
has to be:
Counting up - The value of the current input cycle is higher than the preceding one.
If the actual output is 9 the counter should restart to 0
Auto-run - The counter starts automatically when powered on
Synchronous - All FFs in the counter are triggered by the same clock pulse
The numbers are to be coded in a 5-3-2-1 binary code. We use four JK flip-flops, each one
representing one digit of the binary code according to the truth table below (Table 3.1.1).

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FCE1 Lab Experiment 3: Flip-flops, Design of a counter

Decimal Value of the Bit 5 3 2 1

Decimal numbers
Q4 Q3 Q2 Q1
(Counter state)

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 1 0 0

4 0 1 0 1

5 1 0 0 0

6 1 0 0 1

7 1 0 1 0

8 1 1 0 0

9 1 1 0 1

Table 3.1.1

A 5-3-2-1 code is just another 4-bit binary code, but with different decimal values assigned to
each bit.
Example:
Decimal number: 7
4-bit binary code: 0111 = 023 + 122 + 121 + 120 = 7
4-bit 5-3-2-1 code: 1010 = 15 + 03 + 12 + 01 = 7

3.2 Designing the counter circuit

To design a counter out of 4 flip-flops we have to find out how we should connect them to one
n+1
another, so that they match the truth table (Table 3.1.1). Therefore, for the output Qa of a
flip-flop we search the equation:
n+1 n n n n
Qa = f (Qa , Qb , Qc , Qd )

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FCE1 Lab Experiment 3: Flip-flops, Design of a counter

As the JK flip-flops behavior is described by

Q n + 1 = K Q n + J Q n
a a a
we have to find by comparison the equations for the inputs J and K for every flip-flop:

J a = f (Qb , Qc , Qd ) K a = f (Qb , Qc , Qd )
For this task we set up a KV-diagram representing the formerly given truth table (Table 3.1.1).

Q9: Complete the KV-diagram of the 5-3-2-1 code:

Q2

X
Q1

Q3

8 3

2 7

Q4
Fig. 3.2.1: KV-diagram of a 5-3-2-1 code

For every flip-flop we follow the steps:

1. List all counter states Z n for which the following state Z n +1 contains Qan +1 = 1 for the
corresponding flip-flop.
n +1 n n n n
2. Read the simplified functions Qa = f (Qa , Qb , Qc , Qd ) from the KV-Diagram in Q9.
n+1
3. Deduce the equations for Ja and Ka by comparing the function of Qa with the flip-
flops characteristic equation.

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FCE1 Lab Experiment 3: Flip-flops, Design of a counter

As an example we will derive the equations for J3 and K3:

n +1 n +1
1. Q3 = 1 occurs for the counter states ( Z n +1 ) 3, 4, 8 and 9. Thus, Q3 must be set, for
the preceding counter states ( Z n ) 2, 3, 7 and 8.
2. From the truth table we can read the disjunctive normal form expression of Q3n +1 for
the counter states 2, 3, 7 and 8 or we could directly deduce the simplified expression
for Q3n +1 from the KV-diagram in question Q9 as:
n n n n n n
Q3n +1 = Q1 Q2 Q3 + Q1 Q2 Q3
3. Comparing the equation from step 2 with the characteristic equation of a JK-FF for
n +1 n n
Q3 = K Q 3 + J Q 3 , we find the equations for J3 and K3:

J 3 = Q1n Q 2n and K 3 = Q1n Q 2n , thus K 3 = Q1n + Q 2n

Be aware that when looking for a simplified expression for Qan+1 we have to find one that
contains Qan to be able to compare coefficients!

Following this principle the equations for J1, K1 and J2, K2 are:
n +1
Q1 = Q1 Q2 (follows if we consider the previous states 0,3,5,8)

J1 = Q2

K1 = K1 = 0 K1 = 1

Q2n+1 = Q1 Q2 Q3 (follows if we consider the previous states 1,6)

J2 = Q1 Q3

K2 = K2 = 0 K2 = 1

Q10: Find the functions for the inputs J4, K4 of the fourth flip-flop. Do not make use of the
Dont care states!

Q4n+1 =
J4 =
K4 =

Q11: Is it possible to simplify the expressions for J and K even further? If yes, how?

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FCE1 Lab Experiment 3: Flip-flops, Design of a counter

Q12: Complete the circuit in Fig. 3.2.2 using the equations for K3 , J4 und K4.

Fig. 3.2.2: 5-3-2-1 Counter

Q13: What is the difference between a synchronous and asynchronous counter? Which type of
counter is the circuit in Fig. 3.2.2? Explain your answer.

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 FCE1 Lab Experiment 3: Flip-flops, Design of a counter

4. Controlling a 7-segment display

To see whether our 5-3-2-1 counter is working correctly we connect it to a 7-segment display.
This display is composed of an array of 7 LEDs (Light Emitting Diodes) as illustrated in Fig.
4.1. Now we should design a controller that connects the outputs of the counter to the 7-
segment display in such a way that the actual numbers are displayed. A segment is on when it
is triggered with a logical 0. An unrecognized input (a signal representing none of the
numbers from 0 to 9) should cause the controller to turn all segments on.

S1 S1 S1 S1 S1
S3

S3

S3

S3

S3
S2

S2

S2

S2

S2
S1
S4 S4 S4 S4 S4
S5

S5

S5
S6

S6

S6

S6

S6
S5

S5
S3

S2

S7 S7 S7 S7 S7
S4
S1 S1 S1 S1 S1
S5
S6

S3

S3

S3

S3
S2

S2

S2

S3

S2
S2
S4 S4 S4 S4 S4
S7
S5

S5

S5

S5

S5
S6

S6

S6

S6

S6
S7 S7 S7 S7 S7

Fig. 4.1
Q14: Complete the truth table shown below:

Number Q4 Q3 Q2 Q1 S7 S6 S5 S4 S3 S2 S1

0 0 0 0 0 0 0 0 1 0 0 0
1 0 0 0 1 1 0 1 1 0 1
2 0 0 1 0 0 1 0 1 0 0
3 0 1 0 0 1 0 0 1 0 0
4 0 1 0 1 1 0 0 0 0 1
5 1 0 0 0 1 0 0 0 1 0
6 1 0 0 1 0 0 0 0 1 1
7 1 0 1 0 1 0 1 1 0 0
8 1 1 0 0 0 0 0 0 0 0
9 1 1 0 1 1 0 0 0 0 0
Table 4.1: Truth table for the 7-segment-display controller

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FCE1 Lab Experiment 3: Flip-flops, Design of a counter

From the truth table we get the equations for S1,...,S6 in disjunctive normal form:

S1= (Q1 Q 2 Q 3 Q 4 ) + (Q1 Q 2 Q3 Q 4 ) + (Q1 Q 2 Q 3Q4 )

S2= (Q1 Q 2 Q 3Q4 ) + (Q1 Q 2 Q 3Q4 )

S3= (Q1 Q 2 Q 3 Q 4 ) + (Q1Q2 Q 3 Q 4 ) + (Q1 Q 2Q3 Q 4 ) + (Q1Q2 Q 3Q4 )

S4= (Q 1 Q 2 Q 3 Q 4 ) + (Q1 Q 2 Q 3 Q 4 ) + (Q1Q2 Q 3Q4 )

S5= (Q 1Q2 Q 3 Q 4 )

S6= (Q1 Q 2 Q 3 Q 4 ) + (Q1 Q 2 Q3 Q 4 ) + (Q1 Q 2 Q3 Q 4 ) + (Q1 Q 2 Q 3Q4 ) + (Q1Q2 Q 3Q4 ) + (Q1 Q 2 Q3Q4 )

Q15: Write down the disjunctive normal form for S7.

S7=_________________________________________________________________

Simplifying the functions for S1,...,S6 (with KV-Diagramms and boolean Algebra) leads to:

S1= (Q1 Q 2 Q 4 ) + (Q1 Q 2 Q 3 ) = Q1 Q 2 (Q 3 + Q 4 )

S2= (Q 2 Q 3Q4 )

S3= Q1 Q 2 Q 3 Q 4 + Q1 Q 2Q3 Q 4 + Q1Q2 Q 3 = Q 2 Q 4 (Q1 Q3 ) + (Q1Q2 Q 3 )

S4= (Q 2 Q 3 Q 4 ) + (Q1Q2 Q 3Q4 )

S5= (Q 1Q2 Q 3 Q 4 )

S6= Q 2 Q 4Q1 + Q 2 Q 4Q3 + Q1 Q 2Q3 + Q1 Q 3Q4 = Q 2 Q 4 (Q1 + Q3 ) + Q1 Q 2Q3 + Q1 Q 3Q4

Q16: Simplify the functions for S7 from Q15 with the help of KV-diagrams and write down
the simplified equation.

S7=_________________________________________________________________

Q17: Complete the circuit for the display controller (see next page)!

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FCE1 Lab Experiment 3: Flip-flops, Design of a counter

Fig. 4.2

Fig. 4.2 15/19

FCE1 Lab Experiment 3: Flip-flops, Design of a counter

5. Introduction to hierarchical blocks

When we design more complex circuits with lots of elements we often come across the same
problems: keeping track of the circuit connections becomes impossible; we often have to keep
re-making the same sections of circuits which are used several times.
To aid us in our work, OrCAD offers the generation of hierarchical circuit blocks. Hierarchical
blocks refer to circuits grouped together, which are defined as a part to place in the Schematic
Page Window. These hierarchical blocks can carry different circuit designs between schematic
folders as long as they are in the same design.

5.1 Placing hierarchical ports

You place hierarchical ports on the schematic page where the circuit you plan on grouping as a
hierarchical block is. Then you name the ports so that they connect to like-named hierarchical
pins inside the hierarchical block. Ports are usually setup for the inputs and outputs of a
particular circuit.
To place a hierarchical port, navigate to Place Hierarchical Port, after which the Place
Hierarchical Port dialog box should appear.
Select the Capsym.olb library. In the list of parts select the type of the hierarchical port you
require and type in the name for the port. The name is added to the attached net, and is used to
determine which like-named hierarchical pins the port connects to. When you have specified
the characteristics of the hierarchical port, click OK. You can now place and connect the
hierarchical port anywhere on the schematic page like an ordinary part.

5.2 Placing Hierarchical blocks

Hierarchical blocks represent child schematic folders and when you create a hierarchical
block, you specify the name of the child schematic page that the hierarchical block represents.
To place a hierarchical block, after you have designed your circuit and placed the ports,
choose Place Hierarchical Block from the editors menu or choose the hierarchical block
tool from the tool palette. The Place Hierarchical Block dialog box should appear as
illustrated in Fig. 5.2.1.
In the Reference text box, type the name of the
schematic page you want your hierarchical block to
refer to. Accept the Primitive setting as Default and
specify the type of implementation, pointing out what
exactly you want to implement with this hierarchical
block. In our practice we will deal with schematics,
so for Implementation Type choose Schematic View.
The Implementation name field is now active. In it
write the name of the schematic folder, which
contains the schematic page you specified in the
Reference field.

Fig. 5.2.1: Place Hierarchical Block

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FCE1 Lab Experiment 3: Flip-flops, Design of a counter

Click OK to close the Place Hierarchical Block dialog box. Now you can draw the hierarchical
block using the mouse by pressing the left button and dragging the mouse to draw a rectangle.
If you have entered the names of the schematic page and folder correctly then your block
should appear with already set-up pins and pin names.

6. Design and simulation of the counter and display controller

6.1 Implementing the sequential circuit

T1: Create a new Analog or Mixed A/D project named Lab2. Rename SCEMATIC1 to Lab2
and PAGE1 to Lab2Circuit. This will be your complete circuit schematic page and folder.

T2: Create a new schematic folder and name it Counter. In it create a new schematic page
named CounterCircuit. Create the circuit you drew in question Q12 (Fig. 3.2.2) in the
CounterCircuit schematic page and place, and name ports at the inputs and outputs.

T3: Create a hierarchical block in the Lab2Circuit schematic page, which refers to your
counter circuit.

T4: Create and run a simulation of the hierarchical block counter with an appropriate input to
test its functionality.

6.2 Implementing the combinatory circuit

T5: Create a new schematic folder named Controller and a new schematic page in it, named
ControllerCircuit.

T6: Design the 7-segment-display controller from Q17 (Fig. 4.2) in the ControllerCircuit
schematic page and place, and name ports at the inputs and outputs.

T7: Create a hierarchical block in the Lab2Circuit schematic page, which refers to your
controller circuit. Connect the controller hierarchical block to the counter one.

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FCE1 Lab Experiment 3: Flip-flops, Design of a counter

6.3 Simulating the complete circuit

Fig. 6.3.1 shows how individual components are connected to realize the complete circuit.

Fig. 6.3.1: Complete circuit

T8: Create and run a simulation with an appropriate input to test the functionality of both
blocks.

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FCE1 Lab Experiment 3: Flip-flops, Design of a counter

Digital Components

Symbol-Name Type-Number Library

NOT 7404 7400

AND
7408 7400
2-Input
AND
7411 7400
3-Input
NAND
7400 7400
2-Input
NAND
7410 7400
3-Input
NAND
7420 7400
4-Input
OR
7432 7400
2-Input
NOR
7402 7400
2-Input
NOR
7427 7400
3-Input
XOR 7486 7400
JK-FF
7473 7400
with CLR
JK-FF
7476 7400
with PRE/CLR
JK-FF
74107 7400
with CLR
JK-FF
74109 7400
with PRE/CLR
D-FF
7474 7400
with PRE/CLR
D-FF 7474 7400
D-TYPE
74LS173A 74ls
REGISTER
REGISTER
74170 7400
FILE O.C.
PRESETTABLE
74LS197 74ls
BINARY COUNTER
7493A
BINARY
74293 7400
COUNTER
74177

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