Professional Documents
Culture Documents
discussions, stats, and author profiles for this publication at: https://www.researchgate.net/publication/294580407
CITATIONS READS
0 1,794
1 author:
E.A. Vittoz
Institute of Electrical and Electronics Engineers
175 PUBLICATIONS 6,351 CITATIONS
SEE PROFILE
All content following this page was uploaded by E.A. Vittoz on 15 February 2016.
The user has requested enhancement of the downloaded file. All in-text references underlined in blue are added to the original document
and are linked to publications on ResearchGate, letting you access and read them immediately.
Analog Layout Techniques
Eric A.Vittoz
evittoz@ieee.org
MOS transistors.
CMOS compatible bipolars.
Resistors and capacitors.
Control of absolute values.
Matching.
Parasitic effects.
Long-range coupling.
E. Vittoz, 2015
Analog Layout Techniques
LA-1
INTRODUCTION
signals electrical
represented by: processing with:
numbers
DIGITAL (codes) regeneration
E. Vittoz, 2015
Analog Layout Techniques
LA-2
TRANSISTOR LAYOUT
G L = Lm + L
minimum size poly Si metal
Wm W = Wm + W
given by layout rules S D
mask drawing
contact window Lm n+ diffusion electrical
D D
G Wm Wm Lm
Lm G
min. diffusion min. S and D resistance
S areas S
G
long S D
Wm
Lm
E. Vittoz, 2015
Analog Layout Techniques
LA-3
VERY WIDE TRANSISTORS
W
Lm
D
G
G D
contacts to metal all along the fingers
E. Vittoz, 2015
Analog Layout Techniques
LA-4
VERY WIDE TRANSISTORS FOR RF OR LOW-NOISE
Lfinger
S
G can be reduced if many
metal layers
E. Vittoz, 2015
Analog Layout Techniques
LA-5
CLOSED TRANSISTOR STRUCTURES
Maximum /Drain-junction area
No side of channel (lower leakage and/or noise)
S
G D
G
S
Large W/L per area
Low S,G,D series resistance
E. Vittoz, 2015
Analog Layout Techniques
LA-6
Serpentine structure
L W
Wm
S G
E. Vittoz, 2015
Analog Layout Techniques
Lm
Wm resistive
layer L
end uncertainty
contact resistance may be folding uncertainty
non-negligible
E. Vittoz, 2015
Analog Layout Techniques
LA-9
CAPACITORS
Inter-layer capacitors (vertical field):
layer 1
compensation layer 2
tab Wm
area depends on alignement
Lm
clearance larger than
maximum mask misalign
Intra-layer capacitors (lateral field):
applicable when the electrode thickness is larger than the feature size.
d1
electrode 1 d1, d2: minimum
same layer
electrode 2 d2
LA-11
MATCHING OF DEVICES
LA-12
MATCHING: SAME TEMPERATURE
LA-13
MATCHING: SAME SHAPE, SAME SIZE
Examples:
Resistors Transistors Capacitors
(4 squares) (W/L=2) (area A)
A Reference
A Good
A Bad
E. Vittoz, 2015
Analog Layout Techniques
LA-14
MATCHING: MINIMUM DISTANCE
Example:
A B C D
A B C D
E. Vittoz, 2015
Analog Layout Techniques
LA-15
MATCHING: COMMON-CENTROID GEOMETRIES
For compensation of constant gradients
Best solution: "quad" of similar devices grouped in two pairs
Principle Example for a pair of transistors
D1
G2
1/2 1/2
device 2 device 1
1/2 1/2
device 1 device 2 S
G1
D2
Simpler solution
D1 D2
1/2 1/2 1/2 1/2
dev.2 dev.1 dev.1 dev.2
S G1 G2
Does not respect rule 7 (same surroundings)
E. Vittoz, 2015
Analog Layout Techniques
LA-16
MATCHING: SAME ORIENTATION
D2 D1 D2
D1 D1 D2 D1 D2
S
S S S
z
L L L
W y W W
device 1 ideal device: Xs xs device 2
+: area WL
and relative mismatch: (WL1)/(WL1) = W/W L/L
: ratio W/L
(WL1) 1 1 1 1 1
Thus: 1
2 + 2 = +
WL W L L W WL L W
Minimum for a square shape
E. Vittoz, 2015
Analog Layout Techniques
LA-20
MATCHING FOR NON UNITY RATIOS
Rational ratios n/m with m and n integers
use m+n identical devices
matching rules can be respected
example: ratio of capacitors C1/C2 = 3.5 =7/2
almost common centroid C2
compensation tabs:- non aligned
- aligned to connect
C1
dummy structure for homogeneous etching
E. Vittoz, 2015
Analog Layout Techniques
LA-22
LONG-RANGE COUPLING
E. Vittoz, 2015
Analog Layout Techniques
LA-23
RESISTIVE COUPLING THROUGH SUBSTRATE
direct connection capacitive bipolar
V V I=IC
I CV
I=
p+ n+ p+
p p p
n
coupling to substrate
r1 Rr1,r2 r2
coupling from substrate:
r1 r2
Solutions: V2
direct connection
I
minimize d1 and d2 R
substrate modulation.
maximize D capacitive (drain, pad, bottom
p layer on grounded p+substrate plate of capa)
put critical zones in (or on) special wells
e.g.: capacitors on special grounded well.
E. Vittoz, 2015
Analog Layout Techniques
LA-24
CAPACITIVE COUPLING THROUGH AIR
distance D
noisy area A1 sensitive area A2
C12C2 C12
V1 V2 V1
C2
silicon substrate (ground) C2
A1 and/or A2:
diffusion (drains) 0A1A2
2
If D A1 and A2, then: C12 =
interconnections 3
2D
pads
Numerical examples (for 120dB attenuation):
A1 [m2] A2 [m2] C2 [fF] C12max [F] Dmin [m]
10 10 5 5.10-21 30
10000 10 5 5.10-21 300
10000 10000 100 100.10-21 1120
Possible improvements:
reduce A1 and/or A2
increase distance D
shield A1 and/or A2.
E. Vittoz, 2015
Analog Layout Techniques
LA-25
COUPLING BY MINORITY CARRIERS
E. Vittoz, 2015
Analog Layout Techniques
REFERENCES
1. J . L. McCreary, "Matching properties, and voltage and temperature dependence of MOS capacitors", IEEE Journal of
Solid-State Circuits, vol. SC-16, pp.608-616, Dec. 1981.
2. J. B. Shyu et al., "Random errors in MOS capacitors", IEEE Journal of Solid-State Circuits, vol. SC-17, pp.1070-1076,
Dec.1982
3. J. B. Shyu et al, "Random errors effects in matched MOS capacitors and current sources"", IEEE Journal of Solid-State
Circuits, vol.-19, pp.948-955, Dec.1984.
4. E. A. Vittoz, "The design of high-performance analog circuits on digital CMOS chips", IEEE Journal of Solid-State
Circuits, vol. SC-20, June 1985
5. K. R. Lakshmikumar et al., "Characterization and modeling of mismach in MOS transistors for precision analog design",
IEEE Journal of Solid-State Circuits, vol. SC-21, pp.1057-1066, Dec.1986.
6. M. Pelgrom et al.,"Matching properties of MOS transistors", IEEE Journal of Solid-State Circuits, vol. 24, pp.1433-1440,
Oct.1989.
7. B. R. Stanisic et al.,"Addressing substrate coupling in mixed-mode IC's: simulation and power distribution synthesis",
March 1994.
8. M. J. McNutt et al.,"Systematic capacitance matching errors and corrective layout procedures", IEEE Journal of Solid-
State Circuits, vol. 29, pp.611-616, May 1994.
9. J. D. Bruce et al.,"Analog layout using ALAS", IEEE Journal of Solid-State Circuits, vol. 31, pp.271-274, Febr. 1996.
10. H. Samavati et al.,"Fractal capacitors", IEEE Journal of Solid-State Circuits, vol. 33, Dec. 1998.
11. K. Okada et al.,Layout dependent matching analysis in CMOS circuits", Analog Integrated Circuits and Signal Processing,
vol.25, pp.309-318, Dec. 2000.