Digital design

Combinational circuits
 Combinational circuits
Combinational logic symbols
Common combinational logic systems have standard symbols called
logic gates
A B A*B A+B
Buffer, NOT
0 0 0 0
0 1 0 1
1 0 0 1
AND, NAND 1 1 1 1

OR, NOR Easy to implement

with CMOS transistors
(the switches we have
available and use most)
 Combinational logic symbols(Cont.)

X Y Z
0 0 1
NAND X
Z 0 1 1
Y 1 0 1
1 1 0
X Y Z
NOR X
0
0
0
1
1
0
Z
Y 1 0 0
1 1 0

XOR X X Y Z
X xor Y = X Y' + X' Y
0 0 0
X Y Y Z
0 1 1 X or Y but not both
1 0 1 ("inequality", "difference")
1 1 0
XNOR X
Y Z X Y Z X xnor Y = X Y + X' Y'
X=Y 0 0 1 X and Y are the same
0 1 0
1 0 0 ("equality", "coincidence")
1 1 1
 Example : two-bit comparator
A B C D LT EQ GT
0 0 0 0 0 1 0
0 1 1 0 0
1 0 1 0 0
N1 A LT AB<CD 1 1 1 0 0
B 0 1 0 0 0 0 1
EQ AB=CD
C 0 1 0 1 0
N2 GT AB>CD 1 0 1 0 0
D
1 1 1 0 0
1 0 0 0 0 0 1
0 1 0 0 1
1 0 0 1 0
1 1 1 0 0
block diagram 1 1 0 0 0 0 1
and 0 1 0 0 1
truth table 1 0 0 0 1
1 1 0 1 0

we'll need a 4-variable Karnaugh map

for each of the 3 output functions
 Example : two-bit comparator(Cont.)

A B C D

two alternative
implementations of EQ
with and without XOR

EQ

XNOR is implemented with

at least 3 simple gates
EQ
 Example: 2x2-bit multiplier

A2 A1 B2 B1 P8 P4 P2 P1
0 0 0 0 0 0 0 0
0 1 0 0 0 0
1 0 0 0 0 0
1 1 0 0 0 0
A1 P1 0 1 0 0 0 0 0 0
A2 2x2-bit P2 0 1 0 0 0 1
1 0 0 0 1 0
B1 multiplier P4 1 1 0 0 1 1
B2 P8 1 0 0 0 0 0 0 0
0 1 0 0 1 0
1 0 0 1 0 0
1 1 0 1 1 0
1 1 0 0 0 0 0 0
block diagram 0 1 0 0 1 1
and 1 0 0 1 1 0
truth table 1 1 1 0 0 1

4-variable K-map
for each of the 4
output functions
 Example : BCD increment by 1

I8 I4 I2 I1 O8 O4 O2 O1
0 0 0 0 0 0 0 1
0 0 0 1 0 0 1 0
0 0 1 0 0 0 1 1
0 0 1 1 0 1 0 0
I1 O1 0 1 0 0 0 1 0 1
0 1 0 1 0 1 1 0
I2 BCD O2 0 1 1 0 0 1 1 1
I4
increment
O4 0 1 1 1 1 0 0 0
by 1 1 0 0 0 1 0 0 1
I8 O8 1 0 0 1 0 0 0 0
1 0 1 0 X X X X
1 0 1 1 X X X X
1 1 0 0 X X X X
1 1 0 1 X X X X
block diagram 1 1 1 0 X X X X
and 1 1 1 1 X X X X
truth table
4-variable K-map for each of
the 4 output functions
 Making connections
Direct point-to-point connections between gates
Wires we've seen so far
Route one of many inputs to a single output ---
multiplexer
Route a single input to one of many outputs ---
demultiplexer

control control

multiplexer demultiplexer 4x4 switch

 Making connections(Cont.)
Mux and de-mux
Switch implementation of multiplexers and de-
multiplexers
Can be composed to make arbitrary size switching networks
Used to implement multiple-source/multiple-destination
interconnections

A Y

B Z

A Y

B Z
 Making connections(Cont.)
Mux and de-mux (Cont.)
Uses of multiplexers/de-multiplexers in multi-
point connections
A0 A1 B0 B1

MUX Sa MUX Sb multiple input sources

A B

Sum

Ss DEMUX multiple output destinations

S0 S1
 Multiplexers/Selectors
Multiplexers/Selectors: general concept
2n data inputs, n control inputs (called "selects"), 1 output
Used to connect 2n points to a single point
Control signal pattern forms binary index of input connected
to output

A Z I1 I0 A Z
0 I0 0 0 0 0
Z = A' I0 + A I1 0 0 1 0
1 I1
0 1 0 1
0 1 1 0
1 0 0 0
functional form 1 0 1 1
logical form 1 1 0 1
1 1 1 1
two alternative forms
for a 2:1 Mux truth table
 Multiplexers/Selectors(Cont.)

A B

S
I0
I1
C I2
I3 8:1
I0 I4 Z
mux
I1 4:1 I5
I0 2:1 I2 Z
mux I6
I1 Z
mux I3 I7

A A B A B C
A31:0 B31:0

C
 Multiplexers/Selectors(Cont.)
Gate level implementation of muxes

2:1 mux

4:1 mux
 Multiplexers/Selectors(Cont.)
Cascading multiplexers
alternative
implementation
I0 2:1 8:1
I1 mux mux
8:1
I0 I2
I1 4:1 mux 2:1
I3 mux
I2 mux 4:1
I3 Z
2:1 I4 mux
Z 2:1
mux I5 mux
I4
I5 4:1
I6 2:1
I6 mux
I7 mux
I7

B C A C A B
 Multiplexers/Selectors(Cont.)
Multiplexers as general-purpose logic
Example:
1 0
F(A,B,C) = m0 + m2 + m6 + m7 0 1
1 2
= A'B'C' + A'BC' + ABC' + ABC 0 3
0 4 8:1 MUX F
= A'B'(C') + A'B(C') + AB'(0) + 0 5
1 6
AB(1) 1 7
S2 S1 S0
Example :
F(A,B,C) = m0 + m2 + m6 + m7 A B C
= A'B'C' + A'BC' + ABC' + ABC
1 0
0 1
= A'B'(C') + A'B(C') + AB'(0) + AB(1)
1 2
0 3 A B C F
0 4 8:1 MUX 0 0 0 1 C'
0 0 1 0 C' 0
0 5 F
F 0 1 0 1 C' 1 4:1 MUX
1 6 C'
0 1 1 0 0 2
1 7
1 0 0 0 1 3 S1 S0
S2 S1 S0 0
1 0 1 0
1 1 0 1 1 A B
A B C 1 1 1 1
 Multiplexers/Selectors(Cont.)
Multiplexers as general-purpose logic(Cont.)
Generalization

I0 I1 . . . In-1 In F
. . . . 0 0 0 1 1 four possible
n-1 mux control configurations
variables . . . . 1 0 1 0 1 of truth table rows
single mux data can be expressed
variable as a function of In
0 In In' 1

Example: F(A,B,C,D) implemented by an 8:1

MUX A 1
D
0
1
1 0 1 1 0 2
choose A,B,C as control variables 1 3
1 0 0 0 D 4 8:1 MUX
D D 5
multiplexer implementation D 6
1 1 0 1
D 7
C
S2 S1 S0
0 1 1 0
B
A B C
 De-multiplexers/Decoders
Decoders/de-multiplexers: general concept
Single data input, n control inputs, 2n outputs

N inputs 2N outputs

Decoder

Enable

Control inputs (called selects (S)) represent binary index of

output to which the input is connected 3:8 Decoder:
Data input usually called enable (G) O0 = G S2 S1 S0
O1 = G S2 S1 S0
O2 = G S2 S1 S0
2:4 Decoder: O3 = G S2 S1 S0
O0 = G S1 S0 O4 = G S2 S1 S0
1:2 Decoder: O1 = G S1 S0 O5 = G S2 S1 S0
O0 = G S O2 = G S1 S0 O6 = G S2 S1 S0
O1 = G S O3 = G S1 S0 O7 = G S2 S1 S0
 De-multiplexers/Decoders(Cont.)
Gate level implementation of de-multiplexers
1:2 Decoders
active-high active-low
enable enable
G O0 \G O0
S S
O1 O1
2:4 Decoders
G \G O0
O0
active-high active-low
enable O1 enable O1

O2 O2

O3 O3

S1 S0 S1 S0
 De-multiplexers/Decoders(Cont.)
Cascading decoders

0 A'B'C'D'E' 0
1 1
2 2 A'BC'DE'
3:8 DEC3 3:8 DEC3
4 4
5 5
6 6
7 7
S2 S1 S0 S2 S1 S0
0
F 2:4 DEC 1
2
S1 S0 3
0 0 AB'C'D'E'
A B 1 1
2 2
3:8 DEC3 3:8 DEC 3
4 4
5 5
6 6
7 ABCDE 7 AB'CDE
S2 S1 S0 S2 S1 S0

C D E C D E

5:32 DEC
 De-multiplexers/Decoders(Cont.)
De-multiplexers as general-purpose logic
0 A'B'C'
1 A'B'C
2 A'BC' demultiplexer generates appropriate
3 A'BC minterm based on control signals
1 3:8 DEC 4 (it "decodes" control signals)
AB'C'
5 AB'C
6 ABC'
7 ABC 0 A'B'C'D'
S2 S1 S0 1 A'B'C'D
2 A'B'CD' F1
3 A'B'CD
A B C 4 A'BC'D'
5 A'BC'D
Example 6 A'BCD'
4:16 7 A'BCD
Enable
-F1 = A' B C' D + DEC 8
9
AB'C'D'
AB'C'D
F2

A' B' C D + A B C D 10 AB'CD'

11 AB'CD
-F2 = A B C' D + A B C 12 ABC'D'
13 ABC'D
-F3 = (A' + B' + C' + D') 14 ABCD'
15 ABCD F3

A B C D
Combinational circuit analysis
 Tri-state gates
Third value
Logic values: 0, 1
Don't care: X (must be 0 or 1 in real circuit!)
Third value or state: Z high impedance, infinite R, no connection
Tri-state gates
OE
Additional input output enable (OE)
Output values are 0, 1, and Z In Out
When OE is high, the gate functions normally
When OE is low, the gate is disconnected from wire at output
Allows more than one gate to be connected to the same output wire
As long as only one has its output enabled at any one time (otherwise, sparks
could fly)
100
In OE Out
non-inverting X 0 Z In
tri-state 0 1 0 OE
buffer 1 1 1
Out
 Tri-state gates(Cont.)
Tri-state and multiplexing
When Using tri-state logic
(1) Never more than one "driver" for a wire at any one
time (pulling high and low at same time can severely
damage circuits)
(2) Only use value on wire when its being driven (using a
floating value may cause failures)
Using tri-state gates to Implement an economical
multiplexer
Input0 F
OE when Select is high
Input1 is connected to F
Input1 when Select is low
OE Input0 is connected to F

this is essentially a 2:1 mux

Mux
Select
 Tri-state gates(Cont.)
Bi-direction circuit

X Y

Bi-direction circuit
Open-collector gates and wired-AND
Open collector: another way to connect gate outputs to same wire
Gate only has the ability to pull its output low
Cannot actively drive wire high (default pulled high through resistor)
Wired-AND can be implemented with open collector logic
If A and B are "1", output is actively pulled low
If C and D are "1", output is actively pulled low
If one gate output is low and the other high, then low wins
If both outputs are "1", the wire value "floats", pulled high by resistor
Low to high transition usually slower than if gate pulling high
Hence, the two NAND functions are ANDed together

with ouputs wired together

open-collector
using "wired-AND"
NAND gates
to form (AB)'(CD)'
 Relationship among representations
Theorem: Any Boolean function that can be expressed as a truth table can be
written as an expression in Boolean Algebra using AND, OR, NOT.

unique
? Truth Table
not ?
unique
gate
Boolean not
representation
Expression unique
(schematic)
[convenient for [close to
manipulation] implementaton]

How do we convert from one to the other?

thanks
digital design