TASK 1

Objective:
Realization of the following circuits using VHDL
a) AND Gate
b) NAND Gate
c) XNOR Gate
d) D Flip flop
e) JK Flip flop

Requirement:
a) Simulation Software: Xilinx ISE
b) Programming Language: VHDL

Theory:
a) AND Gate:
A Logic circuit whose output is logic 1 if and only if all of its inputs are logic 1. AND operation is
done in AND gate. This operation is represented by a dot or by the absence of an operator. For example,
x y = z or xy = z is read x AND y is equal to z. The logical operation AND is interpreted to mean that
z = 1 if and only if x = 1 and y = 1; otherwise z = 0. The result of the operation x y is z.
Logic Diagram Truth Table

c = a AND b
= ab

b) NAND Gate:
A logic gate which gives logic 0 output if and only if all of its inputs are logic 1. It is just reversed
of AND Gate. The NAND Gate is said to be a universal gate because any logic circuit can be implemented
with it. A convenient way to implement a Boolean function with NAND gates is to obtain the simplified
Boolean function in terms of Boolean operations and then convert the function to NAND logic.
Logic Diagram Truth Table

C = a NAND b
= NOT (ab)

c) XNOR Gate:
A logic gate that produces a logic 1 only when the two inputs are equal.
Logic Diagram Truth Table

C = a XNOR b
= NOT (a (+) b)
= NOT (ab) + ab
d) D Flip Flop:
The D flip-flop is the most common flip-flop in use today. It is better known as delay flip-flop. The Q
output always takes on the state of the D input at the moment of a positive edge (or negative edge if the
clock input is active low). The D flip-flop can be interpreted as a primitive memory cell, zero-order hold,
or delay line. Whenever the clock pulses, the value of Qnext is D and Qprev otherwise.
Logic Diagram

e) JK Flip flop:
The JK flip flop augments the behaviour of the SR flip-flop (J = set, K= Reset) by interpreting the S =
R = 1 condition as a flip or toggle command. Specifically, the combination J = 1, K= 0 is a command to
set the flip-flop; the combination J = 0, K = 1 is a command to reset the flip-flop; and the combination J =
K =1 is a command to toggle the flip-flop, i.e., change its output to the logical complement of its current
value.
Logic Diagram Truth Table

Procedure:
1) New project was created using VHDL module.
2) Entity for the concerned circuit was defined.
3) Architecture for the entity was defined.
4) Any syntax error was checked.
5) Test Bench was used to observe the waveform for the circuit for different input cases.

VHDL Code and Result:

a) AND Gate:
----------------------------------------------------------------------------------
-- Company: NIT, Rourkela
-- Engineer: Bharat Chandra Sahu
--
-- Create Date: 15:05:52 03/01/2017
-- Design Name: And gate using VHDL
-- Module Name: AND_Gate - Behavioral
-- Project Name: VHDL Task-1
-- Target Devices:
-- Tool versions:
-- Description:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity AND_Gate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end AND_Gate;

architecture Behavioral of AND_Gate is

begin
c <= a and b ;

end Behavioral;

Test Bench Code for AND Gate:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY AND_Simulation IS
END AND_Simulation;

ARCHITECTURE behavior OF AND_Simulation IS

-- Component Declaration for the Unit Under Test (UUT)
COMPONENT AND_Gate
PORT(
a : IN std_logic;
b : IN std_logic;
c : OUT std_logic
);
END COMPONENT;

--Inputs
signal a : std_logic := '0';
signal b : std_logic := '0';
--Outputs
signal c : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: AND_Gate PORT MAP (
a => a,
b => b,
c => c
 );
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
a <= '0' ; b <= '0' ;
wait for 200 ns;
a <= '0' ; b <= '1' ;
wait for 200 ns;
a <= '1' ; b <= '0' ;
wait for 200 ns;
a <= '1' ; b <= '1' ;
wait for 200 ns;
wait;
end process;
END;

b) NAND Gate:
----------------------------------------------------------------------------------
-- Company: NIT, Rourkela
-- Engineer: Bharat Chandra Sahu
--
-- Create Date: 15:24:09 03/01/2017
-- Design Name: VHDL Code for NAND gate
-- Module Name: NAND_Gate - Behavioral
-- Project Name: VHDL Task-1
-- Target Devices:
-- Tool versions:
-- Description:
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity NAND_Gate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end NAND_Gate;
architecture Behavioral of NAND_Gate is
begin
c <= a nand b ;

end Behavioral;
 Test Bench:
begin
-- hold reset state for 100 ns.
a <= '0' ; b <= '0' ;
wait for 200 ns;
a <= '0' ; b <= '1' ;
wait for 200 ns;
a <= '1' ; b <= '0' ;
wait for 200 ns;
a <= '1' ; b <= '1' ;
wait for 200 ns;
wait;
end process;
END;

c) XNOR Gate:
----------------------------------------------------------------------------------
-- Company: NIT, Rourkela
-- Engineer: Bharat Chandra Sahu
--
-- Create Date: 15:44:50 03/01/2017
-- Design Name: VHDL Code for XNOR
-- Module Name: XNOR_Gate - Behavioral
-- Project Name: VHDL Task-1
-- Target Devices:
-- Tool versions:
-- Description:
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity XNOR_Gate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end XNOR_Gate;

architecture Behavioral of XNOR_Gate is

begin
c <= a xnor b ;
end Behavioral;

Test Bench:
 begin
-- hold reset state for 100 ns.
a <= '0' ; b <= '0' ;
wait for 200 ns;
a <= '0' ; b <= '1' ;
wait for 200 ns;
a <= '1' ; b <= '0' ;
wait for 200 ns;
a <= '1' ; b <= '1' ;
wait for 200 ns;
wait;
end process;
END;

d) D Flip-Flop:
----------------------------------------------------------------------------------
-- Company: NIT, Rourkela
-- Engineer: Bharat Chandra Sahu
--
-- Create Date: 15:53:31 03/01/2017
-- Design Name: D-Flipflop
-- Module Name: D_FlipFlop - Behavioral
-- Project Name: VHDL Task-1
-- Target Devices:
-- Tool versions:
-- Description:
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity D_FlipFlop is
Port ( d : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
Q : out STD_LOGIC;
Qb : out STD_LOGIC);
end D_FlipFlop;

architecture Behavioral of D_FlipFlop is

begin
process (clk, rst) begin
if (rst = '1' ) then
 Q <= '0' ;
Qb <= '1' ;
elsif (clk' event and clk = '1' ) then
Q <= d;
Qb<= not d;
end if;
end process;
end Behavioral;

Test Bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY D_flipflop_simulation IS
END D_flipflop_simulation;

ARCHITECTURE behavior OF D_flipflop_simulation IS

-- Component Declaration for the Unit Under Test (UUT)
COMPONENT D_FlipFlop
PORT(
d : IN std_logic;
clk : IN std_logic;
rst : IN std_logic;
Q : OUT std_logic;
Qb : OUT std_logic
);
END COMPONENT;

--Inputs
signal d : std_logic := '0';
signal clk : std_logic := '0';
signal rst : std_logic := '0';
--Outputs
signal Q : std_logic;
signal Qb : std_logic;
-- Clock period definitions
constant clk_period : time := 30 ns;
BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: D_FlipFlop PORT MAP (
d => d,
clk => clk,
rst => rst,
Q => Q,
Qb => Qb
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
 clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
d <= '0' ; rst <= '1' ;
wait for 100 ns;
d <= '0' ; rst <= '0' ;
wait for 100 ns;
d <= '1' ; rst <= '0' ;
wait for 100 ns;
d <= '0' ; rst <= '0' ;
wait for 100 ns;
d <= '1' ; rst <= '0' ;
wait for 100 ns;
d <= '1' ; rst <= '1' ;
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;

e) JK Flip-Flop:
----------------------------------------------------------------------------------
-- Company: NIT, Rourkela
-- Engineer: Bharat Chandra Sahu
--
-- Create Date: 16:33:02 03/01/2017
-- Design Name: JK FlipFlop
-- Module Name: jk12 - Behavioral
-- Project Name: VHDL Task-1
-- Target Devices:
-- Tool versions:
-- Description:
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity jk12 is
Port ( j : in STD_LOGIC;
k : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC;
qb : out STD_LOGIC);
end jk12;

architecture Behavioral of jk12 is

begin
PROCESS(clk)
variable TMP: std_logic;
begin
if(clk' event and clk = '1') then
if(j='0' and k='0')then
TMP:=TMP;
elsif(j='1' and k='1')then
TMP:= not TMP;
elsif(j='0' and k='1')then
TMP:='0';
else
TMP:='1';
end if;
end if;
q<=TMP;
qb <= not TMP;
end PROCESS;
end Behavioral;

Test Bench:
begin
-- hold reset state for 100 ns.
rst <= '0';
wait for 200 ns;
rst <= '1'; j<= '0'; k <= '0';
wait for 200 ns;
rst <= '1'; j<= '0'; k <= '1';
wait for 200 ns;
rst <= '1'; j<= '1'; k <= '0';
wait for 200 ns;
rst <= '1'; j<= '1'; k <= '1';
wait for 200 ns;

wait for clk_period*10;

-- insert stimulus here

wait;
end process;

END;
Conclusion:
Experiment was done successfully in Xilinx ISI using VHDL code and all the output of the given
circuits were checked and observed using isim simulator.