2012 IEEE 7th International Power Electronics and Motion Control Conference - ECCE Asia
June 2-5, 2012, Harbin, China
Design and Implementation of a Non-Destructive
Test Circuit for SiC-MOSFETs
Keiji Wada , Shin-ichi Nishizawa , and Hiromichi Ohashi
*Tokyo Metropolitan University, 1-1 Minami Osawa, Hachioji, Tokyo, JAPAN
**National Institute of Advanced Industrial Science and Technology(AIST), Ibaraki, JAPAN
AbstractSilicon carbide(SiC) power devices have been de-
veloped and they are sold in markets. Many papers have dealt
with inverter circuits that use SiC power devices to improving
eciency and realize high power density converters. However,
the power converters that use SiC power devices have not
become commercially available, because the reliability of the SiC-
MOSFET under switching-operation has not been suciently
discussed. This paper presents a non-destructive test circuit for
SiC-MOSFETs, and the experimental results have confirmed
the validity of the non-destructive test circuit for Si- and SiC-
MOSFETs. Moreover, the experimental results presents the
phenomenon just before destruction of the MOSFETs. The
purpose of the non-destructive test circuit is to evaluate the
extreme conditions under actual switching operation without
the destruction of the power devices. This paper shows exper-
imental results under short-circuit tests for Si super junction
MOSFETs (SJ-MOSFETs), and SiC double-diusion MOSFETs
(DMOSFETs). These experimental results will be analyzed to
improve the reliability of SiC power device. As a result, the short-
circuit switching operation of the SiC-MOSFET is observed to
be dierent from that of the Si-MOSFET.
IndexT erms Failure Mechanism, Non-Destructive Test Cir-
cuit, Short-Circuit Test, SiC-MOSFET.
I. Introduction
Si-MOSFETs are widely used in the field of home appliance
applications and a power supplies for information technology
equipment. Thus, the cost of the Si-MOSFETs is not so
expensive, and they have very high reliability. SiC(Silicon
Carbide) power devices have been developed and are commer-
cially available. Many papers have dealt with inverter circuits
that employ SiC power devices to improve eciency and
realize high power density converters. SiC-MOSFETs have
lower on-resistance and are available for higher temperature
operation than Si-MOSFET. The material properties of SiC
in power devices are superior to those of Si MOSFETs and
low-switching losses and high eciency converters have been
reported for SiC power devices. However, power converters,
such as PWM inverters and DC-DC converters that employ
SiC power devices, have not become commercially available,
because the reliability of the SiC-MOSFET under switching-
operation has never been suciently discussed. Data sheets
of MOSFETs represent only the device characteristics under a
rated voltage and current. Therefore, in order to improve the
reliability of the switching characteristics of SiC-MOSFET,it
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should be discussed under the extreme characteristics, such as
short-circuit conditions and high-temperature operations.
Refs. [1]-[6] have discussed short circuit failure mechanisms
of IGBT, and four type of the mechanisms are reported. In
addition, theoretical analysis based on temperature dependency
of device failure after turn o [2] are discussed. Refs. [7]-[11]
have proposed a non-destructive test circuit for MOSFETs and
IGBTs. The non-destructive test circuit is used to evaluate the
dynamic characteristics and undesirable oscillations of power
devices without destruction. These papers have been presented
a test circuit configuration and experimental results; however,
the circuit structures and measurement systems have never
been discussed in detail.
This paper presents a non-destructive test circuit for SiC-
MOSFETs. The switching speed of SiC power devices is faster
than that of the Si power devices, so that the non-destructive
test circuit has to operate with the high-speed switching.
Therefore, the stray inductance inside the non-destructive test
circuit should be minimized. The circuit structure is presented
with considering for both the probe connection and low-stray
inductance. This paper presents experimental results under
the extreme conditions of an short-circuit test for a Si super
junction MOSFET (Si-MOSFET), and SiC double-diusion
MOSFET (SiC-MOSFET). These experimental results confirm
that the validity of the non-destructive test circuit for Si-
and SiC-MOSFETs. Moreover, the phenomenon observed just
before destruction of the MOSFETs will be shown under short-
circuit tests. These experimental results will be applied to
improve the reliability of SiC power devices.
II. Circuit Configuration of the Non-destructive Test
Circuit
A. Circuit Configuration
Fig. 1 shows the configuration of the non-destructive test
circuit, and Table I shows circuit parameters used in the
experimental system. The maximum voltage rating of the non-
destructive test circuit is set to 1,200 V, so that the voltage
rating of the device under test (DUT) can be set to less than
600 V. The current rating is 250 A with a 300 s pulse current.
The gate signals of the circuit are controlled by FPGA (Field
Program Gate Array), because the time step of the switching
sequence should be controlled to less than 30 ns. The main
978-1-4577-2088-8/11/$26.00 2012 IEEE
switch Q1 of the circuit is used to an IGBT, and only a SiC- Q1 Q3 iQ3
SBD (Schottky Barrier Diode) is used as the Q3 in order to iL iD
VDC C
mitigate the reverse recovery current. The Q2 employs a PN- vGE
diode inside the IGBT module, and the Q4 is a discrete IGBT L
used to reduce the stray inductance of the power device. Q2 Q4 vDS
vGS
DUT
B. Gate Drive Circuit for Q1 and DUT
RG
An optical coupler which is for switching an IGBT is used
V+ Gate
for isolation and amplification in the gate drive circuit for Q1 Drive
and the DUT, and the gate drive voltage (V+ and V) for DUT V Circuit
can be changed from 15 V to +25 V. The gate drive voltage
for a conventional Si-MOSFET can generally be used to 15 Fig. 1. Non-destructive test circuit
V. However, the suitable gate drive voltage for SiC switching
devices, such as normally-OFF, -ON JFETs, and MOSFETs, TABLE I
are not the same voltage as the Si-MOSFET. Therefore, two Test Circuit Parameters
DC voltage sources (V+ and V) with voltage regulation are Device Under Test(DUT) 600 V Power MOSFET
be connected to the gate drive circuit of the DUT as shown Q1 and Q2 IGBT: CM150DY-24H
in Fig. 1. In addition, the switching speed of the DUT can be Q3 SiC-SBD: C2D10120A
Q4 IGBT: IXGF30N400
changed by the gate resistance, RG . Current Rating 250 A (less than 300 s)
Test Sequence Short circuit, one cycle pulse (less
than 300 s)
C. DC Capacitor C DC Inductor L 120 H
DC capacitor C 4,700 F
It is important to design the DC capacitance C of the test Controller FPGA (Clock Frequency: 30 MHz)
circuit to precisely evaluate under the extreme characteristics
of the MOSFET. The stored energy in the DC capacitor is
dissipated to the MOSFET, because the MOSFET acts as the
the inductor current is set to 0.2 A, the inductance L is given
resistor under short-circuit tests. Therefore, it is necessary to
by:
design the capacitance of the DC capacitor C DC , to prevent
the DC voltage drop. The maximum avalanche energy of a t 50 109[s]
L = VDC = 4 102[V]
commercial 600 V Si-MOSFET is generally designed to be i 2 101[A]
less than 2,000 mJ. Therefore, the maximum supply energy per = 100 106 H. (3)
one cycle of the capacitor is set to 5,000 mJ and the allowable
DC voltage drop V, is only 1% to 400 V. In this case, the An air core inductor with 120 H is used in the experi-
capacitance can be calculated using the following equations. mental system, so that the volume of the inductor is quite
large. However, the DC bias characteristics and the saturation
2 5, 000 103 phenomenon of the core can be ignored, and the frequency
C= = 3.14 103 F, (1)
VDC 2 {VDC V}2 characteristics are linear within the range of the experiment.
where the V is set to 4 V. The experimental system uses as E. Structure of the Non-destructive Test Circuit
an electrolytic capacitor rated at 550 V, 4,700 F.
Fig. 2 shows a representation of the non-destructive test
circuit structure and Fig. 3 shows a photograph of the circuit.
D. Inductor L
The operation condition is not operated at high-temperature
The diL /dt of the inductor current is dependent on the but at the room-temperature in this paper.
inductance L, and the DC voltage, VDC . The peak value of the An IGBT module is used for Q1 and Q2 of the first layer,
test current IDpeak is determined by the following equation: and the MOSFET as the DUT, Q3 and Q4 are placed on the
second layer, as shown in Fig. 2. The stray inductance of
VDC
IDpeak = (t1 t2 ) (2) the the stray inductance of the experimental system has to be
L
minimized because it may aect the switching operation and
where time t1 and t2 , represents the experimental test period measurement waveforms. Therefore, this circuit is designed
as shown in Fig. 5. and implemented for low stray inductance with consideration
The time step t, can be controlled every 30 ns in this for the connection of the voltage and current probes. A passive
experimental system, because the clock frequency of the voltage probe has a 50100 mm ground wire, but the wire
FPGA is set to 30 MHz. When the current resolution i of inductance may cause oscillation phenomenon of the voltage

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 BNC connectors Third Layer:
DUT Drive Circuit
Second Layer:
SiC-SBD Q3
IGBT Q4
DUT
(MOSFET)
First Layer:
IGBT module
Fig. 2. Representation of the non-destructive test circuit
Fig. 3. Photograph of the non-destructive test circuit
waveforms. Therefore BNC connecters instead of the voltage
probe head and ground wire are used to measure the voltage
waveforms of vDS and vGS , and the connectors are placed on
the third layer. A Rogowsky current sensor (PEM: CWT3)
for measurement iD is used to measure the current waveform,
because the volume of the Rogowsky current sensor is smaller
than that of conventional current sensors.
The gate drive circuit of the DUT must be connected to
the third layer because of reducing the inductance inside the
gate drive circuit. On the other hand, the gate drive circuits of
Q1 and Q4 are placed adjacent to the IGBT module. This
experimental system does not connect any cooling device,
because the short-circuit time is set to less than 1 ms and
the transient thermal resistance of the DUT is less than 0.1
C/W under the shot-circuit test period.
III. Operation Mode for the Short-Circuit Test
Fig. 4 shows the operation mode of the short-circuit test,
and Fig. 5 shows voltage and current waveforms from t1 to t3 .
Both Q1 and the MOSFET are turned-on at t1 , and the
current flows to Q1 , L, and the MOSFET, as shown in Fig. 4
(a). The current slope diD /dt is settled by the DC voltage
VDC and the inductance L, and the peak current IDpeak is
determined using Eq. (2). In the short-circuit condition shown
in Fig. 4(b), the MOSFET acts as a resistor and the resistance
12
of the MOSFET is larger than that of the data sheet value
(RDS (ON) ). As a result, the voltage vDS , increases with time,
t. When the voltage vDS reaches VDC at t2 , iD is reduced, as
shown in Fig. 5. In this case, the resistance of the MOSFET
is continuously increasing, because the junction temperature
of the MOSFET is also increasing. The gate signal vGS of the
MOSFET changes to the o signal at t3 , then iD reduces to
zero and the inductor current flows to the diodes (Q2 and Q3 ).
IV. Experimental Results
Table II shows device ratings of the device under tests
(DUTs) used for the following experiments. A Si super junc-
tion MOSFET and SiC double-diusion MOSFET are used for
evaluation of the MOSFETs characteristics under the short-
circuit tests.
A. Si Super Junction MOSFET (Si-MOSFET)
Fig. 6 shows experimental results for the Si super junction
MOSFET rated at 600 V, 12 A. The gate drive voltage is set
from 15 to +15 V, and the gate resistor RG , is set to 22 . The
short-circuit time (t3 t1 ) is set to 75 s. The DC voltage is 380
V, and the peak current of IDpeak is set to 47 A, which is 4 times
larger than the rated DC drain current. During the time period
from t1 to t3 , the current iD and voltage vDS waveforms are the
same as Fig. 5. When the o-signal is sent to the MOSFET
at t3 , the MOSFET could not be turned o completely. As
a result, the drain current iD does not completely reach zero
before it increases again. In this case, the MOSFET could not
operate as in a typical power device, and Q1 is turned o at t4
to prevent destruction of the MOSFET. The inductor current
flows to both Q2 , Q3 and the MOSFET, as shown in Fig. 4(d),
and then vDS is reduced to zero. In this case, the time period
from t3 to t4 is set to 19.9 s. The dissipation energy of the
MOSFET can be calculated using the following equation:
 t4
PD = vDS iD dt [J] (4)
t1
where the integral time is from t1 to t4 . For this experiment,
the energy was 0.72 J just before destruction. In this case, the
dissipation energy of the MOSFET is 10 times larger than the
rated avalanche energy.
On the other hand, the time period from t3 to t4 is set to
20.0 s, so that the MOSFET could be destroyed under this
experimental condition, as shown in Fig. 7. This destruction
mode corresponds to inhomogeneous operation failure [2],[5].
Fig. 8 shows the non-destruction operation waveform from
t3 to t4 , and Fig. 9 shows the magnified waveforms of id .
The MOSFET under the short-circuit condition could not be
turned o completely, so that the MOSFET will be destroyed
under these conditions. On the other hand, the main switch
Q1 is turned o at t4 , so the experimental system can prevent
destruction of the MOSFET.
 50
Q1 Q1
VDC VDC

iD [A]
L L
DUT DUT 0
100 200
(a) t1 (Initial Condition) (b) t1 t2
600

Q1 Q1

vDS [V]
VDC VDC
L L
DUT DUT 0
0 t1 t2 t3 t4
(c) t2 t3 (d) t4
100 200
time [s]
Fig. 4. Operation mode of the short-circuit test
Fig. 6. Experimental results for the Si-MOSFET with non-destructive
operation

50
vGE 0
iD [A]

100 200
vGS 0 0

600
vDS [V]

vDS

0
0
0 t1 t2 t3 t4
iD 100 200
time [s]
0 Fig. 7. Experimental results for the short-circuit test of the Si-MOSFET
with abnormal operation
iQ3

0
t1 t2 t3 B. SiC Double-Diusion MOSFET (SiC-MOSFET)

Fig. 5. Operation waveform of the short-circuit test Fig. 10 shows experimental results for the SiC double-
diusion MOSFET rated at 1,200 V, 33 A. The gate drive
voltage is set from 2 to +18 V, and the gate resistor RG , is
set to 5 . The short-circuit time (t3 t1 ) is set to 100 s.
TABLE II The DC voltage is set to 350 V, and the peak current of iDpeak
Device Rating of Device Under Test (DUT)
is to 175 A which is 5 times as large as the rated current.
Item Si-MOSFET SiC-MOSFET
The experimental waveforms show surge voltages in vDS at
Type TK12A60U CMF20120D
Package TO-220FM TO-267 t3 and t4 , which are dependent on the stray inductance of the
Drain to Source Voltage [V] 600 1,200 circuit. However, the surge voltage does not reach the rated
Drain Current (DC) [A] 12 33(25 C)
DC voltage at 600 V. In this case, diD /dt is to 1 kA/s, and
Drain Current(pulsed) [A] 24 78
Avalanche Current [A] 12 - the peak voltage of vDS reaches 536 V. As a result, the stray
Avalanche Energy (one cycle) [mJ] 69 2,200 inductance of the experimental system can be calculated 157
Power Dissipation [W] 35 150
ON-state resistance [] 0.36 0.08
nH which is including wire inductance and ESL (Equivalent
Series Inductance) of the capacitor C. When the o-signal is
sent to the MOSFET, id reaches zero at t3 , therefore, it can

13
 200
vGE 0

iD [A]
vGS 0
0
100 200
600
vDS

vDS [V]
0

iD
0 0
t1 t2 t3 t4
0
100 200
time [s]
iQ3
0
t3 t4 Fig. 10. Experimental results for the SiC-MOSFET with non-destructive
operation

Fig. 8. Si-MOSFET with non-destructive operation

200

iD [A]
Destruction
Phenomenon 0
100 200
iD Experimental
600
Condition
vDS [V]

Abnormal Operation

t3 t4
0
Fig. 9. Magnified abnormal operation waveforms of the Si-MOSFET t1 t2 t3
0
100 200
time [s]

be turned o completely. In this case, the MOSFET appears
to operate as a normal switching devices and the dissipation
energy was 1.6 J just before destruction.
Fig 11 shows experimental results for the destruction con-
dition. In this case, the DC voltage is set to 360 V, and other
conditions are the same as above experimental result. The
MOSFET can also be turned o completely at t3 , the same
as that shown in Fig. 10. However, id suddenly increases 7
s after t3 , and the MOSFET is destroyed. This destruction
mode corresponds to device failure after turn o [2]. In this
condition, the main switch Q1 does not operate. However, Q1
should be turned o to prevent destruction of the MOSFET
within 7 s from t3 . Therefore, the experimental result in Fig.
10 shows the non-destruction test result for the SiC-MOSFET.
Fig. 12 shows the non-destructive test operation waveforms
for the SiC-MOSFET from t3 to t4 , and Fig. 13 shows
magnified waveforms of id . In the case of short-circuit test
condition, the turn-o current iD of the MOSFET appears
similar to the tail current of an IGBT. In addition, it may
be destroyed several s after t3 as shown in Fig. 13. In order
Fig. 11. Experimental results for the SiC-MOSFET with destructive operation
to conduct a non-destructive test, the main switch Q1 should
be turned o during abnormal operation conditions.
V. Conclusion
This paper presents the circuit structure of a non-destructive
test rated at 600 V, 250A for SiC-MOSFET of which the
validity is confirmed from the experimental results. The ex-
perimental system can obtain a current waveform just before
destruction of Si- and SiC-MOSFETs. As a result, the short-
circuit switching operation of the SiC double-diusion MOS-
FET is observed to be dierent from that of the Si super
junction MOSFET.
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6, pp. 939-943, 2010.

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 vGE 0

vGS 0

vDS

iD
0

iQ3
0
t3 t4
Fig. 12. SiC-MOSFET non-destructive operation

Destruction
Phenomenon

iD
Abnormal
Condition

t3
Fig. 13. Magnified abnormal operation waveforms of the SiC-MOSFET

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