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It is easy to get confused with the denitions of setup and hold violations. We are used to the denitions of
setup and hold times for a single ipop. The setup and hold violation checks done by STA tools are slightly
diIerent. PT aptly calls them max and min delay analysis. However, the other terminology is more common.
Setup time is the minimum amount of time the data signal should be held steady before the clock event so
that the data are reliably sampled by the clock. Hold time is the minimum amount of time the data signal
should be held steady after the clock event so that the data are reliably sampled.
However, we are checking the setup at the clock edge B. So we need to add one clock cycle to the clock path
delay to get the Required Time.
Data launched at FF1/CP should arrive at FF2/D in one clock period. So in setup check, we say a violation has
occured if the data path delay is more than one clock cycle.
And the actual clock path delay is: CLK delay till FF2/CP.
Required Time = Clock period + CLK delay till FF2/CP.
Now, we should also take into account the setup requirement of FF2. ie. Data at FF2/D should be stable for at
least TsFF2 before the clock edge. So the required time for data arrival at FF2/D is Clock period + CLK delay
till FF2/CP- TsFF2 .If data arrives later than the clock path delay calculated above, the data wont be captured
at edge B.
From above, it is clear that setup analysis checks for the maximum allowable delay for the timing path.
Let us take the same timing path above. Here you are verifying that the data is not captured at FF2/D on
launching edge A of the CLK. ie. it is checking for the minimum delay the data should take to arrive at the
second op for the circuit to function correctly.
ThFF2 is the library hold time value of op FF2. If the Data launched by FF1 reaches D of FF2 fast enough, it
may be captured at the same clock edge A by the op FF2. Hence the minimum delay requirement for the
timing path is that the path to D should at least take more time than the hold time requirement of the op
FF2, so as not to corrupt the data. (Look up the .lib le for the hold time values for pin D relative to clcok pin
CP of the ip op type of FF2).
In simple terms, this makes sure the launched data does not arrive at the capture point too soon. Data
launched from launching op is allowed to arrive at the input of the second op only after a delay greater
than its hold requirement so that it is properly captured.
Take a timing report and draw the clock and data path diagrams to understand this further.
18 Comments
arrival at FF2/D is Clock period + CLK delay till FF2/CP+ TsFF2 .If data arrives later than the clock path
delay calculated above, the data wont be captured at edge B.
Can you explain what is the reason of setup and hold time? Why do they exist?
Can setup and hold violations possible for same path? if yes how can we resolve them?
1. You may see setup and hold violation on the same path for diIerent corners.
2. If you are seeing setup and hold violation for the same path for same corner/view, you need to
look at the report to see whats happening. Most probably you have derates, uncertainties etc, and
taken together with slowest data+ fastest clock for setup check and fastest data+ slowest clock, it
could report such a scenario. This is not valid in real life, so need to x the constraints and analysis
type.
Hey as already mentioned in one of the comments, data required time for setup should be Time period+
Clock Network delay of FF2/CP Tsu.
Thanks.
plainspeak 2 years ago
I suspect synthesis(and timing run in synthesis tool) wont even consider this path. You can try adding
this CLR pin as a sync pin and try to match the skew to clock pins, but I dont know how eIective that
will be in ensuring you meet one cycle after the reset.
Of course, I am just theorizing. Maybe you can try out the report.
The clocks for op A and clock to op B come 100ns apart. So, the clocks being diIerent to ops
A and B wont cause any timing issue. But, what Im worried is the path I have mentioned in my
previous message. Even I suspected that the path wont be timed by the tools. I was reviewing a
design which had the kind of logic described above and I found it odd. Thats why I asked your
opinion. May be, I should try out synthesizing it and see if that path is timed.
I am seeing setup violation from my block reg2out port to top-level reg2out port. There are no
combinational logics between them. Should I add false path at these ports. If so, how?
Sini Mukundan 9 months ago
Can you report the timing from the begin point of the block path to top level reg2out? Or is your
block a hardmacro?
My block is a hard macro and I am seeing atleast -1ns violation at the o/p port of my block to top
level o/p port (violation is seen at reg2out path-group in top level) with no combinational logic in-
between them. Is it related to incorrect budgeting?
hi
could you please tell me why hold is checked on same edge of clock while setup on next edge? why hold
is not responsible for deciding maxi frequency?
When you check hold, you are trying to make sure the minimum time required for the path is met. If
the data reaches the capture op too soon, it may not be stable enough. Hence the same clock edge.
max delay is what denes max frequency, whereas hold is min delay.
Can you please explain why setup time is greater than hold time?
Is there any good book which explains basics of Setup and hold time ?