ECEN 454 Lab0: Setup Instructions & Overview

In the labs for this course, you will use the Cadence set of tools for VLSI design. These tools are the
state-of-the-art CAD tools widely used in the industry. It is hard to learn the whole software set in one
semester. In this semester, you will focus on the part that is very useful in digital IC design.

1. UNIX login

By now you should have UNIX accounts on the SUN workstations. If you still do not
have accounts, please inform the TA. You will be working independently on all the
labs.

Every time you login you are in your home directory. Create a directory called (lets
say), "cadence" in your home directory where you will do all your Cadence-related
works for the whole semester. The UNIX command for creating directory is "mkdir".
So type "mkdir cadence" and press return. (UNIX is case-sensitive so type in small
alphabets). If you are familiar with UNIX go to section 2. You can find some useful
UNIX commands help at http://www.math.utah.edu/lab/unix/unix-commands.html

Cadence tool (virtuoso is an Integrated circuit front end to back end Cadence design
integration tool) stores all the files in the directory from which it is started. So every
time you start virtuoso go to this directory (cadence) before starting it. The UNIX
command "cd" is used to change directory. Type "cd cadence" to change your working
directory to cadence.

The other UNIX command for changing directories is "cd .." which means to go back
one level (to the parent) in the hierarchy. "cd" takes to the home directory.

Another concept in UNIX is that of a process. Every time you run a task on UNIX, it is
given a process ID called PID. The UNIX command for finding process id is "ps". Type
"ps" to see all the processes running on the machine. Processes can be killed using kill
# command where # is the PID. After you finish your lab, type exit to log off if
there is no process running or kill 1 1 to close all processes and log off. Please
make sure you log off since other students cannot access the machine if you do not
log off and leave.

UNIX allows tasks to be run in background meaning, you can run other task at the
prompt. To run a task in background you should type "&" at the end of the command.

You can use any editor you want, such as emacs, vi, etc. To start emacs type "emacs &"
(this is an example of running a task in the background). For vi you can try vim g
filename &.

These are some of the basic commands of UNIX. To make you more familiar with
UNIX commands refer to some book on UNIX.

If you are not in cadence directory, change to cadence.

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 ECEN 454 Lab0: Setup Instructions & Overview

2. Objective

Through Labs 1-9, you will be required to design an 8-bit Pipelined Adder. Following is the
block diagram of the circuit.

Fig 1. Block diagram for an 8 bit Pipelined adder.

Following is a brief description of the design flow you will be using over the next few lab
sessions. The detailed requirements for each stage will be in the respective lab manuals

You will begin with the implementation of the schematic and its logic simulation. You
will be guided to design each of the blocks (using logic gates such as And, Nand, Inv
and Flip-Flops) in the above diagram.

After verifying the logic design of the circuit you will be designing the custom layout of
the gates (standard cells) that were used in the design.

The next stage involves performing the standard cell characterization which includes
finding rise and fall delay times of the standard cells using transistor level
implementation of the cells using Spectre.

The next step would be to merge all the standard cell layouts to create a 1-bit full adder.

Using the 1-bit full adders, design one sub-block (one 4-bit adder) of the entire design.

You are then required to perform optimization of the circuit in terms of transistor sizes/
circuit area (an increased transistor size may occupy more area but is faster in terms of
its delay and your design should keep such trade-offs in mind), delay of the circuit and

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 ECEN 454 Lab0: Setup Instructions & Overview

power consumed.

The next step requires you to design the layout and characterize a Flip-Flop. The
characterization would include finding the setup and hold time of the FF. (FF stands for
Flip-Flop in all the following sections and manuals).

Finally, you will combine all the blocks designed (4-bit adders, FF's and the registers) to
implement the entire design. The combined design should also include a buffered clock
tree implemented as a H-tree.

The grading would be based on weekly reports and would be based on design metrics such as
area, clock period and power consumption wherever applicable.

Through Labs 6, 10 and 11, you will implement a circuit design using ASIC design flow.

1) You will begin by writing a behavioral description of a Cruise Control system of a car using
verilog. You will be required to verify its operation.

2) Next you will synthesize the verilog code using Design Analyzer to generate a gate level netlist
of the circuit you designed.

3) You will then use a tool called SoC Encounter to perform Place and Route for the netlist that
you generated in the previous step.

4) Next you will be performing static timing analysis on this circuit and make any required
modifications to improve the delay along any path which has a low slack.

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