Low-Complexity Reconfigurable Fast Filter Bank for Multi-Standard Wireless

Receivers
Abstract
An approach of new low-complexity reconfigurable fast filter bank (RFFB) for
wireless communication applications such as spectrum sensing and
channelization is discussed here. In RFFB, the bandwidth and center frequency
of sub-bands can be varied with high frequency resolution without hardware
reimplementation. This is achieved with an improved modified frequency
transformation-based variable digital filter (MFTVDF) at the first stage of the
implemented multistage implementation. Existing second-order frequency
transformation-based low-pass VDFs have limited cutoff frequency range which
is approximately 12.5% of the sampling frequency. The designed low-pass MFT-
VDF offers unabridged control over the cutoff frequency on a wide frequency
range thereby, improving the cutoff frequency range of existing VDFs. The
design example shows that the RFFB is easy to design and offers substantial
savings in gate counts over other filter banks.

Existing System
Design of new low-complexity reconfigurable fast filter bank (RFFB) for wireless
communication applications such as spectrum sensing and channelization is
discussed here The designed low-pass MFT-VDF offers unabridged control over
the cutoff frequency on a wide frequency range thereby, improving the cutoff
frequency range of existing VDFs. The design example shows that the RFFB is
easy to design and offers substantial savings in gate counts over other filter
banks.

Proposed System
Design of reconfigurable fast filter bank system for communication and signal
processing platforms is implemented here with a advancement of auto tuning
facility which enables the filter configurations get tuned automatically according
to the receiver requirements. A look up table for various frequency channels is
generated and applied to a configurable filter block. DPA (Digital parameter
analyzer) is strongly implemented using various logical blocks to analyze the
parameters before the filter process starts.

APPLICATIONS
High speed radio frequency applications
RF Front end and fast spectrum analysis

ADVANTAGES
FPGA Core acts as a AI (Artificial Intelligence) for FILTER configurations,
which enable to utilize area and reduce power drastically
FUTURE SCOPE
Application such as simple radio receiver , wireless transponder prototype
is made using this FILTER
 INTRODUCTION

A multi-standard wireless receiver (MSWR) enables different air interfaces to be

implemented on a single generic hardware platform by replacing conventional
analog signal processing with the digital signal processing. Operations such as
spectrum sensing and channelization for MSWRs are usually performed using a
filter bank. The filter bank must be dynamically reconfigurable with minimum
hardware overhead to support multiple communication standards with different
channel bandwidth and center frequency specifications. Moreover, the filter
bank should be hardware-efficient in terms of area and power. The design of
such low-complexity reconfigurable filter bank is the objective of this brief.A
number of different filter bank design approaches are available.

The discrete Fourier transform filter bank (DFTFB) is a modulated filter bank that
consists of a low-pass prototype filter followed by DFT operation and widely
used for various communication applications. However, DFTFBs have the
drawbacks of uniform sub-band bandwidth and fixed center frequency for each
sub-band. An improved DFTFB using coefficient decimation method (CDM) has
been proposed in which allows changing sub-band bandwidths using a fixed-
coefficient filter at low reconfiguration overhead. However, it provides only
coarse control over sub-band bandwidth because the decimation factor in the
CDM is restricted to be integers. Also, center frequency of sub-bands in CDM-
DFTFB is fixed.

Low-complexity, reconfigurable filter banks based on frequency response

masking and CDM for MSWRs are proposed in and . As the decimation and
interpolation factors are limited to integer values, a fine control over the
bandwidth is difficult to achieve using these filter banks. The fast filter bank
(FFB) is a low complexity alternative to DFTFB and is suitable for applications
requiring sharp transition bandwidth (TBW). However, the FFB in [6] has the
same drawbacks as that of DFTFB, i.e., the inability to provide nonuniform
bandwidth sub-bands and the constraint of fixed center frequency for each sub-
band. Further extensions and improvements of FFBs have been suggested in
next chapters. In particular, multiresolution FFB in 8provides coarse control over
sub-band bandwidth by changing the filter bank resolution. However, all filter
banks mentioned above fail
to provide fine control over the bandwidth and center frequency of sub-bands. In
this brief, we propose a new approach of reconfigurable filter bank design by
combining FFB and a variable digital filter (VDF).
First, a modified second-order frequency transformation-based low pass VDF
(MFT-VDF) that offers wide cutoff frequency range than existing VDFs is
proposed. Then, the proposed reconfigurable FFB (RFFB) is designed by
replacing fixed-coefficient low-pass subfilter in the first stage of FFB with the
MFT-VDF. The RFFB provides fine control over the sub-band bandwidth on the
desired bandwidth range. This makes RFFB suitable for MSWRs where
wideband input signal consists of channels of distinct bandwidths.
The RFFB also offers fine control over the center frequency of fixed bandwidth
subbands. This unique property is useful where wideband input consists of
channels of fixed bandwidth but dynamically varying locations. The rest of this
brief is organized as follows. The design details of VDFs are provided in Section
II followed by design of the RFFB in Section III. A design example and gate
count complexity comparisons are shown in Section IV and Section V
respectively. Finally, Section VI concludes this brief.

VARIABLE DIGITAL FILTER

VARIABLE digital filters (VDFs)are digital filters with controllable spectral

characteristics such as variable cutoff frequency response, adjustable passband
width, controllable fractional delay, etc. They found applications in different
areas of signal processing and communications, e.g., fractional delay digital
filters for timing adjustment in digital receivers. Methods for designing variable
digital filters can broadly be classified into two categories: transformation and
spectral parameter approximation methods. In the former, a prototype filter with
certain desirable frequency characteristics is first designed. Certain
transformation such as the all pass transformation method is then applied to the
prototype filter to obtain the final VDF. In general, transformation method is
applicable to VDF with variable cutoff frequencies, but not general variable
characteristics say variable fractional delay. The spectral parameter
approximation method is more general in that it assumes that either the impulse
responses or the poles and zeros of the filters are polynomials of certain
spectral parameters.

The coefficients of the polynomials are then determined to provide continuous

tuning of the VDF by the spectral parameters. The spectral parameter method
was proposed by Zarour and Fahmy where the poles and zeros of an infinite-
impulse response (IIR) filter are assumed to be polynomials of the spectral or
tuning parameters. Most of the works on VDF reported are focused on the
design of IIR VDF, and methods for guaranteeing their stability. More recently,
the design of one-dimensional and two-dimensional (2-D).
In signal processing, a digital filter is a system that performs mathematical
operations on a sampled, discrete-time signal to reduce or enhance certain
aspects of that signal. This is in contrast to the other major type of electronic
filter, the analog filter, which is an electronic circuit operating on continuous-time
analog signals.
A digital filter system usually consists of an analog-to-digital converter to sample
the input signal, followed by a microprocessor and some peripheral components
such as memory to store data and filter coefficients etc. Finally a digital-to-
analog converter to complete the output stage. Program Instructions (software)
running on the microprocessor implement the digital filter by performing the
necessary mathematical operations on the numbers received from the ADC. In
some high performance applications, an FPGA or ASIC is used instead of a
general purpose microprocessor, or a specialized DSP with specific paralleled
architecture for expediting operations such as filtering.
Digital filters may be more expensive than an equivalent analog filter due to their
increased complexity, but they make practical many designs that are impractical
or impossible as analog filters. When used in the context of real-time analog
systems, digital filters sometimes have problematic latency (the difference in
time between the input and the response) due to the associated analog-to-digital
and digital-to-analog conversions and anti-aliasing filters, or due to other delays
in their implementation.
Digital filters are commonplace and an essential element of everyday electronics
such as radios, cellphones, and AV receivers.

Characterization
A digital filter is characterized by its transfer function, or equivalently, its
difference equation. Mathematical analysis of the transfer function can describe
how it will respond to any input. As such, designing a filter consists of
developing specifications appropriate to the problem (for example, a second-
order low pass filter with a specific cut-off frequency), and then producing a
transfer function which meets the specifications.
The transfer function for a linear, time-invariant, digital filter can be expressed as
a transfer function in the Z-domain; if it is causal, then it has the form:
where the order of the filter is the greater of N or M. See Z-transform's LCCD
equation for further discussion of this transfer function.
This is the form for a recursive filter with both the inputs (Numerator) and
outputs (Denominator), which typically leads to an IIR infinite impulse response
behaviour, but if the denominator is made equal to unity i.e. no feedback, then
this becomes an FIR or finite impulse response filter

Analysis techniques
A variety of mathematical techniques may be employed to analyze the
behaviour of a given digital filter. Many of these analysis techniques may also be
employed in designs, and often form the basis of a filter specification.
Typically, one characterizes filters by calculating how they will respond to a
simple input such as an impulse. One can then extend this information to
compute the filter's response to more complex signals.

Impulse response

The impulse response, often denoted or , is a measurement of how a

filter will respond to the Kronecker delta function. For example, given a

difference equation, one would set and for and evaluate.

The impulse response is a characterization of the filter's behaviour. Digital filters
are typically considered in two categories: infinite impulse response (IIR) and
finite impulse response (FIR). In the case of linear time-invariant FIR filters, the
impulse response is exactly equal to the sequence of filter coefficients:

IIR filters on the other hand are recursive, with the output depending on both
current and previous inputs as well as previous outputs. The general form of an
IIR filter is thus:
Plotting the impulse response will reveal how a filter will respond to a sudden,
momentary disturbance

Difference equation
In discrete-time systems, the digital filter is often implemented by converting the
transfer function to a linear constant-coefficient difference equation (LCCD) via
the Z-transform. The discrete frequency-domain transfer function is written as
the ratio of two polynomials. For example

and to make the corresponding filter causal, the numerator and denominator are
divided by the highest order of :
Filter design
The design of digital filters is a deceptively complex topic. [1] Although filters are
easily understood and calculated, the practical challenges of their design and
implementation are significant and are the subject of much advanced research.
There are two categories of digital filter: the recursive filter and the nonrecursive
filter. These are often referred to as infinite impulse response (IIR) filters and
finite impulse response (FIR) filters, respectively

Filter realization
After a filter is designed, it must be realized by developing a signal flow diagram
that describes the filter in terms of operations on sample sequences. A given
transfer function may be realized in many ways. Consider how a simple
expression such as could be evaluated one could also compute

the equivalent . In the same way, all realizations may be seen as

"factorizations" of the same transfer function, but different realizations will have
different numerical properties. Specifically, some realizations are more efficient
in terms of the number of operations or storage elements required for their
implementation, and others provide advantages such as improved numerical
stability and reduced round-off error. Some structures are better for fixed-point
arithmetic and others may be better for floating-point arithmetic.

Direct Form I
A straightforward approach for IIR filter realization is Direct Form I, where the
difference equation is evaluated directly. This form is practical for small filters,
but may be inefficient and impractical (numerically unstable) for complex
designs.[3] In general, this form requires 2N delay elements (for both input and
output signals) for a filter of order N.
Direct Form II
The alternate Direct Form II only needs N delay units, where N is the order of
the filter potentially half as much as Direct Form I. This structure is obtained by
reversing the order of the numerator and denominator sections of Direct Form I,
since they are in fact two linear systems, and the commutativity property

applies. Then, one will notice that there are two columns of delays ( ) that tap
off the center net, and these can be combined since they are redundant, yielding
the implementation as shown below.
The disadvantage is that Direct Form II increases the possibility of arithmetic
overflow for filters of high Q or resonance. [4] It has been shown that as Q
increases, the round-off noise of both direct form topologies increases without
bounds.[5] This is because, conceptually, the signal is first passed through an all-
pole filter (which normally boosts gain at the resonant frequencies) before the
result of that is saturated, then passed through an all-zero filter (which often
attenuates much of what the all-pole half amplifies).
Cascaded second-order sections
A common strategy is to realize a higher-order (greater than 2) digital filter as a
cascaded series of second-order "biquadratric" (or "biquad") sections [6] (see
digital biquad filter). The advantage of this strategy is that the coefficient range is
limited. Cascading direct form II sections results in N delay elements for filters of
order N. Cascading direct form I sections results in N+2 delay elements since
the delay elements of the input of any section (except the first section) are
redundant with the delay elements of the output of the preceding section

Comparison of analog and digital filters

Digital filters are not subject to the component non-linearities that greatly
complicate the design of analog filters. Analog filters consist of imperfect
electronic components, whose values are specified to a limit tolerance (e.g.
resistor values often have a tolerance of 5%) and which may also change with
temperature and drift with time. As the order of an analog filter increases, and
thus its component count, the effect of variable component errors is greatly
magnified. In digital filters, the coefficient values are stored in computer memory,
making them far more stable and predictable.[9]
Because the coefficients of digital filters are definite, they can be used to
achieve much more complex and selective designs specifically with digital
filters, one can achieve a lower passband ripple, faster transition, and higher
stopband attenuation than is practical with analog filters. Even if the design
could be achieved using analog filters, the engineering cost of designing an
equivalent digital filter would likely be much lower. Furthermore, one can readily
modify the coefficients of a digital filter to make an adaptive filter or a user-
controllable parametric filter. While these techniques are possible in an analog
filter, they are again considerably more difficult.
Digital filters can be used in the design of finite impulse response filters. Analog
filters do not have the same capability, because finite impulse response filters
require delay elements. Digital filters rely less on analog circuitry, potentially
allowing for a better signal-to-noise ratio. A digital filter will introduce noise to a
signal during analog low pass filtering, analog to digital conversion, digital to
analog conversion and may introduce digital noise due to quantization. With
analog filters, every component is a source of thermal noise (such as Johnson
noise), so as the filter complexity grows, so does the noise.
However, digital filters do introduce a higher fundamental latency to the system.
In an analog filter, latency is often negligible; strictly speaking it is the time for an
electrical signal to propagate through the filter circuit. In digital systems, latency
is introduced by delay elements in the digital signal path, and by analog-to-
digital and digital-to-analog converters that enable the system to process analog
signals.
In very simple cases, it is more cost effective to use an analog filter. Introducing
a digital filter requires considerable overhead circuitry, as previously discussed,
including two low pass analog filters. Types of digital filters Many digital filters
are based on the fast Fourier transform, a mathematical algorithm that quickly
extracts the frequency spectrum of a signal, allowing the spectrum to be
manipulated (such as to create band-pass filters) before converting the modified
spectrum back into a time-series signal.
Another form of a digital filter is that of a state-space model. A well used state-
space filter is the Kalman filter published by Rudolf Kalman in 1960.
Traditional linear filters are usually based on attenuation. Alternatively nonlinear
[10]
filters can be designed, including energy transfer filters which allow the user
to move energy in a designed way. So that unwanted noise or effects can be
moved to new frequency bands either lower or higher in frequency, spread over
a range of frequencies, split, or focused. Energy transfer filters complement
traditional filter designs and introduce many more degrees of freedom in filter
design. Digital energy transfer filters are relatively easy to design and to
implement and exploit nonlinear dynamics
 INTRODUCTION TO VLSI

VLSI BASICS:

The first semiconductor chips held two transistors each.

Subsequent advances added more and more transistors, and, as a
consequence, more individual functions or systems were integrated over time.
The first integrated circuits held only a few devices, perhaps as many as ten
diodes, transistors, resistors and capacitors, making it possible to fabricate one
or more logic gates on a single device. Now known retrospectively as small-
scale integration (SSI), improvements in technique led to devices with hundreds
of logic gates, known as medium-scale integration (MSI).Further improvements
led to large-scale integration (LSI), i.e. systems with at least a thousand logic
gates. Current technology has moved far past this mark and today's
microprocessors have many millions of gates and billions of individual
transistors. Very-large-scale integration (VLSI) is the process of creating
integrated circuits by combining thousands of transistors into a single chip.

VERILOG:

Verilog standardized as IEEE 1364, is a hardware description

language (HDL) used to model electronic systems. It is most commonly used in
the design and verification of digital circuits at the register-transfer level of
abstraction. It is also used in the verification of analog circuits and mixed-signal
circuits. Hardware description languages such as Verilog differ from software
programming languages because they include ways of describing the
propagation of time and signal dependencies (sensitivity). There are two
assignment operators, a blocking assignment (=), and a non-blocking (<=)
assignment. The non-blocking assignment allows designers to describe a state-
machine update without needing to declare and use temporary storage
variables. Since these concepts are part of Verilog's language semantics,
designers could quickly write descriptions of large circuits in a relatively compact
and concise form. At the time of Verilog's introduction (1984),Verilog
represented a tremendous productivity improvement for circuit designers who
were already using graphical schematic capture software and specially written
software programs to document and simulate electronic circuits.

VHDL:

VHDL (VHSIC Hardware Description Language) is a hardware

description language used in electronic design automation to describe digital
and mixed-signal systems such as field-programmable gate arrays and
integrated circuits. VHDL can also be used as a general purpose parallel
programming language. VHDL is commonly used to write text models that
describe a logic circuit. Such a model is processed by a synthesis program, only
if it is part of the logic design. A simulation program is used to test the logic
design using simulation models to represent the logic circuits that interface to
the design. This collection of simulation models is commonly called a test bench.
VHDL has constructs to handle the parallelism inherent in hardware designs, but
these constructs (processes) differ in syntax from the parallel constructs in Ada
(tasks). Like Ada, VHDL is strongly typed and is not case sensitive. In order to
directly represent operations which are common in hardware, there are many
features of VHDL which are not found in Ada, such as an extended set of
Boolean operators including nand and nor. VHDL also allows arrays to be
indexed in either ascending or descending direction; both conventions are used
in hardware, whereas in Ada and most programming languages only ascending
indexing is available.
FPGA:

A field-programmable gate array (FPGA) is an integrated circuit

designed to be configured by a customer or a designer after manufacturing
hence "field-programmable". The FPGA configuration is generally specified
using a hardware description language (HDL), similar to that used for an
application-specific integrated circuit (ASIC) (circuit diagrams were previously
used to specify the configuration, as they were for ASICs, but this is increasingly
rare). Contemporary FPGAs have large resources of logic gates and RAM
blocks to implement complex digital computations. As FPGA designs employ
very fast IOs and bidirectional data buses it becomes a challenge to verify
correct timing of valid data within setup time and hold time. Floor planning
enables resources allocation within FPGA to meet these time constraints.
FPGAs can be used to implement any logical function that an ASIC could
perform. The ability to update the functionality after shipping, partial re-
configuration of a portion of the design and the low non-recurring engineering
costs relative to an ASIC design (notwithstanding the generally higher unit cost),
offer advantages for many applications.

Gate level modeling for verilog

A logic network can be modeled using continuous assignments or switches and

logic gates. Gates and continuous assignments serve different modeling
purposes and it is important to appreciate the differences between them in order
to achieve the right balance between accuracy and efficiency in Verilog-XL.
Modeling with switches and logic gates has the following advantages:

Gates provide a much closer one to one mapping between the actual
circuit and the network model.
There is no continuous assignment equivalent to the bidirectional transfer
gate.
A limitation of those nets declared with the keyword vectored affects gates and
switches as well as continuous assignments. Individual bits of vectored nets
cannot be driven; thus, gates and switches can only drive scalar output nets. If
you declare a multi-bit net as vectored and you drive individual bits of it, Verilog-
XL will display a compilation error message. If you do not declare a multi-bit net
as vectored, Verilog-XL handles it as a vector except in the following cases. A
multi-bit net is handled as a scalar if:

Part of the vector is driven by a gate or switch.

Part of the vector is assigned a value with a continuous assignment.

Behavioral Model:

Behavioral level describes the system the way it behaves instead of a lower
abstraction of its connections. Behavioral model describes the relationship
between the input and output signals. The description can be a Register
Transfer Level (RTL) or Algorithmic (set of instruction) or simple Boolean
equations.

Register Transfer Level:

RTL typically represents data flow within the systems like data flow between
registers. RTL is mostly used for design of combinational logics.

Algorithmic Level:

In this method, specific instruction set of statements define the sequence of

operations in the system. Algorithmic level is mostly used for design of
sequential logics.
Structural Model:

Structural level describes the systems as gates or component block

interconnected to perform the desired operations. Structural level is primarily the
graphical representation of the digital system and so it is closer to the actual
physical representation of the system.

VHDL Programming Structure:

Entity and Architecture are the two main basic programming structures in VHDL.

Entity: Entity can be seen as the black box view of the system. We define the
inputs and outputs of the system which we need to interface.

Entity ANDGATE is

Port (A: in std_logic;

B: in std_logic;

Y: out std_logic);

End entity ANDGATE;

Entity name ANDGATE is given by the programmer, each entity must have a
name. There are certain naming conventions which will be explained later in the
tutorial.
 INTRODUCTION TO XILINX

Xilinx software:

It is an American technology company, primarily a supplier of programmable

logic devices. It is known for inventing the field programmable gate array
(FPGA) and as the first semiconductor company with a fabless manufacturing
model. Founded in Silicon Valley in 1984, the company is headquartered in San
Jose, California, with additional offices in Longmont, Colorado; Dublin, Ireland;
Singapore; Hyderabad, India; Beijing, China; Shanghai, China and Tokyo,
Japan.

Xilinx designs, develops and markets programmable logic products,

including integrated circuits (ICs), software design tools, predefined system
functions delivered as intellectual property (IP) cores, design services, customer
training, field engineering and technical support.Xilinx sells both FPGAs and
CPLDs for electronic equipment manufacturers in end markets such as
communications, industrial, consumer, automotive and data processing.Xilinx
introduced new high capacity 3D FPGAs, including Virtex-7 2000T and Virtex-7
H580T products, these devices began to outpace the capacity of Xilinxs design
software, which led the company to completely redesign its tool set. The result
was the introduction of the Vivado Design Suite, which reduces the time needed
for programmable logic and I/O design, and speeds systems integration and
implementation compared to the previous software.

Kintex:

The Kintex-7 family is the first Xilinx mid-range FPGA family that the company
claims delivers Virtex-6 family performance at less than half the price while
consuming 50 percent less power. The Kintex family includes high-performance
12.5 Gbit/s or lower-cost optimized 6.5 Gbit/s serial connectivity, memory, and
logic performance required for applications such as high volume 10G optical
wired communication equipment, and provides a balance of signal processing
performance, power consumption and cost to support the deployment of Long
Term Evolution (LTE) wireless networks.

Artix:

The Artix-7 family delivers 50 percent lower power and 35 percent lower cost
compared to the Spartan-6 family and is based on the unified Virtex-series
architecture. Xilinx claims that Artix-7 FPGAs deliver the performance required
to address cost-sensitive, high-volume markets previously served by ASSPs,
ASICs, and low-cost FPGAs. The Artix family is designed to address the small
form factor and low-power performance requirements of battery-powered
portable ultrasound equipment, commercial digital camera lens control, and
military avionics and communications equipment.

Zynq:

The Zynq-7000 family addresses high-end embedded-system applications, such

as video surveillance, automotive-driver assistance, next-generation wireless,
and factory automation. Zynq-7000 integrate a complete ARM Cortex-A9
MPCore-processor-based 28 nm system. The Zynq architecture differs from
previous marriages of programmable logic and embedded processors by
moving from an FPGA-centric platform to a processor-centric model. The new
Zynq-7000 product family posed a key challenge for system designers, because
Xilinx ISE design software had not been developed to handle the capacity and
complexity of designing with an FPGA with an ARM core. Xilinxs new Vivado
Design Suite addressed this issue, because the software was developed for
higher capacity FPGAs, and it included high level synthesis functionality that
allows engineers to compile the co-processors from a C-based description.
Spartan:

The Spartan series targets applications with a low-power footprint, extreme cost
sensitivity and high-volume. The Spartan-6 family is built on a 45-nanometer
[nm], 9-metal layer, dual-oxide process technology. The Spartan-6 was
marketed in 2009 as a low-cost solution for automotive, wireless
communications, flat-panel display and video surveillance applications.

Model sim:

Mentor Graphics ModelSim ME HDL Simulator is a source-level verification tool,

allowing you to verify HDL code line by line. You can perform simulation at all
levels: behavioral (pre-synthesis), structural (post-synthesis), and back-
annotated, dynamic simulation. Coupled with the most popular HDL debugging
capabilities in the industry, ModelSim ME is known for delivering high
performance, ease of use, and outstanding product support. An easy-to-use
graphical user interface enables you to quickly identify and debug problems,
aided by dynamically updated windows. For example, selecting a design region
in the Structure window automatically updates the Source, Signals, Process,
and Variables windows. These cross linked ModelSim windows create an easy-
to-use debug environment. Once a problem is found, you can edit, recompile,
and re-simulate without leaving the simulator. ModelSim ME fully supports
current VHDL and Verilog language standards. You can simulate behavioral,
RTL, and gate-level code separately or simultaneously. ModelSim supports all
Microsemi FPGA libraries, ensuring accurate timing simulations. The
comprehensive user interface makes efficient use of desktop real estate. The
intuitive arrangement of interactive graphical elements (windows, toolbars,
menus, etc.) makes it easy to view and access the many powerful capabilities of
ModelSim. The result is a feature-rich user interface that is easy to use and
quickly mastered.
 INTRODUCTION TO VLSI HARDWARE

The CoolRunner-II 1.8V CPLD family leads the industry with its high
performing, low power capabilities. Enhanced with revolutionary features such
as DataGATE, advance I/Os and the industry's smallest form factor packaging,
CoolRunner-II CPLDs deliver the ultimate system solution for today's designing
challenges

Enhanced design security

Only CoolRunner-II CPLDs provide an unprecedented four levels of design

security that guard against pattern theft.

Designs can be secured during programming to prevent either overwriting

or pattern theft via readback

Electrical or visual detection of configuration patterns is eliminated with

four new levels of on-chip security

Electrical or laser tampering causes the device to automatically lock down

Protection is buried deeply within the device making it virtually

undetectable

DataGATE signal blocking

The CoolRunner-II architecture, with its all-digital core, requires far less
power than the older CPLD technologies that use power-hungry analog
sense amplifiers.

Permits input signal blocking, stops input switching, and reduces power.

Power management (duty cycle, clock input and input pin)

Block input pins during insertion with hot plugging

 Block sections of logic and snapshot signals with latches through
debugging

Improve security by blocking access for various on stored code inside the
device

Employ the features of FZP technology to further advanced CoolRunner-II

CPLDs as the low power standard

DataGATE enables CoolRunner-II to be a small fraction of the system

power consumption -- no other CPLD can do this!

Input hysteresis and programmable grounds

Input hysteresis provides designers with a tool to minimize external

components. Whether using the inputs to create a clock, or reducing the
need for external buffers to sharpen up an input signal, CoolRunner-II
CPLD inputs provide designers with a flexible and powerful features:

Improved noise immunity

Reduced power consumption

Superior signal integrity

Clock Divider

Clock Divider improves power savings by providing clock division at

standard values. CoolRunner-II CPLDs give the designer unsurpassed
clock management features that enable an easy to implement total clock
management solution.

Gives solid clock division without using macrocells

Duty cycle improvement

Available in large densities (128 macrocells and above)

Very low lag ...typically 50 ps!

CoolCLOCK

CoolCLOCK is a combination clock divider and clock doubler that divides

the incoming clock by two and then doubles the clock at the output level
to maintain the same performance while reducing the internal power
consumption.

Combines clock divider and doubler

Divides incoming clock by 2

Reduces overall clocking power

DualEDGE Flip-Flop

The DualEDGE Flip-Flop capability increases the effective synchronous

operation rate of any design up to the bandwidth limits of the device. In
other words, you can operate any sequential design twice as fast for a
given clock rate, or do the same amount of processing for 1/2 the external
clock frequency.

Distributes divided clock globally then double locally at macrocell

 Use 2x clocking for double data rate applications

No additional insertion delay

Available in all CoolRunner-II CPLDs

Multiple LVCMOS, HSTL, SSTL I/O

You can easily create standard chip-to-chip and chip-to-memory interfaces

and thus remove discrete interface devices from your system. This saves
you money and increases your system reliability.

LVTTL and LVCMOS for standard chip-to-chip interfacing

SSTL and HSTL for standard chip-to-memory interfacing

Figure 1: I/O Performance and Flexibility (*1.5V inputs need hysteresis)

Small form factor packaging

Xilinx leads the way in advanced package innovation by offering two new,
ultra small form-factor, Quad Flat no-lead (QF) packages to the popular full
line-up of Chip Scale Packages (CP).

Maximum board space savings

Lower cost QF32 package only requires 25mm2 of board space

Simplifies board routing and allowing smaller overall end-products

Perfect for handheld and other space constrained applications that need
32 or 64 macrocell CPLDs in the smallest possible space.

CoolRunner-II offers the newest 0.5mm pitch QF and CP packages for the
broadest selection of low cost, small form-factor packages at 1.8 volts from 21 to
117 I/O.
Internal Logical Diagram
Programming

The programming data sequence is delivered to the device using either Xilinx
iMPACT software and a Xilinx download cable, a third-party JTAG development
system, a JTAG-compatible board tester, or a simple microprocessor interface
that emulates the JTAG instruction sequence. The iMPACT software also
outputs serial vector format (SVF) files for use with any tools that accept SVF
format, including automatic test equipment. See CoolRunner-II CPLD
Application Notes for more information on how to program.

In System Programming

All CoolRunner-II CPLD parts are 1.8V in system programmable. This means
they derive their programming voltage and currents from the 1.8V VCC (internal
supply voltage) pins on the part. The VCCIO pins do not participate in this
operation, as they might assume another voltage ranging as high as 3.3V down
to 1.5V (however, all VCCIO, VCCINT, VCCAUX, and GND pins must be
connected for the device to be programmed, and operate correctly). A 1.8V VCC
is required to properly operate the internal state machines and charge pumps
that reside within the CPLD to do the nonvolatile programming operations. I/O
pins are not in user mode during JTAG programming; they are held in 3-state
with a weak pullup. The JTAG interface buffers are powered by a dedicated
power pin, VCCAUX, which is independent of all other supply pins. VCCAUX
must be connected. Xilinx software is provided to deliver the bitstream to the
CPLD and drive the appropriate IEEE 1532 protocol. To that end, there is a set
of IEEE 1532 commands that are supported in the CoolRunner-II CPLD parts.
Programming times are less than one second for 32 to 256 macrocell parts.
Programming times are less than four seconds for 384 and 512 macrocell parts.
Programming of CoolRunner-II CPLDs is only guaranteed when operating in the
commercial temperature and voltage ranges as defined in the device-specific
data sheets.
PARTIAL CODE

-- Generation of FILTER input

Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.math_real.all;
use ieee.numeric_std.all;

entity sig_shap_ckt is
port(clk,clr : in std_logic;
op1:out std_logic);
end entity sig_shap_ckt;

architecture behave of sig_shap_ckt is

signal counter1 : std_logic_vector(3 downto 0);

signal temp, bus1,bus2 : std_logic_vector(2 downto 0);
signal dcd, lat_dcd : std_logic;
signal asig : real;
signal sigout : std_logic;

begin
----------------------------------------------------
--Generation of analog Signal with a LUT
----------------------------------------------------
a2: process(clr,clk,lat_dcd)
begin
if clr='1' or lat_dcd='1' then
counter1<="0000";
elsif rising_edge(clk) then
counter1<= counter1+1;
end if;
end process a2;

dcd <= ( counter1(3) and counter1(2) and (not counter1(1)) and ( not
counter1(0)));

a3 : process(clk,clr)
begin
if clr='1' then
lat_dcd <='0';
elsif rising_edge(clk) then
lat_dcd<=dcd;
end if;
end process a3;

--a4 : process(counter1,clr)
-- begin
-- case counter1 is
-- when "0000" | "1100" => asig <= 0.50; --0.010;
-- when "0001" | "1011" => asig <= 1.00; --0.020;
-- when "0010" | "1010" => asig <= 1.50; --0.030;
-- when "0011" | "1001" => asig <= 2.00; --0.040;
-- when "0100" | "1000" => asig <= 2.20; --0.050;
-- when "0101" | "0111" => asig <= 2.50; --0.060;
-- when "0110" => asig <= 3.00; --0.070;
-- when others => asig <= 0.000;
-- end case;
-- end process a4;

a4 : process(counter1,clr)
begin
case counter1 is
when "0000" | "1100" => asig <= 0.50; --0.010;
when "0001" | "1011" => asig <= 1.00; --0.020;
when "0010" | "1010" => asig <= 1.50; --0.030;
when "0011" | "1001" => asig <= 2.00; --0.040;
when "0100" | "1000" => asig <= 2.20; --0.050;
when "0101" | "0111" => asig <= 2.50; --0.060;
when "0110" => asig <= 3.00; --0.070;
when others => asig <= 0.000;
end case;
end process a4;

---------------------------------------------------
-- SIGNAL SHAPING OUTPUT
---------------------------------------------------
a5 : process(asig)
begin
if clr='1' then
 sigout<='0';
else if (asig > 2.0) then
sigout <='1';
else
sigout <='0';
end if;
end if;
end process a5;

end behave;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity SineCosineFIR is
port (
clock: in std_logic;
nd : in std_logic;
sine: OUT std_logic_VECTOR(15 downto 0);
cosine: OUT std_logic_VECTOR(15 downto 0);
rfd: OUT std_logic;
rdy: OUT std_logic;
FIR : OUT std_logic_VECTOR(35 downto 0));

end SineCosineFIR;
architecture Behavioral of SineCosineFIR is
component FIRFILTER is
port (clk: IN std_logic;
nd : in std_logic;
rfd: OUT std_logic;
rdy: OUT std_logic;
din: IN std_logic_VECTOR(15 downto 0);
dout: OUT std_logic_VECTOR(35 downto 0));
end component;

component SineCosine is
port ( clock: in std_logic;
sine: OUT std_logic_VECTOR(15 downto 0);
cosine: OUT std_logic_VECTOR(15 downto 0));
end component;

signal sinetemp: std_logic_VECTOR(15 downto 0);

begin

sine <= sinetemp;

u1: SineCosine port map (

clock => clock,
sine => sinetemp,
cosine => cosine);

u2: FIRFILTER port map(

 clk => clock,
nd => nd,
rfd => rfd,
rdy => rdy,
din => sinetemp,
dout => FIR
);

end Behavioral;
SIMULATION RESULTS

One Stage Filter Block

Signal Shaping Circuit
Frequency Analyzer Result
DATA FLOW DIAGRAMS