PRODUCT PROFILE RSCAD V5 The new and improved RTDS Simulator software Technologies Released in August 2016, RSCAD Version 5 offers many new advantages to users of the RTDS® Simulator. V5 includes a facility for simulating distribution networks, a component for streaming IEC 61850 Sampled Values via new FPGA-based hardware, and is built on an exciting new compiler which will make RSCAD much easier to maintain and enhance moving forward. RSCAD V5 is compatible with racks containing PBS and/or GPC Processor Cards. New and Improved Compiler Rewritten, simplified compiler takes advantage of consistent data structure for each component The largest and most complex part of the code that sits under the graphical user interface of the RTDS Simulator is the RTDS compiler. The compiler puts together the executable code and associated data that is sent to the processors and memory on the RTDS Simulator hardware for each simulation case and is a critical part of every simulation. AlLof the power system and control system components in RSCAD were originally hand-coded in assembly language. New code was added to the compiler each time a new power system ar control system model was added to RSCAD. With the introduction of the new and powerful processors for the RTDS Simulator, it became possible to write models in a higher level language, typically C, and use a C compiler to generate the executable code modules that could be run as part of the simulation. RSCAD was then enhanced to include the CBuilder module, in which users could create custom components. ‘As mare and more models in the RSCAD library were developed using the CBuilder tool, the requirements of the RTOS compiler changed. CBuilder created the executable code and associated data in a consistent way for each model so that the RTDS compiler could handle those new components in a general way without the requirement to add special code for each new model. Once all of the power system and control system models were imported into CBuilder, it became possible to re-write the compiler and take advantage of the consistent data structure for each component, thus greatly simplifying the compiler. The new compiler under RSCAD VS and the availability of all power system and control system models in a high level language makes it easier to maintain and enhance the RTOS software going forward. Small timestep components remain in assembly code, but will be converted to CBuilder in the future. Increasing Backplane Transfers and Removing Hard Limits Many maximum quantities now depend on available resources rather than fixed hard limits ‘The number of variables that can be communicated over the rack backplane has been increased from 1000 in V4 to 2000 in V5 for racks that contain only PBS cards. Anumber of hard limits have also been removed in RSCAD V5, including (but not limited to] number of G-matrix overlays, passed G-values, current injections, switches per network solution, and controls components per Draft case. Limits still exist in V5, but depend entirely upon available resources rather than fixed hard limits. Learn more at www.rtds.com, or contact us: POSER acu ee ea eePRODUCT PROFILE RSCAD V5 The new and improved RTDS Simulator software Technologies Distribution Mode Simulates several hundred to over a thousand nodes in one tightly coupled area RSCAD Version 5 includes Distribution Mode, @ new feature allowing users to simulate large distribution networks using the RTDS Simulator. These networks can include several hundred to over a thousand nodes, and are typically made up of short lines and cables which do not allow the circuit to be separated into subsystems. With Distribution Mode, these very large networks can now be simulated in one tightly coupled area. Distribution Mode relies on the distribution feeder being radial in structure, which creates a highly sparse admittance matrix compared to non-distribution cases and reduces the computational burden on the network solution. Furthermore, the simulation timestep for Distribution Mode may be in the range of 150-200 microseconds to provide more time for the calculation of the network solution. The combination of the highly sparse admittance matrix as well as the larger timestep allow a vastly larger number of nodes to be modelled in one subsystem. The Distribution Mode component library is a limited subset of components from the RSCAD library. It does not include travelling wave transmission line or cable madels, synchronous machine models, or switching models for power electronics. Power electronics associated with Distributed Energy Resources can be represented using averaging models. GTFPGA-SV for IEC 61850 Sampled Values Streaming via FPGA Significantly increases the number of SV data streams that can be output from the RTDS Simulator The GTFPGA-SV component provides IEC 61850-9-2LE and IEC 61869-9 Sampled Values [SV| communications using the GTFPGA Unit hardware. The GTFPGA Unit is connected to the RTDS Simulator via a fiber optic cable, which runs from the rear of the GTFPGA Unit to one GTIO port on the rear of a PBS Processor Card. It can be connected to external IEDs through the sixteen Ethernet ports on the front of the GTFPGA Unit, When using the |= 61850-9-2LE configuration: When using the |EC 1869-9 configuration: © 16 data streams for up to 4 current and 4 voltage © 16 data streams for up to 24 quantities, at a rate of 80 channels, at a rate of 80 samples/cycle (1 ASDU] or samples/cycle (1 ASDU), 9 samples/cycle (1 ASDU), or 256 samples/cycle (8 ASDU) 4,800 Hz (2 ASDU) © 16 data streams for up to 9 quantities, at a rate of 256 When being used for SV, the GTFPGA Unit may eamnlesseves (A200) on 1004 eADSL) be connected to PBS Processor Cards only. In IEC 61869-9 mode, the quantities can be currents, voltages, or time-delay. The time-delay channel is the first channel in a Chinese National Standard merging unit SV data stream. PE a ead SCS Dae un eC ees ee eC Re