CMOS Circuit and Logic Design

1.1. Introduction
To study the following two areas of CMOS design:
Circuit (structural) design
Layout (physical) design
The goal to achieve:
Functional correctness
Smallest area, highest speed, lowest power consumption

1.2. CMOS Logic Gate Design

To achieve correct operation of any integrated logic gate, the following
two constraints must be satisfied:
Functional constraint
Temporal (timing) constraint
For COMS logic the following effects can result in incorrect
functioning of a gate:
Insufficient power supply (may due to noise on power/ground
bus)
Noise on gate inputs
Faulty transistors
Incorrect connections to transistors
Incorrect ratios in ratioed logic
Charge sharing or incorrect clocking in dynamic gates
Functional correctness versus logic design styles
Complementary CMOS gate (circuit) will always function
correctly.
The function of ratioed or dynamic gates (circuits) may be
compromised by poor design, sloppy layout, and unforeseen
noise.
 The timing of a circuit is determined by the delay time of the slowest
(longest ) paths in the circuit. These paths are called critical paths.
A path is defined as an alternating sequence of logic gates and signal
nets from source to sink. The following objects can be served as a
source:
primary input
memory element (latch or flip-flop)
The following object can serve as a sink:
primary output
memory element (latch or flip-flop)
The critical paths can be affected at four main levels:
The architectural level
The RTL/logic level
The circuit level
the layout level

ASIC
An Application Specific Integrated Circuit (ASIC) is a semiconductor
device designed especially for a particular customer (versus a Standard
Product, which is designed for general use by any customer)
1 The three major categories of ASIC Technology are :
Gate Array-Based
Standard Cell-Based
Full custom

The Characteristics of ASICs

The remarks that follow further discuss some trade-offs of
ASICs with respect to the following categories:
Complexity
Silicon Efficiency
Design Risks
Prototype Turnaround
 NRE
CAD / CAE Support
Performance

Digital design process

Design complexity increasing rapidly
o Increased size and complexity
o CAD tools are essential
The present trend
o Standardize the design flow
What is design flow?
Standardized design procedure, starting from the design idea down to
the actual implementation (using FPGA, ASIC,)
Encompasses many steps
o Specification
o Synthesis design translation from the specification to netlist
o Simulation.. check the synthesized ckt is correct or not
o Layout .think how to place the components
o Testability analysis
o And many more..
MOS transistors are four terminal devices: source ,
drain, gate and substrate. The gate contros
whether a current flow between source and drain can be established. Source and drain
are physically equivalent and their name assignment depends on the direction of current
flow. Substrate acts as the fourth terminal. A PMOS transistor has a negatively doped
substrate while an NMOS transistor has a positively doped substrate. The current flow
between source and drain is mainly formed by the movement of majority carriers which
are electrons for an NMOS transistor and holes for a PMOS transistor. The terminal
supplying the majority carrier is called source, while the terminal receiving the majority
carriers is called Drain. In general, there is no other conducting path in a MOS
transistor except the path between source and drain. That is there is no conducting path
between source and drain.
When the gate voltage exceeding a threshold voltage V tn(Vtp) for an NMOS(PMOS)
transistor, the transistor starts to conduct and there is a sign cant current flow between
its source and drain. Let Vgs denote the voltage between the gate and the source. Vds
and Ids denote respectively the voltage and current between its drain and source, Vdd
denote the power supply, and Vss denote the ground.