Interrupt is the method of creating a temporary halt during program execution and

allows peripheral devices to access the microprocessor. The microprocessor responds to

that interrupt with an ISR (Interrupt Service Routine), which is a short program to instruct
the microprocessor on how to handle the interrupt.
The following image shows the types of interrupts we have in a 8086 microprocessor
Hardware Interrupts
Hardware interrupt is caused by any peripheral device by sending a signal through a
specified pin to the microprocessor.
The 8086 has two hardware interrupt pins, i.e. NMI and INTR. NMI is a non-maskable
interrupt and INTR is a maskable interrupt having lower priority. One more interrupt pin
associated is INTA called interrupt acknowledge.
NMI
It is a single non-maskable interrupt pin (NMI) having higher priority than the maskable
interrupt request pin (INTR) and it is of type 2 interrupt.
When this interrupt is activated, these actions take place
Completes the current instruction that is in progress.
Pushes the Flag register values on to the stack.
Pushes the CS (code segment) value and IP (instruction pointer) value of the return
address on to the stack.
IP is loaded from the contents of the word location 00008H.
CS is loaded from the contents of the next word location 0000AH.
Interrupt flag and trap flag are reset to 0.
INTR
The INTR is a maskable interrupt because the microprocessor will be interrupted only if
interrupts are enabled using set interrupt flag instruction. It should not be enabled using
clear interrupt Flag instruction.
The INTR interrupt is activated by an I/O port. If the interrupt is enabled and NMI is
disabled, then the microprocessor first completes the current execution and sends 0 on
INTA pin twice. The first 0 means INTA informs the external device to get ready and
during the second 0 the microprocessor receives the 8 bit, say X, from the programmable
interrupt controller.
These actions are taken by the microprocessor
First completes the current instruction.
Activates INTA output and receives the interrupt type, say X.
Flag register value, CS value of the return address and IP value of the return address
are pushed on to the stack.
IP value is loaded from the contents of word location X 4
CS is loaded from the contents of the next word location.
Interrupt flag and trap flag is reset to 0
Software Interrupts
Some instructions are inserted at the desired position into the program to create
interrupts. These interrupt instructions can be used to test the working of various interrupt
handlers. It includes
INT- Interrupt instruction with type number
It is 2-byte instruction. First byte provides the op-code and the second byte provides the
interrupt type number. There are 256 interrupt types under this group.

Its execution includes the following steps

Flag register value is pushed on to the stack.
CS value of the return address and IP value of the return address are pushed on to
the stack.
IP is loaded from the contents of the word location type number 4
CS is loaded from the contents of the next word location.
Interrupt Flag and Trap Flag are reset to 0
The starting address for type0 interrupt is 000000H, for type1 interrupt is 00004H similarly
for type2 is 00008H and so on. The first five pointers are dedicated interrupt pointers.
i.e.
TYPE 0 interrupt represents division by zero situation.
TYPE 1 interrupt represents single-step execution during the debugging of a
program.
TYPE 2 interrupt represents non-maskable NMI interrupt.
TYPE 3 interrupt represents break-point interrupt.
TYPE 4 interrupt represents overflow interrupt.
The interrupts from Type 5 to Type 31 are reserved for other advanced microprocessors,
and interrupts from 32 to Type 255 are available for hardware and software interrupts.
INT 3-Break Point Interrupt Instruction
It is a 1-byte instruction having op-code is CCH. These instructions are inserted into the
program so that when the processor reaches there, then it stops the normal execution of
program and follows the break-point procedure.
Its execution includes the following steps
Flag register value is pushed on to the stack.
CS value of the return address and IP value of the return address are pushed on to
the stack.
IP is loaded from the contents of the word location 34 = 0000CH
CS is loaded from the contents of the next word location.
Interrupt Flag and Trap Flag are reset to 0
INTO - Interrupt on overflow instruction
It is a 1-byte instruction and their mnemonic INTO. The op-code for this instruction is CEH.
As the name suggests it is a conditional interrupt instruction, i.e. it is active only when the
overflow flag is set to 1 and branches to the interrupt handler whose interrupt type
number is 4. If the overflow flag is reset then, the execution continues to the next
instruction.
Its execution includes the following steps
Flag register values are pushed on to the stack.
 CS value of the return address and IP value of the return address are pushed on to
the stack.
IP is loaded from the contents of word location 44 = 00010H
CS is loaded from the contents of the next word location.
Interrupt flag and Trap flag are reset to 0

An interrupt is a special condition that arises during the working of a microprocessor. The
microprocessor services it by executing a subroutine called Interrupt Service Routine (ISR).
There are three sources of interrupts for 8086:
1. Hardware interrupt-
These interrupts occur as signals on the external pins of the microprocessor. 8086
has two pins to accept hardware interrupts, NMI and INTR.
2. Software interrupt-
These interrupts are caused by writing the software interrupt instruction INT n where
n can be any value from 0 to 255 (00H to FFH). Hence all 256 interrupts can be
invoked by software.
3. Error conditions (Exception or types)-
8086 is interrupted when some special conditions occur while executing certain
instructions in the program. Example: An error in division automatically causes the
INT 0 interrupt.
Interrupt Vector Table (IVT):
 1. The interrupt vector (or interrupt pointer) table is the link between an interrupt type
code and the procedure that has been designated to service interrupts associated
with that code. 8086 supports total 256 types i.e. 00H to FFH.
2. For each type it has to reserve four bytes i.e. double word. This double word pointer
contains the address of the procedure that is to service interrupts of that type.
3. The higher addressed word of the pointer contains the base address of the segment
containing the procedure. This base address of the segment is normally referred as
NEW CS.
4. The lower addressed word contains the procedures offset from the beginning of the
segment. This offset is normally referred as NEW IP.
5. Thus NEW CS: NEW IP provides NEW physical address from where user ISR routine
will start.
6. As for each type, four bytes (2 for NEW CS and 2 for NEW IP) are required; therefore
interrupt pointer table occupies up to the first 1k bytes (i.e. 256 x 4 = 1024 bytes) of
low memory.
7. The total interrupt vector table is divided into three groups namely,
A. Dedicated interrupts (INT 0..INT 4)
B. Reserved interrupts (INT 5..INT 31)
C. Available interrupts (INT 32..INT 225)

A. Dedicated interrupts (INT 0..INT 4):

1. INT 0 (Divide Error)-
o This interrupt occurs whenever there is division error i.e. when the result of a
division is too large to be stored. This condition normally occurs when the
divisor is very small as compared to the dividend or the divisor is zero.
o Its ISR address is stored at location 0 x 4 = 00000H in the IVT.
2. INT 1 (Single Step)-
o The microprocessor executes this interrupt after every instruction if the TF is
set.
o It puts microprocessor in single stepping mode i.e. the microprocessor pauses
after executing every instruction. This is very useful during debugging.
o Its ISR generally displays contents of all registers. Its ISR address is stored at
location 1 x 4 = 00004H in the IVT.
3. INT 2 (Non mask-able Interrupt)-
o The microprocessor executes this ISR in response to an interrupt on the NMI
(Non mask-able Interrupt) line.
o Its ISR address is stored at location 2 x 4 = 00008H in the IVT.
4. INT 3 (Breakpoint Interrupt)-
o This interrupt is used to cause breakpoints in the program. It is caused by
writing the instruction INT 03H or simply INT.
o It is useful in debugging large programs where single stepping is efficient.
o Its ISR is used to display the contents of all registers on the screen. Its ISR
address is stored at location 3 x 4 = 0000CH in the IVT.
5. INT 4 (Overflow Interrupt)-
o This interrupt occurs if the overflow flag is set and the microprocessor
executes the INTO (Interrupt on Overflow) instruction.
o It is used to detect overflow error in signed arithmetic operations.
o Its ISR address is stored at location 4 x 4 = 00010H in the IVT.
B. Reserved interrupts (INT 5..INT 31):
1. These levels are reserved by Intel to be used in higher processors like 80386,
Pentium etc. They are not available to the user.
C. Available interrupts (INT 32..INT 225):
1. These are user defined, software interrupts.
2. ISRs for these interrupts are written by the users to service various user defined
conditions.
3. These interrupts are invoked by writing the instruction INT n. Its ISR address is
obtained by the microprocessor from location n x 4 in the IVT.
Hardware Interrupts:
1. NMI (Non mask-able interrupt)-
o This is a non-mask-able, edge triggered, high priority interrupt.
o On receiving an interrupt on NMI line, the microprocessor executes INT
o Microprocessor obtains the ISR address from location 2 x 4 = 00008H from the
IVT.
o It reads 4 locations starting from this address to get the values for IP and CS to
execute the ISR.
2. INTR-
This is a mask-able, level triggered, low priority interrupt.
On receiving an interrupt on INTR line, the microprocessor executes 2 INTA pulses.
1st INTA pulse The interrupting device calculates (prepares to send) the vector
number.
2nd INTA pulse The interrupting device sends the vector number N to the
microprocessor.
Now microprocessor multiplies N x 4 and goes to the corresponding location in the IVT to
obtain the ISR address. INTR is a mask-able interrupt.
It is masked by making IF = 0 by software through CLI instruction.
It is unmasked by making IF = 1 by software through STI instruction.