sensors

Article
All-Digital Time-Domain CMOS Smart Temperature
Sensor with On-Chip Linearity Enhancement
Chun-Chi Chen *, Chao-Lieh Chen and Yi Lin
Department of Electronic Engineering, National Kaohsiung First University of Science and Technology,
Kaohsiung 81146, Taiwan; frederic@nkfust.edu.tw (C.-L.C.); u0252807@nkfust.edu.tw (Y.L.)
* Correspondence: ccchen@nkfust.edu.tw; Tel.: +886-7-6011-000 (ext. 2513)

Academic Editor: Vittorio M. N. Passaro

Received: 17 December 2015; Accepted: 26 January 2016; Published: 30 January 2016

Abstract: This paper proposes the first all-digital on-chip linearity enhancement technique for
improving the accuracy of the time-domain complementary metal-oxide semiconductor (CMOS)
smart temperature sensor. To facilitate on-chip application and intellectual property reuse, an
all-digital time-domain smart temperature sensor was implemented using 90 nm Field Programmable
Gate Arrays (FPGAs). Although the inverter-based temperature sensor has a smaller circuit area
and lower complexity, two-point calibration must be used to achieve an acceptable inaccuracy.
With the help of a calibration circuit, the influence of process variations was reduced greatly for
one-point calibration support, reducing the test costs and time. However, the sensor response still
exhibited a large curvature, which substantially affected the accuracy of the sensor. Thus, an on-chip
linearity-enhanced circuit is proposed to linearize the curve and achieve a new linearity-enhanced
output. The sensor was implemented on eight different Xilinx FPGA using 118 slices per sensor in
each FPGA to demonstrate the benefits of the linearization. Compared with the unlinearized version,
the maximal inaccuracy of the linearized version decreased from 5 C to 2.5 C after one-point
calibration in a range of 20 C to 100 C. The sensor consumed 95 W using 1 kSa/s. The proposed
linearity enhancement technique significantly improves temperature sensing accuracy, avoiding
costly curvature compensation while it is fully synthesizable for future Very Large Scale Integration
(VLSI) system.

Keywords: CMOS; smart temperature sensor; time domain; linearity enhancement; field
programmable gate array (FPGA)

1. Introduction
Thermal management systems (TMSs) are frequently used to manage the temperature of devices
and equipment to prevent thermal damage [1]. The lifespans of components decrease when their
temperature surpasses the safe temperature range, eventually causing damage and system breakdown.
Temperature sensors are used to monitor temperature and send temperature information to TMSs. To
ensure cost effectiveness and facilitate direct temperature monitoring, sensors can be mounted close to
crucial heat sources and implemented in a complementary metal-oxide semiconductor (CMOS) process
and, thus, be easily integrated with other Very Large Scale Integration (VLSI) circuits. Because of the fast
growth in the circuit density and clock frequency, current VLSI systems, such as microprocessors [13],
suffer from severe challenge in the temperature monitoring and control. Thus, the market demand for
integrated temperature sensors for many industrial and home applications has increased substantially.
Scientists integrate sensors into numerous systems since sensors become essential and tiny while
consuming low energy. For precise monitoring, integrated temperature sensors require careful
calibration to accurately read the temperature before use in TMSs because of process variations
and silicon aging in integrated circuits (ICs).

Sensors 2016, 16, 176; doi:10.3390/s16020176 www.mdpi.com/journal/sensors

Sensors 2016, 16, 176 2 of 13

To produce digital codes for communicating with VLSI systems, analog-to-digital converters
Sensors 2016, 16, 176 2 of 14
(ADCs) have been integrated into temperature sensors to create smart temperature sensors [48].
Temperature sensors based on bipolar junction transistors are utilized to translate the temperature
to a voltage To signal
produce digital codes to
proportional forthe
communicating with VLSI systems,
absolute temperature (PTAT),analog-to-digital
and then an ADC converters
is used for
(ADCs) have been integrated into temperature sensors to create smart temperature sensors [48].
digital temperature readings. Sophisticated circuits using additional on-chip calibration techniques
Temperature sensors based on bipolar junction transistors are utilized to translate the temperature
are frequently
to a voltage used to ensure
signal accuracy
proportional to theand full compatibility
absolute with the
temperature (PTAT), andstandard
then an ADCCMOS process
is used for [28].
Excellent performance,
digital specifically,
temperature readings. an extremely
Sophisticated circuitshigh
usingaccuracy
additionalof 0.1 C
on-chip (3) and
calibration a low power
techniques
dissipation of tensused
are frequently of to
microwatts,
ensure accuracy hasand been achieved. Offset
full compatibility with the cancellation
standard CMOS techniques,
process [28].dynamic
C (3) and a low power
element matching [5,7], and linearity enhancement techniques [6,8] are usually used; however, the
Excellent performance, specifically, an extremely high accuracy of 0.1
circuitdissipation
complexity of tens
andof microwatts,
area increases hassubstantially
been achieved.toOffset cancellation techniques,
be unattractive dynamic
to the low-cost element
TMS.
matching [5,7], and linearity enhancement techniques [6,8] are usually used; however, the circuit
Time-domain CMOS smart temperature sensors [919] have been developed to reduce the
complexity and area increases substantially to be unattractive to the low-cost TMS.
circuit area and complexity substantially compared with that of voltage-domain smart temperature
Time-domain CMOS smart temperature sensors [919] have been developed to reduce the circuit
sensors. The
area andfirst CMOSsubstantially
complexity time-domain sensor
compared consisted
with of a temperature-to-pulse
that of voltage-domain smart temperature generator
sensors. with
inverter-based
The first CMOS delaytime-domain
lines and sensor
a time-to-digital
consisted of aconverter (TDC) [9],
temperature-to-pulse as shown
generator with in Figure 1. CMOS
inverter-based
inverters (NOT
delay gates)
lines and have been converter
a time-to-digital used to sense temperature
(TDC) [9], as shown in innovatively
Figure 1. CMOS[919].
invertersThe
(NOTsensor
gates)had an
error of 0.70.9 C after two-point calibration in a range of 0 C100 C. With such simple structure,
have been used to sense temperature innovatively [919]. The sensor had an error of 0.70.9 C
afterchip
two-point calibration in a range accuracy
of 0 C100 C. achieved.
With such simple structure, oscillators
the small chip
the small size and the satisfactory were Inverter-based of which
size and the satisfactory accuracy were achieved. Inverter-based oscillators of which the PTAT
the PTAT period can be transformed into temperature information are frequently implemented in
period can be transformed into temperature information are frequently implemented in time-domain
time-domain temperature sensors. A temperature sensor implemented using two current-starved
temperature sensors. A temperature sensor implemented using two current-starved oscillators reached
oscillators reachedofan
an inaccuracy inaccuracy
1.63.0 of 1.63.0
C in a range of 0100C C in a Another
[10]. range of 0100 Csensor
temperature [10]. with
Another temperature
a differential
sensorPTAT
withdelay a differential PTAT
generator using delay
a linear MOSgenerator
operation using
had an aerror
linear MOS operation
of 0.81.0 C in a range had
of 0 an error of
C to

0.81.0
100CCin a range of 0 C to 100 C [11].
[11].

Figure 1. Architecture
Figure ofoffirst
1. Architecture firsttime-domain smart
time-domain smart temperature
temperature sensor.
sensor.

To eliminate the the

To eliminate burden
burden associated
associatedwith
with full customdesigns,
full custom designs, an an all-digital
all-digital smartsmart temperature
temperature
sensorsensor
implemented
implemented using
using Field FieldProgrammable
Programmable Gate Gate Arrays
Arrays(FPGAs)(FPGAs) waswas proposed
proposed for rapid
for rapid
prototyping [12]. [12].
prototyping As shown
As shown in Figure
in Figure2,2,an
anoscillator composed
oscillator composed of of inverters
inverters is first
is first used used to generate
to generate
the oscillation period (t ) PTAT. To achieve satisfactory sensor resolution,
the oscillation period (td,osc) PTAT. To achieve satisfactory sensor resolution, a time amplifier
d,osc a time amplifier (TA) (TA)
comprising a circulation counter is then used to amplify the td,osc . An adequately wide pulse (t p )
comprising a circulation counter is then used to amplify the td,osc. An adequately wide pulse (tp) is
is obtained using a simple XOR gate. A TDC is composed of the reference period width (tREF ), the
obtained using a simple XOR gate. A TDC is composed of the reference period width (tREF), the
AND gate, and the counter to convert the t p into the digital code. The smart sensor was realized
AND with
gate,140and the counter to convert the t p into the digital code. The smart
logic elements (LEs) in FPGA chips and had an inaccuracy of 1.50.8 C after two-point sensor was realized
with 140 logic elements
calibration in a range(LEs)
of 075 in FPGA chipsthat
C, showing andtime-domain
had an inaccuracy
temperature of sensors
1.50.8areCsuitable
after two-point
for
calibration in a or
cell-based range of 075
all-digital CMOS C,designs.
showing that time-domain
However, temperature
two-point calibration, sensors
which can are suitable
compensate for for
both or
cell-based gain and offsetCMOS
all-digital errors, designs.
needs to be used to reach
However, an acceptable
two-point inaccuracy
calibration, which at the
cancost of test
compensate for
costs and time [912]. One-point calibration halves the test cost and time of two-point
both gain and offset errors, needs to be used to reach an acceptable inaccuracy at the cost of test costs calibration for
high-volume production; thus, it is more attractive in the market.
and time [912]. One-point calibration halves the test cost and time of two-point calibration for
high-volume production; thus, it is more attractive in the market.
with 140 logic elements (LEs) in FPGA chips and had an inaccuracy of 1.50.8 C after two-point
calibration in a range of 075 C, showing that time-domain temperature sensors are suitable for
cell-based or all-digital CMOS designs. However, two-point calibration, which can compensate for
both gain and offset errors, needs to be used to reach an acceptable inaccuracy at the cost of test costs
and time [912]. One-point calibration halves the test cost and time of two-point calibration for
Sensors 2016, 16, 176 3 of 14
high-volume production; thus, it is more attractive in the market.

Figure 2. 2.
Figure Architecture
Architectureofofoscillator-based
oscillator-based smart temperaturesensor.
smart temperature sensor.
Sensors 2016, 16, 176 3 of 13

Another FPGA
Another FPGA version
version with
with one-point
one-point calibration
calibration support
support was
was invented
invented and
and its
its architecture
architecture is is
presented in Figure 3 [13]. The structure of the simple smart temperature sensor is the
presented in Figure 3 [13]. The structure of the simple smart temperature sensor is the same as that of same as that
of [12].
[12]. Differently,
Differently, anan off-chip
off-chip calibration
calibration circuitand
circuit andananadjustable-gain
adjustable-gainTA TA(AGTA)
(AGTA) were
were used
used to to
reduce the
reduce the influence
influenceofofprocess
processvariations.
variations.Thus,
Thus,one-point
one-point calibration cancan
calibration be used to save
be used the test
to save the cost.
test
However, the sensor has poor linearity because of the curvature caused by the CMOS
cost. However, the sensor has poor linearity because of the curvature caused by the CMOS inverter inverter [919].
To overcome
[919]. the problem
To overcome of curvature,
the problem costly off-chip
of curvature, second-order
costly off-chip master curve
second-order fitting
master curvewas usedwas
fitting for
curvature correction to achieve a satisfactory accuracy of 0.70.6 C after one-point calibration in
used for curvature correction to achieve a satisfactory accuracy of 0.70.6 C after one-point
a range of 0100 C [13]. Excluding the SAR-based (successive approximation register) calibration
calibration in a range of 0100 C [13]. Excluding the SAR-based (successive approximation register)
circuit, onlycircuit,
calibration 48 LEsonly
for the simple
48 LEs for smart temperature
the simple sensor weresensor
smart temperature used. were used.

Figure
Figure 3.
3. Architecture
Architecture of
of smart
smart temperature
temperature sensor
sensor with one-point calibration
with one-point calibration support.
support.

A cell-based temperature sensor based on inverters was invented for self-calibration to

A cell-based temperature sensor based on inverters was invented for self-calibration to eliminate
eliminate the influence of process variations [14]. When no second-order master curve fitting was
the influence of process variations [14]. When no second-order master curve fitting was applied, the
applied, the temperature sensor exhibited a substantial inaccuracy of 5.13.4 C after one-point
temperature sensor exhibited a substantial inaccuracy of 5.13.4 C after one-point calibration in a
calibration in a range of 060 C. Without applying the curve fitting, a frequency-based temperature
range of 060 C. Without applying the curve fitting, a frequency-based temperature sensor achieved a
sensor achieved a large inaccuracy of 2.82.9 C after one-point calibration in a range of 40 C to
large inaccuracy of 2.82.9 C after one-point calibration in a range of 40 C to 110 C [15]. Later
110 C [15]. Later research by the same team, a CMOS temperature sensor based on a
research by the same team, a CMOS temperature sensor based on a process-variations-compensated
process-variations-compensated frequency-to-digital converter was proposed [16]. The accuracy
frequency-to-digital converter was proposed [16]. The accuracy was enhanced by linearizing the
was enhanced by linearizing the frequency to digital conversion. Under one-point calibration, the
frequency to digital conversion. Under one-point calibration, the achieved accuracy is scaled 1.5 C
achieved accuracy is scaled1.5 C when measuring from 40 C to 110 C.
when measuring from 40 C to 110 C.
To enhance on-chip linearity without adopting the off-chip second-order master curve fitting,
To enhance on-chip linearity without adopting the off-chip second-order master curve fitting,
two delay lines were used at the cost of two-point calibration for curvature compensation, yielding
two delay lines were used at the cost of two-point calibration for curvature compensation, yielding the
the currently optimal inaccuracy of 0.350.3 C from 0 to 90 C [17]. To ensure acceptable
currently optimal inaccuracy of 0.350.3 C from 0 to 90 C [17]. To ensure acceptable inaccuracy
inaccuracy in wider temperature range operations, another curvature compensation technique that
in wider temperature range operations, another curvature compensation technique that involves
involves using two oscillators was proposed. The sensor adopted two-point calibration to achieve a
maximum inaccuracy of 1.4 C for 40120 C extensive range [18].
Either costly off-chip second-order master curve fitting [13] or a time-consuming analog
linearization technique [17,18] must be adopted to enhance linearity and achieve acceptable
inaccuracy because of the curvature of CMOS inverters. Otherwise, the inaccuracy is substantial
[14,15] or the operating temperature range is limited [12,14]. This study proposes the first all-digital
on-chip linearity enhancement technique. Furthermore, applying the calibration technique
Sensors 2016, 16, 176 4 of 14

using two oscillators was proposed. The sensor adopted two-point calibration to achieve a maximum
inaccuracy of 1.4 C for 40120 C extensive range [18].
Either costly off-chip second-order master curve fitting [13] or a time-consuming analog
linearization technique [17,18] must be adopted to enhance linearity and achieve acceptable inaccuracy
because of the curvature of CMOS inverters. Otherwise, the inaccuracy is substantial [14,15] or the
operating temperature range is limited [12,14]. This study proposes the first all-digital on-chip linearity
enhancement technique. Furthermore, applying the calibration technique described in [13] enables the
fully digital smart temperature sensor to achieve a satisfactory accuracy after one-point calibration for
a wider temperature range. The rest of this paper is organized as follows: Section 2 provides details
on the proposed sensor, including the calibration circuit and the linearity enhancement technique;
Section 3 presents the Experimental results; and finally, Section 4 concludes the paper.

2. Circuit Description

SensorsThe architecture
2016, 16, 176 of the proposed all-digital smart temperature sensor is presented in Figure4 4. It
of 13
comprises a simple smart temperature sensor, a calibration circuit for one-point calibration support,
and a proposed
support, and a linearity-enhanced circuit. The main
proposed linearity-enhanced feature
circuit. The that
main differentiates
feature that thedifferentiates
proposed sensor the
from the time-domain
proposed sensor from thesensors proposedsensors
time-domain in previous studies
proposed in is the firststudies
previous all-digital on-chip
is the linearity
first all-digital
enhancement technique
on-chip linearity proposed
enhancement in this paper.
technique In contrast
proposed with the
in this paper. Instructure
contrast shown
with the in structure
Figure 3,
the calibration circuit is implemented on-chip, and the linearity-enhanced circuit is connected
shown in Figure 3, the calibration circuit is implemented on-chip, and the linearity-enhanced circuit with
the simple version
is connected to linearize
with the the digital
simple version value N(T)
to linearize theand derive
digital a new
value N(T)digital value N'(T).
and derive a newProcess
digital
variation calibration
value N'(T). Process and linearity
variation enhancement
calibration enable improving
and linearity enhancement accuracy
enableand reducingaccuracy
improving the test costs
and
of high-volume production.
reducing the test costs of high-volume production.

Figure 4. Architecture of the proposed all-digital smart temperature sensor.

Figure 4. Architecture of the proposed all-digital smart temperature sensor.

The proposed technique was introduced simply in [19]. The linearity-enhanced circuit and the
The proposed
calibration technique
circuit were was introduced
implemented simplyboard
on one FPGA in [19].
to The linearity-enhanced
off-chip circuit and
calibrate and linearize the
simple
calibration circuit were implemented on one FPGA board to off-chip calibrate and linearize
smart temperature sensors fabricated in a 0.35-m CMOS process. In this paper, the proposed sensor simple
smart temperaturecircuit
with calibration sensors fabricated
and in a 0.35-m circuit
linearity-enhanced CMOS wasprocess. In thisusing
realized paper,the
theFPGA
proposed sensor
boards; a
with calibration circuit and linearity-enhanced
detailed description is provided. circuit was realized using the FPGA boards; a detailed
description is provided.
2.1. Inverter-Based Smart Temperature Sensor and One-Point Calibration Technique
2.1. Inverter-Based Smart Temperature Sensor and One-Point Calibration Technique
As mentioned previously, a CMOS NOT gate composed of a P-channel MOS and a N-channel
As mentioned previously, a CMOS NOT gate composed of a P-channel MOS and a N-channel
MOS transistor can be used for temperature sensing to produce the PTAT delay. This can be
MOS transistor can be used for temperature sensing to produce the PTAT delay. This can be expressed
expressed as [20]
as [20]
2 LC
2LC LL 11 ln(lnp3
3 4V (T )th/ pTq{V
th 4V VDD ) DD q
t NOT
t NOT pTq (T ) (1)
(1)
WC WC
OXOX V
V DDDD (T )
pTq 1 Vth (T )th/ VDD DD
1 V pTq{V

where T, W/L, and CL are the operation temperature, aspect ratio of transistors, and loading
capacitance of the NOT gates, respectively. The temperature relationship of mobility () and
threshold voltage (Vth) are expressed as [21]
T km
Sensors 2016, 16, 176 5 of 14

where T, W/L, and C L are the operation temperature, aspect ratio of transistors, and loading capacitance
of the NOT gates, respectively. The temperature relationship of mobility () and threshold voltage
(Vth ) are expressed as [21]
T km
pTq 0 p q , km 1.2 2.0 (2)
T0
Vth pTq Vth pT0 q ` pT T0 q, 0.5 3mV{ C (3)

where T0 is the reference temperature. Although and Vth are both affected by the temperature, the
thermal influence of t NOT (T) is dominated by [919]. Therefore, the thermal relationship of Vth (T)
can be ignored for simplification, and t NOT (T) can be further expressed as

2LCL T0 km lnp3 4Vth {VDD q 1

t NOT pTq 0 C
km T km (4)
W V
OX DD 1 V {V
th DD T
Sensors 2016, 16, 176 5 of 13

where is a process-dependent factor with nearly temperature independence. In Equation (4), the
gates resembles the NOT gate and can be used to generate an oscillation period PTAT, which is
PTAT delay is dependent on the process variations. Furthermore, the oscillator constructed by the
expressed as
NOT gates resembles the NOT gate and can be used to generate an oscillation period PTAT, which is
km
expressed as td ,osc (T ) 2 k t NOT (T ) 2 k Tkm (5)
td,osc pTq 2 k t NOT pTq 2 k T (5)
where
where kk is
is the
the number
number of of stages
stages in
in the
the oscillator.
oscillator. The
The period
period is
is usually
usually too
too short
short to
to attain
attain aa desired
desired
temperature
temperature resolution, unless k is set to an extremely high value. Thus, a TA with aa gain
resolution, unless k is set to an extremely high value. Thus, a TA with gain ofof n
n was
was
designed to amplify t d,osc and obtain the tp PTAT. Finally, the reference clock (tREF) was used to count
designed to amplify td,osc and obtain the t p PTAT. Finally, the reference clock (tREF ) was used to count
tp
tp to
to output
output the
the sensor
sensor output
output N(T), which can
N(T), which can be
be formulated
formulated as
as

t p (T ) n td ,osc (T ) n km
N (T )t ppTq n td,osc pTq n 2 k T T km (6)
NpTq t t t 2 k T km T km (6)
t REF REF t REFREF t REF
REF

where
where is
is aa factor
factor with with process
process dependence
dependence and and temperature
temperatureinsensitivity
insensitivitybecause
becausen,n,k,k,and REF are
andttREF are
ideally temperature insensitive. The characteristic of N(T) unavoidably resembles
ideally temperature insensitive. The characteristic of N(T) unavoidably resembles that of the NOT gate. that of the NOT
gate. In Equation
In Equation (6), if(6),
km ifiskm
1is(the
1 (the
idealideal value),
value), thenthen
N(T)N(T) is perfectly
is perfectly linear.
linear. However,
However, the the value
value of
of km
km rangers
rangers from from
1.21.2 to 2.0
to 2.0 for for a 0.35-m
a 0.35-m CMOSCMOS process
process [21],[21], indicating
indicating that that the transfer
the transfer curvecurve of
of N(T)
N(T) has
has curvature. curvature.
As shown in
As shown in Figure
Figure55[13],
[13],the
theoscillator
oscillatorconsists
consistsofof a NAND
a NAND gate
gate andand
24 24
NOTNOT gates
gates to produce
to produce the
the t d,osc PTAT. The AGTA consists of a programmable down counter and D type Flip Flops (DFFs) to
td,osc PTAT. The AGTA consists of a programmable down counter and D type Flip Flops (DFFs)
amplify
to amplify thethe td,osc . The
td,osc . TheDFFDFF1 was used for deglitching. Through the simple AND gate, an
1 was used for deglitching. Through the simple AND gate, an
end-of-conversion
end-of-conversion (EOC) (EOC) signal was activated
signal was activated to
to stop
stop the
the oscillator
oscillator for
for power
power saving.
saving.

Figure 5. Circuits of the oscillator and the AGTA.

Figure 5. Circuits of the oscillator and the AGTA.

Compared with the simple version, two parts were modified to support one-point calibration;
Compared with the simple version, two parts were modified to support one-point calibration; an
an AGTA rather than the fixed-gain TA was used, and the calibration circuit composed of a
AGTA rather than the fixed-gain TA was used, and the calibration circuit composed of a magnitude
magnitude comparator and SAR control logic was added. As described, the calibration technique
comparator and SAR control logic was added. As described, the calibration technique used in this
used in this study is similar to that used in [13], in which the theory and calibration procedure were
introduced. The temperature of the ith sensor was set to the calibration temperature (TC), and the
corresponding N(T) of the sensor was varied by adjusting the time gain (n) of the AGTA to
approximate the preset calibration value (NC). A magnitude comparator was used to detect the
difference between N(T) and NC. The result, Comp, was sent to the SAR logic to set n to the proper
Sensors 2016, 16, 176 6 of 14

study is similar to that used in [13], in which the theory and calibration procedure were introduced.
The temperature of the ith sensor was set to the calibration temperature (TC ), and the corresponding
N(T) of the sensor was varied by adjusting the time gain (n) of the AGTA to approximate the preset
calibration value (NC ). A magnitude comparator was used to detect the difference between N(T)
and NC . The result, Comp, was sent to the SAR logic to set n to the proper value (ni ) at TC . The
variation in the oscillation period (td,osc,i ) of the ith sensor at TC was compensated properly to obtain
the identical NC for all sensors. After calibration, all calibrated sensors have similar digital codes at the
corresponding temperature because sensor resolution is stable (gain calibration) and all sensors have
the same values at TC (offset calibration).

2.2. Proposed All-Digital On-Chip Linearity Enhancement Technique

Form Equation (6), because km is nearly constant for a given process technology [13,18], almost
identical curvature is expectable among the error curves of the all calibrated sensors. According to the
character of the similar curvature, individual linearization for each sensor is not required. Thus, the
transfer curve of only one sensor is required to design the linearity-enhanced circuit, which linearizes
Sensors 2016, 16,
the output 176 of all sensors to attain the new curves with linearity improvement.
curves 6 of 13
Figure 6 illustrates the concept of the proposed linearity enhancement technique. One transfer
curve Figure
of the6 calibrated
illustrates sensor
the concept of the as
is denoted proposed
the N(T)linearity
curve. enhancement
In addition totechnique.
the NC at One transfer
the medium
curve of the calibrated sensor is denoted as the N(T) curve. In addition to the N C at the medium
calibration temperature Tmc (i.e., TC at the one-point calibration step), the two digital values N(Tlc ) and
calibration
N(Thc ) at the temperature
highest and Tmclowest
(i.e., Ttemperatures
C at the one-point calibration step), the two digital values N(Tlc) and
(Thc and Tlc ) were measured. Subsequently, according
N(T hc) at the highest and lowest temperatures (Thc and Tlc) were measured. Subsequently, according to
to the three known values NC = N(Tmc ), N(Thc ) and N(Tlc ), we perform linear interpolation, S H (T)
the
andthree known
S L (T), values NC the
for estimating = N(T mc), N(Thc) and N(Tlc), we perform linear interpolation, SH(T) and SL(T),
error between the N(T) and the ideal line N0 (T). Therefore, the error
for
N(T)N0 (T) in the high-temperature N(T)
estimating the error between the regionand the ideal
(HTR) line N0(T). Therefore,
with temperature T > Tmc isthe error N(T)Nwith
approximated 0(T) in

the high-temperature region (HTR) with temperature T > Tmc is approximated with
NH pTq S H pTq N0 pTq (7)
NH (T ) SH (T ) N0 (T ) (7)

Figure
Figure 6.
6. Concept
Concept of
of the
the linearity
linearity enhancement
enhancement technique.
technique.

Then, the new output curve is calibrated as

Then, the new output curve is calibrated as
N (T ) N (T ) N H (T ) N (T ) S H (T ) N0 (T ) (8)
N 1 pTq NpTq NH pTq NpTq pS H pTq N0 pTqq (8)
Similarly, for the low-temperature region (LTR), the new output curve is calibrated as
Similarly, for the low-temperature region (LTR), the new output curve is calibrated as
N (T ) N (T ) N L (T ) N (T ) SL (T ) N0 (T ) (9)
N 1 pTq NpTq
The effect of the linearization NL pTq
regarding NpTq pSisL pTq
thecurvature N0 pTqq
obvious (9)
by observing the following
facts. The maximum errors of N(T) in the HTR and LTR are respectively

N (Thc ) N 0 (Thc ) S H (Thc ) N 0 (Thc ) (10)

N (Tlc ) N 0 (Tlc ) S H (Tlc ) N 0 (Tlc ) (11)

while the ones of N'(T) in the HTR and LTR are smaller since derived from Equations (11) and (12)
Sensors 2016, 16, 176 7 of 14

The effect of the linearization regarding the curvature is obvious by observing the following facts.
The maximum errors of N(T) in the HTR and LTR are respectively

NpThc q N0 pThc q S H pThc q N0 pThc q (10)

NpTlc q N0 pTlc q S H pTlc q N0 pTlc q (11)

while the ones of N'(T) in the HTR and LTR are smaller since derived from Equations (11) and (12)
we have
1
N pTq N0 pTq |NpTq S H pTq| S H pTq NpTq S H pTq N0 pTq S H pThc q N0 pThc q (12)

for Tmc < T < Thc and

1
N pTq N0 pTq |NpTq S L pTq| S L pTq NpTq S L pTq N0 pTq S L pTlc q N0 pTlc q (13)

for Tlc < T < Tmc .

The linear error approximation exhibits a curvature reduction with a noticeable linearity
improvement in the new transfer curve.
Presented in Figure 7 are the corresponding error curves EpNq NpTq N0pTq and EpNq N0pTq N1pTq
Sensors 2016, 16, 176 7 of 13
along with digital value at different temperature. After the procedure of one-point calibration, the error at Tmc is
zero,
E(N).and theerror
The maximal
lineserror in E(N)
of linear is greater thanE(S
approximation theHone E(N1).and
) forinHTR TheE(S
error lines of linear approximation
L) for LTR can be respectively
E(SH ) for
formulated HTR as and E(SL ) for LTR can be respectively formulated as

E(TEpT ) Eq( T EpT

) mcq E(T ) EpT q
(SHH) q hc hc mc N
EEpS (T ) pNpTq
N (Tmc mcqqhc ( N (T )hc NC ) pNpTq NCq
) NpT (14)
(14)
N (NpT
Thc ) hcNq (
TmcNpT
) mcq N (Thc ) NCNpThcq NC

E(TEpT
lc ) lcE
q(TmcEpT
) mcq E(T )
EEpS
(SL )L
q N (TmcpNpT
) N (mc NpTqqlc ( NEpT
T )q lcq
C N (T )) pNC NpTqq (15)
(15)
N (TNpT
mc ) mcN q(T
lc )
NpT lc q NC N (Tlc )
N C NpT lcq

where E(T hc), E(Tlc

E(Thc ), and
lc), and E(Tmc
mc)) are
are the
the errors of digital
digital value
value at at TThc,
hc, T and TTmc
Tlc,lc, and mc, respectively, and
E(Tmc
mc)) =
=00as
asmentioned.
mentioned. Theoretically,
Theoretically, the linearized errors at Tlclc,, TTmc
the linearized andTThchcshould
mc, ,and shouldbebezero.
zero.

Figure
Figure 7.
7. Error
Error curves
curves versus
versus temperature with and
temperature with and without
without and
and the
the linearization.
linearization.

As mentioned, the transfer curves of the calibrated sensors before linearization are almost the
As mentioned, the transfer curves of the calibrated sensors before linearization are almost the
same, the proposed linearity-enhanced circuit is designed according to one sensors transfer curve,
same, the proposed linearity-enhanced circuit is designed according to one sensors transfer curve,
and it is applicable for linearization of other sensors to produce new curves with reduced curvature.
and it is applicable for linearization of other sensors to produce new curves with reduced curvature.
According to Equations (14) and (15), the flowchart for the linearization procedure is presented in
According to Equations (14) and (15), the flowchart for the linearization procedure is presented in
Figure 8. The first step is to determine the falling region of the algorithm input N read out from the
Figure 8. The first step is to determine the falling region of the algorithm input N read out from
calibrated sensor. When N is large than NC, it falls into HTR for the linearization. Contrarily, N falls
the calibrated sensor. When N is large than NC , it falls into HTR for the linearization. Contrarily,
into the LTR because it is smaller than NC. Then, the difference Ndiff between N and NC is calculated.
N falls into the LTR because it is smaller than NC . Then, the difference Ndi f f between N and NC
By linear approximations of the digital value errors in Equations (14) and (15), the correction either
is calculated. By linear approximations of the digital value errors in Equations (14) and (15), the
N H E ( S H ) or N L E ( S L ) is determined in the third step. Finally, the linearized value
N N N H or N N N L is attained.
same, the proposed linearity-enhanced circuit is designed according to one sensors transfer curve,
and it is applicable for linearization of other sensors to produce new curves with reduced curvature.
According to Equations (14) and (15), the flowchart for the linearization procedure is presented in
Figure 8. The first step is to determine the falling region of the algorithm input N read out from the
calibrated sensor. When N is large than NC, it falls into HTR for the linearization. Contrarily, N falls
Sensors 2016, 16, 176 8 of 14
into the LTR because it is smaller than NC. Then, the difference Ndiff between N and NC is calculated.
By linear approximations of the digital value errors in Equations (14) and (15), the correction either

correction ) or N
N H E ( S Heither NHL E ( SHL )q orisN
EpS determined in the third step. Finally, the linearized value
L EpSLq is determined in the third step. Finally, the linearized
N NN
value 1 orN
N HN NH NN
or NL NL is attained.
1 Nisattained.

Figure 8.
Figure Flowchartfor
8. Flowchart forthe
thelinearization
linearization procedure.
procedure.
Sensors 2016, 16, 176 8 of 13

To
To demonstrate
demonstrate thethe performance
performance of the the linearization,
linearization, theoretical modeling using pure software
(MATLAB) and and simulation
simulation using the FPGA EDA (Electronic Design Automation) tool (Xilinx
(Integrated Software Environment) ISE) were performed. performed. The estimated inaccuracies are shown in
Figure 9 for comparison. Compared with the
Figure 9 for comparison. Compared with the unlinearized unlinearized version, the error isthe
version, improved
error isconsiderably.
improved
The linearized The
considerably. results from theoretical
linearized modeling
results from using modeling
theoretical MALTAB using
and ISE simulation
MALTAB andwere
ISE similar and
simulation
resembled the expected effect (i.e., E(N 1 )). This successfully validates the function of the proposed
were similar and resembled the expected effect (i.e., E(N)). This successfully validates the function of
all-digital
the proposed linearity enhancement
all-digital technique. Linearity
linearity enhancement enhancement
technique. enables improving
Linearity enhancement the
enables accuracy
improving
of
thethe sensor at
accuracy oflow-cost
the sensorcondition, and neither
at low-cost costly
condition, andoff-chip
neithersecond-order
costly off-chip master curve fitting
second-order nor
master
time-consuming analog signal linearization are necessary.
curve fitting nor time-consuming analog signal linearization are necessary.

150
Unlinearised
Matlab
100 ISE Simulation
Error

50

-50
2.9 3 3.1 3.2 3.3
Digital Value x 10
4

Figure 9. Inaccuracy of the unlinearized sensor and estimated inaccuracies of theoretical model using
Figure 9. Inaccuracy of the unlinearized sensor and estimated inaccuracies of theoretical model using
Matlab and ISE simulation for the proposed linearization.
Matlab and ISE simulation for the proposed linearization.

The proposed linearity enhancement is easy to implement in a simple circuitry, which is more
The proposed
cost-effective linearity
compared to enhancement
higher degreeisinterpolation.
easy to implement in a simple
The circuit area circuitry,
costs of which is more
the proposed
cost-effective compared to higher degree interpolation. The circuit area costs of the proposed
linearity enhancement and degree-2 Lagrange polynomial interpolation technique [22] are 43 and 70linearity
slices, respectively, while the respective accuracy ranges are 1.50.7 C and 11 C. By applying to
eight sensors before linearization, the simulated results after improvement by the two techniques
using ISE simulation tool are shown in Figure 10. The degree-2 method reaches a little bit better
accuracy, but it noticeably requires much higher circuit area cost and design complexity.
 -50
2.9 3 3.1 3.2 3.3
Digital Value x 10
4

Figure 9. Inaccuracy of the unlinearized sensor and estimated inaccuracies of theoretical model using
Matlab and ISE simulation for the proposed linearization.
Sensors 2016, 16, 176 9 of 14
The proposed linearity enhancement is easy to implement in a simple circuitry, which is more
cost-effective compared to higher degree interpolation. The circuit area costs of the proposed
linearity
enhancementenhancement and degree-2
and degree-2 Lagrange Lagrange
polynomialpolynomial interpolation
interpolation technique
technique [22] are[22]
43 are
and43 70and 70
slices,
slices, respectively,
respectively, while
while the the respective
respective accuracy accuracy
rangesranges
are 1.50.7 C andC
are 1.50.7 and11
11 C. ByC. By applying
applying to
to eight
eight
sensorssensors
beforebefore linearization,
linearization, the simulated
the simulated results
results after after improvement
improvement by the two bytechniques
the two techniques
using ISE
using ISE simulation
simulation tool in
tool are shown areFigure
shown 10.inThe
Figure 10. The
degree-2 degree-2
method reachesmethod
a littlereaches a accuracy,
bit better little bit better
but it
accuracy,
noticeablybut it noticeably
requires requires
much higher much
circuit higher
area cost circuit area complexity.
and design cost and design complexity.

2
Degree-2 Lagrange Polynomial Interpolation
Linearity Enhancement
1
Error (C)

-1

-2
-20 0 20 40 60 80 100
Temperature (C)
Figure 10. Estimated inaccuracies of the two techniques considering process variations of eight sensors.
Figure 10. Estimated inaccuracies of the two techniques considering process variations of eight sensors.

In IC design, we usually utilize FPGA for ASIC (Application-Specific Integrated Circuit) fast
In IC design,
prototyping. we digital
For pure usuallydesign,
utilizethe
FPGA for ASIC
cell-based (Application-Specific
design Integrated
flow is usually applied. Circuit)
Though fast
the same
linearity enhancement is also applicable to sensors designed by a full-custom flow, we usually the
prototyping. For pure digital design, the cell-based design flow is usually applied. Though do
same linearity enhancement is also applicable to sensors designed by a full-custom flow,
not compare area cost between cell-based ASICs and full-custom ones. For cell-based digital signal we usually
do not compare area cost between cell-based ASICs and full-custom ones. For cell-based digital
signal processing IC implementations, we usually express area cost in terms of number of arithmetic
operations or in terms of basic components such as gates in ASIC or slices in FPGA. Traditional digital
curve-fitting circuits require much more arithmetic operations especially when we were exploiting
higher-degree polynomials for better accuracy. Due to a large amount of transistor counts, high degree
curve fittings or interpolations are few implemented by full-custom design flow. In this paper, we
recruit linear approximation which has successfully enhanced the accuracy using a small number of
slices. It is possible to further improve the accuracy by using higher degree polynomial approximations.
However, the number of arithmetic operations will also increase exponentially. The optimization of
high order interpolation is another challenge.

3. Experimental Results
To evaluate the performance, a Xilinx XC3S200AN FPGA board with a low reference clock
frequency of 40 MHz was used to realize the sensor, as shown in Figure 11. A total of eight FPGA chips
for the simple smart temperature sensor with 16 output bits (i.e., simple version without uncalibration
and unlinearizion) were implemented to examine the influence of process variations, and the logic
utilization for a single sensor is 50 slices. The measurements were performed in 10 C steps in a range
of 20 C to 100 C by using a programmable temperature and humidity chamber (MHG-120AF). The
operating range was limited to 100 C because the plastic devices on the board are easily damaged when
the temperature is above 100 C. The measured transfer curves of the simple version are presented
in Figure 12a. The gain and offset errors caused by process variations are evident. Thus, two-point
calibration was adopted to derive an acceptable inaccuracy. The temperature resolution ranges from
0.028 to 0.033 C, and the large inaccuracy of 2.53.5 C from 20 C to 100 C is exhibited, as
presented in Figure 12b. As mentioned previously, to reduce test costs and time, a calibration technique
for one-point calibration support was adopted in this study.
 are easily damaged when the temperature is above 100 C. The measured transfer curves of the
simple version are presented in Figure 12a. The gain and offset errors caused by process variations
simple version are presented in Figure 12a. The gain and offset errors caused by process variations
are evident. Thus, two-point calibration was adopted to derive an acceptable inaccuracy. The
are evident. Thus, two-point calibration was adopted to derive an acceptable inaccuracy. The
temperature resolution ranges from 0.028 to 0.033 C, and the large inaccuracy of 2.53.5 C from
temperature resolution ranges from 0.028 to 0.033 C, and the large inaccuracy of 2.53.5 C from
20 C to 100 16,
C is exhibited, as presented in Figure 12b. As mentioned previously, to reduce test
20 Sensors 100 C176is exhibited, as presented in Figure 12b. As mentioned previously, to 10
C to2016, of 14 test
reduce
costs and time, a calibration technique for one-point calibration support was adopted in this study.
costs and time, a calibration technique for one-point calibration support was adopted in this study.

Figure
Figure11.
11.Photograph
Photograph of
of thetest
test FPGAboard.
board.
Figure 11. Photograph ofthe
the testFPGA
FPGA board.
4
x 10 4
3.5 x 104
3.5 4
3
3.4 3
3.4
2
2
Value

3.3 (C)
DigitalValue

3.3 1
Error(C)
1
3.2
3.2 0
Error
Digital

0
3.1 -1
3.1 -1
3 -2
3 -2
-3
2.9 -20
-3 0 20 40 60 80 100
-20
2.9 0 20 40 60 80 100 -20 0 20 40 (C)
60 80 100
-20 0 20 40 (C)
Temperature 60 80 100 Temperature
Temperature (C) Temperature (C)
(a) (b)
(a) (b)
Figure 12. (a) Measured transfer curves of the simple smart temperature sensor for eight FPGA chips;
Figure 12. 12.
(a) (a)
Measured
Measured transfer curves
transfer curves of
of the simplesmart
the simple smarttemperature
temperature sensor for eight FPGA
chips;chips;
Figure
(b) Inaccuracies of the simple smart temperature sensor after two-pointsensor for eight
calibration. FPGA
(b) Inaccuracies
(b) Inaccuraciesof of
the simple
the simplesmart
smart temperature sensorafter
temperature sensor after two-point
two-point calibration.
calibration.

To verify the calibration performance, the logic utilization of 75 slices for a calibrated sensor (i.e.,
unlinearized version) is implemented on the same FPGA board. Excluding the simple version, 25 slices
were used for the calibration circuit. The measured transfer curves of the N(T) for the eight FPGA chips
and the ideal curve are shown in Figure 13a for comparison. The N(T) of these chips nearly coincided
at TC and changed linearly with the stable resolution as the temperature varied. Compared with the
simple version, the gain and offset errors of the calibrated version decreased substantially, showing
that the influence of process variations was effectively reduced to support one-point calibration. After
one-point calibration, the corresponding inaccuracies are 5 C in a range of 20 C to 100 C, as
shown in Figure 13b. The curvature is apparent in the error curves, which conforms to Equation (6).
Because of the curvature, greater inaccuracy is expected for wider temperature ranges [13,18]. If the
curvature can be reduced or linearized, then the accuracy improves correspondingly. Therefore, this
paper proposes the first all-digital on-chip linearity enhancement technique for reducing the curvature
and improving accuracy.
one-point calibration. After one-point calibration, the corresponding inaccuracies are 5 C in a range
of 20 C to 100 C, as shown in Figure 13b. The curvature is apparent in the error curves, which
conforms to Equation (6). Because of the curvature, greater inaccuracy is expected for wider
temperature ranges [13,18]. If the curvature can be reduced or linearized, then the accuracy
improves correspondingly.
Sensors 2016, 16, 176 Therefore, this paper proposes the first all-digital on-chip11linearity
of 14
enhancement technique for reducing the curvature and improving accuracy.
4
x 10
3.4
Measured 5
Ideal
3.3 4
Digital Value

Error (C)
3.2 3

2
3.1
1
3
0
2.9 -20 0 20 40 60 80 100
-20 0 20 40 60 80 100
Temperature (C) Temperature (C)
(a) (b)

Figure 13. (a)13.Measured

Figure transfer
(a) Measured curves
transfer of the
curves of N(T) for eight
the N(T) FPGA
for eight FPGAchips after
chips calibration
after and
calibration ideal
and curve
ideal
for comparison; (b) Inaccuracies
curve for comparison; of the calibrated
(b) Inaccuracies (unlinearized)
of the calibrated sensorsensor
(unlinearized) after one-point calibration.
after one-point calibration.

To determine
To determine the the
feasibility ofof
feasibility the
theproposed
proposedtechnique,
technique, thetheproposed
proposedsensor
sensor waswas realized
realized usingusing
118 slices in eight FPGA chips without employing any full custom devices, increasing
118 slices in eight FPGA chips without employing any full custom devices, increasing flexibility, flexibility,
portability, and and
portability, simplicity. The
simplicity. Thecalibration
calibrationcircuit,
circuit,which is useless
which is uselessafter
aftercalibrating
calibrating a sensor,
a sensor, can can
be be
implemented off-chip to reduce the circuit cost. Only 43 slices were used for the linearity-enhanced
implemented off-chip to reduce the circuit cost. Only 43 slices were used for the linearity-enhanced
circuit.
circuit. AfterAfter linearization,
linearization, thethe measurementresults
measurement resultsand
and the
the ideal
idealcurve
curvearearepresented
presented in Figure
in Figure14a 14a
for comparison. Compared with the unlinearized sensor, lower inaccuracies of 1.60.9 C from
for comparison. Compared with the unlinearized sensor, lower inaccuracies of 1.60.9 C from 20
C to
to 10020 100 achieved,
were C were achieved, as presented
as presented in Figure
in Figure 14b. 14b.
The The measured
measured error
error curveswere
curves weresimilar
similar toto the
the expected curves, E(N1 ), and the estimated results from theoretical modeling using MALTAB and
expected curves, E(N), and the estimated results from theoretical modeling using MALTAB and ISE
ISE simulation. The measurement results demonstrated that the proposed method, which features a
simulation. The measurement results demonstrated that the proposed method, which features a
fully digital CMOS design, functions favorably. The sensor had a resolution of 0.03 C, and its power
fully dissipation
digital CMOS wasdesign,
measured functions
as 95 Wfavorably. The sensor
at 1 kHz sampling ratehad
and a3.3
resolution
V supply. ofA 0.03 C, andamong
comparison its power
dissipation was measured
the measured as 95
performances of W at 1 kHz
the simple sampling
version, rate and 3.3
the unlinearized V supply.
version, and theA proposed
comparison workamong
is
the measured
Sensors performances
2016, 16, 176in Table 1.
summarized of the simple version, the unlinearized version, and the proposed work
11 of 13
is summarized in Table 1.
4
x 10 1
3.4
Measured
Ideal 0.5
3.3
0
Digital Value

Error (C)

3.2
-0.5
3.1
-1

3 -1.5

2.9 -2
-20 0 20 40 60 80 100 -20 0 20 40 60 80 100
Temperature (C) Temperature (C)
(a) (b)

Figure 14.14.
Figure (a)(a)Measured transfercurves
Measured transfer curvesof of
thethe N'(T)
N'(T) for eight
for eight FPGA FPGA chips
chips after after linearization
linearization and ideal and
ideal curve
curve forfor comparison;
comparison; (b) Inaccuracies
(b) Inaccuracies of the of the linearized
linearized sensor
sensor for eight for
FPGAeight FPGA chips.
chips.

Table 1. Measured performances of the three versions for easy comparison.

Sensor Resolution (C) Error (C) Calibration Area (Slices) Range (C) Technology (m)
Simple 0.028 ~ 0.033 2.5 ~ 3.5 Two-point 50 20 ~ 100 0.09
Calibrated
0.03 0~5 One-point 75 20 ~ 100 0.09
(Unlinearized)
Linearized 0.03 1.6 ~ 0.9 One-point 118 20 ~ 100 0.09
Sensors 2016, 16, 176 12 of 14

Table 1. Measured performances of the three versions for easy comparison.

Sensor Resolution ( C) Error ( C) Calibration Area (Slices) Range ( C) Technology (m)

Simple 0.028 ~ 0.033 2.5 ~ 3.5 Two-point 50 20 ~ 100 0.09
Calibrated
0.03 0~5 One-point 75 20 ~ 100 0.09
(Unlinearized)
Linearized 0.03 1.6 ~ 0.9 One-point 118 20 ~ 100 0.09

Basically, we exploit signal processing technique to ease the design of accurate temperature
sensors. Traditionally, to design an accurate temperature sensor, some sophisticated techniques either
based on analog or digital circuit design principles are required. Then, the trimming would also
become challenging. If we further consider the yield of manufacturing, the cost would be more
uncertain. In this paper, the linearity-enhanced circuit is part of the sensor producing the linearized
output N1 (T), and it occupies a small area. We successfully avoid costly curvature compensation or
other complex accuracy improvement techniques such that the sensor is fully synthesizable for future
VLSI integration. According to the results of simulation and experiment, we can see the accuracy of
the temperature sensor is much improved by the linearity-enhanced circuit. Moreover, the on-chip
enhancement enables online field calibration which was difficult for traditional sensors since deployed.
If we were applying off-chip enhancement, we have to additionally record each sensors data for
individual calibration. On the other hand, since FPGAs are usually used for fast prototyping of ASIC
designs, the linearity-enhanced circuit is applicable not only to sensors realized by FPGAs but also to
those realized by ASICs or custom ICs.
For the accuracy comparison between the sensor in this FPGA and the one in [19], the primary
difference is the process technology. Therefore, the initial inaccuracy caused by the process technology
is also different. In this paper, we improve the accuracy from 05 C to 1.60.9 C, while, in [19],
we improved the 0.35-m full-custom sensor from 03 C to 0.850.65 C. Both of the linearizations
have achieved 50% enhancement. Thus, we prove that the on-chip linearity enhancement works well
even we are calibrating an ASIC prototype, an FPGA manufactured with 90-nm process. Generally,
calibrating a sensor of high-end process technology is much more difficult than calibrating one of
traditional process technology.

4. Conclusions
An all-digital CMOS smart temperature sensor featured with on-chip calibration and linearity
enhancement has been proposed. After calibration, the sensor can support one-point calibration for
test-cost and time reduction. To enhance accuracy, the all-digital linearity enhancement technique
is proposed. Only one sensor must be measured for designing the linearity-enhanced circuit. When
linearization was applied, the measurement results showed that the maximal inaccuracy of 5 C
was improved to 2.5 C from 20 to 100 C, and a twofold improvement in accuracy was achieved.
The proposed sensor was developed without adopting a time-consuming full custom design for
performance estimation or function certification. It occupied 118 slices in FPGA chip, achieved a
robust resolution of 0.03 C, and consumed 95 W at 1 kHz. The measured performances of the
related time-domain sensors is listed in Table 2 for comparison. With one-point calibration and fully
digital CMOS design, the sensor exhibited the acceptable inaccuracy without requiring the off-chip
second-order master curve fitting. Future studies will focus on a more effective all-digital on-chip
linearity enhancement technique for time-domain smart temperature sensors.
Sensors 2016, 16, 176 13 of 14

Table 2. Performance comparisons among related works.

Resolution Power Technology

Sensor Type Error ( C) Calibration Area (mm2 ) Range ( C)
( C) Consumption (W) (m)
[9] Analog 0.12 ~ 0.16 0.7~0.9 Two-point 9 @5 Hz 0.175 0~100 0.35
[10] Analog 0.3 1.6~3.0 Two-point 0.22 @100 Hz 0.05 0~100 0.18
[11] Analog 0.3 0.8~1 Two-point 0.4 @1k Hz 0.032 0~100 0.18
[12] Digital 0.058 1.5~0.8 Two-point 8.4 @2 Hz 140 LEs 0~75 0.22/0.18
[13] Digital 0.133 0.7~0.6 #1 One-point 175 @1k Hz 48 Les #2 0~100 0.22/0.18
[14] Digital 0.139 5.1~3.4 One-point 150 @10k Hz 0.01 0~60 0.065
[15] Analog 0.043 2.7~2.9 One-point 400 @366k Hz 0.0066 40~110 0.065
[16] Analog 0.18 1.5 One-point 500 @ 465k Hz 0.008 0~110 0.065
[17] Analog 0.088 ~ 0.093 0.25~0.35 Two-point 36.7 @10 Hz 0.6 0~90 0.35
[18] Analog 0.043 ~ 0.047 0.2~1.2 Two-point 23 @10 Hz 0.07 40~120 0.35
This
Digital 0.03 1.6~0.9 One-point 95 @1k Hz 118 Slices 20~100 0.09
work
#1 with off-chip second order curve fitting; #2 without one-point calibration circuit.

Acknowledgments: The authors would like to thank Ministry of Science and Technology (MOST) of Taiwan for
Grant MOST 104-2221-E-327-031 and the National Chip Implementation Center of Taiwan (CIC) for supporting
EDA tools.
Author Contributions: Chun-Chi Chen proposed the idea, designed the circuit, and wrote the manuscript.
Chao-Lieh Chen helped with the circuit design and the manuscript writing. Yi Lin implemented the circuit on
FPGA chips and tested the chips.
Conflicts of Interest: The authors declare no conflict of interest.

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