library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
entity Register_74194 is
port(
SDR,S1,S0,SDL,CLRb,Clk : in std_logic
D : in std_logic_vector
(3 downto 0);
Q : out std_logic_vector(3
downto 0)
);
architecture Register_arch of Register_74194 is
begin
process(clr,CLRb)
variable S : std_logic;
begin
S:= S0&S1;
if CLRb = '0' then
Q <= "0000";
else
if clk'event and Clk = '1' then
if S = "11" then
Q <= D;
elsif S = "10" then
Q <= SDR & Q(2 downto 0);
elsif S = "01" then
Q <= Q(2 downto 0) & SDL;
end if;
end if;
end if;
end process;
end Register_arch;