13EC301-MICROPROCESSOR & INTERFACING

Chapter 2

Software Architecture of the 8088 and 8086 Microprocessors

2.1 Micro architecture of the 8088 and 8086 Microprocessors

The micro architecture of a processor is its internal architecture- that is, the circuit
building blocks that implement the software and hardware architectures of the 8088/8086
microprocessors. Due to the need for additional features and higher performance, the
micro architecture of a microprocessor family evolves over time. In fact, a new micro
architecture is introduced for Intels 8086 family every few years. Each new generation of
processors (the 8088/8086, 80286, 80386, 80486 and Pentium processors) represents
significant changes in the micro architecture of the 8086.
The micro architectures of 8088 and 8086 microprocessors are similar. They both employ
parallel processing. They contain two processing units: the bus interface unit (BIU) and
the execution unit (EU). Figure 2-1(a) shows the internal architecture of 8088 and 8086
microprocessors.
The BUI connects the microprocessor to external devices. BUI performs following
operations:
1) Instruction fetching
2) Reading and writing data of data operands for memory
3) Inputting/outputting data for input/output peripherals.
4) And other functions related to instruction and data acquisition.
Data transfer takes place over the system bus. System bus includes an 8-bit bidirectional
data bus for the 8088 (16 bits for the 8086), a 20-bit address bus, and the signals need to
control transfers over the bus.
To implement above functions, the BIU contains the segment registers, the instruction
pointer, address generation adder, bus control logic, and an instruction queue. The figure
2-1(b) shows the bus interface unit of the 8088/8086 in more detail. The BIU uses a
mechanism known as an instruction queue to implement pipelined architecture.

The execution unit is responsible for decoding and executing instructions. The EU
performs the arithmetic, logic, and shift operations required by an instructions.
The EU consists of arithmetic logic unit (ALU), status and control flags, general-purpose
registers, and temporary-operand registers.

2.2 Software Model of the 8088/8086 Microprocessor

Figure 2-2 shows the software architecture of the 8088 microprocessor. It includes 13
16-bit internal registers: the instruction pointer (IP), four data registers (AX, BX, CX, and
DX), two pointer registers (BP and SP), two index registers (SI and DI), and four
segment registers (CS, DS, SS, and ES). In addition to these registers, there is another
register called status register (SR), with nine of its implemented for status and control
flags.

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8088 software architecture implements independent memory and input/output address

spaces. Memory address space is 1,048,576 (1 Mbyte) in length and the I/O address space
is 65,536 bytes (64Kbytes) in length.

2.3 Memory Address Space and Data Organization

The 8088s 1Mbyte memory address space is organized from software point of view as
individual bytes of data stored at consecutive addresses over range 0000016 to FFFFF16.

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The memory in an 8088 microcomputer is organized as 8-bit bytes. The 8088 can access
any two consecutive bytes as a word of data. The lower address byte is called least
significant byte of the word and the higher address byte is its most significant byte.
For efficient use of memory, words of data can be stored at either even- or odd-address
word boundary. The least significant bit of the address determines the type of word
boundary. It this bit is 0, the word is said to be held at an even-address boundary; that is,
a word at even-address boundary corresponds to two consecutive bytes, with the least
significant byte located at an even address.

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A word stored at an even-address boundary, such as 00000 16 , 0000216 , and so on, is said
to be an aligned word. That is, all aligned words are located at an address that is multiple
of 2. On the other hand, a word of data stored at an odd-address boundary, such as
0000116, 0000316 , and so on, is called a misaligned word. Figure 2-5 shows some aligned
and misaligned words of data.
When expressing addresses and data in hexadecimal form, it is common to use the letter
H to specify the base.
The double word is another data form that can be processed by the 8088 microcomputer.
A double word corresponds to four consecutive bytes of data stored in memory; an
example of double-word is a pointer. A pointer is a two-word address element that is used
to access data or code outside the current segment of memory. The word of this pointer
that is stored at the higher address is called the segment base address and the word at the
lower address is called the offset value. Double word of data can be aligned or
misaligned.

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Address Physical memory Aligned words

00008 H Byte 8

00007 H Byte 7
Word
00006 H Byte 6 6
Word
00005 H Byte 5 5
Word
00004 H Byte 4 4

00003 H Byte 3
Word
00002 H Byte 2 2
Word
00001 H Byte 1 1
Word
00000 H Byte 0 0
Misaligned words

Figure 2.5 Examples of aligned and misaligned data words.

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2.4 Data types

Following are the data types supported by 8088 microprocessor:
1) Unsigned integer numbers: each type of integer can be either byte-wide or
word-wide. Figure 2-8(a) shows an unsigned byte integer; this data type can be used
to represent decimal numbers in the range 0 through 255. The unsigned word integer
is shown in figure 2-8(b); it can be used to represent decimal numbers in the range 0
through 65,535.

MSB LSB

D7 D0

(a)

MSB LSB

D15 D0

(b)

Figures 2-8 (a) Unsigned byte integer. (b) Unsigned word integer.

2) Signed integer numbers: each type of integer can be either byte-wide or

word-wide. They are similar to unsigned integer numbers except the most significant
byte in signed integer data type is a sign bit. A zero in this position identifies a
positive number. Fig. 2-9(a) shows a signed byte integer; this data type can be used to
represent decimal numbers in the range +127 to 128. The signed word integer is
shown in fig. 2-9(b); it can be used to represent decimal numbers in the range
+32,767 to 32,768.
3) Binary-coded decimal (BCD) numbers: BCD data can be stored on either
unpacked or packed form. In unpacked BCD, a single BCD digit is stored in four
least significant bits, and the four bits are set to 0. In packed BCD, two BCD numbers
are stored in a byte.
4) ASCII (American Standard Code Information Interchange) : ASCII codes can
be processed by 8088 microprocessor.

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MSB LSB

D7 D0

sign bit
(a)

MSB LSB

D15 D0

sign bit

(b)

Figures 2-9 (a) Signed byte integer. (b) Signed word integer.

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2.5 Segment Registers and Memory Segmentation

In 8088, the 1Mbytes of memory is partitioned into 64Kbyte segments. A segment

represents an independently addressable unit of memory consisting of 64K consecutive
byte-wide storage locations. Each segment is assigned a base address that identifies its
starting point-that is, its lowest byte-storage location.

Only four of these 64Kbyte segments can be active at a time: the code segment, stack
segment, data segment, and extra segment. The segments of memory that are active, as
shown in fig. 2-12, are identified by the values of addresses held in the 8088s four

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internal segment registers: CS (code segment), SS (stack segment), DS (data segment),

and ES (extra segment). Each of these registers contains 16-bit base address that points to
the lowest addressed byte of the segment in memory. Four segments give a maximum of
256Kbytes of active memory. Of this , 64Kbytes are for code (program storage),
64Kbytes are for a stack, and 128Kbytes are for data storage.

Fig 2-13 shows the segmentation of memory.

2.6 Dedicated, Reserved, and General-use Memory

In 8088 microprocessor, not all 1Mbytes of memory are available to user. Some memory
is reserved for storage of special functions.

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Fig. 2-14 shows reserved, dedicated-use and general-use parts of the 8088/8086s address
space. Storage locations from 0000016 to 0001316 are dedicated and those from address
0001416 to 0007F16 are reserved. These 128 bytes of memory are used for storage of the
pointers to interrupt service routines. The dedicated part is used for storage of the pointers
for the 8088s internal interrupts and exceptions. On the other hand, the reserved
locations are saved for storage of pointers that are used by the user-defined interrupts.
The part of address space labeled open in fig. 2-14 is general-use memory and is where
data or instructions of the program are stored.

2.7 Instruction Pointer

The instruction pointer (IP) is 16 bits in length and identifies the location of the next
word of the instruction code to be fetched from the current code segment of the memory.
The IP is similar to a program counter but it contains the offset of the next word of
instruction code instead of its actual address. This is because the IP and CS are both 16
bits in length, but a 20-bit address is needed to access memory. Internal to the 8088, the
offset in IP is combined with the current value in CS to generate the address of the
instruction code. Therefore, the value of the address for the next code access is often
denoted as CS: IP.

2.8 Data Registers

As shown in fig. 2-2, four general purpose data registers are located within the 8088.
During program execution, they are used for temporary storage of frequently used
intermediate results. Their contents can be read, loaded, or modified through software.
Any of the general-purpose data registers can be used as the source or destination of an
operand during an arithmetic operation such as ADD, or a logic operation such as AND.

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The four registers, known as the data registers, are shown in more detail in fig. 2-15(a).
They are referred to as the accumulator register (A), the base register (B), the count
register (C), and the data register (D). Fig. 2-15(b) summarizes the operations.

2.9 Pointer and Index Register

There are four other general-purpose registers shown in fig. 2-2: two pointer registers and
two index registers. They are used to store offset addresses. An offset address represents
the displacement of a storage location in memory from the segment base address in a
segment register-that is , they are used as a pointer or index to select a specific storage
location within a 64Kbyte segment memory. Values held in the index registers are used
to reference data relative to the data segment or extra segment register, and the pointer
register are used to store offset addresses of memory locations relative to the stack
segment register.

Figure 2-16 shows that the two pointer registers are the stack pointer (SP) and base
pointer (BP). The values in SP and BP are used as offsets from the current value of the SS
during the execution of instructions that involves the stack segment of memory and
permits easy access to storage locations in the stack part of memory. BP also represents
an offset relative to the SS register. It is used to access data within the stack segment of
memory.

The index registers are used to hold offset addresses for instructions that access data
stored in the data segment of the memory and are automatically combined with the value
in the DS or ES register during address calculation. The index register can also be used as
source or destination registers in the arithmetic and logical operations.

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2.10 Status Register

The status register, also called the flags register, is 16-bit register with in 8088.

This register is shown in more detail in fig. 2-17. Nine of its bits are implemented. Six of
these represent status flags: the carry flag (CF), parity flag (PF), auxiliary flag (AF), zero
flag (ZF), sign flag (SF), and overflow (OF). The logic state of these flags indicates
conditions that are produced as the result of executing an instruction.
The summary of operation of these flags is given below:
1. The carry flag (CF): CF is set if there is a carry-out or a borrow-in for the most
significant bit of the result during the execution of an arithmetic instruction.
Otherwise, CF is reset.
2. The parity flag (PF): PF is set if the result produced by the instruction has even
parity-that is, it contains an even number of bits at the 1 logic level. If parity is odd,
PF is reset.
3. The auxiliary carry flag (AF): AF is set if there is a carry-out from the low nibble
into the high nibble or a borrow-in from the high nibble into the low nibble of the
lower byte in a 16-bit word. Otherwise, AF is reset.
4. the zero flag (ZF): ZF is set if the result of an arithmetic or logic operation is zero.
Otherwise, ZF is reset.
5. the sign flag (SF): The MSB of the result is copied into SF. Thus SF is set if the
result is a negative number or reset if it is positive.
6. the overflow flag (OF): When OF is set, it indicates that the signed result is out of
range. If the result is not out of range, OF remains reset.

The 8088 provides instructions within its instruction set that are able to use these flags to
alter the sequence in which the program is executed. The other three implemented flag
bits-direction flag (DF), interrupt enable flag (IF), and trap flag (TF)- are control flags.
These flags are provided to control functions of 8088 as follows:

1. The trap flag (TF): if TF is set, the 8088 goes into the single-step mode of operation.
2. The interrupt flag (IF): for 8088 to recognize maskable interrupt requests at its INT
Input, the IF flag must be set. When IF is reset, requests at INT are ignored and the
maskable interrupt interface is disabled.

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3. The direction flag (DF): the logic level of DF determines the direction in which
string operations will occur. When set, the string instruction automatically
decrements the address. Resetting DF causes the string address to be incremented-
that is, data transfers proceed from the high address.

2.11 Generating a Memory Address

A segment base and an offset describe a logical address in the 8088 microcomputer. As
shown in fig. 2-18, both the segment base and offset are 16-bit quantities since all
registers and memory locations used in address calculations are 16 bits long. The
physical addresses that are used to access memory are 20 bits in length. The generation
of the physical address involves combining a 16-bit offset value that is located in the
instruction pointer; a base register, an index register, or a pointer register and a 16-bit
segment base value that is located in one of the segment registers.

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The source of the offset value depends on which type of memory reference is taking
place. It can be base pointer (BP) register, base (BX) register, source index (SI) register,
destination index (DI) register, or instruction pointer (IP). An offset can even be formed
from the contents of several of these registers. On the other hand, the segment base value
always resides in one of the segment registers: CS, DS, SS, or ES.

2.12 The Stack

The stack is implemented in the memory of the 8088 microcomputer and is used for
temporary storage of information such as data or addresses. The stack is 64Kbytes long
and is organized from a software point of view as 32Kwords.

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Fig.
2-22 shows that the lowest address word in the current stack is pointed to by the segment
base value in the SS register. The contents of the SP and BP registers are used as offsets
into the stack segment of memory.
From the figure 2-22 we can see that SP contains an offset value that points to a storage
location in the current stack segment. The address obtained from the contents of SS and
SP (SS:SP) is the physical address of the last storage location in the stack to which data
were pushed. This memory address is known as the top of stack. At the microcomputers
start-up, the value in SP is initialized to FFFFF16. Combining this value with the current
value in the SS gives the highest address word location in the stack (SS: FFFE 16)-that is,
the bottom of the stack.
The 8088 can push data and address information onto the stack from its internal registers
or a storage location in memory. Data transferred to and from the stack are word-wide,
not byte-wide. Each time a word is to be pushed onto the top of the stack, the value in SP
is first automatically decremented by two, and then contents of the register are written
into the stack part of memory.

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2.13 Input/Output Address Space

The 8088 has separate memory and input/output (I/O) address space. The I/O address
space is the place where I/O interfaces, such as printer and terminal ports, are
implemented. Fig. 2-25 shows a map of the 8088s I/O address space. This address range
is 0000016 to FFFFF16 . This represents just 64Kbyte addresses; therefore, unlike
memory, I/O addresses are only 16 bits long. Each of these addresses corresponds to one
byte-wide I/O port.

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The part of the map from address 00000 16 through 000FF16 is referred to as page 0.
Certain of the 8088s I/O instructions can perform only input or output data-transfer
operations to I/O devices located in this part of the I/O address space. Other I/O
instructions can input or output data for devices anywhere in the I/O address space. I/O
data transfers can be byte-wide or word-wide.

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