Et Ref Messages

Encounter Test: Reference: Messages
Product Version 15.12

October 2015
20032015 Cadence Design Systems, Inc. All rights reserved.
Portions IBM Corporation, the Trustees of Indiana University, University of Notre Dame, the Ohio State
University, Larry Wall. Used by permission.
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Contents
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Typographic and Syntax Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Encounter Test Documentation Roadmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Getting Help for Encounter Test and Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Contacting Customer Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Encounter Test And Diagnostics Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Using Encounter Test Contrib Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
What We Changed for This Edition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Revisions for Version 15.10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Interactive and Background Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Message Severity Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Message Return Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Extended Message Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2
C5C - Audit Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
C5CCS-001 through C5CCS-003 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3
CMD - Core Migration Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
CMD-001 through CMD-050 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
October 2015 3 Product Version 15.12

1999-2015 All Rights Reserved.
4
DFTS - Design for Test Synthesis Messages . . . . . . . . . . . . . . . . . 43
DFTS-001 through DFTS-025 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5
EDAM - Extended Direct Access Method Messages. . . . . . . . . 55
EDAM-001 through EDAM-050 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
EDAM-051 through EDAM-0160 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6
FW - Graphical User Interface Framework Messages . . . . . . . 75
FW-001 through FW-050 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
FW-051 through FW-100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
7
TBD - Generate Test Pattern Data Messages . . . . . . . . . . . . . . . . 97
TBD-001 through TBD-050 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
TBD-051 through TBD-100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
TBD-101 through TBD-230 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
TBD-231 through TBD-999 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
8
TBM - Test Pattern Manipulation Messages. . . . . . . . . . . . . . . . . . 167
TBM-001 through TBM-030 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
TBM-031 through TBM-999 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
9
TBV - RPCT Boundary Scan Verification Messages . . . . . . . . 203
TBV-210 through TBV-360 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
TBV-410 through TBV-999 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

10
TBX - Extension Language Messages . . . . . . . . . . . . . . . . . . . . . . . . 225
TBX-001 through TBX-050 .............................................. 225
TBX-051 through TBX-119 .............................................. 237
TBX-120 through TBX-174 .............................................. 248
TBX-175 through TBX-219 .............................................. 261
TBX-220 through TBX-481 .............................................. 272
11
TCC - Random Pattern Generation Messages . . . . . . . . . . . . . . 307
TCC-001 through TCC-116 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
12
TCE- Domain Constraint Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
TCE-400 through TCE-450 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
13
TCI - Structure Analysis Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
TCI-001 through TCI-002 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
14
TCL - High Speed Scan Based Simulation Messages . . . . . . 323
TCL-001 through TCL-049 ............................................... 323
TCL-052 through TCL-096 ............................................... 330
TCL-150 through TCL-198 ............................................... 339
TCL-200 through TCL-520 ............................................... 352
TCL-622 through TCL-999 ............................................... 363
15
TCT - Test Data Core Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
TCT-001 through TCT-108 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
TCT-110 through TCT-580 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381

16
TCW - Stand Alone Random Pattern Simulation Messages . .
391
TCW-001 through TCW-030 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
TCW-031 through TCW-055 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
17
TDA - General Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
TDA-001 through TDA-222 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
18
TDC - Design Constraint Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
TDC-001 through TDC-050 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
TDC-051 through TDC-301 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
19
TDG - Diagnostic Simulation Messages . . . . . . . . . . . . . . . . . . . . . . 423
TDG-001 through TDG-043 .............................................. 423
TDG-096 through TDG-150 .............................................. 445
TDG-151 through TDG-200 .............................................. 460
TDG-201 through TDG-250 .............................................. 472
TDG-254 through TDG-300 .............................................. 488
TDG-301 through TDG-350 .............................................. 496
TDG-351 through TDG-400 .............................................. 505
TDG-401 through TDG-502 .............................................. 515
TDG-503 through TDG-999 .............................................. 528
20
TDL - True-Time Test Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553
TDL-001 through TDL-230 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553
TDL-240 through TDL-301 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561

21
TDM - Delay Model Build Messages . . . . . . . . . . . . . . . . . . . . . . . . . . 565
TDM-001 through TDM-050 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565
TDM-051 through TDM-200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580
TDM-201 through TDM-317 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589
22
TDR - Tester Description Rule Messages . . . . . . . . . . . . . . . . . . . . 599
TDR-002 through TDR-600 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599
TDR-601 through TDR-683 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612
23
TDS - Convert Vectors To Smartscan Messages . . . . . . . . . . . . 625
TDS-001 - TDS-050 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625
24
TDY - Delay Simulation Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659
TDY-001 through TDY-071 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659
25
TDX - Dynamic Test Generation Messages . . . . . . . . . . . . . . . . . . 671
TDX-001 through TDX-049 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671
26
TEI - Build Model Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681
TEI-001 through TEI-050 ................................................ 681
TEI-051 through TEI-145 ................................................ 692
TEI-154 through TEI-220 ................................................ 709
TEI-221 through TEI-279 ................................................ 730
TEI-280 through TEI-800 ................................................ 748
TEI-801 through TEI-999 ................................................ 760

27
TFA - Deterministic Fault Analysis Messages . . . . . . . . . . . . . . . . 767
TFA-001 through TFA-050 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767
TFA-051 through TFA-089 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782
28
TEM - Insert Embedded Test Messages. . . . . . . . . . . . . . . . . . . . . . 793
TEM-039 through TEM-100 .............................................. 793
TEM-110 through TEM-250 .............................................. 810
TEM-251 through TEM-328 .............................................. 818
TEM-341 through TEM-378 .............................................. 830
TEM-400 through TEM-450 .............................................. 842
TEM-451 through TEM-700 .............................................. 855
TEM-701 through TEM-749 .............................................. 882
TEM-752 through TEM-799 .............................................. 886
TEM-801 through TEM-850 .............................................. 890
TEM-851 through TEM-900 .............................................. 908
TEM-902 through TEM-999 .............................................. 926
29
TFL - Failure Data Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937
TFL-001 through TFL-050 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937
TFL-051 through TFL-100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951
TFL-101 through TFL-150 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965
TFL-151 through TFL-299 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979
TFL-300 through TFL-999 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003
30
TFM - Fault Model Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1015
TFM-002 through TFM-050 ............................................. 1015
TFM-051 through TFM-100 ............................................. 1031
TFM-101 through TFM-155 ............................................. 1044
TFM-376 through TFM-999 ............................................. 1056

31
TFS - Test Simulation Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077
TFS-001 through TFS-454 .............................................. 1077
TFS-500 through TFS-600 .............................................. 1087
TFS-602 through TFS-850 .............................................. 1093
TFS-851 through TFS-936 .............................................. 1106
32
TFW - Encounter Test Framework Utilities Messages . . . . . 1117
TFW-001 through TFW-050 ............................................. 1117
TFW-051 through TFW-100 ............................................. 1127
TFW-101 through TFW-289 ............................................. 1135
TFW-600 through TFW-999 ............................................. 1144
33
TGD - GlobalData Audit Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . 1157
TGD-001 through TGD-110 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1157
TGD-111 through TGD-161 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1164
34
TGI - RPCT Boundary Scan Interconnect Test Messages 1171
TGI-100 through TGI-889 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1171
35
TGR - Test Simulation and Manipulate Tests Messages . . 1177
TGR-006 through TGR-050 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1177
TGR-052 through TGR-100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1185
TGR-101 through TGR-342 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1191
36
THT - Hierarchical Core Test System Messages . . . . . . . . . . . 1199
THT-001 through THT-599 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1199

THT-600 through THT-999 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1205
37
THM - Hierarchical Model Messages . . . . . . . . . . . . . . . . . . . . . . . . 1209
THM-002 through THM-430 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1209
THM-431 through THM-524 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1218
THM-806 through THM-899 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1226
38
TID - Electronic Chip ID Test Generation Messages . . . . . . . 1235
TID-001 through TID-300 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1235
39
TIE - Import EVCD Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1243
TIE-001 through TIE-999 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1243
40
TIM - Import Test Pattern Data Messages . . . . . . . . . . . . . . . . . . . 1251
TIM-001 through TIM-050 .............................................. 1251
TIM-051 through TIM-088 .............................................. 1261
TIM-402 through TIM-500 .............................................. 1274
TIM-501 through TIM-999 .............................................. 1287
41
TIS - Import STIL Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1299
TIS-001 through TIS-052 ............................................... 1299
TIS-400 through TIS-450 ............................................... 1312
TIS-451 through TIS-499 ............................................... 1327
TIS-801 through TIS-999 ............................................... 1344

42
TJA - Write BSDL Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1351
TJA-103 through TJA-653 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1351
43
TJB - Parse BSDL Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1363
TJB-100 through TJB-250 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1363
TJB-251 through TJB-300 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1382
TJB-301 through TJB-900 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1395
44
TJC - IEEE 1149.1 Boundary Scan Verification Messages 1415
TJC-102 through TJC-200 .............................................. 1415
TJC-201 through TJC-300 .............................................. 1429
TJC-301 through TJC-351 .............................................. 1438
TJC-500 through TJC-531 .............................................. 1452
TFK-100 through TFK-101 .............................................. 1458
45
TLD - Signature-Based Test Messages . . . . . . . . . . . . . . . . . . . . . . 1459
TLD-001 through TLD-999 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1459
46
TJM - IEEE 1149.1 Boundary Scan Chain Test Mode Define
Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1463
TJM-100 through TJM-105 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1463
47
TLH - Linehold Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1465
TLH-001 through TLH-050 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1465
TLH-051 through TLH-999 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1482

48
TLM - Logic Model Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1489
TLM-001 through TLM-050 ............................................. 1489
TLM-051 through TLM-150 ............................................. 1501
TLM-152 through TLM-193 ............................................. 1517
TLM-201 through TLM-999 ............................................. 1526
49
TLP - Low Power Messages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1535
TLP-100 through TLP-700 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1535
50
TLS - Logic Model Smart Scan Messages . . . . . . . . . . . . . . . . . . 1557
TLS-001 - TLS-050 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1557
51
TMD - Manufacturing Release Data Messages . . . . . . . . . . . . . 1571
TMD-001 through TMD-100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1571
52
TMI - Verify Macro Isolation Messages . . . . . . . . . . . . . . . . . . . . . . 1583
TMI-001 through TMI-050 .............................................. 1583
TMI-051 through TMI-088 .............................................. 1596
TMI-101 through TMI-150 .............................................. 1603
TMI-151 through TMI-200 .............................................. 1621
TMI-201 through TMI-250 .............................................. 1630
TMI-251 through TMI-392 .............................................. 1642
TMI-420 through TMI-800 .............................................. 1652
53
TMT - Create MacroTests Messages . . . . . . . . . . . . . . . . . . . . . . . . 1659
TMT-001 through TMT-050 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1659

TMT-051 through TMT-306 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1664

TMT-400 through TMT-521 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1672
54
TND - Good Machine Delay Simulation Messages . . . . . . . . . 1683
TND-001 through TND-600 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1683
TND-601 through TND-799 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1692
TND-800 through TND-936 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1700
55
TNP - Delay Timing Messages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1713
TNP-011 through TNP-099 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1713
56
TNS - Netname Services Messages . . . . . . . . . . . . . . . . . . . . . . . . . 1715
TNS-001 through TNS-042 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1715
57
TOM - Objective Model Build and Access Messages . . . . . . 1727
TOM-001 through TOM-072 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1727
TOM-100 through TOM-722 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1739
58
TPC - Parallel Processing Communications Messages . . . 1747
TPC-001 through TPC-005 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1747
59
TPD - Test Pattern Display Messages . . . . . . . . . . . . . . . . . . . . . . . 1753
TPD-100 through TPD-900 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1753

60
TPL - Pipeline Verification Messages . . . . . . . . . . . . . . . . . . . . . . . . 1759
TPL-001 through TPL-050 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1759
TPL-060 through TPL-296 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1770
61
TPO - Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1781
TPO-001 through TPO-099 ............................................. 1781
TPO-100 through TPO-199 ............................................. 1796
TPO-200 through TPO-299 ............................................. 1800
TPO-300 through TPO-399 ............................................. 1806
TPO-400 through TPO-499 ............................................. 1811
TPO-500 through TPO-599 ............................................. 1816
TPO-600 through TPO-699 ............................................. 1820
TPO-700 through TPO-799 ............................................. 1828
TPO-800 through TPO-899 ............................................. 1857
TPO-900 through TPO-999 ............................................. 1880
62
TPT - Path Test Analysis Messages . . . . . . . . . . . . . . . . . . . . . . . . . . 1907
TPT-001 through TPT-317 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1907
63
TPU - Test Pattern Utility Messages. . . . . . . . . . . . . . . . . . . . . . . . . . 1915
TPU-002 through TPU-972 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1915
64
TRA - Random Resistant Fault Analysis Messages . . . . . . . . 1923
TRA-001 through TRA-050 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1923
TRA-051 through TRA-600 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1935

65
TSM - Simulation Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1949
TSM-003 through TSM-900 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1949
66
TSC - Test Sequence Effectiveness Checker Messages . . 1955
TSC-001 through TSC-050 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1955
TSC-061 through TSC-130 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1964
67
TSR - Scan and LSSD Flush Test Messages . . . . . . . . . . . . . . . 1975
TSR-001 through TSR-360 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1975
68
TSS - Signature Observation Sequence Messages . . . . . . . . 1983
TSS-001 through TSS-117 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1983
69
TST - Sequential Stored Pattern Test Generation Messages .
1993
TST-001 through TST-405 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1993
70
TSU - Segment/Symbol Utilities Messages . . . . . . . . . . . . . . . . . 1999
TSU-001 through TSU-200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1999
71
TSV- Test Structure Verification Messages . . . . . . . . . . . . . . . . . . 2005
TSV-001 through TSV-050 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2005
TSV-051 through TSV-099 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2046
TSV-101 through TSV-150 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2077

TSV-151 through TSV-194 .............................................. 2093

TSV-201 through TSV-250 .............................................. 2102
TSV-251 through TSV-296 .............................................. 2128
TSV-305 through TSV-350 .............................................. 2148
TSV-351 through TSV-400 .............................................. 2168
TSV-401 through TSV-596 .............................................. 2190
TSV-900 through TSV-999 .............................................. 2199
72
TSY - Test Synthesis Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2207
TSY-001 through TSY-050 .............................................. 2207
TSY-051 through TSY-105 .............................................. 2219
TSY-200 through TSY-266 .............................................. 2224
TSY-300 through TSY-390 .............................................. 2243
TSY-400 through TSY-450 .............................................. 2254
TSY-451 through TSY-500 .............................................. 2264
TSY-501 through TSY-550 .............................................. 2277
TSY-551 through TSY-600 .............................................. 2293
TSY-601 through TSY-700 .............................................. 2298
TSY-701 through TSY-921 .............................................. 2314
73
TTA - Testability Measurements Messages . . . . . . . . . . . . . . . . . 2335
TTA-001 through TTA-038 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2335
74
TTC - Test Generation Controller Messages . . . . . . . . . . . . . . . . 2341
TTC-001 through TTC-050 ............................................. 2341
TTC-051 through TTC-100 ............................................. 2356
TTC-102 through TTC-145 ............................................. 2364
TTC-151 through TTC-402 ............................................. 2376

75
TTM - Test Mode Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2389
TTM-001 through TTM-050 ............................................. 2389
TTM-051 through TTM-124 ............................................. 2401
TTM-267 through TTM-300 ............................................. 2420
TTM-301 through TTM-350 ............................................. 2435
TTM-351 through TTM-400 ............................................. 2449
TTM-401 through TTM-450 ............................................. 2466
TTM-451 through TTM-500 ............................................. 2479
TTM-501 through TTM-550 ............................................. 2496
TTM-551 through TTM-600 ............................................. 2507
TTM-601 through TTM-699 ............................................. 2520
TTM-700 through TTM-750 ............................................. 2538
TTM-751 through TTM-999 ............................................. 2557
76
TTU - Timing Utility Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2577
TTU-001 through TTU-031 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2577
TTU-100 through TTU-140 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2581
TTU-200 through TTU-907 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2590
77
TTV - Test View Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2601
TTV-005 through TTV-050 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2601
TTV-051 through TTV-083 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2612
78
TUI - User Interface Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2623
TUI-022 through TUI-999 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2623

79
TVC - Create Vector Correspondence Messages . . . . . . . . . . 2651
TVC-001 through TVC-802 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2651
80
TVE - Vector Export Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2657
TVE-001 through TVE-150 ............................................. 2657
TVE-151 through TVE-251 ............................................. 2666
TVE-300 through TVE-400 ............................................. 2671
TVE-420 through TVE-999 ............................................. 2688
81
TVS - Verify On Product Clock Sequences Messages. . . . . 2727
TVS-001 through TVS-130 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2727
82
TWC - Command Script Messages . . . . . . . . . . . . . . . . . . . . . . . . . . 2743
TWC-001 through TWC-020 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2743
83
TWT - Weighted Random Pattern Test and LBIST Messages
2751
TWT-002 through TWT-050 ............................................. 2751
TWT-051 through TWT-100 ............................................. 2766
TWT-101 through TWT-147 ............................................. 2781
TWT-161 through TWT-200 ............................................. 2796
TWT-710 through TWT-999 ............................................. 2803
84
Additional TSV Message Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2811
TSV-014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2812

Troubleshooting TSV-014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2814

What If You Do Not Fix TSV-014? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2814
TSV-016 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2814
TSV-024 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2815
TSV-027 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2818
TSV-051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2822
TSV-310 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2823
Messages Related to TSV-310 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2829
TSV-311 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2830
TSV-315 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2831
TSV-350 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2834
TSV-352 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2837
TSV-387 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2838

TSV-388 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2842
Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2847

Preface
This manual contains Cadence Encounter Test messages with their explanation and user
response.
Typographic and Syntax Conventions

The Encounter Test library set uses the following typographic and syntax conventions.
Text that you type, such as commands, filenames, and dialog values, appears in Courier
type.
Example: Type diagnose_failset_logic -h to display help for the command.
Variables appear in Courier italic type.
Example: Use TB_SPACE_SCRIPT=input_filename to specify the name of the
script that determines where Encounter Test results files are stored.
User interface elements, such as field names, button names, menus, menu commands,
and items in clickable list boxes, appear in Helvetica italic type.
Example: Select File - Delete - Model and fill in the information for the model.

Preface
Encounter Test Documentation Roadmap

The following figure depicts a recommended flow for traversing the documentation structure.
Getting
Started New User
Overview
and
Models
Testmode
Guides
Test
Faults
ATPG
Test Vectors
Diagnostic
Flow PMBIST
PMBIST ET Pattern
Command GUI Expert

Reference Messages Test Pattern
Documents
Extension Glossar

Preface
Getting Help for Encounter Test and Diagnostics

Use the following methods to obtain help information:
1. From the <installation_dir>/tools/bin directory, type cdnshelp and press
Enter. The installed Cadence documentation set is displayed.
2. To view a book, double-click the desired product book collection and double-click the
desired book title in the lower pane to open the book.
Click the Help or ? buttons on Encounter Test forms to navigate to help for the form and its
related topics.
Refer to the following in the Encounter Test: Reference: GUI for additional details:
Help Pull-down describes the Help selections for the Encounter Test main window.
View Schematic Help Pull-down describes the Help selections for the Encounter Test
View Schematic window.
Contacting Customer Service

Use the following methods to get help for your Cadence product.
Cadence Online Customer Support
Cadence online customer support offers answers to your most common technical
questions. It lets you search more than 40,000 FAQs, notifications, software updates,
and technical solutions documents that give step-by-step instructions on how to solve
known problems. It also gives you product-specific e-mail notifications, software updates,
service request tracking, up-to-date release information, full site search capabilities,
software update ordering, and much more. Go to http://www.cadence.com/support/
pages/default.aspx for more information on Cadence Online Customer Support.
Cadence Customer Response Center (CRC)
A qualified Applications Engineer is ready to answer all your technical questions on the
use of this product through the Cadence Customer Response Center (CRC). Contact the
CRC through Cadence Online Support. Go to http://support.cadence.com and click
Contact Customer Support link to view contact information for your region.
IBM Field Design Center Customers
Contact IBM EDA Customer Services at 1-802-769-6753, FAX 1-802-769-7226. From
outside the United States call 001-1-802-769-6753, FAX 001-1-802-769-7226. The e-
mail address is edahelp@us.ibm.com.

Preface
Encounter Test And Diagnostics Licenses

Refer to Encounter Test and Diagnostics Product License Configuration in Encounter Test:
Release: Whats New for details on product license structure and requirements.
Using Encounter Test Contrib Scripts

The files and Perl scripts shipped in the <ET installation path>/ etc/tb/contrib
directory of the Encounter Test product installation are not considered as "licensed
materials". These files are provided AS IS and there is no express, implied, or statutory
obligation of support or maintenance of such files by Cadence. These scripts should be
considered as samples that you can customize to create functions to meet your specific
requirements.
What We Changed for This Edition

Refer to the following:
Revisions for Version 15.10

TBD messages
TBD-118
TBD-119
TBD-811
TDA messages
TDA-500
TDS messages
TDS-284
TDS-286

Preface
TDS-288
TDS-290
TDS-300
TEI messages
TEI-232
TFL messages
TFL-253
TFL-254
TFM messages
TFM-901
TFW messages
TFW-942
THT messages
THT-132
TIS messages
TIS-051
TIS-052
TIS-500
TIS-501
TIS-822
TIS-823
TLH messages
TLH-065
TLP messages
TLP-342
TLP-343
TLP-346

Preface
TLP-652
TRA messages
TRA-026
TSR messages
TSR-363
TSR-364
TRS-365
TSV messages
TSV-055
TSV-208
TSV-126
TSV-308
TSV-343
TSV-344
TSV-345
TSV-346
TTC messages
TTC-077
TTC-198
TTC-212
TTM messages
TTM-340
TTM-341
TTM-669
TTM-670
TTM-671
TTM-672

Preface
TTM-673
TTM-674
TTM-675
TTM-760
TTM-761
TTM-762
TTM-763
TTM-884
TTM-885
TTM-886
TUI messages
TUI-333
TUI-362
TUI-363
TUI-364
TUI-737
TUI-738
TUI-739
TUI-740
TUI-741
TUI-742
TUI-743
TUI-744
TUI-745
TUI-746
TUI-747
TUI-748

Preface
TVE messages
TVE-187
TVE-188

TBD messages
TBD-811
TDS messages
TDS-214
TEM messages
TEM-664
TEM-665
TFM messages
TFM-726
TRA messages
TRA-167
TSV messages
TSV-334
TVE messages
TVE-627

TBD messages
TBD-856
TDS messages
TDS-430
TEM messages

Preface
TEM-331
TEM-666
TFL messages
TFL-257
TFM messages
TFM-811
TFM-812
TFM-813
TFM-814
TFM-815
TFM-816
TFM-817
TFM-818
TFM-819
THT messages
THT-160
THT-166
THT-430
TIM messages
TIM-092
TPO messages
TPO-767
TPO-767
TPO-768
TPO-769
TPO-770
TPO-771

Preface
TPO-772
TPO-773
TPO-774
TPO-775
TPO-776
TPO-777
TPO-778
TPO-779
TPO-780
TPO-989
TTM messages
TTM-113
TTM-114

1
Overview
Interactive and Background Messages

There are two types of Encounter Test Messages:
Messages with interactive analysis
Chapter 71, TSV- Test Structure Verification Messages
Chapter 52, TMI - Verify Macro Isolation Messages
Chapter 44, TJC - IEEE 1149.1 Boundary Scan Verification Messages
Chapter 9, TBV - RPCT Boundary Scan Verification Messages
Chapter 27, TFA - Deterministic Fault Analysis Messages
Chapter 64, TRA - Random Resistant Fault Analysis Messages
Chapter 62, TPT - Path Test Analysis Messages
Background messages
Chapter 2, C5C - Audit Messages
Chapter 5, EDAM - Extended Direct Access Method Messages
Chapter 6, FW - Graphical User Interface Framework Messages
Chapter 7, TBD - Generate Test Pattern Data Messages
Chapter 8, TBM - Test Pattern Manipulation Messages
Chapter 10, TBX - Extension Language Messages
Chapter 11, TCC - Random Pattern Generation Messages
Chapter 14, TCL - High Speed Scan Based Simulation Messages
Chapter 15, TCT - Test Data Core Messages

Overview
Chapter 16, TCW - Stand Alone Random Pattern Simulation Messages

Chapter 17, TDA - General Messages
Chapter 18, TDC - Design Constraint Messages
Chapter 19, TDG - Diagnostic Simulation Messages
Chapter 20, TDL - True-Time Test Messages
Chapter 21, TDM - Delay Model Build Messages
Chapter 22, TDR - Tester Description Rule Messages
Chapter 24, TDY - Delay Simulation Messages
Chapter 25, TDX - Dynamic Test Generation Messages
Chapter 26, TEI - Build Model Messages
Chapter 29, TFL - Failure Data Messages
Chapter 30, TFM - Fault Model Messages
Chapter 31, TFS - Test Simulation Messages
Chapter 32, TFW - Encounter Test Framework Utilities Messages
Chapter 33, TGD - GlobalData Audit Messages
Chapter 34, TGI - RPCT Boundary Scan Interconnect Test Messages
Chapter 35, TGR - Test Simulation and Manipulate Tests Messages
Chapter 37, THM - Hierarchical Model Messages
Chapter 38, TID - Electronic Chip ID Test Generation Messages
Chapter 40, TIM - Import Test Pattern Data Messages
Chapter 41, TIS - Import STIL Messages
Chapter 42, TJA - Write BSDL Messages
Chapter 43, TJB - Parse BSDL Messages
Chapter 46, TJM - IEEE 1149.1 Boundary Scan Chain Test Mode Define
Messages
Chapter 45, TLD - Signature-Based Test Messages
Chapter 47, TLH - Linehold Messages

Overview
Chapter 48, TLM - Logic Model Messages

Chapter 51, TMD - Manufacturing Release Data Messages
Chapter 53, TMT - Create MacroTests Messages
Chapter 54, TND - Good Machine Delay Simulation Messages
Chapter 55, TNP - Delay Timing Messages
Chapter 56, TNS - Netname Services Messages
Chapter 57, TOM - Objective Model Build and Access Messages
Chapter 58, TPC - Parallel Processing Communications Messages
Chapter 59, TPD - Test Pattern Display Messages
Chapter 60, TPL - Pipeline Verification Messages
Chapter 63, TPU - Test Pattern Utility Messages
Chapter 66, TSC - Test Sequence Effectiveness Checker Messages
Chapter 65, TSM - Simulation Messages
Chapter 67, TSR - Scan and LSSD Flush Test Messages
Chapter 68, TSS - Signature Observation Sequence Messages
Chapter 69, TST - Sequential Stored Pattern Test Generation Messages
Chapter 70, TSU - Segment/Symbol Utilities Messages
Chapter 72, TSY - Test Synthesis Messages
Chapter 73, TTA - Testability Measurements Messages
Chapter 74, TTC - Test Generation Controller Messages
Chapter 75, TTM - Test Mode Messages
Chapter 76, TTU - Timing Utility Messages
Chapter 77, TTV - Test View Messages
Chapter 78, TUI - User Interface Messages
Chapter 79, TVC - Create Vector Correspondence Messages
Chapter 80, TVE - Vector Export Messages
Chapter 81, TVS - Verify On Product Clock Sequences Messages

Overview
Chapter 82, TWC - Command Script Messages

Chapter 83, TWT - Weighted Random Pattern Test and LBIST Messages
Message Severity Codes

The following are the message severities used by Encounter Test.
Code Explanation
INFO This message is issued for information purposes only; no error is found.
Typically, this message severity gives status about a process that is running
or a process that has completed running.
WARNING WARNING messages are issued for situations that may be problematic, but
do not cause the program to prematurely terminate. The data produced may
be reliable, but should be verified.
A warning message may also produce a sub-level code of [Severe] to
indicate that invalid test data or that other unreliable data may result, but that
processing will continue as far as possible.
ERROR ERROR messages indicate severe system, program, or input errors that
explain why the program is terminating prematurely, or to indicate the results
produced are unreliable. The following sub-level codes accompany error
messages when applicable:
[Input] indicates an input error in either the specification of a keyword
value or within the input itself.
[Tool] indicates a problem in the system or execution environment
related to issues such as memory, licensing, or other peripheral settings
that affect the performance of the software.
[Internal] indicates that an unexpected code condition has occurred
and is typically caused by a code bug.
For details about the severity and content of messages, refer to "Message Summary Window"
in the Encounter Test: Reference: GUI.
Note: Items that appear in this manual as objectName may be a pin, block, or net, and the
identification of which it is part of the objectName in Encounter Test. The objectName

Overview
may be customized (netname vs. pinname, proper name vs. short name). These options are
described in the Options Setup section of the Encounter Test: Reference: GUI.
Message Return Codes

The Encounter Test program return codes are related to the message severities as follows:
Severity Code Return Code

INFO 0
WARNING 2
WARNING [Severe] 4
ERROR [Input] or [Tool] 5
ERROR [Internal] 6
Extended Message Help

Display Interactive extended help information for a message by entering either of the following
commands either directly on the command line or in the GUI Command Input field:
msgHelp <message_prefix-error_number1> <message_prefix-
error_number1> ...
For example,
msgHelp TSV-001 TSV-314
displays interactive help information for messages TSV-001 and TSV-314.

help <message_prefix-error_number1> displays interactive help for the
specified message.
The GUI Session Log is also available to vew message text and extended help. Refer to
"Using the Session Log to View Message Help" in the Encounter Test: Reference: GUI for
details.

Overview

2
C5C - Audit Messages
C5CCS-001 through C5CCS-003 on page 37
C5CCS-001 through C5CCS-003

WARNING (C5CCS-001): [Severe] ---- ERROR ---- Error accessing file filename.
EXPLANATION:
The file name passed to the Checksum routine could not be accessed. Possible reasons
for this are:
The file does not exist.
The permissions for the file are not correct. Read permission is required.
Processing halts.
USER RESPONSE:
Determine if the file exists and check the permissions for the file.
WARNING (C5CCS-002): [Severe] C5CChecksum - Cannot open file file name because
it is a directory.
EXPLANATION:
The file name passed to the Checksum routine was determined to be a directory name,
NOT a file name. Processing halts.
USER RESPONSE:
Determine why the program passed the name of a directory instead of the name of a file.
WARNING (C5CCS-003): [Severe] Invalid mode specified mode.

EXPLANATION:

C5C - Audit Messages
The Checksum program has 4 modes of operation. The calling program has passed in
a mode that is not recognized by the Checksum routine. Processing halts.
USER RESPONSE:
The valid modes are COMPUTE, VERIFY, UPDATE, and HOSTUPDATE. Change the mode
passed to the program to match one of these modes.

3
CMD - Core Migration Messages
CMD-001 through CMD-050 on page 39
CMD-001 through CMD-050

INFO (CMD-001): prepare_core_migration_info has started time.
EXPLANATION:
The prepare_core_migration_info process has started.
USER RESPONSE:
None.
INFO (CMD-002): prepare_core_migration_info has ended time.

EXPLANATION:
The prepare_core_migration_info process has ended.
USER RESPONSE:
None.
ERROR (CMD-003): prepare_core_migration_info was unable to access the flat

model.
EXPLANATION:
prepare_core_migration_info could not load the flat model.
USER RESPONSE:
Review the log for any messages that indicate the cause of the problem. Contact
Cadence Customer Support for additional help (see Contacting Customer Service on
page 23).

ERROR (CMD-004): prepare_core_migration_info could not withdraw the

PROJECT keyword from the environment.
EXPLANATION:
The PROJECT keyword is required for loading of the Encounter Test model. This
keyword is extracted from the specification of the WORKDIR.
USER RESPONSE:
Check that your WORKDIR specification is correct. If the WORDIR: specification is
correct, contact Cadence Customer Support for additional help (see Contacting
Customer Service on page 23).
ERROR (CMD-005): prepare_core_migration_info could not withdraw the PARTID

keyword from the environment.
EXPLANATION:
The PARTID keyword is required for loading of the Encounter Test model. This keyword
is extracted from the specification of the WORKDIR.
USER RESPONSE:
Check that your WORKDIR specification is correct. If the WORDIR specification is
correct, contact Cadence Customer Support for additional help (see Contacting
ERROR (CMD-006): prepare_core_migration_info could not withdraw the

TESTMODE keyword from the environment.
EXPLANATION:
The TESTMODE keyword is required for loading of the Encounter Test model. This
keyword is specified on the prepare_core_migration_info command line.
USER RESPONSE:
Check that your command line specification for the testmode keyword is correct. If the
testmode keyword specification iscorrect, contact Cadence Customer Support for
additional help (see Contacting Customer Service on page 23).
ERROR (CMD-007): prepare_core_migration_info was unable to open the

Encounter Test model.
EXPLANATION:
The Encounter Test model must be loaded during prepare_core_migration_info.

USER RESPONSE:
Check that you have permissions to the specified workdir. If you have permission to the
workdir, contact Cadence Customer Support for additional help (see Contacting
ERROR (CMD-008): prepare_core_migration_info was unable to set the testmode.

EXPLANATION:
The Encounter Test testmode must be loaded during
prepare_core_migration_info.
USER RESPONSE:
Check that you have permissions to the specified testmode. If the testmode is correct,
contact Cadence Customer Support for additional help (see Contacting Customer
Service on page 23).
ERROR (CMD-009): prepare_core_migration_info was unable to load the

Encounter Test model methods.
EXPLANATION:
The model methodes for Encounter Test must be loaded during
prepare_core_migration_info.
USER RESPONSE:
Contact Cadence Customer Support for additional help (see Contacting Customer
ERROR (CMD-010): prepare_core_migration_info was unable to open file

filename.
EXPLANATION:
prepare_core_migration_info creates the coreInfo file for the migration of test
patterns. The coreInfo file could not be created.
USER RESPONSE:
Verify that the coremigrationdir directory is writable and has adequate space
available for the coreInfo file. Cadence Customer Support for additional help (see
Contacting Customer Service on page 23).
ERROR (CMD-011): prepare_core_migration_info was unable to open a storage

area for file filename.

EXPLANATION:
patterns. The coreInfo file could not be created.
USER RESPONSE:
Verify that the coremigrationdir directory is writable and has adequate space available for
the coreInfo file. Cadence Customer Support for additional help (see Contacting
ERROR (CMD-012): The testmode is not a migrate or bypass testmode.

prepare_core_migration_info cannot be run on this testmode.
EXPLANATION:
patterns. The coreInfo file could not be created because the boundary keyword of the
scan type statement in the mode definition file did not specify boundary=migrate or
boundary=bypass.
USER RESPONSE:
Specify a testmode which is built using a mode definition file with a scan type statement
that specifies boundary=migrate or boundary=bypass. Cadence Customer
Support for additional help (see Contacting Customer Service on page 23).

4
DFTS - Design for Test Synthesis
Messages
DFTS-001 through DFTS-025 on page 43

DFTS-001 through DFTS-025

ERROR (DFTS-001): [Input] The program cannot read file file_name specified for
keyword keyword.
EXPLANATION:
The command was unable to open the indicated file. The command terminates.
RESPONSE:
Ensure the file exists and is readable, and then rerun.
ERROR (DFTS-002): [Input] The program cannot write to file/directory file_name

specified for keyword keyword.
EXPLANATION:
The command was unable to write to the indicated file.The command terminates.
RESPONSE:
Ensure the file/directory exists and is writable, and then rerun.
ERROR (DFTS-003): [Internal] The progame cannot open and create the file file_name
when trying to action.
EXPLANATION:

DFTS - Design for Test Synthesis Messages
The command was unable to open/create the indicated file. The command terminates.
RESPONSE:
Contact customer support (see Contacting Customer Service on page 23).
ERROR (DFTS- 004): [Input] The insert_scan command was unable to determine the
number of scan chains desired. More input is required.
EXPLANATION:
The insert_scan command requires additional information to determine the number
of scan chains desired. This message indicates that insert_scan could not determine
this number based on the inputs provided.
RESPONSE:
Either supply an IOSpecList (using the iospeclistin keyword) or specify a value for
the keyword numscanchains to provide sufficient input for insert_scan to determine
the number of scan chains to be inserted.
ERROR (DFTS-005): [Input] Invalid value is specified with pin pinName for the
keywordName keyword.
EXPLANATION:
The specified value is invalid. If specified, only the values 0 or 1 are valid.
RESPONSE:
Correct the keyword value and rerun.
ERROR (DFTS-006): [Input] The keyword keyword must be specified for the
insert_scan command.
EXPLANATION:
insert_scan requires the named keyword to be specified.
RESPONSE:
Enter a valid value for the keyword and rerun.
ERROR (DFTS-007): [Input] The numchains parameter must be greater than or equal to
integer for compression_type compression.
EXPLANATION:

The requested type of compression requires a minimum number of scan chains to be

present. Fewer scan pins are not allowed since it will yield poor ATPG results or
diagnostic capability.
RESPONSE:
Specify a larger value for the numchains keyword and rerun.
ERROR (DFTS-013): [Input] The keyword keyword must be specified for the
build_top_shell command.
EXPLANATION:
build_top_shell requires the named keyword to be specified.
RESPONSE:
ERROR (DFTS-020): [Input] The value for misrsize must be divisible by 2.

EXPLANATION:
The value for the size of the OPMISR+ macro must be at least 16, at most 128, and must
be an even integer (divisible by 2).
RESPONSE:
ERROR (DFTS-021): [Input] When scanio=uni, the value for numchains must be even,
greater than or equal to 16, and less than or equal to 128. The specified numchains value
was integer.
EXPLANATION:
The value for numchains must be an even number ranging from 16 to 128 for
OPMISR+ with scanio=uni .
RESPONSE:
Specify a valid value for the keyword and rerun.
ERROR (DFTS-022): [Input] When scanio=bidi, the value for numchains must be
greater than or equal to 8, and less than or equal to 64. The specified numchains value was
integer.
EXPLANATION:
The value for numchains must range from 8 to 64 for OPMISR+ with scanio=bidi

RESPONSE:
ERROR (DFTS-023): [Input] The value for misrsize must be even, greater than or equal
to 16, and less than or equal to 128. The specified misrsize value was integer.
EXPLANATION:
The size of the MISR must be an even number ranging from 16 to 128 for OPMISR+ .
RESPONSE:
ERROR (DFTS-024): [Input] The value for numchannels integer must be at least twice
numchains integer.
EXPLANATION:
For XOR Compression, the number of scan channels (numchannel) must be two times
greater than the number of top-level scan chains (numchains).
RESPONSE:
Enter a valid value for the keyword and rerun. Refer to build_compression_macro in the
Encounter Test: Reference: Commands for keyword details.
ERROR (DFTS-025): [Input] For OPMISR+ generation the value of the misrsize parameter
times the fanout parameter must be smaller than 65536. The values requested are
misrsize (integer) and fanout (integer) (the product is integer).
EXPLANATION:
The size of the generated OPMISR+ compression is limited by size and time constraints.
RESPONSE:
Decrease the size of the MISR on the fanout parameter and rerun.

ERROR (DFTS-100): [Tool] BuildGates script generation aborted with major errors.
Consult filename for more information.
EXPLANATION:

The message indicates that the generation of the BuildGates script by Encounter Test
Synthesis terminated with major errors.
RESPONSE:
Examine the resulting error messages and respond accordingly.
ERROR (DFTS-101): [Internal] BuildGates script generation terminated with programming

error messages. Consult filename for more information.
EXPLANATION:
This message indicates that the generation of the BuildGates script by Encounter Test
Synthesis terminated with programming errors.
RESPONSE:
Contact customer support (see ).
ERROR (DFTS-102): [Tool] Processing aborted with major errors.

EXPLANATION:
This message indicates that the processing required by the command terminated with
major errors.
RESPONSE:
ERROR (DFTS-103): [Internal] Processing terminated with programming error messages.

EXPLANATION:
This message indicates that the processing required by the command terminated with
programming errors.
RESPONSE:
ERROR (DFTS-200): [Tool] Could not establish directory path.

EXPLANATION:
The program was unable to establish the fully qualified location of the specified path.
RESPONSE:
Verify the directory structure and specified path names are properly set up and rerun.

ERROR (DFTS-300): [Tool] Unable to obtain license.

EXPLANATION:
The program was unable to obtain the license required for Encounter Test.
RESPONSE:
Verify the availability of the necessary license.

WARNING (DFTS-400): BuildGates script generation completed with warning level
messages. Consult filename for more information.
EXPLANATION:
Synthesis issued warning level messages.
RESPONSE:
Examine the resulting warning level messages and respond accordingly.
WARNING (DFTS-401): BuildGates script generation completed with error messages.

Consult filename for more information.
EXPLANATION:
Synthesis issued error messages.
RESPONSE:
WARNING (DFTS-402): [severe] BuildGates script generation completed with severe error
EXPLANATION:
Synthesis issued severe level error messages.
RESPONSE:

WARNING (DFTS-403): BuildGates processing completed with error messages.

EXPLANATION:
This message Indicates that the processing performed by BuildGates issued error
messages. Netlist generation may have been unsuccessful or incomplete.
RESPONSE:
Examine the error messages issued by BuildGates and respond accordingly.
WARNING (DFTS-404): Processing completed with warning level messages.

EXPLANATION:
This message indicates that the processing required by the command issued warning
level messages.
RESPONSE:
Examine the resulting warning level messages and respond accordingly.
WARNING (DFTS-405): Processing completed with error messages.

EXPLANATION:
This message indicates that the processing required by the command issued error
messages.
RESPONSE:
WARNING (DFTS-406): [severe] Processing completed with severe error messages.

EXPLANATION:
This message indicates that the processing required by the command issued severe
level error messages.
RESPONSE:
WARNING (DFTS-410): Global Data will not be written. File filename was not found.
EXPLANATION:
A file required for the determination of data to be written to global data could not be
located. No global data will be written by this command.

RESPONSE:
WARNING (DFTS-411): Global Data will not be written. Could not establish topname.
EXPLANATION:
The value for topname is obtained from .globalData.dft. However there was a
problem in obtaining this value. No global data will be written by this command.
RESPONSE:
WARNING (DFTS-412): The build_opmisr_plus command has been replaced with the
build_compression_macro command. Please use that command instead. The
build_opmisr_plus command will be removed in a future release.
EXPLANATION:
The build_opmisr_plus command has been renamed because it can now build both
opmisr plus and xor compression macros.
RESPONSE:
Change scripts to use the build_compression_macro command instead of the
build_opmisr_plus command.
WARNING (DFTS-413): When inserting XOR compression and numchains is integer,

optimum test coverage can be achieved when the number of channels is less than or equal
to integer.
EXPLANATION:
For XOR compression, optimum test coverage is achieved when numchannels is less
than or equal to (n choose 3) + (n choose 4), where n is numchains.
RESPONSE:
For optimum test coverage, enter a low numchannel value and rerun.
WARNING (DFTS-414): The numchannels parameters is not divisible by numchains.

This will result in unbalanced FULLSCAN mode scan chains.
EXPLANATION:

For XOR compression, if specified numchannels value is not divisible by the specified
numchains value, the number of channels in each FULLSCAN chain will not be the
same, resulting in unbalanced scan chains.
RESPONSE:
Ensure the specified numchannels value is divisible by the specified numchains
value and rerun.
WARNING (DFTS-415): The size of the OPMISR+ macro is large and will take a lengthy
time to generate.
EXPLANATION:
RTL Compilation of large OPMISR+ macros tend to take more time.
RESPONSE:
Verify the compression parameters are correct and rerun if necessary.
INFO (DFTS-800): Creating file_description file_name.

EXPLANATION:
The command will attempt to create the file/directory named in the message.
RESPONSE:
No response required.
INFO (DFTS-801): The insert_scan command command_name is generating a

BuildGates script.
EXPLANATION:
The insert_scan command is automatically generating a BuildGates script file based
on the specified inputs.The script file is intended to be used as input to BuildGates for
scan insertion.
RESPONSE:
INFO (DFTS-802): BuildGates script generation completed successfully.

EXPLANATION:
Indicates that the insert_scan command successfully created a BuildGates script.
RESPONSE:

INFO (DFTS-803): Edif format requires the design to be mapped to the library before being
saved. A simple mapping will be performed.
EXPLANATION:
The Edif format cannot be used without tech-mapping the design. Techmap will be set to
1, and processing will continue.
RESPONSE:
INFO (DFTS-804): The insert_scan command is launching a BuildGates process.

EXPLANATION:
The insert_scan command is launching a BuildGates process for scan insertion.
RESPONSE:
INFO (DFTS-805): BuildGates processing completed successfully.

EXPLANATION:
BuildGates processing completed without errors.
RESPONSE:
INFO (DFTS-806): Launching process_name processing.

EXPLANATION:
The command is forking an instance of the program referenced in the message.
RESPONSE:
INFO (DFTS-807): Processing completed successfully.

EXPLANATION:
This message indicates that the processing required by the command was successful.
RESPONSE:

INFO (DFTS-808): The command command is using IOSpecList file filename for
processing.
EXPLANATION:
This message provides the names the file command is using as the IOSpecList.
RESPONSE:
INFO (DFTS-809): Executing command.

EXPLANATION:
This message lists the command being executed.
USER RESPONSE:
INFO (DFTS-810): Output netlist will be written to outnetlistdir.

EXPLANATION:
This message lists the directory the output netlist will be written to.
USER RESPONSE:
INFO (DFTS-811): Setting misrsize to integer based on scanio=string and

numchains=integer.
EXPLANATION:
The misrsize keyword was not specified in the command string and is being
determined from the number of scan chains requested.
USER RESPONSE:
INFO (DFTS-812): Setting numchains to integer based on scanio=string and

misrsize=integer.
EXPLANATION:

The misrsize keyword was specified in the command string. The numchains value is
being set to match.
USER RESPONSE:

5
EDAM - Extended Direct Access Method
Messages
EDAM-001 through EDAM-050 on page 55

EDAM-051 through EDAM-0160 on page 65
EDAM-001 through EDAM-050

WARNING (EDAM-001): [Severe] System error occurred while trying to mmap the EDAM
buffer file. Error code from mmap system call was (errno).
EXPLANATION:
The system failed to allocate the EDAM buffer. The most likely cause is insufficient swap
space left. Since the EDAM buffer space requirements are minimal (about 8 MB), this
error is unlikely to occur. The operating systems reason for failure should be provided on
the next line of output.
USER RESPONSE:
Make sure the system has sufficient swap space to run the application.
WARNING (EDAM-001): [Severe] System error occurred while trying to munmap the
EDAM buffer file. Error code from munmap system call was (errno).
EXPLANATION:
The system failed to free the EDAM buffer. This is a very unlikely error and should only
occur if the operating system has failed, possibly due to memory corruption. The
operating systems reason for failure should be provided on the next line of output.
USER RESPONSE:
Check the error code from the system to see if anything can be done.
INFO (EDAM-003:) EDAM Debugging has been enabled.

EDAM - Extended Direct Access Method Messages
EXPLANATION:
The environment variable EDAMDEBUG was set or an application has explicitly turned on
debug checking. This will cause EDAM to continually check the validity of its internal
buffer control blocks. This debug checking is usually done only in an effort to find
programming errors.
USER RESPONSE:
INFO (EDAM-004): EDAM default paging buffer size has been overridden to numbytes.
EXPLANATION:
The environment variable EDAMRAM was set and this has caused EDAM to change the
default buffer size from approximately 8 Megabytes to the number of bytes specified in
the EDAMRAM variable (numbytes).
USER RESPONSE:
WARNING (EDAM-005): EDAM file locking has been disabled. Avoid use of the same files
by applications running simultaneously.
EXPLANATION:
The environment variable TB_NOLOCK or TFWDDMNOLOCK has been set. This will
prevent EDAM from performing normal file locking operations. This can cause files to
become corrupted and is intended for expert use only.
USER RESPONSE:
INFO (EDAM-006): EDAM maximum paging buffer size was exceeded. Size set to
numbytes.
EXPLANATION:
The environment variable EDAMRAM was set and this has caused EDAM to change the
default buffer size from approximately 8 Megabytes to the number of bytes specified in
the EDAMRAM variable except that this would exceed the maximum buffer size allowed.
The buffer size is set to (numbytes) which is the current maximum allowed buffer size.
On the 32-bit systems,
The maximum buffer size is about 1GB. On 64-bit systems, the maximum buffer size is
about 64GB.

USER RESPONSE:
If a higher buffer size is needed, contact customer support (see Contacting Customer
ERROR (EDAM-010): [Internal]IEDAMsfre found an empty Page Table or PTD with a

useCount of count.
EXPLANATION:
This is most likely a programming error.
USER RESPONSE:
WARNING (EDAM-011): [Severe] Application is attempting to mmap an area of (request)

bytes, which is too large for a 32-bit system.
EXPLANATION:
The application is requesting to map more than 2 GBytes of data while running on a 32-
bit operating system. This request can only be satisfied by running on a 64-bit operating
system.
USER RESPONSE:
Run the application on a 64-bit operating system.
WARNING (EDAM-012): [Severe] System error trying to map file filename.

Offset = offsetllx, Length = lengthllu
EXPLANATION:
The operating system failed while trying to map a portion of the filename file into
memory starting at offset offset bytes into the file for a length of length bytes.
There may be other messages to help determine why the system failed.
USER RESPONSE:
Determine why the system failed. If possible, remove the cause of the problem and try
again.
WARNING (EDAM-013): [Severe] Error trying to unmap file filename.

EXPLANATION:
The operating system failed while trying to unmap a portion of the filename file from
memory. There may be other messages to help determine why the system failed.

USER RESPONSE:
again.
ERROR (EDAM-014): [Internal]Internal error trying to map file filename.

EXPLANATION:
The EDAM utility detected an internal programming error.
USER RESPONSE:
WARNING (EDAM-015): [Severe] Error trying to unmap storage at (address) for file
filename.
EXPLANATION:
The operating system failed while trying to unmap a portion of the filename file from
memory. There may be other messages to help determine why the system failed.
USER RESPONSE:
again.
WARNING (EDAM-016): Attempting to by-pass SunOS bug. This bug does not allow
mapping an NFS file when locks exist against any file. File data will be copied into memory -
requiring more swap space.
EXPLANATION:
This message is obsolete and should never be seen. There is no longer a warning
message produced when this SunOS bug is bypassed.
USER RESPONSE:
ERROR (EDAM-017): [Internal]Application error. NULL pointer passed to EDAMread.

Application was accessing file filename.
EXPLANATION:
The EDAM utility detected an application programming error. The buffer parameter must
be a valid pointer and was found to be NULL.
USER RESPONSE:

WARNING (EDAM-020): [Severe] System error occurred while opening file filename.
Look at the following system message to understand why:
EXPLANATION:
The operating system failed while trying to open the filename file. The systems
reason for failing is printed on the next line of output.
USER RESPONSE:
again.
WARNING (EDAM-021): [Severe] System error while removing file filename. Look at
subsequent system messages for further information.
EXPLANATION:
The operating system failed while trying to remove the filename file. The systems
reason for failing is printed on the next line of output.
USER RESPONSE:
again.
WARNING (EDAM-022): Unable to obtain use of file filename because other users of this
file exist and their use of the file conflicts with the current request for purpose use of the file.
Try again later.
EXPLANATION:
The system failed to provide locks to access the filename file. The most likely reason
is that some other process (perhaps on a different processor) is already using this file in
a manner that conflicts with the desired purpose for this process. Two processes cannot
write to a file at the same time. Only one process can obtain mutually exclusive use of a
file.
USER RESPONSE:
Wait for the other use of the file to end and try again.
In certain cases where systems have crashed without returning their outstanding locks,
it is possible for the system to assume there is a lock outstanding when in fact the original
process is no longer alive. There is no simple solution to free up such locks, but the
following steps may be used and may work in many situations:

Remove all .lock* files in the directory containing the file by being in that
directory and using this command: rm .lock*
If there is a locks subdirectory there, remove all files there by using this
command: rm locks.
The above steps are drastic and should be done only when it is known that there are no
processes currently running that may be using any of the files in the same directory as
the file that could not be locked.
WARNING (EDAM-023): [Severe] The fsync() failed for file filename. Unable to ensure
updates to this file have been written to disk. Checkpointing of this file is incomplete due to a
system error:
EXPLANATION:
The system failed to sync the filename file, which may mean that the checkpoint
operation is corrupted and that the system may not be able to successfully restart/reopen
this file.
USER RESPONSE:
If the reason the sync failed (which should be stated immediately following this message)
is due to insufficient space, you should make sure the file system being used has
sufficient space before trying this again. If at least one previous checkpoint was
successful, you should be able to restart the application once additional file system
space has been provided. If the restart is successful, it will pick up wherever the previous
checkpoint had left off.
INFO (EDAM-024): Opening file filename for purpose access.

EXPLANATION:
The file filename is being opened for purpose use. This is informational only and
is printed as debug information if the EDAMFILES environment variable is defined.
USER RESPONSE:
INFO (EDAM-025): Closing file filename.

EXPLANATION:
The file filename is being closed. This is informational only and is printed as debug
information if the EDAMFILES environment variable is defined.
USER RESPONSE:

WARNING (EDAM-026): The fsync() failed for file filename due to a network or system
timeout.
EXPLANATION:
The system failed to sync the filename file because of a network timeout. The fsync()
operation will be retried a limited number of times. See the explanation for message
EDAM-054 for more details.
USER RESPONSE:
If the system continues to timeout even after all retry attempts, try to determine why the
system (network) is timing out and fix that problem before running the application again.
WARNING (EDAM-027): Unable to obtain use of file filename because permission to lock
the file was denied. User has permission for purpose use of the file, but cannot lock it. Get
permission to lock the file.
EXPLANATION:
The system failed to provide locks to access the filename file. The reason appears to be
due to lack of permission to lock the file. Some file systems have separate permissions
for locking. For example, the Andrew File System (AFS) has separate permissions (-k)
for locks.
USER RESPONSE:
Have the owner of the directory give you permission to lock files. For cases where the file
being accessed is linked to the real file, ensure that you have permission to lock the
target file. For example, if the target file is in an AFS directory, for read-only use ensure
you have rlk (read, list and lock) permission to the containing directory.
WARNING (EDAM-028): [Severe] System error occurred while opening lock file
filename. Look at the following system message to understand why:
EXPLANATION:
The operating system failed while trying to open the filename file.The systems reason
for failing is printed on the next line of output.
USER RESPONSE:
Determine why the system failed. If possible, remove the cause of the problem and rerun.
INFO (EDAM-029): File filename changed while awaiting lock. Trying again...
EXPLANATION:

While waiting for a lock against the referenced file, some other process updated the file.
Since there are two versions of the data kept within an EDAM file, we have to lock the
appropriate version. Because the file has been updated, we have to release the locks
and try to get a lock against the newer version of the file. If there are many parallel
processes trying to update the same EDAM file, only one will get the file at a time. Such
serialization could cause some processes to wait quite some time before the lock is
issued without the file changing.
USER RESPONSE:
This is normal behavior when multiple processes attempt to update the same EDAM file.
This serialization mechanism is necessary to ensure only one process gets authority to
make updates to the file at any one time. This informational message is intended to alert
you to the fact that several processes are trying to update the referenced file and delaying
access to it.
ERROR (EDAM-030): [Internal] Storage Area handle (handle) not in open list for file
filename".
EXPLANATION:
The EDAM utility detected an application programming error. The calling application
requested to close or delete a storage area, but the handle provided is not valid.
USER RESPONSE:
ERROR (EDAM-040): [Internal]Internal error: LRU page not free!! Paging buffers are
corrupted.
EXPLANATION:
The EDAM utility detected that its internal buffers were corrupted. The problem could be
caused by either an internal EDAM error, or by an application that erroneously wrote on
top of the EDAM buffers. To prevent the possible corruption of files that have not yet been
closed, EDAM forces the process to end.
USER RESPONSE:
ERROR (EDAM-041): [Tool] EDAM is shutting down to avoid corrupting data.

EXPLANATION:

USER RESPONSE:
ERROR (EDAM-042): [Internal] LRU Page Table (page) has use count = count.
EXPLANATION:
top of the EDAM buffers. EDAM forces the process to end.to prevent the possible
corruption of files that have not yet been closed.
USER RESPONSE:
ERROR (EDAM-043): [Internal] Unrecognized page (page) of type (type) found in the
LRU queue.
EXPLANATION:
USER RESPONSE:
ERROR (EDAM-044): [Internal] Data page (page) has invalid parent (page2).
EXPLANATION:
USER RESPONSE:
ERROR (EDAM-045): [Internal] Page Table Directory (page1) has invalid page table
directory (page2).

EXPLANATION:
USER RESPONSE:
ERROR (EDAM-046): [Internal] Page Table Directory (page1) has invalid file control block
(page2).
EXPLANATION:
USER RESPONSE:
ERROR (EDAM-047): [Internal] Available pages = num1 not equal numPagesAvail =

num2.
EXPLANATION:
The EDAM utility detected that its internal buffers were corrupted. The two available page
counts should always be equal but were found not to be. This is likely to be an internal
EDAM program error.
USER RESPONSE:
ERROR (EDAM-048): [Internal] PTD Directory (page1) has invalid file control block
(page2).
EXPLANATION:
caused by either an internal EDAM error, or by an application that wrote on top of the
EDAM buffers in error. To prevent the possible corruption of files that have not yet been
USER RESPONSE:

EDAM-051 through EDAM-0160

ERROR (EDAM-050): [Internal] EDAM Current Limitation of 1 file exceeded while
processing file filename. Alert Encounter Test development.
EXPLANATION:
The EDAM utility in its current implementation cannot allocate more than 1 physical file
to deal with a single large logic EDAM file. Since this is a fundamental limitation, EDAM
will end the process. The file being processed is simply too large for the system. In some
rare cases, this error message can occur due to a programming error rather than
because a file is too large.
USER RESPONSE:
WARNING (EDAM-051): [Severe] System error occurred while Seeking to (offset) in file
filename.
EXPLANATION:
The operating system failed while trying to read data from a location offset bytes
from the beginning of the filename file. The systems reason for failing is printed on
the next line of output.
USER RESPONSE:
again.
WARNING (EDAM-052): [Severe] System error occurred while Writing to offset in file
filename.
EXPLANATION:
The operating system failed while trying to write data to a location offset bytes from
the beginning of the filename file. The systems reason for failing is printed on the
next line of output. A typical reason for failing is no space left on disk.
USER RESPONSE:
again.

WARNING (EDAM-053): [Severe] System error occurred while Reading numbytes bytes
into address address from offset in file filename.
EXPLANATION:
The operating system failed while trying to read data from a location offset bytes
from the beginning of the filename file. numBytes of data was being read into
process memory at location address. The systems reason for failing is printed on the
next line of output.
USER RESPONSE:
again.
INFO (EDAM-054): Waiting 10 seconds and trying again (retry # try of maxtries).
EXPLANATION:
The previously reported I/O failure appears to be a network timeout problem, so we
attempt to recover by waiting a few seconds and trying the I/O again. This is attempt
number try. The I/O will be attempted up to maxtries times before giving up.
USER RESPONSE:
If the retry succeeds, there is nothing more to do; otherwise, try to determine why the
system is timing out. If possible, remove the cause of the problem and try again. You can
change the number of retry attempts allowed to the value of the TB_RETRY environment
variable. For example, TB_RETRY=2 or TB_RETRY=100. Setting TB_RETRY=0 will
cause the system to fail immediately with no retry attempts.
WARNING (EDAM-055): An I/O operation failed for file filename.

EXPLANATION:
The system failed to perform an I/O operation for the filename file. The I/O operation
will be retried a limited number of times. See the explanation for message EDAM-054 for
more details.
USER RESPONSE:
If the system continues to timeout even after all retry attempts, try to determine why the
I/O operation is failing and fix that problem before running the application again.
ERROR (EDAM-060): [Internal] Internal error: file filename has no FREE Queue!
EXPLANATION:

The EDAM utility detected an internal programming error. The internal File Control Block
for the open filename file is missing a queue of free disk pages.
USER RESPONSE:
ERROR (EDAM-061): [Internal] Internal error: file filename has no AVAIL Queue!
EXPLANATION:
The EDAM utility detected an internal programming error. The internal File Control Block
for the open filename file has an empty queue of available disk pages.
USER RESPONSE:
ERROR (EDAM-062): [Internal] Internal error: file filename next free slot (slotID),
not on disk!
EXPLANATION:
The EDAM utility detected an internal programming error. While processing the
filename file, an invalid disk address slotID was selected as the next free slot to
write data to.
USER RESPONSE:
WARNING (EDAM-063): [Severe] File filename is too large. EDAM limit of 1 Terabyte
reached.
EXPLANATION:
The EDAM utility attempted to write a page to file filename, but this would have
created a file larger than 1 Terabyte in size. This exceeds the current maximum storage
capability for a single EDAM file. The application writing this file will need to be rewriten
to either write less data, or use multiple files to store all of its data.
USER RESPONSE:
INFO (EDAM-070): Waiting to obtain purpose use of file filename.

EXPLANATION:

The system failed to provide locks to access the referenced file. The most likely reason
is that some other process (perhaps on a different processor) is already using this file in
a manner that conflicts with the desired purpose for this process. Two processes
cannot write to a file at the same time. Only one process can obtain mutually exclusive
use of a file.
USER RESPONSE:
Wait for the other use of the file to end and this process should then continue. If the
process never continues, the system may think the lock is held by a process (perhaps on
another system on the network) that is no longer running.
In certain cases where systems have crashed without returning their outstanding locks,
it is possible for the system to assume there is a lock outstanding when in fact the original
process is no longer alive. There is no simple solution to free up such locks, but the
following steps may be used and may work in many situations:
1. Remove all .lock* files in the directory containing the file by being in that
directory and using this command: rm .lock*
2. If there is a locks subdirectory there, remove all files thereby using this
command: rm locks/*.
3. If this process continues to wait, you may have to kill the process.
The preceding steps are drastic and should be done only when it is known that there are
no processes currently running that may be using any of the files in the same directory
as the file that could not be locked.
INFO (EDAM-071): Waited time time to obtain purpose use of file filename.
EXPLANATION:
This process waited for the referenced amount of elapsed time to gain access to the
referenced file for the referenced purpose. This is normal for serialized access to
updatable files.
USER RESPONSE:
If the wait time is very long, there may be multiple processes attempting to update the
same file or a long running process may tie up the file for read-only use. To avoid this, do
not run parallel tasks that need the same file for long periods of time.
ERROR (EDAM-100): [Internal] Application Error: Too little memory supplied to EDAM for
buffers. Memory given = given, minimum allowed = minimum.
EXPLANATION:

An application program failed to give the EDAM utility enough buffer space.
USER RESPONSE:
ERROR (EDAM-110): [Internal] Application Error: EDAMsfre or EDAMsfre64 addr1

parameter (addr) not on a page boundary.
EXPLANATION:
An application program parameter, addr1, has a (hex) value of addr which is not on a
page boundary. This is not legal as input to the EDAMsfre or EDAMsfre64 function.
USER RESPONSE:
ERROR (EDAM-111): [Internal] Application Error: cannot find mapped area to be

unmapped. mapped addr=(addr), File = filename.
EXPLANATION:
An application program attempted to unmap an area of storage that EDAM could find no
record of being mapped. The application program has probably tried to free the storage
more than once.
USER RESPONSE:
ERROR (EDAM-112): [Internal] Application Error: An offset of xoffset was specified

to EDAMsget64, EDAMsput64, EDAMnxra64, EDAMsfre64, EDAMmap64, or EDAMread64,
which exceeds the offset limit of x0000040000000000 of EDAM64. Application was
accessing file filename.
EXPLANATION:
The EDAM utility detected an application programming error. The application attempted
to access an offset within a storage area that is beyond the current limits allowed by the
EDAM utility. The current offset limit is x0000040000000000, which represents an offset
4 TeraBytes into the storage area.
USER RESPONSE:
ERROR (EDAM-120): [Internal] Application Error: Invalid file handle (handle) specified.

EXPLANATION:
An application program provided an invalid EDAM file handle to an EDAM program
interface (such as EDAMfcls). The application program probably closed the file already
or never opened it.
USER RESPONSE:
WARNING (EDAM-121): [Severe] EDAM paging buffers too low (numBuffers). File
filename is not opened. Application should close some files or storage areas to free up
buffers.
EXPLANATION:
The EDAM paging buffers only have numBuffers free, which is too few to allow
another file to be opened. The opening of the filename file fails. There appears to be
too many open files and open storage areas forcing buffers to be removed from service.
USER RESPONSE:
WARNING (EDAM-122): Application has opened file filename too often (numOpens).
File is not opened for caller.
EXPLANATION:
The file filename was opened numOpens times, which is the limit of how many
times the same file can be opened without it ever being closed. The calling application
will probably fail. The application should be modified to keep track of opened file handles.
USER RESPONSE:
WARNING (EDAM-123): Application warning: CheckPointing file filename which was.

NOT opened for Global Exclusive use. File is CheckPointed. This could cause problems if
other processes access the file.
EXPLANATION:
The file filename was opened for updating, but was not opened for mutually exclusive
use. This provides an exposure to the checkpoint processing if there are other processes
which are reading the file. These other processes could fail. Any file that will be
checkpointed should be opened for exclusive use.
USER RESPONSE:

ERROR (EDAM-124): [Internal] Application error: CheckPointing file filename which

was. NOT opened for update. File is not CheckPointed.
EXPLANATION:
The file filename is attempting to be checkpointed, but is was opened for read-only
processing. The application should be fixed to open the file being checkpointed for
mutually exclusive update access.
USER RESPONSE:
ERROR (EDAM-130): [Internal] Application error: request to open storage area (areaID)
denied. Valid range for a storage area number is (0 to maxID).
EXPLANATION:
An application attempted to open a 32-bit storage area within a file but specified an
numeric ID areaID outside the allowed range of 0 to maxID. The application should
be fixed.
USER RESPONSE:
WARNING (EDAM-131): [Severe] EDAM paging buffers too low (numBuffers). Storage
Area (areaID) in File filename is not opened. Application should close some files or
storage areas to free up buffers.
EXPLANATION:
The EDAM paging buffers only have numBuffers free, which is too few to allow
another storage area to be opened. The opening of the storage area fails. There appears
to be too many open files and open storage areas forcing buffers to be removed from
service.
USER RESPONSE:
ERROR (EDAM-132): [Internal] Application error: Invalid storage area handle (handle)
specified.
EXPLANATION:

The application program supplied a storage area handle that is not valid. It may be
because it used to be a valid handle, but that storage area is no longer open. The
application needs to be fixed.
USER RESPONSE:
ERROR (EDAM-134): [Internal] Application error: EDAMsdel request to close Storage

Area (handle) in file filename is denied. Storage area is currently opened (numOpens)
times. A storage area must be opened exactly once to delete it.
EXPLANATION:
The application program tried to close and delete a storage area in file filename, but
the storage area handle indicates it was opened numOpens times. A storage area
can only be deleted if it is opened exactly one time.
USER RESPONSE:
WARNING (EDAM-135): [Severe] Application error: request to find next storage area after
(areaID) denied. Valid range for a storage area number is (0 to maxID).
EXPLANATION:
An application specified a storage area numeric ID of areaID which is outside the
allowed range of 0 to maxID. The application should be fixed.
USER RESPONSE:
ERROR (EDAM-140): [Internal] Application error: Closed Storage area (areaID) for file
filename appears to have been referenced after it was closed.
EXPLANATION:
An application appears to have referenced data within a storage area that is currently
closed. The storage area ID areaID within the filename file is one in error. The
application should be fixed.
USER RESPONSE:
WARNING (EDAM-154): [Severe] Application error: File filename is not a valid EDAM
file.

EXPLANATION:
The file filename appears not to be a valid EDAM file. The file cannot be opened for
access by EDAM. Either the user has specified some identifiers incorrectly, the file has
been corrupted, or the application had provided the wrong file name.
USER RESPONSE:
Make sure you have supplied the correct identifiers to the application program and that
the file reference has not been corrupted. If everything looks OK but continues to fail,
contact customer support (see Contacting Customer Service on page 23).
WARNING (EDAM-160): [Severe] Application error: file filename has been modified,
but it was opened for READONLY use!
EXPLANATION:
An application appears to updated the file filename, but it was opened for read-only
access. The file is not updated. The application should be fixed.
USER RESPONSE:


6
FW - Graphical User Interface Framework
Messages
FW-001 through FW-050 on page 75

FW-051 through FW-100 on page 87
FW-001 through FW-050

ERROR (FW-001): [Tool] Unable to initialize the Graphical User Interface - return
code=gui_return_code
EXPLANATION:
The graphical user interface initialization failed to return a valid return code.
USER RESPONSE:
Check for messages from the TUI component
ERROR (FW-002): [Tool] Unable to close the Graphical User Interface

EXPLANATION:
The graphical user interface initialization failed to return a valid return code on a close.
USER RESPONSE:
ERROR (FW-003): [Tool] Graphical Interface does not match current environment
EXPLANATION:
A method attempted to connect to an existing motif Encounter Test GUI and the current
environment in the Tcl Gui does not match the environment in the motif Encounter Test
GUI. The setHostAddress first argument requested that an error be issued in this
case.

FW - Graphical User Interface Framework Messages
USER RESPONSE:
Either invoke setProject, etc. to force the script to be working in the same
environment as the graphical user interface, or issue an error message and quit, or
specify a different action in the setHostAddress first parameter
ERROR (FW-004): [Tool] Unable to connect to existing graphical user interface. Return
code=returnCode.
EXPLANATION:
A method attempted to connect to an existing graphical user interface, but the underlying
code was unable to connect to that interface. The return code from the underlying code
is specified in the returnCode field.
USER RESPONSE:
Either execute setHostAddress with a null argument to force a new graphical user
interface to start up, or determine why you were unable to connect to the host address
specified in setHostAddress.
ERROR (FW-005): [Input] Invalid WORKDIR : project

EXPLANATION:
The value specified for keyword WORKDIR is not a valid directory
USER RESPONSE:
Check either the environment variable PROJECT or global variable WORKDIR to ensure it
is a valid directory.
ERROR (FW-006): [Input] Invalid WORKDIR subdirectory : project/entity

EXPLANATION:
The value specified as an ENTITY is not a valid sub-directory of WORKDIR.
USER RESPONSE:
Check both the environment variable ENTITY and PARTID and validate that their values
represent a valid sub-directory to WORKDIR.
ERROR (FW-007): [Input] Invalid TESTMODE : testmode

EXPLANATION:
The value specified as a testmode is not a valid testmode for the current project and
entity.

USER RESPONSE:
Check either the environment variable TESTMODE, or the value of the setEnv testmode
method to ensure it is a valid testmode for the current part.
ERROR (FW-008): [Input] Invalid EXPERIMENT : experiment

EXPLANATION:
The value specified as a experiment is not a valid experiment for the current project,
entity, and testmode.
USER RESPONSE:
Check either the environment variable EXPERIMENT, or the value of the setEnv
experiment method to ensure it is a valid experiment for the current testmode.
ERROR (FW-009): [Input] Invalid FAILSET : failset

EXPLANATION:
The value specified as a failset is not a valid failset for the current project, entity,
and testmode, and experiment.
USER RESPONSE:
Check either the environment variable FAILSET, or the value of the set failset method to
ensure it is a valid failset for the current experiment.
ERROR (FW-010): [Input] Invalid DELAYMODEL : delayModel

EXPLANATION:
The value specified as a delay model is not a valid delay model for the current
project, and entity.
USER RESPONSE:
Check either the environment variable DELAYMODEL, or the value of the
setdelaymodel method to ensure it is a valid delay model for the current part.
ERROR (FW-011): [Input] Invalid HOSTADDRESS : hostAddress

EXPLANATION:
The value specified as a host address is not valid. The host address must consist of four
integers, separated by periods, followed by a colon, followed by a fifth integer e.g.
9.130.46.7:5501
USER RESPONSE:

Check either the environment variable TB_HOSTADDR, or the value of the

setHostAddress method to ensure it is a valid host address.
WARNING (FW-012): [Severe] Graphics connection action of connectionAction not

recognized.
EXPLANATION:
The first argument to the setHostAddress method must be one from the valid action
list: spawn, control, or error. The connection action specified does not match any of these
entries.
USER RESPONSE:
Fix the first argument to setHostAddress. A value of spawn, or no value specified
indicates that if the graphical user interface is working on a different part, then the
connect should not occur, but a new graphical user interface should be created. A value
of error indicates that if the graphical user interface is working on a different part, an
error should occur. A value of control indicates that if the graphical user interface is
working on a different part, the graphical user interface should be forced to work on the
same part as the current script.
ERROR (FW-013): [Tool] Unable to save registration and dependency information

EXPLANATION:
Any global data changes did not become persistent. Global data will not reflect any
updates.
USER RESPONSE:
Check for possible low system resources, or global data write authority.
ERROR (FW-014): [Tool] Failed to remove dependencies on nameObject

EXPLANATION:
The named object is registered in global data, but has failed to remove any dependencies
registered on the object.
USER RESPONSE:
Use TFWgdata to validate that the given named object has registered dependencies. If
so, check for global data write authority.
WARNING (FW-015): nameObject is not registered in global data. No global data

updates occurred.
EXPLANATION:

The given named object is not registered in global data. No global data updates were
performed. Register the named object into global data first.
USER RESPONSE:
Use the Tcl Command registerObject method to register the named object into
global data.
ERROR (FW-016): [Tool] Failed to register nameObject in global data.

EXPLANATION:
Global data could not register the given object.
USER RESPONSE:
Using TFWgdata, validate the given object is not previously registered, or registered with
dependencies in global data. If not, check for global write authority.
ERROR (FW-017): [Tool] Failed to unregister nameObject in global data.

EXPLANATION:
Global data failed to unregister the given name object.
USER RESPONSE:
Using TFWgdata, validate that the given named object is registered in global data. If so,
then check for global data write authority.
ERROR (FW-018): [Tool] Failed to register dependent child on object parent in global
data.
EXPLANATION:
Global data failed to register the dependent child object to the parent object with a
specified dependency type of file, stat, char, or all.
USER RESPONSE:
Validate that the parent and child objects are registered in global data using TFWgdata.
If so, check for global data write authority.
ERROR (FW-019): [Tool] Failed to unregister dependent child on object parent in

global data.
EXPLANATION:
Global data failed to unregister the child object dependency on the given parent object.

USER RESPONSE:
Using TFWgdata, validate that the parent and child objects are registered in global data,
and that the child is also registered as a dependency to the parent. If so, check for global
data write authority.
WARNING (FW-020): WORKDIR is set to NULL.

EXPLANATION:
The value specified as WORKDIR is not a valid directory.
USER RESPONSE:
Tcl Gui accepts the NULL value under the assumption that the PROJECT environment
variable is to be unset.
WARNING (FW-021): WORKDIR sub-directory is set to NULL

EXPLANATION:
The value specified as an entity is not a valid sub-directory of the project specified in the
environment variable PROJECT or global variable WORKDIR.
USER RESPONSE:
Tcl Gui accepts the NULL value under the assumption that s the ENTITY environment
variable is to be unset.
WARNING (FW-022): [Severe] Invalid CALLOUT : failset

EXPLANATION:
The value specified as a callout is not a valid callout for the current project, entity,
testmode, and experiment.
USER RESPONSE:
Check either the environment variable CALLOUT, or the value of the setEnv callout
method to ensure it is a valid callout for the current experiment.
WARNING (FW-023): [Severe] Tcl Gui framework method methodName does not
recognize key keyName
EXPLANATION:
Invalid key for Tcl Gui for specified method call.
USER RESPONSE:

See TCL Gui documentation for a listing of recognized keys for this method.
WARNING (FW-024): Global Data List is NULL for parent pName and child cName
EXPLANATION:
The specified parent and child do not exist in global data.
USER RESPONSE:
Use TFWgdata to verify contents of global data.
WARNING (FW-025): Global Data Stat is NULL for object objName and key keyName
EXPLANATION:
The specified Object and Key do not exist in global data.
USER RESPONSE:
Use TFWgdData to verify contents of global data.
ERROR (FW-026): [Tool] Unable to display the Graphical User Interface viewName
Window.
EXPLANATION:
The viewName could not be displayed. The following are possible causes:
The design model is currently being modified by another application.
The design model could not be loaded.
The TUIgui or TUIserv analysis process could not be started.
USER RESPONSE:
Check for messages in the window from which the Encounter Test GUI was started.
If locking messages are produced, wait until modification of the design model is
complete and then proceed with your analysis. Note that the application
modifying the design model may be one which you started, or one which is
being run by a colleague.
If you see messages concerning the hierModel or hierAttributes file, it
may indicate that the file is corrupt or incomplete. Try rebuilding the model. If
this does not fix the problem, contact customer support (see Contacting

If you see messages concerning TUIgui or TUIserv, this likely indicates a

path or installation problem. Contact your local Cadence tool support person. If
that does not resolve the problem, contact customer support (see Contacting
ERROR (FW-028): [Tool] Unable to display the objectType objectIndex.

EXPLANATION:
The specified objectType failed to be displayed on View Schematic Display. The
index must be zero or greater, and less than the total number for objectType.
USER RESPONSE:
Enter a valid objectType for the desired objectIndex.
INFO (FW-029): There are no messages to view.

EXPLANATION:
There are no messages available for the application.
USER RESPONSE:
WARNING (FW-030): Problem detected while closing GlobalData.

EXPLANATION:
The closing of globalData for the current part detected some difficulties. It may be the file
was already closed.
USER RESPONSE:
Check permissions. Refer to any previous TFW messages. If the file was already closed,
no previous TFW message will exist.
ERROR (FW-031): [Input] -workdir and -projectname are mutually exclusive.

EXPLANATION:
When opening a project, either -workdir or -projectname can be specified, but not
both.
USER RESPONSE:
Only specify one option, not both.
ERROR (FW-032): [Input] workdir is not a valid project (part) directory.

EXPLANATION:
The specified project (part) directory does not preexis, or was incorrectly entered from
the TCL command.
USER RESPONSE:
Provide a valid preexisitng project directory or use the new_project TCL command to
create a new project directory.
ERROR (FW-033): [Input] The specified Alias: projectName, is unknown.

EXPLANATION:
The TCL open_project command cannot find the specified preexisting alias that
represents a project (part) directory.
USER RESPONSE:
Use TCL open_project -workdir option and specify the fully qualified project (part)
directory instead of using the alias option -projectname. To create an alias, specify the
fully qualified project directory using the -workdir option and the
-newprojectname aliasname option. Subsequently, when calling open_project,
specify just the -projectname aliasname.
WARNING (FW-034): No value specified for -projectname, ignoring option.

EXPLANATION:
The TCL open_project command requires a value specified when using the option
-projectname.
USER RESPONSE:
The -projectname option value is an aliasname for a project (part) directory. This
option is typically used instead of specifying a fully qualified part directory using the -
workdir option. The aliasname must preexist in order to use this option. See
open_project in the Encounter Test: Reference: Commands for additional
information.
INFO (FW-035): Unrecognized argument: theArg, ignoring option.

EXPLANATION:
The TCL command did not recognize the input argument option and ignores it.
USER RESPONSE:

See the Encounter Test: Reference: Commands for the TCL commands list of valid
options, or utilize the TCL commands -h (HELP) option.
INFO (FW-036): Unrecognized argument: theArg, ignoring value.

EXPLANATION:
An argument value was found without a corresponding option, and is ignored.
USER RESPONSE:
See the Encounter Test: Reference: Commands for the TCL commands list of valid
options, or utilize the TCL commands -h (HELP) option.
INFO (FW-037): No project directory specified, using default current directory.

EXPLANATION:
The TCL command did not detect options specified that indicated a project (part)
directory, and is therefore using the current working directory as the project directory.
USER RESPONSE:
Refer to open_project in the Encounter Test: Reference: Commands or use the -h
option for more details on entering a specified project directory to override the defaulted
behavior for the TCL command.
WARNING (FW-038): [Severe] Failed to create Alias: aliasname, Reason:

theErrorCode
EXPLANATION:
The Tcl command failed in the attempt to create an Alias directory to hold the new Alias
in the users Home directory.
USER RESPONSE:
Check permissions or disk space on the home directory or contact Cadence support (see
ERROR (FW-039): [Input] The specified -setupfile setupfile, is an invalid file.

EXPLANATION:
The TCL command does not recognize the specified setupfile as a valid file type.
USER RESPONSE:
Make sure the specified setupfile is a preexisting file and that it is specified as a fully
qualified filename.

INFO (FW-040): The -setupfile option is not specified - defaulting to filename

setupfile.
EXPLANATION:
The TCL command did not detect the option -setupfile specified. The defaulted
filename: setup, found in the current working directory will be used.
USER RESPONSE:
To override the default, -setupfile must be specified with a fully qualified filename.
INFO (FW-041): Proceeding without a setupfile...

EXPLANATION:
The TCL command did not detect the option -setupfile specified. The defaulted
filename: setup could not be found in the current working directory. Therefore, no
setupfile will be utilized.
USER RESPONSE:
If a setup file is desired, specify the -setupfile option with a fully qualified filename, or
ensure a file named setup (the default name) is in the current working directory.
ERROR (FW-042): [Input] Create project failed because dirname is not a valid directory.
EXPLANATION:
The TCL command new_project failed to create a new project (part) directory because
the fully qualified path that will contain the new project directory is invalid.
USER RESPONSE:
Specify a valid pathname (directory structure).
ERROR (FW-043): [Tool] Failed to create the project directory: projectname, Error
theErrorCode
EXPLANATION:
The Tcl command failed in the attempt to create a new project (part) directory.
USER RESPONSE:
Check for directory write permissions, or contact Cadence support (see Contacting
ERROR (FW-044): [Tool] Failed to create the project directory: projectName/tbdata,

Error theErrorCode

EXPLANATION:
The Tcl command failed in the attempt to properly create a new project (part) directory
structure.
USER RESPONSE:
Check for directory write permissions, or contact Cadence support (see Contacting
INFO (FW-045): The -projectname option to create an Alias was not specified. Defaulting
Alias value to projectname.
EXPLANATION:
When creating a new project, an alias for the project directory must be specified through
option -projectname. If it is not specified, the tail of the fully qualified new project is
used as the aliasname by default.
USER RESPONSE:
Specify the -projectname option with a value to override this default behavior.
WARNING (FW-046): Setup file invalid syntax, ignoring entry : setupfilename.

EXPLANATION:
While processing user-specified setupfile, a syntax error was detected in a line item
specification, and was ignored.
USER RESPONSE:
Refer to Setup and Methodology Files Overview in the Encounter Test: Reference:
GUI for proper syntax when creating a setup file for a project.
WARNING (FW-047): Catch Error - catchErr : Setup file invalid syntax, ignoring entry :
setupfileline.
EXPLANATION:
While processing user specified setupfile, a syntax error was detected in a line item
specification, was caught by set_global, and was ignored.
USER RESPONSE:
Refer to Setup and Methodology Files Overview in the Encounter Test: Reference:
GUI for proper syntax when creating a setup file for a project.
WARNING (FW-048): [Severe] The specified -setupfile setupfile does not exist.

EXPLANATION:
The TCL command does not recognize the specified setupfile.
USER RESPONSE:
Make sure the specified setupfile is a preexisting file and that it is specified as a fully
qualified filename.
WARNING (FW-049): [Severe] The specified -setupfile setupfile does not have
read permissions.
EXPLANATION:
The TCL command cannot open for "read" the specified setupfile.
USER RESPONSE:
Change permissions on the file to read access.
ERROR (FW-050): [Input] The specified -methfile mfile is an invalid file.

EXPLANATION:
The TCL command does not recognize the specified methodology file as a valid file type.
USER RESPONSE:
Make sure the specified methodology file is an existing file and that it is specified as a
fully qualified filename.
FW-051 through FW-100

INFO (FW-051): The -methfile option is not fully qualified - defaulting to filename
EXPLANATION:
The TCL command did not detect a fully qualified path for option -methfile. The TCL
command will use the current working directory to find it.
USER RESPONSE:
To override the default using current working directory, -methfile must be specified
with a fully qualified filename.
WARNING (FW-052): [Severe] TNo design model could be found for this project. The file
hierModel does not exist.

EXPLANATION:
The requested operation requires a design model, but the model was not found.
USER RESPONSE:
If you have not yet built the model, build it and then try your view request again. If you
copied this part from elsewhere, check to make sure that the hierModel file was copied.
If the hierModel is a symbolic link, make sure that the link is valid.
WARNING (FW-053): [Severe] The testmode tmode is not registered in global data.
EXPLANATION:
The given TESTMODE for the current design is invalid.
USER RESPONSE:
Utilize the getGdList method to retrieve a valid list of testmodes for the current
WORKDIR.
WARNING (FW-054): [Severe] The experiment experiment is not registered in global

data.
EXPLANATION:
The given EXPERIMENT for the current design is invalid.
USER RESPONSE:
Utilize the getGdList method to retrieve a valid list of experiments for the current
WORKDIR.
WARNING (FW-055): [Severe] The delaymodel delaymodel is not registered in global

data.
EXPLANATION:
The given DELAYMODEL for the current design is invalid.
USER RESPONSE:
Utilize the getGdList method to retrieve a valid list of delaymodels for the current
WORKDIR.
WARNING (FW-056): [Severe] The failset failset is not registered in global data
EXPLANATION:
The given FAILSET for the current design is invalid.

USER RESPONSE:
Utilize the getGdList method to retrieve a valid list of failsets for the current WORKDIR.
WARNING (FW-057): [Severe] The callout callout is not registered in global data.
EXPLANATION:
The given ALTCALLOUT for the current design is invalid.
USER RESPONSE:
Utilize the getGdList method to retrieve a valid list of callouts for the current WORKDIR.
WARNING (FW-058): [Severe] Invalid ALTFAULT: altfault

EXPLANATION:
The value specified as an alternate fault model is not valid for the current project and
entity (WORKDIR).
USER RESPONSE:
Use TFWgdata to determine a valid list of alternate fault models registered in global data
for the current WORKDIR (project and entity).
WARNING (FW-059): [Severe] The alternate fault model altfault is not registered in
global data.
EXPLANATION:
The given value of ALTFAULT keyword for the current design is invalid.
USER RESPONSE:
Utilize the the TFWgdata binary or the Tcl getGdList method to retrieve a valid list of
alternate fault models for the current WORKDIR.
ERROR (FW-060): [Input] Invalid application name appName was specified.

EXPLANATION:
The specified application window failed to be displayed for the given application name.
USER RESPONSE:
Check for valid application name, Otherwise, contact Cadence support. Refer to
Contacting Customer Service on page 23.
INFO (FW-061): The testresults project directory will not be removed.

EXPLANATION:
The Encounter Test data created within the project testresults directory will not be
removed from the project.
USER RESPONSE:
ERROR (FW-062): [Input] Delete aborted - WORKDIR workdir is a back-leveled project.

EXPLANATION:
The specified project (WORKDIR) has globaldata detected in its top level directory
structure. This indicates the project requested for removal is a back-leveled part
directory. No attempt is made to remove any data from this type of project. type of project.
USER RESPONSE:
Automated removal is not available for back-leveled projects.
)ERROR (FW-063): Catch Error: catchError - Delete project failure in projectDir

EXPLANATION:
Failed to remove the directory within the specified project.
USER RESPONSE:
Check permissions or contact Cadence support (see Contacting Customer Service on
page 23).
ERROR (FW-064): [Input] Project workdir preexists, new project request aborted.
EXPLANATION:
Detected a pre-exisitng tbdata directory when requesting the creation of a new project
for the specified project directory.
USER RESPONSE:
Use the delete_project tcl command prior to the new_project command request
on a preexisting part. This will remove any preexisting tbdata and testresults data
in a project directory.
WARNING (FW-065): Warning : catchError- Failed to remove alias link aliasLink.

EXPLANATION:

Failed to remove an alias symbolic link previously established for a project that is deleted.
These links will continue to be displayed in the Encounter Test Open Project window.
USER RESPONSE:
Check permissions or contact customer support (see Contacting Customer Service on
page 23).
ERROR (FW-066): [Input] Fail Set not specified\

EXPLANATION:
A fail set was specified. Fail set was not defined in the current environment.
USER RESPONSE:
See fwTuiCmnd Itcl class setEnv method for setting environment variables into the
environment.
WARNING (FW-067): [Severe] Failed to launch the Physical Design Viewer.

EXPLANATION:
An internal error was detected while attempting to allocate resources for the launching
of the Physical Design Viewer. This error should be accompanied by additional error
messages in the console.
USER RESPONSE:
Contact customer support (see Contacting Customer Service on page 23) and provide
this message and the accompanying console messages.
ERROR (FW-068): [Tool] Failed to close the Physical Design Viewer.

EXPLANATION:
An error was detected while attempting to deallocate the Physical Design Viewer
resources.This error should be accompanied by additional error messages in the
console.
USER RESPONSE:
this message and the accompanying console messages..This error is also indicative of
an extraneous TUIxComm process that is still running. If this is the case, manually kill this
process.
ERROR (FW-069): [Tool] Failed to launch the Physical Design Viewer.

EXPLANATION:
An internal error was detected while attempting to launch the Physical Design Viewer.
This error may be accompanied by additional error messages in the xterm window from
which the Encounter Test GUI was launched.
USER RESPONSE:
Follow the instructions given in the message. If there are no instructions, contact
Cadence Customer Support (see Contacting Customer Service on page 23) with this
message and the accompanying xterm messages.
WARNING (FW-070): Specified global METHODOLOGY orgMeth does not exist.

Defaulting value.
EXPLANATION:
The specified globals METHODOLOGY value from setup file is invalid. The value for it is
overridden with a default value dependent upon product.
USER RESPONSE:
Utilize method update_project to reset the project METHODOLOGY value within the
existing project.
WARNING (FW-071): Failed to load the specified physical design.

EXPLANATION:
The layout specified by Library, Cell, and View in the Project set up could not be loaded
by the Physical Design Viewer.
USER RESPONSE:
Verify/correct the Library, Cell, and View specifications in the Project set up and retry..
WARNING (FW-072): [Severe] Write permission failure.

EXPLANATION:
Write permission access is unavailable for the directory.
USER RESPONSE:
Validate that WORKDIR and subsequent directories have write permissions set.
INFO (FW-074): The Physical Design Viewer could not be launched because the necessary
Test_Mfg_Analysis license is not currently available.
EXPLANATION:

The Physical Design Viewer could not be launched because a Test_Mfg_Analysis

license is not currently available.
USER RESPONSE:
Obtain a license and relaunch the Physical Design Viewer.
WARNING (FW-075): The set environment request for keyword keyword failed. Your
environment may be full.
EXPLANATION:
Your request to set an environment value for the specified keyword failed, probably
because your environment is full.
USER RESPONSE:
Remove unnecessary keywords from your environment, and retry your request.
WARNING (FW-076): Unable to display the Graphical User Interface viewName Window.
EXPLANATION:
The referenced window could not be displayed because it is not valid when the circuit
model is being edited.
USER RESPONSE:
Complete your edits for the circuit model and then retry your view request.
ERROR (FW-077): An unexpected error occurred for opcode opcode. The return code was
return code.
EXPLANATION:
An unexpected error occurred in your Encounter Test graphical analysis. The opcode
that caused the error has been listed.
USER RESPONSE:
Complete your edits for the circuit model and then retry your view request.
INFO (FW-078): Failed to establish a connection with the Physical Design Viewer on
machine machine name|IP address and port port_number. Cross-probing is not
enabled.
EXPLANATION:
Encounter Test was unable to successfully establish communication with the specified
physical design viewer session identified by the referenced machine and port

specification. Consequently, the cross- probing capabilities supported by the Encounter

Test GUI are not enabled for use with the specified physical design viewer.
USER RESPONSE:
Ensure the machine and port specifications correctly identify an existing physical design
viewer process and rerun.
WARNING (FW-079): [Severe] Unable to display the viewName window. The testmode
could not be established.
EXPLANATION:
The viewName window could not be displayed. Following are the possible reasons:
The testmode does not exist.
The testmode data is corrupt.
USER RESPONSE:
Ensure that the specified testmode exists. If not, choose a different testmode. If the
testmode exists, check for messages in the window from which the Encounter Test GUI
was started. Contact Cadence Customer Support (see Contacting Customer Service
on page 23) and report any messages observed.
WARNING (FW-080): [Severe] The requested testmode could not be established. If there
was a previously selected testmode, it is still in effect.
EXPLANATION:
The requested testmode could not be set for analysis. Following are the possible
reasons:
The testmode does not exist.
The testmode data is corrupt.
If a testmode was previously selected, it will continue to be in effect. If there was no
previously selected testmode, there is none in effect now. The current testmode can be
determined by examining the Analysis Context window.
USER RESPONSE:
Ensure that the specified testmode exists. If not, choose a different testmode. If the
testmode exists, check for messages in the window from which the Encounter Test GUI
was started. Contact Cadence Customer Support (see Contacting Customer Service
on page 23) and report any messages observed.

WARNING (FW-081): [Severe] Unable to display the viewName window. The testmode
could not be established because the testmode data was created before 2004. This mode
must be rebuilt using build_testmode.
EXPLANATION:
The viewName window could not be displayed. The specified testmode was created
before 2004 and cannot be automatically migrated to conform to the current testmode
data format.
USER RESPONSE:
Use the build_testmode command to rebuild the testmode.
WARNING (FW-082): [Severe] The requested testmode could not be established because
the testmode data was created before 2004. This mode must be rebuilt using
build_testmode. If there was a previously selected testmode, it is still in effect.
EXPLANATION:
The requested testmode could not be set for analysis. The specified testmode was
created before 2004 and cannot be automatically migrated to conform to the current
testmode data format.
If a testmode was previously selected, it will continue to be in effect. If there was no
previously selected testmode, there is none in effect now. The current testmode can be
determined by examining the Analysis Context window.
USER RESPONSE:
Use the build_testmode command to rebuild the testmode.


7
TBD - Generate Test Pattern Data
Messages
TBD-001 through TBD-050 on page 97

TBD-001 through TBD-050

ERROR (TBD-001): [Input] Failure to read file header from input test vectors file. File
name: fileName is not complete and must be rebuilt. The log file for the Encounter Test
command which created the test vectors file should be inspected for errors. Correct any
problems found before recreating the test vectors file.
EXPLANATION:
The input test vectors file or sequence file is incomplete and cannot be processed.
USER RESPONSE:
Ensure that the application creating the input test vectors or sequence file successfully
completed. Review the log file for the Encounter Test command that created the input test
vectors file. Correct any errors found before attempting to recreate inputs and then rerun.
ERROR (TBD-002): [Input] Filename: fileName was created using a newer version of
Encounter Test software than the one you are currently running. You must either return to the
version of Encounter Test software which was used to create the input file or recreate the
input file in your current version of Encounter Test software.
EXPLANATION:
The input file was created using a newer version of the Encounter Test than you are
currently running.

TBD - Generate Test Pattern Data Messages
USER RESPONSE:
Use the Encounter Test software that was used to create the input file or recreate the
input in your current version of Encounter Test software.
ERROR (TBD-003): [Input] Open binary pattern file : error - no name returned from
TFWgetExperFilename. Circuit qualifiers were incorrectly specified.
EXPLANATION:
Design qualifiers were incorrectly specified.
USER RESPONSE:
Ensure the working directory is correctly specified and then rerun.
ERROR (TBD-004): [Input] Could not open Filename: fileName. Ensure that the working
directory was correctly specified and that you have the necessary file permissions.
EXPLANATION:
The application failed while attempting to open the output test vectors file.
USER RESPONSE:
Ensure the working directory is correctly specified and that you have write authority to
your working directory and then rerun.
ERROR (TBD-005): [Tool] Space allocation failed. program cannot allocate space for
table. Rerun when more space is available.
EXPLANATION:
Sufficient space was not available to run the requested application.
USER RESPONSE:
Rerun when more space is available.
ERROR (TBD-006): [Internal] Invalid node (pinName) in pulse data. Non-clockindex

found in pulse event. Contact Cadence Test Customer Support for assistance.
EXPLANATION:
A non-clock index was found in a pulse command. This is a program error.
USER RESPONSE:
Contact customer support (see Contacting Customer Service on page 23) for
assistance.

ERROR (TBD-007): [Internal] Write test vector error - TLMgetContext returned NULL.
Contact Cadence Customer Support for assistance..
EXPLANATION:
The program cannot establish model context. This is a program error.
USER RESPONSE:
assistance.
ERROR (TBD-008): [Input] Write test vector error - rc = NNN received from
TLMloadModel. Ensure that the working directory is correctly specified.
EXPLANATION:
The flatModel cannot be loaded.
USER RESPONSE:
Rerun after ensuring that WORKDIR is correctly specified. If this fails to correct the
problem, contact customer support (see Contacting Customer Service on page 23) for
assistance.
ERROR (TBD-009): [Tool] Failed attempting to write filename: fileName. Insufficient

space was available to create the requested pattern file. Ensure that enough space is
available in your working directory before restarting your job.
EXPLANATION:
Insufficient space was available to create the requested output file.
USER RESPONSE:
Ensure that sufficient space exists and rerun. If this fails to correct the problem, contact
customer support (see Contacting Customer Service on page 23) for assistance.
ERROR (TBD-010): [Tool] TBDallocateWorkArea: error - malloc returned NULL; size

= NNN.
EXPLANATION:
Space allocation failed.
USER RESPONSE:
Ensure that sufficient space exists and rerun the job. If this fails to correct the problem,
contact customer support (see Contacting Customer Service on page 23) for
assistance.

ERROR (TBD-011): [Input] TBDopenPatternFile: error - no name returned from

TFWgetExperFileName or TFWgetModalFileName. Ensure that your working directory is
correctly specified.
EXPLANATION:
Program parameters were incorectly specified,
USER RESPONSE:
Rerun after ensuring the working directory is correctly specified.
ERROR (TBD-012): [Input] TBDopenPatternFile: error opening pattern output file:

fileName. Ensure that your working directory is correctly specified.
EXPLANATION:
Program parameters were incorectly specified,
USER RESPONSE:
Rerun after ensuring the working directory is correctly specified.
ERROR (TBD-015): [Tool] TBDwriteBinaryFile failed to write test vectors to the output
vectors file. Refer to previous error messages. Contact Cadence Customer Support for
assistance If previous messages do not help resolve the problem.
EXPLANATION:
The program failed while trying to write the output test vectors file. The log contains
previous messages that may assist in resolving the problem.
USER RESPONSE:
Refer to previous messages. Contact customer support (see Contacting Customer
Service on page 23) if previous messages do not help to resolve the problem
ERROR (TBD-016): [Tool] TBDwriteBinaryTestProcedure error writing out a test

procedure to the test vectors file. Refer to previous error messages. Contact Cadence
Customer Support for assistance If previous messages do not help resolve the problem.
EXPLANATION:
The program failed while trying to write a test procedure to the test vectors file. The log
contains previous messages that may assist in resolving the problem.
USER RESPONSE:
Refer to previous messages. Contact customer support (see Contacting Customer
Service on page 23) if previous messages do not help to resolve the problem

ERROR (TBD-017): [Input] TBDopenBinaryFile: error - unable to open test vectors file.
Ensure the working directory is correctly specified and rerun.
EXPLANATION:
The program filed while trying to open the test vectors file.
USER RESPONSE:
Rerun after ensuring the working direcotory is correctly specified. Contact customer
support (see Contacting Customer Service on page 23) if the failure still occurs.
ERROR (TBD-018): [Input] Error printing ASCII pattern file. Ensure the working directory
is correctly specified and rerun.
EXPLANATION:
The program failed while trying to print a test vectors file or sequence file.
USER RESPONSE:
Rerun after ensuring the working directory is correctly specified. that WORKDIR,
TESTMODE and EXPERIMENT are specified correctly. Contact customer support (see
Contacting Customer Service on page 23) if the failure still occurs.
ERROR (TBD-019): Error opening input Filename fileName. Ensure that the file exists
and that you have the necessary file permissions.
EXPLANATION:
Failure while trying to open the specified input file.
USER RESPONSE:
Ensure that the input file exists. Recreate the file if it has been deleted. Ensure that
necessary file permisions exist before restarting the job. Refer to log that created the
input file. Correct any errors which may have caused the file not to be created.
Rerun after ensuring all identified problems have been corrected. If the failure persists,
ERROR (TBD-020): [Input] Design data within the Filename: fileName does not match
this design.
EXPLANATION:
Test vectors in the specified file were created on a different design. The number of input
pins, output pins, scan latches, and scan registers do not match this design.
USER RESPONSE:

Recreate test vectors for the current design and rerun.
ERROR (TBD-021): [Input] Error in the Vector Correspondence file. Correct the error and
rerun.
EXPLANATION:
The program detected an error in the vector correspondence file.
USER RESPONSE:
Correct problems in the vector correspondence file and then rerun the job. Refer to
TBDpatt and TBDseqPatt Format in the Encounter Test: Reference: Test Pattern
Formats for vector correspondence file information.
ERROR (TBD-022): Error detected attempting to update the faultModel. Correct the
faultModel problems before rerunning commit_tests.
EXPLANATION:
The commit_tests command is unable to update the faultModel with the test results
for this experiment due to errors in the faultModel.
USER RESPONSE:
Refer to previous faultModel messages. Rerun after correcting faultModel problems. If
problems persist, contact customer support (see Contacting Customer Service on
page 23).
ERROR (TBD-022): Error detected attempting to update the master faultStatus file. The
TFM function failed. Review prior TFM messages to identify and correct any problems before
rerunning commit_tests. It maybe necessary to review the logfile of the process which
created this experiment to determine what caused the problem.
EXPLANATION:
commit_tests is unable to update the faultModel with the test results for this
experiment because of faultModel errors. To prevent corrupting the master test vectors
file commit_tests terminates.
USER RESPONSE:
Refer to previous TFM messages in the commit_tests logfile. Failure maybe the result
of problems in the test generation/simulation run that created this experiment and it
maybe helpful to review that logfile. After correcting any faultModel problems, rerun your
commit_tests job. If problems persist, contact customer support (see Contacting
Customer Service on page 23) for assistance.

ERROR (TBD-023): Error - failure attempting to lock objectName object. Object is not
registered on the globalData file or wrong input parameters specified.
EXPLANATION:
Object indicated in the messages is not registered on the globalData file. Wrong input
parameters could have been specified.
USER RESPONSE:
Refer to previous messages. Rerun after correcting any problems. If problems persist,
assistance.
WARNING (TBD-024): [Severe] commit_tests failed while trying to register the master
Committed tests file on the globalData file.
EXPLANATION:
After creating or updating the master Committed tests file, commit_tests was unable
to register the master Committed tests file on the globalData file.
USER RESPONSE:
Applications which use our system expect this file to be registered and will fail when
asked to run on this data. The only path which will get this data back into our system will
require:
1.Perform report_vectors on the Committed Tests.
2.Perform read_vectors on the TBDpatt file.
3.Resimulate the Uncommitted tests you created.
4.Rerun commit_tests to create a new Committed tests file.
WARNING (TBD-025): [Severe] commit_tests failed while trying to register the

committed tests file dependencies on the globalData file.
EXPLANATION:
The program failed while trying to register the committed tests file dependent on the
testmode.
USER RESPONSE:
If you rebuild the testmode, the committed tests file will not be automatically deleted.
Delete the file manually.

WARNING (TBD-026): [Severe] commit_tests failed while trying to remove the

uncommitted test file and dependencies from the globalData file.
EXPLANATION:
As a normal part of processing commit_tests deletes and unregisters uncommitted
files and dependencies.
USER RESPONSE:
If this happens you may have experimental files still in existence at the end of your job.
These files must be manually deleted.
WARNING (TBD-027): [Severe] commit_tests failed while removing the experiment

object from the globalData file.
EXPLANATION:
commit_tests failed while trying to unregister the experiment from the globalData file.
USER RESPONSE:
The experiment name is still registered on the globalData file. If you create additional
experiments, use different experiment names to ensure there is no conflict.
ERROR (TBD-028): [Input] Error - rc = NNN received from TLMsetMode. for test mode
modename. Ensure the specified testmode exists.
EXPLANATION:
The program failed while trying to load the Encounter Test test mode.
USER RESPONSE:
Rerun after ensuring the test mode is correctly specified. If the test mode is correctly
specified, ensure that previous steps which created the test mode successfully
completed. If the application is still failing after ensuring that the test mode is correct,
assistance.
ERROR (TBD-029): [Input] Missing argument: specify parameter. Rerun after adding
the missing argument.
EXPLANATION:
The identified program parameter was missing.
USER RESPONSE:

Rerun report_vectors specifying the missing parameter. Specify, report_vectors

-h for a complete list of all report_vectors options.
Refer to "report_vectors" in the Encounter Test: Reference: Commands for additional
information.
ERROR (TBD-030): [Internal] TBDskew error: Non-existent event type. Line: offset.
Contact customer support for assistance.
EXPLANATION:
A program error has occurred.
USER RESPONSE:
assistance.
ERROR (TBD-031): [Internal] TBDskew error: NULL TestSequenceID. Line: offset.

EXPLANATION:
USER RESPONSE:
assistance.
ERROR (TBD-032): [Internal] TBDskew error: NULL TestPatternID. Line: offset.

EXPLANATION:
USER RESPONSE:
assistance.
ERROR (TBD-033): [Internal] TBDskew error: program failed setting the pattern type. Line:
offset. Contact customer support for assistance.
EXPLANATION:
USER RESPONSE:

assistance.
ERROR (TBD-034): [Internal] TBDskew error: NULL EventID. Line: offset. Contact
customer support for assistance.
EXPLANATION:
USER RESPONSE:
assistance.
ERROR (TBD-035): [Internal] TBDskew error: program failed setting the event type. Line:
EXPLANATION:
USER RESPONSE:
assistance.
ERROR (TBD-036): [Internal] TBDskew error: program failed setting the timed type. Line:
EXPLANATION:
USER RESPONSE:
assistance.
ERROR (TBD-037): [Internal] TBDskew error: program failed adding stim data. Line:
EXPLANATION:
USER RESPONSE:
assistance.

ERROR (TBD-038): [Internal] TBDskew error: program failed adding pattern data. Line:
EXPLANATION:
USER RESPONSE:
assistance.
ERROR (TBD-039): [Internal] TBDskew error: program failed adding measure data. Line:
EXPLANATION:
USER RESPONSE:
assistance.
ERROR (TBD-040): [Internal] TBDskew error: program failed adding pulse data. Line:
EXPLANATION:
USER RESPONSE:
assistance.
ERROR(TBD-041): [Internal] TBDskew error: nsl pattern failed. Line: offset. Contact
customer support for assistance.
EXPLANATION:
USER RESPONSE:
assistance.
ERROR (TBD-042): [Internal] TBDskew error: nsl pattern type failed. Line offset.

EXPLANATION:
USER RESPONSE:
assistance.
ERROR (TBD-043): [Internal] TBDskew error: non-RSL or RML found in StimLatch event.
Line: offset. Contact customer support for assistance.
EXPLANATION:
USER RESPONSE:
assistance.
ERROR (TBD-044): TBDwriteBinaryFile failed while trying to put the experimental

PattAuditStats to the globalData file. Refer to previous error messages and correct
any problems before rerunning.
EXPLANATION:
The experimental PattAuditStats were not written to the globalData file. The test
vectors file was not written.
USER RESPONSE:
Refer to previous messages. Rerun after correcting problems. If problems persist,
assistance.
ERROR (TBD-045): TBDwriteBinaryFile failed while trying to get the experimental

PattAuditStats from the globalData file. Refer to previous error messages and correct
any problems before rerunning.
EXPLANATION:
The experimental PattAuditStats were not found on the globalData file. Test data
counts for the experiment could not be updated.
USER RESPONSE:

Refer to previous messages. Rerun after correcting any problems. If problems persist,
assistance.
ERROR (TBD-046): [Internal] commit_tests failed while trying to get the master
PattAuditStats from the globalData file. Contact Cadence Customer Support for
assistance.
EXPLANATION:
The master PattAuditStats were not found on the globalData file. This is a
program error.
USER RESPONSE:
assistance.
ERROR (TBD-047): [Internal] commit_tests failed while trying to get the experimental
PattAuditStats from the globalData file. Contact Cadence Customer Support for
assistance.
EXPLANATION:
The experimental PattAuditStats were not found on the globalData file. This is a
program error.
USER RESPONSE:
assistance.
ERROR (TBD-048): [Internal] commit_tests failed while trying to commit the

experimental PattAuditStats to the committed PattAuditStats. Contact Cadence
Customer Support for assistance.
EXPLANATION:
Update of the master PattAuditStats failed. This is a program error.
USER RESPONSE:
assistance.
ERROR (TBD-049): [Input] Audits indicate that the test vectors contained within this
uncommitted tests file may be suspect. If you wish to commit these uncommitted tests to the
committed tests file, you must do an unconditional commit.

EXPLANATION:
Potential problems exist in the test vectors.
USER RESPONSE:
Review previous messages for a list of potential problems. After reviewing the list of
potential problems with the test vectors, if you still wish to commit these vectors to the
committed tests file, perform an unconditional commit. Using the unconditional commit
performs the normal commit_tests checking and forces the uncommitted tests to be
committed.
ERROR (TBD-050): [Tool] Error expanding the test vectors file. Refer to previous error
messages for problem details.
EXPLANATION:
An error occurred while trying to expand the file.
USER RESPONSE:
Refer to previous error messages, resolve the identified errors and then rerun. If no
errors are reported, contact customer support (see Contacting Customer Service on
page 23) for assistance.

ERROR (TBD-051): [Input] When expanding test vectors, INEXPERIMENT must be
different then EXPERIMENT.
EXPLANATION:
The INEXPERIMENT and EXPERIMENT have the same name. They must be different.
USER RESPONSE:
Change the EXPERIMENT name to a unique identifier.
ERROR (TBD-052): [Tool] Unable to obtain a read lock on the objectName object.
EXPLANATION:
The object indicated in the messages is not currently available. Object may not be
registered. Input parameters may be specified incorrectly.
USER RESPONSE:
Rerun job after object has been freed.

WARNING (TBD-053): [Severe] Unable to register the expanded uncommitted tests file on
the globalData file. Check file permissions.
EXPLANATION:
The program was unable to register the expanded uncommitted tests file.
USER RESPONSE:
If this file is to be used as input to an application requiring the file to be registered, then
do the following:
Check the globalData file and correct any problems which might prevent
writing to it (for example, file permissions).
Rerun report_vectors to recreate the expanded uncommitted tests and
register it.
WARNING (TBD-054): [Severe] Unable to register the uncommitted tests file

dependencies on the globalData file.
EXPLANATION:
Processing failed while trying to register the uncommitted tests file dependent on the
testmode. However, the expanded uncommitted tests file itself is accurate.
USER RESPONSE:
If you rebuild the test mode, the uncommitted tests file will not be automatically deleted.
It must be manually deleted.
ERROR (TBD-055): [Tool] Unable to obtain a write lock on the objectName object.
EXPLANATION:
The program was unable to write lock the referenced object. The object may be
unavailable or not registered on globalData. Input parameters may be specified
incorrectly.
USER RESPONSE:
Correct any errors and rerun the program and see if the problem still exists. If the problem
presists, call customer support (see Contacting Customer Service on page 23) for
assistance.
ERROR (TBD-056): Error while trying to expand file workdir/TBDpatt.

testMode.inexperiment. Refer to previous messages to determine the problem.
Contact Cadence Customer Support for assistance if unable to correct the problem.

EXPLANATION:
An error occurred. Previous error messages describe the error condition.
USER RESPONSE:
Refer to the previous error messages for more information. Contact customer support
(see Contacting Customer Service on page 23) if you cannot resolve the problems.
ERROR (TBD-057): The number scan cycles in the scanfill sequence is greater then the
scanfill length. Either the scanfill length or the scanfill Sequence_Definition is incorrect.
The number of scan cycles in the scanfill sequence must match the scanfill length.
Processing terminates.
EXPLANATION:
The number of scan cycles found within the scanfill sequence must match the scanfill
length.
USER RESPONSE:
Correct either the scanfill length or the scanfill sequence then rebuild your testmode.
After rebuilding your testmode rerun the your job.
ERROR (TBD-058): Unable to allocate NNN bytes. Ensure that sufficent space is available
and rerun
EXPLANATION:
Space allocation failed.
USER RESPONSE:
Ensure that sufficient space exists and rerun the job.
ERROR (TBD-059): [Internal] Test Vector files containing eventName events cannot be
expanded by the function routine.
EEXPLANATION:
The referenced event type is not currently supported for expansion. This was either due
to a program error, or the input file was created with a previous release of Encounter Test
(earlier than Version 1 Release 2).
USER RESPONSE:
If the input file was created with a previous release of Encounter Test (earlier than
Version 1 Release 2), recreate your test data using this Encounter Test release and

rerun. Otherwise, call customer support (see Contacting Customer Service on

ERROR (TBD-060): [Internal] commit_tests failed while trying to commit the

experimental MacroAuditStats to the master MasterAuditStats. Contact Cadence
EXPLANATION:
Update of the Master MacroAuditStats failed. This is a program error.
USER RESPONSE:
assistance.
ERROR (TBD-067): [Input] Filename: fileName is not complete and must be rebuilt. The
log file for the Encounter Test command which created the input test vectors file should be
inspected for errors. Correct any problems found before recreating the test vectors file.
EXPLANATION:
The input test vectors file or sequencefile is incomplete and cannot be processed.
USER RESPONSE:
Ensure that the application creating the input test vectors or sequence file successfully
completed. Review the log file for the command that created the input test vectors file.
Correct any detected errors before attempting to recreate the input file.
ERROR (TBD-068): Error writing to Filename: filename. Write to file offset offset
failed. Before restarting your process ensure that enough space is available in your working
directory.
EXPLANATION:
Encounter Test failed while attempting to write the referenced output file.
USER RESPONSE:
Ensure that enough space is available and then rerun.
ERROR (TBD-069): [Input] commit_tests was unable to commit test data. Failed
attempting to open file fileName. The input file is bad. Refer to previous messages, correct
problems, and rerun.
EXPLANATION:
commit_tests failed when asked to open the specified input file. The input file is bad.

USER RESPONSE:
Refer to previous messages. Rerun your job(s) after correcting any problems. If problems
persist, contact customer support (see Contacting Customer Service on page 23) for
assistance.
ERROR (TBD-070): These test vectors can not be migrated. Compression test vectors are
only migrated if the testmode was built using boundary=migrate. Processing terminates.
EXPLANATION:
The testmode was not build specifing boundary=migrate. Test vectors an not be
migrated.
USER RESPONSE:
If migration is required you must rebuild your testmode specifying boundary=migrate.
Recreate your test vectors and then rerun prepare_macro_migration_tests.
ERROR (TBD-073): Unable to process Filename: fileName using restart=yes because

the file checkpoint could not be found. Restart your process specifying restart=end.
EXPLANATION:
The requested checkpoint could not be found in the test vectors file. Processing can not
continue using restart=yes.
USER RESPONSE:
The application that created the test vectors file did not successfully complete and
checkpoint information is incomplete. The program cannot add to the input test vectors
file. Rerun using restart=end. Review the log file for the Encounter Test command that
created the input test vectors file. Correct any errors found before attempting to generate
additional test vector files.
ERROR (TBD-074): Invalid attempt to open checkpointed file fileName with write access
ignored. Checkpointed test vectors file can only be exported to TBDpatt file or used to
continue a test generation run.
EXPLANATION:
An application attempted to update the checkpointed vectors file. A checkpointed test
vectors file has limited use: it cannot be committed or used other than for printing, except
to continue the checkpointed run.
USER RESPONSE:

Rerun test generation with this experiment to complete the checkpointed test vectors file,
then rerun.
WARNING (TBD-075): [Severe] Vector file checkpoint failed. Refer to previous messages
to determine the problem.
EXPLANATION:
Checkpoint of test vectors file failed.
USER RESPONSE:
Review previous messages to determine and resolve the problem and then rerun.
ERROR (TBD-076): TBDcloseBinaryFile: failure to close test vectors file: fileName.

Refer to previous messages to determine the problem.
EXPLANATION:
The test vector file failed to close.
USER RESPONSE:
Look for system messages such as "afs out of space". Rerun job after correcting
any problems.
WARNING (TBD-077): [Severe] Modeinit sequence definition not found in the sequence
file. The test vectors will not contain an initialization test sequence and the testmode was
improperly created..
EXPLANATION:
The mode initialization sequence definition is required, but was not found in the
sequence file. This sequence should be added to your sequence definition file by
build_testmode.
USER RESPONSE:
Rebuild your test mode, or replace your sequence file with a back-up copy.
ERROR (TBD-078): [Internal] Error - rc = NNN received from TLMloadMethods for

testMode modeName. Could not continue processing test mode modeName because it
could not be loaded.
EXPLANATION:
The program failed while trying to load the flatModel methods for the specified test mode.
USER RESPONSE:

Ensure that the test mode exists. If you are importing test vectors or sequence
definitions, any test modes specified in Begin_Test_Mode events, Going_To_Mode or
In_Test_Mode objects must exist. If the test mode is not required, remove the
reference from the input and rerun. If the test mode does not exist and is required, the
test mode must be built the test mode before you can continue processing.
Rerun your process after ensuring that the test modes are correct. If the failure still
occurs, customer support (see Contacting Customer Service on page 23) for
assistance.
ERROR (TBD-079): [Input] Audits indicate that TSV default tests have not been run. If you
wish to commit this experiment to the committed tests, you must do an unconditional commit.
EXPLANATION:
Audits indicate that one or more of the default TSV tests for the mode have not been run.
USER RESPONSE:
If you wish to commit this test data to the Committed tests file you must force the commit.
ERROR (TBD-080): [Tool] convert_vectors_for_core_tests does not support

accessing data from a parent testmode. Only test vectors created on the parent testmode can
be migrated.
EXPLANATION:
While processing the input test vectors, a BeginTestMode event was encountered in
the test vectors. Encounter Test does not currently support creating Structure Neutral
test vectors for parent/child testmodes.
USER RESPONSE:
If you wish to migrate test vectors, the test vectors must be created on a parent testmode.
ERROR (TBD-081): [Tool] commit_tests does not support committing checkpointed

vectors. Your experiment which created this tes vectors file did not successfully complete. You
should be either restart that application and continue, or restart and save the test vectors that
were created up to that point.
EXPLANATION:
The Ucommitted tests to be committed is a checkpointed file. The process which created
this file must be run to completion before the uncommitted tests can be committed to the
committed vectors File.
USER RESPONSE:

Rerun the process which created this experiment to completion and then rerun
commit_tests.
ERROR (TBD-082): [Input] Test Vector expansion failed while trying access data from the
scanop sequence.
EXPLANATION:
While trying to expand data for a Scan_Load or Scan_Unload command, a NULL
pointer was returned when trying to access the scanop sequence. Without this data,
latch commands cannot be expanded.
USER RESPONSE:
Ensure that there are no problems with the sequence file for the testmode you are
processing. If the data being expanded includes LoadSR and UnLoadSR events ensure
that the required scan information is present on the experiment that we are expanding.
If there are no problems with the sequence file or the sequences on the experiment,
assistance.
INFO (TBD-083): Sequence_Definition sequenceName was not found in the TBDseq

file. The Sequence_Definition will not be added the the application object collection of
Experiment experiment. Import the Sequence_Definition and then rerun.
EXPLANATION:
The Sequence_Definition was not found in the TBDseq file. As a result it could not
be added to the experiments application object collection.
USER RESPONSE:
Import the Sequence_Definition and then rerun.
ERROR (TBD-084): [Tool] The program failed. Refer to previous error messages. If there
are none, contact Cadence Customer Support for assistance.
EXPLANATION:
A program error occurred while either processing the input file or writing the output file.
There should be additional error messages to give more details about the problem.
USER RESPONSE:
Resolve the conditions identified in previous error messages. if no messages are
produced, contact customer support (see Contacting Customer Service on page 23)
for assistance.

ERROR (TBD-085): [Input] Program error: INEXPERIMENT must be different from

EXPERIMENT.
EXPLANATION:
The INEXPERIMENT name and the EXPERIMENT name are the same name. The input
file name cannot be the same as the output file name.
USER RESPONSE:
Change the EXPERIMENT name to a unique identifier.
ERROR (TBD-086): [Input] Missing argument: specify parameter. Specify the missing
argument and rerun.
EXPLANATION:
The referenced program parameter was missing.
USER RESPONSE:
Specify the missing parameter and rerun.
ERROR (TBD-087): Unable to initialize test vectors. See preceding messages. Ensure that
directory permissions are correctly set.
EXPLANATION:
The program was unable to initialize resources.
USER RESPONSE:
Refer to the preceding messages to evaluate the problem. Ensure directory permissions
are correct. Rerun after resolving the problem(s).
ERROR (TBD-088): Unable to open test vectors file. Ensure that the correct working
directory was specified.
EXPLANATION:
The program failed while trying to open the test vectors file.
USER RESPONSE:
Ensure that the correct working directory was specified and that the test vectors file
exists. Use preceding messages to evaluate and resolve the problem. Rerun after
correcting problems.
ERROR (TBD-089): [Input] The program (TBDmigrate) does not support migration from
a checkpointed TBDbin file. Your experiment which created this TBDbin file did not

successfully complete. Either restart the application and continue, or restart and save the
data that was created up to that point.
EXPLANATION:
The experimental TBDbin is a checkpointed file. The process which created this file must
be run to completion before TBDmigrate can be created from the TBDbin File.
USER RESPONSE:
Rerun the process which created this experiment to completion and then rerun
TBDmigrate.
WARNING (TBD-090): [Severe] TBDmigrate: unable to register the output TBDbin file on
the globalData file. Refer to previous messages for help in correcting the problem.
EXPLANATION:
The program was unable to register the TBDbin file.
USER RESPONSE:
Correct problems identified in previous messages and rerun.
WARNING (TBD-091): [Severe] TBDmigrate: Unable to register the TBDbin file

dependencies on the globalData file. Refer to previous messages for help in correcting the
problem.
EXPLANATION:
Processing failed while trying to register the TBDbin file dependent on the testmode.
However, the TBDbin file itself is accurate.
USER RESPONSE:
If you rebuild the test mode, the output TBDbin file will not be automatically deleted. It
must be manually deleted.
ERROR (TBD-092): [Input] TBDmigrate: Unable to obtain a write lock on the

objectName object. Ensure that the object exists and is registered on globalData.
EXPLANATION:
The program was unable to do a write lock. The referenced object may not be registered
on globalData Input parameters may be incorrectly specified.
USER RESPONSE:

Correct any errors and rerun the program and see if the problem still exists. If the problem
presists, contact customer support (see Contacting Customer Service on page 23) for
assistance.
ERROR (TBD-093): [Input] Encountered an experiment which contains structure neutral

test vectors. This test vectors file cannot not processed.
EXPLANATION:
The experiment contains Load and unLoad commands rather then Scan_Load and
Scan_Unload commands. The TBDmigrate code does not support these commands.
USER RESPONSE:
Only attempt to migrate test vectors files which are not in the structure neutral format.
ERROR (TBD-094): commit_tests: the space required to update the committed tests file
with the experimental uncommitted tests is not available. NNN mbytes are required and only
NNN mbytes are available. Rerun when the required space is available.
EXPLANATION:
The space required to update the committed tests file is not available.
USER RESPONSE:
Rerun commit_tests after ensuring the required space is available.
ERROR (TBD-095): Vectors file: fileName has a file format level which is greater than the
file format level of the Committed tests file. This experiment cannot added to the Committed
tests file. The test vectors must be recreated using the Encounter Test release used to create
the test_vectors contained within the Committed tests file.
EXPLANATION:
The Uncommitted vectors were created using a newer release of Encounter Test than
was used to create and commit the tests stored on the Committed tests File.
USER RESPONSE:
Either recreate the test vectors using the earlier release or rebuild your testmode and
recreate all your test vectors for the test mode.
ERROR (TBD-096): [Input] Vectors file: fileName was created prior to Encounter Test
support for large file (64 bit) support. You cannot restart your experiment using this level of
Encounter Test.
EXPLANATION:

The experiment was created using a Encounter Test level which wrote the test vectors
using 32 bit file offsets. Encounter Test does not support test vectors file containing with
both 32 and 64 bit offsets.
USER RESPONSE:
Restart your experiment using the earlier version of Encounter Test.
ERROR (TBD-097): [Input] Filename: fileName indicates that it was produced with a
later version of Encounter Test software. This file cannot be processed using this version of
Encounter Test.
EXPLANATION:
The format level for the test vectors file being processed is a newer level then what is
supported by the version of Encounter Test being run.
USER RESPONSE:
Either use the newer version of Encounter Test to continue processing or recreate the
input test vectors file using the this version of the Encounter Test software.
WARNING (TBD-098): [Severe] TBDmigrate found a clock that was not at its OFF value
before scan. This is a probable error in test generation. Contact Cadence Customer Support
for assistance.
EXPLANATION:
One or more clocks were not at their OFF value prior to doing a scan. This should not
occur and is a probable error in test generation.
USER RESPONSE:
assistance.
ERROR (TBD-099): [Input] Error detected attempting to update the objective model.
EXPLANATION:
commit_tests is unable to update the Encounter Test objective model with the test
results for this experiment.
USER RESPONSE:
Refer to previous objective model messages. Rerun after correcting any faultModel
problems. Contact customer support (see Contacting Customer Service on page 23) if
problems persist.

WARNING (TBD-100): Override of TI fixed value latch netName by the Scan_Unload

event in the seed file is not allowed. Override will not be honored, run continues.
EXPLANATION:
The seed file specified an override of the referenced TI value latch. This override could
cause problems in the test vectors and will not be honored.
USER RESPONSE:
Overrides of TI fixed value latches are not allowed. No action is required.

WARNING (TBD-101): [Severe] report_vector_volume failed. Refer to previous
program messages.
EXPLANATION:
report_vector_volume failed while trying to process the input test vectors file.
USER RESPONSE:
Review previous messages and correct the identified failure(s), and then rerun. If the
failure persists, contact customer support (see Contacting Customer Service on
page 23).
ERROR (TBD-102): [Tool] Error occurred writing to Filename: fileName. Write of

length bytes to the output file failed. Ensure enough space is available before rerunning.
EXPLANATION:
An attempt to write data to the output file failed.
USER RESPONSE:
Ensure that enough space is available and then rerun.
ERROR (TBD-103): [Input] Read failure for Filename: fileName. File read from offset +
offset failed. The log file for the Encounter Test command which created the test vectors
file should be inspected for errors. Correct any problems found before recreating the input file.
IEXPLANATION:
The application is attempting to read using a bad file offset. The input cannot be
processed.
USER RESPONSE:

Check the log for the job that created the input file for an indication of where the
problem(s) with the input file occured. Fix any problems, recreate the input file and then
rerun.
ERROR (TBD-104): Error reading from Filename: fileName. This may indicate that the
file name is wrong or that the file has been deleted, moved, or corrupted.
EXPLANATION:
An error occurred while reading the test vector file.
USER RESPONSE:
Ensure that the correct workdir and experiment were specified. Check previous job
logs for an indication of whether or not there were problem(s) when the test vectors
where created. Fix any problems and rerun.
ERROR (TBD-105): [Input] TBDopenConvertLatch failed attempting to process the

misrobserve sequence. Either the misrobserve sequence does not exist or no
Measure_MISR_Data event was found within the misrobserve sequence.
EXPLANATION:
Either the misrobserve sequence did not exist or no Measure_MISR_Data event was
found within the misrobserve sequence.
USER RESPONSE:
Ensure that a misrobserve sequence exists for the mode and that it contains a
Measure_MISR_Data event. Correct any problems then rerun.
ERROR (TBD-106): [Input] Vectors file filename is not registered on globalData file.
Ensure that the working directory and other parameters are correctly specified.
EXPLANATION:
The application failed while checking test vectors file registration. The referenced test
vectors file was not registered on the globalData file.
USER RESPONSE:
Rerun job after ensuring that WORKDIR, TESTMODE, and EXPERIMENT are correctly
specified.
ERROR (TBD-107): [Internal] A testmode number of zero was returned by

TLMmodeNumber(). Contact Cadence Customer Support for assistance.
EXPLANATION:

Zero is an invalid mode number, the utility is unable to continue processing. A NULL
pointer is returned to the calling function.
USER RESPONSE:
ERROR (TBD-108): [Input] commit_tests requires that the test vectors be manipulated
before they can be committed to the committed tests file. Run
insert_vector_pipeline_sequence and then rerun commit_tests.
EXPLANATION:
The experimental pattern audit statistics indicate that the test vectors must be
manipulated before they can be applied at the tester.
USER RESPONSE:
Run the insert_vector_pipeline_sequence program to manipulate the
experimental test vectors. After manipulating the test vectors, rerun commit_tests.
Refer to "insert_vector_pipeline_sequence" in the Encounter Test: Reference:
Commands.
ERROR (TBD-109): [Input] Vectors must be manipulated before they can be expanded.
Run insert_vector_pipeline_sequence and then rerun report_vectors.
EXPLANATION:
the test vectors must be manipulated before vector expansion can be run for this
experiment.
USER RESPONSE:
Run the insert_vector_pipeline_sequence program and then rerun
report_vectors . Refer to "insert_vector_pipeline_sequence" in the Encounter
Test: Reference: Commands.
ERROR (TBD-110): [Input] Test vectors must be manipulated before structure neutral test
vectors can be created. Run insert_vector_pipeline_sequence and then rerun
onvert_vectors_for_core_tests.
EXPLANATION:
The test vectors must be manipulated before convert_vectors_for_core_tests
can be run for this experiment.
USER RESPONSE:

Run the insert_vector_pipeline_sequence program and then rerun

onvert_vectors_for_core_tests. Refer to "insert_vector_pipeline_sequence" in
the Encounter Test: Reference: Commands.
WARNING (TBD-111): [Severe] commit_tests failed while trying to register the

committed experiment name dependency on the globalData file. Processing continues.
EXPLANATION:
The program failed to register the committed experiment name dependent on the
testmode.
USER RESPONSE:
If you rebuild the testmode, the committed experiment name will not be automatically
deleted. After rebuilding the testmode you will still be prevented from using this
experiment name unless the experiment is manually deleted.
ERROR (TBD-112): [Tool] Error occured closing Filename: fileName. Sufficient space
to complete writing the output file is not available. Ensure that enough space is available in
your working directory and rerun.
EXPLANATION:
The program was unable to sucessfully close the output file.
USER RESPONSE:
Ensure you are not running out of space in your working directory, and check for any
system error messages, resolve all problems, and then rerun.
ERROR (TBD-113): [Input] The Test Pattern Audits indicate that test vector resimulation is
required to recalculate the test responses. To commit these tests, resimulate them prior to
running commit_tests.
EXPLANATION:
Test vectors within the test vector file were created with order dependencies. An audit
was set when some of the original test vectors were deleted from the test vector file. This
removal of test vectors has invalidated the test responses.
USER RESPONSE:
Run either analyze_vectors or simulate_vectors to recalculate the test vector
responses and then run commit_tests on the new test data.
ERROR (TBD-114): [Input] Encounter Test does not support creating test vectors for
designs which contain unequal Channel Mask Enable pipeline lengths. Processing ends.

EXPLANATION:
The CME pipelines must be of equal length for Encounter Test to create valid test vectors.
The testmode contains CME pipelines of differing lengths.
USER RESPONSE:
Alter the design to ensure that if CME pipelines exist, they are of equal lengths before
test vectors can be produced, and then rerun.
ERROR (TBD-115): The Test Pattern Audits indicate that test vectors are smart scan test
vectors. Smart Scan test vectors can not be committed to the master TBDbin file.
EXPLANATION:
After test vectors have been manipulated for smart scan they may not be committed to
the master TBDbin file.
USER RESPONSE:
None.
ERROR (TBD-116): Encounter Test does not support migration of designs with more than
four channel mask enable pins. This design can not be migrated at this time.
EXPLANATION:
Current Encounter Test hierarchical test support is currently limited to designs with one
or two channel mask enable pins.
USER RESPONSE:
Processing terminates. This design can not be migrated at this time.
ERROR (TBD-118): Cannot use expandscan=yes on a testmode whose scan inputs are not
primary inputs (PIs). For LBIST you can run convert_vectors_to_stored_pattern to
get the correct format for input to expandscan=yes.
EXPLANATION:
During expandscan no stim_PI events were found in the Define_Sequence.
USER RESPONSE:
If you are trying to report LBIST vectors you need to run
convert_vectors_to_stored_patterns.

ERROR (TBD-119): Cannot expand Init Sequence defined in testmode, testmode. It

does not contain RMLs.
EXPLANATION:
A TBD method was called to expand the parent mode init sequences with an invalid
mode.
USER RESPONSE:
Check the parent mode definitions to validate use of RSL/RML logic.
ERROR (TBD-210): [Input] The committed tests will not be altered because the
INEXPERIMENT experiment for testmode testmode could not be found in the
committed test vector file.
A list of valid INEXPERIMENTS, inexperiment_numbers, fault status association and test

section types follows:
list of experiment, numbers, and test section types
EXPLANATION:
The specified INEXPERIMENT could not be found.
USER RESPONSE:
Specify a valid INEXPERIMENT name and rerun.
INEXPERIMENT experimen, for testmode testmode has fault status associated with
it. Encounter test does not allow theremoval of experiments that have fault status associated
with them. A list of valid INEXPERIMENTS, inexperiment_numbers, fault status
association and test section types follows:
list of experiments, numbers, and test section types
EXPLANATION:
The specified INEXPERIMENT has fault status associated with it. INEXPERIMENTS
which have associated fault status cannot be removed from the committed test vector file.
The removal of these tests would invalidate the reported fault coverage.
USER RESPONSE:
Specify a pattern-only (one with no associated fault status data) committed
INEXPERIMENT and rerun.
INEXPERIMENT experiment for testmode testmode is not unique. The

INEXPERIMENT number must be provided. Multiple experiments were created and

committed using this experiment name. A list of valid INEXPERIMENTS,
inexperiment_numbers, fault status association and test section types follows:
EXPLANATION:
The specified INEXPERIMENT is not unique. Multiple experiments were created and
committed using the same experiment name. We will not remove tests because we are
not sure which ones to remove.
USER RESPONSE:
Specify a valid inexperiment_numberand rerun.
inexperiment_number inexperiment_number for testmode testmode could
not be found in the committed test vectors file. A list of valid INEXPERIMENTS,
inexperiment_numbers, fault status association and test section types follows:
EXPLANATION:
The specified inexperiment_number could not be found.
USER RESPONSE:
Specify a valid inexperiment_number and rerun.
inexperiment_number inexperiment_number for testmode testmode has
fault status associated with it. A list of valid INEXPERIMENTS, inexperiment_numbers,
fault status association and test section types follows:
EXPLANATION:
The specified inexperiment_number has fault status associated with it.
INEXPERIMENTS which have associated fault status cannot be removed from the
committed test vector file. The removal of these tests would invalidate the reported fault
coverage.
USER RESPONSE:
Specify a pattern-only (one with no associated fault status data) committed
inexperiment_numberand rerun.

ERROR (TBD-218): [Input] NNN Channel Mask Registers exist but none are valid. No
mask all ability was defined. TBDgenerateMasks fails
EXPLANATION:
When the test mode was built, it was determined that all of the channel Mask Registers
were invalid. No mask all CME state exists. Unable to mask any X responses that it may
find. Processing terminates.
USER RESPONSE:
Determine the design problem that is causing all Channel Mask Registers to be invalid.
Fix the problem, rebuild and process your mode.
ERROR (TBD-219): [Tool] expand_vectors does not support expanding patterns on

testmodes with test_type running or final.
EXPLANATION:
Vector expansion does not support overlapped scan. Overlap is required with a
test_type of running or final because we are accumulating signatures.
USER RESPONSE:
This is a system limitation, unable to expand patterns for this testmode.
ERROR (TBD-220): [Tool] The program failed while attempting to obtain the OPCG
statistics for testmode modename. Contact Cadence Customer Support for assistance.
EXPLANATION:
The test pattern utility failed to obtain the OPCG register data. and terminated.
USER RESPONSE:
assistance.
ERROR (TBD-221): [Input] Invalid specification of testrange keyword . The tests must
exist within the file and be specified using one of the following forms:
testrange = testgroup, testgroup, ...
testgroup = odometer:odometer or
testgroup = testNumber:testNumber
odometer = blank, stored pattern type, signature-based type
for example, 1.1.1.3 or 1.1.1.2.5 for stored pattern type and
1.1.1.3(1.1) or 1.1.1.5(5.256) for signature-based type
testNumber = relative Test_Sequence number
EXPLANATION:

The data supplied with the testrange keyword is invalid. It must be specified using the
following guidelines:
testrange=testgroup,testgroup ,...
testgroup = odometer (process single piece of test data)
testgroup = odometer: (process test data beginning with
odometer through the end of the test data)
testgroup = :odometer (process from the beginning of the test
data to the end of the odometer test data)
testgroup = odometer:odometer (process beginning with odometer
test data to the end of the odometer test data)
testgroup = testNumber (process single piece of test data)
testgroup = testNumber: (process from the beginning with test
and through the end of the test data)
testgroup = :testNumber (process from the beginning of the test
data the end of testNumber
testgroup = testNumber:testNumber (process beginning with
testNumber to the end of testNumber
odometer = stored pattern type (that is, 1.1.1.3) or signature-
based type(that is, 1.1.1.3(1.1))
testNumber - integer (Test_Sequence number)
USER RESPONSE:
Correct the testrange specification and rerun the command.
ERROR (TBD-222): [Input] Test testNum was not found within filename.
EXPLANATION:
The specified test number does not exist within the test vector file.
USER RESPONSE:
ERROR (TBD-223): [Input] Overlapping ranges of tests were specified using the
testrange keyword. Correct the testrange specifications and rerun.
EXPLANATION:

Multiple test ranges were specified using the testrange keyword. These test ranges
overlap each other. Ensure the test ranges specified for the testrange keyword do not
overlap.
USER RESPONSE:
ERROR (TBD-224): [Input] The specified test can not be simulated using
controlpipeline=skip.
EXPLANATION:
Encounter Test was asked to simulate using the original un-manipulated scan latch
values. These values are saved within a Internal_Scan_Load event during
manipulation of the vectors. No Internal_Scan_Load event was found.
This indicates that the patterns were manipulated by an earlier release of Encounter
Test. Without the initial scan latch values, Encounter Test cannot simulate the un-
manipulated scan latch values.
USER RESPONSE:
Rerun simulation specifying controlpipeline=fm|gm.
ERROR (TBD-225): [Input] Found TG=IGNORE_LAST before finding TG=IGNORE_FIRST.

EXPLANATION:
TG=IGNORE_FIRST starts a group of patterns that the test generator ignores.
TG=IGNORE_LAST completes the group. The program detected a TG=IGNORE_LAST
before a TG=IGNORE_FIRST was encountered in the user-supplied sequence definition.
USER RESPONSE:
Correct the problems with the TG ignore Keyed_Data, reimport the sequence definition,
and then rerun test generation. Refer to TG=keyed data in the Automatic Test Pattern
Generation User Guide for additional information.
ERROR (TBD-226): [Internal] Tests created by the test generator could not be merged with
the specified test sequence. Contact Cadence Customer Support for assistance.
EXPLANATION:
An internal program failed due to one or more differences between the tests generated
by Encounter Test and the specified user sequence.
USER RESPONSE:

assistance.
ERROR (TBD-227): [Input] Found TG=IGNORE_FIRST but no TG=IGNORE_LAST was

found.
EXPLANATION:
TG=IGNORE_FIRST starts a group of patterns that the test generator ingores.
TG=IGNORE_LAST completes the group. The program detected a TG=IGNORE_FIRST
but did not detect an associated TG=IGNORE_LAST in the user-supplied sequence
definition.
USER RESPONSE:
Correct the problems with the TG ignore key_Data, reimport the sequence definition, and
then rerun test generation.
ERROR (TBD-228): [Input] Error while trying to add Scan_Unload events following the
final Product_Signature events for file working directory/testmode/
TBDpatt.experiment. Refer to previous messages to determine the problem. Contact
Cadence Customer Support for assistance if unable to correct the problem.
EXPLANATION:
An error has occurred. Previous error messages describe this condition.
USER RESPONSE:
Refer to the previous error messages for more information. Contact customer support
(see Contacting Customer Service on page 23) for assistance if you are unable to
determine the problem.
WARNING (TBD-229): [Severe] An OSCILLATE linehold statement was specified for pin
pinname, but this pin has no Start_Osc event in the mode initialization
Sequence_Definition. This OSCILLATE linehold override will be ignored.
EXPLANATION:
The linehold file allows changing the oscillator frequency on pins, but it does not allow for
defining or starting an oscillator on a pin that was not started when the testmode was
built. Processing continues but this pin will not be treated as an oscillator and the results
are likely to be invalid.
USER RESPONSE:
Ensure that the correct pin name was used in the OSCILLATE statement. If it is the
correct pin name, rebuild the testmode, ensuring that this pin has a Start_Osc event in

the mode initialization Sequence_Definition. Note that the pin must also have a
+/-OSC test function.
WARNING (TBD-230): An OSCILLATE linehold statement specified that pin pinname

should not oscillate, but this pin has no Start_Osc event in the modeinit
Sequence_Definition. This OSCILLATE linehold will be ignored.
EXPLANATION:
The linehold file allows removal of oscillation from a pin that was oscillating as a result of
a Start_Osc event in the mode initialization Sequence_Definition, but this pin had
no Start_Osc event.
USER RESPONSE:
Ensure that the correct pin name was used in the oscillator statement. If it is the correct
pin name, check the mode initialization Sequence_Definition to make sure that it is
correct. If the mode initialization Sequence_Definition is correct, then it is merely a
matter of redundant information, and this message can be ignored. You can remove this
message from future runs by removing the statement from the linehold file.

ERROR (TBD-231): Invalid logic value(s) specified in the input test vectors. Logic values of
0, 1, x, and Z are supported. Update your input TBDpatt or TBDseqPatt to ensure that all
specifed logic values are set to 0, 1, x, or Z. Rerun read_vectors or
read_sequence_definition.
EXPLANATION:
Supported logic values for Scan_Load, Scan_Unload, Stim_PI, and Measure_PO
events are 0,1, x, and Z.
USER RESPONSE:
Correct any incorrectly specified logic values and rerun.
ERROR (TBD-232): Found TG=IGNORE_FIRST or TG=IGNORE_LAST on a test_vector

event. TG=IGNORE_FIRST and TG=IGNORE_LAST keydata are not supported at the
test_vector event level. Each test_vector event to be ignored must have keyData of
TG=IGNORE.
EXPLANATION:

When indicating individual events for the Test Generation code to ignore, the group
delimiters of TG=IGNORE_FIRST and TG=IGNORE_LAST cannot be used. Each event
that you want to have ignored must have keyData of TG=IGNORE.
USER RESPONSE:
Correct the problems with TG ignore key_Data and reimport your sequence
definition. Rerun your test generation command.
ERROR (TBD-233): observeType signature observation requires a sequenceType

Sequence Definition, none was found, expand_vectors termainates.
EXPLANATION:
Produce MISR signature values can be observed either serially or in parallel. To do a
parallel observation of the MISR a misrobserve sequence must exist. To do a serial
observation of the MISR a sigobs sequence must exist. The sequence definition type
required to do the requested measure type does not exist. Process terminates.
USER RESPONSE:
If observation type chosen is not acceptable you will need to review the job log from
build_testmode to determine why the requested sequence definition type does not
exist. Corect these errors and rebuild your tesmode before rerunning
expand_vectors.
ERROR (TBD-234): misrobserve=parallel was specified on the command line.

Testmode requires a serial observation of the Product_MISR_Signature values using the
signature observation testmode. Serial MISR observation will occur.
EXPLANATION:
When your testmode was built serial MISR observation was specified. Your command
line specification of misrobserve=parallel will be reset to serial.
USER RESPONSE:
None
ERROR (TBD-235): Testmode modeName requires a serial observation of the

Product_MISR_Signature values. A sigobsreturn Sequence_Definition is also
required to return to the target testmode, none was found. Process terminates.
EXPLANATION:
When your testmode was built serial MISR observation of the
Product_MISR_Signature was specified. No signature observation return sequence
was found. Signature observation return sequence is required. Process will terminate.

USER RESPONSE:
review your build_testmode log to determine what went wrong. Correct problems
before resuming processing.
ERROR (TBD-236): There is a syntax error in your testrangefile, filename. Verify before
attempting to continue.
EXPLANATION:
There is a syntax error in the file you have supplied as your testrangefile. The file
can handle single testpatterns or a range of testpatterns seperated by a colon(:).
USER RESPONSE:
Correct the input file and rerun delete_testrange.
ERROR (TBD-237): The inputfile provided for

report_vectors_for_core_migration_tests, filename, is not a valid file produced
by prepare_core_migration_tests.
EXPLANATION:
The file provided for reporting was not generated by
prepare_core_migration_tests.
USER RESPONSE:
Provide the TBDtdm file that was created by prepare_core_migration_tests to
obtain the vectors for the core migration tests.
ERROR (TBD-300): Unable to establish pathname path as required to continue.

EXPLANATION:
The directory path named pathname could not be identified. Processing will terminate.
USER RESPONSE
Ensure that the correct values of keywords or environment variables have been specified
for WORKDIR and TESTMODE for the circuit being processed.
ERROR (TBD-301): All test types (intradomain, interdomain and static) are set to
no. Processing terminates.
EXPLANATION:

At least one of intradomain, interdomain or static keywords must be set to yes

or the default to yes for test sequences to be generated.
USER RESPONSE:
Ensure that at least one of the keywords intradomain, interdomain or static is
set to yes.
ERROR (TBD-302): Unknown clock name lhname in holdclock list will be ignored.
EXPLANATION:
The name lhname provided in the holdclock list keyword is not recognized as a valid
PI clock name, or valid PPI clock name or valid OPCG domain name. It is ignored and
processing continues.
USER RESPONSE:
Ensure all holdclock list entries are valid names of clock PIs or PPIs or OPCG Domain
names.
ERROR (TBD-303): Unable to open file filename for output. Processing terminates.
EXPLANATION:
Opening the file filename for output failed, which prevents writing any sequence
definitions.
USER RESPONSE:
Ensure the WORKDIR, TESTMODE, EXPERIMENT and outfilename are specified
correctly.
Contact customer support to have this investigated and fixed (see Contacting Customer
ERROR (TBD-304): Program Error. Domain opcgdomain needs delay, but has no down
counter. Processing terminates.
EXPLANATION:
While trying to program a test sequence that uses OPCG domain opcgdomain, a delay
counter was to be set, but this domain does not have a delay down counter. This is a
programming error.
USER RESPONSE:
Contact customer support (see Contacting Customer Service on page 23) to have this
investigated and fixed.

ERROR (TBD-305): Domain opcgdomain needs to program a delay count of

delayCount, but this will not fit in its delay counter of length regLen. Processing
continues.
EXPLANATION:
While trying to program a test sequence that uses OPCG domain opcgdomain, a delay
counter was to be set, but this domain's delay down counter length regLen is not large
enough to handle the desired delay counter value delayCount.
USER RESPONSE:
Ensure that delay counters large enough to cover delay for faster domains preceeded by
slower domains. Processing will continue with less efficient test sequences being
produced.
WARNING (TBD-306): There are opcgdomains OPCG domains, but only

opcgdomainswithcounters have delay counters. Inter-domain test sequences for
OPCG require delay counters. Coverage between domains may suffer.
EXPLANATION:
While trying to generate inter-domain test sequences for OPCG domains, it appears that
many domains do not have the delay counter implemented that is required in order to
create valid inter-domain delay tests when using OPCG clocking. Some inter-domain test
sequences cannot be generated, resulting in possibly poor inter-domain transition fault
coverage. There are opcgdomains OPCG domains defined with
opcgdomainswithcounters of them having delay counters.
USER RESPONSE:
If inter-domain testing of OPCG domains is required, ensure to add domain delay
counters when inserting the OPCG logic macros.
INFO (TBD-307): There are interdomanpairs valid inter-domain clock pairings, but
maxinterdomainseqs limits to maxinterdomainseqs the number of inter-domain
sequences that will be generated.
EXPLANATION:
While trying to generate inter-domain test sequences for OPCG domains, it appears that
there are more sequences that could be generated to cover valid inter-domain clock
pairings, but that the limit of maxinterdomainseqs is going to limit the number of
inter-domain test sequences that will be generated. Some loss of fault coverage is
possible.
USER RESPONSE:

Increase the setting of the maxinterdomainseqs keyword to obtains more test

sequences.
INFO (TBD-308): There were numseqs seqtype sequences generated.

EXPLANATION:
There were numseqs test sequences generated of type seqtype. The sequence
types are intra-domain, inter-domain or static.
USER RESPONSE:
If you do not see sequences of the type you are looking for, try using other keywords on
the prepare_opcg_test_sequences command line.
ERROR (TBD-309): Unable to load the OPCG Statistics for this test mode.
EXPLANATION:
There was a problem loading the OPCG information for this test mode. Be sure to specify
a valid OPCG test mode when running prepare_opcg_test_sequences.
USER RESPONSE:
This command is intended only for OPCG test modes and specifically for designs with
Cadence inserted OPCG logic. Be sure to specify a valid OPCG test mode when running
prepare_opcg_test_sequences.
INFO (TBD-310): Clock Information Table: there are numclks clocks of which numUsedClk
may be used in sequences
Clock Name Clock# Clock Information (# Gates/Nodes Observed)
EXPLANATION:
This provides a list of clocks associated with the circuit and test mode. It reports the
number of clocks defined for the test mode and the number to be used in sequences. For
eachclock, the number of nodes/gates observed by each clock is reported or the clock is
identified as a set/reset clock. Any identified set or reset clocks will not be used for
creating test sequences. Any clocks be held off are also denoted.
USER RESPONSE:
INFO (TBD-312): Clock Communication Table: Launch Clock# Capture Clocks(#nodes)

EXPLANATION:

This table indicates for each clock, which clocks capture data launchd by that clock. Each
listed capturing clock also denotes the (number) of gates/nodes between the domains.
USER RESPONSE:
None.
INFO (TBD-314): seqtype Clock Sequences Generated: Sequence Name Clocks Used
EXPLANATION:
This table lists the set of test sequences generated of type seqtype. It shows the clocks
being pulsed in each sequence.
USER RESPONSE:
None.
WARNING (TBD-316): Testmode testmodename does not appear to use Cadence

inserted OPCG macros. Better results may be obtained using the
prepare_sequence_templates command.
EXPLANATION:
The command prepare_opcg_test_sequences is intended for use with OPCG logic
inserted by Cadence. Test mode testmodename and this design does not appear to
use Cadence inserted OPCG logic. When Cadence inserts OPCG logic, it also
generates test mode assign files that specify all the OPCG domains and the
programming registers for them. All defined OPCG domain registers have specific types
and do not specify a type of custom. The prepare_opcg_test_sequences command
may not provide proper clocking sequence definitions for non-Cadence OPCG or for test
modes using tester clocks.
USER RESPONSE:
It is recommended that you try using the command prepare_sequence_templates
instead. Any clocking sequences produced by the prepare_opcg_test_sequences
command may not work correctly for non-Cadence OPCG logic.
WARNING (TBD-317): PPI ppiname is a clock not associated with an OPCG domain. It is
not known how to control this clock. Better results may be obtained using the
prepare_sequence_templates command.
EXPLANATION:
The command prepare_opcg_test_sequences is intended for use with OPCG logic
inserted by Cadence. The design and test mode define a clock PPI named ppiname

that is not associated with an OPCG clock domain, so there is no defined way to control
this clock PPI. Any sequences generated that use such a PPI will likely not work correctly.
USER RESPONSE:
It is recommended that you try using the command prepare_sequence_templates
instead. Any clocking sequences produced by the
prepare_opcg_test_sequences command may not work correctly for non-
Cadence OPCG logic.
INFO (TBD-318): There are blockingDomains domains with domain input blocking
provided. Domain input blocking may be used to improve test efficiency.
EXPLANATION:
They are blockingDomains OPCG domains defined with the ability to block their
inputs from other domains. The capability to block inputs from other domains is
programmable based on a program register setting. The blockinputs keyword was
specified or defaulted to yes, so generated sequences may exploit the use of domain
input blocking to enable more clocks to be pulsed in the same sequence.
USER RESPONSE:
None. You can avoid use of domain input blocking by specifying blockinputs=no on
the prepare_opcg_test_sequences command line. You should get better results by
letting it default to yes.
WARNING (TBD-319): Domain domainName register blockReg is of type

BLOCK_DOMAIN_INPUTS, but no programming values are listed with meanings of BLOCK or
ENABLE. Processing continues with an assumption that a value of 1 blocks the domain
inputs.
EXPLANATION:
The OPCG clock domain domainName has a programming register named blockReg
that is defined to be of type BLOCK_DOMAIN_INPUTS. This register type should
normally be defined along with a set of valid programming values to denote which value
will BLOCK and/or which value will enable the domain inputs to be observed. There
appear to be no valid programming values defined, so an assumption will be made that
a programmed value of 1 will block the domain from seeing inputs from other domains.
This matches the assumption of Cadence supplied domain blocking support.
USER RESPONSE:
Verify that the domain input blocking register should be programmed to 1 when blocking
of domain inputs is required and 0 to enable observation of domain inputs. If this is not

correct, redefine the test mode and explicitly specify programming value of 0 with a
meaning of "BLOCK" or "block".
WARNING (TBD-320): Domain domainName will not fire at half speed as requested
because its CLOCK_HIGH_GATE_SR domainReg is less than 3 bits long.
EXPLANATION:
The OPCG clock domain domainName has a programming register named
domainReg that is of type CLOCK_HIGH_GATE_SR but is less than 3 bits long. This
register type should be defined as 3+ bits long to enable running at half speed for
intradomain tests. This domain will run at its normal, full speed.
USER RESPONSE:
If you want this domain to be able to run at half speed, it needs to have been inserted
with a clock gating SR of 3 or more bits. Go back and insert domain macros that support
at least 3 pulses if you want the halfspeed keyword to apply to this domain.
INFO (TBD-321): There are numDomains domains that will fire at half speed in the
intradomain tests requested by the halfspeed keyword.
EXPLANATION:
Since the halfspeed option was requested, this message reports the number of
domains for which it is possible to run at half speed. This capability requires that OPCG
domains have the capability of firing at least 3 pulses. If no domains have at least 3 pulse
capability, then no domains will run at half speed for intradomain testing.
USER RESPONSE:
If you want domains to be able to run at half speed, they need to have been inserted with
a clock gating SR of 3 or more bits. Go back and insert domain macros that support at
least 3 pulses if you want the halfspeed keyword to apply.
WARNING (TBD-322): Domain domainName has a GO signal that was not resolved to a
primary input pin. This OPCG domain cannot be used.
EXPLANATION:
The OPCG clock domain domainName has a specified GO signal that was not resolved
to be one of the identified GO test function primary input pins. Without knowing which
GO signal to use to trigger this domain, we cannot use it in any generated test
sequences.
USER RESPONSE:

Ensure the clock domain has a valid primary I/O pin (input or bidirectional) specified in
the OPCG DOMAIN statement.
WARNING (TBD-323): Domain domainName register blockReg is of type

BLOCK_DOMAIN_INPUTS, but there is no cut-point found that prevents this control bit from
being observed. Processing continues with an assumption that no cut-point/PPI needs to be
set.
EXPLANATION:
The OPCG clock domain domainName has a programming register named blockReg
that is defined to be of type BLOCK_DOMAIN_INPUTS. All OPCG control register bits
need to be hidden behind cut-points. This specific programming register needs to have
its own cut-point and PPI associated with it that will block observability of this control bit.
When such a PPI exists, any generated sequence that uses the
block_domain_inputs register will also set the PPI to the appropriate value. Without
this PPI defined, the generated clocking sequence may not work as intended.
USER RESPONSE:
Ensure that there are cut-points and PPIs defined for all block_domain_inputs
control registers when the test mode is defined.
WARNING (TBD-326): [SEVERE] Glitches may occur when switching back into scan state
to apply the scan shift cycles that are part of the scan fill processing. A test pattern audit will
be set to prevent the commit_tests process from adding these test vectors to the master
test vectors file.
EXPLANATION:
Encounter test simulators do not catch possible glitches that may occur when switching
back into scan state to apply the scan shift cycles that are part of the scan fill processing.
Pattern audits will prevent commiting these test vectors.
USER RESPONSE:
Rebuild the testmode after changing the design to remove potential glitches. Recreate
test vectors.
WARNING (TBD-401): Audits indicate that the test vectors contained within this vector file
may be suspect. Audits Summary will be printed in TBDpatt file.
EXPLANATION:
The PattAuditStats for the vector file you are printing contains potential test data
problems. A list of the audits will be printed in the TBDpatt file.
USER RESPONSE:

If problems are unacceptable, correct the problem with your part and recreate the test
data.
WARNING (TBD-402): The sequence file for this mode (testMode) could not be opened.
expand_vectors will not be able to expand scan operations in this mode.
expand_vectors will not be able expand scan operations in this mode. Ensure that the
correct working directory was specified.
EXPLANATION:
The sequence file for this testmode could not be opened or expanded.
USER RESPONSE:
Ensure that the correct working directory is specified and rerun if necessary
WARNING (TBD-403): At NNN number level in the test vectors no data were found in
the requested range to be printed.
EXPLANATION:
The data requested to be printed does not exist.. report_vectors will continue without
any problems. Most likely this error is caused by something simple such as requesting
the third test section, when there are only two test sections in the test vectors.
USER RESPONSE:
Check your input parameters and change them if needed. If you were trying to print data
which you expected to be in your test vectors, check the run which created the test
vectors for any errors. For example, if you requested that experiment 1 be printed
(exper=1), and you expect that there should be an experiment in your test vectors, check
the preceding test generation run for errors.
WARNING (TBD-404): No levels were found in the requested range to be printed.

EXPLANATION:
The data requested to be printed does not exist. report_vectors will continue without
any problems. Most likely this error is caused by something simple such as requesting
the third test section, when there are only two test sections in the test vectors.
USER RESPONSE:
Check your input parameters and change them if needed. If you were trying to print data
which you expected to be in your test vectors, check the run which created these test
vectors for any errors. For example, if you requested that experiment 1 be printed
(exper=1), and you expect that there should be an experiment in your test vectors,
check the preceding test generation run which created these test vectors.

WARNING (TBD-405): Override of fixed value or lineheld latch netName by the

Scan_Load event in the seed file is ignored. Value from the linehold file is used.
EXPLANATION:
Your seed file specified an override of the named fixed value on a lineheld latch. This
override could cause problems in your test data. This override will not be honored.
USER RESPONSE:
Ensure that the requested override matches your intent. If so, add the needed value to
your linehold file and rerun if necessary. Refer to Linehold File in the Automatic Test
Pattern Generation User Guide for additional information.
WARNING (TBD-406): LBIST test vectors are not supported by Test Data Migration. The
LBIST tests will be dropped. The output test vector file may be empty.
EXPLANATION:
The test vectors file contains LBIST test vectors which are not supported for Test Data
Migration. The tests are not migrated.
USER RESPONSE:
Be aware that the If the input test vector file only contained LBIST test vectors, the output
test vectors file may be empty.
WARNING (TBD-408): User sequence Name: seqName was not found in the sequence file
for testmode modeName.
EXPLANATION:
The referenced sequence was not found in the sequence file for the testmode.
USER RESPONSE:
Ensure that sequence names are correctly specified and rerun if necessary.
WARNING (TBD-409): None of the user-specified sequences passed sequence checking

by TBDfitSequenceInit. Correct errors in specified sequences and rerun.
EXPLANATION:
TBDfitSequenceInit checks to ensure that the conditional stims make sense. If
PI_STIMS = 7 is the highest conditional stim found on a stim event, the number of
unconditional stims plus the number of conditional stims with the same or smaller value
must exist. If not equal, the user sequence cannot be used. A similar check is made for
LATCH_STIMS. It is also possible that the sequences had stims that conflicted with
Lineholds or Test Inhibits in effect for this run. In this case, there should be a message

preceding this one that explains the problem. TBDfitSequence found no good user
sequences in the list.
USER RESPONSE:
Correct any errors in the user sequence(s) and import the corrected user sequence
using read_sequence_definition.
WARNING (TBD-411): A linehold specified on pin pinName is overridden by test sequence

sequenceName. If the linehold was intended only to guide the test generator and not to
impose a firm restriction on the sequence, then ignore this message. If not, edit the sequence
and rerun read_vectors to reimport the sequence, and then rerun test generation
EXPLANATION:
A linehold was specified on the referenced pin name, but the referenced test sequence
specifies a pulse or stim (to the opposite state) on this pin.
USER RESPONSE:
Ensure the test sequence is correct. If not, edit the sequence and rerun read_vectors
to reimport the sequence, and then rerun test generation. If the sequence is correct, then
rerun test generation, removing the offending linehold. If the linehold was intended only
to guide the test generator and not to impose a firm restriction on the sequence, then
ignore this message. Refer to Linehold File in the Automatic Test Pattern
WARNING (TBD-412): Test sequence sequenceName specified an impossible condition

in a conditional event. This sequence will not be used.
EXPLANATION:
A test sequence may have conditional events, meaning that the event is not used if the
test generator did not produce enough Stim_PI (or Scan_load) events. The condition,
specified in Keyed_Data as PI_Stims = n (or Latch_Stims = m), stipulates that
the associated event is to be omitted in any test for which the test generator did not
produce at least n Stim_PI (or m Scan_Load) events.
The purpose of conditional events is to allow the possibility for one sequence to be
substituted for automatically generated tests where the number of Stim events may be
variable. When a generated test has fewer Stim events than the sequence, the user must
have specified which Stim events in the sequence should be skipped, or else the
sequence cannot be used for this test.
This message is produced if the condition requires more Stims than are contained in the
sequence. The event associated with such a condition would always be omitted,
because if there were enough Stims to satisfy the condition, then there would be more

Stims than were specified in the sequence, so the sequence would not match this test in
the first place.
If your sequence contains at least as many Stims as the largest number on the
conditionals, then this message means that for some conditional, there will be an
ambiguity in trying to match the sequence with a test containing that number of stims.
USER RESPONSE:
Examine the test sequence and correct the mistake, then re-import the sequence and
run the test generator again.
In tracking down the problem, first count the number of Put_Stim_PI events in the
sequence. Make sure that there is no conditional (PI_Stims = n) where n exceeds this
number. If this does not expose the problem, then for each n specified on a
Put_Stim_PI conditional, identify the exact Put_Stim_PI events which could be used
for a test with n Stim_PI events. If you find some value of n where the number of usable
Put_Stim_PI events in the sequence is not exactly equal to n, then you have found the
problem.
If the problem is not found in the PI_Stims = n conditionals, then follow the same
process for the Latch_Stims = m conditionals, comparing the number of usable
Scan_Load events with each value of m.
WARNING (TBD-413): Test sequence sequenceName conflicts with the TI attribute

specified on pin pinName. This sequence will not be used. If this sequence is required, edit
the sequence and rerun read_vectors to reimport the sequence and then rerun test
generation.
EXPLANATION:
The referenced pin name was specified to be held constant by a TI attribute. These
attributes are not intended to be overridden. Verify Test Structures (TSV) uses these
values in determining whether the logic conforms with the design guidelines which
support the generation of valid test vectors. The referenced sequence name specifies a
pulse or stim (to the opposite state) on this pin, invalidating the TSV assumptions.
Encounter Test cannot guarantee that its test vectors will be valid if this state is
overridden.
USER RESPONSE:
Ensure the test sequence is correct. If not, edit the sequence and rerun read_vectors
to reimport the test sequence and then rerun test generation. If the sequence is correct,
change the test function pin attribute editing the test mode definition and rebuilding the
test mode.

WARNING (TBD-414): Test sequence sequenceName conflicts with the specified linehold
on pseudo PI ppinName. If the linehold was intended only to guide the test generator and
not to impose a firm restriction on the sequence, then ignore the message. If not, edit the
sequence and rerun read_vectors to reimport the sequence, then rerun test generation.
EXPLANATION:
A linehold was specified on ppinName, but the test sequence sequenceName
specifies a pulse or stim (to the opposite state) on this pseudo primary input.
USER RESPONSE:
Make sure the test sequence is correct. If not, edit the sequence and and rerun
read_vectors to re-import the sequence, then rerun test generation. If the sequence
is correct, rerun test generation, removing the offending linehold. If the linehold was
intended only to guide the test generator and not to impose a firm restriction on the
sequence, ignore the message. Refer to Linehold File in the Automatic Test Pattern
WARNING (TBD-415): Test sequence sequenceName contains a dynamic pattern with

conditional events. This sequence will not be used because conditional events are not
supported on events within the dynamic pattern. To use this sequence, edit the sequence
definition by removing all keyed data conditionals from events within the dynamic pattern.
Then rerun read_sequence_definition and test generation.
EXPLANATION:
Timing data makes reference to the events in a sequence by their relative position within
the dynamic pattern. A conditional event is one that has an associated keyed data
statement of "PI_Stims = n" or "Latch_Stims = n", and will be dropped from the test
sequence for any automatic test that contains fewer than n of the referenced stim events.
Since the dropping of an event would change the relative number of any following events,
the timing data would not be usable. To specify the timing, you must know the exact
number and order of the events within the dynamic pattern.
USER RESPONSE:
Edit the sequence definition by removing all keyed data conditionals from events within
the dynamic pattern. Then rerun read_sequence_definition and test generation.
WARNING (TBD-416): Test sequence sequenceName contains a timing object and

WRPT events. This is not valid for stored pattern tests; the sequence will not be used. To
specify the timing data for stored pattern tests, define the test sequence using only stored
pattern events
EXPLANATION:

When a WRP test sequence is specified for stored pattern test generation, the sequence
is converted by replacing uniquely WRPT events by equivalent stored pattern events.
This may result in more or fewer events in the resulting sequence definition. Since timing
data makes reference to the events in a sequence by their relative position within the
dynamic pattern, the timing data would not make sense for the converted stored-pattern
sequence definition.
USER RESPONSE:
If you want to specify the timing data for stored pattern tests, you must define the test
sequence using only stored pattern events. Either specify a different sequence definition
or edit the sequence definition by removing all Channel Scan,
Connect_Tester_PRPG, Pulse_Tester_PRPG_Clocks, and
Pulse_Tester_SISR_Clocks events, replacing them with their equivalent stored
pattern events. Then rerun read_sequence_definition and test generation.
WARNING (TBD-417): Test Sequence sequenceName contains a timing object and

stored-pattern events. This is not valid for WRP tests. The sequence will not be used. To
specify the timing data for WRP tests, define the test sequence using only WRPT events.
EXPLANATION:
When a stored pattern test sequence is specified for WRP test generation, the sequence
is converted by replacing uniquely stored-pattern events by equivalent WRP events. This
may result in more or fewer events in the resulting sequence definition. Since timing data
makes reference to the events in a sequence by their relative position within the dynamic
pattern, the timing data would not make sense for the converted stored-pattern sequence
definition.
USER RESPONSE:
If you want to specify the timing data for WRP tests, you must define the test sequence
using only WRPT events. Either specify a different sequence definition or edit the
sequence definition by removing all Scan_load, Skewed_Scan_Load, Scan_Unload,
Skewed_Scan_Unload, Measure_PO, Stim_PI_Plus_Random, and Put_Stim_PI
events. Then rerun read_sequence_definition and test generation.
WARNING (TBD-418): Test Sequence sequenceName specified setup sequence

setupSequenceName, but sequence setupSequenceName cannot be found.
Sequence SequenceName will not be used. To use sequence sequenceName, import
setup sequence setupSequenceName before running test generation.
EXPLANATION:
A setup sequence was specified, but apparently it has not yet been imported to the
sequence file. The specified test sequence cannot be used without its setup sequence.

USER RESPONSE:
Run read_sequence_definition on setupSequenceName, the setup
sequence, and then rerun test generation.
WARNING (TBD-419): The channel scan in test sequence sequenceName has a different
[skewed_load|skewed_unload] attribute than its setup sequence,
setupSequenceName. This sequence will not be used. If you are initializing the channels
by using a channel scan event in the setup sequence, then it must be homogeneous with the
channel scan event in the test sequence with respect to the number of shift clocks. Edit the
setup sequence by correcting the skewed_load and/or the skewed_unload attribute on the
channel scan event. Rerun read_sequence_definition to import the updated setup
sequence before rerunning test generation.
EXPLANATION:
The setup sequence for this test sequence specified a channel scan, but with different
skewing (number of A and/or B clock pulses) than the channel scan in the test sequence.
If you are initializing the channels by using a channel scan in the setup sequence, it
must be homogeneous with the channel scan in the test sequence with respect to the
number of shift clocks.
USER RESPONSE:
Edit the setup sequence by correcting the skewed_load and/or the skewed_unload
attribute on the channel scan event. Then rerun read_sequence_definition to
imiport the updated setup sequence and then rerun test generation.
WARNING (TBD-420): All user sequences failed checking in TBDfitSequenceInit. No

clock yemplates were created by the generate clock template code. Correct any errors in the
user sequence(s) and import the corrected user sequence(s) using
read_sequence_definition and then rerun test generation.
EXPLANATION:
TBDfitSequenceInit checks to ensure that the user Sequences can be used for this
test generation run. The user sequences which pass TBDfitSequenceInit checking
are used to generate the clock templates. TBDfitSequenceInit found no good user
sequences in the list. No clock templates were generated.
USER RESPONSE:
Correct any errors in the user sequence(s) and import the corrected user sequence
using read_sequence_definition and then rerun test generation.
WARNING (TBD-421): Test Sequence sequenceName specifies user timing data but no
dynamic patterns exist. Timing of static patterns is not supported. Sequence

sequenceName will not be used. Correct sequence sequenceName by either removing

the timing object or adding dynamic patterns. Reimport the corrected sequence using
read_sequence_definition and then rerun test generation.
EXPLANATION:
The sequence contains timing data but no dynamic patterns exist.
USER RESPONSE:
Correct the user sequence by either removing the timing object or adding dynamic
patterns. Reimport the corrected user sequence using read_sequence_defintion,
and then rerun test generation.
ERROR (TBD-422): [Internal] The test generator Test Procedure contains non-uniform test
sequences. TBDfitSequence cannot process it. Contact Cadence Customer Support for
assistance.
EXPLANATION:
For sequence matching purposes between the TG sequences and the user sequences,
TBDfitSequence makes an assumption that all TG sequences will have uniform
clocking. The TG Test Procedure received by TBDfitSequence does not have uniform
sequences.
USER RESPONSE:
assistance.
WARNING (TBD-423): Test sequence sequenceName conflicts with the TC attribute

specified on pin pinName. The sequence will be used. Ensure the test sequence is correct.
If not, edit the sequence and rerun read_sequence_definition to import the updated
sequence, and then rerun test generation. If the sequence is correct, change the test
constrained pin attribute by editing the test mode definition and rebuilding the testmode
EXPLANATION:
The pin, pinName, was specified to be held constant by a TC attribute. These attributes
are not intended to be overridden. TSV uses these values in determining whether the
logic conforms with the design guidelines which support the generation of valid test
vectors. sequenceName specifies a pulse or stim (to the opposite state) on this pin,
invalidating the TSV assumptions. Encounter Test cannot guarantee that its test vectors
will be valid if this state is overridden.
USER RESPONSE:

Ensure the test sequence is correct. If not, edit the sequence and rerun
read_sequence_definition to reimport the sequence and then rerun test
generation. If the sequence is correct, change the test constrained pin attribute by editing
the test mode definition and rebuilding the test mode.
WARNING (TBD-424): Automatic clock sequence generation has produced pulses on one
or more pseudo-primary inputs. Tests produced by these sequences cannot be applied to the
hardware. Specify one or more or more user-generated test sequences when running test
generation for tests that can be applied to the hardware.
EXPLANATION:
This test mode contains some pseudo primary inputs, which Encounter Test can exercise
only with the help of user-supplied sequences. Test generation will proceed on an
uncommitted basis using automatic sequences to exercise the pseudo primary inputs.
An audit bit is set to alert downstream (manufacturing) processes that the test vectors do
not include all the primary input stimuli required to run on a hardware tester.
USER RESPONSE:
Specify one or more user-generated test sequences. The test sequences must first be
coded and imported using read_sequence_definition unless this has already
been done. If you are not familiar with this process, see "Coding Test Sequences" in the
Automatic Test Pattern Generation User Guide.
WARNING (TBD-425): Test Sequence, seqName, did not qualify for the run. A stim event
conflicted with a specified linehold value. Conflicts with lineholds are not supported. Either
remove the linehold which is conflicting with the stim event or change the value of the linehold
and then rerun.
EXPLANATION:
The referenced sequence name did not qualify for the run. A linehold value in the
sequence conflicts with a stim event.
USER RESPONSE:
If the Test Sequence is to be used, ensure the sequence is correct. Either remove the
linehold which is conflicting with the stim event or change the value of the linehold and
then rerun.
WARNING (TBD-426): seqName could not be collapsed. The test type of the sequence
was not specified as opcbistand only sequences with a test type of opcbistand are
collapsed.
EXPLANATION:

TBDCollapseSequence collapsed the sequence, but this sequence was not specified
as opcbist type.
USER RESPONSE:
Ensure the sequence is specified as test type of opcbist and rerun if necessary.
WARNING (TBD-427): [Severe] seqName was not able to be collapsed. The test type of
the sequence was specified as opcbist, but it did not pass TBDcollapseSequence
validation
EXPLANATION:
TBDcollapseSequence was a collapsed sequence, but this sequence was not
specified as opcbist type.
USER RESPONSE:
Ensure the sequence is specified as test type of opcbist and rerun if necessary.
WARNING (TBD-428): Scan cycle NNN of Observe register NNN contained an X which
could not be masked be the TBDgenerateMasks function. The existing Channel Mask
Register(s) could not mask this Observe reqister.
EXPLANATION:
The Observe register which required masking could not be masked. The existing
Channel Mask Register(s) could not mask this Observe reqister.
USER RESPONSE:
Processing continues. No signature will be produced for the test. If the masking logic is
incorrect, correct the problem and rerun.
WARNING (TBD-429): A scan load or unload event was found within the modeinit
sequence. Scan load and unload events within the modeinit sequence are not expanded.
EXPLANATION:
If a scan load or unload event is found within the modeinit sequence, it is not expanded
by report_vectors when expanding scan operations. Processing continues.
USER RESPONSE:
WARNING (TBD-430): No Channel_Scan event was found in test sequence

sequenceName. Its setup sequence, setupSequenceName contains a Channel_Scan
event. This sequence will not be used.

EXPLANATION:
The setup sequence for the referenced test sequence specified a channel scan, but the
test sequence does not include a Channel_Scan event.
USER RESPONSE:
Edit the test sequence and add a Channel_Scan event. Rerun
read_sequence_definition to import the updated test sequence and then rerun
test generation.
WARNING (TBD-431): One or more holes exist in this designs controllable registers. These
holes will cause scan values to be lost when data is shifted within the control registers.
EXPLANATION:
TBDmanipulateStimLatchEvent found that one or more scan chain holes exist.
When shifting scan chain values the existance of holes causes some data values to be
losted. Loss of these values may cause one or more of the targeted faults to not be
tested.
USER RESPONSE:
none.
WARNING (TBD-432): The test mode is not built correctly to allow for masking. Masking
will not be done for any tests. Check the configuration of your masking.
EXPLANATION:
ATPG is unable to mask any X's in the channels. Check the masking configuration add
adjust as desired. See build_testmode and verify_test_structures for
possible mask configuration problems.
USER RESPONSE:
WARNING (TBD-500): Lineholds and/or LFSR seed specifications caused the mode
initialization sequence to be updated. The modified Scan_Load event is changed and there
is a Scan_Unload event which may no longer have the correct values.
EXPLANATION:
The mode initialization sequence was modified by the specification of lineholds on fixed
value latches and/or LFSR seeds. This affected the last Scan_Load event in the
sequence. This event is followed by a Scan_Unload event, but the Scan_Unload event

is not updated since the mode initialization sequence is not resimulated. Therefore, the
Scan_Unload event may have the wrong value.
USER RESPONSE:
Make sure you really wanted to override the fixed value latch(es). Make sure you
specified the correct test mode for this run. Export the mode initialization sequence and
examine it to verify that all Scan_Unload events following the last Scan_Load event are
still valid when the Scan_Load event is changed in accordance with the lineholds and
seeds for this run. If you find that some Scan_Load in the mode initialization sequence
is not valid for this run, then you will have to either change the setup for this run and
repeat it or fix the initialization sequence and rebuild the test mode.
WARNING (TBD-502): User sequence: seqName failed TBDfitSequenceInit checking.

The sequence type is not supported. Contact Cadence Customer Support for assistance.
EXPLANATION:
The sequence type is not supported.
USER RESPONSE:
assistance.
WARNING (TBD-503): User sequence: seqName failed TBDcollapseSequence.

Stim_PI events are not supported by TBDcollapseSequence.
EXPLANATION:
The sequence passed to TBDcollapseSequence contains a Stim_PI or
Stim_PI_Plus_Random event.
USER RESPONSE:
Remove the Stim_PI event from the user sequence and rerun if necessary.
WARNING (TBD-505): The stim to stim val on net name, flat index flat index
overrides the non-default LINEHOLD to Line Hold val.The stim value will be simulated.
EXPLANATION:
A non-default linehold is overriden by a stim. The override is allowed.
USER RESPONSE:
Ensure that the override is correct.
INFO (TBD-801): Application_name Output file will be fileName.

EXPLANATION:
Name of the output file.
USER RESPONSE:
INFO (TBD-805): File(s) generated (bytes and name):

file_data
EXPLANATION:
The size and names of the files produced by this invocation of commit_tests are listed
for informational purposes following this message.
USER RESPONSE:
Informational message, no response necessary.
INFO (TBD-808): The objectName object is already in use try again later.
EXPLANATION:
Data is currently in use. Rerun application after the other jobs have completed.
USER RESPONSE:
INFO (TBD-810): Experiment experimentName is saved to the master test vectors

odometers: firstOdometer to lastOdometer (Relative test numbers firstNumber
to lastNumber).
EXPLANATION:
Odometers and relative test numbers for the test vectors of the experiment after they are
commited to the master test vectors file.
USER RESPONSE:
WARNING (TBD-811): Experiment experimentName does not contain valid test data.
commit_tests will not continue.
EXPLANATION:
An empty experiment was created by atpg. We will not attempt to commit this to the
master bin file.

USER RESPONSE:
INFO (TBD-813): expand_vectors input Vectors file is fileName. The input sequence
is sequenceFileName.
EXPLANATION:
The message states the name of the input test vectors file and the input sequence
definition file.
USER RESPONSE:
INFO (TBD-814): expand_vectors output Vectors file is fileName.

EXPLANATION:
The message states the name of the output test vectors file.
USER RESPONSE:
INFO (TBD-815): Sequence file (fileName) has been temporarily renamed from
fileName to fileName while a new version of it is being created.
EXPLANATION:
The sequence file has been temporarily renamed as indicated.
USER RESPONSE:
If any errors or system failures occur before program execution is complete, you may
recover your old sequence file by renaming the sequence file back to its original name.
INFO (TBD-816): Sequence file (fileName) has been successfully updated. fileName
has been deleted.
EXPLANATION:
The sequence file, which was temporarily renamed, now exists again with its original
name.
USER RESPONSE:
recover your old sequence file by renaming the TBDseq file back to its original name.

INFO (TBD-817): The test vectors file has been temporarily renamed from fileName to
fileName while a new version of it is being created.
EXPLANATION:
The test vectors file has been temporarily renamed as indicated.
USER RESPONSE:
recover your old tes vectors file by renaming the temporary vectors file back to its original
name.
INFO (TBD-818): The vectors file (fileName) has been successfully updated. fileName
has been deleted.
EXPLANATION:
The vectors file, which was temporarily renamed, now exists again with its original name.
USER RESPONSE:
recover your old vectors file by renaming the temporary file back to its original name.
INFO (TBD-822): cmdname Output test vectors file name will be filename.
EXPLANATION:
Name of the test vectors output file.
USER RESPONSE:
INFO (TBD-823): Pattern audit statistics cannot be printed because they do not exist.
EXPLANATION:
No pattern audit statistics exist for the file.
USER RESPONSE:
INFO (TBD-824): The following test sequence was generated by ATPG, but could not be
matched with any of the user-specified sequences. This sequence will not be used.
EXPLANATION:

Test generation is being run with user-defined test sequences. The test pattern generator
has created the sequence which is printed following this message, but the number of PI
and Latch stims do not match any of the specified user sequences so it cannot be used.
The faults targetted by this sequence may go untested.
USER RESPONSE:
If you have flexibility to define other sequences, examine this automatic sequence and
then define one that more closely matches it and conforms to the necessary constraints.
Then code it, run read_sequence_definition to import the sequence, and run
another test generation job.
INFO (TBD-827): The test vectors file is already at the required format level, migration is not
required.
EXPLANATION:
The user is only required to use the TBDmigrate function when processing TBDbin files
produced prior to TestBench Test 4.1. The Migrate function has determined that the
formatlevel of the TBDbin is TestBench Test 4.1 or greater.
USER RESPONSE:
INFO (TBD-828): TBDmigrate: the input TBDbin file is backlevel. Run TBDmigrate with the
-w flag to create an experiment at the current release level.
EXPLANATION:
The test vectors file was produced prior to TestBench 4.1.
USER RESPONSE:
Run TBDmigrate with the -w flag to create an experiment at the current release level.
INFO (TBD-829): TBDmigrate for: PROJECT=project PARTID=entity/

variation/iteration TESTMODE=testMode INEXPERIMENT=experiment is not
necessary. No changes in test data were required.
EXPLANATION:
No changes in the test vectors were required. The pattern Audit statistics for the input
TBDbin file were updated to indicate that no migration is required. If an output experiment
was requested, none will be written.
USER RESPONSE:

INFO (TBD-830): Test vectors file has been renamed from fileName to fileName.
EXPLANATION:
The vectors file has been renamed as indicated.
USER RESPONSE:
No user response required.
(severity) (TBD-831): ) commit_tests CompletionString.

EXPLANATION:
Indicates whether or not commit_tests was successful.
USER RESPONSE:
No response required, this is informational.
WARNING (TBD-832): fileName is not registered on the globalData file. No updates were
made to the committed tests file.
EXPLANATION:
The uncommitted tests file was not registered on the globalData File. commit_tests
could not update the committed tests File.
USER RESPONSE:
Check messages from the job log which created this experiment.
INFO (TBD-836): Pattern Statistics for test vectors: TBDbin.testmode.experiment

EXPLANATION:
Gives the name of the testmode being processed by report_vector_volume.
USER RESPONSE:
INFO (TBD-838): commit_tests produced the following files (bytes/name):

EXPLANATION:
The size and names of the files produced by this invocation of commit_tests are listed
for informational purposes following this message.
USER RESPONSE:

Informational message, no response necessary.
INFO (TBD-840):
Experiment: experiment
---------------------------------
Tester loops: NNN
Test Sequences: NNN
ScanLoad Events: NNN
ScanUnloadEvents: NNN
Number of weight sets: NNN
Effective patterns: NNN
Total patterns: NNN
EXPLANATION:
This message states Information about test vectors contained within the test vectors file.
USER RESPONSE:
No response required, informational message.
INFO (TBD-841): Effective tester cycles: NNN

Total Tester cycles: NN
EXPLANATION:
This message is a continuation of message 840. Only 9 parameters are allowed by the
message handler.
USER RESPONSE:
(severity) (TBD-842): report_vector_volume CompletionString.

EXPLANATION:
Indicates whether or not report_vector_volume was successful.
USER RESPONSE:
No response required if informational. If a terminating message, refer to previous error
messages. Correct problem(s) and rerun.
INFO (TBD-843): FCM/WBM module test data volume calculation

Mode: testmode
------------------------------
Scan Chains: NNN
Maximum scan chain length: NNN
Total # tests per 256k logical buffer: NNN

Logical 256k buffers in a single buffer load: NNN

Total # effective tests generated: NNN
Max tests generated must be less than: NNN
EXPLANATION:
Information about test data contained within the vectors. Based on FCM/WBM Module
test data volume calculation from Burlington.
USER RESPONSE:
INFO (TBD-844): FCH module test data volume calculation

Mode: testmode
------------------------------
Scan Chains: NNN
Total tester data volume, must be less than 64M: NNN
EXPLANATION:
Information about test data contained within the vectors. Based on FCH Module test data
volume calculation from Burlington.
USER RESPONSE:
INFO (TBD-845): WBL module test data volume calculation

Mode: testmode
------------------------------
Scan Chains: NNN
Total # tests per 2M buffer segment: NNN
Max tests that fit in a single buffer load: NNN
EXPLANATION:
Information about test vectors contained within the vectors file. Based on FCM/WBM
Module test data volume calculation from Burlington.
USER RESPONSE:
INFO (TBD-846):
Mode: testmode
------------------------------

Scan Chains: NNN

EXPLANATION:
Information about test vectors contained within the vector file.
USER RESPONSE:
INFO (TBD-847): Simulation options report for file: fileName

EXPLANATION:
The simulations options report has started.
USER RESPONSE:
INFO (TBD-848): Experiment NNN TestSection NNN simulation options: options

EXPLANATION:
The simulation options in effect for when this test section was created are listed.
USER RESPONSE:
INFO (TBD-849):No simulation options were found for Experiment NNN TestSection NNN.
EXPLANATION:
No simulation options were found for this TestSection. There are two possible
explanations for this. The tests were created before simulation options were stored
within the test vectors file, or the vectors have not been simulated by Encounter Test.
USER RESPONSE:
INFO (TBD-850): File name contains no test vectors.

EXPLANATION:
Either no experiments were found or the experiment(s) found contained no Test
Sections. The file contains no test vectors.

USER RESPONSE:
INFO (TBD-851): Simulation options report complete.

EXPLANATION:
The simulation options report has completed.
USER RESPONSE:
INFO (TBD-852): Sequence sequenceName was found to be complex for the following
reason(s): reasons
EXPLANATION:
Encounter Test test generators cannot process user sequences that contain more than
the following:
1 scan_load event
2 Stim_PI, Stim_PI_Plus_Random, Put_Stim_PI or Stim_PPI events
2 static clock pulses
10 dynamic clock pulses
1 dynamic pattern
Events with Control Statements STIM=DELETE PI_STIMs=n or
LATCH_STIMs=n Stim_Clock events
If the user-supplied sequence exceeded one or more of the preceding limits, the
sequence is complex. Patterns that are marked with key data TG=IGNORE or groups of
patterns beginning with TG=IGNORE_FIRST and ending with TG=IGNORE_LAST are
skipped during the complexity checking. When the sequence is found to be complex,
Encounter Test will attempt to use the older sequence fitting process.
USER RESPONSE:
WARNING (TBD-853): Sequence SequenceName has more than 1 clock input active
during a dynamic clock pulse event. Simulation will be done with the clocks overlapped. The
results may be incorrect if there are races in the design.
EXPLANATION:

A patterns has been detected which activates multiple clock inputs simultaneously. For
cases in which multiple clocks are pulsed simultaneously within the same event,
Encounter Test does not do any timing verification to ensure the clock pulses will actually
overlap in the logic. Encounter Test will simulate the logic with the clocks on
simultaneously, but this may produce incorrect results if the clocks do not actually
overlap.
USER RESPONSE:
There are two different responses that can be taken. If the clocks are not required to be
on simultaneously, the input patterns can be modified to serially activate and deactivate
the clocks. If the clocks are required to be overlapping to produce the correct results, the
user should verify that the timing of the common logic ensures that the clocks are
overlapped so that the simulator's predicted results will match the actual hardware.
TBD Internal program error messages 999.
All internal program error messages will use message # 999. This internal message will
give the filename of the file where the error occurred, the line number where the error
occurred and a short string identifying the program problem.
INFO (TBD-854): No skewedscanfill sequence exists for the test mode. A default
skewedscanfill sequence has been created by the scanfill process.
EXPLANATION:
Skewed_Scan_Loads are possible for the specified test mode. No skewedscanfill
sequence exists for this test mode. The scanfill code creates a default
skewedscanfill sequence. The default skewedscanfill sequence consists of:
SCANENTRY sequence ( if one exists )
SCANPRE
1 to n copies of the SCAN sequence ( scanfill length )
SKEWLOAD sequence
SECTEXIT sequence ( if one exists )
SCANEXIT sequence ( if one exists )
USER RESPONSE:
INFO (TBD-855): Holes exist within the control registers. ScanFill processing shifts values
within the Scan_Load events as part of the scanFill processing. Latch values which are
shifted into holes within the control register are lost. Test coverage could be affected.

EXPLANATION:
Shifting values within the control registers which contain holes can affect the test
coverage. Some faults targeted by test generation may not be tested.
USER RESPONSE:
No response required, this is informational. If this is a probelm correct control register
problems to remove the holes, rebuild the testmode and then rerun.
INFO (TBD-856): After prepare_core_migration_tests, numberSequences test

sequences have been converted.
EXPLANATION:
This is a count of the number of patterns that were converted to the TBDtdm file.
USER RESPONSE:
ERROR (TBD-999): [Internal] Internal Program Error occurred in file: fileName

line:NNN.msgString
EXPLANATION:
Program Error.
USER RESPONSE:
assistance.


8
TBM - Test Pattern Manipulation
Messages
TBM-001 through TBM-030 on page 167

TBM-031 through TBM-999 on page 175
TBM-001 through TBM-030

ERROR (TBM-001): [Internal] Space allocation failed. Cannot allocate space for table.
EXPLANATION:
USER RESPONSE:
INFO (TBM-002): Encounter Test Pattern Audit statistics indicate that no pattern
manipulation is required.
EXPLANATION:
The Encounter Test pattern audit statistics indicate that manipulation is not required for
this experiment.
USER RESPONSE:
INFO (TBM-003): Encounter Test test pattern audit statistics indicate that the test patterns
for this experiment have already been manipulated.
EXPLANATION:

TBM - Test Pattern Manipulation Messages
The Encounter Test pattern Audit statistics indicate that

insert_vector_pipeline_sequence was previously run on this experiment. No
manipulation is required.
USER RESPONSE:
ERROR (TBM-004): [Internal] Unable to obtain a read lock on the objectName object.
EXPLANATION:
The object indicated in the message is currently unavailable.
USER RESPONSE:
Rerun after object has been freed.
ERROR (TBM-005): [Internal] Error - failure attempting to lock objectName object.

Object is not registered on the globalData file or incorrect input parameters have been
specified.
EXPLANATION:
The object indicated in the message is not registered on the globalData file. Wrong input
parameters could have been specified.
USER RESPONSE:
Refer to previous messages. After correcting any problems rerun your job(s).
If problems persist, contact customer support (see Contacting Customer Service on
page 23).
INFO (TBM-006): insert_vector_pipeline_sequence for: filename

EXPLANATION:
The message states the name of the test vector file being manipulated.
USER RESPONSE:
ERROR (TBM-007): [Internal] Failed while trying to register the output uncommitted test
vectors file on the globalData.
EXPLANATION: globalData

The command attempted to register the output test vectors file on the globalData file, but
failed. A preceding error message describes the error condition. Processing terminates.
USER RESPONSE:
Correct the error condition described in the preceding message and rerun.
ERROR (TBM-008): [Internal] Failure attempting dependency creation: experiment ->

testmode.
EXPLANATION:
This experiment is dependent on the test mode. The command attempted to register this
dependency in the globalData file, but failed.
A preceding message from the globalData file utility describes the error condition.
USER RESPONSE:
ERROR (TBM-009): One or more test vectors have already been manipulated. Tests which
already have been manipulated may not be manipulated again.
EXPLANATION:
The test pattern audit statistics indicate that manipulation is required, but one or more
test vectors within the file have already been manipulated.
Determine how this occurred and correct the errors.
USER RESPONSE:
Reprocess after correcting test vector errors. If the problems persist, contact customer
support (see Contacting Customer Service on page 23).
ERROR (TBM-010): The input uncommitted tests contain an non-supported testSection

Type. Processing terminates.
EXPLANATION:
insert_vector_pipeline_sequence found a test section type of channelScan,
logic_BIST, logic_WRP or Macro. These test section types are not supported by
insert_vector_pipeline_sequence. Determine how this occurred and correct the
errors.
USER RESPONSE:

Reprocess after correcting test vector errors. If the problems persist, contact customer
INFO (TBM-011): TestSequence

experiment.testSection.testerLoop.testProcedure.testSequence
was found to be invalid. It will be dropped from the output test vectors file. A pipeline scan test
must begin with a Scan_Load event and either end with a Scan_Unload event or contain a
Channel_Scan event. One or more of these events were missing from the specified test.
EXPLANATION:
A pipeline scan test must begin with a Scan_Load event and either end with a
Scan_Unload event or contain a ChannelScan event. One or more of these events were
missing from the specified test.
USER RESPONSE:
ERROR (TBM-012): insert_vector_pipeline_sequence encountered an

unsupported event type of type. insert_vector_pipeline_sequence processing will
terminate.
EXPLANATION:
Skewed loads are not supported for pipeline scan. The input test vectors contain skewed
loads. The patterns cannot be manipulated.
USER RESPONSE:
Correct the input patterns and rerun.
ERROR (TBM-013): insert_vector_pipeline_sequence failed while trying access

data from the scanop sequence. Processing will terminate.
EXPLANATION:
While trying to process a Scan_Load or Scan_Unload event,
insert_vector_pipeline_sequence was returned a NULL pointer when trying to
access the scan operation sequences. Without this data,
insert_vector_pipeline_sequence cannot continue processing.
USER RESPONSE:
Ensure there are no problems with the sequence file for the currently processed
testmode. If there are no problems with the sequence file, contact customer support (see
Contacting Customer Service on page 23) for assistance.

INFO (TBM-014): The test vectors file has been temporarily renamed from fileName to
fileName while a new version of it is being created.
EXPLANATION:
The test vectors file has been temporarily renamed as indicated.
USER RESPONSE:
recover your old test vectors file by renaming the temporary file back to its original name.
ERROR (TBM-015): Failed while attempting to rename fileName.

insert_vector_pipeline_sequence processing will terminate.
EXPLANATION:
An attempt to rename the referenced file failed and caused termination.
USER RESPONSE:
Ensure the file exists. If the file exists, contact customer support (see Contacting
ERROR (TBM-016): Failed while attempting to open the fileName file.

EXPLANATION:
An attempt to open the referenced file failed and caused termination.
USER RESPONSE:
Ensure the file exists. If the file exists, contact customer support (see Contacting
ERROR (TBM-017): Failure reading Filename fileName.

EXPLANATION:
An attempt to read the referenced file failed and caused termination.
USER RESPONSE:
Review preceding error messages to determine the cause. Correct error(s) and rerun.
ERROR (TBM-018): [Internal] I/O error occurred writing to fileName.


EXPLANATION:
An I/O error occurred and caused termination.
USER RESPONSE:
Verify that you are not running out of space in your working directory, and check for any
system error messages. Fix any problems and rerun.
(severity) (TBM-019): insert_vector_pipeline_sequence CompletionString.

EXPLANATION:
The message indicates whether insert_vector_pipeline_sequence was
successful.
USER RESPONSE:
INFO (TBM-020): File(s) generated (bytes and name):

EXPLANATION:
The size and names of the files produced and/or updated by this invocation of
insert_vector_pipeline_sequence are listed for informational purposes following
this message.
USER RESPONSE:
ERROR (TBM-021): insert_vector_pipeline_sequence - pinname has a CME or

CMI flag and is also pipelined.
EXPLANATION:
The referenced pin contains either a CME or CMI flag as well as being pipelined. Further
updates to insert_pipeline_vector_sequence are required before this design
style can be handled.
USER RESPONSE:
Do not pipeline these control signals.
WARNING (TBM-022): Sequence Definition name was found to be invalid.

insert_vector_pipeline_sequence cannot process this sequence definition.
EXPLANATION:

A pipeline scan sequence definition must contain a Channel_Scan event, however

none was found. The sequence definition will not be manipulated.
USER RESPONSE:
WARNING (TBM-023): Sequence Definition name was not found in the TBDseq file.
Processing continues.
EXPLANATION:
The referenced sequence was not found in the sequence definition file therefore it cannot
be manipulated.
USER RESPONSE:
No response is required.
WARNING (TBM-024): Sequence Definition name has already been manipulated. It will
not be manipulated again. Processing continues.
EXPLANATION:
The referenced sequence definition has already been manipulated. The program does
not manipulate a previously manipulated sequence definition.
USER RESPONSE:
WARNING (TBM-025): The test mode initialization sequence does not need to be
manipulated. Processing continues.
EXPLANATION:
The program has determined the test mode initialization sequence does not require
manipulation.
USER RESPONSE:
ERROR (TBM-026): insert_vector_pipeline_sequence failed attempting to open

the name.
EXPLANATION:
insert_vector_pipeline_sequence failed to open the referenced TBDseq.

USER RESPONSE:
Verify the name and permissions, then rerun.
WARNING (TBM-027): insert_vector_pipeline_sequence found conflicting values

for PI pinname and it corresponding pseudo PI. Output TBDbin file pattern odometer.
EXPLANATION:
When manipulating the pattern, the PPI event following the Stim_PI event contained a
conflicting value on the pseudo PI. The Stim_PI value is dropped and the pseudo PI
value is used.
USER RESPONSE:
If the Stim_PI value is required, correct the pseudo PI value in the input file and rerun.
severity (TBM-028): delete_testrange completionString

EXPLANATION:
The message and severity indicates whether delete_testrange successfully
completed.
USER RESPONSE:
ERROR (TBM-029): The delete_testrange command failed due to an invalid

testrange specification. Refer to preceding messages which highlight testrange
problems. Correct the testrange specification and rerun.
EXPLANATION:
The specified testrange either does not exist in the input experiment or it is not wholly
contained within the input experiment. That is, nonexistent tests were asked to be
removed. Tests are not removed if a request is ambiguous.
USER RESPONSE:
Ensure the existence of all tests specified for removal from the input test vectors. Correct
the testrange specification and rerun delete_testrange.
ERROR (TBM-030): The delete_testrange command encountered looping tests within

the input experiment and cannot be used to remove tests from the input test vector file.
EXPLANATION:

The delete_testrange command does not support removal of looping

Test_Sequences from the test vector file.
USER RESPONSE:
Use the following procedure to delete looping Test_Sequences:
1 Run report_vectors to create a TBDpatt file for the input experiment
2. Delete the required tests from the TBDpatt file.
3. Run read_vectors to create a new experiment.
TBM-031 through TBM-999

WARNING (TBM-031): [Severe] The delete_testrange command removed one or
more tests where string_describing_condition.
EXPLANATION:
When removing a test where the preceding Channel_Scan or
Compressed_Output_Stream event indicates overlapped scan, the tests are not
independent. Each test influences not only the output responses for that test, but also for
the preceding test. When such tests are rearranged in any manner, the output responses
are no longer valid and must be recomputed. Tests will fail at the tester.
USER RESPONSE:
Run simulate_vectors or analyze_vectors on the new experiment to recompute
the output responses.
WARNING (TBM-032): [Severe] The delete_testrange command removed one or

more tests where string_describing_condition.
EXPLANATION:
The tests must be independent however the condition stated by this message indicates
the tests are not independent. Each test influences not only the output responses for that
test, but also for the succeeding test. When such tests are rearranged in any manner, the
output responses are no longer valid and must be recomputed. Tests will Fail at the
tester.
USER RESPONSE:
the output responses.

ERROR (TBM-033): The testrange specified to the delete_testrange command

would result in the removal of all tests from the uncommitted test vector file. The
delete_testrange command treats this as an error. If your intent is to remove all tests,
use the delete_tests command. If your intent is to remove some but not all tests, correct
the testrange specification and then rerun delete_testrange.
EXPLANATION:
The delete_testrange command treats the stated condition as an error for the
following reasons:
It is safer to assume erroneous testrange input rather than using
delete_testrange to delete all of the tests.
Removing all test vectors is more efficiently accomplished by the
delete_tests command. The delete_tests command removes all
Encounter Test files associated with the uncommitted test vectors as well as the
test vectors.
USER RESPONSE:
Either correct the testrange specification and rerun delete_testrange or run
delete_tests to remove all tests.
ERROR (TBM-034): name was specified for both EXPERIMENT and INEXPERIMENT.
EXPERIMENT and INEXPERIMENT can not be the same. Processing terminates. Rerun
specifying a new EXPERIMENT name.
EXPLANATION:
When running edit_compression_pipeline_vectors you cannot over write the
input experiment file with the manipulated test vectors. The un-manipulated vectors are
required for diagnostic processing.
USER RESPONSE:
Specify a new output experiment name and then rerun.
ERROR (TBM-035): Error opening required file file_name. Processing terminates.

EXPLANATION:
The referenced file cannot be opened or does not exist.
USER RESPONSE:
Ensure the file exists and that it has the correct permissions. If the file does not exist, run
the prepare compression pipeline script to generate the file and then rerun this
command.

WARNING (TBM-036): TBM error on line line_number. object_name is not an SI or

SO pin (entry is ignored).
EXPLANATION:
Specify only scan input and scan output pins in the compressionPipelineInfo.
There is an error in the script to prepare compression pipelines.
USER RESPONSE:
assistance.
INFO (TBM-040): Initializing togglegram data structure

EXPLANATION:
The toggle gram data structure allocation process is starting.
USER RESPONSE:
INFO (TBM-041): Reading design into memory

EXPLANATION:
The program is reading the design information.
USER RESPONSE:
INFO (TBM-042): Successfully read design into memory

EXPLANATION:
The design information has been successfully read into memory.
USER RESPONSE:
ERROR (TBM-043): string register number of length number is string.

EXPLANATION:
The toggle information for the scan chain cannot be calculated if a scan chain is only
controllable or only observable.
USER RESPONSE:

Correct the scan chain, rerun ATPG, and then run write_toggle_gram.
INFO (TBM-044): Found number scan chains that are both observable and controllable in
the current test mode.
EXPLANATION:
The message gives information on the control and observe register mappings for the
current test mode.
USER RESPONSE:
ERROR (TBM-045): write_toggle_gram requires all scan chains to be both observable

and controllable to calculate toggle information.
EXPLANATION:
The program has detected that not all all registers are both controllable and observable.
The toggle information for the scan chain cannot be calculated if a scan chain is only
controllable or only observable.
USER RESPONSE:
Correct the scan chain, rerun ATPG, and then run write_toggle_gram.
INFO (TBM-046): The longest scan chain length is number.

EXPLANATION:
The message states the longest scan chain length, that is, the number of shift cycles for
each sequence.
USER RESPONSE:
INFO (TBM-047): Reading weight table file filename.

EXPLANATION:
The program is reading the weight table file. The flops under the block will be assigned
the weight specified in the file.
USER RESPONSE:
INFO (TBM-048): Completed reading weight table file

EXPLANATION:
The program has completed reading the weight table file.
USER RESPONSE:
INFO (TBM-049): Completed initializing togglegram data structures

EXPLANATION:
The toggle gram data structure initialization process is complete.
USER RESPONSE:
INFO (TBM-050): Processing toggle information for the specified testrange

EXPLANATION:
The program is processing the test sequences that will be analyzed for toggle activity.
USER RESPONSE:
INFO (TBM-051): Processing Scan_Unload of sequence string and Scan_Unload

sequence of string.
EXPLANATION:
This message identifies the currently processed sequence.
USER RESPONSE:
INFO (TBM-052): Completed processing toggle information for the specified testrange
EXPLANATION:
Toggle information processing is complete for the specified testrange.
USER RESPONSE:
INFO (TBM-053): Generating a toggle report categorized by Sequence/ScanCycle/Flop

EXPLANATION:
The program is generating a categorized toggle analysis report.
USER RESPONSE:
INFO (TBM-054): string Toggle report is categorized by category

EXPLANATION:
The toggle analysis report is categorized by the referenced category.
USER RESPONSE:
INFO (TBM-055): Writing toggle count file filename for string cycles only.
EXPLANATION:
The program is writing the toggle count file to the referenced file name.
USER RESPONSE:
ERROR (TBM-056): License string is unavailable.

EXPLANATION:
The referenced license is required to run the program, but is unavailable.
USER RESPONSE:
Ensure the license is available and rerun.
ERROR (TBM-057): Unable to check-in license string

EXPLANATION:
An error occurred while returning the license.
USER RESPONSE:
Check the license server, resolve problems, and rerun.
INFO (TBM-058): Successfully obtained licenses string , string

EXPLANATION:

The referenced licenses were successfully obtained.

USER RESPONSE:
INFO (TBM-061): Obtaining licenses string , string

EXPLANATION:
The program is obtainng the referenced licenses.
USER RESPONSE:
INFO (TBM-062): All test sequences will be analyzed for toggle activity.
EXPLANATION:
All test sequences in the TBDbin will be analyzed for toggle activity.
USER RESPONSE:
INFO (TBM-063): Test sequences between odometer range string and string will be
analyzed for toggle activity.
EXPLANATION:
Test sequences in the referenced odometer range will be analyzed for toggle activity.
USER RESPONSE:
INFO (TBM-064): Relative test sequence number string maps to odometer string
EXPLANATION:
The message states the mapping from the referenced relative test sequence number to
the referenced odometer string.
USER RESPONSE:
ERROR (TBM-065): write_toggle_gram will need at least two sequences to analyze

toggle count information.

EXPLANATION:
The write_toggle_gram command uses the Scan_Unload of the first sequence and
the Scan_Load of the next sequence to analyze toggle activity for the sequence.
USER RESPONSE:
Regenerate test patterns with more than one sequence and then rerun
write_toggle_gram.
WARNING (TBM-066): Window size of number cycles for calculating sliding average is
reduced to number
EXPLANATION:
If the scan chain length is lesser than the specified window size, the window size used
for calculating the sliding window is reduced.
USER RESPONSE:
No response is required if this condition is acceptable; otherwise, modify the window size
to obtain the desired results.
WARNING (TBM-067): Unable to find flop/block string in the design

EXPLANATION:
The program was unable to find the flop or block associated with the referenced flop/
block name given in the weight table file.
USER RESPONSE:
Ensure the flop or block name is in the design and rerun if necessary.
INFO (TBM-068): Assigning weight float to scan-flip flop string

EXPLANATION:
The assigned weight is based on the information in weight table file.
USER RESPONSE:
WARNING (TBM-069): Weights assigned to string are commented. The commented

weights are not assigned.
EXPLANATION:

One of the lines in the weight table file is commented, the weight is not assigned. A line
beginning with a hash is a commented line.
USER RESPONSE:
No response is required if this condition is acceptable; otherwise modify the commented
string as necessary and rerun.
ERROR (TBM-070): Unable to find committed experiment string

EXPLANATION:
The committed experiment was not found in the TBDbin data.
USER RESPONSE:
Specify a valid committed experiment and rerun.
ERROR (TBM-071): Unable to find an uncommitted experiment string

EXPLANATION:
The uncommitted experiment was not found in the TBDbin data.
USER RESPONSE:
Specify a valid uncommitted experiment and rerun.
INFO (TBM-072): The keyword string takes the value string

EXPLANATION:
This message lists all keywords and their values for the current invocation of the
command.
USER RESPONSE:
WARNING (TBM-074): Could not find a Scan_Unload and Scan_Load pair in the
specified testrange.
EXPLANATION:
One Scan_Unload of a sequence and Scan_Load of the immediate next sequence is
required to calculate the switching activity. The specified testrange does not include
these.
USER RESPONSE:

Specify a valid testrange and rerun.
WARNING (TBM-075): No valid test sequences found in the specified experiment.

EXPLANATION:
The program could not find valid test sequences in the TBDBIN for the specified
experiment.
USER RESPONSE:
Check if ATPG has generated valid test patterns. Specify a valid experiment and rerun.
ERROR (TBM-076): The input experiment is created with

createinternalscanload=no. Resimulate the experiment with
createinternalscanload=yes.
EXPLANATION:
The program did not detect an Internal_Scan_Load event in the TBDbin.
USER RESPONSE:
Resimulate the experiment with createinternalscanload=yes and then rerun
write_toggle_gram.
INFO (TBM-077): Processed number sequences.

EXPLANATION:
This message states the current number of sequences for which toggle activity has been
calculated.
USER RESPONSE:
INFO (TBM-078): The design in the current testmode has number controllable scan chains
and number observable scan chains.
EXPLANATION:
The message states the number of scan chains that can be stimulated and the number
of scan chains that can be measured.
USER RESPONSE:

ERROR (TBM-079): Error in weight specification in weight table file at line number.
Unexpected character number
EXPLANATION:
The weight table contains an invalid weight specification. A valid weight specification
such as 10,15,20 and so on is expected. Only zero or any positive integer are allowed.
USER RESPONSE:
Specify a valid weight specification number and then rerun.
ERROR (TBM-080): Error in weight specification in weight table file at line number.
EXPLANATION:
The weight table file contains an invalidly specified name. The name must be quoted.
USER RESPONSE:
Correct the name and rerun.
INFO (TBM-081): Reading region file filename

EXPLANATION:
The region file is read and the flops or all flops under the block will only be accounted for
calculating toggles.
USER RESPONSE:
INFO (TBM-082): Completed reading region file filename

EXPLANATION:
The program has completed reading the region file.
USER RESPONSE:
ERROR (TBM-083): Module name specification error in region file at line number.
EXPLANATION:
The region file contains an invalidly specified module name. The name must be quoted.
USER RESPONSE:

Correct the module name and rerun.
ERROR (TBM-084): Error in generating Tester Cycle Information file string from
write_vectors.
EXPLANATION:
The write_toggle_gram command runs write_vectors as a sub-process to generate
tester cycle information. An error has occurred during the write_vectors phase that
prevents generation of the Test Cycle Information file.
USER RESPONSE:
Run write_vectors separately, determine and correct problems, and then rerun
write_toggle_gram.
WARNING (TBM-085): Unexpected clock toggle at event string for clock string. The
capture toggles might be incorrect for this sequence.
EXPLANATION:
The write_toggle_gram command currently supports capture toggle calculation for
only one capture pulse.
USER RESPONSE:
Either ignore the capture toggle information or generate test vectors with a single capture
cycle and then rerun write_toggle_gram.
ERROR (TBM-086): No scannable flops found in the region(s) specified in the region file.
Ensure the region file contains at least one scannable flop and then rerun
write_toggle_gram.
EXPLANATION:
No scannable flip-flops were detected in the regions for which the toggle must be
calculated. Either the modules(s) specified in the region file do not exist or region file
does not contain any scannable flops.
USER RESPONSE:
Ensure that specified modules in the region file contain at least one scannable flop, and
then rerun write_toggle_gram.
ERROR (TBM-087): Unable to identify spreader network in the current testmode.

EXPLANATION:

The number of observable scan chains must be greater than the number of controllable
scan chains.
USER RESPONSE:
Check the scan chains configurations, correct where required, and rerun
write_toggle_gram.
INFO (TBM-088): The total number of sequences to be analysed for scan is number and
for capture is number.
EXPLANATION:
This message gives information about the number of scan-load and scan-unload
sequence pairs to be analyzed for calculating toggle count for scan and the number of
test sequences having capture pulse events for analyzing toggle activity for capture.
USER RESPONSE:
No response is required
WARNING (TBM-089): The expected time to complete the run is number hr number mins.
EXPLANATION:
The message states a time estimate for the current execution to complete. The
calculation is based on the number of sequences to analyze and the time it takes to
analyze each sequence.
USER RESPONSE:
No response is required if the estimated time is acceptable. If the estimated run time is
unacceptable, split the runs into multiple runs with smaller numbers of sequences (using
the testrange keyword) to analyze and submit the runs on different machines.
INFO (TBM-090): the time for design load and data structure initialization is number
seconds.
EXPLANATION:
The message states the total time in seconds used to load the design and initialize data
structures.
USER RESPONSE:
ERROR (TBM-091): Unable to create the template files for VoltageStorm. Ensure
permissions are properly set to create these files and then rerun write_toggle_gram.

EXPLANATION:
The application could not create the files run_vstorm2, powermeter_command.tcl,
and vstorm2_command.tcl. These files are required to run the power flow using
VoltageStorm.
USER RESPONSE:
Ensure permissions are properly set to create these files and then rerun
write_toggle_gram.
ERROR (TBM-092): Unable to create the specified TCF file tcf_file for string.
Ensure the path is correctly specified or ensure sufficient permissions are in place.
EXPLANATION:
The application could not create the specified toggle count file. Either the specified path
does not exist or you do not have sufficient permissions to create the file.
USER RESPONSE:
Ensure the specified path is correct and that there is sufficient permission to create the
file and then rerun write_toggle_gram.
INFO (TBM-093): Writing VoltageStorm file file_name.

EXPLANATION:
The program is writing the script for VolatageStorm to the referenced file name.
USER RESPONSE:
INFO (TBM-094): Number of scan load events for sequencestring = number.

Scan_Load event id string shall be used for scan toggle computation and event id
string will be used for capture toggle computation.
EXPLANATION:
The write_toggle_gram command does toggle calculation for one pair of
Scan_Load and Scan_Unload events. The Scan_Load from one sequence is
overlapped with the Scan_Unload from the previous sequence for scan shift
computation.
If there are multiple Scan_Load events in the same sequence, the first Scan_Load
event in that sequence is overlapped with the Scan_Unload from the previous
sequence for scan shift toggle computation. For capture toggle computation, the
Scan_Load event just before the and earlier Scan_UnLoad events is used.

USER RESPONSE:
ERROR (TBM-095): No scan chains that are both observable and controllable are detected
in the current test mode.
EXPLANATION:
The calculation of scan chain toggle information requires Tscan chains that are both
observable and controllable.
USER RESPONSE:
Ensure the test mode includes scan chains that are both observable and controllable,
rerun ATPG, and then rerun write_toggle_gram.
ERROR (TBM-096): Encountered simulator errors while simulating sequences having

multiple capture pulses. Review the previous warning/error messages and take appropriate
action
EXPLANATION:
The write_toggle_gram command runs High-Speed Scan Based simulation to detect
internal state of flops, at each capture pulse. This is done for those test sequences that
have more than one capture pulse.
While simulating the multiple capture pulses, High-Speed Scan Based simulation
encountered problems and may have generated some warning or error messages. This
can cause the capture cycle reports to be empty/incorrect. The scan cycle report is not
affected by this message.
USER RESPONSE:
Correct the errors identified in the previous messages and then rerun
write_toggle_gram.
INFO (TBM-097): No scan_unload event found in test sequence number number at

odometer string. This sequence will be ignored for computing the scan toggle.
EXPLANATION:
The write_toggle_gram command calculates scan toggle for each pair of scan_load
and scan_unload events. The scan_load from one sequence is overlapped with the
scan_unload from the previous sequence for scan shift computation. This message
implies there is no scan_unload event in the reported test sequence. This sequence will
be ignored for scan toggle computation. The capture toggle computation, for this test
sequence will still be reported.

USER RESPONSE:
ERROR (TBM-098): The tcfscope=string specification has an invalid value. The

tcfscope keyword accepts a comma separated list of the values capture, chain,
init, and shift.
EXPLANATION:
The tcfscope keyword requires a list of comma separated values from capture,
chain, init, and shift, as shown in the following examples:
tcfscope=capture
tcfscope=shift,capture
tcfscope=chain,capture,init,shift
For more information on this keyword, type write_toggle_gram help on command
line and then type tcfscope.
USER RESPONSE:
Correct the tcfscope specification and rerun write_toggle_gram.
WARNING (TBM-099): Test mode power toggle level has exceeded the threshold value of
30%, which can affect the signal integrity at the tester.
EXPLANATION:
The toggle activity caused by the current set of test vectors is more than the threshold
value.
The threshold is set at 30% switching in any capture or scan cycle. This value depends
upon many factors and may vary from design to design. The excessive toggle activity can
result in power issues on the tester.
USER RESPONSE:
Rerun the atpg with maxscanswitching and maxcaptureswitching keywords set
to an appropriate value. Run the write_toggle_gram command under an advanced
license to get the exact toggle information for scan and capture and which set of test
vectors are causing it. Refer to Encounter Test: Flows for more details on how to
produce low power vectors and do analysis with the write_toggle_gram command.
WARNING (TBM-100): Advanced license for running write_toggle_gram is not

available. Only a summary report will be produced.

EXPLANATION:
The write_toggle_gram command calculates the switching activity caused by the
test vectors for both scan and capture cycles. It provides both the peak and average
switching percentage and generates various toggle reports for test sequence, scan
cycle, capture cycle and flop switching. These detailed toggle reports are available with
an advanced license. With the basic license, this command only generates the basic
summary report for the switching activity.
USER RESPONSE:
Contact Cadence customer support to obtain the advanced license which will enable you
to extract detailed switching information and reports.
WARNING (TBM-102): Unsupported test section code number type string at odometer
string. This test section will be ignored for toggle calculations.
EXPLANATION:
Write_Toggle_Gram currently only supports toggle calculations for test section type
'scan', 'logic' and 'path'.
USER RESPONSE:
Contact Cadence customer support (see Contacting Customer Service on page 23), in
case you need switching activity reports for any other test section types.
WARNING (TBM-103): No scan_load event found in test sequence number=number at

odometer=string. This sequence will be ignored for overlapping scan in the scan toggle
computation.
EXPLANATION:
The write_toggle_gram command does toggle calculation for one pair of
scan_load and scan_unload events. The scan_load from one sequence is
overlapped with the scan_unload from the previous sequence for scan shift toggle
computation. This message implies there is no scan_load/internal_scan_load
event in the reported test sequence. This sequence will be ignored only for overlapping
scan during scan toggle computation. The capture toggle computation, for this test
sequence will still be reported if it contains capture pulse.
USER RESPONSE:
Check if atpg was run with createinternalscanload=no. In this case rerun atpg
with this option set to yes.
WARNING (TBM-104): The value specified with keyword string will be ignored. This
keyword is not applicable for the current tcfscope=string.

EXPLANATION:
The keyword specified is not applicable for generating the toggle count file for the
specified tcfscope. Use tcfperiodshift, tcfperiodcapture, tcfperiodinit,
or tcfperiodchain to specify the tcfperiod for tcfscope shift, capture, init and
chain respectively.
USER RESPONSE:
Use the appropriate keyword for the specified tcfscope and rerun
write_toggle_gram command.
WARNING (TBM-105): No capture pulses found in the specified test range. The capture
toggle reports will be empty.
EXPLNATION:
write_toggle_gram reports capture toggle for each pulse and stim clock event during
capture phase. There are no capture pulses found in the current processing range of test
vectors. The capture toggle reports will be empty.
USER RESPONSE:
Check if the atpg generated any capture pulse events. In case the tests are designed
such that no capture pulse events are needed, then this warning can be ignored.
WARNING (TBM-106): The current testmode type is assumed scan.

write_toggle_gram does not support generation of tcf file for this test mode.
EXPLANATION:
Write_Toggle_Gram currently does not support generation of tcf files for assumed
scan type testmodes.
USER RESPONSE:
Contact Cadence customer support (see Contacting Customer Service on page 23), if
you need the tcf file generation for this test mode.
WARNING (TBM-107): Scannable latch latchname is not reachable from any output pin
on cell instance instname. Toggle activity at this latch will not be written to the TCF file.
EXPLANATION:
The write_toggle_gram command will trace back from the output pins of a library cell
instance to the measure (RML) latch contained within the cell. This is done when
generating TCF files, so that toggle activity at the latch can be reported at the output pin
of the library cell (after accounting for inversions along the path). In this case the

command could not find any output pin that was driven by the scannable latch. This can
happen for any of the following reasons:
This could be an instance of a multi-bit cell, and the latch only goes to other latches
within the cell.
The command is unable to trace through complex logic that is present between the
output pins and the specified latch.
If an RLM block has been incorrectly marked as a technology CELL in the Verilog,
there could be lot of complex logic present between the pin and the latch.
USER RESPONSE:
No response is required if the latch truly does not drive any output pin, either directly or
via simple combinational logic. If this module has been incorrectly marked as a CELL,
one way to fix this is to add the attribute TYPE=RLM on the specified module in the
Verilog. Refer to the Encounter Test: Guide 1: Models for further details. For all other
reasons, contact Cadence customer support to report this problem.
WARNING (TBM-108): Pin pinname on multi-bit cell instance instname is reachable

from multiple RML latches within this block. Toggle activity at latch latchname will not be
written to the TCF file. In the generated TCF file, the toggle rate and probability on this pin
may not be accurate.
EXPLANATION:
Technology cells can contain multiple scan bits within them, resulting in multiple latches
within these cells being marked as measure (RML) latches. Some output pins on these
technology cells could be driven by a combination of multiple RML latches. In such
cases, the TCF file generated by this command will use the toggle activity on one of the
RMLs to report as the toggle activity at the output pin of the cell. For the remaining RMLs
in this cell, this warning is generated.
USER RESPONSE:
Ensure that the specified instance is truly a technology cell and not an RLM that has
been mistakenly represented as a cell. Otherwise, contact customer support (see
Contacting Customer Service on page 23) if you need the command to be enhanced
to support such scenarios more accurately.
WARNING (TBM-109):X values were found in the patterns during toggle calculation. X
values are recorded for unknown latch/flop states, and for any known latch/flop state masked
or blocked due to another unknown latch/flop state. The X values can impact toggle numbers
significantly. The default x-handling policy (if not specified otherwise) is dontcare=random.
EXPLANATION:

Measure events may record values of X

If the state of a flop/latch is unknown (for example, due to unmodeled logic or a
timing constraint), The default policy is to treat X's toggle 50 percent of times
(random) in write_toggle_gram. write_toggle_gram uses the dontcare
keyword to determine the toggle due to X value in the pattern:
If dontcare=pessimistic, each X value is treated as a toggle in that cycle.
If dontcare=optimistic, no toggle is accounted for any of the X values.
If dontcare=random, 50% of X values are treated as toggle and rest 50% are
treated as no toggle. By default, dontcare is set as random, which means that
50 percent of X values are treated as toggle.
USER RESPONSE:
To use a more pessimistic reporting strategy, specify dontcare=pessimistic. To use
a more optimistic reporting strategy specify dontcare=optimistic.
INFO (TBM-110): Test section type string at odometer string will be ignored for toggle
analysis.
EXPLANATION:
write_toggle_gram currently only supports toggle calculations for test section type
'scan', 'logic' and 'path'. The keyword testsectiontype can be used to do toggle
analysis for only specific test section type(s). The reported test section is not matching
the specified testsectiontype and hence will be ignored for toggle calculations.
USER RESPONSE:
ERROR (TBM-111): The testsectiontype=string specification has an invalid

value.Valid testsectiontype values are a list of comma separated values from:logic, scan, and
path.
EXPLANATION:
The testsectiontype keyword requires a list of comma separated values from 'logic',
'scan', and 'path'. The following are the examples of valid values. Example:
testsectiontype=logic
testsectiontype=logic,scan
testsectiontype=logic,scan,path

For more information on this keyword run the command write_toggle_gram help
and on the help prompt type testsectiontype.
USER RESPONSE:
Correct the testsectiontype specification and rerun write_toggle_gram.
ERROR (TBM-152): Invalid specification for sequencenum=string. Specify a valid test

sequence number or odometer value.
EXPLANATION:
The valid values are either the test sequence number or the test sequence odometer
string, for one test vector that needs to be analyzed. This does not accepts a range of
tests and only one test vector can be specified for doing vector based dynamic power
analysis in EPS.
USER RESPONSE:
Correct the sequencenum parameter and rerun this command.
ERROR (TBM-153): Unable to create the output directory string. Ensure permissions are
properly set to create this directory and then rerun this command.
EXPLANATION:
The application could not create the specified output directory.
USER RESPONSE
Check the file create permissions. Try creating the directory or specify the name for an
existing directory.
ERROR (TBM-154): Either project or testmode is not specified. Provide this information
to proceed.
EXPLANATION:
The application requires the project and testmode information to identify the test
vector set for which analysis is needed.
USER RESPONSE:
Check the project and testmode keywords. Specify a valid value for these and rerun
this command.
ERROR (TBM-155): Either workdir is not specified or is null. Provide this information to
proceed.

EXPLANATION:
The application requires the workdir directory to know the work area for the specified
project.
USER RESPONSE:
Check the workdir keyword. Specify a valid value and rerun this command.
ERROR (TBM-156): Cannot establist path to the specified workdir directory string.
Ensure a valid directory is specified.
EXPLANATION:
The application requires the workdir directory to know the work area for the specified
project. The path to specified workdir directory could not be established.
USER RESPONSE:
Check the file permissions and specify a valid path.
ERROR (TBM-157): Keyword sequencenum is not specified. This keyword is required for
generating scripts for vector based power analysis
EXPLANATION:
The sequencenum keyword is needed to specify the testsequence number for which
dynamic vector based power analysis is needed. The vcd based dynamic power analysis
can be done for one test vector at a time.
USER RESPONSE:
Specify the sequencenum keyword and rerun this command.
ERROR (TBM-158): Failed to open file for writing : string. Check the access permissions
and rerun this command.
EXPLANATION:
The application failed to open the specified file for writing. Verify if the access
permissions are set correctly and the user has write permissions in the specified
directory.
USER RESPONSE:
Check the access permissions or specify a valid outputdir keyword and rerun this
command.
INFO (TBM-159): Mode is set to generate scripts for string power analysis string.

EXPLANATION:
This command will generate scripts for the specified mode.
USER RESPONSE:
INFO (TBM-160): Generating script string.

EXPLANATION:
The application is generating the specified script at the mentioned path.
USER RESPONSE:
ERROR (TBM-161): Keyword tcffilename is not specified. This keyword is required for
generating scripts for vector less power analysis.
EXPLANATION:
The tcffilename keyword is needed to specify the path to an existing tcf file for
generating scripts for vector less power analysis.
USER RESPONSE:
Specify the tcffilename keyword and rerun this command.
WARNING (TBM-162): Keyword vcdscancycles is not specified. This will set the scripts
to generate vcd for all the scan cycles for sequence string. The total number of scan cycles
is number.
EXPLANATION:
The vcdscancycles keyword is needed to identify the scan cycle number or range for
which vcd file needs to be generated. This keyword is recommended to use if vector
based analysis for only worst case scan cycle(s) is desired. The scan cycle number for
maximum toggle activity can be identified by running the write_toggle_gram
command.
USER RESPONSE:
Specify the vcdscancycles if generation of vcd for only one or a few scan cycles is
desired. In case you want to generate vcd for all the scan cycles, this warning can be
ignored.

ERROR (TBM-163): Invalid specification for vcdeventodometer=string. Specify a

valid event odometer value for either scan_load or scan_unload event.
EXPLANATION:
The valid values are the event odometer for either scan_load or a scan_unload
event. The vcd will be generated for the overlap scan of scan_load and scan_unload
of which the specified event odometer is one event. This does not accepts a range of
events only one event odometer can be processed at a time. The event odometer for
worst case switching activity can be identified by running the write_toggle_gram
command.
USER RESPONSE:
Correct the vcdeventodometer parameter and rerun this command.
ERROR (TBM-164): Invalid values for vcdscancycles=string. Specify a valid scan

cycle number or range. The valid range for scan cycles is from 1 to number.
EXPLANATION:
The specified scan cycle number(n) or range (n:m) with vcdscancycle keyword is not
within the valid range. The correct scan cycle number for worst case switching activity
can be identified by running the write_toggle_gram command.
USER RESPONSE:
Provide a valid value and rerun this command.
ERROR (TBM-165): Test or odometer string was not found within string.
EXPLANATION:
The test number or odometer value specified does not exist within the test vector file.
USER RESPONSE:
Check the value specified with sequencenum or vcdeventodometer keyword.
Provide a valid test number or odometer value and rerun this command.
ERROR (TBM-166): Event odometer string is not a valid event for generating vcd for
scan.
EXPLANATION:
The valid scan events types are Scan_Load, Internal_Scan_Load, Scan_Unload,
and Diagnostic_Scan_Unload. For generating vcd for scan, event odometer for one
of the above events can be specified.

USER RESPONSE:
Provide a valid event odometer for one of the above events and rerun this command.
ERROR (TBM-167): Event odometer for generating vcd for scan, cannot be identified from
test sequence string.
EXPLANATION:
Vector based analysis for scan requires an event odometer for which vcd needs to be
generated. This can be specified with vcdeventodometer keyword. If this is not
specified this command looks for scan_unload event in the specified test sequence.
This error implies no valid scan_unload event can be identified or this test sequence is
invalid.
USER RESPONSE:
Provide a valid event odometer with vcdeventodometer keyword and rerun this
command.
INFO (TBM-169): Keywords libfiles and innetlist are not specified. Getting this information
from the Encounter Test database
EXPLANATION:
The libfiles and innetlist are provided as keywords on the write_eps
command and specifies the input design source and technology library file names.
These file are needed by NCSIM tool and this information is written in the script
generated for running NCSIM. In case these keywords are not specified, write_eps
tries to get the information which was passed in the designsource and techlib
keywords during the build_model run. This information is then written in the run_ncsim
script. Note that the library files passed to build_model may not be sufficient for
running NCSIM. In this case ou may need to mannauly edit the generated script to add
the libraries which are missing.
USER RESPONSE:
INFO (TBM-170): The keywords libfiles and innetlist are not specified and TEIsourceLibPath
file not found in tbdata. Edit the run_ncsim script to provide the input design source and
technology library files information.
EXPLANATION:
The libfiles and innetlist are provided as keywords on the write_eps
command and specifies the input design source and technology library file names.
These file are needed by NCSIM tool and this information is written in the script gnerated

for running NCSIM. In case these keywords are not specified, write_eps tries to get
the information which was passed in the designsource and techlib keywords during the
build_model run. This information is then written in the run_ncsim script. The
build_model stores this information in the TEIsourceLibPath file and in this case
write_eps is not able to find/read the TEIsourceLibPath file. You will need to manually
edit the generated run_ncsim script to add this information.
USER RESPONSE:
WARNING (TBM-171): Developer keyword tscode is being used. Some of the test section
types are not supported. Allowing a non-supported testsection type can cause unexpected
results, including crashing of the application.
EXPLANATION:
Write_Toggle_Gram currently only supports toggle calculations for test section type
scan, logic and path.
USER RESPONSE:
Contact Cadence customer support (see Contacting Customer Service on page 23), in
case you need switching activity reports for any other test section types.
WARNING (TBM-172): [Severe] The weight number specified for flop string can result
in calculation overflow. Only positive integers below 100 are recommended for assigning
weights.
EXPLANATION:
The weight table contains an invalid weight specification. A valid weight specification
such as 10,15, 20 etc is expected. Only zero or any positive integer number less than
100 is expected. A higher value may cause computation overflow.
USER RESPONSE:
Specify a weight below 100 and rerun.
WARNING (TBM-173): The flop string specified in weight table specification is not a
scan flop. The weight number assigned to it will be ignored.
EXPLANATION:
The weight table contains an invalid specification. write_toggle_gram reports
switching only for the scan flops in the design. A non-scan flop is not processed by this
command, hence any weight assigned to it will be ignored.

USER RESPONSE:
Specify only the scan flops in the weight table specification and rerun the command. This
message can also be ignored safely, if you do not wish to change your weight table
specification.
ERROR(TBM-999) [Internal] Internal Program Error occurred in file: fileName line:

NNN.
msgString
EXPLANATION:
USER RESPONSE:
assistance.


9
TBV - RPCT Boundary Scan Verification
Messages
TBV-210 through TBV-360 on page 203

TBV-410 through TBV-999 on page 217
TBV-210 through TBV-360

WARNING (TBV-210): Receiver data signal net signal for NonTestIO block IOname from
chip pin chip_pin is not controllable.
EXPLANATION:
Rule IN.1: The receiver data signal must be controllable to 0/1.
The receiver data signal, when traced forward from the port of the receiver I/O cell, must
be controllable by a stim latch or test I/O by satisfying IN.1.1 or IN.1.2 below. At least one
of data signals must be connected. The control must not be through. the receivers I/O
cell. All fanouts of the receiver data signal that are connected must satisfy at least one of
these conditions:
IN.1.1
The first multi-input primitive fed by any receiver signal must have its output
controllable to 0 and 1 in this test mode,
IN.1.2
Every multi-input primitive fed by the first multi-input primitive must have its
output controllable to a 0 and 1, AND all inputs to the first multi-input primitive,
except the receiver input, must be observable at an SRL or at a test output.
IN.1.3

TBV - RPCT Boundary Scan Verification Messages
If the first multi-input primitive is a mux primitive, then rule IN.1.1 applies without
the final OR This message indicates that a connected Receiver Data Signal
(RDS) has not met the controllability requirements of IN.1.1, IN.1.2, or IN.1.3.
USER RESPONSE:
Ensure that the design complies with the rule.
WARNING (TBV-211): No receiver data signals are used for NonTestIO block IOname from
chip pin chip_pin.
EXPLANATION:
Rule IN.1: At least one receiver data signal must be connected The receiver data signal,
when traced forward from the port of the receiver I/O cell, must be controllable by a stim
latch or test I/O by satisfying IN.1.1 or IN.1.2 below. At least one of data signals must be
connected. The control must not be through. the receivers I/O cell. All fanouts of the
receiver data signal that are connected must satisfy at least one of these conditions:
IN.1.1
controllable to 0 and 1 in this test mode, or
IN.1.2
IN.1.3
the final
OR
This message indicates that a connected Receiver Data Signal (RDS) (Z,AH,AN) was
connected (re: IN.1).
USER RESPONSE:
WARNING (TBV-212): No receiver data signals were checked for NonTestIO block IOname
from chip pin chip_pin.
EXPLANATION:

Rule IN.1: At least one receiver data signal should be checked.

of data signals must be connected. The control must not be through. the receivers I/O
these conditions:
IN.1.1
controllable to 0 and 1 in this test mode,
OR
IN.1.2
IN.1.3
the final OR
USER RESPONSE:
chip pin chip_pin is gated with net net which is not observable.
EXPLANATION
Rule IN.1: Clause IN.1.2 is violated.
of data signals must be connected. The control must not be through .. the receivers I/O
these conditions:
IN.1.1
controllable to 0 and 1 in this test mode
IN.1.2

IN.1.3
the final
OR
This message indicates that a connected Receiver Data Signal (RDS) has not met the
observability requirements of IN.1.2.
USER RESPONSE
WARNING (TBV-220): Driver data signal net signal for NonTestIO block IOname from chip
pin chip_pin is not observable.
EXPLANATION:
Rule IN.2: The driver data signal must be observable.
The signal feeding the driver data port of a nontest I/O cell must be observable at an SRL
or at a test I/O, by satisfying at least one of these conditions, with buffers allowed in all
connections:
IN.2.1
The driver data port may be fed by a scannable L1 or L2.
IN.2.2
The driver data port may be fed by a net which is observable at a scannable
latch or a test output. A buffer tree may be between the observable net and the
driver data port.
This message indicates that a Driver Data Signal (DDS) has not met the observability
requirements of IN.2.1 or IN.2.2.
USER RESPONSE:
chip pin chip_pin not controlled by unique boundary latch.
EXPLANATION:

Recommendation IN.4 : The receiver data signal should be supplied by a unique

receiver boundary latch (the latch provides the controllability). That is, there should be a
one-to-one correspondence between receiver data signals and receiver boundary
latches.
USER RESPONSE:
pin chip_pin not observed in unique boundary latch.
EXPLANATION:
Recommendation IN.5: The driver data signal should be observable in a unique
boundary latch (the latch provides the observability). That is, there should be a one-to-
one correspondence between driver data signals and driver data boundary latches.
USER RESPONSE:
WARNING (TBV-230): Driver enable signal net signal for NonTestIO block IOname from
chip pin chip_pin is not observable or tied enable.
EXPLANATION:
Rule IN.3: The driver enable signal must be observable or tied to 1
The signal feeding the driver enable port of a nontest I/O cell must satisfy at least one of
the following conditions, with buffers allowed in all connections:
IN.3.1
The enable data port may be fed by an L1, L2, or L3. If an L3, then that L3 must
be feed directly from a scannable L1.
IN.3.2
The enable data port may be fed by a net which is observable at a scannable
driver data port.
IN.3.3
The driver enable port may be tied to 1 (tied enabled).
This message indicates that a Driver Enable Signal (DES) has not met the observability
requirements of IN.3.1 or IN.3.2 AND the DES is not tied enabled.

USER RESPONSE:
chip pin chip_pin can not observe signal net net.
EXPLANATION:
Rule IN.3: The driver enable signal is fed by a 2-input gate where one of the input
signals to the gate is not observable.
The signal feeding the driver enable port of a nontest I/O cell must satisfy at least one of
the following conditions, with buffers allowed in all connections:
IN.3.1
IN.3.2
driver data port.
IN.3.3
USER RESPONSE:
chip pin chip_pin is tied to tie_val.
EXPLANATION:
Rule IN.3: The signal feeding the driver enable port of a nontest I/O cell must satisfy at
least one of the following conditions, with buffers allowed in all connections:
IN.3.1
IN.3.2

driver data port.
IN.3.3
This message indicates that a Driver Enable Signal (DES) is tied to a value other than
one.
USER RESPONSE:
INFO (TBV-237): Driver enable signal net signal for NonTestIO block IOname from chip pin
chip_pin should follow Rule IN.3.2 rather than IN.3.3.
EXPLANATION:
Rule IN.3: The signal feeding the driver enable port of a nontest I/O cell must satisfy at
least one of the following conditions, with buffers allowed in all connections:
IN.3.1
IN.3.2
driver data port.
IN.3.3
USER RESPONSE:
chip pin chip_pin has no observe point.
EXPLANATION:
No observable Latch or TestIO for signal

Rule EX.1: The receiver data signal must be either unconnected or observable (0 and
1) at an SRL or test output, with at least one signal per I/O observable. The observation
may be at the L1 or L2 of the SRL. .. Intervening logic is allowed, as long as the path can
be sensitized by a test PI and/or scannable latch state that also sensitizes the path from
the observe clock PI to the observe latch, if the observation is at an SRL.
This message indicates that a connected Receiver Data Signal (RDS) has not met the
observability requirements.
USER RESPONSE:
chip pin chip_pin has no sensitizable path to any observe point.
EXPLANATION:
No path to any observable Latch or TestIO for signal can be sensitized
Rule EX.1: The receiver data signal must be either unconnected or observable (0 and
1) at an SRL or test output, with at least one signal per I/O observable. The observation
may be at the L1 or L2 of the SRL. .. Intervening logic is allowed, as long as the path can
be sensitized by a test PI and/or scannable latch state that also sensitizes the path from
the observe clock PI to the observe latch, if the observation is at an SRL.
This message indicates that a connected Receiver Data Signal (RDS) has intervening
logic which is not sensitizable.
USER RESPONSE:
chip pin chip_pin shares observe point block observe.
EXPLANATION:
Rule EX.5: A receiver boundary latch or test input cannot be used for observing more
than one receiver data signal.
This message indicates that a boundary latch or test I/O is used for more than one
Receiver Data Signal (RDS).
USER RESPONSE:

WARNING (TBV-313): No receiver data signals are used for NonTestIO block IOname from
Chip pin chip_pin.
EXPLANATION:
This message indicates that EX.1 has been violated. Rule EX.1 requires that at least one
Receiver Data Signal (RDS) per I/O is observable. The NonTestIO block has no receiver
data signals.
USER RESPONSE:
WARNING (TBV-314): No receiver data signals were checked for NonTestIO block IOname
from Chip pin chip_pin.
EXPLANATION:
This message indicates that EX.1 has been violated. Rule EX.1 requires that at least one
Receiver Data Signal (RDS) per I/O is observable. The NonTestIO block has one or more
receiver data signals but none are connected.
USER RESPONSE:
pin chip_pin has no control stims.
EXPLANATION:
No stim Latch or TestIO for signal
Rule EX.2: The driver data signal must be controllable (to 0 and 1) from an L1, L2, L3,
or test input. Intervening logic that is sensitizable is allowed.
This message indicates that a Driver Data Signal (DDS) has not met the controllablity
requirements.
USER RESPONSE:
pin chip_pin has no sensitizable control stim path.
EXPLANATION:
The paths from the stim Latch or TestIO for signal can not be sensitized.

This message indicates that a Driver Data Signal (DDS) has intervening logic which is
not sensitizable.
USER RESPONSE:
pin chip_pin blocked in Test Inhibit state.
EXPLANATION:
The driver data signal must be controllable to 0/1.
This message indicates that a Driver Data Signal (DDS) is TIE/TIed in the Test Inhibit
state.
USER RESPONSE:
chip pin chip_pin has no control stims.
EXPLANATION:
No stim Latch or TestIO for signal.
Rule EX.3: The driver enable signal must be controllable (to 0 and 1) from an L1, L2,
L3, or test input or must be tied enabled (1). Intervening logic that is sensitizable is
allowed.
This message indicates that a Driver Enable Signal (DES) has not met the controllability
requirements.
USER RESPONSE:
chip pin chip_pin has no sensitizable control stim path.
EXPLANATION:

The paths from the stim Latch or TestIO for signal can not be sensitized.
allowed.
This message indicates that a Driver Enable Signal (DES) has intervening logic which is
not sensitizable.
USER RESPONSE:
chip pin chip_pin tied to tie_val.
EXPLANATION:
The enable signal can only be tied if tied to 1 (enabled).
allowed.
This message indicates that a Driver Enable Signal (DES) is TIEed to a state other than
one.
USER RESPONSE:
chip pin chip_pin blocked in Test Inhibit state.
EXPLANATION:
The driver enable signal must be controllable to 0/1.
allowed.
This message indicates that a Driver Enable Signal (DES) is TIed in the Test Inhibit state.
USER RESPONSE:
chip pin chip_pin tied to tie_val by test inhibit (TI).

EXPLANATION:
The enable signal can only be tied to 1 by TIE1 or VDD.
L3, or test input or must be tied enabled (1). .. Intervening logic that is sensitizable is
allowed.
USER RESPONSE:
WARNING (TBV-339): Test I/O pin test_pin used as both func1 and func2 for
NonTestIO block IOname from chip pin chip_pin.
EXPLANATION:
Same test I/O used for multiple functions.
Rule EX.4: The same L1, L2 or test I/O cannot be used as both a receiver boundary
latch and a driver boundary latch or as both a receiver boundary and an enable boundary
latch. The same L1, L2, L3 or test I/O cannot be used a both a driver boundary latch and
an enable boundary latch in a single I/O. This rule applies to the chip as a whole.
This message indicates that a test I/O is shared.
USER RESPONSE:
WARNING (TBV-340): Boundary latch block latch used as both func1 and func2 for
NonTestIO block IOname from chip pin chip_pin.
EXPLANATION:
Same Latch used for multiple functions.
Rule EX.4 : The same L1, L2 or test I/O cannot be used as both a receiver boundary
latch and a driver boundary latch or as both a receiver boundary and an enable boundary
latch. The same L1, L2, L3 or test I/O cannot be used a both a driver boundary latch and
an enable boundary latch in a single I/O.
This message indicates that a boundary latch is shared.
USER RESPONSE:
WARNING (TBV-341): Cannot sensitize any driver/receiver path for NonTestIO block
IOname from chip pin chip_pin.

EXPLANATION:
No static sensitizing state exists for which rules EX.1, EX.2 and EX.3 are satisfied.
Rule EX.6: There must exist a static sensitizing state, which may include test PIs and/
or scannable latches, for which rules 1, 2, and 3 are simultaneously satisfied for all
nontest I/O.
USER RESPONSE:
chip pin chip_pin not observed in SRL.
EXPLANATION:
Recommendation EX.7: In each external test mode, the receiver data signal should
be observable at the L1 or L2 of an SRL.
USER RESPONSE:
WARNING (TBV-352): Driver data signal net signal for NonTestIO block IOname from
chip pin chip_pin not controlled from SRL.
EXPLANATION:
Recommendation EX.8: In each external test mode, the driver data signal should be
controllable from the L1 or L2 of an SRL.
USER RESPONSE:
chip pin chip_pin not controlled from SRL.
EXPLANATION:
Recommendation EX.9: In each external test mode, the driver enable signal should
be controllable from the L1 or L2 of an SRL.
USER RESPONSE:
INFO (TBV-354): All latches for external test are in number scan chains.

EXPLANATION:
The fewer chains the better - loads/unloads and skin models.
Recommendation EX.10: All boundary latches should be in one or more scan chains,
with no non-boundary latches in those chains. This recommendation is useful for doing
MCM interconnect test or other high-level package use of boundary scan.
USER RESPONSE:
WARNING (TBV-355): Driver data signal net signal for NonTestIO block IOname from
chip pin chip_pin shares data stim block stim.
EXPLANATION:
Same data stim is used by multiple driver data signals.
Recommendation EX.11:The same driver boundary latch should not be used for more
than one I/O cell. This recommendation allows a shorted nets test to be performed.
USER RESPONSE:
WARNING (TBV-356): Receiver data signal net signal for TestIO block IOname not
observable.
EXPLANATION:
Recommendation EX.12: Test I/O should also be observable or controllable from
boundary latches.
USER RESPONSE:
WARNING (TBV-357): Driver data signal net signal for TestIO block IOname not
controllable.
EXPLANATION:
boundary latches.
USER RESPONSE:

WARNING (TBV-358): Driver enable signal net signal for TestIO block IOname not
controllable.
EXPLANATION:
boundary latches.
USER RESPONSE:
INFO (TBV-359): Complex logic found between NonTestIO block IOname from chip pin
chip_pin and associated boundary latches.
EXPLANATION:
Recommendation EX.14: The only logic between the nontest I/O cell and the
boundary latch should be a multiplexing function.
USER RESPONSE:
WARNING (TBV-360): Cannot sensitize all NonTestIO driver/receiver paths for shorted nets
test.
EXPLANATION:
Recommendation EX.13: There should exist a static state sensitizable by test I/O in
which rules 1, 2, and 3 are simultaneously met for all nontest I/O.
USER RESPONSE:
TBV-410 through TBV-999

WARNING (TBV-410): Cannot sensitize any I/O Wrap path for NonTestIO block IOname
from chip pin chip_pin while enabled.
EXPLANATION:
Rule WR.2: The path from the driver data boundary latch to the receiver data boundary
latch must be sensitizable for each nontest bidirectional I/O, simultaneously with the
driver being enabled.
USER RESPONSE:

WARNING (TBV-415): NonTestIO block IOname from chip pin chip_pin is not
bidirectional.
EXPLANATION:
Recommendation WR.4: All nontest I/O should be bidirectional I/O.
USER RESPONSE:
WARNING (TBV-416): NonTestIO block IOname from chip pin chip_pin has no
inversion between data latch block release and capture latch block capture.
EXPLANATION:
Recommendation WR.5: If the receiver and driver boundary latches are part of the
same SRL, the data path from the driving latch through the 3-state driver and input buffer
to the capturing latch should include an inversion.
USER RESPONSE:
INFO (TBV-417): All boundary latches are in number scan chains.

EXPLANATION:
Recommendation IOW.7: The fewer chains the better - loads/unloads and skin models
USER RESPONSE:
WARNING (TBV-420): Cannot sensitize all driver latch to receiver latch paths for shorted
nets test.
EXPLANATION:
Recommendation WR.6: All driver data boundary latch to receiver data boundary
latch paths should be able to be simultaneously sensitized.
USER RESPONSE:
INFO (TBV-801): NonTestIO block IOname from chip pin chip_pin is exempt from
checking because reason.

EXPLANATION:
The I/O was not checked due to the given reason.
USER RESPONSE:
Review the reason that the I/O was not checked and determine if it should have been
checked or not.
WARNING (TBV-802): NonTestIO block IOname from chip pin chip_pin will not be
checked because reason.
EXPLANATION:
The I/O was not checked due to the given reason.
USER RESPONSE:
Review the reason that the I/O was not checked and determine if it should have been
checked or not.
INFO (TBV-803): Receiver data signal net signal for NonTestIO block IOname from chip
pin chip_pin not checked because reason.
EXPLANATION:
The signal was not checked due to the given reason.
USER RESPONSE:
Review the reason that the signal was not checked and determine if it should have been
checked or not.
INFO (TBV-804): Driver enable signal net signal for NonTestIO block IOname from chip
pin chip_pin not checked because reason.
EXPLANATION:
USER RESPONSE:
checked or not.
INFO (TBV-805): Driver data signal net signal for NonTestIO block IOname from chip pin
chip_pin not checked because reason.
EXPLANATION:


USER RESPONSE:
checked or not.
INFO (TBV-900): All Checks Passed OK

EXPLANATION:
No severe, error or warning messages were produced.
USER RESPONSE:
INFO (TBV-901): No TBV Checking Messages Printed

EXPLANATION:
Errors or warnings were produced but no messages were printed.
USER RESPONSE:
INFO (TBV-905): The maximum number of msg_sev messages have been issued.
EXPLANATION:
The maximum number of messages for the severity has been issued.
USER RESPONSE:
ERROR (TBV-984): [Input] No stim or capture latches were found in model structure.
EXPLANATION:
No stim or capture latches were found so no checking is done.
USER RESPONSE:
Ensure that the model structure of the chip is correct.
WARNING (TBV-985): chip Pin pin_pame has an unsupported model structure.

EXPLANATION:

The model structure of the pin and cell prevents verification checking.
USER RESPONSE:
Ensure that the model structure of the pin and cell are correct.
ERROR (TBV-986): [Input] RPCT Boundary Scan Verification was unable to find any
chipIOs.
EXPLANATION:
No NonTestIO was found to verify therefore no checking is done.
USER RESPONSE:
Ensure that the model structure of the chip is correct.
INFO (TBV-987): Test Structure Verification was successful for this Test Mode.
EXPLANATION:
Test Structure Verification was successful for this Test Mode.
USER RESPONSE:
WARNING (TBV-988): Test Structure Verification reported arg which may adversely affect
the results of Boundary Scan Verification.
EXPLANATION:
Test Structure Verification errors may adversely affect the results of Boundary Scan
Verification.
USER RESPONSE:
Ensure that Test Structure Verification is correct.
WARNING (TBV-989): Test Structure Verification was not run for this Test Mode.
EXPLANATION:
Test Structure Verification was not run for this Test Mode.
USER RESPONSE:
Run Test Structure Verification for this Test Mode.
WARNING (TBV-990): [Input] RPCT Boundary Scan Verification Command Line Error -
Required keyword keyword must be specified.

EXPLANATION:
The keyword is required and must be specified.
USER RESPONSE:
Ensure that the keyword is specified.
ERROR (TBV-991): Reduced Pin Count Test Boundary Scan Verification Command Line
Error - Unknown value for keyword=value.
EXPLANATION:
An unknown value for a keyword was passed in.
USER RESPONSE:
Ensure that the value for the keyword is correct and rerun.
ERROR (TBV-992): [Input] RPCT Boundary Scan Verification Command Line Syntax Error
- keyword=value.
EXPLANATION:
There is a syntax error in the command line.
USER RESPONSE:
Ensure that the command line syntax is correct.
Refer to "verify_lssd_boundary" in the Encounter Test: Reference: Commands for
additional information.
INFO (TBV-993): RPCT Boundary Scan Verification Command Line - Unknown option or
incorrect value or for keyword keyword=. The option=value option=value will be
ignored.
EXPLANATION:
An unknown option or incorrect value or for a keyword was passed in. The
option=value will be ignored.
USER RESPONSE:
Ensure that the option or value is correct.
Refer to "verify_lssd_boundary" in the Encounter Test: Reference: Commands for

ERROR (TBV-994): [Input] RPCT Boundary Scan Verification Command Line Error - The
file name does not exist.
EXPLANATION:
The file does not exist.
USER RESPONSE:
Ensure that the file exists.
ERROR (TBV-995): [Input] RPCT Boundary Scan Verification Methodology Error - Can not
verify verify with Test Mode Boundary boundary.
EXPLANATION:
Internal checks cannot be done in an external test mode boundary. External checks
cannot be done in an internal test mode boundary.
USER RESPONSE:
Ensure that the test mode boundary and verify option are compatible.
ERROR (TBV-996): [Input] RPCT Boundary Scan Verification Methodology Error - Test
Mode Scan Type must be LSSD or GSD
EXPLANATION:
The Test Mode Scan Type must be LSSD or GSD.
USER RESPONSE:
Rebuild the mode with scan type of LSSD or GSD.
INFO (TBV-997): RPCT Boundary Scan Verification Methodology Error - Another

verification is currently being run.
EXPLANATION:
RPCT Boundary Scan Verification is being run on this chip by another process.
USER RESPONSE:
Wait for the other process to finish.
ERROR (TBV-998): [Input] RPCT Boundary Scan Verification Methodology Error -

verify=verify previously run on this Test Mode use reruntests=y to run again.
EXPLANATION:

The first time RPCT Boundary Scan Verification is run, an audit record is created which
contained the highest severity message of that run. This record should not change if the
application is run again.
USER RESPONSE:
Either rerun the application or not.
ERROR (TBV-999): RPCT Boundary Scan Verification System Error - See previous
messages for problem description.
EXPLANATION:
See previous messages for problem description.
USER RESPONSE:
Fix problem(s) from previous messages.

10
TBX - Extension Language Messages
TBX-001 through TBX-050 on page 225

TBX-001 through TBX-050

ERROR (TBX-001): Project not specified. Specify the project as either an environment
variable, or with the TBX::selectProject method.
EXPLANATION:
No project was specified either as an environment variable, or with the
TBX::selectProject method.
USER RESPONSE:
Specify a project and rerun.
ERROR (TBX-002): Entity not specified. Specify the entity as either an environment variable
or with the TBX::selectEntity method.
EXPLANATION:
No entity was specified either as an environment variable or with the
TBX::selectEntity method.
USER RESPONSE:
Specify an entity and rerun.

ERROR (TBX-003): Unable to open hierModel because the file pointed to by the current
project and entity could not be loaded. Check that both the project and entity are correct, file
permissions allow read access, and sufficient resources are available on the system to allow
the model to be opened.
EXPLANATION:
The "hierModel" and "hierAttributes" files pointed to by the current project and entity
could not be loaded. Either the project is incorrect, the entity is incorrect, file permissions
did not allow the files to be read, or there were not enough resources on the system to
allow the model to be opened. Check for other messages for more details.
USER RESPONSE:
Make sure that the current workdir is specified correctly. If so, check other messages for
more details.
ERROR (TBX-004): [Internal] Unable to obtain the flat model context. Check that the
current project and entity are specified correctly. Check additional messages for more details.
EXPLANATION:
The extension language could not access the flat model for this part.
USER RESPONSE:
Make sure that the current project and entity are specified correctly. If so, check other
messages for more details.
ERROR (TBX-005): Unable to load the flat model. Ensure the current project and entity are
correctly specified. Check additional messages for more details.
EXPLANATION:
The extension language could not access the flat model for this part.
USER RESPONSE:
Make sure that the current project and entity are specified correctly. If so, check other
ERROR (TBX-006): [Internal] Unable to load the hierarchical/flat model correlation data
because insufficient resources were available. Check additional messages for more details.
Check for system resources which might be low, such as paging space.
EXPLANATION:
The flat model was loaded, but there were not enough resources to load the information
that correlates between the flat model and the hierarchical model.

USER RESPONSE:
Check other messages for more details. Check for system resources which might be low,
such as paging space.
ERROR (TBX-007): Testmode not specified. Specify the testmode as either an environment
variable, or with the TBX::selectTestMode method.
EXPLANATION:
No test mode was specified either as an environment variable, or with the
TBX::selectTestMode method.
USER RESPONSE:
Select a test mode and rerun.
ERROR (TBX-008): Unable to load the test mode. Ensure the current project, entity, and
testmode are correctly specified. Check additional messages for more details.
EXPLANATION:
The extension language could not access the test mode.
USER RESPONSE:
Make sure that the current project, entity, and test mode are correctly specified. If so,
check other messages for more details.
ERROR (TBX-009): [Internal] Unable to load the flat model latch methods because
insufficient resources were available. Check additional messages for more details. Check for
system resources which might be low, such as paging space.
EXPLANATION:
that keeps track of how each latch functions in the current mode.
USER RESPONSE:
ERROR (TBX-010): No master fault model file exists because a fault model was never
created for this part or because the fault model is not accessible. Build the fault model and
rerun.
EXPLANATION:

A fault model was never created for this part, or the fault model is not accessible.
USER RESPONSE:
Build the fault model and rerun.
ERROR (TBX-011): Unable to open the global fault model. The fault model could not be read
either because of file permissions or a lack of system resources. Ensure the current project
and entity are correctly specified. Check additional messages for more details.
EXPLANATION:
The fault model exists, but cannot be read either because of file permissions or lack of
system resources.
USER RESPONSE:
Make sure that the current project and entity is specified correctly. If so, check other
ERROR (TBX-012): Failset not specified.

EXPLANATION:
No failset was specified either as an environment variable, or with the
TBX::selectFailSet method.
USER RESPONSE:
Select a failset and rerun.
ERROR (TBX-013): [Internal] Unable to open the failset.

EXPLANATION:
The fail set exists, but cannot be read either because of file permissions or lack of system
resources.
USER RESPONSE:
Make sure that the current project, entity, testmode, experiment, and failset are specified
correctly. If so, check other messages for more details.
ERROR (TBX-014): Experiment not specified.

EXPLANATION:
No experiment was specified either as an environment variable, or with the
TBX::selectExperiment method.

USER RESPONSE:
Select an experiment and rerun.
ERROR (TBX-015): [Internal] Unable to load the TBD repository.

EXPLANATION:
There were not enough resources to load an experiment.
USER RESPONSE:
ERROR (TBX-016): Unable to open the experimental TBDbin file.

EXPLANATION:
Could not find and/or read the pattern data in the experimental TBDbin file.
USER RESPONSE:
Make sure that the current project, entity, testmode, and experiment are specified
ERROR (TBX-017): [Internal] Unable to unload flat model.

EXPLANATION:
The extension language opened a flat model associated with the previous project
specified, but was not able to unload the flat model.
Subsequent invocations of extension language functions may work with the flat model
associated with the previous project.
USER RESPONSE:
WARNING (TBX-018): Child net is cloaked. Tracing incomplete.

EXPLANATION:
The trace fed into a net inside a block which was cloaked; that is, intellectual property for
which details may not be made available. The list of pins returned will not include the pins
fed through this cloaked net.
USER RESPONSE:

Either get an uncloaked version of the model which contains this net, or find a way to
avoid this net, or understand that the results of this function may be incomplete.
WARNING (TBX-019): Sink pin is cloaked. Tracing incomplete.

EXPLANATION:
The trace fed into a sink pin on a net, and the sink pin was inside a block that was
cloaked; that is, intellectual property for which details may not be made available. The list
of pins returned will not include the pins fed through this cloaked pin.
USER RESPONSE:
Either get an uncloaked version of the model which contains this pin, or find a way to
avoid this pin, or understand that the results of this function may be incomplete.
WARNING (TBX-020): Parent net is cloaked. Tracing incomplete.

EXPLANATION:
The trace fed into a net inside a block which was cloaked; that is, intellectual property for
which details may not be made available. The list of pins returned will not include the pins
fed through this cloaked net.
USER RESPONSE:
Either find a way to get an uncloaked version of the model which contains this net, or find
a way to avoid this net, or understand that the results of this function may be incomplete.
WARNING (TBX-021): Source pin is cloaked. Tracing incomplete.

EXPLANATION:
The trace fed into a source pin on a net, and the source pin was inside a block that was
cloaked; that is, intellectual property for which details may not be made available. The list
of pins returned will not include the pins fed through this cloaked pin.
USER RESPONSE:
Either find a way to get an uncloaked version of the model which contains this pin, or find
a way to avoid this pin, or understand that the results of this function may be incomplete.
ERROR (TBX-022): [Internal] Unable to zero flat model usage. Usage is usage.
EXPLANATION:
The extension language opened a flat model and was not able to unload all usages of
the flat model. Subsequent invocations of extension language functions may not work
with the flat model in use.

USER RESPONSE:
Close current extension language session and restart methods.
ERROR (TBX-023): [Internal] Unable to load the flat model with usage usage.
EXPLANATION:
The extension language could not access the flat model for this part. The extension
language was not able to unload all usages of the previous flat model.
USER RESPONSE:
ERROR (TBX-024): [Internal] Unable to load the model correlation data with usage
usage.
EXPLANATION:
that correlates between the flat model and the hierarchical model. The extension
language was not able to unload all usages of the previous flat model.
USER RESPONSE:
ERROR (TBX-025): [Internal] Unable to load the flat model active data methods.
EXPLANATION:
that keeps track of whether each node is active in the current mode.
USER RESPONSE:
WARNING (TBX-026): [Severe] Unable to open the first experiment in the file.
EXPLANATION:
Probably, the TBDBin file contains no data.
USER RESPONSE:
Print the current experiment as a TBDpatt, and analyze the results.

WARNING (TBX-027): [Severe] Unable to open the experiment after

experiment_number.
EXPLANATION:
The TBDBin file does not contain as many experiments as expected.
USER RESPONSE:
Print the current experiment as a TBDpatt, and analyze the results.
ERROR (TBX-028): [Internal] Unable to get to experiment experiment_number.

EXPLANATION:
An error occurred traversing the TBDBin data to get to the specified experiment.
USER RESPONSE:
Print the current experiment as a TBDpatt, and look at the results. Check other
WARNING (TBX-029): [Severe] Unable to open the first test section in experiment
experiment_number.
EXPLANATION:
Probably, the experiment contains no data.
USER RESPONSE:
Print the current experiment as a TBDpatt, and look at the results.
WARNING (TBX-030): [Severe] Unable to open the test section after

experiment_number.test_section_number.
EXPLANATION:
The experiment does not contain as many test sections as expected.
USER RESPONSE:
ERROR (TBX-031): [Internal] Unable to get to test section

EXPLANATION:
An error occurred traversing the TBDBin data to get to the specified test section.

USER RESPONSE:
WARNING (TBX-032): [Severe] Unable to open the first tester loop in test section
EXPLANATION:
Probably, the test section contains no data.
USER RESPONSE:
WARNING (TBX-033): [Severe] Unable to open the tester loop after

experiment_number.test_section_number.test_loop_number.
EXPLANATION:
The test section does not contain as many tester loops as expected.
USER RESPONSE:
ERROR (TBX-034): [Internal] Unable to get to tester loop

EXPLANATION:
An error occurred traversing the TBDBin data to get to the specified tester loop.
USER RESPONSE:
WARNING (TBX-035): [Severe] Unable to open the first test procedure in tester loop
EXPLANATION:
Probably, the tester loop contains no data.
USER RESPONSE:

WARNING (TBX-036): [Severe] Unable to open the test procedure after

experiment_number.test_section_number.test_loop_number.test_pr
ocedure_number.
EXPLANATION:
The tester loop does not contain as many test procedures as expected.
USER RESPONSE:
ERROR (TBX-037): [Internal] Unable to get to test procedure

ocedure_number.
EXPLANATION:
An error occurred traversing the TBDBin data to get to the specified test procedure.
USER RESPONSE:
WARNING (TBX-038): [Severe] Unable to open the first test sequence in test procedure
ocedure_number.
EXPLANATION:
Probably, the test procedure contains no data.
USER RESPONSE:
WARNING (TBX-039): [Severe] Unable to open the test sequence after

ocedure_number.test_sequence_number.
EXPLANATION:
The test procedure does not contain as many test sequences as expected.
USER RESPONSE:

ERROR (TBX-040): [Internal] Unable to get to test sequence

ocedure_number.test_sequence_number
EXPLANATION:
An error occurred traversing the TBDBin data to get to the specified test sequence.
USER RESPONSE:
WARNING (TBX-041): [Severe] Unable to open the first test pattern in test sequence
ocedure_number.test_sequence_number.
EXPLANATION:
Probably, the test sequence contains no data.
USER RESPONSE:
WARNING (TBX-042): [Severe] Unable to open the test pattern after

ocedure_number.test_sequence_number.test_pattern_number.
EXPLANATION:
The test procedure does not contain as many test patterns as expected.
USER RESPONSE:
ERROR (TBX-043): [Internal] Unable to get to test pattern

EXPLANATION:
An error occurred traversing the TBDBin data to get to the specified test pattern.
USER RESPONSE:

WARNING (TBX-044): [Severe] Unable to open the first test event in test pattern
EXPLANATION:
Probably, the test pattern contains no data.
USER RESPONSE:
WARNING (TBX-045): [Severe] Unable to open the test event after

ocedure_number.test_sequence_number.test_pattern_number.test_e
vent_number.
EXPLANATION:
The test procedure does not contain as many test events as expected.
USER RESPONSE:
ERROR (TBX-046): [Internal] Unable to get to test event

ocedure_number.test_sequence_number.test_pattern_number.test_e
vent_number.
EXPLANATION:
An error occurred traversing the TBDBin data to get to the specified test event.
USER RESPONSE:
WARNING (TBX-047): [Severe] Unable to open the test mode fault model.
EXPLANATION:
system resources. The extension language will try to use the global fault status instead.
USER RESPONSE:
Make sure that the current project, entity, and testmode are specified correctly. If so,

WARNING (TBX-048): [Severe] Unable to open the experiment fault model.

EXPLANATION:
system resources. The extension language will try to use the test mode fault status
instead.
USER RESPONSE:
Make sure that the current project, entity, testmode, and experiment are specified
ERROR (TBX-049): Cannot open fault model for updates when experiment specified.
EXPLANATION:
The fault model exists, but cannot be opened for updates while an experiment is
specified.
USER RESPONSE:
Set the experiment to null and rerun.
ERROR (TBX-050): Unable to open the fault model for updates.

EXPLANATION:
The fault model exists, but cannot be opened for update either because of file
permissions or lack of system resources.
USER RESPONSE:

ERROR (TBX-051): Unable to close the fault model after updates.
EXPLANATION:
The fault model exists, but cannot be closed after updates either because of file
permissions or lack of system resources.
USER RESPONSE:

ERROR (TBX-052): Unable to initialize the Encounter Test Graphical User Interface - return
code=gui_return_code
EXPLANATION:
The graphical user interface initialization failed to return a valid return code.
USER RESPONSE:
ERROR (TBX-053): Unable to close the Encounter Test Graphical Interface.

EXPLANATION:
The graphical user interface initialization failed to return a valid return code on a close.
USER RESPONSE:
Check for messages from the TUI component.
ERROR (TBX-054): Graphical Interface does not match current environment

EXPLANATION:
A method attempted to connect to an existing graphical user interface, but the current
environment (PROJECT, ENTITY, VARIATION, ITERATION, and/or TESTMODE) in the
script does not match the environment in the graphical user interface, and the
TBX::selectGraphicsAddress second argument requested that an error be issued
in this case.
USER RESPONSE:
Either invoke TBX::selectProject, etc. to force the script to be working in the same
environment as the graphical user interface, or issue an error message and quit, or
specify a different action in the TBX::selectGraphicsAddress second parameter
ERROR (TBX-055): Unable to connect to existing graphical user interface. Return

code=return code.
EXPLANATION:
A method attempted to connect to an existing graphical user interface, but the underlying
code was unable to connect to that interface.
The return code from the underlying code is specified in the return code field.

USER RESPONSE:
Either execute TBX::selectGraphicsAddress with a null argument to force a new
graphical user interface to start up, or determine why you were unable to connect to the
host address specified in TBX::selectGraphicsAddress.
ERROR (TBX-056): [Internal] Unable to load the scan identification data methods.
EXPLANATION:
that keeps track of whether each node is on the scan path.
USER RESPONSE:
ERROR (TBX-057): Invalid PROJECT: project

EXPLANATION:
The value specified as a project is not a valid directory
USER RESPONSE:
Check either the environment variable PROJECT, or the value of the
TBX::selectProject method to ensure it is a valid directory.
ERROR (TBX-058): Invalid PROJECT/ENTITY : project/entity

EXPLANATION:
The value specified as an entity is not a valid sub-directory of the project.
USER RESPONSE:
Check either the environment variable ENTITY or the value of the
TBX::selectEntity method to ensure it is a valid sub-directory of the current project
ERROR (TBX-059): Invalid TESTMODE: testmode

EXPLANATION:
The value specified as a testmode is not a valid testmode for the current project and
entity.
USER RESPONSE:

Check either the environment variable TESTMODE, or the value of the

TBX::selectTestMode method to ensure it is a valid testmode for the current part.
ERROR (TBX-060): Invalid EXPERIMENT: experiment

EXPLANATION:
The value specified as an experiment is not a valid experiment for the current project,
USER RESPONSE:
Check either the environment variable EXPERIMENT, or the value of the
TBX::selectExperiment method to ensure it is a valid experiment for the current
testmode.
ERROR (TBX-061): Invalid FAILSET: FAILSET name

EXPLANATION:
The value specified as a failset is not a valid failset for the current project, entity,
testmode, and experiment.
USER RESPONSE:
Check either the environment variable FAILSET, or the value of the
TBX::selectFailSet method to ensure it is a valid failset for the current experiment.
ERROR (TBX-062): Invalid DELAYMODEL: delay model name

EXPLANATION:
The value specified as a delay model is not a valid delay model for the current project
and entity.
USER RESPONSE:
Check either the environment variable DELAYMODEL, or the value of the
TBX::selectDelayModel method to ensure it is a valid delay model for the current
part.
ERROR (TBX-063): Invalid HOSTADDRESS: host address

EXPLANATION:
The value specified as a host address is not valid. The host address must consist of four
integers, separated by periods, followed by a colon, followed by a fifth integer, for
example, 9.130.46.7:5501

USER RESPONSE:
Check either the environment variable HOSTADDR, or the value of the
TBX::selectGraphicsAddress method to ensure it is a valid host address.
ERROR (TBX-064): Callout not specified.

EXPLANATION:
No callout was specified either as an environment variable, or with the
TBX::selectCallout method.
USER RESPONSE:
Specify callout and rerun.
ERROR (TBX-065): [Internal] Unable to open the callout.

EXPLANATION:
The callout exists, but cannot be read either because of file permissions or lack of system
resources.
USER RESPONSE:
Verify the current project, entity, , test mode, experiment, failset, and callout are correctly
specified. If the settings are correct, review other messages for more details.
ERROR (TBX-066): Invalid callout sort field callout_sort_field.

EXPLANATION:
The specified field is not a valid field to sort a callout on. Valid fields are fault, score,
contributions, conflicting, tfsp, tpsf, or tfsf.
USER RESPONSE:
Correct the sort field parameter to TBX::calloutSort and rerun.
ERROR (TBX-067): Invalid callout sort direction callout_sort_direction.

EXPLANATION:
The specified sort direction is not valid for callout sorts. The sort direction must be a
string that starts with either a, A, d, or D.
USER RESPONSE:
Correct the sort direction parameter to TBX::calloutSort and rerun.

.ERROR (TBX-068) [Internal]: Unable to load the flat model all methods.
EXPLANATION:
that keeps track of all flat model functions in the current mode.
USER RESPONSE:
Check other messages for more details.
Check for system resources such as paging space, which might be low.
Correct the detected problems and rerun.
ERROR (TBX-069): Failed to obtain a license for product product_name. This method
terminates.
EXPLANATION:
A required license could not be obtained for the indicated product. The method cannot
proceed without the required licenses. Either no license for the specified product is
available, or all licenses for the specfied product are currently in use.
USER RESPONSE:
Ensure the availability of the required license, and rerun.
ERROR (TBX-070): The action of action_parameter has not been registered against
object_type objects because the label, label_parameter, matches a predefined
label for object_type objects.
EXPLANATION:
The Extension language method specified a label that exactly matches the label of an
existing predefined action related to that object_type. Replacing predefined actions
is not supported.
USER RESPONSE:
Invoke the Extension language method using a label parameter that does not match the
predefined action labels associated with that object type.
WARNING (TBX-071): [Severe] Unable to find Net net_name in the physical design.
Error description: error_string. An empty string is returned.
EXPLANATION:

The extension language method TBX::circaNetCommand was invoked with a net

name, but that net could not be found in the physical design. The result of this method
will be an empty string. The error string gives an indication of why the net was not found.
USER RESPONSE:
No response is required. To avoid this error, improve the correlation between the physical
design and the logical design. Use the report_physical_correlation command
to understand what percentage of nets will cause this message.
WARNING (TBX-100): [Severe] Pin index pin_index is cloaked.

EXPLANATION:
The pin specified by the pin_index argument is inside logic which is cloaked; that is,
intellectual property for which details may not be made available. An invalid value will be
returned.
USER RESPONSE:
a way to avoid this pin.
ERROR (TBX-101):Pin index pin_index is invalid.

EXPLANATION:
The pin specified by the pin_index argument could not be found in the current
hierModel. An invalid value will be returned.
USER RESPONSE:
Check to see that pin_index is correct, (a number between zero and the number of
hierarchical pins on the part) and that you are pointing to the correct model.
WARNING (TBX-102): [Severe] Pin pin_name is cloaked.

EXPLANATION:
The pin specified by the pin_name argument is inside logic which is cloaked; that is,
returned.
USER RESPONSE:
WARNING (TBX-103): [Severe] Pin pin_name cannot be found.

EXPLANATION:
The pin specified by the pin_name argument could not be found in the current
USER RESPONSE:
Check to see that pin_name is correct and that you are pointing to the correct model.
WARNING (TBX-104): [Severe] Node node is cloaked.

EXPLANATION:
The node specified by the node argument is inside logic which is cloaked; that is,
returned.
USER RESPONSE:
Either find a way to get an uncloaked version of the model which contains this node, or
find a way to avoid this node.
WARNING (TBX-105): Node node traces into cloaked logic.

EXPLANATION:
One or more nodes encountered in the trace from the argument node are contained in
cloaked logic; that is, intellectual property for which details may not be made available.
The nodes inside the cloaked logic will not be returned, so the returned node list will be
incomplete.
USER RESPONSE:
Either find a way to get an uncloaked version of the model which contains the traced
nodes, find a way to avoid this node, or accept that the returned node list will be
incomplete.
WARNING (TBX-106): [Severe] Pin pin_index traces into cloaked logic.

EXPLANATION:
The pin specified by pin_index argument traces into logic which is cloaked; that is,
returned.
USER RESPONSE:

WARNING (TBX-107): [Severe] Block block_name cannot be found.

EXPLANATION:
The block specified by the block_name argument could not be found in the current
USER RESPONSE:
Check that block_name is correct and that you are pointing to the correct model.
WARNING (TBX-108): [Severe] Block block_name is cloaked.

EXPLANATION:
The block specified by the block_name argument is inside logic which is cloaked; that
is, intellectual property for which details may not be made available. An invalid value will
be returned.
USER RESPONSE:
Either find a way to get an uncloaked version of the model which contains this block, or
find a way to avoid this block.
WARNING (TBX-109): [Severe] Unable to map block block_name to a single flat model
node.
EXPLANATION:
The block name specified in the argument cannot map to a single flat model node,
probably because it is not the name of a block which is an Encounter Test primitive.
USER RESPONSE:
Check the specified block to make sure it has only one output.
ERROR (TBX-110): [Internal] Unable to load highest net name table.

EXPLANATION:
The flat model was loaded, but there were not enough resources to load the table that
describes the highest net name for a node.
USER RESPONSE:
Check for other messages. Check for system resources which might be low, such as
paging space.
ERROR (TBX-111): Controllable register register is invalid.

EXPLANATION:
The register specified by the register argument is out of range for valid controllable
registers. An invalid value will be returned.
USER RESPONSE:
Check to see that the register is correct and within the range of valid controllable register
values.
ERROR (TBX-112): Measure register register is invalid.

EXPLANATION:
The register specified by the register argument is out of range for valid measure
registers. An invalid value will be returned.
USER RESPONSE:
Check to see that register is correct and within the range of valid measure register
values.
WARNING (TBX-113): At least one floating latch is in cloaked logic.

EXPLANATION:
At least one of the latches which should have been included in the floating latch list was
inside cloaked logic; that is, intellectual property for which details may not be made
available. All cloaked latches will not appear in the node list that is returned.
USER RESPONSE:
Either find a way to get an uncloaked version of the model which contains the cloaked
floating latches, or work only with uncloaked floating latches.
WARNING (TBX-114): At least one latch is in cloaked logic.

EXPLANATION:
At least one of the latches which should have been included in the list of latch nodes was
inside cloaked logic; that is, intellectual property for which details may not be made
available. All cloaked latches will not appear in the node list that is returned.
USER RESPONSE:
latches for this bit, or work only with uncloaked floating latches for this bit.
ERROR (TBX-115): Bit bit cannot be found in stim register register.

EXPLANATION:
The bit position specified by the bit argument could not be found in the stim register
specified by the register argument. An invalid value will be returned.
USER RESPONSE:
Check to see that bit is correct (a number between one and the number of bits in this stim
register), and that you are pointing to the correct stim register.
WARNING (TBX-116): [Severe] Requested latch is in cloaked logic.

EXPLANATION:
The latch which should have been the return value for this function was inside cloaked
logic; that is, intellectual property for which details may not be made available. An invalid
value will be returned.
USER RESPONSE:
latch for this bit, or ignore this bit.
ERROR (TBX-117): Bit bit cannot be found in measure register register.

EXPLANATION:
The bit position specified by the bit argument could not be found in the measure register
specified by the register argument. An invalid value will be returned.
USER RESPONSE:
Check to see that bit is correct (a number between one and the number of bits in this
measure register), and that you are pointing to the correct measure register.
WARNING (TBX-118): At least one clock node is in cloaked logic.

EXPLANATION:
This will only happen if the entire design is cloaked.
USER RESPONSE:
Get an uncloaked version of this design.
WARNING (TBX-119): [Severe] Node node is not a primary input.

EXPLANATION:

The node specified as an argument does not correlate to a primary input pin. An invalid
USER RESPONSE:
Check to see if the node is correct.

WARNING (TBX-120): [Severe] Unable to find representative fault for fault index
fault_index.
EXPLANATION:
Most probably, the fault specified as an argument could not be found in the Encounter
Test global fault model. An invalid value will be returned.
USER RESPONSE:
Check the fault index argument.
ERROR (TBX-121): Sequence sequence ID is not correct syntax.

EXPLANATION:
The sequence specified by the sequence ID argument could not be found in the current
experiment because it was not syntactically correct. An invalid value will be returned.
USER RESPONSE:
Check to see that sequence ID is correct (Five integers, separated by four periods).
WARNING (TBX-122): [Severe] Sequence sequence ID cannot be found.

EXPLANATION:
The sequence specified by the sequence ID argument could not be found in the current
experiment because even though it was syntactically correct, there is no such sequence
in the Vectors file. An invalid value will be returned.
USER RESPONSE:
Check to see that sequence ID is correct and is a valid sequence for the current
experiment.
INFO (TBX-123): Sequence sequence ID has no successor.

EXPLANATION:

The sequence specified by the sequence ID is the last sequence in the current
experiment. An invalid value will be returned.
USER RESPONSE:
ERROR (TBX-124): Node node is invalid.

EXPLANATION:
The node specified by the node argument is out of range for the flatModel. An invalid
USER RESPONSE:
Check to see that node is correct and within the range of valid node values.
ERROR (TBX-125): Block index block_index is invalid.

EXPLANATION:
The block specified by the block_index argument could not be found in the current
USER RESPONSE:
Check to see that block_index is correct, (a number between zero and the number
of hierarchical pins on the design) and that you are pointing to the correct model.
ERROR (TBX-126): Net index net_index is invalid.

EXPLANATION:
The net specified by the net_index argument could not be found in the current
USER RESPONSE:
Check to see that net_index is correct, (a number between zero and the number of
hierarchical pins on the design) and that you are pointing to the correct model.
WARNING (TBX-127): [Severe] Net net_name cannot be found.

EXPLANATION:
The net specified by the net_name argument could not be found in the current
USER RESPONSE:

Check to see that net_name is correct and that you are pointing to the correct model.
WARNING (TBX-128): [Severe] Node node is an input pin with no associated block name.
EXPLANATION:
The node specified by the node argument is an input pin and has no associated block
name in the hierModel. An invalid value will be returned.
USER RESPONSE:
Check to see that node reference is correct or use alternate methods to define block
name.
WARNING (TBX-129): [Severe] Node node is an output pin with no associated block
name.
EXPLANATION:
The node specified by the node argument is an output pin and has no associated block
name in the hierModel. An invalid value will be returned.
USER RESPONSE:
name.
WARNING (TBX-130): [Severe] Node node is a net with no associated block name.
EXPLANATION:
The node specified by the node argument is a net and has no associated block in the
USER RESPONSE:
name.
WARNING (TBX-131): [Severe] Block index block_index is cloaked.

EXPLANATION:
The block specified by the block_index argument is inside logic which is cloaked; that
be returned.
USER RESPONSE:

Either find a way to get an uncloaked version of the model which contains this block, or
find a way to avoid this block.
WARNING (TBX-132): [Severe] Net index net_index is cloaked.

EXPLANATION:
The net specified by the net_index argument is inside logic which is cloaked; that is,
returned.
USER RESPONSE:
a way to avoid this net.
WARNING (TBX-133): [Severe] Net net_name is cloaked.

EXPLANATION:
The net specified by the net_name argument is inside logic which is cloaked; that is,
returned.
USER RESPONSE:
ERROR (TBX-134): Fault fault_index is invalid.

EXPLANATION:
The fault index specified by the fault_index argument is out of range for the fault
model. An invalid value will be returned.
USER RESPONSE:
Check to see that fault_index is correct and within the range of valid fault index
values.
INFO (TBX-135): Pin index pin_index has no child net.

EXPLANATION:
The pin specified by the pin_index argument is at a terminating block; that is, no child
net is defined. An invalid value will be returned.
USER RESPONSE:

INFO (TBX-136): Pin index pin_index has no parent net.

EXPLANATION:
The pin specified by the pin_index argument is at the highest level block; that is, no
parent net is defined. An invalid value will be returned.
USER RESPONSE:
INFO (TBX-137): Block index block_index has no child block.

EXPLANATION:
The block specified by the pin_index argument is at the lowest level of hierarchy; that
is, no child block is defined. An invalid value will be returned.
USER RESPONSE:
INFO (TBX-138): Block index block_index has no parent block.

EXPLANATION:
The block specified by the pin_index argument is at the highest level of hierarchy; that
is, no parent block is defined. An invalid value will be returned.
USER RESPONSE:
WARNING (TBX-139): [Severe] Node node is an input pin with no associated block index.
EXPLANATION:
The node specified by the node argument is an input pin and has no associated block
index in the hierModel. An invalid value will be returned.
USER RESPONSE:
index.
WARNING (TBX-140): [Severe] Node node is an output pin with no associated block
index.

EXPLANATION:
The node specified by the node argument is an output pin and has no associated block
index in the hierModel. An invalid value will be returned.
USER RESPONSE:
index.
WARNING (TBX-141): [Severe] Node node is a net with no associated hierarchical index.
EXPLANATION:
The node specified by the node argument is a net and has no associated index in the
USER RESPONSE:
Check to see that node reference is correct or use alternate methods to define
hierarchical index.
WARNING (TBX-143): [Severe] Unable to map block index block_index to a single flat
model node.
EXPLANATION:
The block index specified by the block_index argument cannot map to a single flat
model node, probably because it is not a block index which is a Encounter Test primitive.
An invalid value will be returned.
USER RESPONSE:
Check the specified block to make sure it has only one output.
WARNING (TBX-144): [Severe] Fault index fault_index traces into cloaked logic.
EXPLANATION:
The fault index specified by the fault_index argument traces into cloaked logic; that
be returned.
USER RESPONSE:
Either find a way to get an uncloaked version of the model which contains traceable faults
or find a way to avoid this fault.
WARNING (TBX-145): [Severe] Unable to map node node to a single pin index.

EXPLANATION:
The node specified by the node argument cannot map to a single pin. An invalid value
will be returned.
USER RESPONSE:
Check to see that node reference is correct or use alternate methods to define pin index.
ERROR (TBX-146): Unable to load the fault specification.

EXPLANATION:
The fault model was loaded, but there were not enough resources to load the fault
specification.
USER RESPONSE:
paging space.
WARNING (TBX-147): [Severe] Propagation value for fault fault_index is unknown.

EXPLANATION:
The fault propagation value for the fault index specified by the fault_index argument
can not be determined. An invalid value will be returned.
USER RESPONSE:
Check to see that fault_index is correct and has an expected propagation value.
ERROR (TBX-148): Skewed measure latch at bit bit of register register cannot be
found.
EXPLANATION:
The bit position bit in measure register register does not contain a skewed latch
node. An invalid value will be returned.
USER RESPONSE:
Check to see that bit bit and measure register register are both correct.
ERROR (TBX-149): Unable to update the fault model.

EXPLANATION:
The fault model was loaded, but there were not enough resources to update the fault
model.

USER RESPONSE:
paging space.
ERROR (TBX-150): PRPG register register is invalid.

EXPLANATION:
The register specified by the register argument is out of range for valid PRPG registers.
USER RESPONSE:
Check to see that register is correct and within the range of valid PRPG register values.
ERROR (TBX-151): MISR register register is invalid.

EXPLANATION:
The register specified by the register argument is out of range for valid MISR registers.
USER RESPONSE:
Check to see that register is correct and within the range of valid MISR register values.
ERROR (TBX-152): Failure Index failureIndex is invalid.

EXPLANATION:
The failure index specified by the failIndex argument is out of range for valid failure
data indexes. An invalid value will be returned.
USER RESPONSE:
Check to see that failIndex is correct and within the range of valid failure indexes
(from 1 to numFails)
ERROR (TBX-153): Device Name deviceName is invalid.

EXPLANATION:
The device name specified by the deviceName argument does not exist in the current
failset. An empty list will be returned.
USER RESPONSE:
Check to see that deviceName is correct for the current fail set (must appear in
deviceList).

WARNING (TBX-154): [Severe] Graphics connection action of connectionAction not

recognized.
EXPLANATION:
The optional second parameter to the TBX::selectGraphicsAddress method must
have one of the valid values: spawn, control, or error. The specified value does not
match any of these entries. The default action spawn will be used.
USER RESPONSE:
Change the value of the second parameter of TBX::selectGraphicsAddress
method to any of the mentioned valid values or null and rerun. A value spawn, or no value
specified indicates that if the Graphical User Interface is working on a different part, then
the connect should not occur, but a new Graphical User Interface should be created. A
value of error indicates that if the graphical user interface is working on a different part,
an error should occur.
ERROR (TBX-155): TSV returned a non-zero return code of TSV return code while
attempting to get default values.
EXPLANATION:
Attempt to get TSV defaults failed because TSV returned a bad return code.
USER RESPONSE:
Check for other messages from TSV.
ERROR (TBX-156): Child net is cloaked

EXPLANATION:
A pin index is not cloaked, but the internal child net to which the pin connects is cloaked.
A child net index of -1 will be returned.
USER RESPONSE:
a way to avoid this net, or understand that the results of this function are incomplete.
ERROR (TBX-157): Unable to initialize the simulator.

EXPLANATION:
The extension language could not initialize the Simulator for this design.
USER RESPONSE:

Make sure that the current project and entity are specified correctly. If these parameters
are specified correctly, check other messages for more details.
ERROR (TBX-158): Unrecognized design state: state.

EXPLANATION:
The extension language could not properly interpret the given device under test (design)
state.
USER RESPONSE:
Refer to setCircuitState in the Encounter Test: Reference: Extension
Languagefor a list of acceptable design states:
ERROR (TBX-159): Multiple Scan Sections detected and Scan Section Entry not specified.
EXPLANATION:
This design contains multiple scan sections, that is, different ways in which a single scan-
in or scan-out pin can be used to drive more than one scan register. In this case, the scan
chain must be configured to address one of these scan sections.
USER RESPONSE:
Set Scan Section Entry by calling the extension language method
TBX::selectScanSection. Refer to selectScanSection in the Extension Language
Reference.
ERROR (TBX-160): Unrecognized scan section sequence name:

scan_section_sequence.
EXPLANATION:
A scan section sequence name which matches the name specified as a parameter was
not found.
USER RESPONSE:
Check the TBDseqPatt file produced by report_sequences to find the valid scan
section sequence names. See report_sequences in the Encounter Test: Reference:
Commands for additional information.
WARNING (TBX-161): Three-State contention occurred.

EXPLANATION:
A hard three state contention occurred (i.e. a single net driven by both a one and a zero)
at one or more nets.

USER RESPONSE:
No response is required. Simulation will assume an unknown resolved value for the
net(s). For a list of nodes with three state contention, utilize the method
TBX::getThreeStateContentionNodeList. Refer to
getThreeStateContentionNodeList in the Extension Language Reference.
WARNING (TBX-162): Three-State contention occurred when setting design state

EXPLANATION:
The design state specified in the parameter causes hard three-state contention (i.e. a
single net driven by both a one and a zero) at one or more nets.
USER RESPONSE:
No response is required. Check TSV burnout messages for more detail. Simulation will
assume an unknown resolved value for the net(s) in contention.
ERROR (TBX-163): Invalid argument. Detected NULL for value.

EXPLANATION:
Cannot stimulate design state with a null value.
USER RESPONSE:
Specify a value of 0, 1, Z, X, +, or - as an argument.
WARNING (TBX-164): [INTERNAL] Unable to load the flat model circuit state methods.
EXPLANATION:
The flat model was loaded, but there were not enough resources to load the circuit state
custom protocol methods.
USER RESPONSE:
ERROR (TBX-165): [Internal] No DOTT blocks were found

EXPLANATION:
There were no DOTT blocks (two three-state drivers dotted together) found for this
model. Therefore, the TBX::getThreeStateContention method will always return
an empty list.
USER RESPONSE:

WARNING (TBX-166): [Severe] Unable to add the first experiment in the file.
EXPLANATION:
It is probable the file has write permission problems.
USER RESPONSE:
ERROR (TBX-167): Unable to set experiment name in the experiment.

EXPLANATION:
It is probable the file has write permission problems.
USER RESPONSE:
ERROR (TBX-168): New experiment name must be specified.

EXPLANATION:
Cannot create an new experiment without a new experiment name specified as input.
Refer to createNewExperiment in the Extension Language Reference.
USER RESPONSE:
Ensure that the new experiment name parameter is specified in the invocation of the
TBX::createExperiment method.
ERROR (TBX-169): Failed to register experiment file experiment_name.

EXPLANATION:
The Encounter Test function to register this experiment on globalData failed.
USER RESPONSE:
Check globalData write authority in the part directory.
ERROR (TBX-170): Experiment already exists.

EXPLANATION:
Cannot create a new experiment because experiment already exists for the current
testmode.

USER RESPONSE:
Change testmode or provide a different experiment name.
ERROR (TBX-171): [Internal] Unable to register experiment experiment_name as

dependent on testmode testmode.
EXPLANATION:
The Encounter Test function to register the dependency of the experiment on the test
mode in globalData failed.
USER RESPONSE:
ERROR (TBX-172): Unable to save registration and dependency information.

EXPLANATION:
Any global data changes did not become persistent. Global data will not reflect any
updates.
USER RESPONSE:
Check for possible low system resources, or global data write authority.
ERROR (TBX-173): Unrecognized event type: event type name

EXPLANATION:
TBD/TBX failed to recognize the given event type provided in ASCII format.
USER RESPONSE:
Specify a valid event type as an argument to TBX::createEvent.
ERROR (TBX-174): Incorrect node specification for event type: event type name
EXPLANATION:
The node specified is not a valid node for the event type of the specified event. For
instance, a node which is not a primary input node was specified for a Stim_PI event.
USER RESPONSE:
Ensure that the node specified is valid for the event type for the event.


ERROR (TBX-175): Incorrect net value specification for event type: event type name.
EXPLANATION:
The specified net value is not valid for the event type.
USER RESPONSE:
Refer to createEventFromPatternType in the Encounter Test: Reference:
Extension Languagefor a list of valid net values.
ERROR (TBX-176): Incorrect polarity value specification for event type: event type
name
EXPLANATION:
The specified polarity value is not valid. Valid polarity values include "0","1","-", and "+".
"0" and "-" are equivalent and represent 1-0-1 pulse. "1" and "+" are equivalent and
represent the 0-1-0 pulse.
USER RESPONSE:
Ensure that the create method specifies a valid polarity value as an argument.
ERROR (TBX-177): Invalid number of TBD hierarchical levels specified. Minimum required
is minimum levels.
EXPLANATION:
The minimum number of odometer levels for the extension language "Create" method
was not specified. For example, the minimum odometer levels that must be specified
when creating a tester loop are two, the experiment level and the test section level, for
example, 1.1.
USER RESPONSE:
Refer to "Test Pattern Methods" in the Encounter Test: Reference: Extension
Language for standards and conventions.
ERROR (TBX-178): Failed to remove dependencies on object name.

EXPLANATION:
The named object is registered in global data, but has failed to remove any dependencies
registered on the object.
USER RESPONSE:

Validate that the given named object has registered dependencies. If so, check for global
data write authority.
WARNING (TBX-179):object name is not registered in global data. No global data

updates occurred.
EXPLANATION:
The given named object is not registered in global data. No global data updates were
performed. Register the named object into global data first.
USER RESPONSE:
Use the Encounter Test Extension Language TBX::registerObject method to
register the named object into global data.
ERROR (TBX-180): Failed to register object name in global data.

EXPLANATION:
Global data could not register the given object.
USER RESPONSE:
Validate the given object is not previously registered, or registered with dependencies in
global data. If not, check for global write authority.
ERROR (TBX-181): Failed to unregister object name in global data.

EXPLANATION:
Global data failed to unregister the given name object.
USER RESPONSE:
Validate that the given named object is registered in global data. If so, then check for
global data write authority.
ERROR (TBX-182): Failed to register dependent child on object parent in global data.
EXPLANATION:
Global data failed to register the dependent child object to the parent object with a
specified dependency type of file, statistic, character, or all.
USER RESPONSE:
Validate that the parent and child objects are registered in global data. If so, check for
global data write authority.

ERROR (TBX-183): Failed to unregister dependent child on object parent in global

data.
EXPLANATION:
Global data failed to unregister the child object dependency on the given parent object.
USER RESPONSE:
Validate that the parent and child objects are registered in global data, and that the child
is also registered as a dependency to the parent. If so, check for global data write
authority.
ERROR (TBX-184): Both a child and parent objects must be specified.

EXPLANATION:
The Encounter Test Extension language detected that either the child or parent object
was not specified (NULL).
USER RESPONSE:
Specify a valid parent/child object pair as input.
WARNING (TBX-185): [Severe] Unable to initialize the Distance Model.

EXPLANATION:
There was a problem initializing the Timing Utilitys Distance Model needed for
determining path lengths. This can be caused by an inability to open the Delay Model or
an internal program error.
USER RESPONSE:
Ensure that the Delay Model has been selected and that it exists and can be accessed.
WARNING (TBX-186): [Severe] Illegal net value requested for hold: net Value.
EXPLANATION:
The TBX::holdPinForPathCalc method was called with a net value of something
other than 0, 1, or X. The only three acceptable values for this function are 0, 1, or X.
USER RESPONSE:
Modify the script to ensure that only values of 0, 1, or X are passed to the
TBX::holdPinForPathCalc method.
WARNING (TBX-187): Delay Model name not set. Unable to open Delay Model.

EXPLANATION:
The DELAYMODEL environment variable was not set, but the Delay Model resource was
requested. The Delay Model cannot be opened unless the DELAYMODEL environment
variable is set.
USER RESPONSE:
Set the DELAYMODEL environment variable to name the Delay Model that you would like
to use.
WARNING (TBX-188): [Severe] Failed to open the Delay Model (delay Model Name).
EXPLANATION:
There was an error attempting to open the Delay Model. Refer to the TDM messages
prior to this message to determine the cause.
USER RESPONSE:
Refer to the suggested responses for the TDM messages describing the cause of the
problem. See Chapter 21, TDM - Delay Model Build Messages.
INFO (TBX-189): Using gate delays for path distance calculations.

EXPLANATION:
The DELAYMODEL environment variable was not set, so gate delays will be used in path
distance calculations instead of timing information. This will lead to less accurate longest
path calculations.
USER RESPONSE:
No response is required. If more accurate path length calculations are desired, make
sure that you have a Delay Model and set the DELAYMODEL environment variable to the
name of it.
ERROR (TBX-190): Initialization of clock affiliation tables failed.

EXPLANATION:
The Encounter Test Extension language failed to obtain resources for initializing the
clock affiliation tables.
USER RESPONSE:
ERROR (TBX-191): Bit bit index not found in PRPG register register index.

EXPLANATION:
The bit index specified is either not a positive number or greater than the number of bit
positions for the given PRPG register.
USER RESPONSE:
Check the bit position passed into this method.
ERROR (TBX-192): [Internal] Unable to find latch for bit bit index in PRPG register
register index.
EXPLANATION:
The bit index specified is a valid bit position, but Encounter Test was unable to find the
corresponding Representative Stimmable Latch (RSL).
USER RESPONSE:
ERROR (TBX-193): Bit bit index not found in MISR register register index.
EXPLANATION:
The bit index specified is either not a positive number or greater than the number of bit
positions for the given MISR register.
USER RESPONSE:
Check the bit position passed into this method.
ERROR (TBX-194): [Internal] Unable to find latch for bit bit index in MISR register
register index.
EXPLANATION:
The bit index specified is a valid bit position, but Encounter Test was unable to find the
corresponding Representative Measure Latch (RML).
USER RESPONSE:
ERROR (TBX-195): Invalid experiment odometer level specified: input experiment

odometer
EXPLANATION:

For creation and population of an experiment, the only valid experiment odometer level
value accepted is 1. Attempting to add more than one experiment is not permitted.
USER RESPONSE:
Specify a value of 1 for the experiment odometer level when creating and populating an
experiment.
INFO (TBX-196): parseArgs returned a null result because help was requested.
EXPLANATION:
The TBX::parseArgs method was called with the -h or -H option which activates the
help function. Once the help function is completed, this method returns a null value.
USER RESPONSE:
Specification of the -h or -H option to the TBX::parseArgs method activates Help
function and returns a null value.
ERROR (TBX-197): An invalid or missing argument was discovered by parseArgs.

EXPLANATION:
A missing or invalid argument was detected by parseArgs, such as a non-supported
option specified.
USER RESPONSE:
Validate the arguments specified as input to this method. To force parseArgs to
override this error, specify TB_CONTINUE.
ERROR (TBX-198): [Internal] parseArgs returned an invalid result.

EXPLANATION:
parseArgs failed to parse the specified keyword file given the specified arguments.
USER RESPONSE:
Validate the arguments specified as input to this method. Validate the specified keyword
file exists and is correct. Validate the specified arguments are not a mismatch with the
keyword file. Contact customer support (see Contacting Customer Service on page 23)
for support.
ERROR (TBX-199): [Internal] Port instance attributes not found for block index block
index.
EXPLANATION:

No attribute names were found to be assigned to the pins of block instance(s) for the
given block index in the hierarchical model.
USER RESPONSE:
The attribute names may be assigned to the pins of a block definition for the given block
index. Try using TBX::portPropertyListFromBlockIndex method as an
alternative.
ERROR (TBX-200): [Internal] Port instance attribute value not found for attribute
attribute name of pin index pin index.
EXPLANATION:
An attribute value was not found given the attribute name and pin index for pin
instance(s) in the hierarchical model.
USER RESPONSE:
Validate the attribute name is valid for this pin index, or the attribute name may be
assigned to a pin definition and would alternatively use the
TBX::portPropertyValueFromPinIndexProperty method.
ERROR (TBX-201): [Internal] Port attributes not found for block index block index.
EXPLANATION:
No attribute names were found to be assigned to the pins of the block definition for the
USER RESPONSE:
The attribute names may be assigned to the pins of block instance(s) for the given block
index. Try using TBX::portInstancePropertyListFromBlockIndex method as
an alternative.
ERROR (TBX-202): [Internal] Port attribute value not found for attribute attribute
name of pin index pin index.
EXPLANATION:
An attribute value was not found given the attribute name and pin index for pin definition
in the hierarchical model.
USER RESPONSE:
Validate the attribute name is valid for this pin index, or the attribute name may be
assigned to a pin instance(s) and would alternatively use the
TBX::portInstancePropertyValueFromPinIndexProperty method.

ERROR (TBX-203): [Internal] Block instance attributes not found for block index block
index.
EXPLANATION:
No attribute names were found to be assigned to the block instance(s) for the given block
index in the hierarchical model.
USER RESPONSE:
The attribute names may be assigned to the block definition for the given block index. Try
using TBX::cellPropertyListFromBlockIndex method as an alternative.
ERROR (TBX-204): [Internal] Block instance attribute value not found for attribute
attribute name of block index block index.
EXPLANATION:
An attribute value was not found given the attribute name and block index for block
instance(s) in the hierarchical model.
USER RESPONSE:
Validate the attribute name is valid for this block index, or the attribute name may be
assigned to a block definition and would alternatively use the
TBX::cellPropertyValueFromBlockIndexProperty method.
ERROR (TBX-205): [Internal] Cell attributes not found for block index block index.
EXPLANATION:
No attribute names were found to be assigned to the cell (block definition) for the given
block index in the hierarchical model.
USER RESPONSE:
The attribute names may be assigned to the block instance(s) for the given block index.
Try using TBX::instancePropertyListFromBlockIndex method as an
alternative.
ERROR (TBX-206): [Internal] Cell attribute value not found for attribute attribute
name of block index block index.
EXPLANATION:
An attribute value was not found given the attribute name and block index for the cell
(block definition) in the hierarchical model.
USER RESPONSE:

Validate the attribute name is valid for this block index, or the attribute name may be
assigned to a block instance(s) and would alternatively use the
TBX::instancePropertyValueFromBlockIndexProperty method.
ERROR (TBX-207): [Internal] Net attributes not found for block index block index.
EXPLANATION:
No attribute names were found to be assigned to the nets of the block definition for the
USER RESPONSE:
Validate the block index is valid for a block definition that has net definition attributes
assigned and rerun.
ERROR (TBX-208): [Internal] Net attribute value not found for attribute attribute
name of net index net index.
EXPLANATION:
An attribute value was not found given the attribute name and net index for a net
definition in the hierarchical model.
USER RESPONSE:
Validate the attribute name is valid for this net index.
ERROR (TBX-209): Pin proper pin name is invalid.

EXPLANATION:
Could not find pin from the specified pin name.
USER RESPONSE:
Validate that the specified cell name and pin name is correct, provided to the TBX
method in proper parameter order, and that the correct hierarchical model is used.
ERROR (TBX-210): Missing or invalid argument specified.

EXPLANATION:
An argument for the TBX method is missing or invalid. NULL detected or possibly an
invalid type or value specified.
USER RESPONSE:
Validate that all arguments are specified, NULL is not specified, or validate argument
value or type specification.

WARNING (TBX-211): TDR specified for the current testmode does not contain
PIN_TIMING information.
EXPLANATION:
The TBX::getTDR method requires that the TDR specified by the testmode contains
PIN_TIMING data. The TDR associated with this testmode does not contain
PIN_TIMING data.
USER RESPONSE:
Review which TDR contains the PIN_TIMING information and select the mode that
specifies this TDR.
WARNING (TBX-212): TBX::setDetermineTimeLinearComb the best, nominal, and

worst values to be >= 0 and least parameter to > 0.
EXPLANATION:
The linear combination is used to select what portion of the delays are used. For example
0,1,0 would select the nominal, while .5,.5,0 would select the mid-point between the best
and nominal. At least one of the three values must be > 0.
USER RESPONSE:
Ensure at least one of the three parameters is > 0 and the rest >= 0.
WARNING (TBX-213): No distance could be determined by

TBX::determineLongestTimeTo, TBX::determineLongestSourceTimeTo or
TBX::getSourcesforTimeTo, the nodes are may at a stable state.
EXPLANATION:
No distance to the all the given flat nodes could be determined. This could be because
the nodes are at a stable state.
USER RESPONSE:
Select pins that are not at a stable state.
WARNING (TBX-214): circuit_state is not an allowed circuit state for the determine
time functions.
EXPLANATION:
The determine time circuit has a limited set of states. Read the documentation for the
allowed states.
USER RESPONSE:

Refer to setDetermineTimeCircuitState in the Encounter Test: Reference:

Extension Language for the allowed states and use one of the allowed sets.
WARNING (TBX-215): TBX::getDetermineTimeCmfm or

TBX::getDetermineTimeGoto passed a node that does not feed a cell boundary.
EXPLANATION:
The model used for distance time uses delays that only reside on the upper most cell
boundaries. Nodes that do not connect to a cell boundary are not in the model.
USER RESPONSE:
Ensure the nodes passed into TBX::getDetermineTimeCmfm or
TBX::getDetermineTimeGoto are on cell boundaries or ignore the warning.
WARNING (TBX-216): Linear Combination not yet set.

EXPLANATION:
The selected mode does not set the late mode linear combination (LC) or the linear
combination was not set by the TBX::setDetermineTimeLinearComb method.
USER RESPONSE:
Set the linear combination by calling TBX::setDetermineLinearComb or adding late
mode to the mode information.
WARNING (TBX-217): [Severe] Node node is not a Latch.

EXPLANATION:
The flat node specified to this TBX method must be a latch.
USER RESPONSE:
Validate flat node input is a latch by using the TBX::simFunctionFromNode method.
WARNING (TBX-218): [Severe] Node node is not a Stimmable Latch.

EXPLANATION:
The flat node specified to this TBX method must be a latch that is controllable.
USER RESPONSE:
Use the Extension Language method TBX::nodeListFromStimRegBit for a node
list of valid controllable latches.
WARNING (TBX-219): [Severe] Node node is not a Measure Latch.

EXPLANATION:
The flat node specified to this TBX method must be a latch that is measurable.
USER RESPONSE:
Use the Extension Language method TBX::nodeFromMeasureRegBit for a valid
measure latch flat node.

WARNING (TBX-220): Violation Message Summary List not available.
EXPLANATION:
Encounter Test failed to load the violation message summary list.
USER RESPONSE:
Validate that the appropriate analysis has been performed. Refer to preceding messages
for more detailed information.
WARNING (TBX-221): [Severe] Range violation range is invalid

EXPLANATION:
The range provided as input is either invalid in syntax, or is greater than the total available
violations for the given Text Message identfier.
USER RESPONSE:
Refer to the Encounter Test: Reference: Extension Language for valid range syntax
or utilize the appropriate Extension Language method to retrieve the violation message
list data for determining maximum range.
WARNING (TBX-222): [Severe] Text Message identifier text message identifier

not found.
EXPLANATION:
Encounter Test failed to match the given text message identifier in the violation message
summary list.
USER RESPONSE:
Utilize the appropriate Extension Language method to retrieve the violation message
summary list for determining valid available message identifiers.

ERROR (TBX-223): Node node is not a latch.

EXPLANATION:
The TBX method expects the input node to point to a latch primitive. This method only
works when the input node is a latch.
USER RESPONSE:
Check the input node to ensure it points to a latch primitive.
ERROR (TBX-224): Node node is not a controllable latch.

EXPLANATION:
The invoked TBX method expects the input node to point to a controllable latch primitive.
This method only works when the input node is a controllable latch.
USER RESPONSE:
Check the input node to ensure it points to a controllable latch primitive in the current test
mode.
ERROR (TBX-225): Node node is not a measurable latch.

EXPLANATION:
The invoked TBX method expects the input node to point to a measurable latch primitive.
This method only works when the input node is a measurable latch.
USER RESPONSE:
Check the input node to ensure it points to a measurable latch primitive in the current test
mode.
ERROR (TBX-226): Node node is not a PRPG latch.

EXPLANATION:
The invoked TBX method expects the input node to point to a PRPG latch primitive. This
method only works when the input node is a PRPG latch.
USER RESPONSE:
Check the input node to ensure it points to a PRPG latch primitive in the current test
mode.
ERROR (TBX-227): Node node is not a MISR latch.

EXPLANATION:

The invoked TBX method expects the input node to point to a MISR latch primitive. This
method only works when the input node is a MISR latch.
USER RESPONSE:
Check the input node to ensure it points to a MISR latch primitive in the current test
mode.
INFO (TBX-228): No bidirectional pins found for block index block index.
EXPLANATION:
The invoked TBX method expects the given block index to have input-output pins.
USER RESPONSE:
WARNING (TBX-229): [Severe] The specified Primary Input node index is not a top
level block bidirectional pin.
EXPLANATION:
The invoked TBX method expects the given primary input node to be a Common Input
Output pin (top level block bidirectional pin).
USER RESPONSE:
Utilize the Extension Language method TBX::bidiPinListFromBlockIndex for a list of
bidirectional hier model pin indexes.
WARNING (TBX-230): [Severe] The specified Primary Output node index is not a top
level block bidirectional pin.
EXPLANATION:
The invoked TBX method expects the given PO node to be a Common Input Output pin
(top level block bidirectional pin).
USER RESPONSE:
Utilize the Extension Language method TBX::bidiPinListFromBlockIndex for
a list of bidirectional hier model pin indexes.
WARNING (TBX-231): [Severe] Node node is not a primary output.

EXPLANATION:
The node specified as an argument does not correlate to a primary output pin. An invalid

USER RESPONSE:
WARNING (TBX-232): PROJECT is set to NULL.

EXPLANATION:
The value specified as a project is not a valid directory.
USER RESPONSE:
Encounter Test Extension Language accepts NULL value under the assumption the
script writer wants the PROJECT environment variable unset.
WARNING (TBX-233): ENTITY is set to NULL

EXPLANATION:
The value specified as an entity is not a valid sub-directory of the project specified in the
environment variable PROJECT.
USER RESPONSE:
Encounter Test Extension Language accepts the NULL value under the assumption the
script writer wants the ENTITY environment variable unset.
WARNING (TBX-234): Come from Node from node is not valid for Node to node.
EXPLANATION:
The node specified as a come from node is not valid for the specified "to" node in the
trace.
USER RESPONSE:
Validate the specified arguments are in the correct order.
WARNING (TBX-235): [Severe] Block name block name is not an instance of a primitive.
EXPLANATION:
The specified Block Name is for a hierarchical non-primitive block.
USER RESPONSE:
Specify block name for a primitive. Refer to blockNameFromNode in the Extension
Language Reference.

WARNING (TBX-236): [Severe] Block index block index is not an instance of a

primitive.
EXPLANATION:
The specified block index is for a hierarchical non-primitive block.
USER RESPONSE:
Specify block index for a primitive. Refer to blockIndexFromNode in the Extension
Language Reference.
WARNING (TBX-237): [Severe] Invalid CALLOUT: CALLOUT name

EXPLANATION:
The value specified as a callout is not a valid callout for the current project, entity,
testmode, experiment, and FAILSET.
USER RESPONSE:
Check either the environment variable CALLOUT, or the value of the
TBX::selectCallout method to ensure it is a valid callout for the current experiment.
ERROR (TBX-238): Invalid Pseudo Primary Input (PPI): pseudo primary input
index
EXPLANATION:
The value specified as a Pseudo Primary Input (PPI) index is not valid for the current
project, entity, and testmode.
USER RESPONSE:
Correct the pseudo primary input index and rerun.
ERROR (TBX-239): Invalid node node index for Pseudo Primary Input (PPI) pseudo
primary input index
EXPLANATION:
For the current project, entity, and testmode, the specified cut point is not found for the
given PPI index. There is a mismatch in input parameters.
USER RESPONSE:
To obtain a valid node list from a Pseudo Primary Input entry, refer to the method
TBX::nodeListFromPPI.
ERROR (TBX-240): There are no Pseudo Primary Inputs (PPI) for this testmode.

EXPLANATION:
For the current project, entity, and testmode, no pseudo primary inputs were found.
USER RESPONSE:
Select a different testmode.
ERROR (TBX-241): There is no Pseudo Primary Input (PPI) from the node cut point
node.
EXPLANATION:
The node index specified is not a cut point node for any PPIs found for the current project,
USER RESPONSE:
Refer to the method TBX::clockNodeListFromNode in the Encounter Test:
Reference: Extension Language to obtain a list of valid pseudo primary input entries.
ERROR (TBX-242): Invalid RRFA EXPERIMENT : experiment

EXPLANATION:
The specified experiment does not contain generated random resistant data.
USER RESPONSE:
Run the analyze_random resistance command to create an EXPERIMENT for this
application.
WARNING (TBX-243): [Severe] Invalid RRFA EAI/EOI value.

EXPLANATION:
The value returned from the EAI/EOI request was not a valid value.
USER RESPONSE:
Review the values from the analyze_random_resistance experiment for this part.
ERROR (TBX-244): Unable to get RRFA EAI/EOI data.

EXPLANATION:
The attempt to get RRFA data failed.
USER RESPONSE:
Review the creation of the analyze_random_resistance experiment for this part.

WARNING (TBX-245): [Severe] Input pin position pin position is invalid for flat node
flat node.
EXPLANATION:
The requested pin position is larger than the number of input pins for the node.
USER RESPONSE:
Review the number of inputs for the node.
ERROR (TBX-246): No RRFA EXPERIMENT specified.

EXPLANATION:
An experiment containing random resistant data was not specified.
USER RESPONSE:
Specify the experiment or run analyze_random_resistance to create an
EXPERIMENT for this application.
ERROR (TBX-247): Callout Index callout index is invalid.

EXPLANATION:
The callout index specified by the callout index argument is out of range for valid
callout data indices.
USER RESPONSE:
Verify the value for callout index is correct and within the range of valid callout indexes
(from 1 to numCallouts).
WARNING (TBX-248): [Severe] Callout sort failed.

EXPLANATION:
An error occurred while trying to sort the callout data.
USER RESPONSE:
Check for other errors such as the callout was not open.
WARNING (TBX-249): [Severe] Tester/Simulation Passed/Failed data only available for

callouts from the logic monitor.
EXPLANATION:
One of the following methods:

TBX::tfsfFromCalloutIndex
TBX::tfspFromCalloutIndex
TBX::tpsfFromCalloutIndex
was invoked on a callout that was not created using the logic monitor.
The tfsf, tfsp, or tpsf data is only valid when the logic monitor was used to create the
callout. A value of 0 will be returned.
USER RESPONSE:
Verify the correct monitor was used to create the callout using the
TBX::calloutMonitor method before invoking the methods listed in the
EXPLANATION section.
WARNING (TBX-250): [Severe] True/False Passed/Failed data only available for callouts
from the invariant analysis monitor.
EXPLANATION:
One of the followingmethods:
TBX::tfFromCalloutIndex
TBX::tpFromCalloutIndex
TBX::ffFromCalloutIndex
TBX::fpFromCalloutIndex
was invoked on a callout that was not created using the invariant analysis monitor.
The tf, tp, ff, or fp data is only valid when the invariant analysis monitor was used to create
the callout. A value of 0 will be returned.
USER RESPONSE:
Verify the correct monitor was used to create the callout using the
TBX::calloutMonitor method before invoking the methods listed in the
EXPLANATION section.
ERROR (TBX-251): [Internal] Callout Index callout_index does not point to valid
callout data.
EXPLANATION:
The callout index is a valid number, but there is no data related to the callout associated
with the referenced index.

USER RESPONSE:
ERROR (TBX-252): Argument to TBX::selectFilteredFails was argument but

should be a 0 or 1.
EXPLANATION:
The TBX::selectFilteredFails method takes an argument of 0 to use unfiltered
failures, and 1 to use the subset of failures when creating the callout data. No other
arguments are valid for this method.
USER RESPONSE:
Validate the specification of the arguments to TBX::selectFilteredFails.
ERROR (TBX-253): WorkDir value WORKDIR name is not a valid directory

EXPLANATION:
The argument to TBX::selectWorkDir must be a valid working directory.
USER RESPONSE:
Correct the argument to TBX::selectWorkDir and rerun.
ERROR (TBX-254): WorkDir value WORKDIR name does not point to an Encounter Test
model.
EXPLANATION:
The specified argument to TBX::selectWorkDir should point to an Encounter Test
model.
USER RESPONSE:
Correct the argument to TBX::selectWorkDir and rerun.
ERROR (TBX-255): Search level specification to

TBX::blockAndValueListFromPropertyName,
TBX::pinAndValueListFromPropertyName, or
TBX::netAndValueListFromPropertyName must be primitive, techlib, or top. It
was search level specification.
EXPLANATION:
The second argument to TBX::blockAndValueListFromPropertyName,
TBX::pinAndValueListFromPropertyName, or

TBX::netAndValueListFromPropertyName must be one of primitive,

techlib, or top. None of these arguments were specified.
USER RESPONSE:
Correct the argument to method and rerun.
WARNING (TBX-256): At least one block_pin_or_net with attribute attribute

name is in cloaked logic.
EXPLANATION:
At least one of the blocks, pins, or nets which should have been included in the
TBX::blockAndValueListFromPropertyName,
TBX::netAndValueListFromPropertyName, or
TBX::pinAndValueListFromPropertyName results was inside cloaked logic; that
is, intellectual property for which details may not be made available.
All cloaked blocks, pins, or nets will not appear in the result that is returned.
USER RESPONSE:
Either obtain an uncloaked version of the model which contains the cloaked attributes, or
work only with uncloaked blocks, pins, or nets.
ERROR (TBX-257): Second argument to TBX::templateDetailsFromSequence was

argument but should be eventType, TBDshort, or TBDlong.
EXPLANATION:
The second argument for TBX::templateDetailsFromSequence specifies the
format of the details. The allowed values are eventType, TBDshort, or TBDlong. If no
second argument is specifed, it defaults to eventType.
USER RESPONSE:
Correct the specification of the arguments to
TBX::templateDetailsFromSequence.
ERROR (TBX-258): An incorrect number of arguments was passed to

TBX::templateDetailsFromSequence. The correct number of arguments is either one
or two.
EXPLANATION:
TBX::templateDetailsFromSequence accepts two arguments, the second of
which can be defaulted.
USER RESPONSE:

Correct the specification of the arguments to

TBX::templateDetailsFromSequence.
ERROR (TBX-259): Unable to simulate the unrecognized event event.

EXPLANATION:
The specified extension language method is unable to simulate the referenced event
because the event type is not recognized. Cannot simulate the unrecognized event.
USER RESPONSE:
Correct the event type and rerun the application.
WARNING(TBX-260): Node node number is not a valid clock node.

EXPLANATION:
One or more elements of the clock list argument to TBX::traceForwardFromNode or
TBX::traceBackwardFromNode contains a node index which is not a clock. Tracing
will perform as if the nodes which are not clocks were not specified.
USER RESPONSE:
Modify the argument list of TBX::traceForwardFromNode or
TBX::traceBackwardFromNode from its second argument to contain only clock
nodes as inputs.
WARNING(TBX-261): Unable to determine the predominant clock sequence.

EXPLANATION:
There are no sequences found either in the current experiment, or in the committed test
data if no experiment has been selected. The predominant clock sequence is null, and
since a clock list was not specified, an empty clock list will be used for tracing. In this
case, tracing will stop at all memory elements.
USER RESPONSE:
If the default of the predominant clock sequence should be used to determine the clock
list, select a combination of testmode and/or experiment for which valid patterns exist.
WARNING(TBX-262): Unable to determine the clocks for the sequence sequence

odometer.
EXPLANATION:
No clocks were found for the referenced sequences. Tracing will stop at all memory
elements.

USER RESPONSE:
WARNING (TBX-263): [Severe] The value of the addOrReplace addOrReplace value is

not recognized.
EXPLANATION:
The optional third parameter to the TBX::selectGraphicsAddress method must
have one of the valid values, add or replace. The specified value does not match with
any of these entries. The default value replace will be used.
USER RESPONSE:
Change the value of the third parameter of TBX::selectGraphicsAddress method
to any of the mentioned valid values or null and then rerun.
WARNING (TBX-264): [Severe] The value of the autoRefresh autoRefresh value is

not recognized.
EXPLANATION:
The optional fourth parameter to the TBX::selectGraphicsAddress method must
have one of the valid values: yes or no. The specified value does not match with any of
these entries. The default action "yes" will be used.
USER RESPONSE:
Change the value of the fourth parameter of TBX::selectGraphicsAddress method
to any of the mentioned valid values or null and then rerun.
WARNING (TBX-265): [Severe] Unable to launch the physical design viewer with
parameters oa path: oa_path library: library cell: cell view: view.
EXPLANATION:
Tried to load the physical design sofware with the parameters specified, but physical
design data was not available.
USER RESPONSE:
Run TBX::selectCircaParms with parameters that point to a valid open access
database and rerun.
ERROR (TBX-266): There are no conflicts and hence, there is no first conflicting event
EXPLANATION:

The TBX::firstConflictingEventFromCalloutIndex method was invoked with

a callout index argument that points to a fault callout which has no conflicts. Every failure
was predicted by this fault, and there are no failures predicted by this fault that were not
measured.
USER RESPONSE:
No response required. A null event string is returned by the method.
INFO(TBX-401): Status - status

EXPLANATION:
This message conveys the latest status information available.
USER RESPONSE:
ERROR(TBX-402): Unable to open the journal control file journal_control_file.

The journal will not be updated.
EXPLANATION:
The journal control file specified by the journalcontrolfile keyword could not be
opened for reading.
USER RESPONSE:
Make sure that the journalcontrolfile keyword specifies a file with at least read
access, and rerun the command.
WARNING(TBX-403): Line journal_control_file_line_number in journal

control file journal_control_file is not recognized and will be ignored. Ignored text:
ignored_text
EXPLANATION:
The application could not recognize the indicated line as a valid journal control file
keyword/value pair or as a comment. Therefore, this line will be ignored.
USER RESPONSE:
Modify the journal control file to resolve the identified problem either by making the
indicated line a valid keyword/value pair, or by making it a comment. Then rerun the
update_diagnostic_journal command, if necessary.
ERROR(TBX-404): Journal directory journal_directory does not exist, and could not
be created. No further journal updates will be performed.

EXPLANATION:
The journal directory specified by the journaldirectory keyword in the journal
control file or one of its subdirectories did not previously exist, and could not be created.
USER RESPONSE:
Change the value of the journaldirectory keyword in the journal control file to point
to either an existing directory or a directory whose parent directory exists and you have
the authority to create a subdirectory in the parent directory, and then rerun.
INFO(TBX-405): Created journal directory journal_directory

EXPLANATION:
The diagnostic journal directory or one of its subdirectories did not previously exist, and
was created successfully.
USER RESPONSE:
ERROR(TBX-406): File file_name exists but could not be opened for

read_or_write. No further journal updates will be performed.
EXPLANATION:
While updating a diagnostic journal, the application could not open the indicated file for
the specified purpose.
USER RESPONSE:
Ensure the specified file has the required access and rerun.
ERROR(TBX-407): Report report_name has an unrecognized report style of

report_style. The journal has not been updated.
EXPLANATION:
The indicated report does not have any of the recognized report style values of pareto,
trend, or wafermap in the journal control file.
USER RESPONSE:
Correct the report specification in the journal control file and rerun.
WARNING(TBX-408): Report report_name specified a field field that is not in the

diagnostic database at the current level (part, lot, or wafer) or below. The journal has not been
updated.

EXPLANATION:
The report identified by the report name has a field specification, the value of which does
not match a field name in the diagnostic database either at the current level (part, lot or
wafer) for which the report is being generated, or any lower level in the hierarchy.
USER RESPONSE:
Correct the report specification in the journal control file and rerun.
WARNING(TBX-409): The categorization function file

categorization_function_file specified in the journal control file does not exist or
could not be read. No custom categorization functions are available.
EXPLANATION:
The journal control file contained a categorizationfunction keyword, but the value
of that keyword pointed to a file that does not exist or could not be read. No custom
categorization functions will be available.
USER RESPONSE:
Correct the categorizationfunction keyword in the journal control file or rectify the
permissions for the categorization function file and rerun.
WARNING(TBX-410): The categorization function file

categorization_function_file specified in the journal control file could not be
evaluated. Perl reports the following problem: perl error. No custom categorization
functions are available.
EXPLANATION:
The journal control file contained a categorizationfunction keyword but Perl
encountered an error while evaluating the file pointed to by that keyword. No custom
categorization functions will be available.
USER RESPONSE:
Correct errors in the categorization function file and rerun.
ERROR(TBX-411): Unable to connect to the diagnostic database. Error message from the
connect is: database_error. The journal has not been updated.
EXPLANATION:
The command was unable to establish contact with the diagnostic database associated
with this part, and therefore was unable to continue.

USER RESPONSE:
Ensure that the part is connected to a diagnostic database. If the part is connected, make
sure the database server is running. Otherwise, fix the problem, and rerun the command.
ERROR(TBX-412): Unable to create the .in_process sub-directory of the failure data

directory faildatadirectory. Processing ends.
EXPLANATION:
The indicated sub-directory could not be created in the specified failure data directory.
Hence processing ends.
USER RESPONSE:
Ensure the failure data directory specified in the volume control file exists, the write
permissions are set, and then rerun.
INFO(TBX-413): diagnose_volume_failures complete. Final summary report:

EXPLANATION:
The diagnose_volume_failures command completed processing and is issuing its
final summary report.
USER RESPONSE:
INFO(TBX-414): The highest return code for diagnose_volume_failures is

highest_return_code.
EXPLANATION:
This message indicates the completion of the diagnose_volume_failures
command processing.
USER RESPONSE:
ERROR(TBX-415): Unable to open the volume control file volume_control_file.

Processing ends.
EXPLANATION:
The application could not open the volume control file specified by the
volumecontrolfile keyword for reading. Hence processing ends.
USER RESPONSE:

Ensure the volumecontrolfile keyword specifies a readable file and rerun.
WARNING(TBX-416): Unable to action the include file include_file specified in

volume control file volume_control_file on line line_number. Processing ends.
EXPLANATION:
The indicated action could not be performed on the include file specified in volume
control file. Hence processing ends.
USER RESPONSE:
Ensure the specified include file exists and is readable, then rerun.
WARNING(TBX-418): The sub-command_name sub command in the volume control file

is specified with the keyword keyword. This keyword specification is ignored.
EXPLANATION:
The diagnose_volume_failures command ignores the keyword option specified in
the sub-command_options keyword in the volume control file. The
diagnose_volume_failures command generates the correct value for this keyword
automatically. All other keywords and values specified in the sub-command_options
keyword are respected.
USER RESPONSE:
No response is required. To avoid this message, remove the keyword in the sub-
command_options specification of the volume control file.
WARNING(TBX-419): Keyword keyword is specified with an invalid value of bad_value

in the volume control file volume_control_file line
volume_control_file_line_number. This keyword value will be set to a default
value of default_value.
EXPLANATION:
The diagnose_volume_failures command detected an unsupported value for the
indicated keyword in the volume control file. Processing continues with the default value
for the keyword.
USER RESPONSE:
No response is required if the default value is acceptable. To avoid this value in future
runs, modify the volume control file by removing the offending keyword or specifying a
valid value. If the default is not acceptable, modify the volume control file specifying a
valid keyword value and then rerun.

ERROR(TBX-420): Unable to create the sub-directory sub-directory of the failure data

directory failure_data_directory. Processing ends.
EXPLANATION:
The application could not create the indicated subdirectory in the specified failure data
directory, hence processing ends.
USER RESPONSE:
Ensure the failure data directory specified in the volume control file exists, that write
permissions are set, and then rerun.
WARNING(TBX-421): Unable to find the failing die lot and wafer information in the
failure_data_file file.
EXPLANATION:
The diagnose_volume_failures command failed to find the lot, wafer, wafer x, and
wafer y information in the failure data file. The lot name will default to a unique FAILSET
name. However, the read_failures command will not be able to update the
diagnostics database with the failures in this file.
USER RESPONSE:
Modify the failure data file as needed and then rerun.
ERROR(TBX-422): Unable to create or write to sub-command log directory

logdirectory. Processing ends.
EXPLANATION:
The indicated sub-command log directory is not created or the directory is not writable,
hence processing ends.
USER RESPONSE:
Ensure the sub-command log directory can be created and the write permissions are set
and then rerun.
WARNING(TBX-423): Unable to create the category defined by report report_name. No

graphs or reports generated for report_title.
EXPLANATION:
The named report requires the creation of a category pareto from the diagnostic
database, but the category could not be created. No graph or report will be created or
updated in the diagnostic journal for this report.

USER RESPONSE:
Determine why the category could not be created. Either update the journal control file
parameters so that a report can be created, or remove this report from the diagnostic
journal.
WARNING(TBX-424): Unable to create the trend defined by report report_name because

the secondary category on secondary_category_field has only one bin. No graphs
or reports generated for report_title.
EXPLANATION:
The named report requires the creation of a trend from the diagnostic database, but the
trend could not be created because the secondary category contains only a single bin.
No graph or report will be created or updated in the diagnostic journal for this report.
USER RESPONSE:
Determine why the secondary category has only a single bin. Either update the journal
control file parameters so that a report can be created, or remove this report from the
diagnostic journal.
ERROR(TBX-425): Failset: failset_name already exists. Processing ends.

EXPLANATION:
The failset name generated by the diagnose_volume_failures command already
exists in the Encounter Test data. The failset name is derived from the FAILSET keyword
in the volume control file. The FAILSET value must be specified in such a way that a
unique failset name can be generated.
Duplicate failset names can cause incorrect results, especially when multiple
diagnose_volume_failures commands are running simultaneously. Therefore,
diagnose_volume_failures terminates when it encounters duplicate failset names.
USER RESPONSE:
Modify the value of the FAILSET keyword in the volume control file to ensure that a
unique FAILSET name will be generated, and rerun.
ERROR(TBX-426): Unable to connect to the diagnostic database. Error message from the
connect is: database_error. Processing ends.
EXPLANATION:
The diagnose_volume_failures command was unable to establish a connection
with the diagnostic database server associated with this design, and therefore was
unable to continue.

USER RESPONSE:
Ensure that the design is connected to a diagnostic database by using the User Interface
Setup icon, and then choosing Diagnostic Database. If values are specified, the
design is connected to a server. If the design is connected, ensure the database server
is running. Fix the problem and rerun the command.
WARNING (TBX-427): Unable to access the physical design. Volume analysis on physical
design attributes is not possible.
EXPLANATION:
A volume analysis report which requires physical design information, such as Pareto by
layer, was requested, but the physical design was not accessible. All requests for
physical design attributes will be resolved as "UNCLASSIFIED".
USER RESPONSE:
Start the Encounter Test User interface, and verify correct settings are specified via
Setup-Paths-Physical Design and Setup-Options-Physical Design. When these
are correct, try to start View Physical Design. If any errors occur, additional messages
should appear. Resolve all encountered errors and rerun the command.
INFO (TBX-428): convert_diagdb_to_postgres completed the execution of

internal_step.
EXPLANATION:
This message indicates the completion of a internal step in the
convert_diagdb_to_postgres command.
USER RESPONSE:
INFO (TBX-429): The highest return code for convert_diagdb_to_postgres is

EXPLANATION:
This message indicates the completion of the convert_diagdb_to_postgres
command.
USER RESPONSE:
ERROR (TBX-430): Program failed to do mysqldump. Run terminates.

EXPLANATION:
Program failed to execute mysqldump. The following are possible reasons for the failure:
The MySQL server may not be running.
The design may not be connected to the MySQL server.
Insufficient space in the current directory. Available space should be at least
double the size of the MySQL database directory size.
USER RESPONSE:
Check the stated conditions in the explanation of this message. Correct any problems or
any issues from preceding messages and then rerun.
ERROR (TBX-431): database_error Processing ends.

EXPLANATION:
The message text contains the explanation.
USER RESPONSE:
The message text contains the response. Correct any problems and rerun.
INFO (TBX-432): info_message

EXPLANATION:
The message text contains the explanation.
USER RESPONSE:
WARNING (TBX-433): Unable to find the normalization file file_name. Normalized

pareto will not be created for report.
EXPLANATION:
The specified normalization file could not be found. This could happen due to incorrect
value specified to normalize keyword or the normalization file is not generated prior to
the invocation of update_diagnostic_journal command. When the normalization
file is not found, the program creates a pareto without normalization.
UNCLASSIFIED.
USER RESPONSE:

If you wish to generate normalized paretos, run report_physical_correlation if

the report is related to a physical attribute or run volume analysis to generate the
normalization file and then rerun.
INFO (TBX-434): diagnose_failures subcommand summary report:

EXPLANATION:
diagnose_failures completed processing and is issuing its subcommand summary
report.
USER RESPONSE:
INFO (TBX-435): The highest return code of diagnose_failures is

EXPLANATION:
This message indicates the completion of reported command.
USER RESPONSE:
INFO (TBX-436): Failures specified in importfile_name are imported into Encounter

Test with the FAILSET name failset_name.return_status log_name
EXPLANATION:
This message indicates the completion of importing the fail data in to Encounter Test.
The imported fail data will be stored with a FAILSET name specified in the message.
USER RESPONSE:
If there are any warnings, severe warnings, or errors reported, check the latest log file
(log_read_failures_*) generated at the location specified using the
SUBCOMMAND_LOGS keyword in the precision controlfile. Otherwise, no response is
required
INFO (TBX-437): Scan chain defect is present in device(s)

list_of_scanfail_devices.
EXPLANATION:
The reported device(s) failed the scan chain test. Scan Chain diagnostics will be
performed on the reported device(s).

USER RESPONSE:
INFO (TBX-438): Performed scan diagnostics on device device_name for FAILSET

failset_name.return_status Defect locations will be printed at the end. log_name
EXPLANATION:
This message indicates the completion of scan chain diagnostics on the specified
device. The identified defective flip-flop locations and their corresponding score will be
printed at the end of the run.
USER RESPONSE:
(log_diagnose_failset_scanchain_*) generated at the location specified using
the SUBCOMMAND_LOGS keyword in the precision controlfile. Otherwise, no response is
required
INFO (TBX-439): Logic defect(s) are present in device(s) list_of_devices.

EXPLANATION:
The reported device(s) passed the scan chain test. Logic diagnostics will be performed
on the reported device(s).
USER RESPONSE:
INFO (TBX-440): Performed multiple defect analysis and identified

number_of_independent_defects independent defects.return_status The fail
data for these defects is separated and stored in FAILSET failset_name. log_name
EXPLANATION:
This message indicates the completion of multiple defect analysis. This analysis consists
of identifying the presence of defects that are independent of each other. This analysis
helps in getting good accuracy of diagnostics results.
USER RESPONSE:
(log_prepare_failset_partition_*) generated at the location specified using the
required

INFO (TBX-441): Performed logic diagnostics on device device_name on FAILSET

failset_name.(always_diagnose_full_device is set to yes).return_status Defect
locations will be printed at the end. log_name
EXPLANATION:
This message indicates the completion of logic diagnostics on the specified FAILSET
and device. The identified logic defect locations will be printed at the end.
USER RESPONSE:
(log_diagnose_failset_logic_*) generated at the location specified using the
required.
INFO (TBX-442): Performed logic diagnostics on device

device_name.return_status Defect locations will be printed at the end. log_name
EXPLANATION:
This message indicates the completion of logic diagnostics on the specified FAILSET
and device. The identified logic defect locations will be printed at the end.
USER RESPONSE:
INFO (TBX-443): Deleted FAILSET failset_name.

EXPLANATION:
This message indicates the completion of the FAILSET deletion.
USER RESPONSE:
WARNING (TBX-444): The precisioncontrolfile keyword is not specified. Default

values present in the control file <ET Install Directory>/tools/tb/defaults/
samples/example.pcf located in Encounter Test installation will be used.
EXPLANATION:
The precisioncontrolfile keyword identifies the file that controls the precision diagnostics
flow and reporting options. A documented sample precision control file is located in the
Encounter Test installation at: <ET Install Directory>/tools/tb/defaults/
samples/example.pcf.

In this case, the precisioncontrolfile keyword is left unspecified and hence the program
uses the default options for the precision diagnostics flow. For more information about
the default options, refer to the above example.pcf.
USER RESPONSE:
Use default options for best diagnostic results. To create your own precision control file
with different flow or reporting options, copy the file specified above, make necessary
changes and rerun with this new precision control file name specified to
precisioncontrolfile keyword.
INFO (TBX-445): Performed multiple defect analysis and identified single

defect.return_status
EXPLANATION:
This message indicates the completion of multiple defect analysis. This analysis consists
of identifying the presence of defects that are independent of each other. This analysis
helps in getting good accuracy of diagnostics results. In this case, single defect is
identified.
USER RESPONSE:
(log_prepare_failset_partition_*) created at the location specified using the
required.
ERROR (TBX-446): The specified failset already exists and replace=no is specified.
Processing ends.
EXPLANATION:
None.
USER RESPONSE:
Rerun the program with replace=yes or specify a new name to FAILSET keyword.
ERROR (TBX-447): Unable to open the precision control file

precision_control_file. Processing ends.
EXPLANATION:
The precision control file specified by the precisioncontrolfile keyword could not
be opened for read. Hence processing ends.
USER RESPONSE:

Ensure the precisioncontrolfile keyword specifies a readable file and rerun.
INFO (TBX-448): The output of diagnose_failures is stored in the following log file:
logfile_name
EXPLANATION:
None.
USER RESPONSE:
None.
ERROR (TBX-449): Unable to action the include file include_file specified in

precision control file precision_control_file on line line_number, Processing
ends.
EXPLANATION:
The indicated action could not be performed on the include file specified in precision
control file. Hence processing ends.
USER RESPONSE:
Ensure the specified include file exists and is readable, then rerun.
INFO (TBX-450): Encounter Test Diagnostics Report:

EXPLANATION:
This message indicates the completion of precision diagnostics on the failures specified
in the importfile. This message contains the high level summary of the number of failures
processed, kind of diagnostics performed and the results of diagnostics.
USER RESPONSE:
This report contains the fault candidates identified from the diagnostics of failures
specified in the importfile.
WARNING (TBX-451): Line precision_control_file_line_number in precision

control file precision_control_file is not recognized and will be ignored. Ignored
text: ignored_text
EXPLANATION:
The indicated line was not recognized as a valid precision control file keyword/value pair,
or as a comment. The line is ignored.
USER RESPONSE:

Modify the precision control file to resolve the identified problem either by making it a
valid keyword/value pair, or by making the line a comment. Then rerun
diagnose_failures if necessary.
WARNING (TBX-452): The sub-command_name sub-command in the precision control

file is specified with the keyword keyword. This keyword specification is ignored.
EXPLANATION:
The keyword option specified in the <sub-command>_options keyword in the
precision control file is ignored. The diagnose_failures command generates the correct
value for this keyword automatically. All other keywords and values specified in the
<sub-command>_options keyword are respected.
USER RESPONSE:
No response is required. To avoid this message, remove the keyword in the <sub-
command>_options specification of the precision control file.
WARNING (TBX-453): Keyword keyword is specified with an invalid value of bad_value

in precision control file precision_control_file line
precision_control_file_line_number. This keyword value will be set to a
default value of default_value.
EXPLANATION:
The diagnose_failures command detected an unsupported value for the indicated
keyword in the precision control file. Processing continues with the default value for the
keyword.
USER RESPONSE:
No response is required if the default value is acceptable. This message can be avoided
in future runs by modifying the precision control file by removing the offending keyword
or specifying a valid value. If the default is not acceptable, modify the precision control
file specifying a valid keyword value and then rerun.
WARNING (TBX-454): [Severe] The field field is not present in diagnostic database.
EXPLANATION:
The specified field does not exist in the database and hence the condition specified by
the user will be ignored.
USER RESPONSE:
The message will be succeeded by another message that reports the condition name
and title that has the specified field. Take corrective action and rerun.

WARNING (TBX-455): [Severe] The sub-condition statement sub-condition with in

the condition condition is not as per the required syntax.
EXPLANATION:
The specified sub-condition is not as per the required syntax. The required syntax is
(database_field_name operator "value").
USER RESPONSE:
Correct the specified sub-condition according to the required syntax and rerun.
WARNING (TBX-456): [Severe] The title statement condition is not as per the
required syntax and is ignored.
EXPLANATION:
The specified selection statement is not as per the required syntax and hence it is
ignored. The syntax for writing a selection statement is:
<selection_level>:Condition=<condition_string> Title="<title_name>"
Reports=<report1> <report2> ....
<selection_level> is not of PartSelection or LotSelection or

WaferSelection
<condition_string> syntax is nested AND or OR combition of a sub-condition with
syantax (database_field_name operator "value")
title_name is a unique string that identifies the condition in the journal. If 2 selection
statements with same title are specified, the second statement overwrite the first
statement. <report1> is the title name of the reports to be generated based on the
specified condition.
USER RESPONSE:
Take corrective action and rerun.
WARNING (TBX-457): [Severe] The selection statement with title title and condition
condition is not as per the required syntax and is ignored.
EXPLANATION:
The specified condition is not as per the required syntax and hence it is ignored.
USER RESPONSE:
The message will be preceeded by another message that reports the cause for this
problem. The message text contains the response.

msgseverity(TBX-458): Failure Import Summary for failurefile:

summaryreport End of Failure Import Summary
EXPLANATION:
diagnose_failures executed the read_failures sub-command and printed the
summary report. The number of failures successfully read should always be equal to the
total number of failures specified in the importfile. If the number does not match, some
of the tester failures are not properly imported into Encounter Diagnostics. A 'failed'
failure indicates that the value specified for this failure in the importfile matches the good
machine value present in the test sequences. An ignored failure indicates the presence
of 'Z' value as the tester value. Running diagnostics on this FAILSET will cause incorrect
results to be generated since the failed/ignored failures are not considered by the
diagnostics tool.
USER RESPONSE:
Analyze the failures mentioned in failed/ignored rows and rerun with modified failure data
for accurate diagnostics results.
ERROR (TBX-459): Failures specified in importfile_name could not be imported into

Encounter Test.return_code log_name.
EXPLANATION:
The failures specified in the import file could not be imported in to Encounter Test. Check
the specified logfile and understand the root cause of the problem. If the value of the
$parms{stop_on} specified in the precision control file is Error, then program will
terminate and if the value of $parms{stop_on} is never then program will continue till
the end of the command and sub command(s).
USER RESPONSE:
Take corrective action after going through the errors reported in the specified logfile and
rerun.
ERROR (TBX-460): Failed to perform scan diagnostics on device

device_name.return_code log_name.
EXPLANATION:
Scan chain diagnostics on the specified device could not be performed. Check the
specified logfile and understand the root cause of the problem. If the value of the
USER RESPONSE:

rerun.
ERROR (TBX-461): Failed to perform multiple defect analysis.return_code

log_name.
EXPLANATION:
Failed to complete the multiple defect analysis on independent defects. Check the
specified logfile and understand the root cause of the problem. If the value of the
USER RESPONSE:
rerun.
ERROR (TBX-462): Failed to perform logic diagnostics for device device_name.

(always_diagnose_full_device is set to yes).return_code log_name
EXPLANATION:
Failed to complete the logic diagnostics on the specified device. Check the specified
logfile and understand the root cause of the problem. If the value of the
USER RESPONSE:
rerun.
ERROR (TBX-463): Failed to perform logic diagnostics on device

device_name'.return_code log_name.
EXPLANATION:
Failed to complete the logic diagnostics on the specified device. Check the specified
logfile and understand the root cause of the problem. If the value of the
USER RESPONSE:

rerun.
ERROR (TBX-464): Volume Diagnostic Database server is not running. Processing ends.
EXPLANATION :
To perform volume diagnostics using diagnose_volume_failures, two pre-requisite
steps need to be performed. A volume diagnostic database server needs to be started
using the start_diagdb_server command. Once this is successful, the server needs
to be connected to the part using the setup_diagdb_control command.
diagnose_volume_failures makes a check to insure the presence of diagnostic
database server and its connection to the part directory before running diagnostics jobs
on the failure data files. In this case, this checking has failed and hence the program
could not proceed further.
USER RESPONSE:
Make sure the diagnostic database server is running and is connected to the part and
rerun.
ERROR (TBX-466): Unable to load OPCG statistics.

EXPLANATION:
Unable to load OPCG statistics. Check the design to see for OPCG statistics
USER RESPONSE:
Check to see OPCG in the design and rerun.
ERROR (TBX-467): Invalid Scan Pipe Register Entry.

EXPLANATION:
The scan pipe register entry is invalid and it should be less than or equal to the total
number of pipelines within the design.
USER RESPONSE:
Rerun using valid entry.
WARNING (TBX-468): The volumecontrolfile keyword is not specified. Default values

present in the control file: <ET Install Directory>/tools/tb/defaults/
samples/example.vcf located in Encounter Test installation will be used.
EXPLANATION:

The volumecontrolfile keyword identifies the file that controls the volume diagnostics flow
and reporting options. A sample fully documented file is located in the Encounter Test
installation at: <ET Install Directory>/tools/tb/defaults/samples/
example.vcf. In this case, the volumecontrolfile keyword is left unspecified and hence
the program uses the default options for the volume diagnostics flow. For more
information about the default options, refer to the above example.vcf.
USER RESPONSE:
The default options are recommended for best diagnostic results. However, if you wish
to create your own volume control file with different flow or reporting options, copy the file
specified above, make necessary changes and rerun with this new volume control file
name specified to volumecontrolfile keyword.
INFO (TBX-469):Initial Summary

EXPLANATION:
Informational message indicating the initial status of all the failing files in fail data.
directory
USER RESPONSE:
INFO (TBX-470): Interim report

EXPLANATION:
Informational message indicating the number of fail data files that have been processed
till that point.
USER RESPONSE:
INFO (TBX-471): The status of current individual diagnostic run.

EXPLANATION:
Informational message indicating which fail data file from the fail data directory is
currently being processed and the position of their respective logs.
USER RESPONSE:
WARNING (TBX-473): [Severe] Node node is neither a primary input nor a primary
output.

EXPLANATION:
The node specified as an argument does not correlate to a primary input or output pin.
USER RESPONSE:
WARNING (TBX-474): [Severe] Fault id faultID is not a representative fault index.

EXPLANATION:
The fault id specified as an argument does not correlate to a representative fault index.
USER RESPONSE:
Check to see if the fault id is correct.
WARNING (TBX-475): [Severe] Fault id faultID does not have any reduced fault
associated with it.
EXPLANATION:
The fault id specified as an argument does not have any reduced fault associated with it.
USER RESPONSE:
WARNING (TBX-476): [Severe] Fault id fault_ID does not have any equivalent faults
associated with it.
EXPLANATION:
The fault id specified as an argument does not have any equivalent faults associated with
it. An invalid value will be returned.
USER RESPONSE:
ERROR (TBX-477): Unable to create or write to diagnose_failures log directory

logdirectory. Processing ends.
EXPLANATION:

The indicated diagnose_failures log directory is not created or the directory is not
writable hence processing ends.
USER RESPONSE:
Ensure the specified diagnose_failures log directory can be created and the write
permissions are set and then rerun.
INFO (TBX-480): The output of diagnose_volume_failures is stored in the following

log file:logfile_name
EXPLANATION:
The log file name mentioned in the message, contains the output of
diagnose_volume_failures command.
USER RESPONSE:
INFO (TBX-481): The function will not work correctly , execute

TBX::createNewEditableExperiment().
EXPLANATION:
The function requires an editable experiment to work properly, execute
TBX::createNewEditableExperiment() before using this function command.
USER RESPONSE:
Execute TBX::createNewEditableExperiment() to ensure the function works
properly.


11
TCC - Random Pattern Generation
Messages
TCC-001 through TCC-116 on page 307
TCC-001 through TCC-116

INFO (TCC-001): Start of type design compilation for simulation.
EXPLANATION:
The simulator is creating the compiled code file. The compile step may take several
minutes, depending on design size and complexity.
USER RESPONSE:
INFO (TCC-002): Design compilation is complete.

EXPLANATION:
Creation of the compiled code file is complete.
USER RESPONSE:
INFO (TCC-003): Simulation has detected the presence of more than 5 trailing edges clock
choppers chained together. These topologies cannot be simulated with either the compiled
code or interpretive option. The design will be compiled for event driven.
EXPLANATION:
The event driven method is being used per the preceding message text.
USER RESPONSE:

TCC - Random Pattern Generation Messages
No response required
WARNING (TCC-020): [Severe] Cannot set the test mode.

EXPLANATION:
The mode data is not accessible.
USER RESPONSE:
Ensure the mode name is valid, or rebuild the mode. If this does not fix the problem,
WARNING (TCC-034): [Severe] Cannot get storage in file:line (time date).

EXPLANATION:
There is insufficient storage to handle a get storage request.
USER RESPONSE:
Check for possible storage problems and rerun.
WARNING (TCC-035): [Severe] Cannot get storage for an internal table (name size=num
bytes).
EXPLANATION:
There is insufficient storage to handle a get storage request.
USER RESPONSE:
Check for possible storage problems and rerun.
WARNING (TCC-050): [Severe] Unsupported node/SimFunction (nodeid/func)

encountered during compile of a fanout free tree.
EXPLANATION:
Unsupported design logic was encountered preventing the creation of the compiled code
file. Processing terminates.
USER RESPONSE:
ERROR (TCC-083): Error with TSD fault effect detected in TCCfcomp. Processing ends.
EXPLANATION:

An error condition was encountered during processing of a TSD which prevents

processing from continuing. This indicates a problem with the fault model for the mode
being processed.
USER RESPONSE:
If possible, rebuild the fault model for the mode and rerun. If the message still appears,
ERROR (TCC-084): A discrepancy exists between the number of faults expected to be

processed and the actual number of faults being processed. Attempted to load number
type faults when only number were expected.
EXPLANATION:
The fault model indicates there are n faults to process, but during processing, fault n+1
has just been encountered.
USER RESPONSE:
If possible, rebuild the fault model for the mode and rerun. If the message still appears,
ERROR (TCC-090): Run terminating due to error in TCCfl1l2.

EXPLANATION:
This indicates an internal program error.
USER RESPONSE:
WARNING (TCC-100): [Severe] TCCregInit linkage type not recognized.

EXPLANATION:
USER RESPONSE:
WARNING (TCC-101): [Severe] Compiler has run out of assignable registers.

EXPLANATION:
USER RESPONSE:

WARNING (TCC-110): [Severe] Compiled code file is not Readable.

EXPLANATION:
USER RESPONSE:
WARNING (TCC-111): [Severe] Compiled code file is not Writeable.

EXPLANATION:
USER RESPONSE:
WARNING (TCC-112): [Severe] Cannot delete the existing compiled code file.
EXPLANATION:
USER RESPONSE:
WARNING (TCC-113): [Severe] Cannot open the compiled code file.

EXPLANATION:
USER RESPONSE:
WARNING (TCC-114): [Severe] Error from EDAMfcls(fcb,keep) rc=retc

EXPLANATION:
USER RESPONSE:

WARNING (TCC-115): [Severe] Error from EDAMsopn(fcb,sanum)

EXPLANATION:
USER RESPONSE:
WARNING (TCC-116): [Severe] Error from EDAMsput(fcb,addr,offset,size)

rc=retc
EXPLANATION:
USER RESPONSE:


12
TCE- Domain Constraint Messages
TCE-400 through TCE-450 on page 313
TCE-400 through TCE-450

ERROR (TCE-400): Unable to load model or testmode data. command is ending.
EXPLANATION:
The model and testmode data are created by the build_model and build_testmode
commands. Ths command could not load the data. It is either non-existent or the file
permissions do not allow access to the tbdata directory.
USER RESPONSE:
Ensure the file permissions allow access to the tbdata directory and that build_model
and build_testmode have been run.
WARNING (TCE-401): [Severe] When block input and functional clock gates are set for
domain dom1, this domain receives data into state element elem1 from domain dom2 state
element elem2.
EXPLANATION:
When an internal clock domain is programmed to block all inputs from other domains, it
is considered a mistake when data from other domains can in fact be captured into the
domain when the block_inputs and functional clock gate controls are set. The
prepare_domain_constraints command creates constraints that are used by
default during simulation. If they are used, data from other domains will be captured as
an X. If the constraints do not exist or test generation is run with
constraintcheck=no, invalid data may be captured into the domain.
USER RESPONSE:
The domain logic should be fixed to ensure all paths into the domain are correctly
blocked when the block_inputs and functional clock gate controls are set.

INFO (TCE-403): Clock Domain Identification Completed. numDomains Domains

Identified.
EXPLANATION:
Indicates that the process to identify clock domains has completed.
USER RESPONSE:
INFO (TCE-404): Domain Crossing Identification Started.

EXPLANATION:
Indicates that the process to identify domain crossings has started.
USER RESPONSE:
INFO (TCE-405): Domain Crossing Identification Completed.

EXPLANATION:
Indicates that the process to identify domain crossings has started.
USER RESPONSE:
INFO (TCE-406): Domain Fencing Check Started.

EXPLANATION:
Indicates that the process to check whether domains are properly fenced has started.
USER RESPONSE:
INFO (TCE-407): Domain Fencing Check Completed.

EXPLANATION:
Indicates that the process to check whether domains are properly fenced has completed.
USER RESPONSE:

WARNING (TCE-408): Invalid Pin Name: pn on line ln, statement sn of file filename.
The statement is skipped.
EXPLANATION:
The specified pin name does not exist in the Encounter Test logic model. The statment
is skipped and is not processed.
USER RESPONSE:
Correct the pin name or remove the statement from the file and rerun
prepare_domain_constraints.
WARNING (TCE-409): Clock Domain Crossing pn1 to pn2 on line ln, statement sn of file
filename is not found. The statement is skipped.
EXPLANATION:
Encounter Test did not find the domain crossing specified. The statement is skipped.
USER RESPONSE:
Correct the pin name(s) of the domain crossing or remove the statement from the file and
rerun prepare_domain_constraints.
WARNING (TCE-410): Syntax error processing line: ln, statement sn of file: fn. Reason:
reason
EXPLANATION:
A syntax error was found in the specified file. The statement is skipped.
USER RESPONSE:
Correct the syntax error and rerun prepare_domain_constraints.
INFO (TCE-411): Write Constraints Started. c constraints identified.

EXPLANATION:
Indicates that the process to write constraints for ATPG has started.
USER RESPONSE:
INFO (TCE-412): Write Constraints Completed.

EXPLANATION:

Indicates that the process to write constraints for ATPG has completed.
USER RESPONSE:
INFO (TCE-413): Removing Domain Constraints Started.

EXPLANATION:
Indicates that the process to remove domain constraints for ATPG has started.
USER RESPONSE:
INFO (TCE-414): Removing Domain Constraints Completed.

EXPLANATION:
Indicates that the process to remove domain constraints for ATPG has completed.
USER RESPONSE:
INFO (TCE-415): n falsepath constraints have been identified.

EXPLANATION:
Prepare_domain_constraints was run to identify the need for falsepath constraints
during ATPG. For this ATPG / Simulation command, the specified number of constraints
are required to prevent transitions across domains that interact.
USER RESPONSE:
If you do not want the constraints applied, run remove_domain_constraints to
remove the constraint data, or run this command with constraintcheck=no to avoid
checking any ATPG timing constraints.
WARNING (TCE-416): [Severe] When block input and functional clock gates are set for
domain dom1, this domain receives data into state element elem1 from state element
elem2 along the scan path.
EXPLANATION:
During at speed delay test using launch off capture, a transition should not be captured
from the scan path unless the scan path has been timed to operate at speed. When the
block inputs and functional clock gates are set for domain dom1, data is captured along
the scan path. The prepare_domain_constraints command creates constraints

that are used by default during delay test generation and simulation. If they are used,
transitions along the scan path will be captured as an X. If the constraints have been
removed or delay test generation is run with constraintjustify=no
constraintcheck=no, invalid data may be captured.
USER RESPONSE:
The domain fencing logic should be fixed to ensure all scan paths are correctly blocked
when the block_inputs and functional clock gate controls are set.
INFO (TCE-417): n falsepath setup constraints have been identified.

EXPLANATION:
Prepare_domain_constraints was run to identify the need for setup constraints
along the scan path during ATPG. For this ATPG / Simulation command, the specified
number of constraints are required to prevent transitions along the scan path.
USER RESPONSE:
If you do not want the constraints applied, run remove_domain_constraints to
remove the constraint data, or run this command with constraintcheck=no to avoid
checking any ATPG timing constraints.
WARNING (TCE-418): Unable to determine Block Input register value for domain d.
Skipping fencing check for this domain.
EXPLANATION:
The build_testmode input file contains a definition of the Block Input register along
with valid register values and their meanings. prepare_domain_constraints was
unable to determine which value sets the block input register to the state that causes the
blocking to occur. A register value with the string "block" or "BLOCK" in its name is
assumed to set the register to its blocking state. If no such register value is found, then
the complement of a register value with the string "enable" or "ENABLE" in its name is
used as the blocking value. If a value cannot be determined, the checking is skipped for
this domain.
USER RESPONSE:
ATPG will automatically protect the domain crossing even if the domain fencing was not
checked. However to check the domain fencing, you must first rebuild the testmode with
a register value defined that prepare_domain_constraints can use to determine
the blocking state. Then rerun prepare_domain_constraints.

INFO (TCE-419): Domain dom1, state element elem1, feeds domain dom2, state element
elem2.
EXPLANATION:
State element elem2 captures data from state element elem1. elem1 is clocked by
dom1. elem2 is clocked by dom2.
USER RESPONSE:
None required. To suppress this message specify reportdomaincrossings=no.
INFO (TCE-420): Write Setup Sequences Started.

EXPLANATION:
Indicates that the process to write setup sequences for domain groups has started.
USER RESPONSE:
INFO (TCE-421): Write Setup Sequences Completed. n Sequences Identified:\n

EXPLANATION:
Indicates that the process to write setup sequences for domain groups has completed.
The n sequences identified are named setup_group_all and setup_group_1
through setup_group_(n-1).
USER RESPONSE:
INFO (TCE-422): setupsequence_list

EXPLANATION:
RESPONSE:
WARNING (TCE-423): [Severe] Domain dom1, and domain dom2 appear to share the
same domain root: root. Domain crossing checks may produce invalid results.
EXPLANATION:
Two domains share the same domain root. This is most likely due to the fact that the
twodomains are defined in the test mode definition file using the same PPI as their
domain roots.

prepare_domain_constraints is unable to accurately identify the latchee/flops

clocked by these domains. As a result, messages produced during domain checking
may be incorrect.
USER RESPONSE:
If the testmode was created using prepare_opcg_testmode, rebuild the testmode
using ppilimit=0 and then rerun prepare_domain_constraints. Otherwise,
revise the test mode definition file to use unique PPIs for each OPCG domain. Then
rebuild the testmode and rerun prepare_domain_constraints.
WARNING (TCE-424): [Severe] n msgnum Messages were suppressed.

EXPLANATION:
The specified number of messages were suppressed via the SUPPRESS_MSG attribute.
Constraints were not generated to protect potentially unsafe domain crossings. This
could result in invalid test data.
USER RESPONSE:
To see the messages that were suppressed, rerun prepare_domain_constraints
suppressmsg=no.
INFO (TCE-425): number design constraints are being applied.

EXPLANATION:
The constraints from a design constraints file are being applied for ATPG and/or
simulation. As clocking requirements change, the constraints may need to be reapplied,
resulting in multiple occurrences of this message throughout a given ATPG or simulation
experiment.
USER RESPONSE:
No response required. If the test coverage is lower than expected, it is possible that the
design is being over constrained. You may need to review the design constraints to
ensure that they are not overconstraining the ATPG process.
INFO (TCE-425): number design constraints are being applied.

EXPLANATION:
The constraints from a design constraints file are being applied for ATPG and/or
simulation. As clocking requirements change, the constraints may need to be reapplied,
resulting in multiple occurrences of this message throughout a given ATPG or simulation
experiment.

USER RESPONSE:
No response required. If the test coverage is lower than expected, it is possible that the
design is being over constrained. You may need to review the design constraints to
ensure that they are not overconstraining the ATPG process.
INFO (TCE-426): Read fencinglinehold File Started.

EXPLANATION:
The fencinglinehold file is being read to apply lineholds that should be applied when
fencing is being checked.
USER RESPONSE:
INFO (TCE-427): Read fencinglinehold File Complete.

EXPLANATION:
Reading the fencinglinehold file is complete.
USER RESPONSE:
INFO (TCE-428): Read indomainfile Started.

EXPLANATION:
The indomainfile is being read to identify SAFE/UNSAFE domains as specified by the
user.
USER RESPONSE:
INFO (TCE-429): Read indomainfile Complete.

EXPLANATION:
Reading the indomainfile is complete.
USER RESPONSE:

13
TCI - Structure Analysis Messages
TCI-001 through TCI-002 on page 321
TCI-001 through TCI-002

ERROR (TCI-001): Clock Affiliation must be initialized prior to Block Driven Table (BDT)
initialization.
EXPLANATION:
An internal program error has occurred.
USER RESPONSE:
ERROR (TCI-002): Invalid Clock Affiliation handle. Block Driven Table (BDT)
initialization ceases.
EXPLANATION:
Creation of the compiled code file is complete.
USER RESPONSE:
USER RESPONSE:

TCI - Structure Analysis Messages

14
TCL - High Speed Scan Based Simulation
Messages
TCL-001 through TCL-049 on page 323

TCL-001 through TCL-049

IINFO (TCL-001): Simulator initialization completed.
EXPLANATION:
This is an informational message.
USER RESPONSE:
WARNING (TCL-002): Cannot allocate simulation handle.

EXPLANATION:
The allocation and initialization of the simulation handle failed. The run cannot continue.
USER RESPONSE:
More storage may be needed. Contact customer support (see Contacting Customer
Service on page 23) if this does not seem reasonable.

TCL - High Speed Scan Based Simulation Messages
WARNING (TCL-003): Simulator initialization failed. Refer to accompanying messages for

more information and contact customer support (see Contacting Customer Service on
page 23) for more help.
EXPLANATION:
The simulator did not initialize. Refer to accompanying messages for more information.
USER RESPONSE:
Examine accompanying messages and correct the problem.
WARNING (TCL-004): Simulator was not initialized, simulation will not be attempted. Refer
to accompanying messages for more information and contact customer support (see
Contacting Customer Service on page 23) for more help.
EXPLANATION:
An internal program error caused the run to terminate.
USER RESPONSE:
WARNING (TCL-005): type Good Machine 3-State contention on netname (index=

hierIndex) detected at TBD location TBDodometer.
EXPLANATION:
This indicates that conflicting values were driven on the same net. Based on current
options, the test sequence may be written to the Vector output file creating a risk of
burnout at the tester when the generated test data is used. If the sequence is written to
the Vectors it will be audited.
USER RESPONSE:
If desired, correct the design and rerun, or change the options so that sequences causing
such contention are removed.
INFO (TCL-006): type Good Machine 3-State contention on netname (index=

hierIndex) detected at TBD location TBDodometer. The test will be removed.
EXPLANATION:
This indicates an orthogonal condition was encountered that is not allowed to be
included in the Vector output file based on current options. To ensure accurate fault
simulation results the output file should be resimulated. This will happen automatically if
running test generation.

USER RESPONSE:
If desired, correct the design and rerun.
WARNING (TCL-009): Error from EDAMsopn(fcb,sanum). An error was encountered

while attempting to access data from the compiled code file. Check for additional messages
and contact customer support (see Contacting Customer Service on page 23).
EXPLANATION:
An error was encountered while attempting to access data from the compiled code file.
In some cases the run is terminated.
USER RESPONSE:
Check the additional messages and contact customer support (see Contacting
WARNING (TCL-010): Error from EDAMsget(fcb,toptr, offset,size). An error

was encountered while attempting to access data from the compiled code file. Check for
additional messages and contact customer support (see Contacting Customer Service on
page 23).
EXPLANATION:
USER RESPONSE:
Check for additional messages and contact customer support (see Contacting
WARNING (TCL-011): Error from EDAMmap(fcb,offset, size). An error was

encountered while attempting to access data from the compiled code file. Check for additional
messages and contact customer support (see Contacting Customer Service on page 23).
EXPLANATION:
USER RESPONSE:

WARNING (TCL-012): Error from EDAMfcls(fcb,keep) = (retc). An error was

encountered while attempting to access data from the compiled code file. Check for additional
messages and contact customer support (see Contacting Customer Service on page 23)
EXPLANATION:
An error was encountered while attempting to close the compiled code file. In some
cases the run is terminated.
USER RESPONSE:
INFO (TCL-014): num faults are tested, num possibly testable at best faults are possibly
tested and num other faults are not selected for simulation.
EXPLANATION:
The fault model being processed by this simulation run may contain faults that are not
loaded for simulation.
USER RESPONSE:
WARNING (TCL-022): [Severe] Cannot load the flat model. If the flat model does not exist
or is suspect, rerun build_model. Otherwise, contact customer support (see Contacting
EXPLANATION:
An error condition was encountered when attempting to load the flat model.
USER RESPONSE:
If the flatModel file exists, contact customer support (see Contacting Customer Service
on page 23). Otherwise, re-build the flat model and reprocess the part.
WARNING (TCL-023): [Severe] Cannot load the flat model Latch Methods. If the flat model
is suspect, rerun build_model. Otherwise, contact customer support (see Contacting
EXPLANATION:
USER RESPONSE:

WARNING (TCL-024): [Severe] Cannot initialize data structures. An internal program error
caused the run to terminate. Contact customer support (see Contacting Customer Service
on page 23).
EXPLANATION:
USER RESPONSE:
INFO (TCL-025): The simulator has been closed.

EXPLANATION:
Simulation is complete and the simulator has been unloaded.
USER RESPONSE:
WARNING (TCL-027): [Severe] Cannot exhaustively test parts with more than 24 PIs. num
were found on this part. The exhaustive simulation option is limited to combinational parts
with no more than 24 primary inputs. No simulation is performed.
EXPLANATION:
The exhaustive simulation option is limited to combinational parts with no more than 24
primary inputs. No simulation is performed.
USER RESPONSE:
If desired, rerun without the exhaustive simulation option.
INFO (TCL-028): Compile will be done: Compiled code does not exist.
EXPLANATION:
USER RESPONSE:
INFO (TCL-029): Compile will be done: Compiled code is older than Fault Model.
EXPLANATION:

The compiled code is dependent on the fault model. Since the compiled code is older
than the fault model it will be recompiled to ensure it is not backleveled.
USER RESPONSE:
INFO (TCL-030): Compile will be done: Level mismatch between compiled code and
simulator. Simulator level = majorid.minorid
EXPLANATION:
The current compiled code is backleveled and needs to be recompiled. This is usually
due to a new maintenance level.
USER RESPONSE:
INFO (TCL-031): Compile not required: existing type file is up to date.

EXPLANATION:
USER RESPONSE:
WARNING (TCL-037): A Test Procedure with memory cannot be done in Expand mode.
Ignoring specification of Expand.
EXPLANATION:
Expand mode is a test generator specified option that causes multiple test sequences to
be simulated in parallel. If the test procedure requires that non-scannable memory
elements retain their design state across test sequences then they must be simulated
one at a time and the expand option is ignored. This is most likely a programmer error,
but the output data is valid.
USER RESPONSE:
ERROR (TCL-039): Run stopped. Check for additional messages and contact customer
EXPLANATION:
An error was encountered causing the run to terminate.

USER RESPONSE:
WARNING (TCL-040): [Severe] Cannot get storage for an internal table (name). More
internal storage is required for this run. Contact customer support (see Contacting Customer
EXPLANATION:
More internal storage is required for this run.
USER RESPONSE:
WARNING (TCL-041): A Test Procedure with memory is not valid during IDDq processing.
The output data is valid, but the memory attribute will be ignored. Contact customer support
(see Contacting Customer Service on page 23) if these patterns were not user specified.
EXPLANATION:
An IDDq test is expanded into multiple independent test sequences of which the one that
detects the most IDDq faults is kept. A test procedure with memory requires that non-
scannable memory elements retain their design state across test sequences and this is
not supported during IDDq processing. The output data is valid.
USER RESPONSE:
Contact customer support (see Contacting Customer Service on page 23) if this is a
concern.
WARNING (TCL-042): [Severe] Unexpected Error in file:line (time date). An

internal program error caused the run to terminate. Check for additional error messages and
EXPLANATION:
A program error has occurred and the simulator is terminating. The data included in the
message is for developer debug.
USER RESPONSE:
Check for additional error messages and contact customer support (see Contacting
Customer Service on page 23)

WARNING (TCL-048): Unable to access TSV Test Status on the globalData file. An LSSD
flush test cannot be generated.
EXPLANATION:
Generation of an LSSD flush test is dependent on information supplied by TSV but TSV
has not been run.
USER RESPONSE:
Run TSV before attempting to generate an LSSD flush test.
WARNING (TCL-049): Flush Measure Registers do not exist. An LSSD flush test cannot be
generated.
EXPLANATION:
Generation of an LSSD flush test is dependent on the existence of flush measure
registers.
USER RESPONSE:
Contact customer support (see Contacting Customer Service on page 23) if there is a
concern.

INFO (TCL-052): A tester termination of 0|1 will be used.
EXPLANATION:
If Test Termination is 0, 0 will be used to resolve the TSR value. If Test Termination is 1,
1 will be used to resolve the TSR value.
USER RESPONSE:
INFO (TCL-053): The product termination will dominate.

EXPLANATION:
This message informs that product termination will dominate.
USER RESPONSE:

INFO (TCL-053): The tester termination will dominate.

EXPLANATION:
This message informs that tester termination will dominate.
USER RESPONSE:
WARNING (TCL-060): (callcallnum) TBDeventType_Error detected.

EXPLANATION:
An erroneous event was encountered while processing patterns within a test sequence.
USER RESPONSE:
WARNING (TCL-061): (callcallnum) Unknown TBDeventType detected.

EXPLANATION:
An unknown event was encountered while processing patterns within a test sequence.
USER RESPONSE:
WARNING (TCL-062): (callcallnum) Ignoring a clock being stimmed to X (node

nodeid).
EXPLANATION:
The simulator does not allow clocks to be stimmed to an unknown value. The stim is
ignored and processing continues.
USER RESPONSE:
WARNING (TCL-063): (callcallnum) Clock node nodeid has an invalid stability value.
EXPLANATION:
A stability value for a clock cannot be determined.
USER RESPONSE:

WARNING (TCL-064): (callcallnum) Ignoring a PI being stimmed to X (node nodeid).

EXPLANATION:
Stimming a PI to X is not supported. The PI will remain at its current state.
USER RESPONSE:
WARNING (TCL-065): (callcallnum) Test Inhibit node nodeid has an invalid stability
value.
EXPLANATION:
A stability value for a Test Inhibit cannot be determined.
USER RESPONSE:
WARNING (TCL-066): The application encountered an error processing the scan chain test
patterns.
EXPLANATION:
An error condition was encountered processing the scan chain test patterns. Processing
of the scan chain tests terminates.
USER RESPONSE:
WARNING (TCL-067): The application encountered an error processing the LSSD flush
test. Contact customer support (see Contacting Customer Service on page 23).
EXPLANATION:
An error condition was encountered processing the scan chain LSSD flush test patterns.
Processing of the scan chain tests terminates.
USER RESPONSE:
WARNING (TCL-068): A stim was removed because it took a Test Inhibit PI (nodeid) away
from its stability value of value.
EXPLANATION:

The simulator does not allow a test inhibited primary input to be stimmed to anything
other than its stability value. The stim is not placed on the output Vectors.
USER RESPONSE:
If this error occurs during simulation of a user-imported Vectors, if desired, correct the
input data and re-import. If user-imported vectors are not being simulated contact
customer support (see Contacting Customer Service on page 23).
WARNING (TCL-069): [Severe] num clocks are out of stability. This simulator may produce
incorrect results if more than one clock is turned on at a time. The results will be flagged as
suspect.
EXPLANATION:
The simulator cannot guarantee correct response data when multiple clocks are on at
the same time. An audit flag is set for the experiment indicating that the results are
suspect.
USER RESPONSE:
If this error occurs during simulation of a user-imported Vectors file, if desired, correct the
input data and re-import. If user-imported vectors are not being simulated, contact
WARNING (TCL-072): (callcallnum) PI node nodeid has an invalid stability value that
will be ignored. Contact customer support (see Contacting Customer Service on page 23).
EXPLANATION:
A test function PI has an unsupported stability value which will be ignored.
USER RESPONSE:
WARNING (TCL-073): [Severe] The specified tester termination (term) violates the TDR.
EXPLANATION:
There is a conflict between the tester termination specified for the run and the allowable
terminations on the TDR. The override is audited.
USER RESPONSE:
If desired, change the TDR or the run time specification.
WARNING (TCL-074): A test pattern was detected that may cause excessive output
switching. Such tests may be unreliable.

EXPLANATION:
This indicates a clock was pulsed or stimmed on while an output inhibit (OI) test function
pin was enabled. When running test generation this can be controlled via the Allow
Simultaneous Output Switching (SOS) option (sos=yes|no on the command line).
USER RESPONSE:
If desired, disallow the option when running test generation. Or, if using manual patterns,
edit the patterns and rerun.
INFO (TCL-075): Compile will be done: Fault machine code does not exist.
EXPLANATION:
The compiled code was generated for good machine simulation. The compiled code
must be recompiled to include fault machine simulation.
USER RESPONSE:
INFO (TCL-076): Running in clean mode: compiled code files will be deleted.
EXPLANATION:
When running in clean mode the compiled code files are automatically deleted when the
simulator is closed.
USER RESPONSE:
WARNING (TCL-077): Cannot delete the existing compiled code file.

EXPLANATION:
When running in clean mode the compiled code files are automatically deleted when the
simulator is closed. For some reason, a file was not deleted.
USER RESPONSE:
No response required. If desired, delete the file manually.
WARNING (TCL-078): [Severe] The measurepo specification (all) violates the TDR.
EXPLANATION:
The specification of measurepo=all for the run conflicts with the TDR specification of
measurepo = faultdetect. The override is audited.

USER RESPONSE:
If desired, change the TDR or the run time specification.
WARNING (TCL-080): [Severe] The application encountered an error while processing the
output vectors. Check for insufficient filespace or file permissions. Contact customer support
(see Contacting Customer Service on page 23) for further help.
EXPLANATION:
An error condition was encountered during processing of the output Vectors.
USER RESPONSE:
WARNING (TCL-081): [Severe] Cannot add a event to output vectors database. Contact
customer support (see Contacting Customer Service on page 23) for further help.
EXPLANATION:
An error condition was encountered during processing of the output vectors.
USER RESPONSE:
WARNING (TCL-082): [Severe] The applicaion encountered an error while processing the
random pattern clocking sequences. Simulation halted. Contact customer support (see
EXPLANATION:
The applicaion encountered an error while processing the random pattern clocking
sequences.
USER RESPONSE:
WARNING (TCL-083): Command line parameter contentionremove=no has been

specified indicating that test sequences for which 3-state contention was reported should be
written to the output Vector file. This requires that you specify that all test sequences,
including those that are ineffective, be written (command line parameter
writepatterns=all).
EXPLANATION:

By specifying that patterns with 3-state contention should not be removed the user is
requesting that test sequences for which 3-state contention was reported be written to
the output Vector file. When this option is specified the High Speed Scan-Based
Simulator also requires that all sequences, including those that are ineffective, be written
to the output Vector file. This option is most likely to be used when simulating manual test
sequences.
USER RESPONSE:
If it is required that test sequences for which 3-state contention has been reported get
written to the output Vector file, rerun specifying that ineffective patterns should be
included in the output (command line parameter writepatterns=all). Otherwise,
specify that these sequences should be removed (command line parameter
contentionremove=yes).
WARNING (TCL-084): [Severe] An invalid stim to value of Test Inhibit PI/PPI

netname (index= hierIndex) away from its stability value of value has been
encountered.
EXPLANATION:
The simulator does not allow a test inhibited primary input or pseudo primary input to be
stimmed to anything other than its stability value.
The run is terminated.
USER RESPONSE:
If this error occurs during simulation of user-imported Vectors, correct the input data and
re-import. If user-imported Vectors are not being simulated, contact customer support
(see Contacting Customer Service on page 23).
WARNING (TCL-085): An invalid stim to value of Test Constraint PI/PPI netname

(index= hierIndex) away from its stability value of value has been encountered.
EXPLANATION:
The simulator does not allow a test constraint primary input or pseudo primary input to
be stimmed to anything other than its stability value except during a scan operation.
USER RESPONSE:
If this error occurs during simulation of a user-imported Vectors, correct the input data
and re-import. If user-imported Vectors are not being simulated contact customer

WARNING (TCL-086): A Stop_Osc event specifies a quiescent value of value, which

differs from the stability value of value. The PI is set to value. The PI is netname (index=
hierIndex).
EXPLANATION:
The value specified to restore an oscillator was not the stability value of the clock.
USER RESPONSE:
Ensure that the specified Stop_Osc event is intended to leave the clock in the non-
stability state. If not, change the Stop_Osc event to utilize the stability value.
WARNING (TCL-087): [Severe] A clock was not at its stability value when an event
(eventID) requiring a scan operation was encountered. The run terminates. The clock is
netname (index= hierIndex).
EXPLANATION:
In order to ensure that the design correctly scans, the High Speed Scan-Based Simulator
requires that all clocks be at their stability value when a scan operation is invoked.
USER RESPONSE:
re-import.
If user-imported Vectors are not being simulated, contact customer support (see
ERROR (TCL-088): Unable to add failure data to the TBDfail file. Processing terminates.
Check the disk to make sure there is enough space available. If a failure data file is not
needed, specify tbdfail=no on the command line.
EXPLANATION:
Unable to write failure data to the TBDfail file.
USER RESPONSE:
Check the disk quota to make sure there is enough space available. If a failure data file
is not needed, specify tbdfail=no on the command line.
WARNING (TCL-089): [Severe] Hard|Soft|AllX Good Machine 3-State contention on

netname (index= hierIndex). The test data may be invalid.
EXPLANATION:

This message indicates that conflicting strong values were driven on the same net in the
simulation of WRPT or LBIST patterns, creating a risk of burnout at the tester when the
generated test data is used. The data will still be included in the Vectors.
USER RESPONSE:
Determine whether there is a way to prevent this condition by lineholding some primary
inputs and/or latches. If not, then modify the design. The most effective way to prevent
this condition is to put mutually exclusive gating on the enable signals to the driver
circuits that are dotted together.
WARNING (TCL-095): [Severe] An invalid stim to value of Prpg Save PI/PPI_2

encountered.
EXPLANATION:
The simulator does not allow a prpg save primary input or pseudo primary input to be
USER RESPONSE:
re-import. If user-imported Vectors are not being simulated, contact customer support
WARNING (TCL-096): [Severe] An invalid stim to value of Prpg Restore PI/PPI

encountered.
EXPLANATION:
The simulator does not allow a prpg restore primary input or pseudo primary input to be
USER RESPONSE:
re-import. If user-imported Vectors are not being simulated contact customer support


WARNING (TCL-150): [Severe] Cannot set the test mode.
EXPLANATION:
USER RESPONSE:
WARNING (TCL-151): [Severe] Cannot set the testmode. If the testmode is suspect, rerun
build_testmode. If this does not correct the problem, contact customer support (see
EXPLANATION:
An error occurred while trying to set up the mode data for the flat model.
USER RESPONSE:
INFO (TCL-152): Compile will be done: Existing compiled code is for AIX machines only.
EXPLANATION:
The existing compiled code will not run on a non-AIX platform. Valid compiled code will
be built automatically.
USER RESPONSE:
INFO (TCL-153): num tests were removed because of type.

EXPLANATION:
This indicates how many test sequences were not written to the Vector output based on
the current orthogonal elimination option, violation of dynamic constraints, and/or the
current removeXpo and removeXlatch options.
USER RESPONSE:

INFO (TCL-154): contentionreport has been set to type.

EXPLANATION:
This indicates the current setting of the 3-state contention reporting option.
USER RESPONSE:
WARNING (TCL-155): [Severe] Cannot load the faults for simulation. Check for additional
messages and contact customer support (see Contacting Customer Service on page 23).
EXPLANATION:
USER RESPONSE:
WARNING (TCL-156): Multiple stims of non-contacted primary inputs were found in a test
sequence, but the number of tester parametric measure units does not support this. The test
sequence was discarded.
EXPLANATION:
Based on the TDR and circuit, test data is being generated that only allows one PMU to
be used. Any test sequence requiring multiple PMUs is discarded.
USER RESPONSE:
concern.
WARNING (TCL-157): [Severe] Encountered an error while attempting to process the

linehold data. Check for additional messages and contact customer support (see Contacting
EXPLANATION:
An error was encountered while attempting to process the linehold data. In some cases
the run is terminated.
USER RESPONSE:

INFO (TCL-158): This design requires infinite X simulation for Latches. Performance may be
degraded.
EXPLANATION:
A pessimistic mode of simulation, called "infinite X", is being invoked for latch transitions
due to the presence of design guideline violations. This is necessary to guard against
invalid simulation results in the presence of these violations.
Two conditions that can cause infinite X simulation to be invoked for latch input transitions
are:
A memory element is clocked by a clock which is gated by a signal from a
memory element which is clocked by the same clock (TSV059 - LSSD and
GSD).
One or more clock inputs to a latch are not at a known value in the stability state
(TSV310 - GSD).
USER RESPONSE:
If optimum simulation performance and fault coverage are to be achieved then the
underlying design guideline violations must be corrected. Otherwise this message can
be ignored.
Note: If invalid clock gating (TSV059) is the design guideline violation responsible for the
TCL-158 message then check the results of your Test Structure Verification (TSV) run to
see if Check Mutually Exclusive Gating was selected (command line parameter
megraces=yes). If not, then you may want to rerun TSV using this option. The
mutually exclusive gating check may cause the TSV message(s) which prompted the
TCL-158 message to disappear.
INFO (TCL-159): This design requires infinite X simulation for Primary Inputs. Performance
may be degraded.
EXPLANATION:
A pessimistic mode of simulation, called "infinite X", is being invoked for primary input
transitions due to the presence of design guideline violations. This is necessary to guard
against invalid simulation results in the presence of these violations.
Two conditions that can cause infinite X simulation to be invoked for primary input
transitions are:
A clock pin on a memory element is not off in the stability state (message
TSV008 from Test Structure Verification - LSSD).

One or more clock inputs to a latch are not at a known value in the stability state
(TSV310 - GSD).
USER RESPONSE:
If optimum simulation performance and fault coverage are to be achieved then the
underlying design guideline violations must be corrected. Otherwise this message can
be ignored.
WARNING (TCL-161): [Severe] An internal program error caused the run to terminate.
Check for additional messages and contact customer support (see Contacting Customer
EXPLANATION:
An error was encountered while attempting to process the data that is used to do 3-state
contention elimination. In some cases the run is terminated.
USER RESPONSE:
WARNING (TCL-162): A stim to netname of non-contacted primary input n (index=

hierIndex) was found in a test sequence, and a tester parametric measure unit cannot be
used. The test sequence was discarded.
EXPLANATION:
In order to stim a non-contacted primary input a parametric measure unit (PMU) must be
used. Either there are not enough PMUs in the tester or PMUs are not allowed to be used
for the type of tests that are being simulated.
USER RESPONSE:
Check the messages from Build Test Mode for a warning about this condition. If no such
message was produced, or there are other concerns, contact customer support (see
WARNING (TCL-163): A stim to netname of inactive, non-contacted primary input n

(index= hierIndex) was found in a test sequence. It will be ignored.
EXPLANATION:
A stim to an inactive, non-contacted primary input is not valid. The simulator will simulate
such PIs at X, unless they are 3-state PIs in which case they will be simulated at Z.
USER RESPONSE:

If this condition is unacceptable, contact customer support (see Contacting Customer

INFO (TCL-164): Infinite X simulation for Latches has been requested. Performance may be
degraded.
EXPLANATION:
Infinite X simulation for latches was explicitly requested. It may not be required.
USER RESPONSE:
INFO (TCL-165): Infinite X simulation for Primary Inputs has been requested. Performance
may be degraded.
EXPLANATION:
Infinite X simulation for PIs was explicitly requested. It may not be required.
USER RESPONSE:
WARNING (TCL-167): Fault grouping is not supported for this type of experiment.
Simulation using one fault group will be attempted.
EXPLANATION:
Multiple fault groups were requested but this support is not available for WRPT or LBIST.
USER RESPONSE:
WARNING (TCL-168): Fault grouping is not supported for test procedures requiring
memory between test sequences. A test procedure is ignored.
EXPLANATION:
Processing of multiple fault groups is limited to test procedures that do not require
memory between test sequences. The test procedure requiring memory is not simulated
and will not be included in the output Vector file.
USER RESPONSE:

INFO (TCL-169): Fault simulation will be performed with num fault groups using a space of
num meg.
EXPLANATION:
USER RESPONSE:
WARNING (TCL-170): A stim value for correlated PI netname (index= hierIndex) is not
the value required by the correlation. Other conflicts may exist in this event. Processing
continues.
EXPLANATION:
A conflict on a stim PI or stim PI plus random event is detected. The conflicting values
are simulated.
USER RESPONSE:
Ensure the stim value on the correlated PI is correct. No response is required if the stim
value on the correlated PI is correct. If the value is not correct, change the manual
patterns and re-import the patterns to correct the problem.
WARNING (TCL-171): [Severe] A stim|pulse value for correlated clock PI netname

(index= hierIndex) is not the value required by the correlation. Conflicts on clock events
are not supported by the High Speed Scan-Based Simulator. The conflicting value will be
changed to the required value.
EXPLANATION:
There is a conflict between the actual value and the value required by correlation. The
conflicting value will be changed to the required value.
USER RESPONSE:
Ensure the stim|pulse value on the correlated PI is correct. If the stim|pulse
value on the correlated PI is correct, rerun using the General Purpose Simulator. If the
value is not correct, change the manual patterns and re-import the patterns to correct
the problem.
INFO (TCL-172): Compile will be done: overriding current keeper device processing.
EXPLANATION:
A recompile is necessary based on the value of the keeper device parameter.

USER RESPONSE:
ERROR (TCL-173): A event type event specified PI netname (index= hierIndex)

but test function pin flags indicate this PI is not a clock. Processing terminates.
EXPLANATION:
The specified PI is not a clock according to the test function pin flags. The High Speed
Scan-Based Simulator does not support this event on non-clock primary inputs.
USER RESPONSE:
Check the test sequence. Ensure the PI specified in the event is a clock., then rerun.
WARNING (TCL-174): [Severe] Exhaustive simulation is limited to small combinational

parts. A design with clocks, latches or rams cannot be exhaustively simulated.
EXPLANATION:
The design being processed does not meet the criteria to be able to perform exhaustive
simulation. No simulation is performed.
USER RESPONSE:
If desired, rerun without the exhaustive option.
WARNING (TCL-175): [Severe] A TBD error occurred during processing of an init test
procedure. Processing continues, but results are suspect.
EXPLANATION:
A bad return code was received when attempting to put an init test procedure on the
output Vector file. This probably indicates a programming error and it is likely that any
output data is invalid.
USER RESPONSE:
WARNING (TCL-176): The specification to put out all PO measures is being ignored due to
the test section being processed. PO measures will be limited to those which detect faults for
this driver/receiver test section.
EXPLANATION:
The measurepo option does not apply to driver/receiver tests. PO measures are
produced only on POs that detect faults in this type of test section. measurepo=all will

still be in effect for all applicable test sections being processed during this run.
USER RESPONSE:
No response is required; however, you may remove the measurepo=all parameter and
the results will be the same.
WARNING (TCL-177): The specification to put out all PO measures is being ignored due to
the test section being processed. PO measures will be limited to those which detect faults for
this logic test section since the number of active logic pins is greater than the full function pin
limit as specified on the TDR.
EXPLANATION:
The measurepo option does not apply to logic tests when the number of active logic pins
is greater than the full function pin limit as specified on the TDR. PO measures are
produced only on POs that detect faults in this type of test section. measurepo=all will
still be in effect for all applicable test sections being processed during this run.
USER RESPONSE:
No response is required; however, you may remove the measurepo=all parameter and
the results will be the same.
WARNING (TCL-178): [Severe] Fault simulation was requested but there are no faults to
simulate.
EXPLANATION:
No fault data exists for the simulator to fault simulate. This usually occurs when faults do
not exist for the test mode being processed. This can be verified by checking the fault
model statistics for the test mode. Processing terminates.
USER RESPONSE:
If fault simulation is desired, ensure faults exist for the test mode being processed. This
may require rebuilding the fault model for the test mode. If fault simulation is not required
the job should be rerun with good machine simulation specified.
INFO (TCL-179): num miscompares were detected during simulation.

EXPLANATION:
This indicates that the comparemeasures option was in effect and provides the number
of miscompares that occurred between expected values and predicted values. Refer to
message "TCL-710" or "TCL-711" for further explanation.

USER RESPONSE:
WARNING (TCL-180): 1 or more test procedures with memory had conflicts which makes
the fault coverage suspect. A resimulation is necessary to ensure the fault coverage is
correct.
EXPLANATION:
If a test procedure with memory is found to have 3-state contention or a PMU conflict the
entire test procedure is considered to be invalid. Faults detected during simulation of the
test procedure are no longer valid detects and the fault coverage is not accurate. If a
Vector file is being written it must be resimulated in order to get an accurate fault
coverage. This will happen during a test generation experiment if reverse simulation was
selected.
USER RESPONSE:
Review other messages to determine the type of conflict and respond to those if desired.
For test generation applications, specifying reportdebug=yes can give detailed
information about 3-state contention. If reverse simulation was not performed and an
accurate fault coverage is necessary, resimulate the uncommitted Vectors.
INFO (TCL-181): num tests which had type 3-state contention were written to the Vector
output file.
EXPLANATION:
This indicates how many test sequences with a certain type of 3-state contention were
written to the Vector output file. This is based on the contentionreport and
contentionremove options.
USER RESPONSE:
INFO (TCL-182): Compile will be done: 64 bit incompatibility.

EXPLANATION:
A recompile is necessary based on a difference between the existing compiled code and
the current platform. Either the compiled code was built on a 32 bit machine and is being
run on a 64 bit machine or vice versa.
USER RESPONSE:

WARNING (TCL-183): [Severe] The process to generate the compiled code files failed.
This usually indicates a lack of space or an inadequate ulimit setting.
EXPLANATION:
A separate process is used to generate the compiled code files. The return code from
the process indicates that the process failed.
USER RESPONSE:
Check available space. Set ulimits to unlimited.
INFO (TCL-184): 01hot has been set to no%lor.yes.

EXPLANATION:
This indicates the current setting of the 01hot 3-state driver contention reporting option.
If yes, the simulator will report any 3-state with more than 1 driver enabled in the case
where there is a known propagation value. For example, if there are only two drivers and
they are both driving zero this would be reported. Also if one of the drivers was driving a
zero and the other driver was possibly driving a zero this would be reported since the
zero would propagate. If one driver was zero and the other was unknown this would not
be reported since the propagation value would be X. The removal of the sequence
depends on the setting of the contentionremove keyword.
USER RESPONSE:
WARNING (TCL-185): [Severe] This 1149.1 mode requires an update_dr operation in the
form of load suffix patterns. A Scan_Load or Skewed_Scan_Load was found that was not
followed by the required load suffix patterns.
EXPLANATION:
Based on the mode statistics, each pattern containing a Scan_Load or
Skewed_Scan_Load event must be followed by the update_dr operation. This is
indicated by patterns with the load suffix pattern sequence attribute.
This message is printed each time the required patterns are missing.
USER RESPONSE:
If this error occurs during simulation of a user-imported Vectors, if desired, ensure the
load suffix sequence patterns follow each pattern containing a Scan_Load or
Skewed_Scan_Load event, and re-import the patterns to correct the problem.
If user-imported Vectors are not being simulated contact customer support (see

WARNING (TCL-186): [Severe] Pseudo primary inputs were found in the design model,
but no user sequences were provided. The run continues with automatically generated
sequences, but these tests can not be used on the hardware.
EXPLANATION:
only with the help of user-supplied sequences.
Random pattern generation will proceed on an uncommitted basis using automatic
sequences to exercise the pseudo primary inputs. An audit bit is set to alert downstream
(manufacturing) processes that the test data does not include all the primary input stimuli
required to run on a hardware tester.
USER RESPONSE:
User-generated test sequences must be specified for the generated tests to be used on
the hardware. Test sequences must first be coded and imported by selecting File, Import,
Sequence Definition Data. On the General Options screen, under Clocking Sequences,
select Use Manual Sequences and specify Test Sequence Name(s).
INFO (TCL-187): Compile will be done: overriding current measure latch processing.
EXPLANATION:
A recompile is necessary based on the value of the measurelatch parameter.
USER RESPONSE:
ERROR (TCL-189): A event type event specified PI netname (index= hierIndex)

but test function pin flags indicate this PI is not an oscillator. Processing terminates.
EXPLANATION:
The specified PI is not an oscillator according to the test function pin flags. The High
Speed Scan-Based Simulator does not support this event on primary inputs which do not
have an oscillator attribute.
USER RESPONSE:
Check the test sequence. Ensure the PI specified in the event is an oscillator, then rerun.
INFO (TCL-190): The dynamic type constraint placed on netname (index hierIndex)
has been violated.
EXPLANATION:

The simulator detected that the specified model object violated the constraint placed on
it. The test pattern will either be removed or the design fed by the object will be ignored
by simulating X. Message TCL-192 or TCL-193 will describe the action taken as a result
of this violation.
USER RESPONSE:
Determine the cause of the constraint violation and correct it.
NFO (TCL-191): The SDC data will be read from source.

EXPLANATION:
The referenced file contains the SDC data to be read by the program.
USER RESPONSE:
INFO (TCL-192): A constraint violaton has caused portions of the design to be ignored.
EXPLANATION:
One or more constraint violations has resulted in the design fed by the object to ignored
by simulating X. Message TCL-190 describes the constraint violated.
USER RESPONSE:
INFO (TCL-193): A constraint violaton has caused a test pattern to be removed.

EXPLANATION:
One or more constraint violations has resulted in the test pattern in which it was found to
be removed from the Vectors. Message TCL-190 describes the constraint.
USER RESPONSE:
INFO (TCL-194): num tests will be removed due to removeXlatch|removeXPO.

EXPLANATION:
This indicates unknown X is produced at measurable latch or at PO node. if
removeXlatch or removePO is turned on. The test will be removed.
If Channel Masking is available, an X has been propagated to MISR bits, and therefore
the X is not masked out. The test is also removed.

USER RESPONSE:
Verify your command line parameters. Refer to "analyze_vectors in the Encounter
INFO (TCL-195): Clock Choppers will be simulated safe|risky. Pessimistic simulation

will/will not be performed.
EXPLANATION:
By default, Clock Choppers will be simulated safe, pessimistic simulation will be
performed. The default can be overridden by specifying choppers=risky.
USER RESPONSE:
Verify your command line parameters. Refer to "analyze_vectors in the Encounter
INFO (TCL-196): Unknown (X) value was found at netname (index=hierIndex at

odometer). The test sequence will be removed due to removeXlatch / removeXpo.
EXPLANATION:
An unknown (X) value is propagating to an observable latch and is removed to prevent
corruption of a MISR signature in OPMISR mode.
USER RESPONSE:
INFO (TCL-197): Pessimistic simulation will be performed because blank | on

feedbacks because reason.
EXPLANATION:
If Verify Test Structures has been run and TSV001 messages were issued, or if Verify
Test Structures was not run, the default behavior of pessimistic simulation is executed for
the current run.
USER RESPONSE:
If pessimistic simulation is desired, specify feedbacks=risky.
WARNING (TCL-198): Pessimistic simulation on feedbacks will not be performed. The data
might be invalid.
EXPLANATION:

The zero delay simulator does not automatically observe glitches that might cause a
feedback to oscillate and generated vectors with pessimistic simuilation disabled might
contain invalid data.
USER RESPONSE:
If vectors contain invalid data due to disabled pessimistic simulation off, activate
pessimistic simulation by specifying the development keyword needpessfeedback=on
and rerun.
WARNING (TCL-199): The maxscanswitching threshold may be exceeded in some

patterns. The effect of scan overlap on scan switching is estimated during ATPG and a large
percentage of flops (pct) are directly affected by scan overlap. Patterns should be verified
with write_toggle_gram.
EXPLANATION:
When the switching of the scan unload is being evaluated during ATPG, the switching
due to new scan data entering the scan chains is estimated. If the percentage of flops
directly affected by overlapping scan is small (<2%), it should not significantly affect the
overall scan switching of the scan operation. For this design, the number of flops affected
by overlapping scan is large enough to have a non-trivial impact on the early scan cycles
of the scan unload event.
USER RESPONSE:
Once ATPG is complete, you should run write_toggle_gram to identify any patterns
where overlapping the scan unload with the scan load of the next pattern causes the
maxscanswitching threshold to be exceeded. Or, you may run ATPG with a lower
maxscanswitching threshold to allow for the effect of the overlap.

ERROR (TCL-200): Not enough memory to satisfy the request of size of memory bytes.
EXPLANATION:
The system is near OOM (out of memory). The message is issued as an alert that the
process may be terminated due to constrained memory.
USER RESPONSE:
Specify additional keywords to reduce memory usage, such as the expert keyword
maxfaultcopies and rerun.

ERROR (TCL-201): The test sequences in Test Procedure odometer can not be simulated
in parallel since they are non-uniform. Add non-uniform_sequences attribute to the Test
Procedure and rerun.
EXPLANATION:
Test sequences in the same test procedure should be uniform to take gain the advantage
from parallel simulation. Bad data might be produced if test sequences in the same test
procedure are not uniform.
USER RESPONSE:
Verify whether the simulated test sequences are non-uniform. Use one of the following
methods to correct the problem:
Set a non-uniform_sequences attribute on the Test Procedure.
Specify the keyword value force1tseq=yes to force the simulator to do serial
simulation. This keyword is primarily intended for use by Encounter Test
development.
Regroup the test sequences to result in all test sequences being uniform in a
particular test procedure.
INFO (TCL-202): Good circuit simulation will be done using number_of_threads

threads.
EXPLANATION:
This message states the number of threads to perform multi-threading on good circuit
simulation.
USER RESPONSE:
NFO (TCL-203): Faulty circuit simulation will be done using number_of_threads

threads.
EXPLANATION:
This message states the number of threads to perform multi-threading on faulty circuit
simulation.
USER RESPONSE:
INFO (TCL-205): Start the TCL Simulator.

EXPLANATION:
High-Speed Scan Based simulation has begun.
USER RESPONSE:
INFO (TCL-206): removeXlatch is set to be off|on.

EXPLANATION:
When removeXlatch=on is specified, the simulator removes the test sequence which
generates an "X" in the scan chain. Otherwise, the simulator ignores the test sequence.
USER RESPONSE:
(TCL-207):
INFO removeXpo is set to be off|on.
EXPLANATION:
When removeXpo=on is specified, the simulator removes the test sequence which
generates an "X" on any measurable PO. Otherwise, the simulator ignores the test
sequence.
USER RESPONSE:
INFO (TCL-208): Faults will/will not propagate through measure latches.

EXPLANATION:
If measurelatch=normal is specified, and a fault effect propagates to a measurable
latch, either the fault is marked tested if detecting the condition is met. (e.g. fault effect
on a SML and there is a measurelatch event following), or the fault effect will be wiped
out if the fault is not marked tested for the current event.
If measurelatch=sequential is specified, a fault copy is kept if the fault is not marked
as tested on a measurable latch. The fault copy will be kept for a subsequent fault
simulation. Specifying measurelatch=sequential will improve the accuracy but will
also increase the running time.
USER RESPONSE:
Specify measurelatch=sequential to achieve an accurate test coverage..

INFO (TCL-209): All valid keeper devices are active.

EXPLANATION:
This message states status for all valid keeper devices.
USER RESPONSE:
INFO (TCL-210): Valid glitch-free keeper devices are active.

EXPLANATION:
This message states status for valid glitch-free keeper devices.
USER RESPONSE:
INFO (TCL-211): No keeper devices are active.

EXPLANATION:
This message states keeper device status.
USER RESPONSE:
INFO (TCL-215): Sequential elements will be reset at each Test Sequence.

EXPLANATION:
The sequential element (memory element) will be reset to some reset value at the
boundary of each Test Sequence.
USER RESPONSE:
(TCL-216):
INFO A tester termination of 0|1 will be used.
EXPLANATION:
The stated tester termination value is being used.
USER RESPONSE:

INFO (TCL-217): The tester termination will dominate.

EXPLANATION:
This message states that tester termination will be dominant.
USER RESPONSE:
INFO (TCL-218): number tests will be removed since Xs have already propagated into
MISR bits before generating Channel Masking Bits.
EXPLANATION:
The tests the simulator is currently simulating generate "X". The "X" has already
propagated into MISR latches before generating Channel Masking Bits. The tests are
removed to prevent corruption of the MISR signatures.
USER RESPONSE:
INFO (TCL-219): number tests will be removed since the Channel Masking Bits were not
generated. See preceding message.
EXPLANATION:
The simulator has detected X in the scan channel, but Channel Masking Bits cannot be
correctly generated. The simulator will remove those tests in order to prevent the
corruption of the MISR signature.
USER RESPONSE:
INFO (TCL-220): Invoking 2-pass simulation.

EXPLANATION:
The High Speed Scan Based simulator will invoke 2-pass simulation in following
conditions:
If contentionremove=yes is specified and there is potential burnout
(gmonly=no).
If removeXlatch=yes or removeXpo=yes and gmonly=no () are specified.

For OPMISR parts, removeXlatch defaults to yes.

If Channel Masking is available (for OPMISR+ parts).
USER RESPONSE:
WARNING (TCL-221): There are Xs in the scan chain, but the channel masking data was
not generated.
EXPLANATION:
The simulator detected Xs in the scan chain, but channel masking data was not
generated due to either:
Channel masking data cannot be correctly generated.
xmask is set to update, however there is no channel masking data in the input.
experiment.
USER RESPONSE:
Specify xmask=yes to generate channel masking data.
INFO (TCL-222): number tests will be removed due to linehold violations.

EXPLANATION:
A linehold was not honored in the stimulus at a PI or latch. The test will be removed. It is
not always possible to honor latch lineholds for compression testmodes with input
decompression.
USER RESPONSE:
No response is required unless too many tests are being dropped. In that case, re-
examine the linehold set. With input decompression, lineholds contained within one scan
register are easier to solve.
WARNING (TCL-223): Linehold violation at netname (index=hierIndex at

odometer).
EXPLANATION:
A linehold was not honored in the stimulus at a PI or latch. This may occur on
compression testmodes with input decompression.
USER RESPONSE:

WARNING (TCL-226): The Encounter ATPG simulation option

simtype=simulation_type in the vector file cannot honor the specified fault subset.
Simulation continues without the fault subset.
EXPLANATION:
Fault subset lists are only supported by specifying simtype=eventdriven with
flatsim=yes. The specified simtype option in the input vector was compiled or
interpretive.
USER RESPONSE:
Ignore this message if running without a fault subset is acceptible. Otherwise, rerun
without specifying useatpgsimoptions=yes.
WARNING (TCL-226): The Encounter ATPG simulation option

simtype=simulation_type in the vector file can not honor the specified fault subset.
Simulation continues without the fault subset.
EXPLANATION:
A simtype option of either compiled or interpretive was specified and neither
supports a fault subset list. simtype=eventdriven supports a fault subset list.
USER RESPONSE:
Ignored this message if running without a fault subset is acceptible. Otherwise, rerun
without specifying useatpgsimoptions=yes.
INFO (TCL-227): Processing faults that do not meet small delay test thresholds.
EXPLANATION:
Encounter Test has marked those tested faults that were detected during simulation but
did not meet the small delay test thresholds (ndetect, percentpath, or simsdql).
USER RESPONSE:
If you want these faults left as untested, specify marksdfaultstested=no and rerun
the command. Otherwise, no action is required.
ERROR (TCL-300): Stim a value Z on netname (index=hierIndex) which is not

allowed at TBD Loc odometer. Simulation terminates.
EXPLANATION:
Only a strong value is allowed on a net; a weak value is stimmed.
USER RESPONSE:

Check the stim value, correct it, and rerun.
INFO (TCL-301): Maximum fault machine X size of maxFaultXsize will be used.

EXPLANATION:
Allow maxfaultxsize nodes to be X when propagating a fault before dropping it. The
default size is 1000. Decreasing the default size may lower the overall Test Coverage.
Increasing the default size may significantly increase the running time.
USER RESPONSE:
Decrease the maxfaultxsize if the running time is excessive and test coverage is not
a primary consideration. Increase the maxfaultxsize if the test coverage is too low
due to an excessive number of dropped faults.
INFO (TCL-302): Patterns with 3-state contention will NOT be removed.

EXPLANATION:
Patterns with 3-state contention will be written into the output experiment. Specify
writepatterns=all to retain patterns with three-state contention violations.
USER RESPONSE:
To remove patterns with violating three-state contention violations, specify
contentionremove=yes.:
ERROR (TCL-304): Unsupported block type in function functionName,

nodeid=nodeID. Simulation terminates.
EXPLANATION:
The node is not a supported block type in this function. Such as a latch is not supported
in the specific simulation function. nodeid=0 is not supported in any function.
USER RESPONSE:
Determine whether a GMcompiled* or FMcompiled* file exists in the part directory.
Remove the file(s) and rerun.
ERROR (TCL-307): Cant allocate number byte memory for pointerName. Simulation
terminates.
EXPLANATION:
This message indicates that insufficient memory is available to run the application.
USER RESPONSE:

Verify whether sufficient memory is available on the current workstation. If necessary,

rerun the job on a workstation with more memory.
INFO (TCL-308): Latch/Flip-Flops are simulated to X when clock at X.

EXPLANATION:
Latches and Flip-Flops will be pessimistically simulated when the clocks of those
elements are at X.
USER RESPONSE:
No response is required needed if pessimistic simulation on latches is expected.
Otherwise, change the latchsimulation keyword specification to optimistic or
remove the keyword from the command string and rerun.
INFO (TCL-309): Measure Points will be ignored if the input data of those points at X.
EXPLANATION:
If the measure points are at "X" in the input data, the corresponding measurable points
will be ignored for measurement and marking off faults.
USER RESPONSE:
No response is required needed if ignoring of measures when input data are "X" is
expected. Otherwise, set the keyword ignoremeasureinputx to no or remove the
keyword from command line and rerun.
WARNING (TCL-401): [Severe] number of active clock primary inputs or

PPIs clock inputs were active during an Event type event at TBD location odometer.
Simulation will be done with the clocks overlapped. The results may be incorrect if there are
races in the design.
list of violating clocks
EXPLANATION:
Patterns have been detected which activate multiple clock inputs simultaneously. The
offending event which resulted in multiple active clocks is indicated, but may not itself
contain multiple clocks (in which case it must have been preceded by another event
which stimmed a clock active). For cases in which multiple clocks are pulsed
simultaneously within the same event, Encounter Test does not do any timing verification
to ensure the clock pulses will actually overlap in the logic. Encounter Test will simulate
the logic with the clocks on simultaneously, but this may produce incorrect results if the
clocks do not actually overlap. A listing of violating clocks is included at the end of the
message.

USER RESPONSE:
There are two approaches that can be taken:
a. If the clocks are not required to be on simultaneously, the input patterns can be
modified to serially activate and deactivate the clocks.
b. If the clocks are required to be overlapping to produce the correct results, verify that
the timing of the common logic ensures that the clocks are overlapped so that the
simulators predicted results will match the actual hardware.
WARNING (TCL-402): number of active clock primary inputs or PPIs

clock inputs were active during a odometer event @ TBD location odometer . Simulation
will be done with the clocks overlapped. The results may be incorrect if there are races in the
design.
EXPLANATION:
which stimmed a clock active). For cases in which multiple clocks are simultaneously
pulsed within the same event, Encounter Test does not do any timing verification to
ensure the clock pulses will actually overlap in the logic. Encounter Test will simulate the
logic with the clocks on simultaneously, but this may produce incorrect results if the
clocks do not actually overlap.
The violating clocks are listed at the end of the message.
USER RESPONSE:
Use either of the following methods and rerun if necessary:
If the clocks are not required to be simultaneously on, the input patterns can be
If the clocks are required to be overlapping to produce the correct results, verify
that the timing of the common logic ensures that the clocks are overlapped so
that the simulators predicted results will match the actual hardware.
WARNING (TCL-450): Pattern fault index fault index was unable to be injected due to
an unknown or unsupported required value. This fault will not be simulated.
EXPLANATION:
This message indicates either an unsupported required value specification for a pattern
fault or a programming error.

USER RESPONSE:
Examine the fault specification to ensure that the required values are supported within
the pattern fault specification documentation. See "Fault Rule Syntax" in the Encounter
Test: Guide 4: Faults . If this is the case, then please contact customer support (see
ERROR (TCL-470): An illegal force event was encountered on netname (index=

hierIndex). The High Speed Scan-Based Simulator can only support force events on
stable latches. Processing terminates.
EXPLANATION:
The High Speed Scan-Based Simulator is limited in its processing of force events
because it is a compiled logic simulator.
USER RESPONSE:
Ensure that the force events are limited to stable latches. If this is not possible, it may be
necessary to use the general purpose simulator.
ERROR (TCL-471): An illegal force event was encountered on latch netname (index=
hierIndex). The High Speed Scan-Based Simulator does not support the hold attribute.
EXPLANATION:
The High Speed Scan-Based Simulator is limited in its processing of force events
because it is a compiled logic simulator. It cannot hold a force value in a latch.
USER RESPONSE:
Remove the hold attribute from the force event. If this is not possible, it may be necessary
to use the general purpose simulator.
WARNING (TCL-520): Unable to create the diagnostic testset failset name. No

TBDfail file will be produced by this run. Ensure that the design parameters specified are
correct, that there is sufficient space in the file system and that file permissions are set
correctly.
EXPLANATION:
The Encounter ATPG simulation options in the vector file must have the simulation
keyword as the first keyword in the keyed data. This enables verification that the current
simulator is the same as the ATPG simulator. If not matched, the rest of the options in
SimOptions are not relevent and will invalidate the run. SimOptions keyed data must
have been edited and imported back into vector format in order for this problem to occur.

USER RESPONSE:
Ensure that the specified design parameters are correct, that there is sufficient space in
the file system and that file permissions are set correctly. If problems persist, contact

ERROR (TCL-622): No simulation options keyed data found in the vector file for Test Section
test_section.
EXPLANATION:
The use of Encounter Test ATPG simulation options was requested, however there are
no simulation options in the vector file for the indicated test section. The run terminates.
RESPONSE:
Rerun with useatpgsimoptions=no specified.
ERROR (TCL-623): ATPG sim options stored in the vector file (Test Section
test_section) contains simulation=simulator in SimOptions keyed data but
the current run is simulator=simulator for the current run.
EXPLANATION:
The Encounter Test ATPG simulation options in the vector file for the indicated test
section is not the same as the simulator being used for the current run. When specifying
useatpgsimoptions=yes, the simulator selected for the run must be the same as the
simulator used during Encounter ATPG run.
RESPONSE:
Rerun with useatpgsimoptions=no specified or change the simulator to match the
simulation technique that was specified for the simoptions keyword.
ERROR (TCL-624): ATPG simulation option, keyword=current test sectionss

keyword value is stored in Test Section current_test_section. This value is
inconsistent with keyword=first test sectionss keyword value, found in
Test Section first test section in test range.
EXPLANATION:
The Encounter Test ATPG simulation options in the vector file are inconsistent between
the indicated test sections located in the specified test range. When specifying

useatpgsimoptions=yes, certain simulation options must be the same across test

sections in order to be processed in a single run.
RESPONSE:
Either rerun with useatpgsimoptions=no specified or specify a test range with
consistent keyword values..
ERROR (TCL-625): ATPG simulation option in Test Section test_section does not
contain simulation as the first keyword.
EXPLANATION:
The Encounter ATPG simulation options in the vector file must have the simulation
keyword as the first keyword in the keyed data. This enables verification that the current
simulator is the same as the ATPG simulator. If not the same, the rest of the options in
SimOptions invalidate the run. SimOptions keyed data must have been edited and
imported back into vector format in order for this problem to occur.
RESPONSE:
Ensure that simulation is the first keyword in SimOptions and rerun..
ERROR (TCL-626): The accumulated number of faults polling from each gates is larger than
the total faults (total number faults) available in the fault model, simulation will terminate.
EXPLANATION:
The accumulated number of faults polling from each gates is larger than the total number
the simulator detects from the fault model utility. This usually means the fault model or
fault status file is corrupted. The simulation cannot continue since it may leading to a core
dump.
RESPONSE:
Review the methodology to determine which step is corrupting the fault model/fault
status file and report this to customer support. Refer to Contacting Customer Service
on page 23.
WARNING (TCL-700): A good machine oscillation was detected on net netname at TBD
location tbd_location. The good machine logic value is set to X on this net.
EXPLANATION:
The referenced net changed value more times than the specified Good Machine
Oscillation limit (the specified value for the gmosc keyword), for a single event. Tthis
typically indicates that the referenced net is part of an oscillating feedback circuit.

In rare cases, the referenced net may not actually be oscillating and may legitimately
need to change value more times than specified with the gmosc keyword.
USER RESPONSE:
Increase the specified value for the gmosc keywordif it appears that the design cannot
oscillate. The highest allowed is 65535.
Note: Simulation runtime may increase when this value is increased.
WARNING (TCL-710): [Severe] One or more miscompares were detected for the event
type event at TBD location odometer.
EXPLANATION:
This message indicates that miscompares have occurred between expected design
states expressed in the input TBD patterns vs. design states predicted by the High Speed
Scan-Based Simulator.
The event type field in the message indicates the kind of event at which the miscompare
occurred. The tbd loc field gives the hierarchical location in the output TBD patterns
where the miscompare occurred. The miscompare data will be presented in the following
format:
@ Net netname (index=nodeid) - Expected: logic val Found: logic val
The Expected logic val is the value that was predicted in the input TBD event. The Found
logic val is the value that the High Speed Scan-Based Simulator achieved.
USER RESPONSE:
A miscompare message may or may not warrant further investigation, depending on the
source of the input patterns and the reason for performing the simulation. In most cases
miscompare messages do warrant investigation to determine their cause.
WARNING (TCL-711): [Severe] One or more miscompares were detected for the event
type event at relative TBD location odometer.
EXPLANATION:
states expressed in the input TBD patterns vs. design states predicted by the High Speed
Scan-Based Simulator.
occurred. The tbd loc field gives the relative location in the input TBD patterns where
the miscompare occurred. The location is based on the order the events have been
simulated.

For example, if sequences are being simulated in reverse order the location will not
match the location on the input. To make it easier to locate a miscomparing event use
good machine simulation in the forward direction. The miscompare data will be
presented in the following format:
@ Net netname (index=nodeid) -
Expected: logic val Found: logic val
The Expected logic val is the value that was predicted in the input TBD event. The Found
logic val is the value that the High Speed
Scan-Based Simulator achieved.
USER RESPONSE:
source of the input patterns and the reason for performing the simulation. In most cases
miscompare messages do warrant investigation to determine their cause.
INFO (TCL-713): Input measure values of X will be ignored|used for compares.

EXPLANATION:
If ignored, and the measure value from input vector is "X", the simulator will ignore the
compare against the output measure value. If used, the simulator will compare the input
and output measure value regardless of the content of the input vector.
USER RESPONSE:
INFO (TCL-714): A TBDfail file will not be produced for detected miscompares.
EXPLANATION:
By default, a TBDfail file is not generated when output measure data miscompares with
the input measure data.
USER RESPONSE:
INFO (TCL-730): Fault # fault index was dropped for exceeding maximum type of
limit.
EXPLANATION:
A faultXsize is the number of nets on which the faulty logic value is all X and differs from
good machine value. Each such difference costs runtime.

A faultsize is the number of nets on which the faulty logic value differs from the good
machine logic value. Each difference costs runtime.
The named faults size exceeded the faultXSize/faultsize limit and was dropped from the
simulation. The fault will no longer be eligible to be detected by this simulation run. By
dropping faults of this type, significant simulation performance gains may be achieved.
USER RESPONSE:
Typically, none. If you are concerned that the dropped faults may be affecting your test
coverage, you can increase the maxfaultxsize and/or maxfaultsize parameter
and run the simulation again. These keywords are described in the "analyze_vectors
section of the Encounter Test: Reference: Commands.
ERROR (TCL-800): Input pattern error encountered. The Begin Loop pattern at TBD
location odometer contains no repeat event to specify the number of loop iterations.
Processing terminates. Correct the pattern and run the simulation again.
EXPLANATION:
See the message text.
USER RESPONSE:
Correct the pattern to contain a specification of how many loop iterations should be
performed.
INFO (TCL-802): number of MultiPulse events TBD MultiPulse events were simulated.
EXPLANATION:
When there are multiple clock pulses in a single event, they are simultaneously
simulated. If the clock PIs being pulsed are correlated (have a relationship defined with
the CORRELATE attribute) it is assumed that they must be simultaneously
simultaneously so this message is not printed. However, if the clock PIs are not
correlated (non-correlated), pulsing more than one at the same time may produce
unexpected results. The simulation will not account for delays in the clock trees, and son
on, to predict the order of the clocks arrival at the flops. Therefore, if there are any flop-
to-flop paths between the clock domains the results cannot be accurately predicted.
USER RESPONSE:
If the order of the clock pulses is significant, ensure the pulses are in separate events
and rerun if necessary.
ERROR (TCL-805): Input pattern error encountered. The Begin Loop pattern at TBD
location odometer contains an event other than the repeat event.

This is an invalid construct. Processing terminates. Correct the pattern and run the
simulation again.
EXPLANATION:
USER RESPONSE:
Remove the erroneous event from the pattern and ensure that a repeat event is
specified.
ERROR (TCL-806): Input test sequence limitation encountered. There is a loopable test
sequence at TBD location odometer. Its test procedure includes additional test sequences.
The High Speed Scan-Based Simulator requires that a loopable test sequence be the only
test sequence in the test procedure. Processing terminates. Correct the test procedure and
run the simulation again.
EXPLANATION:
USER RESPONSE:
Ensure that a loopable test sequence has no other test sequences in its containing test
procedure.
ERROR (TCL-807): Input test sequence limitation encountered. There is a sequence at

TBD location odometer which contains a pattern loop. Its test procedure includes additional
test sequences. The High Speed Scan-Based Simulator requires that this test sequence be
the only test sequence in the test procedure. Processing terminates. Correct the test
procedure and run the simulation again.
EXPLANATION:
USER RESPONSE:
Ensure that the test sequence with the pattern loop has no other test sequences in its
containing test procedure.
WARNING (TCL-808): The event type Expect is not processed at TBD location odometer.
This event was found in your input test patterns and cannot be simulated in the high speed
scan simulator. Use simulation=gp to verify your test sequences with this event.
EXPLANATION:

The Expect event type was found in the input pattern set, but will not be processed by
the high speed scan simulator. The event will be transferred intact to the output
experiment, but no checking of expected values will be performed for this event. This will
not affect your fault coverage. In order to make use of the functionality of this event, you
must rerun with simulation=gp.
USER RESPONSE:
No response is required. If you wish to verify the expected values using the Expect event,
then rerun with simulation=gp specified on the command line to select a different
simulation engine.
WARNING (TCL-838): [Severe] number of Pulses in the event uncorrelated

inputs were pulsed in a event type TBD event. They were simulated in
parallel(overlapped) order. The simulation results may be wrong if the clocks are not
independent.
EXPLANATION:
The TBD patterns contain an Event which pulses more than one clock at the same time.
The programt does not perform timing verification to ensure that the clock pulses may
overlap in the logic. The program will simulate the logic with the clocks on simultaneously,
but the results may be wrong if the clocks are not supposed to overlap.
USER RESPONSE:
If the clocks are not required to be on simultaneously, the pulses can be serialized by
putting them into separate events.
If the clocks are required to be on simultaneously, verify that the timing of the common
logic ensures that the simulated results will match the hardware.
INFO (TCL-841): There is a sequence at TBD location odometer which does not contain
any target fault information and measures=targeted was specified. Since it cannot be
determined which measure points are being targeted by this sequence, all measures will be
recorded.
EXPLANATION:
The TBD patterns contain a sequence without target fault information. One use of this
information is to identify to simulation which measurable nets in the cicuit are being
targeted by this sequence. Without this information, simulation will record expect values
and (if fault simulating) detect faults at all measurable points on this sequence.
USER RESPONSE:
Certain test sequences such as the scan chain tests or the shorted nets test do not
contain target fault information. Therefore this message is expected for these sequences

if measures=targeted is specified. If this is a resimulation of existing patterns which

were imported from report_vectors output, ensure that report_vectors was run
with targetfault=yes specified.
WARNING (TCL-855): A non-three-state PI is stimmed to an illegal value. The stim value of

Z has been converted to X. The PI is netname (index=hierIndex).
EXPLANATION:
A primary input stimulus value was encountered that was Z. It is converted to X. The
output TBD file will contain the original stim value and not the assumed X.
USER RESPONSE:
If the patterns were manually generated, ensure that the stim value conversion is
acceptable. If not, change the stim value to an explicit legal value. If these patterns were
generated by a Encounter Test automatic test generator, please contact customer
WARNING (TCL-870): There are active clock oscillators at the end of a setup sequence.
These clocks will be set to X at the beginning of each subsequent test sequence, regardless
of any event that may set them to a known value during any test sequence.
EXPLANATION:
One or more clocks were the subject of a Start_Osc event in the setup sequence for the
current test procedure, causing them to become active oscillators. The oscillators on
these clocks, however, were not all deactivated (via a Stop_Osc, stim or pulse event)
prior to the end of the setup sequence. Since sequences do not have memory for this
test procedure, oscillating clocks will be set to X at the start of each test sequence, even
if they are stimmed or deactivated during the course of some test sequence. This is
necessary because these test sequences may be run in any order at the tester.
USER RESPONSE:
Ensure that you really wished to leave the clock oscillator active at the end of the setup
sequence. If not, change the setup sequence to correct the situation.
ERROR (TCL-871): An error occurred during processing of a setup sequence. There was
an active clock oscillator when an event requiring a scan operation was encountered.
Processing terminates. Correct the setup sequence and run the simulation again.
EXPLANATION:
One or more clocks were the subject of a Start_Osc event in the setup sequence for the
current test procedure, causing them to become active oscillators. The oscillators on
these clocks, however, were not all deactivated (via a Stop_Osc, stim or pulse event)

prior to an event requiring a scan operation. In order to ensure that the design scans
correctly the High Speed Scan-Based Simulator requires that all clocks be at their
stability value when a scan operation is invoked.
USER RESPONSE:
Change the setup sequence to correct the situation.
WARNING (TCL-911): [Severe] Error parsing options. keyword=value is not valid.

EXPLANATION:
The simulator was invoked with the specified invalid option.
USER RESPONSE:
Either omit the option, or specify an allowed value.
INFO (TCL-998): Stack Size on this machine is limitation, usually for large circuits.
Simulation needs unlimited stack size to finish initialization.
EXPLANATION:
An unlimited stack size is needed to backtrace large circuits for recursive calls. if the
stack size is small, you might get a core during the initialization of High Speed Scan
Based simulation (hsscan).
USER RESPONSE:
Typically, no response is required. If a core does occur, check the stack size. If required,
use ulimit to the set stack size to unlimited and rerun.
INFO (TCL-999): Exception message summary

EXPLANATION:
The messages that follow are the summary of the issued exception messages during the
run.
USER RESPONSE:
Analyze each exception to determine if you need to change the patterns, test generation/
simulation keywords, the testmode, or the design to remove the condition that caused it.
See the extended help for the individual messages for more information. Refer to
Extended Message Help on page 35.


15
TCT - Test Data Core Messages
TCT-001 through TCT-108 on page 373

TCT-110 through TCT-580 on page 381
TCT-001 through TCT-108

WARNING (TCT-001): [Severe] The TCT function, function, could not find file
filename.
EXPLANATION:
create_macro_tests attempted to open the file listed but the file does not exist.
USER RESPONSE:
Determine the reason (wrong workdir, testmode, path, etc.), correct and rerun.
WARNING (TCT-002): [Severe] The TCT function, function, could not write data to file
filename.
EXPLANATION:
create_macro_tests attempted to write data to the listed file but could not.
USER RESPONSE:
Determine the reason (wrong file, missing file, etc.), correct and rerun.
WARNING (TCT-003): [Severe] The TCT function, function, could not read data from
file filename.
EXPLANATION:
The function was unable to read from the file listed. Processing terminates.

USER RESPONSE:
WARNING (TCT-004): [Severe] The TCT function, function, could not close file
filename.
EXPLANATION:
The function was unable to close the file listed. Processing terminates.
USER RESPONSE:
WARNING (TCT-005): [Severe] The TCT function, function, could not verify the file
header in file filename.
EXPLANATION:
The file header may have been created with an old version of a Encounter Test
application that used an out of date file header format. For example, the
MacroIsolationbin file may have been created with an old version of Verify Macro
Isolation.
USER RESPONSE:
Obtain the correct version of the application that created the specified file and rerun.
WARNING (TCT-010): [Severe] The file, filename, is not registered in globalData and
therefore cannot be accessed.
EXPLANATION:
The MacroIsolationbin Verify Macro Isolation output file was not registered.
USER RESPONSE:
Determine why the file is not registered and rerun.
WARNING (TCT-011): [Severe] The file, filename, is not writeable, therefore the results
of this TCT run cannot be saved.
EXPLANATION:
The permission bits for this file are not set to write.
USER RESPONSE:

The file owner must set the appropriate permission bits to make the file writeable before
create_macro_tests can be rerun.
WARNING (TCT-012): [Severe] The file, filename, is not readable, therefore the results
of this TCT run cannot be saved.
EXPLANATION:
The permission bits for this file are not set to read.
USER RESPONSE:
The file owner must set the appropriate permission bits to make the file readable before
ERROR (TCT-013): [Internal] The master filename for the file filename could not be
constructed.
EXPLANATION:
This is most likely a program error.
USER RESPONSE:
WARNING (TCT-015): [Severe] The directory, directoryname, is not writeable,

therefore the results of this TCT run cannot be saved.
EXPLANATION:
The permission bits for the directory are not set to write.
USER RESPONSE:
The directory owner must have the appropriate permission bits set to make the directory
writable.
WARNING (TCT-016): [Severe] The directory, directoryname, is not readable,

therefore the results of this TCT run cannot be saved.
EXPLANATION:
The permission bits for the directory are not set to read.
USER RESPONSE:
readable.

ERROR (TCT-018): [Internal] The directory name could not be constructed using
PROJECT = projectname, PARTID = partid
EXPLANATION:
USER RESPONSE:
ERROR (TCT-020): [Internal] A non-zero return code was returned from Encounter Test
(TBD) function function. TCT processing terminates.
EXPLANATION:
USER RESPONSE:
WARNING (TCT-022): [Severe] No isolation data exists in the MacroIsolationbin file.

EXPLANATION:
The Verify Macro Isolation run failed before any isolation data could be generated.
USER RESPONSE:
Create valid isolation data and rerun Create Macro Tests.
WARNING (TCT-024): [Severe] No group(s) to process.

EXPLANATION:
None of the groups specified by the selectgroup option exist in the isolation data or
the isolation data did not contain any groups. Processing terminates.
USER RESPONSE:
Correct the group number(s) in the selectgroup option. To print a list of valid group
numbers, run create_macro_tests with the printgroups option. The resulting
group numbers are the valid group numbers which can be used with the selectgroup
option.
WARNING (TCT-040): [Severe] No TDM files were found to be processed.

EXPLANATION:

The name of a macrotest data file must be specified using the tdminput keyword or a
directory name containing macro test data files must be specified using the tdmpath
keyword.
USER RESPONSE:
Ensure the complete path and file name of the file containing the macro test data or the
directory name containing macro test data files is specified on the command line.
WARNING (TCT-050): [Severe] No TDM file name was found for macro macroname,
algorithm algname.
EXPLANATION:
When using the tdmpath keyword, a model attribute on the macro must exist which
contains the algorithm name and test data file name.
USER RESPONSE:
Check that a model attribute for this macro exists and contains the correct algorithm
name and test data file name.
WARNING (TCT-052): [Severe] TDM filename was found for macro macroname,
algorithm algname.
EXPLANATION:
The tdmpath keyword combined with the test data file name from the macros model
attribute for this algorithm formed a fully qualified path name to a file which does not exist.
USER RESPONSE:
Ensure the tdmpath value entered on the command line is correct and that the file
containing the test data for this macro exists.
WARNING (TCT-054): [Severe] No TDM files were found for any of the macros in group
groupname, algorithm algname.
EXPLANATION:
None of the macro test data files were found using the tdmpath keyword and test data
file names retrieved from the macros model attribute.
USER RESPONSE:
Check that the tdmpath is correct and that the macro test data files reside in the
directory.

INFO (TCT-060): Processing group groupnum, algorithm algname, TDM file(s):

filenames.
EXPLANATION:
This informational message provides the group number, algorithm name, and a list of
TDM files that will be processed for this group number.
USER RESPONSE:
WARNING (TCT-062): [Severe] Unable to open or process TDM file tdmfile.

EXPLANATION:
The program was unable to open a TDM file or was not able to process the file data.
USER RESPONSE:
If using the tdminput keyword, ensure that a fully qualified macro test data file name
was entered, the file exists in the directory, and the directory has read permission.
If using the tdmpath keyword ensure the path directory is correct and has read
permission.
If the file is corrupt, re-create the file using supported processes.
WARNING (TCT-070): [Severe] No PI Vector Application Objects.

EXPLANATION:
Each macro test data file should contain information about the input pins on the macro.
This information does not exist in the macro test data file being processed.
USER RESPONSE:
Ensure the correct macro test data file name is being processed from preceding
messages and that the macro test data file is of the structure neutral format.
WARNING (TCT-072): [Severe] No PO Vector Application Objects.

EXPLANATION:
Each macro test data file should contain information about the output pins on the macro.
This information does not exist in the macro test data file being processed.
USER RESPONSE:

Ensure the correct macro test data file name is being processed from preceding
messages and that the macro test data file is of the structure neutral format.
WARNING (TCT-080): [Severe] The input pin pinname does not have a correspondence
pin.
EXPLANATION:
The macro test data requires that a stim value be applied to this pin on the macro but the
pin does not have a corresponding pin on the package that can be used to apply the
value to the macro.
USER RESPONSE:
Ensure the macro input pin is listed in the Macro Isolation Control file for the algorithm
being processed and that the pin was successfully isolated.
WARNING (TCT-082): [Severe] The output pin pinname does not have a correspondence
pin.
EXPLANATION:
The macro test data requires that this pin on the macro be measured but the pin does
not have a corresponding pin on the package that can be used to measure the value.
USER RESPONSE:
Ensure the macro output pin is listed in the Macro Isolation Control file for the algorithm
WARNING (TCT-090): [Severe] A suitable operation was not found for event event. This
event will not be processed.
EXPLANATION:
There is no operation that has correspondence for all pins exercised in this event.
USER RESPONSE:
Ensure that all pins exercised in this event are in the same operation in the Macro
Isolation Control file and that all pins were successfully isolated.
WARNING (TCT-092): [Severe] A suitable operation was not found for events
startevent through endevent. These events will not be processed.
EXPLANATION:
There is no operation that has correspondence for all pins exercised in these events.

USER RESPONSE:
Ensure that all pins exercised in these events are in the same operation in the Macro
WARNING (TCT-100): [Severe] Pin pinname was stimmed to Z in event event but the
pin is not a bidirectional pin.
EXPLANATION:
A pin must be defined as an input pin and an output pin in the macro test data before it
can be classified as a bidirectional pin. Only bidirectional pins can be stimmed to a value
of Z.
USER RESPONSE:
Ensure that the macro test data was created with this pin functioning as a bidirectional
pin and that the correct test data file is being used.
WARNING (TCT-102): [Severe] A correspondence pin was not found for pin pinname
which was stimmed to Z in event event, operation operation.
EXPLANATION:
To ensure that a macro pin required to be set to a Z is not driven to a value by the
package, an output correspondence pin is required. If none is found, the stim Z on this
pin is ignored.
USER RESPONSE:
For macro pins that are stimmed to a Z in the macro test data, ensure that an operation
exists that has output correspondence for these pins.
WARNING (TCT-104): [Severe] A correspondence pin was not found for pin pinname
which was measured at Z in event event, operation operation.
EXPLANATION:
The macro test data requires that this pin be measured to a Z but the pin does not have
a corresponding pin on the package that can be used to measure this value.
USER RESPONSE:
Ensure the macro output pin is listed in the Macro Isolation Control file for the operation
WARNING (TCT-106): [Severe] An input correspondence pin or required pin was not found
for pin pinname in event event, operation operation.

EXPLANATION:
The macro test data requires that this pin be stimmed to a value but the pin does not have
a corresponding pin on the package or a required pin with the same value that can be
used.
USER RESPONSE:
Ensure the macro input pin is listed in the Macro Isolation Control file for the operation
WARNING (TCT-108): [Severe] An output correspondence pin or assumed value pin was
not found for pin pinname in event event, operation operation.
EXPLANATION:
The macro test data requires that this pin be measured at a value but the pin does not
have a corresponding pin on the package or an assumed value pin with the same value
that can be used.
USER RESPONSE:
Ensure the macro output pin is listed in the Macro Isolation Control file for the operation
TCT-110 through TCT-580

WARNING (TCT-110): [Severe] The event type eventtype is not supported.
EXPLANATION:
This event type is not supported by MacroTest.
USER RESPONSE:
Ensure that the macro test data was created using only supported processes. If the event
type referred to in the message was created by a supported process, contact customer
WARNING (TCT-112): [Severe] The event type eventtype is not supported in the
macros modeinit sequence.
EXPLANATION:
The macros modeinit sequence is limited to a subset of event types. The event type
called out in the message is not included in this subset.

USER RESPONSE:
macros scanop sequence.
EXPLANATION:
The macros scanop sequences are limited to a subset of event types. The event type
USER RESPONSE:
macros test data.
EXPLANATION:
Macro Test does not support this event type.
USER RESPONSE:
WARNING (TCT-118): The scan event event_type at event event is within a pattern
loop.
EXPLANATION:
A scan event has been added to the output after a begin loop pattern and before the end
loop pattern. Scan events within loops can severely impact test time.
USER RESPONSE:
Ensure the macro pins that change states within the pattern loop do not have latch
correspondence. This may require that the correspondence requirements for these pins
in the Macro Isolation Control (MIC) file be changed to CORRESP_TYPE=PIPO.
WARNING (TCT-120): [Severe] Unable to process eventtype event event due to

missing correspondence pins.

EXPLANATION:
USER RESPONSE:
Ensure that all pins exercised in this event are in a single operation in the Macro Isolation
Control file and that all pins were successfully isolated.
WARNING (TCT-130): [Severe] One or more measure Zs were encountered in event

event. These pins will be ignored.
EXPLANATION:
The measuring of a Z value at the macro pin can only be accomplished if the pin is
directly connected to a corresponding pin on the package.
USER RESPONSE:
Currently, the measuring of a Z value in the macros test data is not supported.
WARNING (TCT-140): [Severe] Shared pins pinname and pinname are stimmed to
different values in event event.
EXPLANATION:
Two macro pins share the same correspondence pin on the package but the macro test
data requires them to be stimmed to different values.
USER RESPONSE:
Remove the share keyword from the pinname statement for the pins in question.
WARNING (TCT-142): [Severe] Pin pinname was pulsed without shared pin pinname
being pulsed in event event.
EXPLANATION:
data requires one to be pulsed without the other one being pulsed.
USER RESPONSE:
WARNING (TCT-144): [Severe] Shared pins pinname and pinname were pulsed to
EXPLANATION:

data causes them to be pulsed to different values.
USER RESPONSE:
WARNING (TCT-150): [Severe] Latch correspondence in the macro modeinit sequence for
event type eventtype is not supported.
EXPLANATION:
Latch correspondence to exercised pins in the modeinit sequence is not supported.
USER RESPONSE:
Choose the PIPO correspondence type in the Macro Isolation Control file for all
exercised pins in the macros modeinit sequence.
WARNING (TCT-152): [Severe] Latch correspondence in a scanop sequence for event

type eventtype is not supported.
EXPLANATION:
Latch correspondence for pins in a scanop sequence would require loading the package
scan chain at the same time the macro scan chain was being loaded. This would most
likely result in corrupt scan data and should be avoided.
USER RESPONSE:
exercised pins in the macros scanop sequences.
WARNING (TCT-154): [Severe] Latch correspondence for event type eventtype is not
supported.
EXPLANATION:
Macro pins that are pulsed, scanned in, or scanned out must not have latch
correspondence since it would result in long test times and would most likely cause
corrupt macro data.
USER RESPONSE:
Choose the PIPO correspondence type in the Macro Isolation Control file for all pins that
will be pulsed or used as scan in or scan out pins.
WARNING (TCT-170): The scan length of a stim or measure register in the TDM input file
is zero.

EXPLANATION:
The macro test data file did not have a valid scan length for one of its registers.
USER RESPONSE:
Ensure that the macro test data was created using only supported processes. If the
macro test data was created by a supported process, contact customer support (see
WARNING (TCT-180): No stim latches were found within the macro boundary for register
regnum.
EXPLANATION:
None of the stim register latch names listed in the macro test data file for this register
were found within the macro boundary.
USER RESPONSE:
If the macro is a white box macro and the macro tests were created using a supported
process, contact contact customer support (see Contacting Customer Service on
page 23).
WARNING (TCT-182): No measure latches were found within the macro boundary for
register regnum.
EXPLANATION:
None of the measure register latch names listed in the macro test data file for this register
were found within the macro boundary.
USER RESPONSE:
If the macro is a white box macro and the macro tests were created using a supported
process, contact contact customer support (see Contacting Customer Service on
page 23).
WARNING (TCT-184): [Severe] Latch latchName cannot be loaded directly through the
package register in TDM file event event. The data for this latch will be ignored. Regenerate
the macro test data using the normal load option.
EXPLANATION:
To load a macros skewed stim latch (SSL), it must be the first latch in a package stim
register.
USER RESPONSE:

Direct ATPG to create test data using normal loads.
WARNING (TCT-190): [Severe] A skewed stim latch event has been created that combines
skewed and non-skewed data.
EXPLANATION:
In a skewed stim latch event, the master and slave latches may not end up containing the
same data as they do in non-skewed events. Skewing apply data designed for a non-
skewed environment can lead to erroneous test results.
USER RESPONSE:
WARNING (TCT-192): [Severe] A skewed measure latch event has been created that
combines skewed and non-skewed data.
EXPLANATION:
In a skewed measure latch event, data is transferred from the master to the slave latch
before scanning out the data. Skewing expect data that is designed for non-skewed
environment can lead to erroneous test results.
USER RESPONSE:
INFO (TCT-400): Message number TCT-message_number has been printed

message_limittimes and will no longer be printed or recorded for the rest of this run.
EXPLANATION:
Each message has a limit to the number of times it will be printed during the run. The
default is 1000 times. When this limit is reached, a TCT-400 message will be printed
identifying the message number and the number of times it has been printed.
USER RESPONSE:
The number of times a message will be printed can be overridden by the messagecount
keyword. For example: messagecount=90=100,92=100 limits the number of times
messages TCT-090 and TCT-092 are printed to 100.

ERROR (TCT-500): [Internal] Unable to initialize TBD in preparation to open TDM file
tdmfile.
EXPLANATION:
USER RESPONSE:
ERROR (TCT-502): [Internal] Unable to initialize TBD with no model.

EXPLANATION:
USER RESPONSE:
ERROR (TCT-504): [Internal] Unable to open merged TDM file tdmfile.

EXPLANATION:
USER RESPONSE:
ERROR (TCT-510): [Internal] Invalid node ID (nodeID) for macro pin

macropinnodeID.
EXPLANATION:
USER RESPONSE:
ERROR (TCT-512): [Internal] Invalid node ID (nodeID) for correspondence pin

corrpinnodeID.
EXPLANATION:
USER RESPONSE:

ERROR (TCT-520): [Internal] macro scanop sequence number seqNum was not found.
Unable to continue.
EXPLANATION:
USER RESPONSE:
ERROR (TCT-530): [Internal] Invalid subgroup subGroup.

EXPLANATION:
USER RESPONSE:
ERROR (TCT-540): [Internal] The maximum number of LATCH save levels has been
exceeded.
EXPLANATION:
USER RESPONSE:
ERROR (TCT-550): [Internal] Node nodeID is not a valid stim latch node.
EXPLANATION:
USER RESPONSE:
ERROR (TCT-552): [Internal] Node nodeID is not a valid measure latch node.
EXPLANATION:
USER RESPONSE:

ERROR (TCT-560): [Internal] The maximum number of PI save levels has been exceeded.
EXPLANATION:
USER RESPONSE:
ERROR (TCT-570): [Internal] The maximum number of PO save levels has been
exceeded.
EXPLANATION:
USER RESPONSE:
ERROR (TCT-580): [Internal] The macro modeinit pin pinname has a required value that
is not the same as the value in the TDM file.
EXPLANATION:
USER RESPONSE:


16
TCW - Stand Alone Random Pattern
Simulation Messages
TCW-001 through TCW-030 on page 391

TCW-031 through TCW-055 on page 395
TCW-001 through TCW-030

WARNING (TCW-001): [Severe] Error parsing options. keyword=value is not valid.
EXPLANATION:
The simulator was invoked with the specified invalid option. Processing terminates.
USER RESPONSE:
Either omit the option, or specify an allowed value. Refer to "create_exhaustive_tests in
the Encounter Test: Reference: Commands for additional information.
WARNING (TCW-002): The following option flags were ignored: flags

EXPLANATION:
The simulator was invoked with the specified invalid option flags. The invalid options are
ignored and processing continues.
USER RESPONSE:
Either omit the option, or specify an allowed value. Refer to "create_exhaustive_tests in
WARNING (TCW-003): [Severe] Error occurred while trying to obtain proper license.
EXPLANATION:
The necessary license could not be obtained so processing terminates.

TCW - Stand Alone Random Pattern Simulation Messages
USER RESPONSE:
Check for additional messages, correct the problem and rerun.
WARNING (TCW-004): [Severe] Simulator initialization failed. Run terminates.

EXPLANATION:
An error occurred during initialization of the simulator so processing terminates.
USER RESPONSE:
Check for additional messages, correct the problem and rerun.
WARNING (TCW-005): [Severe] Cannot set the test mode.

EXPLANATION:
USER RESPONSE:
WARNING (TCW-006): [Severe] Random pattern generation does not support a scan type
of 1149.1.
EXPLANATION:
The TDR for the mode indicates a scan type of 1149.1, which is not supported by random
pattern generation.
USER RESPONSE:
Run with a valid TDR.
WARNING (TCW-010): [Severe] Unable to obtain shared use of the hierModel. Run
terminates.
EXPLANATION:
The simulator attempted to get a shared lock on the hierModel file to ensure that no other
applications try to rebuild the hierModel file while the simulator is being run. The lock was
not obtained, probably because the file was already exclusively locked by another
application.
USER RESPONSE:

If no other application is running, contact customer support (see Contacting Customer

Otherwise, rerun after other applications have completed.
WARNING (TCW-011): [Severe] Unable to obtain a shared lock on mode modename. Run
terminates.
EXPLANATION:
The simulator attempted to get a shared lock on the mode to ensure that no other
applications try to rebuild the mode while the simulator is being run. The lock was not
obtained, probably because the mode was already exclusively locked by another
application.
USER RESPONSE:
Otherwise, rerun after other applications have completed.
WARNING (TCW-012): [Severe] Unable to obtain a write lock on experiment exp. Run
terminates.
EXPLANATION:
The simulator attempted to get an exclusive lock on the experiment since it will be
creating uncommitted files for that experiment. The lock was not obtained, probably
because the experiment was already in use by another application.
USER RESPONSE:
Otherwise, rerun after other applications have completed or try a different experiment
name.
WARNING (TCW-013): Unable to release read lock on the hierModel.

EXPLANATION:
An error occurred while trying to release a lock. Processing continues.
USER RESPONSE:
Contact customer support (see Contacting Customer Service on page 23) if
subsequent locking problems occur.

WARNING (TCW-014): Unable to release read lock on the mode.

EXPLANATION:
USER RESPONSE:
WARNING (TCW-015): Unable to release write lock on the experiment.

EXPLANATION:
USER RESPONSE:
WARNING (TCW-020): [Severe] Unable to register the experiment object. Run terminates.
EXPLANATION:
This indicates a problem with the globalData file.
USER RESPONSE:
Re-import the design and rerun. If this does not fix the problem, contact customer
WARNING (TCW-021): [Severe] Unable to register an experiment dependency. Run

terminates.
EXPLANATION:
This indicates a problem with the globalData file.
USER RESPONSE:
Re-import the design and rerun. If this does not fix the problem, contact customer
WARNING (TCW-030): [Severe] TSV stored pattern tests were not run. Poor test coverage
and/or invalid test data may result.
EXPLANATION:

Audit information indicates that TSV checks were not performed. Invalid design
structures can cause test coverage to degrade, and can even result in program errors.
USER RESPONSE:
Run TSV prior to Random Pattern Generation.
TCW-031 through TCW-055

WARNING (TCW-031): Unable to access TSV statistics on the globalData file. Results may
be suspect.
EXPLANATION:
Audit information indicates that TSV checks were not performed. Invalid design
structures can cause test coverage to degrade, and can even result in program errors.
USER RESPONSE:
If desired, run TSV prior to Random Pattern Generation.
WARNING (TCW-032): TSV issued warning messages. Test coverage may be impacted.
EXPLANATION:
Audit information indicates that TSV detected design conditions which could result in test
coverage degradation.
USER RESPONSE:
If maximum coverage is desired, correct the problems identified by TSV and rerun.
WARNING (TCW-033): TSV issued error messages. Poor test coverage and/or invalid test
data may result.
EXPLANATION:
Audit information indicates that TSV detected errors which could result in test coverage
degradation and could even result in program errors.
USER RESPONSE:
Correct the design conditions which are in violation and rerun TSV and simulation.
WARNING (TCW-034): [Severe] TSV issued severe error messages. Poor test coverage
and/or invalid test data may result.
EXPLANATION:

Audit information indicates that TSV detected severe errors which could result in test
coverage degradation and could even result in program errors.
USER RESPONSE:
Correct the design conditions which are in violation and rerun TSV and simulation.
WARNING (TCW-040): [Severe] Simulation terminated due to error.

EXPLANATION:
A severe error has occurred and the simulation processing is terminating.
USER RESPONSE:
Check for additional messages and if necessary, contact customer support (see
Contacting Customer Service on page 23)
WARNING (TCW-041): [Severe] Cannot get storage for an internal table (name).
EXPLANATION:
More internal storage is required for this run.
USER RESPONSE:
WARNING (TCW-042): Error from EDAMsopn(fcb,sanum).

EXPLANATION:
The file will be rebuilt.
USER RESPONSE:
WARNING (TCW-043): Error from EDAMsget(fcb,toptr,offset, size).

EXPLANATION:
The file will be rebuilt.
USER RESPONSE:

INFO (TCW-044): Compile will be done: Compiled code does not exist.
EXPLANATION:
A valid compiled code file does not exist. Previous messages may give additional
information.
USER RESPONSE:
INFO (TCW-045): Compile will be done: Level mismatch between compiled code and
simulator. Simulator level = majorid.minorid
EXPLANATION:
The current compiled code is backleveled and needs to be recompiled. This is usually
due to a new maintenance level.
USER RESPONSE:
INFO (TCW-046): Compile will be done: Existing compiled code is for AIX machines only.
EXPLANATION:
The existing compiled code will not run on a non-AIX platform. Valid compiled code will
be built automatically.
USER RESPONSE:
INFO (TCW-047): Compile not required: existing file is up to date.

EXPLANATION:
USER RESPONSE:
INFO (TCW-048): Compile will be done: Fault machine code does not exist.
EXPLANATION:
The compiled code exists for good machine simulation, but not for fault simulation. Valid
compiled code will be built automatically.

USER RESPONSE:
INFO (TCW-049): Compile will be done: Compiled code is older than Fault Model.
EXPLANATION:
The compiled code is dependent on the fault model. Since the compiled code is older
than the fault model it will be recompiled to ensure it is not backleveled.
USER RESPONSE:
INFO (TCW-050): Compile will be done: overriding current keeper device processing.
EXPLANATION:
A recompile is necessary based on the value of the keepers parameter.
USER RESPONSE:
INFO (TCW-051): Compile will be done: overriding current compiled code type.
EXPLANATION:
The existing compiled code type does not match the requested type. A recompile is
required to produce the requested type.
USER RESPONSE:
WARNING (TCW-052): Error from EDAMfcls(fcb,keep) = (rc).

EXPLANATION:
An error was encountered while attempting to close the compiled code file. In some
cases the run is terminated.
USER RESPONSE:
INFO (TCW-053): Compile will be done: 64 bit incompatibility.

EXPLANATION:

A recompile is necessary based on a difference between the existing compiled code and
the current platform. Either the compiled code
was built on a 32 bit machine and is being run on a 64 bit machine or vice versa.
USER RESPONSE:
INFO (TCW-054): Compile will be done: overriding current measure latch processing.
EXPLANATION:
A recompile is necessary based on the value of the measurelatch parameter.
USER RESPONSE:
INFO (TCW-055): Event driven compile will be done: event driven simulation is required to
propagate faults through measure latches.
EXPLANATION:
This indicates that propagation of faults through measure latches was requested. This
requires event driven compiled code and either the current compiled code was not event
driven or event driven was not specified to be built.
USER RESPONSE:


17
TDA - General Messages
TDA-001 through TDA-222 on page 401
TDA-001 through TDA-222

INFO (TDA-001): System Resource Statistics. Maximum Storage used during the run and
Cumulative Time in hours:minutes:seconds:
Working Storage = work_bytes bytes
Mapped Files = mapped_bytes bytes
Shared Memory = shared_bytes bytes (created by this process)
Shared Memory = attached_bytes bytes (attached by this process)
(Paging) Swap Space = swap_bytes bytes
CPU Time = cpu_time
Elapsed Time = elapsed_time
EXPLANATION:
This is a general, informational message that is usually printed at the end of an
application. It reports the maximum storage used during the run in 3 categories.
Working Storage indicates the maximum number of bytes of storage allocated by the
application and any utilities for working storage at any point in time. This does not include
memory for program stack space, which may be a significant amount of memory in
addition to this.
Mapped Files indicates the maximum number of bytes of memory in use at any point
in time for mapping files into virtual memory. Encounter Test uses memory mapping of
certain files (for example, the hierModel and flatModel) to improve start-up performance
for large designs.
Encounter Test uses Shared Memory to read the information present in certain files (for
example, the flatModel and modeinfo). The use of Shared Memory by the application is
controlled by the development keyword usesharedmemory. This information is printed
in this message only when the Shared Memory is successfully used to load the
information in the files.

The Shared Memory statistics have two components. The first component shows the
amount of Shared Memory created by the current process. The second component
shows the amount of Shared Memory utilized by the current process. This utilized
Shared Memory is assumed to be created by previous processes running on the same
design related information.
(Paging) Swap Space indicates the maximum number of bytes of swap space known
to be used specifically by this invocation of the program. All of the numbers reported here
tend to increase with the size of the design being processed. These numbers reflect only
the storage explicitly in use by Encounter Test programs and do not include any operating
system storage that may also be in use. The total memory used for working storage and
mapped files must be able to fit into the virtual address space made available to
application processes by the operating system.
The CPU and Elapsed time for the application are also reported in terms of
hours:minutes:seconds.fractions_of_seconds. CPU time is affected primarily by the
amount of work the application had to do while processing the design. Elapsed time is
also affected by this, but may also be affected by other, unrelated factors such as other
workload running on the same machine and I/O overhead - especially when accessing
file storage across a network.
USER RESPONSE:
This information is provided to allow for a better understanding of the system resource
requirements for all Encounter Test applications.
INFO (TDA-002): System Resource Statistics. Maximum Storage used during the run:
EXPLANATION:
application. It reports the maximum storage used during the run in 3 categories.
Working Storage indicates the maximum number of bytes of storage allocated by the
application and any utilities for working storage at any point in time.
Mapped Files indicates the maximum number of bytes of memory in use at any point
in time for mapping files into virtual memory. Encounter Test uses memory mapping of
certain files (for example, the hierModel and flatModel) to improve start-up performance
for large designs.

example, the flatModel and modeinfo). The use of Shared Memory by the application is
(Paging) Swap Space indicates the maximum number of bytes of swap space known
to be used specifically by this invocation of the program. All of the numbers reported here
tend to increase with the size of the design being processed. These numbers reflect only
the storage explicitly in use by Encounter Test programs and do not include any operating
system storage that may also be in use.
USER RESPONSE:
INFO (TDA-003): Current Storage Usage Statistics:

EXPLANATION:
This is a general, informational message that is usually printed at various times while an
Encounter Test application program is running. It reports the current storage in use in 3
categories.
Working Storage indicates the number of bytes of storage allocated by the application
and any utilities for working storage at this point in time.
Mapped Files indicates the number of bytes of memory in use at this point in time for
mapping files into virtual memory. Encounter Test uses memory mapping of certain files
(for example, the hierModel and flatModel) to improve start-up performance for large
designs.
example, the flatModel, modeinfo). The use of Shared Memory by the application is


(Paging) Swap Space indicates the number of bytes of swap space known to be used
so far during this invocation of the program. All of the numbers reported here tend to
increase with the size of the design being processed. These numbers reflect only the
storage explicitly in use by Encounter Test programs and do not include any operating
system storage that may also be in use.
USER RESPONSE:
INFO (TDA-004): File(s) generated (bytes and name):

EXPLANATION:
Encounter Test application output listing. It reports the permanent files that were created
during the run with their size in bytes.
USER RESPONSE:
This information is provided to allow for a better understanding of the files created by
Encounter Test applications.
INFO (TDA-005): Command Line Invocation:

EXPLANATION:
This is a general, informational message that is usually printed at the beginning of an
Encounter Test application output listing. It reports the user command line invocation.
Note that this message cannot be removed with messagecount or messagelevel
keywords; it is always printed.
USER RESPONSE:
This information is provided to allow for a better understanding of the output created by

INFO (TDA-006): QF path information

EXPLANATION:
This is a general, informational message that is usually printed at the beginning of an
Encounter Test application output listing. It reports the QF (quick fix) path settings.
USER RESPONSE:
This information is provided to allow for a better understanding of the QF environment
settings used by Encounter Test applications.
INFO (TDA-007): Job Information:

Date Started:
EXPLANATION:
This is a general, informational message that is usually printed at the beginning of a
Encounter Test application output listing. It reports the job information such as the local
time.
USER RESPONSE:
INFO (TDA-009): Keywords/Values information.

(keywords marked with * have program generated values,
keywords marked with + were specified to default.)
EXPLANATION:
This is a general, informational message that is usually printed at the beginning of a
Encounter Test application output listing. It reports the keywords/values information.
keywords; it can be removed with preamble=no.
USER RESPONSE:

ERROR (TDA-010): [Tool] The chosen application is not available for general use. The run
terminates.
EXPLANATION:
An attempt was made to run a Encounter Test executable program which is not intended
for general use.
USER RESPONSE:
Refer to the Encounter Test: Reference: Commands for the complete set of available
commands.
ERROR (TDA-011): [Tool] Failed to obtain a license to run Encounter Test application
name. Tried to get license(s): names of licenses. Check license server information to
determine actions to obtain a required license and rerun.
EXPLANATION:
The application tried to obtain the required license and was unsuccessful. If more than
one license is listed, it means any one of those licenses would have worked; more than
one license is not required.
The following are potential causes of the problem:
A license to run this application does not exist in the installation.
All available licenses were in use
There is a problem with the setup or operation of the license server
USER RESPONSE:
Ensure the CDS_LIC_FILE environment variable is correctly specified to point to your
license server(s) and that one of the licenses specified in the message exists in one of
the license files. If you catenate license servers and you have the license defined in more
than one of the license files, ensure the first one we find in the list is valid for the release
level you are running.
If the problem is not obvious, check with your license installation group.
If the licenses appear to be available and the setup appear to be correct, contact the
customer support team using your normal process; SourceLink, email, or direct call to
the customer support line. Refer to Contacting Customer Service on page 23.

Provide the text of this message, the CDS_LIC_FILE setting, and information about the
licenses that are installed.
INFO (TDA-012): Failed to allocate size_of_request bytes of shared memory for the
name_of_data. The run proceeds allocating working storage for this request instead.
EXPLANATION:
This message is issued upon failure to allocate shared memory for loading design
related information. There are several reasons this can occur. The most probable are:
The machine does not have sufficient shared memory to accommodate this
allocation.
The machine is not configured with sufficient shared memory limits.
The shared memory on the machine is already utilized and therefore unavailable.
USER RESPONSE:
No response is generally required. The run should proceed and complete using working
storage rather than shared memory. If it is preferred that shared memory be utilized,
rerun on a machine with sufficient shared memory.
INFO (TDA-013): Additional Keywords/Values information (keywords with no defaults or

program generated defaults):
(keywords marked with '*' have program generated values)
EXPLANATION:
This message is issued based on reportallkeywords=yes and contains a report of
additional keywords and their values not included in the preceding TDA-009 message.
When reportallkeywords=yes, TDA-009 includes all keywords which are either
specified or have pre-defined defaults; it excludes keywords with no defaults and those
with program generated defaults (e.g., based on design information, etc.). In order to
report all keywords, this secondary report is issued after the application has determined
any program generated defaults.
USER RESPONSE:
INFO (TDA-220): Simulation/test generation status

EXPLANATION:
This message contains the simulation/test generation statistics at the end of each
simulation call or after final processing. The header (2 lines) is printed followed by

statistics from each simulation call. The text is formatted by the calling routine which
aligns the data in a tabular format based on whether this is an ATPG run, resimulation/
diagnostics run, or good machine only run.
If it is an ATPG run, the output header and data appear as follows:
--- Tests --- Faults ---- ATCov ---- ---- Faults ---- ---- CPU Time ----
Sim. Eff. Detected Tmode Global Aborted Remain. Sim. Total
If it is a good machine simulation only run, the output header and data appear as follows:
--- Tests --- ---- CPU Time ----
Sim. Eff. Sim. Total
If it is a resimulation run, the output header and data appear as follows:

--- Tests --- Faults ---- ATCov ---- ---- CPU Time ----
Sim. Eff. Detected Tmode Global Sim. Total
The fault detection and test coverage numbers are for the fault type targeted by the test
sequences. For example, the create_*_delay_tests logs will only report on the
dynamic faults.
Sim. Tests - Number of simulated test sequences (cumulative).
Eff. Tests - Number of test sequences that detected faults (cumulative).
Faults Detected - Number of faults detected in that simulation call (per sim call).
ATCov Tmode - Testmode Adjusted TCov, ATcov = #Tested / (#Faults-
#Redund) (cumulative)
ATCov Global - Global Adjusted TCov, ATcov = #Tested / (#Faults-#Redund)
(cumulative)
Faults Aborted - Number of faults the Test Generator aborted on (cumulative)
Faults Remaining - Number of faults remaining for Test Generator to work on
(cumulative)
CPU Time Sim. - Total simulator CPU time (cumulative)
CPU Time Total - Total execution CPU time (cumulative)
USER RESPONSE:
INFO (TDA-221): heartbeat data

EXPLANATION:

This message contains the heartbeat information. The text is formatted by the calling
routine which lines up the data in a tabular format based on whether this is an ATPG run,
resimulation/diagnostics run, or good machine only run.
If it is an ATPG run, the output header and data appear as follows:
--- Tests --- Faults ---- ATCov ---- ---- Faults ---- ---- CPU Time ----
Sim. Eff. Detected Tmode Global Aborted Remain. Sim. Total
If it is a good machine simulation only run, the output header and data appear as follows:
--- Tests --- ---- CPU Time ----
Sim. Eff. Sim. Total
If it is a resimulation run, the output header and data appear as follows:

--- Tests --- Faults ---- ATCov ---- ---- CPU Time ----
Sim. Eff. Detected Tmode Global Sim. Total
The fault detection and test coverage numbers are for the fault type targeted by the test
sequences. For example, the create_*_delay_tests logs will only report on the
dynamic faults.
Sim. Tests - Number of simulated test sequences (cumulative).
Eff. Tests - Number of test sequences that detected faults (cumulative).
Faults Detected - Number of faults detected in that simulation call (per sim call).
ATCov Tmode - Testmode Adjusted TCov, ATcov = #Tested / (#Faults-
#Redund) (cumulative)
ATCov Global - Global Adjusted TCov, ATcov = #Tested / (#Faults-#Redund)
(cumulative)
Faults Aborted - Number of faults the Test Generator aborted on (cumulative)
Faults Remaining - Number of faults remaining for Test Generator to work on
(cumulative)
CPU Time Sim. - Total simulator CPU time (cumulative)
CPU Time Total - Total execution CPU time (cumulative)
USER RESPONSE:
INFO (TDA-222): Checkpoint taken on current date and time

EXPLANATION:
This message indicates the day and time the checkpoint is taken.

USER RESPONSE:
ERROR (TDA-500): The EHF for CCR CCRnumber must be used with release
release_version_of_EHF, but the release you are using is
release_version_of_base_release. The run will continue to check any other
EHF's included in your QF_PATH and then it will end without running the application.
EXPLANATION:
You have set QF_* variables to point to paths for an EHF. The release the EHF is
intended for does not match the base release you are using. This condition can cause
the code to crash or create unexpected results. Therefore, the et script terminates to
prevent this condition from occurring.
USER RESPONSE:
Ensure that the base release you are using matches the release for all EHFs in the
QF_PATH. If the EHF isn't needed for your current run, remove that EHF directory from
your QF_* paths. If the EHF is needed, use et from the base release that matches the
release required for the EHF.
ERROR (TDA-501): The QF_PATH contains one or more EHFs that are not compatible with
the base release. See previous TDA-500 message(s) for more information. The et script is
exiting without setting up the environment or invoking any application.
EXPLANATION:
You have set one or more QF_* variables to point to paths for an EHF. The release one
or more of the EHFs is intended for does not match the base release you are using. This
condition can cause the code to crash or create unexpected results. Therefore, the et
script terminates to prevent this condition from occurring.
USER RESPONSE:
Find all TDA-500 messages in this log and note the CCR numbers that they indicate are
in error. If you need one or more of these EHFs then use the base release that they
require. If you do not need these EHFs, remove their directories from the QF_* paths
and then rerun the et script to set up your environment.

18
TDC - Design Constraint Messages
TDC-001 through TDC-050 on page 411

TDC-051 through TDC-301 on page 415
TDC-001 through TDC-050

INFO (TDC-001): Read and Verify SDC process started
EXPLANATION:
Execution of read and verify SDC processing has begun.
USER RESPONSE:
INFO (TDC-002): read_sdc code version is version

EXPLANATION:
The message lists the date stamp of the currently executed code. The information may
be useful when contacting customer support with a problem.
USER RESPONSE:
INFO (TDC-005): Done reading the SDC file(s). verificationString

EXPLANATION:
The read SDC step has successfully completed. The verification step, if activated, is
beginning.
USER RESPONSE:

INFO (TDC-006): verificationString A total of numConstraints new design

constraints middleSrring will be added to the model.
EXPLANATION:
The verification process completed. The referenced number of verified constraints has
been added to the model. If verification was deactivated, all constraints were added to
the model.
USER RESPONSE:
INFO (TDC-007): verificationString No new design constraints will be added to the

model.
EXPLANATION:
The verification process completed. No new constraints were added to the model. The
following are possible causes:
The constraints already exist in the model.
The constraints failed in the verification step.
USER RESPONSE:
INFO (TDC-008): numConstraints design constraints were registered from previous

read_sdc commands.
EXPLANATION:
every time we run read_sdc, the design constraints are registered in the global data.
These are read now.
USER RESPONSE:
If you don not want these contraints to be read, run remove_sdc.
INFO (TDC-009): Multiple test modes were specified. Test mode testMode will be used
for the analysis, but the data will be registered under all the test modes.
EXPLANATION:
The program selects one of the specified test modes for analysis and registers the
constraints under all specified test modes.
USER RESPONSE:

INFO (TDC-010): Starting verification to determine whether the false and multicycle paths
are logically false.
EXPLANATION:
The program determines whether a path is logically false and uses this information as
input to subsequent test generation.
USER RESPONSE:
INFO (TDC-011): Found numFalsePaths design constraints that were proven to be

logically false.
EXPLANATION:
The message states the detected number of logically false paths. This information is
useful to test generation.
USER RESPONSE:
INFO (TDC-012): Checking multiple test modes for compatibility.

EXPLANATION:
The program is verifying the clock and TIED values to determine whether the values
match to all specified test modes.
USER RESPONSE:
INFO (TDC-013): Test mopde compatibility check successfully completed. Test mode
testMode will be used for analysis since it has the maximum number of clocks.
EXPLANATION:
The test mode compatibility check is complete. The referenced test mode has been
selected for analysis.
USER RESPONSE:
INFO (TDC-014): RTL Compiler (RC) RCversion

EXPLANATION:
This message states the currently used version of RTL Compiler.
USER RESPONSE:
INFO (TDC-015): During parsing the SDC file(s), some errors were found. Check the log
RClogFileName for further details.
EXPLANATION:
These are the parse errors found during parsing the SDC file(s). RC log has more details
on them regarding the real cause of the failure.
USER RESPONSE:
Review and resolve the log messages and rerun if necessary.
INFO (TDC-016): Since verification is turned off, all the constraints will be added to the
model
EXPLANATION:
The program adds all constraints to the model if verification is deactivated.
USER RESPONSE:
INFO (TDC-017): No design constraints are presently registered.

EXPLANATION:
No SDC constraints were found. Run read_sdc to register constraints in ET.
USER RESPONSE:
None.
INFO (TDC-018): report_sdc Output File will be filename

EXPLANATION:
Lists the output file name used to store the constraints written by the report_sdc
command.
USER RESPONSE:
None.

WARNING (TDC-049): A set_case_analysis constraint conflicts with clamping value on

a net within an unpowered domain. The conflicting statement is on pinName with value
value. The constraint will be ignored.
EXPLANATION:
Case statements conflict each other.
USER RESPONSE:
Check the constraints and ensure that the values do not conflict each other and rerun if
necessary.
WARNING (TDC-050): A set_case_analysis constraint conflicts with a previous

set_case_analysis constraint. The conflicting statement is on pinName with value
value. The constraint will be ignored. Listed below are all the set_case_analysis
statements that precede the conflicting statement
EXPLANATION:
The program has detected conflicting case statements.
USER RESPONSE:
Review the constraints and values for conflicts and correct as needed.
TDC-051 through TDC-301

WARNING (TDC-051): An SDC path constraint specified on line number lineNumber in
file fileName could not be verified.
EXPLANATION:
The program was unable to verify the referenced falsepath or multicycle statement.
USER RESPONSE:
Ensure the constraint has a connecting path and rerun if necessary.
WARNING (TDC-052): The Boolean Constraint constraint1 conflicts with a previously

specified constraintconstraint1. The previous constraint will be ignored.
EXPLANATION:
Two Boolean constraints are in conflict with each other.
USER RESPONSE:

Ensure the specified constraints do not conflict and rerun if necessary.
WARNING (TDC-053): A set_case_analysis constraint is specified on internal logic. The

constraint is on pinName with value value. Verification cannot guarantee that a conflict
does not exist with another constraint on another pin. The constraint will be honored during
ATPG and simulation.
EXPLANATION:
Since the constraint is specified on an internal pin, verification cannot prove that another
constraint does not conflict with this one. The constraint will be honored during ATPG and
simulation. However, if the constraint does conflict with another constraint, all patterns
will contain at least one constraint violation, causing an X to propagate forward from the
location of the constraint violation. This may negatively impact test coverage, pattern
count or both.
USER RESPONSE:
Move the constraint to a PI, latch or flop, or verify that there are no conflicts with other
set_case_analysis constraints.
WARNING (TDC-054): [Severe] An SDC path constraint contains -from clock1 and -to
clock2 which are primary input or PPI clocks. This constraint is usually not necessary for
ATPG and overconstrains the design. It is being dropped. The constraint occurs
lineAndFile.
EXPLANATION:
The falsepath or multicycle SDC statement specifies a from clock and a to clock which
are primary inputs or PPIs. This statement constrains all paths from all latches/flops fed
by the "from" clock to all latches/flops fed by the "to" clock and tends to overconstrain the
ATPG process. The constraint is usually not necessary in static ATPG because clock
domains that interact are not pulsed together.
In dynamic ATPG, repeating clocks are used for launch and capture by default unless
specified explicitly by the user (specifying dynseqfilter=norepeat or through a
clockconstraints file or a testsequence.)
USER RESPONSE:
If the constraint is necessary for ATPG, rerun read_sdc and specify keep=all.
WARNING (TDC-055): The SDC statement on line number lineNumber in file

fileName has only a from point which is a clock.
EXPLANATION:

The program has is questioning the validity of the statement in the referenced file and
line number. It is possible the SDC constraint is lingering from previous activity.
USER RESPONSE:
Verify the intended constraint is in the SDC.
WARNING (TDC-056): The type clause of the constraint on line n of file filename
contains x terms - too many to process efficiently. The clause is being dropped from the
constraint. This may affect test coverage or pattern count. The current number of terms
allowed is y To allow more terms, specify the maxconstraintterms kewyord.
EXPLANATION:
The from/through/to clause on the constraint contains a very large number of terms.
A number of terms this large could indicate a problem with the coding of the SDC
constraint and should be verified by the user. Even if the constraint is valid, such a large
number of terms may cause read_sdc and ATPG/simulation to run a very long time.
Dropping the clause automatically reduces the number of terms to process, but may also
impact test coverage or pattern count because it may overconstrain the design.
USER RESPONSE:
If dropping the term is unacceptable and the constraint cannot be recoded to require
fewer terms, then the maximum number of terms allowed on the constraint may be
increased by setting the maxconstraintterms keyword to a number larger than the
number of terms on the constraint.
ERROR (TDC-057): Unexpected failure during RC (reason).

EXPLANATION:
When processing the SDC file, RTL Compiler (RC) encountered an error. The error
message is included in the RC log file.
USER RESPONSE:
If possible, correct the error described by RC and rerun read_sdc.
WARNING (TDC-058): [Severe] The constraint on line filename of file linenumber

references name which contains the special character (char) which is not supported in the
SDC process. The object is being dropped from the constraint. If the constraint is required,
it must be rewritten to reference another object in the path that does not contain the special
character.
EXPLANATION:

The constraint references a name that contains characters that are not supported in the
SDC constraint flow. The name is being dropped from the constraint. If the design is not
adequately protected without the constraint, it may be necessary to rewrite the constraint
so that it references a different object in the design hierarchy that does not contain the
special characters. Doing so may cause the constraint to be more pessimistic but may
be necessary in order to ensure patterns generated are valid.
USER RESPONSE:
Rewrite the constraint if necessary and rerun read_sdc.
WARNING (TDC-060): An Experiment was specified. Since the constraints will be

registered under this experiment, make sure to run the ATPG job with append=yes. Without
this, your constraints will be deleted from the registered data during ATPG.
EXPLANATION:
Since a new ATPG job with an experiment will delete all the previous data registered
under this experiment, make sure to use append=yes.
USER RESPONSE:
To get rid of this probem, either dont use experiment or be carefull while running ATPG.
WARNING (TDC-061): The pin pinName is NOT on a cell boundary. This will cause the
timing engine to ignore the pin.
EXPLANATION:
The timing engine requires the referenced pin to be on a cell boundary to properly
process.
USER RESPONSE:
Modify the pins to place them on cell boundaries.
WARNING (TDC-062): [Severe] An error occurred while reading the SDC file.
EXPLANATION:
The program detected an SDC file error and is unable to parse the file.
USER RESPONSE:
Verify the constraints are syntactically correct.
WARNING (TDC-063): [Severe] An SDC path constraint contains -from clock1 and -to
clock2 which are primary input or PPI clocks as well as one or more -through clauses. This

constraint is being dropped but may need to be re-written to adequately protect the design
during ATPG. The constraint occurs lineAndFile.
EXPLANATION:
The falsepath or multicycle SDC statement specifies a from clock and a to clock which
are primary inputs or PPIs. This statement creates an extremely large number of
possible paths to be checked during ATPG and tends to overburden the ATPG process.
Often, -from <PI clk> -to <PI clk> constraints are not required for ATPG because ATPG
does not tend to generate such tests (i.e., interacting clocks in static ATPG or
interdomain tests in dynamic ATPG.) However this constraint contains a -through clause
which may be required.
USER RESPONSE:
If the constraint is necessary for ATPG, recode it to remove the -from and -to clauses and
rerun read_sdc. If the constraint is not required for ATPG, no action is required
ERROR (TDC-100): Specified SDC file fileName does not exist.

EXPLANATION:
The specified SDC file does not exist.
USER RESPONSE:
Verify the file names and permission settings, then rerun.
ERROR (TDC-102): Verified design constraints cannot be written into the part directory due
to incorrect write permissions.
EXPLANATION:
The specified part directory lacks write permissions.
USER RESPONSE:
Modify the permissions to enable writing of verified constraint data.
ERROR (TDC-103): read_sdc process can only be run on a LINUX machine.

EXPLANATION:
The program is currently supported on Linux platform.
USER RESPONSE:
Run the program on a Linux workstation.
ERROR (TDC-104): Unable to locate the executable RC.

EXPLANATION:
The rc executable was not detected in the PATH setting.
USER RESPONSE:
Modify your path setting to add the rc path, then rerun.
ERROR (TDC-105): Wrong version of RC is being used.

EXPLANATION:
RC version 5.1 or higher is required to run the program.
USER RESPONSE:
Obtain the appropriate version of RC and rerun.
ERROR (TDC-106): Test mode compatibility check failed. Test mode testMode conflicts
with one of the previous test modes specified with the TESTMODE keyword.
EXPLANATION:
The program has detected a test mode mismatch in one or more clock polarity or tied
values on the PIs .
USER RESPONSE:
Remove the conflicting test mode from the TESTMODE keyword specification and perform
read_sdc for the test mode.
severity (TDC-200): The read and verify process ended with errorType.
EXPLANATION:
The message states that the read and verify processes are complete.
USER RESPONSE:
severity (TDC-201): Remove SDC process ended with errorType.

EXPLANATION:
The message states that Remove SDC has completed.
USER RESPONSE:

INFO (TDC-300): Remove SDC process has started.

EXPLANATION:
The message states Remove SDC has started. .
USER RESPONSE:
INFO (TDC-301): remove_sdc code version is codeType

EXPLANATION:
The message states the code date stamp for the currently executing program. The
information may be useful when contacting customer support with a problem.
USER RESPONSE:
INFO (TDC-302): Report SDC Process Completed.

EXPLANATION:
Indicates that the report_sdc command has completed.
USER RESPONSE:


19
TDG - Diagnostic Simulation Messages
TDG-001 through TDG-043 on page 423

TDG-001 through TDG-043

INFO (TDG-001): Start of Encounter Diagnostics Simulation.
EXPLANATION:
This is an informational message signifying the start of Encounter Diagnostics.
USER RESPONSE:
ERROR (TDG-002): The combination of the assumedynamic faultstatus and

testrange specifications cannot be honored because there are no applicable faults.
Processing ends.
EXPLANATION:
The use of assumedynamic to diagnose transition faults using static tests requires that
both dynamic faults and static tests be selected. The current specification of

faultstatus and testrange resulted in no faults to be processed. There are no

applicable faults with the specified status and type, causing the run to terminate.
USER RESPONSE:
Adjust the current faultstatus and/or testrange specification and rerun. It is
possible that the faultset keyword could also be limiting the applicable faults and
therefore contributing to this condition.
ERROR (TDG-003): The combination of the faultstatus and faulttype specifications

cannot be honored because there are no applicable faults. Processing ends.
EXPLANATION:
The faultstatus and faulttype specifications work in conjunction with other
keywords (such as faultset, and testrange), to define the set of faults desired for
processing. Given the applicable faults determined by those other keywords, the current
specification of faultstatus and faulttype resulted in no faults to be processed.
There are no applicable faults with the specified specified status and type, causing the
run to terminate.
USER RESPONSE:
Adjust the current faultstatus and/or faulttype specification and rerun. It is
possible that other keywords such as faultset and testrange could also be limiting
the applicable faults and therefore contributing to this condition.
INFO (TDG-004): The faultstatus specification includes untested faults. The

presence of tested faults , including untested faults is most likely unnecessary and may
therefore unnecessarily increase runtime.
EXPLANATION:
The faultstatus specification enables processing of both tested and untested
faults. In most cases when tested faults are present, processing of only tested faults
is desired to optimize performance. However in rare cases where the fault status does
not reflect fault simulation results of the patterns, it may be necessary to include
untested faults.
USER RESPONSE:
If the fault status reflects the fault simulation results of the specified patterns, subsequent
runs can be made excluding untested faults without loss of accuracy.
Ignore this messages If the fault status does not reflect the fault simulation result of the
specified patterns.

INFO (TDG-005): The faultstatus specification excludes untested faults. Tested faults
are present and therefore excluding untested faults is valid unless the fault status does not
accurately reflect fault simulation results of the specified patterns.
EXPLANATION:
The faultstatus specification excludes the processing of untested faults. In most
cases where tested faults are present, processing of only tested faults is desired to
optimize performance. However, in rare cases where the fault status does not reflect fault
simulation results of the patterns, it may be necessary to also include untested faults
to ensure accurate results.
USER RESPONSE:
Ignore this message if the fault status reflects the fault simulation results of the specified
patterns. Otherwise, subsequent runs should be made including untested faults to
ensure accurate results.
WARNING (TDG-006): The faultstatus specification excludes tested faults. The

presence of tested faults causes accuracy of the results to be suspect.
EXPLANATION:
The faultstatus specification excludes the processing of tested faults. In most
cases where tested faults are present, processing of only tested faults is desired to
optimize performance. Excluding tested faults in this case will most likely lead to
inaccurate results. It is valid to exclude tested faults only in the rare case in which the
fault status does not accurately reflect fault simulation results of the specified patterns.
USER RESPONSE:
If the fault status accurately reflects the fault simulation results of the specified patterns,
rerun including tested faults. Otherwise, inaccurate results will likely occur.
INFO (TDG-007): There were no callouts to report. No callout satisfied the reporting criteria.
EXPLANATION:
Informational message indicating that no callouts were reported. In order to be reported,
a callout must satisfy the following criteria:
be included by any/all reporting options (i.e., scoremargin, threshold)This is fairly
self-explanatory. In order for a callout to be printed, it must satisfy any specified
criteria with regard to its margin from the highest scoring callout, or its actual score.
at least one contribution (e.g., TFSF for logic faults, TP for Invariant Analysis) There
are several contributing factors, perhaps in combination, that could result in no
callout having at least one contribution. These are:

a limited set of candidates initially selected

The candidate callouts initially selected depends on the application. For logic
diagnostics, this pertains to the specified set of faults to be simulated. The fault set is
determined by several keywords including faultset, faulttype, faultstatus, clockfaults, and
testrange. Depending on the setting of these keywords, it is possible that none of the
potential scoring candidates are initially included in the simulation.
For scan diagnostics, this pertains to the failing scan chains, and perhaps any specified
subset of possible failing bit positions therein.
For Invariant Analysis, this pertains to the specified set of Boolean expressions to be
scored, and any specified testrange.
candidate dropping criteria
For logic diagnostics, it is possible to specify a dropping criteria such that when a fault
reaches a certain limit of contradictions, it is dropped from simulation for the remainder
of the run. Once a fault is dropped, no further contributions are considered for that fault.
Depending on whether faults are dropped in the run, this may be a contributing factor.
The futile keyword is used to specify the fault dropping criteria.
USER RESPONSE:
This message is not necessarily indicative of a problem. It reflects the state of the callout,
given the results of the simulation, and any callout reporting controls that may be in
effect. Consider the contributing factors outlined in the explanation and rerun with
alternate options if desired.
WARNING (TDG-008): Physical Design Viewer returned an error for the net
net_name with index net_index. Net pairs for this net are not generated.
EXPLANATION:
The Physical Design Viewer could not find the specified net and has therefore returned
an error. This net should be analyzed and the exact reason for this problem need sto be
understood.
USER RESPONSE:
Analyze the specified net to identify the cause of the error. If the error is valid, no action
is required. Otherwise, contact customer support (see Contacting Customer Service on
page 23).
INFO (TDG-010): No fault_type faults are selected because there are no test_type
tests within the specified testrange.
EXPLANATION:

The informational message reports that no faults of the specified type will be considered
even though they were requested because the testrange specification does not
include tests that target faults of that type.
USER RESPONSE:
In some cases, no response is needed. When this message is accompanied by a
terminating message indicating that there are no applicable faults, you may adjust the
current faulttype or testrange specification and rerun.
INFO (TDG-011): There are no callouts to perform callout_analysis_function for

device device_name.
EXPLANATION:
This informational message indicates that no callouts resulted from diagnostic simulation
to produce a callout. For diagnostic simulation to produce a callout, at least one
contribution must be observed (for example, TFSF for logic faults, TP for Invariant
Analysis). Note that a callout file may be written even though no callouts have
contributions. This enables optionally appending to the callout with results of
subsequent runs.
USER RESPONSE:
This message is not necessarily indicative of a problem. It reflects the state of the callout,
given the results of the simulation, and any simulation controls that may be in effect.
Consider the contributing factors outlined in the explanation, and rerun with alternate
options if desired.
INFO (TDG-012): Targeting number_of_latches_targeting of

number_of_latches_in_scan_chain latches for S-A-0|1 defects along the scan
chain feeding scan-out scan_out_net_name.
EXPLANATION:
This message reports the number of latches along the specified scan chain that will be
targeted by test generation. A latch is considered a candidate for targeting if it is not a
scan-only latch. This implies the latch may be laterally inserted through a functional path.
The effectiveness of the generated patterns to diagnose a faulty chain depends on a high
percentage of laterally inserted latches.
USER RESPONSE:
No response required, however a low percentage of targeted latches implies a low
percentage of latches can be laterally inserted. In this case, this approach will likely not
be effective and an alternative scan chain diagnostics strategy should be pursued.

INFO TDG-013): Generated number_of_test_sequences test sequence(s) which

cover number_of_tested_latches of number_of_targeted_latches (or
percentage_of_targeted_latches_tested%) of the targeted latches.
EXPLANATION:
This message reports the number of generated test sequences and the total number of
latches along the specified scan chain that are covered (or tested) by the generated test
sequences.
USER RESPONSE:
No response required, however a low percentage of tested latches implies a low
percentage of latches are laterally inserted by the generated patterns. Because the
effectiveness of this approach depends on a high percentage of latches laterally
inserted, a low percentage indicates the generated patterns will not provide sufficient
resolution for diagnostics. In this case, the cause for low coverage can be investigated
by rerunning with reportverbose=yes and examining the output from test generation.
If the investigation leads to identifying a cause (for example, aborted faults), that can be
addressed through specifying alternative options, rerun specifying the appropriate
options to improve the percentage of tested latches. Otherwise the design may not be
conducive to generating such tests. In this case, this approach, cannot be effective and
an alternative scan chain diagnostics strategy should be pursued.
INFO (TDG-014): Simulation of

number_of_test_sequences_currently_being_simulated of
number_of_test_sequences_to_simulate_in_run test sequences begins.
EXPLANATION:
Informational message reporting the number of test sequences currently being
simulated. The total number of test sequences to be simulated by this run is also
reported.
USER RESPONSE:
INFO (TDG-015): Test Sequence odometer

experiment_odometer_value.test_section_odometer_value.tester_
loop_odometer_value.test_procedure_odometer_value.test_
sequence_odometer_value is in the specified range, but has been previously
simulated.
EXPLANATION:

Informational message reporting the specified test sequence is not being simulated in
the current append or restart run.
USER RESPONSE:
INFO (TDG-016): Simulation complete. CPU time: CPU_time, cumulative: CPU_time.

EXPLANATION:
Informational message issued upon conclusion of simulation of each group of test
sequences. The CPU time used by the simulator for the group of test sequences is
reported, followed by the cumulative CPU time used by the simulator for the run. Note
that since fractional seconds are not printed but are accumulated, the cumulative total
may appear slightly incorrect.
USER RESPONSE:
INFO (TDG-017): The specified maximum CPU time of CPU_time minutes has been
reached. The run ends.
EXPLANATION:
Informational message indicating the maximum CPU time specified for the run has been
reached. The run will end normally.
USER RESPONSE:
INFO (TDG-018): The specified maximum elapsed time of elapsed_time minutes has
been reached. The run ends.
EXPLANATION:
Informational message indicating the maximum elapsed time specified for the run has
been reached. The run will end normally.
USER RESPONSE:
INFO (TDG-019): The heartbeat elapsed time of elapsed_time minutes has been
reached. Interim report follows.
EXPLANATION:

Informational message indicating the elapsed time associated with heartbeat has
been reached and that an interim report will follow. The run will proceed normally
following the interim report.
USER RESPONSE:
ERROR (TDG-020): The faultset callout specification is invalid when the existing
callout contains composite faults.
EXPLANATION:
Keyword value faultset=callout has been specified and the existing callout file was
created by specifying fmach. This scenario is currently unsupported.
USER RESPONSE:
Use the same fmach specification for any subsequent simulations.
WARNING (TDG-021): An error occurred while attempting to remove Alternate Fault Model
alternate_fault_model.
EXPLANATION:
An error was detected when attempting to remove the identified alternate fault model. An
alternate fault model is automatically built to enable the test generation process.
Following test generation, this alternate fault model is removed as part of final clean-up.
Because an error occurred in this case, the alternate fault model was not removed,
however any resultant patterns from this invocation should be valid.
USER RESPONSE:
Determine the cause of the alternate fault model removal error by running
delete_alternate_faultmodel and examine the output to determine whether
corrective action is required.
ERROR (TDG-022): The callout which this program is trying to read does not exist.
EXPLANATION:
Keyword value faultset-callout was specified and callout data does not exist. -
faultset callout requires that a previous simulation run to completion with
calloutfile=yes specified.
USER RESPONSE:
Select another faultset option.

ERROR (TDG-023): The callout to which this program is to append does not exist.
EXPLANATION:
The specified callout does not exist and cannot be appended to.
USER RESPONSE:
Specify an existing callout or remove append=yes from the invocation and rerun.
ERROR (TDG-024): The reportfaultequivalence=no specification is not valid when

running with an industry-compatible fault model.
EXPLANATION:
The run was made using an industry-compatible fault model. In that case, the equivalent
callout locations for each equivalence-class representative fault are determined by
extracting fault model information for each corresponding reduced fault. The
reportfaultequivalence specification used does not allow this to occur.
USER RESPONSE:
Specify reportfault equivalence=no or remove the specification from the command
line (thus allowing it to default) and rerun.
ERROR (TDG-024): The reportfaultequivalence=no specification is not valid when

running with an industry-compatible fault model. Processing ends.
EXPLANATION:
The run was made using an industry-compatible fault model. In that case, the equivalent
callout locations for each equivalence-class representative fault are determined by
extracting fault model information for each corresponding reduced fault. The
reportfaultequivalence specification used does not allow this to occur.
USER RESPONSE:
Specify reportfaultequivalence=no or remove the specification from the
command line (thus allowing it to default) and re-run.
ERROR (TDG-025): The specified value for failingregs keyword is greater than the
maximum scan chains scan_chains.
EXPLANATION:
The specified failing register number is outside the number of scan chains present in the
design.
USER RESPONSE:

Specify a failing register number less than the maximum number of scan chains.
INFO (TDG-033): The number_of _untested_latches untested latch(es) consist of

number_of _untestable_latches untestable and number_of
_aborted_latches% aborted.
EXPLANATION:
Informational message reporting the number untested latches and a breakdown of that
number into two categories: untestable and aborted. An untestable latch cannot be
tested by this application. An aborted latch may be tested, but only if a subsequent run
is made with increased test generation limits. Note that a subsequent run may also
conclude that a previously aborted latch is untestable.
USER RESPONSE:
No response required, however a low percentage of tested latches implies a low
percentage of latches are laterally inserted by the generated patterns. Because the
effectiveness of this approach depends on a high percentage of laterally inserted
latches, a low percentage indicates the generated patterns will not provide sufficient
resolution for diagnostics. The percentage of tested latches can be determined by
examining a preceding message. If this is relatively low, examine the untested latch
categories in this message.
The reasons for untested latches can also be further investigated by rerunning with
reportverbose=yes and examining the output from test generation. If the
investigation leads to identifying a cause (for example, aborted faults), that can be
addressed through specifying alternative options, rerun specifying the appropriate
options to improve the percentage of tested latches. Otherwise, the design may not be
conducive to generating such tests. In this case, this approach can not be effective and
an alternative scan chain diagnostics strategy should be pursued.
ERROR (TDG-034): This command is not supported on test modes utilizing compression.
EXPLANATION:
The specified command requires direct access to the scan chains by way of scan-in
Primary Inputs and/or scan-out Primary Outputs. Therefore, this command cannot be
executed for test modes which exploit the use of compression logic surrounding the scan
chains. This test mode utilizes some form of compression logic in the form of a spreader
network on the input of the scan chains and/or a space compactor on the output.
USER RESPONSE:
Rerun the command specifying a test mode having full scan capabilities.
INFO (TDG-035): Start of Callout Report:

EXPLANATION:
Informational message indicating the start of the callout report.
The following legend applies to the callout report:
Expression index = Number assigned to Boolean expression from Invariant Analysis
input file.
Score = [ (9 TF / (TF + FF)) + (FP / (TP + FP)) ] * 10
TF = How many times the expression was true for failing measures.
FF = How many times the expression was false for failing measures.
TP = How many times the expression was true for passing measures.
FP = How many times the expression was false for passing measures.
USER RESPONSE:
INFO (TDG-036): End of Callout Report. Time used CPU_time/elapsed_time.

EXPLANATION:
Informational message indicating the end of the callout report.
USER RESPONSE:

EXPLANATION:
Iteration = Integer indicating the number of the trial being reported.
Failing Observable Scan Chain = The observable scan chain number of the failing
chain.
Latch Position = Bit position counting from scan out (observable bit position) used in
this trial.
Score = (TFSF / (TFSF + TFSP + TPSF) ) * 100

TFSP = How many pins/latches that failed at the tester, passed(didnt fail) in
simulation.
TFSF = How many pins/latches that failed at the tester, failed in simulation.
TPSF = How many pins/latches that passed (didnot fail) at the tester, failed in
simulation.
USER RESPONSE:
INFO (TDG-038): End of Callout Report. Time used CPU_time/elapsed_time.

EXPLANATION:
Informational message indicating the end of the callout report.
USER RESPONSE:
WARNING (TDG-039): The reportfaultequivalence=yes option may result in an

incomplete callout report because the logic model is optimized.
EXPLANATION:
The Encounter Test logic model was built using reducemodel=yes which can result in
the identification of fault-equivalent strings of buffers and inverters that are ignored by
diagnostics. This feature is intended to reduce memory usage and improve performance.
As a consequence, the callout report may be incomplete with respect to fault-
equivalence when reportfaultequivalence=yes is specified. This option is not
intended for general use.
USER RESPONSE:
Remove the reportfaultequivalence specification and rerun.
INFO (TDG-040): No latches exist in the design. No clock gating file is generated.
EXPLANATION:
A design must contain one or more latches in order for
prepare_diagnostics_clock_gating to generate a diagnostic clock gating file.
The specified design contains no latches therefore no clock gating file can be generated
nor is one required for diagnostics.
USER RESPONSE:
No response required. Proceed with running diagnostics without the clock gating file.

ERROR (TDG-041): The specified value for bestguess keyword is greater than the scan
chains length chain_length.
EXPLANATION:
The specified bestguess value is greater than the scan chain length.
USER RESPONSE:
Specify a best guess value less than the scan chain length.
INFO (TDG-042): Analysis report based on specified best guess bound_information.

EXPLANATION:
This message reports the failure type, range of bits and the scan-out pin name. The
reported range contains the user specified best guess and program generated upper
bound. The defective scan chain bit lies with in the specified range.
USER RESPONSE:
None.
WARNING (TDG-043): The program is not going to perform further simulations because of
stopafteriteration=stop_after_iteration specification.
EXPLANATION:
Program has stopped with out completing all the simulations due to the value specified
to stopafteriteration keyword.
USER RESPONSE:
If you wish to do the full simulation and get the final result for this FAILSET, rerun the
command by removing the stopafteriteration keyword specification.
ERROR (TDG-044): The reportphysicallocation=yes specification requires the use

of an industry-compatible fault model. Processing ends.
EXPLANATION:
Including physical locations in the callout report requires that an industry-compatible fault
model be used. The fault model defines the locations of the faults. In order to find the
physical locations of the faulted pins, the faults must be defined on the boundaries of the
technology cells. The industry-compatible fault model does this. Since this run was
made using a non-industry-compatible fault model, reporting of physical locations can
not be supported.
USER RESPONSE:

If physical locations are not desired in the callout report, specify

reportphysicallocation=no and rerun. Otherwise an industry-compatible fault
model must be specified upon rerun. If an industry-compatible fault model does not exist,
one needs to be built prior to rerunning diagnostics.
severity (TDG-045): Failure Data Analysis Report:

EXPLANATION:
This message is issued by diagnose_failset_scanchain command and it contains
the information collected by the analysis of failure data. This information is tabulated with
the details of failing chain and the failure type. If the program is not able to determine the
failing chain or the failing types, then this will be an ERROR message.
USER RESPONSE:
None.
ERROR (TDG-047): This command is not supported for testmodes with XOR compression
structures inserted.
EXPLANATION:
For partitioning to work, it is required to have the information of the list of flops at which
failures are captured. In this case, a failure at the output of the chip can not be traced
back to a single flop and hence the partitioning is not helpful.
USER RESPONSE:
There is no need to perform failset partitioning for testmodes with XOR compression
structures inserted. Run diagnose_failset_logic on the failset and multiple
defects will be identified by this command even with out performing the failset
partitioning.
INFO (TDG-048): Report of Top Scoring Flop(s) after Simulation Iteration:

simulation_iteration
EXPLANATION:
This message is issued by diagnose_failset_scanchain command and it contains
the results of scan chain diagnostics simulation.
USER RESPONSE:
None.
severity_type (TDG-050): Pattern Analysis Report for Scan Chain Diagnostics.

EXPLANATION:

This report contains number of scan and logic patterns present in failset.
USER RESPONSE:
If there are very few logic patterns reported in this message, including failures from more
logic paterns will improve the accuracy of the diagnostics process. We recommend
failures from at least 24 logic patterns for good accuracy.
Message_severity ERROR (TDG-051): message_info.

EXPLANATION:
This design contains output compression pipe lines with non-uniform depths. This
program currently supports uniform pipe line depths.
USER RESPONSE:
Contact the customer support team (see Contacting Customer Service on page 23)
and request for an enhancement of this program to support your design specifications.
INFO (TDG-052): Scan Chain Diagnostics Simulation Summary Report(s):

EXPLANATION:
None.
USER RESPONSE:
None.
severity_type (TDG-055): Failing Chain(s) and Failure Type(s) Identification Report.

EXPLANATION:
This message is issued after completion of fail data analysis to identify list of failing
chain(s) and their failure type(s).
USER RESPONSE:
The response to the message is embedded in the message. You may have to refer to
preceding message(s) to understand the root cause of the problem.
INFO (TDG-058): Report of Top Scoring failing chain(s) and fail type(s) combinations.
EXPLANATION:
This message contains the best scoring failing chain(s) and fail type(s) combinations and
their corresponding score. If a single top scoring combination scores close to 100, the
failing chain(s) and fail type(s) are determined by this program. If the top score is too low,
it indicates a failure in the failing chain(s) and fail type(s) identification. When the

determination is successful, if there is a substantial difference between the top scoring

combination and the next top scoring combination, the failing chain(s) and fail type(s) are
determined with out any ambiguity. If the difference is small, there is a possibility of some
ambiguity in the failing chain(s) and fail type(s) determination. This report helps in
understanding the confidence of the failing chain(s) and fail type(s) determinations. The
failingregs and failtype specifications reported will help to rerun the chain diagnostics for
the chains and failure types.
USER RESPONSE:
If there is a single top scoring combination and the top score is close to 100, no action is
required. If there is a small difference in the scores between the top scoring combination
and the next combinations, you may wish to rerun chain diagnostics on these
combinations by adding the failingregs and failtype specification to the command line
specification. If the top scoring combination scores poorly, it indicates the presence of
intermittent defects.
INFO (TDG-060): Started matching failures from scan chain test sequence sequence
against combinations of suspect channels and failure modes up to
'maxcombinationsize=combination_size'.
EXPLANATION:
Informational message indicating the start of the matching process that identifies the
best scoring failing chain(s) and fail type(s) combination.
USER RESPONSE:
None.
WARNING (TDG-062): Fault to failing flops and patterns report will not be generated since
the program is run with explainfails=no specification.
EXPLANATION:
This program is run with either explainfailingflops=yes and/or
explainfailingpatterns=yes specification which requires the availability of
explain failure data. In this case, explainfails=no is specified and hence the fault to
failing flops and/or patterns report will not be generated.
USER RESPONSE:
If fault to failing flops and/or patterns report is desired, rerun
diagnose_failset_logic specifying explainfail=yes. Otherwise, no response
is required.

WARNING (TDG-063): Fault to failing flops and patterns report will not be generated since
the design contains compression structures.
EXPLANATION:
This program is run with either explainfailingflops=yes and/or
explainfailingpatterns=yes specification which is not supported for designs
containing compression structures.
USER RESPONSE:
None.
INFO (TDG-064): Started identifying best test sequences for scan chain diagnostics using
algorithm_type algorithm.
EXPLANATION:
The program has completed running simulations and the process of identifying the best
test sequences based on the specified algorithm is started.
USER RESPONSE:
None.
INFO (TDG-065): Distribution of diagnostics bit range sizes after selecting the sequence
test_sequence Showing cumulative results after selecting
best_test_sequence_selected out of total_best_sequence_requested
sequences based on algorithm
EXPLANATION:
The informational message shows the distribution of diagnostics bit range sizes using
histogram after selecting the given <N> sequence(s) out of total best test sequence
requested. This is a perrank histogram format and reported sequence by sequence
basis. The histogram shows the relative number of bit ranges with a specific size (or
range of sizes) using a row of asterisks ('*'). The cumulative percentage is denoted by
the vertical bar ('|'). The X axis is normalized to a percentage of faults, assuming only a
stuck-at-0 and a stuck-at-1 fault for each scanned latch in the test mode. Each asterisk
in the bar is nominally equal to 1%. The only exception being that a bit range size (or
range of sizes) with a non-zero number of occurrences will have at least one asterisk
(even if the number of occurrences does not round up to 1%).
USER RESPONSE:
None.

INFO (TDG-067): Final Distribution of bit range sizes after selecting the best test sequences
for scan chain diagnostics. Showing cumulative results after selecting
test_sequence_selected out of total_best_test_sequence_requested
sequences based on algorithm :
EXPLANATION:
The informational message shows the final summary of distribution of diagnostics bit
range sizes using histogram after selecting all best test sequence requested. This is a
summary histogram reporting format and reported at the end of the run. The histogram
shows the relative number of bit ranges with a specific size (or range of sizes) using a
row of asterisks ('*'). The cumulative percentage is denoted by the vertical bar ('|'). The
X axis is normalized to a percentage of faults, assuming only a stuck-at-0 and a stuck-
at-1 fault for each scanned latch in the test mode. Each asterisk in the bar is nominally
equal to 1%. The only exception being that a bit range size (or range of sizes) with a
non-zero number of occurrences will have at least one asterisk (even if the number of
occurrences does not round up to 1%).
USER RESPONSE:
None.
INFO (TDG-069): Completed identifying best test sequence for scan chain diagnostics using
algorithm_type algorithm. Time used: CPU_time/elapsed_time.
EXPLANATION:
The program has completed the identification of the best test sequence based on the
specified algorithm.
USER RESPONSE:
None.
INFO (TDG-071): Start of Physical Diagnostics Fault Selection Report:

EXPLANATION:
Informational message indicating the start of Physical Diagnostics Fault Selection
Report.
USER RESPONSE:
None.
INFO (TDG-074) Start of Physical Diagnostics Fault Selection Report:

EXPLANATION:

Informational message indicating the start of Physical Diagnostics Fault Selection

Report.
USER RESPONSE:
INFO (TDG-075) End of Physical Diagnostics Fault Selection Report. Time used
CPU_time/elapsed_time.
EXPLANATION:
Informational message indicating the end of Physical Diagnostics Fault Selection Report.
USER RESPONSE:
None.
WARNING (TDG-076): Net net_name was not included in server's response. Net pairs for
this net are not generated.
EXPLANATION:
The Physical Design server could not find the specified net and hence no net pairs for
this net are not generated.
USER RESPONSE:
Analyze the reported net to identify the cause of this situation. Fix the problem and rerun
if needed.
WARNING (TDG-077): Net net_name was part of server's response but was not part of
the original input list.
EXPLANATION:
The given net name did not match with any net present in the original input list. However,
the Physical Design server had returned adjacent nets for the given net.
USER RESPONSE:
Analyze the reported net to identify the cause of this situation. Fix the problem and rerun
if needed.
WARNING (TDG-078): Driver pin driver_pin_name was not included in server's

response. OPEN faults for this driver pin will not be modeled.
EXPLANATION:

The Physical Design server could not find the specified driver pin and hence the driver
faults for the reported pin will not be modeled.
USER RESPONSE:
Analyze the reported pin to identify the cause of this situation. Fix the problem and rerun
if needed.
WARNING (TDG-079): Driver pin driver_pin_name was part of server's response but
was not part of the original input list.
EXPLANATION:
The given driver pin name did not match with any pin name present in the original input
list. However, the Physical Design server had returned receiver pin list of given driver pin
name.
USER RESPONSE:
Analyze the reported pin to identify the cause of this situation. Fix the problem and rerun
if needed.
WARNING (TDG-080):
EXPLANATION:
The receiver pin list combination for given driver pin name did not have faults on their
respective receiver pins. Hence, no OPEN fault for given fault type will be modelled. This
program currently does not support the process of identifying the equivalent faults
associated with the receiver pins and including them in the OPEN fault modeling.
USER RESPONSE:
Contact the customer support team using your normal process; sourcelink, email, or
direct call to the customer support line, and provide the complete text of the message.
WARNING (TDG-081): Callout file will not be produced for this invocation and is not
supported for Physical Diagnostics flow.
EXPLANATION:
Generation of callout report binary file is not supported for Physical Diagnostics flow.
USER RESPONSE:
If the generation of callout binary file is a mandatory step in your methodology, contact
the customer support team using your normal process; sourcelink, email, or direct call to
the customer support line, and submit an enhancement request.

INFO (TDG-082): The scan chain diagnostics dictionary files are deleted successfully.
EXPLANATION:
The scan chain diagnostics dictionary files are successfully deleted.
USER RESPONSE:
None.
INFO (TDG-083): The scan chain diagnostics dictionary files are not present and hence
could not be deleted.
EXPLANATION:
The scan chain diagnostics dictionary files are not present and hence could not be
deleted.
USER RESPONSE:
None.
WARNING (TDG-084): Observable scan chain observable_scanchain_id has zero

scan chain length. Scan chain tracing will not be performed.
EXPLANATION:
The specified observable scan chain has zero length and hence scan chain tracing will
not be performed on this scan chain.
USER RESPONSE:
None.
ERROR (TDG-085): Observable scan chain observable_scanchain_id has zero

scan chain length. Scan chain tracing will not be performed.
EXPLANATION:
The specified observable scan chain has zero length and hence scan chain tracing will
not be performed on this scan chain.
USER RESPONSE:
None.
WARNING (TDG-086): Observable scan chain observable_scanchain_id is

possibly corrupted. Scan chain tracing will not be performed.
EXPLANATION:

The program is not able to process the scan flops in the reported scan chain and hence
the tracing could not performed.
USER RESPONSE:
Report the entire scan chain information using report_test_structures command
and determine the cause of this situation.
ERROR (TDG-087): There are no observable scan chains in the testmode for performing
the scan chain tracing. Refer to preceding messages. Processing Ends.
EXPLANATION:
The program is unable to find one or more observable scan chains in the testmode for
performing the scan chain tracing.
USER RESPONSE:
Report the observable scan chain information using report_test_structures
command and determine the cause of this situation. If the testmode specified for this
command is incorrect, rerun with appropriate testmode.
INFO (TDG-088): Start of callout histogram containing the number of non-composite faults
in a given score range:
EXPLANATION:
Informational message indicating the start of callout histogram.
USER RESPONSE:
None.
INFO (TDG-089): End of callout histogram.

EXPLANATION:
Informational message indicating the end of callout histogram.
USER RESPONSE:
None.
WARNING (TDG-090): The diagnostic process is unable to model any physical faults from
the selected logic faults. Simulation ends here.
EXPLANATION:
The diagnostic process is unable to model any physical faults from the selected logic
faults. Either physical fault selection criteria is not allowing enough logic faults to be

selected for physical fault modeling or physical layout abstraction information is not
available.
USER RESPONSE:
Correct the values of physicalfaultset and physicalfaultsetscoremargin to
allow more logic faults to be selected for physical fault modelling. If problem continues,
look for the presence of physical layout abstraction data for the selected logic faults.
ERROR (TDG-092): The file type file could not be opened.

EXPLANATION:
The binary file for netadjacency data and subnet data could not be opened in tbdata
directory
USER RESPONSE:
Please ensure enough space is present.

INFO (TDG-096): A total of number_of_failures failures summary_of_failures
will be processed for device device_name.
EXPLANATION:
This message identifies the number of failures which will be processed for the indicated
device. When this number is less than the total number of failures in the specified failset,
see preceding messages for detailed explanation.
USER RESPONSE:
None.
INFO (TDG-097): A total of number-of-failures failures will be processed for the

specified devices.
EXPLANATION:
This message identifies the number of failures which will be processed for all specified
devices. When this number is less than the total number of failures in the specified failset,
see preceding messages for detailed explanation.
USER RESPONSE:

INFO (TDG-098): Generation of normalization file for type started.

EXPLANATION:
The normalization file for the specified physical attribute is being generated.
USER RESPONSE:
None.
WARNING (TDG-099): The normalization file for type normalization_file already

exists and is readable.
EXPLANATION:
The normalization file for the specified physical attribute is already present and the
program does not regenerate this file.
USER RESPONSE:
None. If user intends to create a new normalization file due change in OA database or
change in the model, remove the existing file and rerun this command.
100 INFO (TDG-100): The normalization file for type normalization_file is

successfully created.
EXPLANATION:
The normalization file for the specified attribute is successfully generated.
USER RESPONSE:
None. User can perform volume analysis or run update_diagnostic_journal to
generate normalized paretos for the specified physical attribute.
INFO (TDG-102): No EXPERIMENT specified, using committed vectors.

EXPLANATION:
This application operates on a vector set. This can be either the committed vectors or an
uncommitted set. When EXPERIMENT is unspecified, the committed vectors are used.
USER RESPONSE:
ERROR (TDG-103): The testrange keyword is specified with an invalid value fail.
EXPLANATION:

The value specified to the testrange keyword is not supported.

USER RESPONSE:
Specify a valid value for the testrange keyword and rerun.
WARNING (TDG-104): The callout reported is not accurate since the original diagnostics
run is stopped after stop_after_iteration iterations. The capability to report latches-
in-play in report_callout is not supported.
EXPLANATION:
If stopafteriteration keyword is specified to diagnose_failset_scanchain,
the program stops after performing the specified iterations and the final callout report will
contain the latches-in-play that indicate the range of bits where the diagnostics is yet to
be performed. The current callout is generated from such diagnostics run that is stopped
before completing all the iterations due to stopafteriteration keyword
specification. Currently, reporting the latches-in-play in the callout report generated by
this command is not supported. The callout report contains the best bit and the best
score generated from the simulation iterations performed.
USER RESPONSE:
None.
ERROR (TDG-105): Experiment experiment not found. Specify a valid EXPERIMENT

name.
EXPLANATION:
The application attempted to obtain a Read Lock on this experiment and the return
indicates that the experiment does not exist.
USER RESPONSE:
Pick an experiment that does exist and rerun.
ERROR (TDG-106): Scan Chain test failed and the fail type is not determined. The program
only supports stuck fault scan chain diagnostics when OPMISR is present.
EXPLANATION:
OPMISR is inserted in the design and the program is run in OPMISR mode. Currently,
diagnose_failset_scanchain performs scan chain diagnostics only when the
defect behaves completely like stuck fault.
USER RESPONSE:
No response needed.

INFO (TDG-107): Previous Diagnostics Simulations have processed all the specified
patterns. The request to append is not valid.
EXPLANATION:
The invocation included append=yes, however all the specified patterns have already
been processed by previous diagnostic runs for this callout. Therefore, no Simulation will
be performed by this run.
USER RESPONSE:
There is no user action required unless the input vectors have been erroneously
specified. If this is the case, correct the erroneous keyword (for example, experiment,
failset, or testrange), and rerun.
ERROR (TDG-108): Scan Chain Database diagnosability dictionary is not present.

Processing ends.
EXPLANATION:
The program has not found scan chain diagnosability dictionary in the Encounter Test
database. The availability of this dictionary is necessary for identifying the upper bound
information.
USER RESPONSE:
Run analyze_chain_diagnosability to create the scan chain diagnosability
dictionary and rerun.
ERROR (TDG-109): Specified Test Range does not contain patterns with scan unload
events.Processing ends.
EXPLANATION:
Specified Test Range does not contain patterns with scan unload events. Hence, the
processing ends.
USER RESPONSE:
Correct the testrange specification and rerun.
WARNING (TDG-110): The testrange specification testrange_specification is not

correctly formatted. It will be ignored.
EXPLANATION:
One of the comma separated test ranges in the testrange specification is not in correct
format.

USER RESPONSE:
Correct the testrange specification and rerun. Refer to "diagnose_failset_logic" in the
Encounter Test: Reference: Commands for additional information.
INFO (TDG-111): analyze_chain_diagnosability completed simulation on all the

chain(s).
EXPLANATION:
This is a informational message indicating the completion of simulation in
analyze_chain_diagnosability.
USER RESPONSE:
No response is needed.
ERROR (TDG-112): Invalid value value specified for keyword keyword. Processing
ends.
EXPLANATION:
This message is issued whenever an error is encountered during the processing of the
command line. The keyword is ignored and the remainder of the command line is
checked for errors. The run will be terminated immediately after command line checking
is completed.
USER RESPONSE:
Either omit the keyword or specify an allowed value and rerun. Refer to
"diagnose_failset_logic" in the Encounter Test: Reference: Commands for additional
information.
INFO (TDG-113): The existing scan chain diagnosability binary file will be replaced due to
replace=yes specification.
EXPLANATION:
The program has found an existing scan chain diagnosability database file in the
Encounter Test database. This invocation is made with replace=yes option indicating
that the existing file should be replaced if it exists. Hence, the processing ends.
USER RESPONSE:
Rerun the program with replace=no(default) if you dont want to replace the existing
scan chain diagnosability binary file. If you wish to make this run with out creating the
scan chain diagnosability database file, rerun the command with writebinary=no.
ERROR (TDG-114): There are no scan chains defined. Processing ends.

EXPLANATION:
This run requires at least one scan chain to be defined. There are no scan chains defined
for this test mode.
USER RESPONSE:
Specify a test mode with defined scan chains and rerun. Refer to
"diagnose_failset_scanchain" in the Encounter Test: Reference: Commands for
ERROR (TDG-115): Unable to determine scan-out from name name. Processing ends.
EXPLANATION:
This run requires a scan chain be specified by way of its scan-out. A scan-out could not
be determined from the name provided.
USER RESPONSE:
Correct the scan-out name and rerun.
ERROR (TDG-116): Scan-out name name is ambiguous. Processing ends.

EXPLANATION:
This run requires a scan chain be specified by way of its scan-out. The specified scan-
out name maps to multiple objects in the model.
Consequently, the desired scan chain cannot be determined.
USER RESPONSE:
Specify a unique scan-out name and rerun.
ERROR (TDG-117): Scan chain could not be determined from scan-out name. Processing
ends.
EXPLANATION:
This run requires a scan chain be specified by way of its scan-out. An Observable Scan
Chain could not be determined from the specified name.
USER RESPONSE:
Correct the scan-out name and rerun.
ERROR (TDG-118): Scan-out name is shared by multiple scan chains. Processing ends.
EXPLANATION:

This run requires a scan chain be specified by way of its scan-out. The specified scan-
out is shared by multiple Observable Scan Chains.
Consequently, the desired scan chain cannot be determined.
USER RESPONSE:
Correct the scanout name, if necessary, and rerun.
ERROR (TDG-119): Invalid value of number_specified specified for bitrange - the

scan chain has a total of actual_number bits. Processing ends.
EXPLANATION:
The indicated value specified for bitrange is invalid because it exceeds the actual
number of bit positions in the specified scan chain.
USER RESPONSE:
Correct the indicated value for bitrange or the scan-out name and rerun.
INFO (TDG-120): Status of analyze_chain_diagnosability simulation. Simulation

completed on simulated_chains chain(s) and remaining on remaining_chains
chain(s).
EXPLANATION:
This is a informational message indicating the status of the simulation in
analyze_chain_diagnosability.
USER RESPONSE:
No response is needed. With the information printed in this message, user can
approximately calculate the time taken to execute this command. If the time taken to
simulate 'n' chains is say 'X', then the time taken to simulate remaining 'm' chains will be
(m/n)*X.
INFO (TDG-121): Report of best test sequence for scan chain diagnostics:
EXPLANATION:
Informational message indicating the start of Report of best test sequence for scan chain
diagnostics. Following is a description of the report:
Rank : Report rank of the Pattern.
SA0_Coverage : Estimated SA0 pattern coverage for the design.
SA1_Coverage : Estimated SA1 pattern coverage for the design.

Coverage : Estimated cumulative pattern coverage for the design.

USER RESPONSE:
None.
End of Report of best test sequences for scan chain diagnostics.

EXPLANATION:
Informational message indicating the End of Report of best patterns for scan chain
diagnostics.
USER RESPONSE:
None.
ERROR (TDG-123): The scan chain diagnosability database file already exists and
replace=no(default) is specified. Processing ends.
EXPLANATION:
The program has found an existing scan chain diagnosability database file in the
Encounter Test database. This invocation is made with replace=no(default) option
indicating that the existing file should not be replaced if it exists. Hence, the processing
ends.
USER RESPONSE:
Rerun the program with replace=yes if you wish to replace the existing scan chain
diagnosability database file. If you wish to make this run with out creating the scan chain
diagnosability database file, rerun the command with writebinary=no.
WARNING (TDG-124): A total of number_of_miscompares miscompares were

detected during simulation. Diagnostic results are suspect.
EXPLANATION:
The diagnostic monitor detected the indicated number of miscompares, or discrepancies
between the expected values in the input vector file, and the corresponding values
determined by this simulation. In this case, the discrepancies were known (or non-X),
versus known values. Since the diagnostic monitor does not gather statistics for faults
detected at miscomparing measure points, the diagnostic results may be misleading.
USER RESPONSE:
In the majority of cases, this condition should have no significant impact on the diagnostic
result and thus can be ignored. However if the number of miscompares is extremely high
or there are miscompares present on failing measure points, their root cause should be

identified and corrective action taken prior to proceeding with diagnostics. Providing the
diagnostic simulation was performed using comparemeasures=yes (the default), this
message should be preceded by messages issued by the simulator that identify the
actual miscompares.
Examine these messages for further analysis.
WARNING (TDG-125): A total of number_of_miscompares X versus known

miscompares were detected during simulation. Diagnostic results are suspect.
EXPLANATION:
Diagnostics Simulation detected the indicated number of miscompares, or discrepancies
between the expected values in the input vector file, and the corresponding values
determined by this simulation. In this case, the input vector file indicated unknown (or X)
values but simulation produced known (or non-X) values. Since diagnostics simulation
does not gather statistics for faults detected at miscomparing measure locations, the
results may be misleading.
USER RESPONSE:
In the majority of cases, this condition should have no significant impact on the diagnostic
result and thus can be ignored. However if the number of miscompares is extremely high
or there are miscompares present on failing measure points, their root cause should be
identified and corrective action taken prior to proceeding with diagnostics. Diagnostics
simulation can be rerun specifying ignorexmeasures=no and
comparemeasures=yes. This will cause the simulator to issue additional messages,
each reporting an individual miscompare.
ERROR (TDG-126): Logic model not available. It is currently being updated or reimported.
Processing ends.
EXPLANATION:
The application is attempting to read the logic model and has determined that the model
is being updated.
USER RESPONSE:
Retry after the model is available.
ERROR (TDG-127): Experiment experiment not available because is it being updated

Processing ends.
EXPLANATION:
The application is attempting to read the specified experiment, and has determined that
the experiment being updated.

USER RESPONSE:
Retry after the experiment is available.
ERROR (TDG-128): Simultaneous Diagnostics Simulation runs are using the same
experiment.
EXPLANATION:
Diagnostics Simulation tried to get a Read Lock on temporary files and the return
indicates that the experiment is in use. This can only happen if multiple simulations of the
same input experiment are being run simultaneously.
USER RESPONSE:
Retry after the experiment is free to be used.
ERROR (TDG-130): Error attempting to open the fault model.

EXPLANATION:
The application attempted to open the fault model file, however an error was encountered
preventing this and caused termination. This message is preceded by other messages
explaining the problem.
USER RESPONSE:
Respond to preceding mesages and rerun.
ERROR (TDG-131): The test mode definition file is specified with signatures type 'final'. The
program does not support diagnostics on test modes with this specification. Processing ends.
EXPLANATION:
To perform logic diagnostics in OPMISR mode, signatures should be measured after
every sequence. In this case, the signatures type is specified as 'final' in the mode
definition file.
USER RESPONSE:
Contact the customer support (see Contacting Customer Service on page 23) and
provide the complete text of the message.
ERROR (TDG-132): FAILSET and target cannot have the same value. Processing ends.
EXPLANATION:

The specified input failset name and the target failset name are identical.
prepare_failset_partition requires that the input FAILSET and the output target
names be different. The identically specified names caused the run to terminate.
USER RESPONSE:
Specify a new target failset name and rerun.
ERROR (TDG-133): Error attempting to open input pattern file.

EXPLANATION:
The application attempted to open the input vector file, however an error was
encountered preventing this. Processing ends. This message will be preceded by other
messages explaining the problem.
USER RESPONSE:
Respond to preceding messages.
INFO (TDG-134): Experiment experiment is currently in use. Waiting for experiment to

become available.
EXPLANATION:
The application has tried to get a Read Lock on the input experiment and found it busy.
As directed by the user, it will wait until it becomes free.
USER RESPONSE:
INFO (TDG-135): Experiment experiment is now available. Processing continues.

EXPLANATION:
The application has waited for an input experiment to become available. It is now
available.
USER RESPONSE:
ERROR (TDG-136): Error attempting to open failure data for failset failset_name. See
preceding messages for further information about the error.
EXPLANATION:
An error was encountered preventing the target failst from being read.

USER RESPONSE:
Respond to the preceding messages, correct problems, and then rerun.
WARNING (TDG-137): One or more cloaked pins|nets are included in the callout report.
EXPLANATION:
The callout report includes logic which is cloaked. The names of cloaked pins and nets
are omitted from the callout report and replaced with *** cloaked <pin or net>
***.
USER RESPONSE:
When pin and net names within cloaked logic are required and access is allowed, use
standard procedures for viewing the contents of cloaked logic. Otherwise this message
can be ignored.
WARNING TDG-138): Asterisks indicate callouts that exist on cut points. For these callouts,
the actual defect may reside in the unsimulated logic behind the cut point.
EXPLANATION:
This message indicates that one or more callouts were reported with asterisks (*) in the
first column of the callout report. The asterisk indicates which callout locations are
associated with a cut point for the test mode. This is evidence that the actual defect being
diagnosed may be located in logic behind (or feeding) a cut point and not necessarily at
the reported callout location.
USER RESPONSE:
Asterisks associated with lower scoring callouts can normally be ignored. Asterisks on
higher scoring callouts may require additional analysis to determine actual defect
location.
ERROR (TDG-139): Failed to obtain a license for product product_name. Processing

ends.
EXPLANATION:
A required license could not be obtained for the indicated product. The run cannot
proceed without the required licenses.
USER RESPONSE:
Ensure the availability of the required license, the rerun.
location.

INFO (TDG-140): The number of bits reported in the range are restricted to
maximum_bits_to_report because of maxbitstoreport specification.
EXPLANATION:
Informational message indicating that the number of bits reported in between the range
is restricted because of maxbitstoreport specification.
USER RESPONSE:
ERROR (TDG-141): Scan chain corresponding to scan-out name is not controllable.

Processing ends.
EXPLANATION:
This run requires a scan chain be specified by way of its scan-out. The specified scan
chain must be controllable in the test mode. The specified scan chain is not controllable
in this test mode.
USER RESPONSE:
Correct the scan-out name or the TESTMODE and rerun.
ERROR (TDG-142): Faultset file file_name does not exist or cannot be opened.
EXPLANATION:
An attempt to open the indicated faultset file failed. This is most likely because the file
does not exist.
USER RESPONSE:
Check the file name provided by way of the faultset keyword and rerun.
ERROR (TDG-143): Keywords experiment and calloutexperiment are both

specified as experiment_name.
EXPLANATION:
Both the experiment and calloutexperiment keywords were specified in the
form of the indicated name. This is not permitted since the newly generated output
experiment would overwrite the input experiment.
USER RESPONSE:
Check that the calloutexperiment keyword is set as desired in that it qualifies the
callout data to be used as input. If not, correct it and rerun.

Otherwise, change the value specified for the experiment keyword and rerun. Refer
to "diagnose_failset_logic" in the Encounter Test: Reference: Commands for
WARNING (TDG-144): [Severe] Received non-static fault fault_index to distinguish,

however only static faults are supported. The run continues, ignoring this fault.
EXPLANATION:
The indicated fault is included in the list of faults to be distinguished and is not a static
fault. Currently, only static faults are supported by this application. The run continues, but
this fault is ignored.
USER RESPONSE:
Disregard this message if it is acceptable that this fault be ignored. If an incorrect
faultset has been specified, specify a new faultset and rerun.
WARNING (TDG-145): The scan chain diagnosability dictionary file is not available. The
identifyboundfromdictionary=yes specification will not perform bound finding from
the dictionary file.
EXPLANATION:
This invocation contains identifyboundfromdictionary=yes specification which
requires the availability of the scan chain diagnosability dictionary file generated by
analyze_chain_diagnosability command. In this case, the scan chain
diagnosability dictionary file is not available and hence the bound identification can not
be done using dictionary lookup.
USER RESPONSE:
If bound finding from the scan chain diagnosability dictionary file is desired, create this
file by running analyze_chain_diagnosability command. If not, remove the
identifyboundfromdictionary=yes specification and rerun to resolve this
warning.
ERROR (TDG-146): Fault fault_iedntifier is not a dynamic fault. Processing ends.

EXPLANATION:
This run requires a dynamic fault be specified, however the indicated fault is not a
dynamic fault.
USER RESPONSE:
Specify a dynamic fault and rerun.

ERROR (TDG-147): Invalid fault faultID was specified. Processing ends.

EXPLANATION:
This run requires a dynamic fault be specified, however the indicated fault is not within
the range of valid fault indices for this design.
USER RESPONSE:
ERROR (TDG-148): A dynamic fault was not detected as required. Processing ends.
EXPLANATION:
This run requires a dynamic fault be specified, however no dynamic fault was detected.
This is most likely caused by an incorrect fault type specification in the fault rule file.
USER RESPONSE:
ERROR (TDG-149): Unable to register object object_Name. Processing ends.

EXPLANATION:
The identified object could not be registered in the Encounter Test globalData file. This
may be due to a program error, but could also be a user problem (e.g., permissions).
USER RESPONSE:
Check for preceding messages to determine whether another, possibly related problem
has been identified and take appropriate corrective action. It is possible re-importing the
design could correct the problem. Otherwise, contact customer support (see Contacting
WARNING (TDG-150): Error attempting to save globalData. Output files may exist but are
not registered.
EXPLANATION:
The application has asked that the globalData be saved. The return from this action
indicates that it was not successful. The run completes. However the condition of the
globalDate file is suspect.
USER RESPONSE:
Other messages are expected for response.


ERROR (TDG-151): The use of argument is invalid for callout_type callouts.
EXPLANATION:
The referenced argument is not valid when analyzing callouts of the referenced type.
USER RESPONSE:
Remove the argument from the program invocation and rerun.
INFO (TDG-152): The type test section is in the specified test range, but will not be
simulated.
EXPLANATION:
This condition can occur when unsupported test sections are present within the specified
test range, or when performing Scan Diagnostics and non-logic test sections are
encountered.
USER RESPONSE:
INFO (TDG-153): Trace started for measure register measure_register. Report will be
stored in file: chain_trace_log.
EXPLANATION:
This message identifies the start of tracing for the specified scan chain and also the
location of the report file.
USER RESPONSE:
INFO (TDG-154): Trace completed for measure register measure_register. Time

used: CPU_time/elapsed_time.
EXPLANATION:
Informational message indicating the end of scan chain trace for the specified measure
register.
USER RESPONSE:

ERROR (TDG-155): The specified measure register measure_register in the keyword

keyword is greater than the maximum scan chains scan_chains.
EXPLANATION:
The specified measure register number is outside the number of scan chains present in
the design.
USER RESPONSE:
Specify a measure register number less than the maximum number of scan chains.
INFO (TDG-156): report_scanchains completed loading design and testmode

information. Time used: CPU_time/elapsed_time.
EXPLANATION:
This message indicates the completion of loading the design and testmode information
required for performing the circuit tracing.
USER RESPONSE:
message_severity (TDG-157): A control register for the measure register

measure_register could not be found. report_scanchains supports tracing on
chains that are both controllable and observable.
EXPLANATION:
A control register could not be identified for the specified measure register.
report_scanchains currently supports tracing only those scan chains that are both
controllable and observable.
USER RESPONSE:
ERROR (TDG-158): Error attempting to initialize the diagnostic monitor.

EXPLANATION:
The application invoked the diagnostic monitor with an initial call. The diagnostic monitor
returned an error return code. Processing ends.
USER RESPONSE:
Look for error messages from the diagnostic monitor.
ERROR (TDG-159): Error keyword=value not understood.

EXPLANATION:
The value specified for the keyword is not understood by the diagnostic simulator.
Processing ends.
USER RESPONSE:
Check the syntax of the invocation options used. Refer to "diagnose_failset_logic"" in the
ERROR (TDG-160): You are required to specify a Design Under Test using the WORKDIR
keyword.
EXPLANATION:
Processing cannot continue without a fully specified working directory.
USER RESPONSE:
Specify the working directory associated with the design using the WORKDIR keyword on
the command line, or by exporting it as an environment variable, and then rerun.
WARNING (TDG-161): Cannot load block 0.

EXPLANATION:
While processing the results of Diagnostics Simulation to color the blocks displayed by
Encounter Test, an error occurred accessing the Encounter Test logic model.
USER RESPONSE:
There will undoubtedly be more than one message produced by Encounter Test when
this type of error is encountered.
ERROR (TDG-162): Unable to register dependency for object object_Name.

EXPLANATION:
The identified object could not have a dependency registered against it in the Encounter
Test globalData file. This may be due to a program error, but could also be a user problem
(e.g., permissions).
USER RESPONSE:
Check for preceding messages to determine whether another, possibly related problem
has been identified and take appropriate corrective action. It is possible that re-importing
the design could correct the problem. Otherwise, contact customer support (see

INFO (TDG-163): fail_count failcharacter read

EXPLANATION:
This informational message reports the number of fails read.
USER RESPONSE:
ERROR (TDG-164): You cannot specify both the cone and subset options with the
diagnostic simulator.
EXPLANATION:
Conflicting simulation options have been specified. Processing ends.
USER RESPONSE:
Resolve the conflict and rerun.
INFO (TDG-166): Dropped fault summary:

EXPLANATION:
Informational message heading a summary of dropped fault totals for the run by specific
category. The categories are defined as follows:
futile - fault scoring threshold
maxfaultsize - fault machine activity limit
maxfaultxsize - fault machine X, or unknown state activity activity limit
oscillation - fault machine oscillation limit
USER RESPONSE:
No response is required when the default fault dropping criteria is acceptable. When an
alternate fault dropping criteria is desired, rerun with a modified setting for the category
using the appropriate keyword as indicted in the following table.
Category Keyword
futile futile
oscillation osclim for General Purpose simulation
osc for Hierarchical Fault simulation

Category Keyword
maxfaultsize maxfaultsize for High Speed Scan Based simulation
machinesize for General Purpose simulation
activity for Hierarchical Fault simulation
maxfaultxsize maxfaultxsize
message_severity (TDG-167): report_name

EXPLANATION:
None
RESPONSE:
(TDG-168) report_name
EXPLANATION:
None.
USER RESPONSE:
INFO (TDG-169): Program ends due to stopafterfaultselection=yes specification.

EXPLANATION:
This message indicates the early termination of the program after fault selection process
is completed.
USER RESPONSE:
None.
ERROR (TDG-170): The program has detected corruption in scan chain diagnosability
dictionary file sequence_dictionary_file_name. Printing will be stopped.
EXPLANATION:
The program has detected corruption in the given sequence based scan chain
diagnosability dictionary file. The file header content does not match the desired data
structure format.
USER RESPONSE:

If file was corrupted by manual intervention, rerun

analyze_chain_diagnosability. Otherwise, contact customer support .
INFO (TDG-171): Summary of Known values for each test sequence simulated:
EXPLANATION:
Informational message displaying the count of known values for each test sequence
simulated during the best test sequence identification process.
USER RESPONSE:
INFO (TDG-173): A diagnostic callout is not being produced.

EXPLANATION:
No examples were found for any fault by the diagnostic simulator.
USER RESPONSE:
WARNING (TDG-174): The test sequences in testrange specification do not match with the
best test sequences present in scan chain dictionary. Hence, information in the scan chain
dictionary could not be used for determining initial upper bound.
EXPLANATION:
This warning message is reported due to identifyboundfromdictionary=yes
specification, which requests the program to identify upper bound from scan chain
dictionary. The upper bound information available in the dictionary is valid only when the
best test sequences identified by the analyze_chain_diagnosability command
are applied on the tester and the same set of test sequences are specified for this
program. If different test sequences are applied on the tester, the upper bound
information present in the dictionary will be invalid and should not be used to determine
the upper bound. In this case, scan chain dictionary contains different set of best test
sequences, which do not match with the test sequences specified in testrange.
USER RESPONSE:
If you wish to identify upper bound from scan chain diagnostics dictionary files, rerun the
command with the best test sequences reported by
analyze_chain_diagnosability command.
INFO (TDG-175): Dropping fault fault_index (reason) on pin pin_index pin_name

cell_name

EXPLANATION:
A fault is being dropped for the reason stated during simulation.
USER RESPONSE:
INFO (TDG-176): The application will exit as soon as possible.

EXPLANATION:
The application has received a signal request to stop execution. The program will attempt
to exit gracefully.
USER RESPONSE:
INFO (TDG-177): The application will exit prior to any simulation.

EXPLANATION:
to exit gracefully.
USER RESPONSE:
INFO (TDG-178): The application will exit after simulating procedure

experiment.test_section.tester_loop.test_procedure.
EXPLANATION:
to exit gracefully.
USER RESPONSE:
INFO (TDG-179): The application is currently simulating procedure

experiment.test_section.tester_loop.test_procedure.
EXPLANATION:
The application has received a signal request to print execution status.
USER RESPONSE:

INFO (TDG-180): The application is in its initialization stage.

EXPLANATION:
USER RESPONSE:
INFO (TDG-181): The application is in its reporting results stage.

EXPLANATION:
USER RESPONSE:
ERROR (TDG-182): A system crash is imminent. Simulation will be stopped.

EXPLANATION:
The program has received a signal from the operating system indicating that a system
crash is imminent due to low paging space. The program will attempt to recover and exit
gracefully. The results, if any, may be suspect.
USER RESPONSE:
Although it is possible that the signal was received after the results were produced, in
most cases the program will need to be rerun. If a checkpoint had been taken, a TDG-
301 message will appear in the log, and you may rerun specifying restart=yes.
ERROR (TDG-183): Unable to open callout file file_name.

EXPLANATION:
Encounter Test was unsuccessful opening the specified callout file.
USER RESPONSE:
See preceding messages, resolve the indicated problems, and rerun.
ERROR (TDG-184): Unable to verify callout registration.

EXPLANATION:

The specified callout is found to be unregistered. As a consequence, the callout data is

not expected to exist.
USER RESPONSE:
See preceding messages.
INFO (TDG-185): Append cannot be performed because no previous callout information

exists. Diagnostics Simulation proceeds and will produce a new callout.
EXPLANATION:
No further explanation needed.
USER RESPONSE:
ERROR (TDG-186): The specified options conflict with the options used to produce the
callout you are attempting to append to as indicated in the list below. Processing ends.
EXPLANATION:
Append has been specified for the current Diagnostics Simulation invocation. The
previous Diagnostics Simulation was run with conflicting run-time controls. Examples
would be different monitors or simulators chosen between the two invocations.
USER RESPONSE:
Restart the current simulation with the same arguments that were used in the previous
invocation, or remove the append request. Note that removing the append request will
discard the diagnostic callout results from the previous invocation.
WARNING (TDG-187): [Severe] One or more miscompares were detected for the
event_type event at location odometer.
EXPLANATION:
Diagnostics Simulation results differ from the expected results.
USER RESPONSE:
There is no single response to this message. Some miscompares are easily explained,
others indicate simulation errors or test pattern problems.
ERROR (TDG-188): Dynamic scan chain test(s) were selected which require an LSSD scan
type. These tests cannot be generated because this Design Under Test does not have a scan
type of LSSD.

EXPLANATION:
There are several dynamic scan chain tests which utilize A-SHIFT_CLOCKs and
B_SHIFT_CLOCKs for release and capture. In order to generate these tests, the scan
type of the Design Under Test must be LSSD, but it is not in this case.
USER RESPONSE:
Deselect the test(s) which require LSSD scan type and rerun.
INFO (TDG-189): type test section found. Test sections of this type are not fully supported
by the diagnostic simulator. However, simulation is allowed to continue.
EXPLANATION:
The application has read a test section type on the input Vectors file that the diagnostic
simulator does not fully support. However, processing is allowed to continue.
USER RESPONSE:
WARNING (TDG-190): A callout_sort_option sort specification is only valid for the

lpds monitor.
EXPLANATION:
This sort option identifies information that is not gathered by the monitor chosen at the
time of Diagnostics Simulation. The sort option will be ignored and an appropriate default
will be used in its place.
USER RESPONSE:
ERROR (TDG-192): Dynamic scan chain test(s) were selected which require skewed scan
loads. These tests cannot be generated because this Design Under Test does not support
skewed scan loads.
EXPLANATION:
There are several dynamic scan chain tests which utilize skewed loads for transition set-
up.
In order to generate these tests, the Design Under Test must support skewed scan loads.
This Design Under Test does not support skewed loads however.
USER RESPONSE:
De-select the test(s) which require skewed scan loads and rerun.

ERROR (TDG-193): Insufficient number of faults (number_of_faults) specified for fault

distinguishing. Processing ends.
EXPLANATION:
Given the current keyword settings, there are the indicated number of faults which
qualified for fault distinguishing. There must be at least two such faults, but there was less
than two in this case.
USER RESPONSE:
If specifying faultset=filename, where the file contains the faults to be
distinguished, check to ensure this file is of the proper format and contains two or more
faults, then rerun. Otherwise, if faultset=callout, check the settings of the
faultsetthreshold and faultsetscoremargin keywords to ensure they result
the inclusion of two or more faults, then rerun.
WARNING (TDG-195): [Severe] Unable to generate scan patterns for scan chain feeding
scan-out name.
EXPLANATION:
Several conditions must be met in order for patterns to be generated for a given scan
chain. The scan-out must be a Primary Output, the associated scan chain must be both
controllable and observable, and the associated scan-in must be a Primary Input which
is contacted by the tester. One or more of these conditions was not met for the scan chain
associated with the indicated scan-out.
USER RESPONSE:
Investigate the above conditions to determine what, if any, corrective action can be taken.
INFO (TDG-196): A total of number_of_fault_descriptions fault descriptions

were generated for bit position observable_register_bit_position,
Representative|B_SHIFT_CLOCK Measure Latch latch_output_net_name.
EXPLANATION:
Informational message indicating the number of fault descriptions generated for the
identified latch. This application attempts to generate patterns that laterally insert a logic
0 and/or 1 into each latch of the specified scan chain, by way of system ports. To
accomplish this, pattern fault descriptions(s) are created for each latch (excluding some,
e.g., scan-only latches). Each description contains a set of required values for inducing
the desired lateral insertion. For latches having multiple system ports, a fault description
is generated for each port. All pattern fault descriptions intended to laterally insert a
specific value into a latch, are grouped into an Or group. The descriptions are then used
to build an Alternate Fault Model which is utilized in the pattern generation process.

USER RESPONSE:
ERROR (TDG-197): No latches were detected for targeting along the scan chain feeding
scan-out scan_out_net_name.
EXPLANATION:
This application attempts to generate patterns which laterally insert a logic value into
each candidate latch along the specified scan chain, via functional paths. A latch is
considered a candidate for targeting if it is not a scan-only latch. This implies the latch
may be laterally inserted through a functional path. In this case, no candidate latches
were detected for the specified scan chain.
USER RESPONSE:
If all the latches along the specified scan chain are scan-only, no lateral insertion is
possible. Therefore, this application can not be effective at diagnosing the specified scan
chain and an alternative diagnostics approach should be pursued. Also ensure the
intended scan chain was specified. If not, rerun specifying the correct scan chain.
WARNING | ERROR (TDG-198): Transition exercising patterns were were generated with
the following attributes:
EXPLANATION:
No patterns were generated. This may be caused by any of the following reasons:
A terminating condition during test generation
Test generation aborting on all faults
Test generation determining no patterns can be generated
USER RESPONSE:
Determine the reason test generation failed to produce patterns by rerunning with
reportverbose=yes and examine the output to determine any corrective action to be
taken.
INFO (TDG-199): Transition exercising patterns were generated with the following attributes:
attributes
EXPLANATION:
Patterns were generated which exercise the specified transition(s).
USER RESPONSE:

INFO (TDG-200): Initializing Diagnostic Monitor.

EXPLANATION:
Informational message indicating the Diagnostic Monitor is being initialized.
USER RESPONSE:

ERROR (TDG-201): Unable to proceed when no failures are selected.
EXPLANATION:
Terminating message indicating there are no failures selected for simulation. This can
occur when:
testrange was specified in the form: fail,<,odometer range> and
there are failures in the specified odometer range. Note that the device
specification will also determine failure data selection.
append=no was specified.
USER RESPONSE:
Examine testrange, device and append specifications and make necessary corrections.
INFO (TDG-202): Initializing the Physical Design Server with oalib=library,

oacell=cell_name, oaview=cell_view.
EXPLANATION:
This informational message indicates the Physical Design Server is being initialized.
USER RESPONSE:
INFO (TDG-203): Physical Design Server initialization complete. Time used CPU_time/
elapsed_time.
EXPLANATION:
This informational message indicates the Physical Design Server completed.

USER RESPONSE:
INFO (TDG-204): Report Physical Correlation proceeding on

total_objects_to_process of
total_objects_in_Encounter_Test_model total type_of_objects.
EXPLANATION:
Informational message indicating the number of objects to be processed by Report
Physical Correlation. There are two types of objects processed:
nets connecting instances of technology cells
instances of technology cells
USER RESPONSE:
None.
INFO (TDG-205): Physical Correlation Final type_of_objects Report:

physical_correlation_report End of Physical Correlation Final Report. time
taken to correlate
EXPLANATION:
Informational message heading the final report generated by Report Physical
Correlation. A description of the report follows:
Nets Processed Number and percent of nets connecting instances of

technology cells processed.
Correlated Number and percent of nets connecting instances of
technology cells correlated to physical.
Uncorrelated Number and percent of nets connecting instances of
technology cells not correlated to physical.
Query Time (CPU/ CPU and Elapsed times associated with correlating
Elapse) instances of technology cells.
Cells Processed Number and percent of instances of technology cells
processed.
Correlated Number and percent of instances of technology cells
correlated to physical.

Uncorrelated Number and percent of instances of technology cells not

Query Time (CPU/ CPU and Elapsed times associated with correlating
Elapsed) instances of technology cells.
USER RESPONSE:
This message can likely be ignored with minimal negative consequence if there is a high
degree of reported logical-to-physical correlation (say 90% or greater). Otherwise the
logical-to-physical mismatches should be investigated. Individual misses are reported in
message TDG-215 - refer to those for more details. If TDG-215 messages are not
present, another Report Physical Correlation run will be necessary with
netcorrelationreport=uncorrelated or
cellcorrelationreport=uncorrelated to see status of each uncorrelated net or
cell respectively.
INFO (TDG-206): Physical Correlation Interim type_of_objects Report

interim_report_number: physical_correlation_report
End of Physical Correlation Interim Report. time taken to correlate

EXPLANATION:
Informational message heading the interim report generated by Report Physical
Correlation.
A description of the nets connecting instances of technology cells report follows:

Correlated Number and percent of nets connecting instances of
Uncorrelated Number and percent of nets connecting instances of
technology cells correlated to physical
A description of the instances of technology cells report follows:
Cells Processed Number and percent of instances of technology cells

processed.

Correlated Number and percent of instances of technology cells

Correlated Number and percent of instances of technology cells not
USER RESPONSE:
logical-to-physical mismatches should be investigated. Individual misses are reported in
message TDG-215 - refer to those for more details. another Report Physical Correlation
run will be necessary with netcorrelationreport=uncorrelated or
cellcorrelationreport=uncorrelated to see status of each uncorrelated net or
cell respectively.
ERROR (TDG-207): An invalid physical design location was detected. The oapath
specification does not identify a directory containing a readable lib.defs file. Processing ends.
EXPLANATION:
The physical design location specified by oapath appears to be invalid. This should
identify a directory which contains a readable lib.defs file. This file must be read in
order to load the physical design contained in OpenAccess.
USER RESPONSE:
Verify the oapath specification, correct if necessary and rerun.
If the specification is correct, verify that the file permissions associated with the
lib.defs file grant read authority. If not, correct the permissions and rerun.
ERROR (TDG-208): Initialization of the Physical Design Server failed. See preceding
messages.
EXPLANATION:
The Physical Design Server failed to initialize due to an error reading the physical design.
This error is most likely caused by an invalid specification of oapath, oalib, oacell or
oaview. This message should be preceded by additional messages which provide more
detail.
USER RESPONSE:
See the preceding messages and take any necessary corrective action and then rerun.

INFO (TDG-209): Build Bridge Fault Model will extract net pairs from
total_nets_to_process total nets connecting instances of technology cells.
EXPLANATION:
This message indicates the number of nets to be processed in the design. Only nets
connecting instances of technology cells are considered for net pair extraction.
USER RESPONSE:
INFO (TDG-210): Net Pair Extraction Final Report: net_pairs_report

End of Net Pair Extraction Final Report
EXPLANATION:
This message reports the final extracted net pairs. The report contains the following data:
Net Pair Details Report heading

Net Pairs Extracted Number of net pairs extracted.
Extraction Time CPU and elapsed times associated with net pair
(CPU/Elapsed) extraction.
Run Completion Report heading
Estimates
Net pairs Estimated number of net pairs for the run.
Faults to reach Estimated bridge faults required to reach adjacent metal
target coverage "coverage" limit.
Coverage achievable Estimated adjacent metal covered by "faults" limit.
at fault limit
USER RESPONSE:
The number of extracted netpairs should be of the order of number of nets in the design.
If the number is too large, excessive processing time will be consumed in simulating the
bridge fault model in diagnostics. The number of extracted netpairs is controlled by the
proximity and maxnetpairspernet keywords. If the number of extracted netpairs is
too large, analyze the value specified for the proximity keyword or reduce the number
specified for the maxnetpairspernet keyword and then rerun the command.

ERROR (TDG-211): The alternate_fault_model

<name>|net_pair_file|fault_rule_file already exists and replace=no was
specified. Processing ends.
EXPLANATION:
The indicated output file already exists and will not be overwritten because
replace=no. Processing ends with no output generated.
USER RESPONSE:
Either specify replace=yes to overwrite an existing file, or specify an alternate (non-
existent) output file and rerun. Specifying an alternate output file is accomplished by
using the following keywords:
ALTFAULT : alternate fault model
netpairfile : net pair file
faultrulefile : fault rule file
INFO (TDG-212): Net Pair Extraction Interim Report interval: net_pairs_report

End of Net Pair Extraction Interim Report.
EXPLANATION:
This message reports the interim extracted net pairs. The report contains the following
data:
Nets Pair Details Report heading

Nets processed Number and percent of nets connecting instances of
technology cells processed
Net Pairs Extracted Number of net pairs extracted
Extraction Time: CPU and elapsed times associated with net pair
(CPU/Elapsed) extraction
Run Completion Report heading
Estimates
Net Pairs Estimated number of net pairs for the run.
Faults to reach Estimated bridge faults required to reach adjacent metal
target coverage "coverage" limit
Coverage achievable Estimated adjacent metal covered by "faults" limit
at fault limit

USER RESPONSE:
ERROR (TDG-213): An error occurred during net pair extraction. No bridging fault model is
built. Processing ends.
EXPLANATION:
An error occurred during net pair extraction and as a consequence no bridging fault
model is built.
USER RESPONSE:
This error is accompanied by preceding messages that explain the problem. Resolve the
problems and rerun.
ERROR (TDG-214): An error occurred during fault rule generation. No bridging fault model
is built. Processing ends.
EXPLANATION:
An error occurred during fault rule generation and as a consequence no bridging fault
model is built.
USER RESPONSE:
This error is accompanied by preceding messages that explain the problem. Resolve the
problems and rerun.
INFO (TDG-215): Missed Block|Net and its Encounter Test model name
is correlation status reason if uncorrelated
EXPLANATION:
Informational message indicating the identified block or net contained in the Encounter
Testmodel, was not found in the physical design in the specified OpenAccess database.
This is indicative of a discrepancy between the logical and physical designs which may
have impacts on any Encounter Test processing that depends on logical-to-physical
correlation (e.g., building a bridge fault model). There are a number of underlying causes
for logical-to- physical mismatch including:
physical design flattening which modifies the names
missing layout for some modules
divergent logical and physical designs
Encounter Test names which were modified from the original Verilog names

USER RESPONSE:
logical-to-physical mismatches should be resolved. If the suspected reason for
mismatch is Encounter Test incorrectly mapping a name to the Verilog name space,
please contact Cadence Customer Support (see Contacting Customer Service on
page 23).
INFO (TDG-216): Minimum net spacing is being determined for setting of proximity.
EXPLANATION:
Informational message indicating the start of minimum net spacing determination. The
default for the proximity keyword is calculated as 1.5 times the minimum spacing
determined over a random sampling of nets.
USER RESPONSE:
No response is required. This message will be followed by TDG-217 indicating the
calculated value for proximity.
INFO (TDG-217): Minimum net spacing determined to be minimum_spacing5.3f

microns - setting proximity=proximity_setting5.3f microns. Time used CPU_time/
elapsed_time.
EXPLANATION:
Informational message indicating the completion of minimum net spacing determination
together with the calculated (default) value for the proximity keyword. This setting is
calculated to be 1.5 times the minimum spacing and will be used for extracting adjacent
net pairs.
USER RESPONSE:
No response is required unless the indicated proximity setting is undesirable. In that
case, the run should be terminated and a new run made with the desired setting for
proximity.
ERROR (TDG-218): Minimum net spacing could not be determined. Processing ends with
no bridge fault model built.
EXPLANATION:
Minimum spacing could not be determined for calculating the proximity keyword default
value. In order to determine minimum spacing, a sufficient sample of nets must correlate
to the OpenAccess database. In order for a net to correlate, it must be found in the
OpenAccess database and have associated routing information (shapes).

USER RESPONSE:
The report_physical_correlation command should be run to ensure sufficient
net correlation prior to running build_bridge_faultmodel. Refer to the
report_physical_correlation log to determine if a correlation problem exists, and
if so, take any necessary corrective action and then rerun
build_bridge_faultmodel. If no net correlation problem exists, contact Cadence
Customer Support (see Contacting Customer Service on page 23).
INFO (TDG-219): Build Bridge Fault Model limits: faults=faults_setting and

coverage=coverage_setting5.2f%%, whichever is reached first.
EXPLANATION:
Informational message indicating the limits in effect for this run. Based on the actual
number of net pairs extracted (subject to the proximity setting), these limits are
determined by faults and coverage respectively.
USER RESPONSE:
No response is required unless the indicated limits are undesirable. In that case, the run
should be terminated and a new run made with the desired settings for faults and
coverage.
INFO (TDG-220): Each extracted net pair will result in

number_of_bridge_faults_per_net_pair bridge faults based on the settings of
includestatic and includedynamic.
EXPLANATION:
Informational message indicating the number of bridge faults that will be generated for
each extracted net pair based on the settings of the indicated keywords. This number
will factor into the overall number of bridge faults generated and if the faults limit is in
effect, when this limit is reached.
USER RESPONSE:
No response is required unless the indicated settings are undesirable. In that case, the
run should be terminated and a new run made with the desired settings for includestatic
and includedynamic.
INFO (TDG-221): Bridge fault model limited to total_bridge_faults faults based on

the faults|coverage setting.
EXPLANATION:
Informational message indicating the total number of bridge faults that will be generated
based on the setting of the indicated keyword.

USER RESPONSE:
No response is required unless the resultant bridge fault model is undesirable. In that
case, build_bridge_faultmodel would be rerun with desired settings for faults and
coverage.
INFO (TDG-222): Build Bridge Fault Model ended after generating the specified
net_pair|fault_rule file. No bridge fault model is built.
EXPLANATION:
Informational message indicating Build Bridge Fault Model ended after having generated
either a net pair file or fault rule file as specified. When either of these files is generated,
the fault model is not built.
USER RESPONSE:
INFO (TDG-223): Initializing the lpds monitor.

EXPLANATION:
Informational message indicating the code version of the lpds monitor being initialized.
USER RESPONSE:
ERROR (TDG-224): Invalid command line specification: At least one of ALTFAULT,

netpairfile or faultrulefile must be specified. Processing ends.
EXPLANATION:
Build Bridge Fault Model requires that either ALTFAULT, netpairfile or
faultrulefile be specified in order to build a bridge fault model, a net pair file or fault
rule file respectively. None of these were specified in this invocation.
USER RESPONSE:
Specify ALTFAULT, netpairfile or faultrulefile and rerun.
INFO (TDG-225): The following minimum spacing layer constraints (in microns) will be used
in conjunction with a scaling factor of scaling_factor5.3f for net pair extraction.
table_of_minimum_spacing_constraints_by_layer
EXPLANATION:

Informational message indicating the minimum spacing constraints and scaling factor
that will be used for extracting adjacent net pairs.
USER RESPONSE:
ERROR (TDG-226): No layer spacing constraints were found in the OpenAccess database.
Processing ends with no bridge fault model built.
EXPLANATION:
Build Bridge Fault Model uses the minimum spacing constraints for each layer in the
design to set the distance limit for that layer. The minimum spacing is multiplied by a
scaling factor (1.5) to determine the largest separation at which two shapes are
considered proximate for the layer in question. Shapes that come closer than this
separation are considered to be adjacent. This message reports that no minimum
spacing constraints could be found for layers contained in the current OpenAccess
database. Hence a bridge fault model could not be built.
USER RESPONSE:
If a Cadence tools flow was used to produce this OpenAccess database, the minimum
spacing constraints at each layer should have been provided. The problem should be
reported to Cadence Customer Support for resolution. For OpenAccess databases
produced by customer- developed (or third-party) OA writers, the writer should be
updated to include a correct value for each layers' minimum spacing. The 'proximity'
keyword can be used to set one distance limit below which two shapes are considered
to be adjacent. The 'proximity' value is not scaled in any way. This proximity limit will be
used for all layers.
INFO (TDG-227): Fault distribution report:

Number of Faults Selected for Simulation : total_selected_faults
Number of Faults Selected on Clock Lines :

number_of_faults_on_clock_lines
(percentage_faults_on_clock_lines)
Number of Faults Selected on Scan Path :

number_of_faults_on_scan_path(percentage_of_faults_on_scan_pat
h)
Number of Faults Selected on Functional Path :

number_of_faults_on_functional_path
(percentage_of_faults_on_functional_path)

End of Fault distribution report. Time used CPU_time/elapsed_time.

EXPLANATION:
Informational message indicating the fault distribution report on selected faults.
USER RESPONSE:
ERROR (TDG-228): Fault list file file_name does not exist.

EXPLANATION:
The file that was specified for use as the fault list does not exist. Processing ends.
USER RESPONSE:
Verify that the file name is correct.
ERROR (TDG-229): Fault list file file_name is unreadable.

EXPLANATION:
The file that was specified for use as the fault list is not readable. Processing ends.
USER RESPONSE:
Verify that the file permissions allow you to have read authority.
INFO (TDG-230): Conclusion from cell correlation percentage (percentage of

correlation5.2f): Conclusion
EXPLANATION:
The message tells the extent of correlation of blocks between netlist and OA data base.
Processing ends.
USER RESPONSE:
If a high correlation percentage is required, rerun report_physical_correlation
cellcorrelationreport=uncorrelated to see the reason why a particular net
remained uncorrelated.
INFO (TDG-231): Conclusion from net correlation percentage (percentage of

correlation5.2f): Conclusion
EXPLANATION:

The message tells the extent of correlation of nets between netlist and OA data base.$
Processing ends.
USER RESPONSE:
If a high correlation percentage is required, rerun report_physical_correlation
netcorrelationreport=uncorrelated to see the reason why a particular net
remained uncorrelated.
INFO (TDG-232): Table of coverage contribution of net pairs in the decreasing order of their
parallel run lengths (in microns).Table
EXPLANATION:
The message contains the characteristics of net pairs and their percentage contribution
to total coverage. The netpairs are grouped on basis of decreasing parallel run length
therefore groups are made on priority basis i.e. the first group has net pairs with
maximum average parallel run length. It also acts as a correlation table which can be
used to calculate how many net pairs will be used to form bridge faults for a given
coverage setting.
USER RESPONSE:
If the number of bridge faults modeled is acceptable, no response is required. Otherwise,
re-run with an alternate setting for the coverage or faults keyword.
INFO (TDG-233): Fault Index = V indicates that the fault identifier is associated with a virtual
fault model used only by callout post processing. See the callout description for associated
fault indexes.
EXPLANATION:
Informational message identifying the fault model used during callout print.
USER RESPONSE:
INFO (TDG-234): Fault Machine = compound fault identifier.

EXPLANATION:
Informational message identifying compound faults used during simulation.
USER RESPONSE:

INFO (TDG-235): Scan interleaving was not performed - there are no scan events in the
generated test sequence.
EXPLANATION:
The option to perform scan interleaving was selected, however the generated pattern
contains no scan events (Scan_Load, Skewed_Scan_Load), on which to perform scan
interleaving. Instead, the transition was most likely generated by switching Primary
Inputs. This would be the case if the fault site is fed by Primary Inputs and not by
controllable scan chains.
USER RESPONSE:
INFO (TDG-236): Parsing Invariant Analysis file file_name.

EXPLANATION:
Informational message identifying ASCII Boolean expression file being parsed for
Invariant Analysis.
USER RESPONSE:
INFO (TDG-237): The following expressions were parsed for Invariant Analysis:
EXPLANATION:
Informational message identifying Boolean expressions parsed for Invariant Analysis.
USER RESPONSE:
ERROR (TDG-238): A syntax error was detected when parsing the following token on line
line_number. Processing ends.
EXPLANATION:
A syntax error was detected during parsing of the Boolean expressions specified for
Invariant Analysis. Processing ends.
USER RESPONSE:
The name of the file being parsed should appear in a previous message. Identify and
correct the syntax error on the indicated line, save the file and rerun.

Refer to "Boolean Expression File" in the Encounter Test: Guide 7: Diagnostics for
ERROR (TDG-239): Unable to open Invariant Analysis file file_name. Processing ends.
EXPLANATION:
The ASCII Boolean expression file specified for Invariant Analysis could not be opened.
Processing ends.
USER RESPONSE:
If the specified file name is incorrect, correct and rerun. Otherwise, check if the file
permissions allow read access to the file. If not, modify the permissions and rerun.
ERROR (TDG-240): Unable to resolve name block|pin|net name in statement

statement_number, line line_number. Processing ends.
EXPLANATION:
The indicated name could not be found in the Encounter Test logic model. Processing
ends.
USER RESPONSE:
Correct the indicated name in the Invariant Analysis file (the file name should appear in
a previous message), and rerun.
ERROR (TDG-241): Block block_name in statement statement_number, line

line_number is ambiguous because it has multiple outputs. Processing ends.
EXPLANATION:
The indicated block cannot be resolved to a single node because it has multiple outputs.
Processing ends.
USER RESPONSE:
Change the indicated block name in the Invariant Analysis file (the file name should
appear in a previous message), and rerun. This should most likely be changed to one of
the output pins of the block.
INFO (TDG-242): Physical diagnostics server successfully started on

physical_server_host_name. You can now invoke diagnostic commands with below
specification to perform physically-aware diagnostics.
physicalserverhost=physical_server_host_address
physicalserverport=physical_server_port
Once physically aware diagnostics is complete, you can stop the physical diagnostics server

using command invocation stop_physical_server

physicalserverhost=physical_server_host_address
physicalserverport=physical_server_port
EXPLANATION:
Informational message indicating the details of server port and host names and
command line specifications for enabling physical diagnostics and stopping the physical
server.
USER RESPONSE:
For starting diagnostics jobs in physical aware diagnostics mode, use the specification
provided in this message. The command line invocation for stopping the physical server
is also provided in this message. You can save this invocation and invoke this command
after completing physical diagnostics.
INFO (TDG-245): Start of Merge Sequence report:

EXPLANATION:
Informational message stating that the merge sequence diagnostic callout analysis
report has started.
USER RESPONSE:
INFO (TDG-246): End of Merge Sequence report. Time used CPU_time/

elapsed_time
EXPLANATION:
Informational message stating that the merge sequence diagnostic callout analysis
report has completed in the listed time.
USER RESPONSE:
ERROR (TDG-250): Statement statement_number on line line_number contains a

value_type value and a preceding statement contains a value_type value.
Combinations of these statements are not permitted in Invariant Analysis files. Processing
ends.
EXPLANATION:

This terminating message identifies a statement inconsistency in the Invariant Analysis

Boolean expression file. Statements containing transition values and statements
containing static values may not be specified in the same file.
USER RESPONSE:
Correct the inconsistency in the Invariant Analysis file (the file name is referenced in a
previous message), and rerun.

INFO (TDG-254): Initializing the simulator Simulator.
EXPLANATION:
No further explanation is necessary.
USER RESPONSE:
INFO (TDG-255): Simulator initialization completed successfully. Time used CPU_time/

elapsed_time.
EXPLANATION:
No further explanation is necessary.
USER RESPONSE:
ERROR (TDG-256): Simulator initialization failed. See preceding messages.

EXPLANATION:
The simulator failed to initialize.
USER RESPONSE:
Refer to preceding messages for an appropriate response. :
ERROR(TDG-258) There were no test sequences detected for simulation. See preceding
messages.
EXPLANATION:

Terminating message indicating there are no test sequences for simulation. This can
occur for any or all of the following reasons:
testtrange specified in the form: fail,<odometer range> and there
are no failing test sequences in the specified odometer range. Note that the
device specification will also determine failure data selection, and consequently
the set of failing test sequences.
append=yes was specified and the specified testrange identified only
previously simulated test sequences
USER RESPONSE:
Examine the testrange, device and append specifications and make necessary
corrections.
INFO (TDG-259): A total of number_of_test_sequences test sequences will be

simulated as follows:
Passing number_of_passing_test_sequences
Failing number_of_failing_test_sequences
Total total_number_of_test_sequences
EXPLANATION:
This is an informational message indicating the total number of test sequences to be
simulated in this invocation. This message is immediately followed by a table explaining
the breakdown of test sequences according to whether they are passing or failing.
USER RESPONSE:
INFO (TDG-260): The program has started processing the

layout_abstraction_type data from source_name.
EXPLANATION:
Informational message stating that the specified layout abstraction data is processed by
the program.
USER RESPONSE:

WARNING (TDG-261): Writing new layout abstraction data into file

layout_abstraction_file, but the file already exists. The file will be overwritten.
EXPLANATION:
While writing layout abstraction data to the indicated file, it was detected that the file
already exists. The existing file will be replaced with the contents of the new file.
USER RESPONSE:
INFO (TDG-262): The layout abstraction binary file layout_abstraction_file is

created with number_of_groups layout_abstraction_type groups. Processing
ends.
EXPLANATION:
Informational message stating that the specified layout abstraction binary file is created
by the program.
USER RESPONSE:
INFO (TDG-263): The layout abstraction binary file layout_abstraction_file is

successfully deleted.
EXPLANATION:
Informational message stating that the specified layout abstraction binary file is
successfully deleted by the program.
USER RESPONSE:
ERROR (TDG-264): The layout abstraction binary file layout_abstraction_file

does not exist.
EXPLANATION:
The request to delete the specified file could not be performed since the file does not
exist.
USER RESPONSE:
Investigate the above condition to determine what, if any, corrective action can be taken.
WARNING (TDG-265): The objects name name is not present in Encounter Test Model.

EXPLANATION:
The specified object name is not present in Encounter Test Model and hence the layout
abstraction data associated with it could not be added to the binary file.
USER RESPONSE:
Investigate the reported name, identify the source of the problem and update the layout
abstraction file with a name present in Encounter Test Model and rerun the command.
WARNING (TDG-266): The object object_name is contained within the technology

cell boundary.
EXPLANATION:
The specified object is present within the technology cell boundary.
USER RESPONSE:
None.
WARNING (TDG-267): The pin pin_name is not a receiver pin.

EXPLANATION:
The specified pin is not a receiver pin and therefore could not be added to the subnet
group.
USER RESPONSE:
None.
WARNING (TDG-268): Subnet group associated with driver pin pin_name is ignored since
the group contains less than 2 receivers.
EXPLANATION:
The specified pin is not a receiver pin and therefore could not be added to the subnet
group.
USER RESPONSE:
None.
WARNING (TDG-269): abstraction_type for the object_type:name could not be

created.
EXPLANATION:

This message indicates that the sub-group elements for the specified layout abstraction
type are not present or the specified elements are not present in Encounter Test
database.
USER RESPONSE:
Investigate the reported name, identify the source of the problem and update the layout
abstraction file accordingly and rerun the command.
INFO (TDG-270): Start of Explain Failure Report: Time used CPU_time/

elapsed_time.
EXPLANATION:
Informational message stating that the diagnostic explain failure data is about to be
printed in the indicated format. The format is determined by the specified option for the
reportfail keyword.
USER RESPONSE:
INFO (TDG-271): End of Explain Failure Report. Time used CPU_time/elapsed_time

EXPLANATION:
Informational message stating that the diagnostic explain failure data has finished
printing in the listed time.
USER RESPONSE:
INFO (TDG-272): A total of count of total_sequence_count of the specified test

sequences will not be simulated because they were previously simulated.
EXPLANATION:
When appending to or restarting from existing callout data, test sequences previously
simulated to produce the callout will not be subsequently simulated as this would
invalidate the callout. This message indicates the total number of test sequences in the
specified testrange that fall into this category.
USER RESPONSE:
ERROR (TDG-273): Diagnostic fault selection resulted in no faults being selected for
simulation. Processing ends.

EXPLANATION:
This condition usually occurs when only passing test sequences are selected using the
testrange keyword and a fault subset was requested using the faultset keyword
(for example, faultset= union). Fault selection is dependent on failing test
sequences that identify failing measure locations used as back-trace starting points.
USER RESPONSE:
Modify testrange and/or faultset.
ERROR (TDG-274): Diagnostic fault selection exceeded the limit of number of faults
faults. Processing ends.
EXPLANATION:
This condition occurs when a fault limit has been specified for Diagnostics Simulation
using faultlimit, and the number of collapsed faults selected for simulation exceeds
the limit. The number of selected collapsed faults can be influenced by the failing test
sequences selected (that is, device and testrange specifications), and the requested fault
subset (for example,
faultset=union).
USER RESPONSE:
Modify device, testrange, faultset, or faultlimit accordingly.
ERROR (TDG-275): appending_application cannot be used to append callout

callout_name which was produced by calout_producing_application.
EXPLANATION:
An existing callout can only be appended by the application used to create it. In this case,
an attempt was made to append to an existing callout using an alternate application.
USER RESPONSE:
If appending is desired, select the appropriate application. Otherwise, disable the
append option.
INFO (TDG-276): Start of the Boolean Expression true Test Sequence Report:
EXPLANATION:
Informational message indicating the beginning of the Invariant Analysis report which
lists the test sequences (by odometer value), which were detected as true for each
specified Boolean expression.
USER RESPONSE:

INFO (TDG-277): End of the Boolean Expression true Test Sequence Report.
EXPLANATION:
Informational message indicating the beginning of the Invariant Analysis report which
lists the test sequences (by odometer value), which were detected as true for each
specified Boolean expression.
USER RESPONSE:
ERROR (TDG-278): A Boolean expression containing an * (asterisk) character was

detected. This is not permitted when running with listtruesequences=yes.
EXPLANATION:
When Invariant Analysis is run with listtruesequences=yes, only specific Boolean
expressions may be specified, that is, no expressions containing *, which is short-hand
for specifying all nodes).
USER RESPONSE:
Correct the discrepancy and rerun.
WARNING (TDG-279): Simulation will not proceed beyond Test Sequence

experiment_odometer_value.test_section_odometer_value.tester_loo
p_odometer_value.test_procedure_odometer_value.test_sequence_odo
meter_value due to the failcollected=failcollected_value specification.
EXPLANATION:
The failcollected setting indicates the Test Sequence range over which failure data
was collected at the tester. In this case, the failcollected setting truncated the
specified Test Sequences to be simulated. Test Sequences are not simulated unless they
fall within the range defined by the failcollected setting.
USER RESPONSE:
No response is required unless simulation beyond the specified Test Sequence is
desired. To simulate beyond the specified Test Sequence, rerun with
failcollected=all specified.
ERROR (TDG-280): Diagnostic Simulation dropped all faults. Processing ends.

EXPLANATION:

This condition occurs when all faults selected for simulation are dropped. A dropped fault
summary will accompany this message, providing details on why the faults were dropped
and the associated controls.
USER RESPONSE:
No response is required, unless the fault dropping is undesirable. In this case, Refer to
the dropped fault summary, modify the appropriate control, and rerun.
ERROR (TDG-281): A Boolean expression containing a transition value (T01 or T10) was
detected. This is not permitted when running with listtruesequences=no.
EXPLANATION:
When Invariant Analysis is run with -listtruesequences no, Boolean expressions
containing transition values may not be specified (that is, no expressions containing
values T01 or T10).
USER RESPONSE:
Correct the discrepancy and rerun.
ERROR (TDG-298): The checkpoint specification and argument are mutually

exclusive.
EXPLANATION:
A checkpoint interval was specified in conjunction with the indicated argument. The use
of this argument with the checkpoint keyword is not supported.
USER RESPONSE:
Rerun with non-conflicting arguments.
INFO (TDG-299): Diagnostic Simulation ignoring checkpoint checkpoint_details

EXPLANATION:
There was a checkpoint record left from a previous run. It is being ignored as the starting
point for this run due to the restart command specification.
USER RESPONSE:
INFO (TDG-300): Diagnostic Simulation restarting from checkpoint_details

EXPLANATION:

There was a checkpoint record left from a previous run. It is to used as the starting point
for this run.
USER RESPONSE:

INFO (TDG-301): Diagnostic Simulation taking checkpoint checkpoint_details
EXPLANATION:
Informational message telling that a check point has been taken.
USER RESPONSE:
ERROR (TDG-302): Diagnostic Simulation failed restart from checkpoint.

EXPLANATION:
The program is attempting to honor the restart from checkpoint request, but the
diagnostic callout data is not in a checkpoint state.
USER RESPONSE:
Remove restart=yes from the command line.

EXPLANATION:
Informational message indicating the start of the callout report. The following legend
applies to the callout report:
Fault Index = D indicates that the fault identifier is associated with the hierarchical
fault model used only by diagnose_failset_logic_cell.
Score = (TFSF / (TFSF + TFSP + TPSF/10) ) * 100
TFSP = How many pins/latches that failed at the tester, passed(did not fail) in
simulation.
TPSF = How many pins/latches that passed (did not fail) at the tester, failed in
simulation.

First Contributing Sequence = The first Test Sequence that failed while simulating
the specified fault, and also failed at the tester.
First Conflicting Sequence = The first Test Sequence that failed while simulating the
specified fault, and did not fail at the tester.
USER RESPONSE:
INFO (TDG-304): End of Callout Report. Time used CPU_time/elapsed_time

EXPLANATION:
Informational message stating that the diagnostic callout data has finished being printed
in the listed time.
USER RESPONSE:
INFO (TDG-305): Deleting callout_file_name

EXPLANATION:
Informational message telling that the callout file is being deleted together with the
registered dependencies for checkpoint/restart.
USER RESPONSE:
INFO (TDG-306): Callout callout_name already exists, but will be overwritten.

EXPLANATION:
The indicated callout already exists for the current experiment (if any) and failset. The
callout produced by this invocation will overwrite existing data. The indicated name (if
any), reflects the setting of the ALTCALLOUT keyword.
USER RESPONSE:
ERROR (TDG-310): The input vectors file is back-level. Run TBDmigrate with the -w flag
to create an experiment at the current release level in order to perform Diagnostics
Simulation.
EXPLANATION:

The vectors file was produced prior to Encounter Test 1.0.

USER RESPONSE:
Run the program with the -w flag to create an experiment at the current release level.
WARNING (TDG-311): Missing physical information in Open Access database.

EXPLANATION:
The message is self explanatory.
USER RESPONSE:
Re-build the Open Access database by adding appropriate information.
ERROR (TDG-313): The server/client failed to socket_problem. The system

message is system_error_message.
EXPLANATION:
The server/client failed to initialize socket over network for server-client communication.
The error message indicates the nature of socket connection problem and its error
message generated from system.
USER RESPONSE:
Analyze the system error message to rectify the root problem. Some of the common root
cause problems are:
No network connection.
Server or client died/killed before closing connection.
Server Port is already used by other program.
ERROR (TDG-314): The source and target failsets cannot be the same.
EXPLANATION:
The failset filter application does not allow the source and target failset names to be the
same.
USER RESPONSE:
Respecify either failset and rerun.
WARNING (TDG-315): The socket failed to send/receive data packet. The system
message is system_error_message. The program will retry in one second.

EXPLANATION:
The program failed to send/receive a data packet through connected socket.
USER RESPONSE:
Analyze the system error message to rectify the root problem. Some of the common root
cause problems are:
No network connection.
Server or client died/killed before closing connection.
Receiver is not ready to receive data packet because of slow system
processing at receiver end.
INFO (TDG-316): Failset failset already exists. The file will be overwritten.
EXPLANATION:
The target failset failset already exists. The new failset produced from this invocation
will overwrite the existing data.
USER RESPONSE:
ERROR (TDG-317): Failset failset_name could not be created. See preceding

messages for reasons for further information about the failure.
EXPLANATION:
An error was encountered preventing the target failset from being created.
USER RESPONSE:
See preceding messages, take appropriate action, and then rerun.
ERROR (TDG-318): The explain failures file file_name could not be found.
EXPLANATION:
The explain failures file could not be found. This file must be available to provide
information for prepare_filtered_failset.
USER RESPONSE:
Run the appropriate application with the appropriate keywords to create the file. Refer to
Precision Diagnostics in the Encounter Test: Guide 7: Diagnostics for additional
information.

ERROR (TDG-320): The version number in the explain failure file -- file_name is not
current. Recreate the data with the current level of code.
EXPLANATION:
The indicated explain failure file does not have a version number that the current level of
Encounter Test expects.
USER RESPONSE:
Generate new explain failure data using the current level of code.
INFO (TDG-321): The append option was specified but an explain failure file does not exist.
A new file will be created.
EXPLANATION:
Use of the append option presumes the existence of an explain failure file. This file could
not be found. A new file will be created for the new data.
USER RESPONSE:
INFO (TDG-322): The explain failure data will not be printed. See previous message(s) for
probable reasons.
EXPLANATION:
A programming call was made to have the explain failure data printed but that is not
possible due to reasons noted in messages appearing in the output before this one.
USER RESPONSE:
Resolve the problems noted by previous explain failures-related messages and retry the
scenario that just attempted the printing situation.
ERROR (TDG-323): Unable to open Explain Failure file.

EXPLANATION:
An attempt to open the specified Explain Failure file was unsuccessful.
USER RESPONSE:
ERROR (TDG-324): Unable to verify Explain Failure registration.

EXPLANATION:

The specified Explain Failure data is found to be unregistered. As a consequence, the

Explain Failure data is not expected to exist.
USER RESPONSE:
WARNING (TDG-325): The input fault(s) did not contribute to any failures. The output failset
written is the same as the input.
EXPLANATION:
The fault information provided as input was found not to contribute to any failures in the
specified input failset. The output failset was created but it is the same as the input.
USER RESPONSE:
INFO (TDG-328): Start of Failure Distribution Report:

EXPLANATION: Informational message indicating the start of the failure distribution
information for $ scan chain defect(s).
USER RESPONSE:
None.
End of Failure Distribution Report.
ERROR (TDG-330): Attempt to open the callout data has failed. Refer to previous messages
for more specific information.
EXPLANATION:
An attempt to open and initialize the callout data failed. Messages output prior to this one
should provide more information.
USER RESPONSE:
Review previous messages and take appropriate action to rectify the problem.
WARNING (TDG-331): [Severe] program: Encountered problems closing the failset.

EXPLANATION:
A problem occurred when attempting to close the specified data. Prior messages should
indicate the nature of the problem.
USER RESPONSE:

Review the previous messages and correct the problem.
WARNING (TDG-332): Input fault index input_fault_index is greater than the

maximum fault index of maximum_fault_index for which explain failure data exists. This
input fault will be ignored.
EXPLANATION:
The specified input fault index is greater than the largest fault index that had explain
failure data recorded.
USER RESPONSE:
Recheck and correct the input fault index.
INFO (TDG-333): Explain failure data was requested to be collected however this simulation
did not produce any data. For this reason, no explainfailBin file will be written.
EXPLANATION:
Even though explain failure data was requested, the simulation did not produce any
data. As a result, an explainfailBin file will not be written.
USER RESPONSE:
INFO (TDG-334): No explain failure data was produced by this simulation.

EXPLANATION:
Even though explain failure data was requested, the simulation did not produce any
data. As a result, an explainfailBin file was will not be written
USER RESPONSE:
WARNING (TDG-335): The input fault(s) contributed to all the failures, so there is no failure
data to write to a new failset. Therefore, a new output failset is not being produced.
EXPLANATION:
The fault information provided as input was found to contribute to all failures in the
specified input failset. This results in no failure data being available to produce a new
failset with. Therefore, a new output failset was not created.
USER RESPONSE:

INFO (TDG-336): A report_name report was requested, however no Fault Explains

Failures data was collected for the specified callout. The report cannot be generated.
EXPLANATION:
The indicated report was requested but not produced because no Fault Explains Failures
data was collected when the callout was generated.
USER RESPONSE:
Either remove the option to generate the indicated report or regenerate the callout,
specifying Fault Explains Failures data be collected, then generate the report.
INFO (TDG-337): The output failset is not created.

EXPLANATION:
All the devices in the failset are deleted. A probable cause can be a large value specified
for lowpatterncountdefectmargin keyword.
USER RESPONSE:
WARNING (TDG-338): The pin pin_name is not a driver pin.

EXPLANATION:
The specified pin is not a driver pin and therefore a subnet group could not be created
for this pin.
USER RESPONSE:
WARNING (TDG-339): A subnet group associated with driver pin : pin_name is ignored
since it contains less than 2 valid receivers.
EXPLANATION:
A subnet group should contain at least two valid receivers. The subnet group associated
with above reported pin contains less than two valid receivers.
USER RESPONSE:
WARNING (TDG-340): No valid group_name groups are identified.

EXPLANATION:

All the specified netpair groups or subnet groups are invalid.

USER RESPONSE:
Investigate the above condition to determine if any corrective action can needs to be
taken.
ERROR (TDG-341): The specified group_name file has errors and hence the binary layout
abstraction file is not generated. Refer to the above messages for detailed information.
EXPLANATION:
The input file for subnet or net pairs has errors and hence the binary layout abstraction
file could not be generated.
USER RESPONSE:
Investigate the above condition to determine if any corrective action needs to be taken.
WARNING (TDG-342): No group_name group entry found for

net_or_pin:net_name_or_pin_name.
EXPLANATION:
No entry present for subnet or netpair in the tbdata for the given net or pin name.
USER RESPONSE:
Investigate the above condition to determine if any corrective action needs to be taken.
INFO (TDG-343): Report of group_name for the net_or_pin specified in

layout_abstraction_file file.
EXPLANATION:
Processing of netpair or subnet file starts.
USER RESPONSE:
WARNING (TDG-344): Invalid net_or_pin:net_name_or_pin_name. No

group_name will be identified for this net2_or_pin2.
EXPLANATION:
Specified net or pin name is not present in Encounter test model and thus processing
skips for given net or pin
USER RESPONSE:

INFO (TDG-348): Diagnostc fault selection complete. Time used CPU_time/

elapsed_time.
EXPLANATION:
Informational message indicating the completion of fault selection, and the associated
CPU and elapsed time used for fault selection.
USER RESPONSE:
INFO (TDG-349): The keyword reportexplainfail is not supported for a testmode with
XOR compression structures inserted.
EXPLANATION:
The request is unsupported for a testmode with XOR compression structures inserted.
USER RESPONSE:
None.
INFO (TDG-350): Start of SLAT | Bridge Analysis Report:

EXPLANATION:
This Informational message states that the diagnostic analysis report is about to be
printed.
USER RESPONSE:

INFO (TDG-351): End of SLAT | Bridge Analysis Report. Time used CPU_time/
elapsed_time
EXPLANATION:
IThis Informational message states that the diagnostic analysis report has finished being
printed for the listed duration.
USER RESPONSE:

INFO (TDG-352): Starting diagnostic fault selection.

EXPLANATION:
IThis Informational message indicates the start of diagnostic fault selection.
USER RESPONSE:
INFO (TDG-353): The union of all faults encountered will be selected.

EXPLANATION:
Informational message indicating that the union of all faults encountered will be selected
in response to the faultset=union specification.
USER RESPONSE:
ERROR (TDG-354): No Fault Explains Failures data was collected for the specified callout.
Program terminates.
EXPLANATION:
This program needs Fault explains Failures data to perform SLAT analysis. This data can
be collected by specifying reportbridges=yes or reportslat=yes or
explainfails=slat to the diagnose_failset_logic run. The current callout
does not contain Fault Explains Failures data and hence the program terminates.
USER RESPONSE:
Regenerate the callout using one of the above specifications and rerun this command on
the new callout.
INFO (TDG-355): The intersection of all faults encountered will be selected.

EXPLANATION:
Informational message indicating that the intersection of all faults encountered will be
selected in response to the faultset=intersection specification.
USER RESPONSE:

INFO (TDG-356): Device device_name contains failures from splat_patterns slat

patterns is identified as suspected splat partition. The specified value for
lowpatterncountdefectmargin requires failures from atleast
min_splat_patterns slat patterns in every partition.
EXPLANATION:
This is an informational message indicating that suspected splat has been identified by
the program.
USER RESPONSE:
INFO (TDG-357): Scan path faults will | will_not be selected.

EXPLANATION:
This is an informational message indicating whether faults on scan paths will be selected
for logic diagnostics as a result of the scanpathfaults setting.
USER RESPONSE:
None.
INFO (TDG-358): Clock lines to latches will not be followed.

EXPLANATION:
Informational message indicating that clock lines will not be considered in response to
the clockfaults=excludeall specification.
USER RESPONSE:
INFO (TDG-359): Clock lines to latches will be followed only for the clock stuck off.
EXPLANATION:
the clockfaults=excludeclockon specification.
USER RESPONSE:
INFO (TDG-360): Clock lines to latches will be followed in addition to the data lines.
EXPLANATION:

the clockfaults=include specification.
USER RESPONSE:
WARNING (TDG-361): The limit of clusters to be searched for is maxnumclusters.This

limit has been reached and cluster analysis will not continue for device device_name which
has cluster_count clusters.
EXPLANATION:
The limit of clusters to be searched for has been reached. Program output is truncated.
USER RESPONSE:
Set the maxnumclusters keyword to a value that is greater than or equal to the number
of clusters associated with the specified device, and rerun.
WARNING (TDG-362): The limit of failure backcones for which a cluster search will be done
is maxnumcones. This limit has been reached. Cluster analysis will not be performed for
device device_name which has cone_count backcones.
EXPLANATION:
The limit of failure backcones for which a cluster search will be performed on any device
has been reached.
USER RESPONSE:
Set the maxnumcones keyword to a value that is greater than or equal to the number of
backcones associated with the specified device, and rerun.
INFO (TDG-363): Cluster analysis will not be performed on device device_name.

EXPLANATION:
Cluster analysis is not required for the specified device because there is only a single
backcone of logic indicated by the failure data.
USER RESPONSE:
INFO (TDG-364): Handle device device name.

EXPLANATION:
Informational message indicating the device that is currently being processed.

USER RESPONSE:
INFO (TDG-365): Selected number_of_faults of number_of_possible_faults

possible faults as follows:
EXPLANATION:
Informational message indicating the number of faults selected out of the total number of
possible faults.The total number of possible faults is based on the number of faults in the
Encounter Test fault model of the appropriate type(s), as specified by the faulttype
keyword.
The number of selected faults is based on the combination of the faultstatus,
faultset, clockfaults, and testrange keywords. This message is immediately
followed by a table explaining the breakdown of selected faults in terms of type and
status.
USER RESPONSE:
INFO (TDG-366): Net Pair and Bridge Fault statistics:

Statistics of number of net pairs and bridge faults that will be modeled based on coverage
and faults constraints
EXPLANATION:
Informational message indicating the number of net pairs extracted and the number of
bridge faults to be modeled under any constraints in affect coverage or faults
settings)
USER RESPONSE:
If the number of bridge faults modeled is acceptable, no response is required. Otherwise,
re-run with an alternate setting for the coverage or faults keyword.
INFO (TDG-367): Time spent on merging: time in seconds seconds.

EXPLANATION:
Information only message.
USER RESPONSE:

ERROR (TDG-369): Failures from logic tests are not present in the FAILSET. Failures from
logic tests are required to determine failing flop locations. Processing Ends.
EXPLANATION:
Scan Chain Diagnostics requires failures from logic tests to determine the failing flop
locations. In this case, no failures from logic tests are available in the FAILSET. Hence,
the processing ends without proceeding to the diagnostic simulation to determine the
failing flop locations.
USER RESPONSE:
Rerun the command with the FAILSET created from failures obtained from application of
logic tests.
INFO (TDG-370): prepare_failset_partition ended.

EXPLANATION:
Informational message stating the name of the failset created by
prepare_failset_partition. .
USER RESPONSE:
INFO (TDG-371): The output failset name is output failset name.

EXPLANATION:
Informational message indicating the name of the FAILSET created by
prepare_failset_partition.
USER RESPONSE:
INFO (TDG-374): Starting prepare_failset_partition version

EXPLANATION:
Information only message.
USER RESPONSE:
INFO (TDG-375): number of fails failures were added to device device_name.

EXPLANATION:

This Informational message indicates the number of failures that were associated with
the specified device by prepare_failset_partition.
USER RESPONSE:
WARNING (TDG-377): Device device name has no cones.

EXPLANATION:
This device has no cones.
USER RESPONSE
INFO (TDG-378): Device: device name, Cones number of cones, clusters number
of clusters.
EXPLANATION:
The numbers of cones and clusters is listed for each device.
USER RESPONSE:
WARNING (TDG-379): Best test sequence identification ends here after identifying
num_best_test_sequences_identified best test sequences out of
num_total_sequences_simulated test sequences because the remaining
sequences do not met the mincoverageincrease=minimum_coverage_increase
condition criteria.
EXPLANATION:
The last test sequence considered for best test sequence identification does not meet
the minimum coverage increase (mincoverageincrease) criteria. Hence, the
program did not consider the remaining test sequences. All the best test sequences
identified after excluding the last failed simulated test sequence will be reported in final
summary report.
USER RESPONSE:
Decrease the mincoverageincrease value to allow further best test sequences to be
identified.
WARNING (TDG-380): Best test sequence identification ends here after identifying

num_total_sequences_simulated test sequences because all the best test

sequences identified meet the
maxscandiagcoverage=maximum_scan_diagnostics_coverage condition
criteria.
EXPLANATION:
All the best test sequences identified meet the maximum (maxscandiagcoverage)
criteria. The remaining test sequences are not considered as the program has achieved
the maximum scan coverage with the already identified best test sequences.
USER RESPONSE:
Increase the maxscandiagcoverage value to allow further best test sequences to be
identified.
INFO (TDG-381): Best test sequence identification ends here after identifying
num_total_sequences_simulated test sequences because the number of best test
sequences identified matches the
numbestpatterns=numbestpatterns_value_specified specification.
EXPLANATION:
analyze_chain_diagnosability have identified all required best test sequence(s)
from given test range specification. The remaining test sequences are not considered as
number of best test sequences identified matches the specified numbestpatterns
keyword.
USER RESPONSE:
Increase the numbestpatterns value to allow further best test sequences to be
identified.
WARNING (TDG-382): The number of test sequences selected for simulation is less than
the numbestpatterns=numbestpatterns_value_specified keyword. The
number of best test sequences cannot be more than the number of test sequences selected
for simulation.
EXPLANATION:
The number of test sequences selected for simulation is less than the value specified to
numbestpatterns keyword. The number of best test sequences cannot be more than
the number of test sequences selected for simulation.
USER RESPONSE:

If you wish to generate the specified number of best sequences, rerun the command by
specifying more sequences using testrange keyword. To avoid this warning message
in subsequent runs, specify a smaller value to numbestpatterns keyword or specify
numbestpatterns=all. In this case, the run continues and it will identify the best
sequences from the list of sequences simulated in this run.
INFO (TDG-383): Best test sequence identification ends here after identifying
num_total_sequences_simulated test sequences because the remaining test
sequences do not report any known value on any of the flops during simulation.
EXPLANATION:
The remaining test sequences do not report any 0 or 1 known value(s) on any flop. Thus,
they are not considered for best test sequence identification. Best test sequence
identification ends here.
USER RESPONSE:
None.
WARNING (TDG-384): Could not open the results file file_name. Error is
system_error_message.
EXPLANATION
Attempt to open the summary results file for prepare_failset_partition failed.
This is accompanied by the message received from the Operating System.
USER RESPONSE:
Examine the accompanying system message and take the appropriate action.
INFO (TDG-385): Report of sequences simulated for device device_name:

EXPLANATION:
Informational message indicating the start of the sequence report selected for
simulation.
USER RESPONSE:
None.
INFO (TDG-387): Special SLAT intersection will be used.

EXPLANATION:
Diagnostic Fault Selection will use a special combination of intersections and unions.

USER RESPONSE:
INFO (TDG-391): Physical Trends in the Set of Nets. Trends in Physical

Layout
EXPLANATION:
The message is self explanatory
USER RESPONSE:
None
INFO (TDG-392): The upper bound for testmode testmode_name identified by dictionary
look-up is upperbound.
EXPLANATION:
For the specified bestguess and testmode, the scan chain diagnostics dictionary has
identified the reported upperbound.
USER RESPONSE:
None.
ERROR (TDG-397): The device device_name contains duplicate failures and hence the
callout results for this device are suspect.
EXPLANATION:
Whenever there are duplicate failures for a device, diagnostics scoring for the faults
simulated will not be accurate and hence the callout results are also not accurate.
USER RESPONSE:
Reimport the failures for the specified device by eliminating the duplicate failures and
rerun this command.
INFO (TDG-399): Found a loop between nodes: First nodeand: Second Node
EXPLANATION:
The program detected a potential combinational loop when attempting to find logical
connections between two nodes in a split.
USER RESPONSE:
Check the device logic.

WARNING (TDG-400): Bridge analysis cannot be performed on callouts produced by the

Hierarchical Fault Simulator.
EXPLANATION:
The specified callout analysis can only be performed on callouts that use the Encounter
Test fault model, as supported by the General Purpose simulator or the High Speed Scan
Based simulator. The current callout was produced using a simulator other than the gp
or hsscan simulator.
USER RESPONSE:
Rerun Diagnostics Simulation with simulation=gp or simulation=hsscan
specified.

INFO (TDG-401): Start of Confidence Report:
EXPLANATION:
Informational message stating that the diagnostic confidence is about to be printed.
USER RESPONSE:
ERROR(TDG-403) The selected analysis cannot be performed on callouts produced by the

Hierarchical Fault Simulator.
EXPLANATION:
A keyword of stuckatx, slowfaults, multfaults, oredpatterns,
mergesequence, or reportsequence was specified, requesting special callout
analysis. The special callout analysis can only be performed on callouts that use the
Encounter Test fault model, as supported by the General Purpose simulator or the High
Speed Scan Based simulator. The current callout was produced using a simulator other
than the gp or hsscan simulator.
USER RESPONSE:
Rerun Diagnostics Simulation with simulation=gp or simulation=hsscan
specified.
ERROR (TDG-404): Callout analysis to post_analysis_routine was not successful.

EXPLANATION:

An attempt was made to post-process the existing callout data to perform the post
analysis function specified. The program which performs this analysis identified a
condition which prevents it from getting valid results.
USER RESPONSE:
Check for previous messages to determine why the analysis was not successful. It may
be necessary to rerun Diagnostics Simulation with different keywords to gather more
information about the modeled faults before further analysis is productive.
INFO (TDG-405): Multiple Fault Analysis will consider sets of up to number_of_faults

faults.
EXPLANATION:
The Multiple Fault Analysis routine will attempt to find sets of faults which explain all the
failures. The largest number of faults that can be included in a single set is number-of-
faults. Increasing this number will allow the analysis routine to consider sets with more
faults, which will increase the run time. Decreasing the number will force the analysis
routine to consider only smaller sets of faults, which will decrease the chance of finding
the set of faults which best explain the failures.
USER RESPONSE:
No response is required, but to change the number-of-faults considered in subsequent
runs, use an environment variable called nummult, whose value represents the number
of faults to consider in a single set of faults.
ERROR (TDG-406): Multiple Fault Analysis is not possible because the following failure(s)
are not explained by any faults:
failure_description
EXPLANATION:
The Multiple Fault Analysis routine attempts to find sets of faults which explain all the
failures. The routine first checks to make sure that each failure is explained by at least
one fault. The specified failure was not explained by any faults, and therefore, Multiple
Fault Analysis will not produce any results.
USER RESPONSE:
It is very unlikely that a failure is not explained by any faults unless the faults that explain
the failure were not simulated during Diagnostics Simulation, or the failing pattern was
not simulated during Diagnostics Simulation. Check the keywords of the original
Diagnostics Simulation run that created the callout data to determine if fault subsetting
needs refinement, or if the pattern subset did not include all failing patterns. Rerun

diagnostic simulation with modified keywords (such as -faults union, -testrange

fail) before attempting Multiple Fault Analysis again.
See "diagnose_failset_logic" in the Encounter Test: Reference: Commands for
ERROR (TDG-407): No sets of up to nummult faults explain the failures.

EXPLANATION:
The Multiple Fault Analysis routine could not find any sets of faults which did a good
enough job of explaining the fails. No callout report will be produced.
USER RESPONSE:
A first step is to increase the number of faults that can be considered in a set. This can
be done by specifying -nummult n as an argument, where n is the maximum number
of faults to consider. Also, consider the original callout data. Does the fault subsetting
need refinement?
Does the testrange need refinement? If so, rerun Diagnostics Simulation before
attempting Multiple Fault Analysis again.
ERROR (TDG-408): Unable to find the first measure event in sequence sequence_name
EXPLANATION:
The reportsequence sequence_name keyword was specified, but there were no
measure events in the specified sequence. No callout will be produced.
USER RESPONSE:
Check the specified sequence. If it is a valid sequence name, run
report_failset -p to determine if there are any failures at that sequence and rerun
if necessary.
ERROR (TDG-409): No failures occurred in sequence sequence_name

EXPLANATION:
The reportsequence sequence_name keyword was specified, but no failures
occurred in the specified sequence. No callout will be produced.
USER RESPONSE:
Check the specified sequence. If it is a valid sequence name, run report_failset -
p to determine if there are any failures at that sequence.

ERROR (TDG-410): The selected analysis can only be performed on callouts produced
using monitor=lpds.
EXPLANATION:
A keyword of stuckatx, slowfaults, multfault, oredpatterns,
mergesequence, or reportsequence was specified, requesting special callout
analysis. The special callout analysis can only be performed on callouts resulting from
diagnostics simulation using the lpds monitor.
The current callout was produced using a monitor other than the lpds monitor.
USER RESPONSE:
Rerun diagnostic simulation with -monitor lpds specified.
WARNING (TDG-411): [Severe] Multiple uncorrelated clock inputs were pulsed in event
odometer. Simulation of this event will be done with the clocks overlapped, but it may produce
incorrect results if there are races in the Design Under Test.
EXPLANATION:
Patterns have been created which contain an event that pulses more than one clock at
the same time. Encounter Test does not do any timing verification to ensure that the clock
pulses will actually overlap in the logic. Encounter Test will simulate the logic with the
clocks on simultaneously, but it may produce incorrect results if the clocks do
USER RESPONSE:
There are two different approaches that can be taken.
If the clocks are not required to be on simultaneously, the input patterns can be
modified to serialize the clock pulses.
WARNING (TDG-412): [Severe] Multiple uncorrelated clock inputs have been

simultaneously activated at event odometer. Simulation will be done with the clocks
overlapped, but it may produce incorrect results if there are races in the Design Under Test.
EXPLANATION:

USER RESPONSE:
There are two different approaches that can be taken.
WARNING (TDG-413): Complete Explain Fails data was not collected - composite fault
scores in the callout report may be less accurate.
EXPLANATION:
The callout report includes composite callout scores from two or more component faults.
When complete Explains Fails data is collected, it is possible to create accurate
composite fault scores by taking the union of the fails explained by the component faults.
When complete Explain Fails data is not available, there may be inaccuracies in the
calculated composite TFSF values, hence the composite fault scores.
USER RESPONSE:
No response is required unless greater accuracy is important. In that case, rerun
diagnose_failset_logic specifying explainfail=yes.
ERROR (TDG-414): Unable to merge pairs of callout faults without complete explain fail
data.
EXPLANATION:
Complete Explain fail data must be present in the original callout in order to merge pairs
of faults
USER RESPONSE:
Rerun Diagnostics Simulation with -explainfail yes and
-contradictionsperfault nolimit.
INFO (TDG-221): Build Bridge Fault Model limited output to number_generated

bridge_faults|net_pairs|fault_rules based on the faults|coverage
setting.

EXPLANATION:
Informational message indicating the total number of bridge faults, net pairs or fault rules
that were generated based on the setting of the indicated keyword. Note that the number
of bridge faults and fault rules generated are always a multiple of the number of net pairs.
The factor is four if generating only static or dynamic faults and eight if generating both.
This depends on the includestatic and includedynamic specifications.
USER RESPONSE:
No response is required unless the resultant bridge fault model, net pair file or fault rule
file is undesirable. In that case, build_bridge_faultmodel should be rerun with
desired settings for faults and coverage.
WARNING (TDG-451): Multiple defect analysis can not be performed since the program is
run with explainfails=no specification. The program reports the standard callout.
EXPLANATION:
Explain failure data is required to perform multiple defect analysis. In this case, the
program is run with explainfail=no specification that prevents the generation of
explain failure data and hence the multiple defect analysis can not be performed. The
callout reported in this case would be the standard callout that identifies a single defect.
USER RESPONSE:
If multiple defect analysis is required, rerun diagnose_failset_logic specifying
explainfail=yes. Otherwise, no response is required.
INFO (TDG-452): Encounter Test Diagnostics Summary:

EXPLANATION:
Informational message indicating the start of diagnostics summary.
USER RESPONSE:
This message contains a short summary of the defects identified in diagnostics and the
top scoring faults associated with each defect. To view the Pin/Net locations associated
with top scoring faults, refer to the callout report printed above this message.
INFO (TDG-453): End of Encounter Test Diagnostics Summary.

EXPLANATION:
Informational message indicating the end of the diagnostics summary.
USER RESPONSE:

INFO (TDG-456): Callout Report Files Summary Report:

EXPLANATION:
Informational message indicating the start of callout report files summary report. This
report contains list of callout file generated in multiple device diagnostics.
USER RESPONSE:
WARNING (TDG-458): The program is running with the specified volumefile and
xmlscoremargin keyword. Specifying a value (user_specified_value) other than
the default value (default_value) for the xmlscoremargin keyword may alter some of
the volume diagnostics trend analysis results.
EXPLANATION:
The volumefile keyword is used to generate callout report(s) in xml format which are
later used for volume diagnostics trend analysis. The xmlscoremargin keyword
controls the list of faults to be included in a callout xml file. This can affect the outcome
of some of the volume diagnostics trend analysis functions which use data from all the
faults present in the callout xml file. Thus, a default value of xmlscoremargin is
recommended for receiving consistent results in volume diagnostics trend analysis.
USER RESPONSE:
If you have specified the volumefile keyword with the xmlscoremargin keyword,
then rerun the command by specifying the xmlscoremargin keyword with the default
value given in the message.
If you do not intend to use the generated callout xml(s) for Encounter Test volume
diagnostics tool, use the xmlout keyword instead of volumefile to suppress the
warning message.
WARNING (TDG-459): The program is running with the specified volumefile and
scoremargin keyword. When not specified by the user, xmlscoremargin takes its value
from scoremargin keyword. Specifying a value (user_specified_value) other than
the defaultvalue (default_value) for the xmlscoremargin keyword may alter some of
the volume diagnostics trend analysis results.
EXPLANATION:
The volumefile keyword is used to generate callout report(s) in xml format which are
later used for volume diagnostics trend analysis. The xmlscoremargin keyword
controls the list of faults to be included in a callout xml file. This can affect the outcome

of some of the volume diagnostics trend analysis functions which use data from all the
faults present in the callout xml file. Thus, a default value of xmlscoremargin is
recommended for receiving consistent results in volume diagnostics trend analysis.
When not specified by the user, xmlscoremargin takes its value from scoremargin
keyword.
USER RESPONSE:
a. If you have specified the volumefile and scoremargin keyword with no keyword
specification for xmlscoremargin keyword, then rerun the command by specifying
the xmlscoremargin keyword with the default value given in the message.
b. If you do not intend to use the generated callout xml(s) for Encounter Test volume
diagnostics tool, use the xmlout keyword instead of volumefile to suppress the
warning message.
ERROR (TDG-464): The user defined scan fault file contains un-supported data. Number of
failing chains in each block should be equal. Processing Ends.
EXPLANATION:
The 'userdefinedscanfaultfile' keyword is used to build the simulation trial points based
on user specified file. This enables the user to control the trial point flow of simulation in
diagnose_failset_scanchain.
Grammer syntax of file :
a)Syntax of user defined scan fault file:
A repeated structure of
{
<Scan Fault Spec Set>
}
b) "Scan Fault Spec Set" contains
<Chain> <bit> <Fault Type String>
c) Example 1: Contains 2 blocks (set) of trial points of 2 failing locations
{
2 23 stuck1
3 12 stuck0
}
{
2 24 stuck1
3 13 stuck0
}
d) Example 2: Contains 2 blocks (set) of trial points of 1 failing location
{

2 23 stuck1
}
{
2 24 stuck1
}
e) Every specification of a scan fault should have all the entries as mentioned
below
Chain => chainID in which scan fault has to be simulated
Bit => Starting bit from which corruption should happen
Fault_Type => Fault Type to Simulate.
f) Valid values of each attribute mentioned above
Chain => 1 to number of chains in the current test mode
Bit => 1 to number of bits in the specified chain
Fault_Type_ String =>
stuck0|stuck1|slowtofall|fasttofall|slowtorise|fasttorise
The error scenario highlighted by this message is that the size of all block sets specified
by the user is not same. An example case of error scenario is given below
{
2 23 stuck1
}
{
2 23 stuck1
3 12 stuck0
}
In above example case, size of first block set is 1 and size of second block set is 2, which
is an unsupported feature.
USER RESPONSE:
Correct and make all block size same in the user defined scan fault file based on the
grammer rule given in message explanation and rerun
diagnose_failset_scanchain with the updated file.
INFO (TDG-465): Completed simulation iteration iteration_number, Upper Bound

identified is current_upperbound.
EXPLANATION:
Informational message indicating the completion of the specified simulation iteration.
The upper bound value after this iteration is also reported. This message helps in
understanding the improvements to upper bound value after each simulation iteration.
USER RESPONSE:

None.
INFO (TDG-466): The returned maximum defect size is actual defect size.
EXPLANATION:
This Informational message states the actual maximum defect size.
USER RESPONSE:
ERROR (TDG-467): The keyword specification newchaindiag=yes is not supported on

design with OPMISR inserted. Processing ends.
EXPLANATION:
The keyword specification newchaindiag=yes is not supported on design with
OPMISR inserted. This keyword is supported only for a testmode with FULLSCAN and
XOR compression structures.
USER RESPONSE:
To perform scan chain diagnostics, specify newchaindiag=no for design unloaded in
OPMISR-FULLSCAN unload mode. Other unloaded modes for design with OPMISR
inserted are not supported for scan chain diagnostics.
WARNING (TDG-468):
EXPLANATION:
The receiver pins from the physical server for the given driver are not valid Encounter
Test pin names.
USER RESPONSE:
For the driver pin, analyze the receiver pin names sent by the physical server. Ensure
that they are valid Encounter Test pin names.
INFO (TDG-674): Start of scan chain XOR segments diagnostics simulation summary
report:
EXPLANATION:
The informational message indicates the start of summary report on scan chain XOR
segments diagnostics simulation. This summary report contains information on top
scoring scan bit ranges on each failing chain and status on their inclusion in callout.
USER RESPONSE:

INFO (TDG-480): Only clock lines to latches will be followed.

EXPLANATION:
Informational message indicating that the only clock lines to latches will be back-traced
during processing.
USER RESPONSE:
INFO (TDG-483): Processing number of fails for a given device fails.

EXPLANATION:
Informational message indicating the number of failures being processed.
USER RESPONSE:
INFO (TDG-484): The generation of fixed value dictionary begins using number of
parallel process parallel processes.
EXPLANATION:
USER RESPONSE:
None
ERROR (TDG-485): The failingreg failing register and bestguess best guess
specification are valid based on fullscan testmode testmode, but they are not part of a valid
scan chain in misr testmode testmode .
EXPLANATION:
USER RESPONSE:
Ensure appropriate failingreg and bestguess value is specified.
WARNING (TDG-486): The mode specification mode specification in

diagnose_scanchain_nofails does not match with the mode specification mode
specification in analyze_chain_diagnosability present in scan chain

dictionary. But, information in the scan chain dictionary will be used for determining initial
upper bound because force=yes is specified.
EXPLANATION:
USER RESPONSE:
None
INFO (TDG-487): No sinks in streak with number_of_nodes nodes

EXPLANATION:
Informational message indicating the number nodes.
USER RESPONSE:
No response required however a combinational loop may exist in the design.
WARNING (TDG-488): [Severe] The mode specification mode specification in

diagnose_scanchain_nofails does not match with the mode specification mode
specification in analyze_chain_diagnosability present in scan chain
dictionary. Hence, information in the scan chain dictionary could not be used for determining
initial upper bound.
EXPLANATION:
The specification of mode keyword is different from the specification present in the scan
chain dictionary
USER RESPONSE:
Change the mode specification to ensure the value matches with mode specification
while generating scan chain dictionary. To use the scan chain dictionary of different mode
specify force=yes.
INFO (TDG-494): Cumulative coverage of flops with upper bound not more than Value of
bitrangeforcumulativecoverage keyword bits away using Algorithm used
to identify coverage algorithm is Final coverage obtained for
given testrange.
EXPLANATION:
Informational message indicating fixed value coverage for all the flops in the design for
specified algorithm and testrange.
USER RESPONSE:

None.
INFO (TDG-495): The value value of numprocs keyword of numprocs keyword is

greater than number of chains to be simulated number of chains to be simulated,
therefore value of numprocs is reduced to number of chains to be simulated.
EXPLANATION:
None
USER RESPONSE:
None.
ERROR (TDG-496): The parallel process associated with channel channel id

associated with parallel process with process ID process ID terminated
incorrectly.
EXPLANATION:
The parallel process generating fixed value dictionary for the specified channel
terminated incorrectly. The process could have been manually killed by the user or could
have been killed due to CPU anomaly.
USER RESPONSE:
Re-run the command and ensure any child process is not killed. If user suspects problem
with the command , re-run with childprocesslogs=yes. This will generate log file for
each parallel process and help user understand why a child process is terminating
incorrectly.
ERROR (TDG-500): Required keyword required_keyword was not specified.

EXPLANATION:
The program requires specification of the keyword in the message.
USER RESPONSE:
Specify the keyword along with a valid value.
WARNING (TDG-501): The test sequences in testrange specification do not match with the
best test sequences present in scan chain dictionary. But, information in the scan chain
dictionary will be used for determining initial upper bound because force=yes is specified.
EXPLANATION:

USER RESPONSE:
None
ERROR (TDG-502): error_message

EXPLANATION:
USER RESPONSE:
Modify the options specified in the command as explained in the message.

WARNING (TDG-503): Splat search did not complete with remaining commonality
commonality target. number_of_splats_identified splats were identified, ,
with a goal of number of splats needed based on the size of the
multiplets splats.
EXPLANATION:
No more splat clusters can be merged without putting pins from the same multiplet, or
pins with no shared explained patterns into the same splat
USER RESPONSE:
Check the complete detection matrix to make sure the explanation is correct. If not, this
is a programming error. Contact customer support (see Contacting Customer Service
on page 23) for resolution.
ERROR (TDG-505): The custom XOR segment scanchain experiment file(s) already exists
and replace=no(default) is specified. Processing ends.
EXPLANATION:
The program has found an existing custom XOR segment scanchain experiment file(s)
in the Encounter Test database. This invocation is made with replace=no(default)
option indicating that the existing file should not be replaced if it exists. Hence, the
processing ends.
USER RESPONSE:

Rerun the program with replace=yes if you wish to replace existing custom XOR
segment scanchain experiment file(s).
INFO (TDG-506): Existing custom XOR segment scanchain experiment file(s) will be
replaced due to replace=yes specification.
EXPLANATION:
The program has found an existing custom XOR segment scanchain experiment file(s)
in the Encounter Test database. This invocation is made with replace=yes option
indicating that the existing file(s) should be replaced if it exists.
USER RESPONSE:
INFO (TDG-507): Creation of custom XOR segment experiment experiment Name of

type experiment Type status.
EXPLANATION:
This is a general informational message.
USER RESPONSE:
INFO (TDG-508): Distribution of XOR gates and ignore measure bits across all the
scanchains for experiment custom XOR experiment name. distribution statistics of
XOR gates
EXPLANATION:
This message gives user information about how many XOR gates were identified while
generating custom XOR scanchain patterns.
USER RESPONSE:
ERROR (TDG-509):Experiment with name experiment name is already present in

committed set of patterns. Hence, the processing ends.
experiment name
EXPLANATION:

The custom XOR segment experiments have pre-defined names

diag_xorsegment_scan0, diag_xorsegment_scan1,
diag_xorsegment_scan0_inv_expects and
diag_xorsegment_scan1_inv_expects. In the current Encounter Test Data base
experiment with one of the previously mentioned names is present in committed set of
patterns.
USER RESPONSE:
Before generating custom XOR segment patterns, run delete_committed_tests to
remove experiments with custom XOR segment experiment names.
ERROR (TDG-510):No XOR segments were found in any of the measure registers.Hence,
the processing ends.
EXPLANATION:
No XOR segments were found in any of the measure registers, hence customer XOR
patterns cannot be created.
USER RESPONSE:
User should ensure appropriate testmode and xorcontrolsignals are providede
while generating customer XOR experiments.
INFO (TDG-513): Report of estimated failing bit ranges for scan chain
failing_scan_chain after good machine simulation iteration
simulation_iteration_number .
EXPLANATION:
For the specified failing scan chain, the possible defective ranges for each sequence are
reported. This information is helpful in determining the range of bits within which the
defect lies.
USER RESPONSE:
INFO (TDG-515): A hotspot file hotspot_file_name is created for user specified nets.
EXPLANATION:
Informational message indicates the successful creation of hotspot file for user specified
nets.
USER RESPONSE:

INFO (TDG-519): Unreachable failure identification is completed. The number of

unreachable failures is unreachable_fail_count.
EXPLANATION:
The number of fails identified as unreachable are reported in this message. If the
reported number is '0', all failures processed by this program could be caused the failing
scan chain. If a non-zero number is reported, these fails could be caused by a
combinatorial logic defect. These failures could be saved in a FAILSET using
logicdevice keyword and these can be diagnosed using
diagnose_failset_logic command.
USER RESPONSE:
No response is required if the number of unreachable failures reported is zero.
Otherwise, if you are interested to identify the probable logic defect causing the
unreachable failures, re-run this command with logicfailset keyword and run
diagnose_failset_logic command on the output FAILSET created.
INFO (TDG-522): Start of Chain Diagnostics Callout Report:

EXPLANATION:
Failing Observable Scan Chain = The observable scan chain number of the failing chain.
Score = (TFSF / (TFSF + TFSP + TPSF) ) * 100
TFSP = How many pins/latches that failed at the tester, passed(did not fail) in simulation.
TPSF = How many pins/latches that passed(did not fail) at the tester, failed in simulation.
USER RESPONSE:
INFO (TDG-524): Start of failing flops report:

EXPLANATION:
Informational message indicating the start of failing flops report
USER RESPONSE:

ERROR (TDG-526):The testmode testmode name contains migrated cores and failset
failset name has failures from migrated patterns.
EXPLANATION:
The testmode specified on command line has migrated cores and failures from migrated
patterns. Diagnosis of such testmodes require Encounter Test database of each core
which is migrated to chip level.
USER RESPONSE:
Run prepare_core_migration_diagnostics command to ensure chip level
Encounter database is aware of directories in which Encounter Test database of all the
migrated cores are present.
ERROR (TDG-531): This command requires a valid diagnostic unload mode to properly
execute on MISR testmodes.
EXPLANATION:
The MISR testmode specified on command line does not have a valid diagnostic unload
mode.
USER RESPONSE:
Re-run the command specifying a testmode having diagnostic unload mode capabilities.
ERROR (TDG-532): The keyword failingnets is not supported for testmode with
Multiple Scan Sections.
EXPLANATION: The user has specified failingnets keyword on command line. In
testmode with multiple scan sections , failingnets value cannot be mapped to single
measure register because multiple measure registers associated with different scan
sections unload at same failing net.
USER RESPONSE:
Re-run the command after converting value of failingnets keyword to failingregs
keyword based on scan section for which user wants to run diagnosis.
ERROR (TDG-533): The specification newchaindiag=no is not supported on design with

Multiple Scan Sections. Processing ends.
EXPLANATION:
This design uses multiple scan sections(MSS) to unload test patterns. For these designs,

user will have to specify newchaindiag=yes.

USER RESPONSE:
sure newchaindiag is specified with a value of yes and rerun.
INFO (TDG-600): Preanalysis of scan chain failures begins.

EXPLANATION:
Informational message indicating the start of analysis of scan chain failures derived from
the Scan Integrity Test. This is a preparatory step to diagnosing scan chain failures.
USER RESPONSE:
INFO (TDG-601): More than number of chains defined in MAX_CORRUPT_PINS chains

failing scan were found. Additional chains are ignored.
EXPLANATION:
Only up to the indicated number of failing scan chains is supported. Execution stops
unless the maxbadchains number is higher. In that case, only the indicated number of
chains will be analyzed.
USER RESPONSE:
The program is coded to handle only the indicated number of failing chains.
MAX_CORRUPT_PINS would need to be changed and program recompiled to change
this.
ERROR (TDG-602): There are no fails in the failset for the scan integrity test. Processing
ends.
EXPLANATION:
Fails from the scan integrity test allow the program to calculate what type of fault to
simulate. The program cannot proceed without this information.
USER RESPONSE:
Create a failset with fails from scan integrity test or use the failingnets and the
failtype keywords to specify the failing chain (net) and failure type.
When using multiple vector files, use the SCANFAILSET keyword to specify the failset
with fails from scan integrity test.
INFO (TDG-603): Analyzing failures from device device_name

EXPLANATION:
Indicates the failures associated with the identified device are being analyzed for
diagnosable scan failures. This message is succeeded by a table listing information
determined for each failing scan chain as follows:
Failure - failure mode (e.g., Stuck1), determined from analysis of Scan Integrity
Test failures
Bit - possible failing measure bit location along chain
Range - probably range of failing measure bits along chain
Scan-out - name of associated scan-out
USER RESPONSE:
INFO (TDG-604): An incomplete identification of the scan chain path was detected between
consecutive scan bits associated with the scan chain feeding scan-out net netname. The
incomplete identification exists between net_or_block net_or_block_name and
net_or_block net_or_block_name. This may affect the accuracy of the callout
EXPLANATION:
The scan chain path identification in Encounter Test has a limitation associated with
reconvergent fan-out logic. When this logic is present along a scan path, the scan path
may not be fully identified. The selected Scan Chain Diagnostics algorithm (keyword
scanfaults=yes) is dependent on a complete identification of the scan path for the
scan chain being diagnosed.
USER RESPONSE:
If the diagnostic result is satisfactory, no further action is required. Otherwise, rerun with
scanfaults=no.
INFO (TDG-605): The following are the keywords that were specified or generated for this
run:
EXPLANATION:
Any specified keywords or those calculated by the pre-process step are reported to
describe the keywords under which this analysis was done.
USER RESPONSE:
Specify keyword overrides on the command line, and rerun if necessary.

INFO (TDG-606): Observable Scan Chain observable_register_number with scan-

out net index net_index and name net_name.
EXPLANATION:
When combined with the 3 messages below, reports the chain that failed the Scan chain
test and the bit position(s) that caused the fail. The chain is identified by Observable
Scan Chain number, net index, and net name. If there is more than one latch called out,
only the lowest (toward scan-out) and highest (toward scan in) are indicated. Bit position
is determined by counting from 1 starting at scan out. More detail about each latch is
reported below.
USER RESPONSE:
Use this information to further pinpoint the problem.
ERROR (TDG-607): A total of number_of_failing_chains chains failed. However,

only one chain may be diagnosed using scanfaults=yes. Processing ends.
EXPLANATION:
The program determined that multiple failing chains are present. However, the
scanfaults=yes option is restricted to diagnosing failsets containing a single failing
chain.
USER RESPONSE:
Specify scanfaults=no and rerun.
ERROR (TDG-608): A failure type of failure_type cannot be diagnosed using

scanfaults=yes. Processing ends.
EXPLANATION:
The indicated failure type was detected. However, the scanfaults=yes option is
restricted to diagnosing failsets containing a single failing chainwith a failure type of
either Stuck0 or Stuck1.
USER RESPONSE:
Specify scanfaults=no and rerun.
ERROR (TDG-609): The specified test mode is incompatible with scanfaults=yes.

Processing ends.
EXPLANATION:

The use of the scanfaults=yes option is restricted to test modes which certain scan
chain information that is missing from the specified test mode. This is most likely because
the test mode was built using an obsolete version of Encounter Test.
USER RESPONSE:
Either rerun diagnostics using scanfaults=no or rebuild the test mode and then rerun
diagnostics using scanfaults=yes.
INFO (TDG-610): At least one of the chains could not be resolved to a single latch. There
are 2 common reasons. One is insufficient data for differentiation. Another is the latches are
part of an array/register. Look at the names of the latches in the range called out. If they are
similar, they may comprise a memory element or other structure that makes it difficult for the
diagnostic to give finer resolution.
EXPLANATION:
Many times the reason a set of consecutive latches is called is because the latches are
elements of an array or register or latches buffering I/O to an array. The diagnostic
depends on latches propagating values to other latches in order to pinpoint the fault.
Since the latches of an array/register do not propagate, no better resolution is possible.
USER RESPONSE:
Collecting more data or data from a different set of patterns may help if the latches are
not part of an array.
INFO (TDG-611): The callout score and location have been re-evaluated. Since simulation
results in a low score, the defect is most likely in the scan-out logic -- the scan path between
the scan bit closest to the scan out, and the scan-out Primary Output pin.
EXPLANATION:
The symptoms of a defective scan-out logic are that there are no fails in other chains,
and that simulation always scores very low at every bit in the failing chain. This situation
is present, so the callout score has been reset, assuming that the defect is in the scan-
out logic. The score is set to 100, but divided by two for every contradiction, where a
contradiction is either a failure measured on a working chain, or a value contrary to the
defect type measured on the failing chain (for instance, a zero measured when the failing
chain is stuck-at-one.)
USER RESPONSE:
INFO (TDG-612): Multiple chains failed and at least one may fail in its output circuit. The
result is inconclusive.

EXPLANATION:
See also TDG-611. The chain that fails in its output is causing low scores. You may
choose to believe the call.
USER RESPONSE:
INFO (TDG-613): Indications are that the indicated latch is shorted to another chain.
EXPLANATION:
Sometimes the scan paths are shorted. If this short acts like a wired-and, then some
values that are opposite of stuck may pass through when the dominating chain
cooperates. The diagnostic thinks it has detected such a case and reports the latch
nearest the short.
USER RESPONSE:
WARNING (TDG-614): The latches with maximum matches and minimum mismatches do
NOT overlap.
EXPLANATION:
The diagnostic is looking for the best score. Normally the best score will coincide with the
latch that has the best TPSF, TFSF, and TFSP counts. In this case, it does not. If the
TPSF count is best at latch 1 (and perhaps has that same best count for several higher
latches), That is an indication of a short with another scan path. (see TDG-613)
Otherwise, it is an indication that the callout is questionable.
USER RESPONSE:
INFO (TDG-615): At least 1 chain was undiagnosable. An attempt has been made to remove
fails attributable only to that chain(s), but that process is not perfect. Thus, some fails caused
by the undiagnosable chain(s) will remain, causing higher TFSP counts and a lower score.
This should not unduly affect your confidence in the call.
EXPLANATION:
When a bad chain cannot be used in the diagnosis (for instance, because it does not fail
in a consistent way), its influence cannot be completely eliminated and will cause many
fails to go unexplained (the TFSP count). Even though the score is low, you can be
assured that the diagnostic has found the correct location.

USER RESPONSE:
INFO (TDG-616): Preanalysis of scan chain failures ends. Time used time.
EXPLANATION:
Informational message indicating the end of analysis of scan chain failures derived from
the Scan Integrity Test. This is a preparatory step to diagnosing scan chain failures.
USER RESPONSE:
ERROR (TDG-617): The keyword=value_list specification contains redundant

entries. Processing ends.
EXPLANATION:
The list of values specified for the indicated keyword contains duplicate entries. This is
not allowed because scan chain diagnostics is limited to diagnosing one defect per failing
scan chain. Any redundancy will cause the run to terminate.
USER RESPONSE:
Remove the redundant entries from the identified keyword specification and rerun.
ERROR (TDG-618): Max iterations (number_of_iterations_attempted)

attempted. Run terminated.
EXPLANATION:
The program will execute a more than generous number of iterations but eventually will
stop if it cannot find an answer.
USER RESPONSE:
ERROR (TDG-619): The scan chains do not fail the scan integrity test in a recognizable way.
Processing ends
EXPLANATION:
Diagnose Failset Scan Chain must be able to identify the scan chains which failed the
scan integrity test, and associate a specific failure type with each. It does this by
examining the specified failures. In this case, the failing scan chains or failure types could
not be determined. Processing ends with no diagnosis performed.

USER RESPONSE:
Ensure the failset is correctly specified or rerun using the failtype and failingnets
keywords.
ERROR (TDG-620): The diagnosis cannot proceed with number_of_failures

applicable failures. A minimum of minimum_number_of_required_failures is
required. Processing ends.
EXPLANATION:
Diagnose Failset Scan Chain must be able to identify a minimum number of applicable
failures to produce a callout. Applicable failures refer to those associated with failing scan
chains having identified failure types. In this case, the minimum number of applicable
failures was not identified. Processing ends with no diagnosis performed.
USER RESPONSE:
Collect sufficient failure data for the device, create a new failset using Read Failures and
then rerun.
INFO (TDG-621): Corrupting observable latch bit range lower_bound to upper_bound

for event_type event odometer
EXPLANATION:
This is a trace of the corrupting activity for each scan-in type of event. It shows the
specific range of observable latch bit positions that were corrupted. Note that observable
latch bit positions are numbered starting at 1 closest to the scan-out, and increment
traversing up the chain.
USER RESPONSE:
ERROR (TDG-622): Invocation of Scan Chain Diagnostics contained an invalid specification

of vectors. The scantestmode and scanexperiment keywords identify a vector set which
is identical to that specified by the testmode and experiment keywords. Processing ends.
EXPLANATION:
When the scan integrity and logic tests are contained within unique vector sets, the
keywords scantestmode and scanexperiment must identify a vector set that is
unique from that specified by testmode and experiment.
USER RESPONSE:

Correct the specification, ensuring testmode and experiment reference different

vectors than scantestmode and scanexperiment, and then rerun.
ERROR (TDG-624): There is a mismatch in the number of values passed in the Override
arguments.
The following are the number of values found for each argument:
Number of Initial Test Points = Number of Initial Test Points

Number of Failing Chains = Number of Failing Chains*
Number of Failing Types = Number of Failing Types
Number of Lower Bounds = Number of Lower Bounds
*Names of Failing Chains are required if other overrides are used.
EXPLANATION:
If any keyword is overridden, failingnets must also be specified. If more than one is
overridden, each must have the same number of values.
USER RESPONSE:
Provide the proper number of keywords in each case ad rerun.
ERROR (TDG-625): No shift count specified with A-SHIFT_CLOCK or B_SHIFT_CLOCK

stuck keyword.
EXPLANATION:
When an A-SHIFT_CLOCK or B_SHIFT_CLOCK is stuck it affects a number of
latches.The count of latches affected must be specified.This count will be equal to the
count of how much sooner values are observed that they should be.
USER RESPONSE:
The A or B value must be immediately followed by a count (no space).
ERROR (TDG-626): LowerBound bound_or_guess exceeds chain length

guess_or_bound
EXPLANATION:
The indicated values do not agree. The starting point must be between the upper and
lower bound and all must be within the number of latches in the chain.

USER RESPONSE:
Change at least one of the pair of values.
ERROR (TDG-627): LowerBound bound_or_guess exceeds UpperBound

guess_or_bound
EXPLANATION:
USER RESPONSE:
ERROR (TDG-628): UpperBound bound_or_guess exceeds chain length

guess_or_bound
EXPLANATION:
USER RESPONSE:
ERROR (TDG-629): Initial Trial Point bound_or_guess exceeds Upper Bound

guess_or_bound
EXPLANATION:
USER RESPONSE:
ERROR (TDG-630): Initial Trial Point bound_or_guess is less than Lower Bound
guess_or_bound
EXPLANATION:
USER RESPONSE:

ERROR (TDG-631): The net name users_net_name is not a net name or does not
correlate to a scanout.
EXPLANATION:
The name may be mis-spelled or mis-typed or (from a command line). You may need
single quotes if the name contains parentheses. If it is correct, then it is not the name of
a scan out.
USER RESPONSE:
Correct the spelling or name.
ERROR (TDG-632): Initial Trial Point bound_or_guess exceeds chain length

guess_or_bound
EXPLANATION:
USER RESPONSE:
WARNING (TDG-633): [Severe] Requested to corrupt at too many points or chains. Limit
is MAX_CORRUPT_POINTS
EXPLANATION:
There is a limited number of points or chains at which the program can simulate a fault.
When that number is exceeded, processing stops.
USER RESPONSE:
The more bad points/chains that need to be simulated, the less sure the result. The
program allows what should be more than enough. To change this would require
recompiling the code.
INFO (TDG-634): There appears to be a concurrent logic fault on this device. This will cause
additional TFSPs and therefore lower scores should be expected and accepted.
(The concurrent fault caused at least unreachable_count fails that had no path back to
faulty chain(s). These have been removed from consideration. However, in all probability
there are other fails that, despite a path back to a faulty chain, are caused NOT by the scan
fault but rather by the logic fault.)

EXPLANATION:
The program has detected at least 1 fail that has no path back to a faulty chain. This
implies the existence of a secondary logic fault. The fails with no back path are removed
but there will likely be some fails that, although there is a path back to a faulty chain, fail
due to the logic fault. These cannot be removed and will show up as TFSPs. The result
should be a good call but with a marginally lower score than would otherwise be the case.
USER RESPONSE:
Accept the call as a good one.
ERROR (TDG-635): Processing ends because too many chains

(number_of_failing_chains) failed. This can be because it was more than the
maximum set by the user (maxbadchains) or more than the program is coded to handle
(MAX_CORRUPT_PINS).
EXPLANATION:
As more chains fail, the opportunity to gather information about what effect each fault has
diminishes. Therefore it is harder to make a good call when many chains fail. It also takes
longer to make the call. Therefore a lower than maximum limit is set.
USER RESPONSE:
If the number of bad chains is not more than the program can handle, Change the
maxbadchains value.
ERROR (TDG-636): The scan chains in testmode scan_testmode are not identical to
those in testmode logic_testmode. Processing ends.
EXPLANATION:
When Scan Chain Diagnostics is run, and the scan integrity and logic tests are in
separate testmodes, the scantestmode and testmode must have identical scan
chains. This is required to ensure the validity of the Scan Chain Diagnostics results.
USER RESPONSE:
Ensure proper specification of the testmodes associated with the scan integrity and logic
tests, and then rerun.
INFO(TDG-637) The calculated lowerbound for scan-out %1$s was within 10 bit positions
from the scan-in. The lowerbound is reset to include the entire scan chain. This is indicative
of an intermittent fault or a short.
EXPLANATION:

When a short occurs one leg of the short may dominate. This may make the fault look
like a stuck value in the scan integrity test but behave erratically during normal loads
during functional test. This means the bad latch may actually work if the conditions on
the other leg of the short are favorable. This, in turn, means non-stuck values may appear
closer to the scan-in than the faulty latch. And that, in turn, causes the program to
calculate a lowerbound very close to scan-in. The program is abandoning this calculation
in order to find a latch close to the defect.
USER RESPONSE:
Expect a lower score.
INFO (TDG-638): Scan fail failure_type on net_name. Position cannot be estimated

due to lack of data.
EXPLANATION:
Similar to TDG-623.
USER RESPONSE:
INFO (TDG-639): The nature of the defect allows a good value to be unloaded from above
the defect.
EXPLANATION:
Normally it is considered impossible for a good value to pass through the defect. (i.e. if
chain is Stuck0 it should not pass a 1). However, this is sometimes possible if the initial
value of the defective latch is 1 (in this example). Under certain conditions it will pass 1s
until it sees its first 0 then, no more 1s will pass.
USER RESPONSE:
No response required. The defect is in the called latch(es).
WARNING (TDG-640): The program is unable to do an accurate recalculation because it

was unable to track all fails for some iterations. New scores are a good estimate but
inaccuracy can throw off search. maxexplainresults was result count, actual
number needed was result target.
EXPLANATION:
To rescore the program must track each fail for each iteration. To prevent this from using
too much memory, a limit is set.
USER RESPONSE:

If there is enough available memory, increase tracking with maxexplainresults.
ERROR (TDG-641): Failures from multiple devices were detected, however only a single
device can be diagnosed by this application. Processing ends.
EXPLANATION:
The diagnostics application being run can only diagnose failures from a single device. In
this case, the specified failure set contained failures associated with multiple devices.
USER RESPONSE:
Rerun the application, specifying a single failing device.
ERROR (TDG-642): Failures from multiple devices were detected, however multiple device
diagnosis is not enabled. Processing ends.
EXPLANATION:
There are multiple devices in the specified FAILSET. By default, the program does not
diagnose all the devices unless multidevicediagnosis=yes is specified.
USER RESPONSE:
Rerun the application either specifying a single failing device, or specify
multidevicediagnosis=yes if multiple device analysis is desired.
WARNING (TDG-643): Failures from multiple devices are being diagnosed. This may result
in poor callout scores.
EXPLANATION:
It is recommended that this application be used to diagnose failures from a single device
on a single invocation. In general, simultaneously diagnosing multiple devices leads to
poor callout scores.
USER RESPONSE:
Rerun the application either specifying a single failing device, or specify
multipledeviceanalysis=no if multiple device analysis is not desired.
ERROR (TDG-644): Unable to satisfy diagnostic database update request for multiple
devices in a single diagnose_failset_logic run.
EXPLANATION:
The diagnostics application being run can only diagnose failures from a single device
while updating the diagnostic database.

USER RESPONSE:
Rerun the application specifying a single failing device.
WARNING (TDG-645): [Severe] Unable to update the diagnostic database for failset
failset_name and device device_name because associated failure data does not exist
in the database.
EXPLANATION:
The diagnostic database can only be updated by running the
diagnose_failset_logic commands for failsets that have been successfully written
to the diagnostic database by read_failures using
updatediagosticdatabase=yes.
USER RESPONSE:
Perform either of the following actions:
Run read_failures using updatediagosticdatabase=yes then rerun
diagnose_failset_logic or diagnose_failset_scanchain.
Rerun diagnose_failset_logic or diagnose_failset_scanchain
with updatediagosticdatabase=no.
INFO (TDG-646): Diagnostic database update completed successfully. Time used

CPU_time/elapsed_time.
EXPLANATION:
The diagnostic results were successfully stored in the diagnostic database in the
indicated time frame.
USER RESPONSE:
WARNING (TDG-647): Diagnostic database update unsuccessful.

EXPLANATION:
An error occurred while writing the diagnostic results to the diagnostic database. This
does not mean that the callout results are invalid, however performing analysis on the
results stored in the diagnostic database may produce misleading results, and may not
even be possible.
USER RESPONSE:
Correct the indicated problems in preceding messages and rerun.

ERROR (TDG-648): The logicfailset keyword should not be specified when

updatediagnosticdatabase is set to yes. Processing ends.
EXPLANATION:
The failures associated with a non-scan defect will be added in to a failset specified to
logicfailset keyword. When this keyword is specfied,
updatediagnosticdatabase should not be set to yes. This support is not available
currently.
USER RESPONSE:
If you wish to update the volume diagnostic database, rerun the command without
specifying the logicfailset keyword. If you wish to generate the failset that contains
non-scan failures identified by diagnose_failset_scanchain, rerun the command
with updatediagnosticdatabase=no.
INFO (TDG-649): The current range of suspected bits is current_suspected_bits

and user specified value for stopatcalloutrange is stop_at_callout_range.
Since the range is within the value specified to stopatcalloutrange, additional
simulations will not be performed.
EXPLANATION:
This is an informational message indicating the completion of diagnosis due to
stopatcalloutrange specification.
USER RESPONSE:
If best diagnosis accuracy is needed, re-run by removing the stopatcalloutrange
specification. Otherwise, no response is required.
INFO (TDG-650): Current testmode contains OPMISR based compression. For this
testmode, failures collected in FULLSCAN unload mode will only participate in partitioning
process. Failures collected in other modes (MISR unloaded in parallel/serial) will be filtered
out and remain in the input FAILSET.
EXPLANATION:
This informational message indicates the partitioning process for designs with OPMISR
based compression.
USER RESPONSE:
None.
INFO (TDG-665): The xor control signal used to create scan patterns is
xor_control_signals_pin_name .

EXPLANATION:
The information message indicates the xor control signal pin name, which was used to
create scan patterns for xor segment.
USER RESPONSE:
None.
INFO (TDG-700): Program ends due to stopafterdeviceselection=yes specification.

EXPLANATION:
This message indicates the early completion of the program after device selection
process is completed.
USER RESPONSE:
INFO (TDG-701): Program ends due to stopaftersequenceselection=yes

specification.
EXPLANATION:
This message indicates the early termination of the program after sequence selection
process is completed for all devices.
USER RESPONSE:
INFO (TDG-702): The number of test sequences selected for simulation

test_sequences_selected_for_simulation exceeded the value specified to
'multidevicenumtests (maximum_number_of_test_sequences_allowed).
Program ends.
EXPLANATION:
User has requested to stop the program when the total number of sequences selected
for simulation is more than the value specified to multidevicenumtests keyword. In
this case, the number of sequences exceeded the specified value and hence the
processing ends.
USER RESPONSE:
Re-run with a greater value to multidevicenumtests keyword or rerun with a smaller
set of devices.

ERROR (TDG-703): The faultset=faultset_value is not supported when multiple

device diagnosis is enabled. The only supported value for this test mode is
supported_faultset_value. Processing ends.
EXPLANATION:
User has specified an unsupported fault selection option and hence the processing
ended.
USER RESPONSE:
Re-run with the specified value to faultset keyword.
INFO (TDG-704): The diagnose_failset_logic log file name is log_file_name.

EXPLANATION:
The log file name of diagnose_failset_logic is reported for reference purposes.
USER RESPONSE:
INFO (TDG-705): Completed callout reporting for number_of_devices_processed

devices. Cumulative Time used: CPU_time/elapsed_time.
EXPLANATION:
Informational message indicating the completion of callout reporting and the time used.
USER RESPONSE:
INFO (TDG-706): Fault Selection report for selected failing devices:
EXPLANATION:
Informational message indicating the start of fault selection report for multiple device
diagnostics process.
USER RESPONSE:
ERROR (TDG-711): Support for design with migrated OOC cores is not present. Processing
ends.
EXPLANATION:

The Program does not supports hierarchical test diagnostics flow. The design contains
migrated OOC cores.
USER RESPONSE:
Find the TMD (tbdata) directory of OOC core instances and run through that directory.
ERROR (TDG-712): Support for design with migrated cores and OPMISR is not present.
Processing ends.
EXPLANATION:
The migrated core under test in the testmode contains OPMISR and support for scan
chain diagnosis is not present.
USER RESPONSE:
Support for OPMISR testmode is not present.
ERROR (TDG-713): Failure from multiple OPMISR unload modes found in device(s)
list_of_device_name. Support for processing failures from multiple OPMISR unload
modes is not present. Processing ends.
EXPLANATION:
The design contains OPMISR logic and failures are recorded at multiple OPMISR unload
modes for a single device. For further information of types of OPMISR unload modes
refer previous messages. The list of device(s) present in failset contains failures recorded
from multiple OPMISR unload modes. Support for processing failures from multiple
OPMISR unload modes is not present.
USER RESPONSE:
Filter the list of device(s) given in the message from failset using 'device' keyword.
ERROR (TDG-998): Logic model not available.

EXPLANATION:
The application has tried to access the logic model, and was unsuccessful.
USER RESPONSE:
Verify that the logic model has been built, and resides in the specified workiing directory.
ERROR (TDG-999): [Internal] The following internal program error occurred in the
Encounter( Test diagnostics code.

Contact Cadence Customer Support to report this error and give them the following
information
An error occurred on line line_number of file file_name:

variable_text
EXPLANATION:
This error indicates a program error that only the Encounter Test team can fix. The
information provided in this message is not intended to be meaningful to you; but it will
allow the programmer to find and fix the error more quickly.
USER RESPONSE:
Contact the customer support team using your normal process; SourceLink, email, or
This will allow the programmer to find and fix the problem more quickly.
Refer to Contacting Customer Service on page 23.


20
TDL - True-Time Test Messages
TDL-001 through TDL-230 on page 553

TDL-240 through TDL-301 on page 561
TDL-001 through TDL-230

WARNING (TDL-001): [Severe] Error .. msgtext. The Pin/Net/Block index hierIndex
not found in the Model.
EXPLANATION:
The specified Pin/Net/Block index was not found in the model.
USER RESPONSE:
Ensure that the Pin/Net/Block index is correct and rerun if necessary.
INFO (TDL-050): Clock Domains Being Processed.

EXPLANATION:
This message lists the clock domains being processed in this report. The list of clock
domains are derived from the testclockconstraints and sysclockconstraints
files.
USER RESPONSE:
INFO (TDL-051): Defect Probability Report

EXPLANATION:
This message lists each fault whose defect probability exceeds the threshold specified
in the defectprobability keyword. Its purpose is to identify faults that are detected
by short paths relative to their longest possible paths.

The following describes the column headings:
Fault The index number of the fault.

Defect Prob The probability of the defect occurring (per the defect
probability distribution).
System Period The system clock speed (ps)
Longest Poss Path The longest possible path (ps)
Timing Redundant The number of picoseconds between the system period
and Longest Possible Path (ps).
Defects smaller than this number are considered timing
redundant and cannot be observed.
Test Period The test clock speed (ps)
Longest Sens Path The longest sensitized path (ps) where the fault was
tested
Defect Size The number of picoseconds between the system period
and the Longest Sensitized Path (ps); this measures the
maximum size.
USER RESPONSE:
INFO (TDL-052): SDQL By Clock Domain

EXPLANATION:
This message lists each of the clock domains and their respective SDQL results.
Tested SDQL The number of delay defects (in ppm) that are detected by
the set of test patterns
Untested SDQL The number of defects (in ppm) that escape the set of test
patterns
Total SDQL TThe sum of Tested and Untested
Test Effectiveness Ratio of the Tested SDQL / Total SDQL

Note that SDQL calculations do not include faults on latches, flip-flops, RAMs, ROMs, PIs
or POs. Any faults that have been tested without timing information (for example, faults
that were tested via the scanchain test), are therefore not included in the SDQL
calculations.
USER RESPONSE:
ERROR (TDL-053): Either testclockconstraints or testperiod must be specified.

EXPLANATION:
Either testclockconstraints or testperiod keywords must be specified in order
to determine the speed of the clock domains under test. The speed is required to
determine the SDQL for untested faults.
USER RESPONSE:
Specify the missing keyword and rerun report_sdql.
ERROR (TDL-054): One of sysclockconstraints, testclockconstraints or

systemperiod must be specified
EXPLANATION:
One of the keyword sysclockconstraints, testclockconstraints or
systemperiod must be specified in order to determine the speed of the clock domains
in system mode. The speed is required to determine the SDQL for untested faults. When
testclockconstraints file is specified without sysclockconstraints and
testperiod, the system speed is assumed to be the same as the test speed defined
in the testclockconstraints file.
USER RESPONSE:
Specify the missing keyword and rerun report_sdql.
ERROR (TDL-055): System clock period is sp for clock domain d. Processing Terminates.
Specify the system clock period via the systemperiod or sysclockconstraints
keywords
EXPLANATION:
The system clock period specified is less than or equal to zero. It must be a positive
number (in picoseconds). The system clock period may be defined in the
sysclockconstraints file for each clock domain, or a global value may be specified
using the systemperiod keyword. If neither are specified, the
testclockconstraints file periods will be used.

USER RESPONSE:
Specify the correct system clock period and rerun report_sdql.
ERROR (TDL-056): Test clock period is tp for clock domain d. Processing Terminates.
Specify the system clock period via the testperiod or testclockconstraints keyword.
EXPLANATION:
The test clock period specified is less than or equal to zero. It must be a positive number
(in picoseconds). The test clock period may be defined in the testclockconstraints
file for each clock domain, or a global value may be specified using the testperiod
keyword.
USER RESPONSE:
Specify the correct test clock period and rerun report_sdql.
WARNING (TDL-057): Longest Possible Path is lpp (ps) for fault fid. This fault is
excluded from the SDQL calculations
EXPLANATION:
The longest possible path recorded during small delay simulation is less than zero. This
may be due to a problem with the delay model. The fault is excluded from the SDQL
calculations.
USER RESPONSE:
Correct any problems reported by read_sdf and rerun analyze_vectors
defectsize=yes. If the delay model is accurate, contact customer support (see
Contacting Customer Service on page 23) for further assistance.
WARNING (TDL-058): Longest Sensitized Path is lsp (ps) for fault fid. This fault is
excluded from the SDQL calculations.
EXPLANATION:
The longest sensitized path recorded during small delay simulation is less than zero. This
may be due to a problem with the delay model. The fault is excluded from the SDQL
calculations.
USER RESPONSE:
Correct any problems reported by read_sdf and rerun analyze_vectors
defectsize=yes. If the delay model is accurate, contact customer support (see
Contacting Customer Service on page 23) for further assistance.

WARNING (TDL-059): Test clock period is fttc (ps) for fault fid. Using user-specified
test clock period of ttc (ps)
EXPLANATION:
The test clock period recorded during small delay simulation is less than zero. This may
be due to a problem with clock constraints file provided during small delay simulation.
The test clock period specified in the testclockconstraints file or testperiod
keyword is used instead.
USER RESPONSE:
No action is necessary if the test clock period used by report_sdql is correct. If not,
rerun anaylze_vectors defectsize=yes with the correct periods specified in the
clockconstraints file and then report_sdql.
ERROR (TDL-060): Small delay information does not exist for this experiment. Run
analyze_vectors or create_logic_delay_tests with smalldelay=yes and
delaymodel=delaymodel.
EXPLANATION:
This command requires that the small delay defect size information exist for the specified
experiment. The small delay information is recorded during delay test generation or
simulation by adding the keywords smalldelay=yes and
delaymodel=delaymodel. Additional keywords may be added to control the defect
size computation process (for example, percentpath or ndetect).
USER RESPONSE:
Rerun test generation or analyze_vectors using the required keywords. Then rerun
this command.
ERROR (TDL-061): Either a delay model or an experiment must be specified.

EXPLANATION:
This command requires either a delay model to report an SDQL histogram, or an
experiment to report the experiments SDQL.
USER RESPONSE:
Rerun the command with the appropriate keyword.
INFO (TDL-063): Histogram of Per Fault Untested SDQL (Potential)

EXPLANATION:

This message reports a histogram of the per-fault, potential SDQL for various SDQL
ranges. The number of faults and the percentage of the total SDQL are reported for each
range of SDQL values. Also reported are recommended values for tgsdql and
simsdql keywords, which are used to perform small delay ATPG and simulation using
the create_logic_delay_tests and analyze_vectors commands.
USER RESPONSE:
ERROR (TDL-064): Delaymodel is required for experiments created prior to Encounter Test
version 8.1.200.
EXPLANATION:
This command requires a delaymodel when running report_sdql on pattern sets
analyzed using any version prior to Encounter Test 8.1.200.
USER RESPONSE:
ERROR (TDL-065): A clockconstraints file, system period, or test period is required to run
this command.
EXPLANATION:
The command is not able to determine the system period and test period from the
existing pattern set. A clockconstraints file should be provided. If there is a single clock
domain, or all domains use the same test period, the testperiod and/or sysperiod
keywords may be specified in lieu of the clockconstraints file.
USER RESPONSE:
ERROR (TDL-066): No clock domains were found in the small delay defect size information.
Verify that analyze_vectors with smalldelay=yes completed successfully, and that it
will detect faults when smalldelay=no.
EXPLANATION:
There were no clock domains found in the small delay defect size data, indicating that
either the analyze_vectors or create_logic_delay_tests command did not
complete successfully, or no faults were observed at scannable flops so that small delay
data could be recorded.
USER RESPONSE:

Rerun the command used to create the small delay defect size information and then
rerun report_sdql.
WARNING (TDL-150): [Severe] There are no scannable latches for this design.
EXPLANATION:
No scannable latches were found for this design in this test mode.
USER RESPONSE:
If there should be scannable latches, then determine why none are found. Otherwise,
continue processing using only Chip Pins for testing.
WARNING (TDL-151): There are no distances calculated for this design. Frequency will be
set to clockconstraints or maxpathlength.
EXPLANATION:
Frequency cannot be calculated because delays are missing between the launch and
capture PIs, latches, or POs.
USER RESPONSE:
Determine why no distances were calculated and then rerun..
ERROR (TDL-200): Cannot establish parts directory location.

EXPLANATION:
The location of the design is incorrect or missing.
USER RESPONSE:
Ensure that the WORKDIR is correctly set.
ERROR (TDL-201): Cannot continue pre-Delay Test process.

EXPLANATION:
An Error occurred which caused the process to end.
USER RESPONSE:
Read all messages previous to this one to get the reason for termination.
ERROR (TDL-202): Invalid or missing MaxPathLength specified.

EXPLANATION:
Either the MaxPathLength is missing or the value is invalid.

USER RESPONSE:
If running without delays (usedelays=no) or (maxpathcalc=no), then you must
specify a valid maxpathlength. The value must be an integer between 1000 and
500000 and represents the longest path in picoseconds for which faults can be detected.
ERROR (TDL-203): No Delay Model specified.

EXPLANATION:
Delay calculations were asked for but no delay model was specified.
USER RESPONSE:
In order to calculate delays for either maxpath length or to find constraints, a Delay Model
name must be provided.
ERROR (TDL-204): Incorrect arguments or environment in intermediate script.

EXPLANATION:
The expected arguments and environment for the script was not found.
USER RESPONSE:
Do not call this script directly or alter the way it is called from
prepare_timed_sequences.
ERROR (TDL-205): Invalid specification for DI2 pin or Scan Enable pin.
EXPLANATION:
The DI2pin= or scanenable= arguments were incorrect.
USER RESPONSE:
Restart process with valid arguments. Refer to "prepare_timed_sequences" in the
Encounter Test: Reference: Commands.
ERROR (TDL-206): Could not determine the MaxPathLength from path distribution.
EXPLANATION:
The MaxPathLength could not be calculated from analyzing a random sample of paths.
USER RESPONSE:
Rerun the prepare_timed_sequences command. Either pass in a maxpathlength to
use or specify usedelays=no to complete the process without delays.

See "prepare_timed_sequences" in the Encounter Test: Reference: Commands.
WARNING (TDL-207): Unable to determine any testsequences for test generation, since no
faults were found to testable by the given testsequences, clockconstraints or
dynseqfilter.
EXPLANATION:
No faults were found to testable by the given testsequences, clockconstraints or
dynseqfilter.
USER RESPONSE:
Review the testsequences, clockconstraints or dynseqfilter to see why circuit is over
constrainted, such that no faults can be tested.
WARNING (TDL-230): Pin pinName shares both a system and scan clock function. You
may get better results from dedicated scan clocks.
EXPLANATION:
You have provided a Line Hold file by the same name as the one to be generated.
Therefore, your file will be used.
USER RESPONSE:
If this is your intent, no action is required.
TDL-240 through TDL-301

WARNING (TDL-240): The minimum delay test width allowed by the tester of mintest ps
is larger than the calculated maxpath of calctest ps. The tester minimum will be used as
the value.
EXPLANATION:
The minimum delay test width allowed by the tester is the sum of the minimum pulse
widths of the release and capture clocks and the accuracy constants for all four edges of
the clocks. Since any test smaller than this value cannot work on the tester, the
calculated maximum path length will not work.
USER RESPONSE:
Ensure that the delay model is accurate and that the Tester Description Rule reflects the
correct timing attributes of the tester.

WARNING (TDL-241): The minimum delay test width allowed by the tester of mintest ps
is larger than the user specified maximum path width of userval ps.
The user-specified value will be used.

EXPLANATION:
The minimum delay test width allowed by the tester is the sum of the minimum pulse
widths of the release and capture clocks and the accuracy constants for all four edges of
the clocks. Since any test smaller than this value cannot work on the tester, the specified
maximum path length may not work at the tester.
USER RESPONSE:
Ensure that the specified maximum path length is accurate and that the Tester
Description Rule reflects the correct timing attributes of the tester.
ERROR (TDL-242): If the delaymodel is specified, the TDR must contain PIN_TIMING
information. Either remove the delaymodel or add PIN_TIMING information to the TDR.
EXPLANATION:
The delaymodel and TDR PIN_TIMING, which describe testers capabilities, are
required to generate accurate sequencess
USER RESPONSE:
Add the PIN_TIMING information to the TDR or remove the delaymodel keyword from
the prepare_timed_sequences command string. Rerun in either case.
WARNING (TDL-244): More than 10 percent of all measures are ignored at a

maxpathlength of maxpath1 ps. The maxpathlength for this sequence is enlarged to
maxpath2 ps.
EXPLANATION:
When a significant number of measures are ignored, the test coverage is significantly
reduced. The maximum path length is increased to reduce the number of ignored
measures.
USER RESPONSE:
Accept the increased maximum path length, rerun with a larger specified
maxpathlength, or constrain the design switching to shorten the paths.
INFO (TDL-260): Line hold file provided, none will be generated.

EXPLANATION:

You have provided a Line Hold file by the same name as the one to be generated.
Therefore, your file will be used.
USER RESPONSE:
If this is your intent, no action is required.
INFO (TDL-300): Begin Processing Clock Domain domainNumber testsequence

sequenceName.
EXPLANATION:
The ATPG process is now testing the logic controlled by the clocks found in the named
test sequence. Only the faults within this logic will be processed and the statistics also
will only be listed for this logic.
USER RESPONSE:
INFO (TDL-301): Finished Processing Clock Domain domainNumber testsequence

sequenceName.
EXPLANATION:
ATPG is processing the logic controlled by the clocks found in the named test sequence.
USER RESPONSE:


21ste
TDM - Delay Model Build Messages
TDM-001 through TDM-050 on page 565

TDM-001 through TDM-050

INFO (TDM-001): Delay Model Build processing begins.
EXPLANATION:
Indicates that Delay Model Build processing has started.
USER RESPONSE:
(severity) (TDM-002): Delay Model Build processing ended with errorType.

EXPLANATION:
Indicates that Delay Model Build processing has completed.
USER RESPONSE:
WARNING (TDM-003): Lossy triplet compression was requested but no tolerance was
given. Reverting to lossless compression.
EXPLANATION:
Lossy triplet compression was specified using the tripletcompression=lossy
parameter. In order to utilize lossy triplet compression you must also specify a triplet
tolerance factor so that Delay Model Build knows which triplets it can combine to achieve
the desired compression.

USER RESPONSE:
Either specify the triplet tolerance using the triplettolerance parameter or change
the tripletcompression parameter to use lossless or no triplet compression.
Refer to "build_delaymodel in the Encounter Test: Reference: Commands.
ERROR (TDM-004): SDF file name was not specified. Cannot continue.
EXPLANATION:
A request was made to parse a Standard Delay File (SDF), but the name was not
specified.
USER RESPONSE:
Specify the location and name of the SDF using the sdfname and sdfpath parameters
or specify parsesdf=no on the command line if you do not wish to parse an SDF file
and build a delay model.
ERROR (TDM-005): SDF file (sdfName) cannot be found. Cannot continue.

EXPLANATION:
The Standard Delay File (SDF) location was specified on the command line but it could
not be located.
USER RESPONSE:
Specify the correct location of the SDF using the sdfname and sdfpath parameters
and ensure that it can be read by the user running Delay Model Build.
ERROR (TDM-006): Could not open the SDF file (sdfName). Cannot continue.
EXPLANATION:
The Standard Delay File (SDF) location was specified on the command line but it could
not be opened for reading.
USER RESPONSE:
Specify the correct location of the SDF using the sdfname and sdfpath parameters
and ensure that it can be read by the user running Delay Model Build.
INFO (TDM-007): Parsing SDF file.

EXPLANATION:
Delay Model Build has begun parsing the Standard Delay File (SDF).

USER RESPONSE:
WARNING (TDM-008): [Severe] SDF header specifies an invalid hierarchy divider

character (hierChar). Valid characters are . or /.
EXPLANATION:
The Standard Delay File (SDF) contains a DIVIDER specification in its header that is not
a legal hierarchy divider character.
USER RESPONSE:
Change the SDF to use either period (.) or forward slash (/) as the hierarchy divider
character. Refer to the SDF 2.1 specification for further details.
WARNING (TDM-009): SDF version number was not specified. Attempting to process as a
version 2.1 SDF.
EXPLANATION:
The Standard Delay File (SDF) does not specify to which version of the SDF specification
it conforms.
USER RESPONSE:
If the SDF conforms to version 2.1 of the specification, add the header line
SDFVERSION "2.1" or simply ignore the warning. If it does not conform to version 2.1,
you will probably not be able to use this SDF with this version of Delay Model Build.
WARNING (TDM-010): SDF version sdfVersion is not directly supported by

build_delaymodel. Attempting to process as a version 2.1 SDF.
EXPLANATION:
The Standard Delay File (SDF) specifies that it conforms to a version of the SDF
specification that is not supported by Delay Model Build.
USER RESPONSE:
The SDF may be used despite this problem, but if using new or unique constructs that
conform to an SDF specification version greater than 2.1, a syntax error will be produced.
Verify the generated SDF is at version 2.1.
INFO (TDM-011): SDF header information follows:

EXPLANATION:

The Standard Delay File (SDF) has been successfully parsed and a summary of the
information contained in the SDF header will be printed below this point.
USER RESPONSE:
WARNING (TDM-012): [Severe] Unable to create a delay between the following pins
hecause they are not PIs, POs or on the highest level cell.
Pin 1: pin1Name
Pin 2: pin2Name
SDF line number: sdfLine
EXPLANATION:
One or both of the pins specified is not a PI, PO, or cell boundary input or output on the
highest level of hierarchy with the CELL/BOOK attribute. As a result, no delays can be
created to or from this pin, but such a delay was specified in the Standard Delay File
(SDF) on the reported line number. These delays will not be included in the delay model
and as a result, the delay model might be missing important timing information.
USER RESPONSE:
Ensure that the delays are specified from/to a PI or PO or a cell boundary pin. You may
have to change your model if the cell boundaries are not correctly defined, by adding the
CELLTYPE="BOOK" attribute to the level of hierarchy or simply changing the SDF delays
to point to the correct level of hierarchy.
WARNING (TDM-013): [Severe] Unable to create a width/period delay.

Pin: pinName
EXPLANATION:
A width delay is specified in the Standard Delay File (SDF) on a pin that is not a cell
boundary input or output on the highest level of hierarchy with the CELL/BOOK attribute.
This delay cannot be added to the delay model for this reason and the resulting model
may be missing important timing information.
USER RESPONSE:
Ensure that the delays are specified on a PI or PO or a cell boundary pin. You may have
to change your model if the cell boundaries are not correctly defined, by adding the
CELLTYPE="BOOK" attribute to the level of hierarchy or by changing the SDF delays to
point to the correct level of hierarchy.

WARNING (TDM-014): Unresolved delay to/from internal point.

Internal point name: internalPointName
Block: blockName
EXPLANATION:
A pin name was specified in the Standard Delay File (SDF) that does not exist in the
Encounter Test hierarchical model. This is normally ok if valid delays can be related both
from and to this point, however, the name specified in the message could not. As a result
the delay information will not be incorporated into the delay model.
USER RESPONSE:
Verify that you have spelled the name of the pin/internal point correctly. If the name was
intended to be an internal point, verify that you have a delay going from a real pin to it,
and from it to a real pin so that it can be incorporated into the model. If you do not wish
to see these messages relating to internal points of a given name, you can use the
internalpointstring parameter to specify part or all of the name of the internal
points to ignore (if they cannot be resolved).
Refer to "build_delaymodel in the Encounter Test: Reference: Commands for more
details on this parameter.
WARNING (TDM-015): PORT delay contains transitions other than rise/fall, rising, or falling.
Delay on SDF line sdfLine is ignored.
EXPLANATION:
Delay Model Build does not recognize PORT delays for any transitions other than those
listed. The delay specified will be ignored and the resulting delay model will not contain
this information.
USER RESPONSE:
Ensure that you have not specified extra sets of triplets for this delay on the cited line
number of the Standard Delay File (SDF). For PORT delays, only two sets of triplets
("(##:##:##)(##:##:##)") are supported.
WARNING (TDM-016): Unable to allocate temporary space needed for triplet compression.
Leaving triplets uncompressed.
EXPLANATION:
The type of triplet data value compression requested could not be performed due to
insufficient available memory or swap space. The triplet data will be added to the delay
model without being compressed.

USER RESPONSE:
No response is required, however, you may wish to run delay model build again on a
system with more RAM or available swap space to achieve a smaller delay model DASD
and memory footprint.
INFO (TDM-017): Beginning triplet data compression.

EXPLANATION:
The process to reduce the size of the set of data values stored in the delay model is
beginning.
USER RESPONSE:
INFO (TDM-018): compressedTriplets of totalTriplets triplets compressed

(saved megaBytesSaved MB / percentCompressed%)
EXPLANATION:
The process of determining which sets of triplet data can be compressed in the delay
model has completed. The triplet information volume will be reduced as indicated by the
message.
USER RESPONSE:
INFO (TDM-019): Updating delay model with new triplet mappings.

EXPLANATION:
The process to update the delay model with the reduced triplet information is beginning.
USER RESPONSE:
INFO (TDM-020): Triplet compression complete.

EXPLANATION:
The process of updating the delay model with the reduced triplet information has
completed.
USER RESPONSE:

ERROR (TDM-021): [Internal] Attempted to add an invalid delay (TDMnodeID nodeID,

delay type delayType). Delay was ignored.
EXPLANATION:
An internal program error occurred which caused the delay information being added to
the model to become corrupted.
USER RESPONSE:
INFO (TDM-022): Creating human-readable version of the delay model.

EXPLANATION:
You have requested to create a human-readable version of the delay model using the
printmodel parameter. It is being created to the output stream that you have specified.
USER RESPONSE:
ERROR (TDM-023): Unable to allocate memRequested bytes for extent collection.

EXPLANATION:
Delay Model Build required more memory than what could be allocated on the machine
on which it was running. The process cannot complete under this condition.
USER RESPONSE:
Run Delay Model Build for this part on a larger machine with more available RAM and
swap space.
ERROR (TDM-024): [Internal] Extent collection was corrupted!

EXPLANATION:
One of the internal data structures used by Delay Model Build has become corrupted due
to an internal program error.
USER RESPONSE:
ERROR (TDM-025): [Internal] Attempted to operate on a NULL file handle.

EXPLANATION:

A read or write operation was attempted on a file that failed to open.

USER RESPONSE:
ERROR (TDM-026): Unable to access the hierarchical model. Cannot continue.

EXPLANATION:
Delay Model Build could not open the Encounter Test hierarchical model for this design.
Processing cannot continue without it.
USER RESPONSE:
Ensure that the proper WORKDIR parameters are specified and that the hierarchical
model pointed to by these parameters can be read by the current user.
INFO (TDM-027): Building cell-based design model.

EXPLANATION:
Delay Model Build is creating a model of the design that it needs to store its information
properly.
USER RESPONSE:
INFO (TDM-028): Message summary:

EXPLANATION:
A summary of all of the messages issued during this run of Delay Model Build will be
printed after this message. They are displayed by cell and by message ID. This summary
includes the total number of times that these messages occurred, however, the number
of messages actually printed may be significantly less if the same message occurs more
than once about the same pins. This is for information only and is provided to help you
quickly locate if any severe problems occurred, and if so, which cells they pertain to (if
applicable).
USER RESPONSE:
INFO (TDM-029): Writing delay model.

EXPLANATION:

The delay model is being written. If you specified to allow the delay model to be
compressed, gzip will be executed at this point as the delay model is being written to
achieve the compression.
USER RESPONSE:
ERROR (TDM-030): Fatal error (errorType) parsing the SDF on line sdfLine:
lastToken
EXPLANATION:
An error occurred attempting to parse the Standard Delay File (SDF).
USER RESPONSE:
Check the line cited for syntax errors with respect to the SDF 2.1 syntax specification.
WARNING (TDM-031): [Severe] Pin was not found on block.

Pin: pinName
Block: blockName
EXPLANATION:
The Standard Delay File (SDF) specified a pin name that was not found on the block
specified. This delay information will not be added to the delay model.
USER RESPONSE:
Ensure that the pin name was spelled correctly and that the correct block was specified.
Fix the erroneous SDF line and rerun Delay Model Build.
WARNING (TDM-032): Delay type is not supported by build_delaymodel.

Delay type: delayType
EXPLANATION:
The delay type specified is not supported by this version of Delay Model Build. This delay
information is ignored.
USER RESPONSE:

No response is required, however, if you can specify an alternative way of representing

the delay information for this delay type that is understood by Delay Model Build, you may
wish to do so.
WARNING (TDM-033): [Severe] No valid pins were specified in the delay on SDF line
sdfLine.
EXPLANATION:
The Standard Delay File (SDF) contains a delay in which neither of the pins can be
matched to a cell boundary pin in the hierarchical Encounter Test design model. This
delay will be ignored and its data will not be added to the delay model.
USER RESPONSE:
Ensure that the correct pin(s) were specified in the SDF and that they reside on the
correct level of hierarchy (the topmost block with the CELL/BOOK attribute, or a PI or
PO).
WARNING (TDM-034): [Severe] Unable to locate net in the hierarchical model.

Net: netName
EXPLANATION:
A NETDELAY was specified on a net that cannot be located in the Encounter Test
hierarchical model. This delay will be ignored and its data will not be added to the delay
model.
USER RESPONSE:
Ensure that the net name is correct. If erroneous, correct the error and rerun Delay Model
Build.
WARNING (TDM-035): [Severe] Multiple instance specifications are not supported by

Delay Model Build. Only the first instance will be acknowledged. Previous message refers to
SDF line sdfLine.
EXPLANATION:
The Standard Delay File (SDF) contained a cell instance definition that specified that the
definition applied to more than one instance. This is not supported by Delay Model Build
at this time.
USER RESPONSE:
Create a unique cell instance definition for each instance specified by copying the delay
information for each instance. Then rerun Delay Model Build.

WARNING (TDM-036): [Severe] Unable to locate cell instance in the hierarchical model.
Cell instance name: instanceName
EXPLANATION:
The Standard Delay File (SDF) specified the name of a block that cannot be located in
the Encounter Test hierarchical model. The delay data for this instance will be ignored.
USER RESPONSE:
Ensure that the instance name is correct and can be accessed in the Encounter Test
hierarchical model.
WARNING (TDM-037): A delay was specified in the SDF that was not recommended.
Cell name: cellName
From pin: fromPin
From transition: fromTrans
To pin: toPin
To transition: toTrans
EXPLANATION:
The Standard Delay File (SDF) contained a delay definition that did not appear to be
necessary according to the recommendations in the cell delay template database.
USER RESPONSE:
Verify that the delay is needed and is valid. If so, add it to the cell delay template
information for this cell (using build_celldelay_template) to eliminate this
warning.
INFO (TDM-038): Verifying interconnect delays.

EXPLANATION:
Delay Model Build is examining the interconnect delays that were specified making sure
that the points specified in these delays do connect with one another in the Encounter
Test model.
USER RESPONSE:
WARNING (TDM-039): An interconnect delay was specified in the SDF that could not be
verified against the design model.

From pin: fromPin

To pin: toPin
EXPLANATION:
An interconnect delay was specified in the Standard Delay File (SDF) that specified a
delay between two points that did not appear to be on the same net according to the
Encounter Test model. The delay will reside in the delay model as specified, but will not
be marked as a verified delay.
USER RESPONSE:
Verify that the interconnect delay is valid. If not, then remove it from the SDF. No
response is required, but it is recommended that you verify these messages to ensure
that no delay information is missing or misinterpreted.
INFO (TDM-040): Adding recommended delays to the delay model.

EXPLANATION:
Delay Model Build is beginning its analysis of the design and creating its
recommendations for delays.
USER RESPONSE:
WARNING (TDM-041): [Severe] A recommended delay was not specified in the SDF.
Cell name: cellName
From pin: fromPin
To pin: toPin
EXPLANATION:
The delay described in this message was recommended by either the cell delay template
database or by build_delaymodel itself, but was not found to have a matching
counterpart in the Standard Delay File (SDF). Delay Model Build interprets that this delay
will be needed in future processing.
USER RESPONSE:
Check if this delay is needed. If it is not, remove it from the cell delay template. You can
then update the template database using build_celldelay_template.

INFO (TDM-042): Running build_celldelay_template to generate cell delay

templates. Messages from build_celldelay_template follow below.
EXPLANATION:
Delay Model Build needs to run build_celldelay_template to generate cell delay
templates for some cells found in this design. These delay templates will be used later
when Delay Model Build is verifying the delays in the Standard Delay File (SDF) and
creating its delay recommendations. Any messages generated from
build_celldelay_template will be written below the dividing line below this
message. Note that these messages will not be included in the message summary for
Delay Model Build at the end of the run.
USER RESPONSE:
INFO (TDM-043): build_celldelay_template has completed its operation. Verifying

templates.
EXPLANATION:
The process of generating cell delay templates has completed. Delay Model Build is now
verifying that all of the templates that were requested have actually been created.
USER RESPONSE:
WARNING (TDM-044): [Severe] build_celldelay_template did not generate a

required cell delay template. No delay checking will occur for instances of this cell type.
Cell name: cellName
EXPLANATION:
build_celldelay_template did not successfully create a cell delay template for the
cell name specified. As a result, Delay Model Build will not be able to verify or create
recommendations for any delays in this cell.
USER RESPONSE:
Refer to the messages issued by build_celldelay_template to discover what the
problem was, and check the documentation of these messages for recommendations of
how to alleviate the problem.
INFO (TDM-045): Modifying delays for reduced flat model.

EXPLANATION:

Delay Model Build is now modifying the delay model so that it can match up with the
reduced Encounter Test flat model. This is necessary if you imported your design using
the reducemodel parameter.
USER RESPONSE:
ERROR (TDM-046): [Internal] Assertion failed. Program is aborting.

Description: reason
In file: fileName
Line: lineNum
EXPLANATION:
An internal program error occurred and build_delaymodel could not continue.
USER RESPONSE:
WARNING (TDM-047): Excessively large interconnect delay was specified in the SDF. This
delay may cause problems when using the delay simulator.
From Pin: fromPin

To Pin: toPin
Delay Size: delaySize
SDF Line Number: sdfLine
EXPLANATION:
An interconnect delay was specified in the Standard Delay File (SDF) that is larger than
65535 picoseconds. The Delay Simulator does not expect to encounter such a large
delay and will truncate it to 65535 picoseconds.
Having such a delay in your SDF may indicate a problem with the tool that generated the
SDF or the design itself. Such a large latency going across a single interconnect is not
reasonable for modern designs.
USER RESPONSE:
Using the provided information, investigate the source of the large delay. If you do not
intend to run the Delay Simulator, this will not be a problem and can be ignored.

Otherwise, simulation miscompares may be reported as a result of the truncation that will
occur during delay simulation.
WARNING (TDM-048): Could not correlate core delay model to current circuit topology.
Core delays have not been loaded successfully.
EXPLANATION:
The delay model being loaded could not be mapped to the current circuit. Most likely the
delay model was created against a different design that does not match the current
implementation in the current model.
USER RESPONSE:
Verify that the delay model was built against the correct version of the core circuit, and
that this version of the core is used in the current part.
Rebuild the delay model if necessary.
WARNING (TDM-049): Core delay model was rejected because the circuit topology that it
was built against appears incompatible with the current circuit.
Delay Model name: delayModelName
EXPLANATION:
A delay model was located in your COREMODELPATH that could not be used with this
design model, even though the design name matched a cell in the current circuit. This
model was rejected because the circuit topology was different than that of the current
circuit. The delays cannot be properly mapped as a result.
USER RESPONSE:
Verify that the delay model was built against the correct version of the core circuit, and
that this version of the core is used in the current part.
Rebuild the delay model if necessary.
WARNING (TDM-050): Core delay model was rejected because it was built against a
reduced flat model.
Delay Model name: delayModelName
EXPLANATION:
A delay model was located in your COREMODELPATH that could not be used with this
design model, even though the design name matched a cell in the current circuit. This
model was rejected because it was build against a design with a reduced flat model. The
delays cannot be properly mapped as a result.

USER RESPONSE:
Create a design model of the core without specifying the reducemodel parameter and
rebuild the delay model for the core.

WARNING (TDM-051): A hierarchical Macro/RLM was found which contained primitive
blocks directly inside of it, without a containing CELL block around the primitives.
Block name: blockName
EXPLANATION:
A hierarchical block with a level higher than CELL was found which contained primitive
blocks directly inside of it. Primitive blocks are expected to only reside in CELL level
hierarchical blocks. A list of the detected primitve blocks follows this message.
USER RESPONSE:
Modify the hierarchical layout of your model if you wish to be able to model delay
information accurately in these blocks. Correct these problems by wrapping the
primitives inside of these Macros/RLMs with CELL hierarchy levels. After doing this,
ensure that the necessary delay arcs exist in your SDF and match up to the new topology.
WARNING (TDM-052): [Severe] The SDF specified delays for a CELL instance that is
inside of another CELL. All delays going to, from, or through this internal CELL will be ignored.
EXPLANATION:
Delays were specified for an instance named in the SDF that is a CELL, but is not the
highest-level CELL in the hierarchy. Delays may only be specified for top-level CELL
instances.
USER RESPONSE:
Ensure that the hierarchical levels of your design model are correct and that the SDF
correlates to this model correctly. Where necessary, add or remove CELLTYPE attributes
in your models source.
INFO (TDM-053): The SDF specified delays inside a block that is modeled as a blackbox.
These delays cannot be used but will not affect timing anyway.
instance name: instanceName

EXPLANATION:
Delays were specified inside of a level of hierachy that was not modeled, but is contained
within a blackbox. The blackbox will inject Xs into the circuit, so no measures will result
from any transitions that pass through this logic. Hence the timing information is not
important in this area, and can be safely ignored.
USER RESPONSE:
WARNING (TDM-054): [Severe] The following cell output pins are flattened out to the same
net.
Cell name: cellName
Pin name: pinName
Pin name: pinName
EXPLANATION:
Delays are modeled in Encounter Test in a flattened model. The referenced two pins are
being flattened to the same net, making Encounter Test unable to distinguish between
them. The SDF will be able to distinguish these pins, and as a result, may attempt to
create different delay values associated with them. Any such delay values will be merged
by Encounter Test due to the flattening process, and can result in timings with more slack
than the amount required.
USER RESPONSE:
To eliminate this problem, modify the cell library to include a buffer feeding one of these
two pins. This will separate the pins onto two different flattened nets yet will not change
the function of the logic. If making this change is not desirable, the resulting delay model
may be used, however be aware that the timing accuracy will suffer.
WARNING (TDM-055): [Severe] The SDF specified delays to a layer that is not a
technology cell.
Block cell name: viewName
Instance name: instName
EXPLANATION:
The SDF specified delays to a block that is in the wrong layer of hierarchy. Delays may
only be specified to the highest level technology cell level of hierarchy. The SDF specified
delays to a macro boundary, RLM boundary, or higher level of hierarchy.
USER RESPONSE:

Ensure the technology library cells have been successfully imported. If it is required to
explicitly specify the level of hierarchy for our tool to work correctly, use the TYPE attribute
for the technology cells to assign a cell type of CELL or BOOK to the blocks in question.
INFO (TDM-056): Multiple test modes were specified. Checking for compatibility.
EXPLANATION:
The program is verifying whether the clock and the TIED values match in all test modes.
USER RESPONSE:
INFO (TDM-057): Test mode compatibility check successfully finished. Test mode
mode_name will be used for analysis since it had the maximum number of clocks.
EXPLANATION:
The compatibility check is complete. The referenced test mode will be used for analysis.
USER RESPONSE:
ERROR (TDM-058): Testmode compatibility check failed. Testmode mode_name conflicts

with one of the previous testmodes specified in the TESTMODE keyword.
EXPLANATION:
One or more of the clock polarity or the tied values on the PIs are not same in all of the
specified testmodes.
USER RESPONSE:
Remove the conflicting testmode name from the TESTMODE keyword and perform
build_delaymodel (read_sdf) separately for this testmode.
ERROR (TDM-059): User sequence seqName was not found in the sequence file for the
testmode modeName. Make sure the sequence name is correct and has been read in using
sequencefile keyword.
EXPLANATION:
The application could not find the named sequence in the sequence file for the testmode.
USER RESPONSE:

Make sure sequence name is specified correctly. If so, verify that the sequence was read
in correctly using the read_sequence_definition command or specifying the
INFO (TDM-061): Verifying delay information along clock tree.

EXPLANATION:
The process of verifying the validity of delay information in the clock tree has begun. The
purpose of this process is to ensure that specific delay information for rising and falling
transitions is present in the model. This process may be disabled by the user by
specifying the advanced keyword verifyclocktreedelays=no.
USER RESPONSE:
WARNING (TDM-062): [Severe] Ambiguous edge specification found for clock tree delay.
Please verify the SDF delays at this location and ensure that each edge is individually
described.
Affected clocks:clockNames
Location: pinName
Cell name: cellName

EXPLANATION:
A delay definition was found in the specified clock tree that had one or more edge
specifications which were generalized. For clock tree delays, specific information is
required about which clock edge causes the destination pin to have a transition in order
to ensure accuracy of timing constraints and other calculations that depend on SDF
information. The presence of a non-specific (rise/fall) edge specification will force
Encounter Test to handle the timing of this clock pessimistically, which may result in more
timing violations or ignored logic than what is needed. This will reduce your test coverage
for any form of timed delay test.
USER RESPONSE:
Verify the specification of the clock tree delays at the reported location and if necessary
use more specific IOPATH or INTERCONNECT delay descriptions. As an expert user, you
may also write out and modify the cell delay template database using
read_celldelay_template. Locate the cell in question and ensure that the IOPATH
delays are specified with specific edges (rising to rising, falling to falling, rising to falling,
or falling to rising). Then re-run read_sdf after updating the database to verify that the
problem has been resolved.

WARNING (TDM-063): [Severe] Ambiguous clock delays found in additional locations

which were not reported (same kind of cell already reported).
Clock: clockName
# of additional locations: numberOfLocations

EXPLANATION:
Additional TDM-062 messages related to specific locations with ambiguous clock tree
delays have been suppressed. Only one instance of a given library cell with a given pin
configuration will be reported. The number of messages suppressed due to duplication
is reported here.
USER RESPONSE:
See the RESPONSE section for the TDM-062 message.
WARNING (TDM-064): [Severe] delaymodel can not be written since no valid delays exist.
Review previous messages.
EXPLANATION:
SDF does not include cell delays or they are specified for the wrong level of the hierarchy.
USER RESPONSE:
Review the SDF and previous messages to determine why no valid delays where found.
INFO )(TDM-100) Current procedure is still running.

Process: processDescription
Time: elapsedTime elapsed, cpuTime CPU
Memory Usage: kBytes KB (mBytes MB)
Progress: percentDone% complete
EXPLANATION:
This is a status message to inform you of where Delay Model Build is spending its time
and to let you know that it is still working on the problem. You may modify the frequency
of these updates using the heartbeat parameter.
USER RESPONSE:
INFO (TDM-101): Current procedure is still running.


Progress: percentDone% complete
EXPLANATION:
USER RESPONSE:
INFO (TDM-102): Current procedure is still running.

EXPLANATION:
USER RESPONSE:
ERROR (TDM-103): Unable to write delay model to delayModelName.

EXPLANATION:
Delay Model Build was unable to open the file specified for writing.
USER RESPONSE:
Ensure that the correct permissions exist to allow this file to be written and that adequate
space exists to write the file.
WARNING (TDM-104): [Severe] Unable to open delay model: delayModelName

EXPLANATION:
The delay model specified could not be opened.
USER RESPONSE:
Ensure that the correct permissions exist to allow this file to be read.

WARNING (TDM-105): [Severe] Delay model contains evidence of corrupt data. Unable to
read delay model.
EXPLANATION:
The internal structure of this delay model has been compromised or was written by an
old version of build_delaymodel in a format that is no longer recognized.
USER RESPONSE:
Rebuild the delay model or ensure that you are using this delay model with the correct
version of the TDMaccess library.
WARNING (TDM-106): [Severe] Delay model revision revision is not supported by this
version of the delay model access code. Unable to read the delay model.
EXPLANATION:
The delay model could not be loaded because it was written with a newer version of
Delay Model Build than the code attempting to read it.
USER RESPONSE:
Ensure that you are running the correct version of Encounter Test with this delay model.
If so, your delay model may have become corrupted and will need to be rebuilt with this
version of Delay Model Build.
INFO (TDM-107): Loading delay model: delayModelName

EXPLANATION:
The delay model specified is being loaded.
USER RESPONSE:
WARNING (TDM-108): [Severe] Attempted to load a delay model created by a version of

build_delaymodel prior to R2003. This delay model cant be loaded.
EXPLANATION:
You attempted to access a delay model which was created with a previous version of
Encounter Test. This delay model format is not compatible with current versions of
Encounter Test and it must be rebuilt to be able to use it.
USER RESPONSE:
Rebuild the delay model in question with the current version of Delay Model Build and
rerun the process you were attempting if you wish to use delay information.

WARNING (TDM-109): Current delay model is not registered on global data. Correcting.
EXPLANATION:
The current delay model was not registered with Encounter Tests global data repository
and will not be recognized by the Encounter Test GUI. This can be caused by renaming
the delay model or compressing or decompressing it manually after running Delay Model
Build. This situation will be rectified by re-registering the delay model on global data
before the current process completes.
USER RESPONSE:
WARNING (TDM-110): Unable to update global data.

EXPLANATION:
An attempt was made to update the Encounter Test global data repository, but it could
not be updated. Any updates to the global data repository will be lost, though the current
process will run to completion.
USER RESPONSE:
Check the file permissions on globalData your Encounter Test workdir directory to
ensure that you have write access to this file.
INFO (TDM-111): Delay model (delayModelName) was de-registered as a valid delay

model.
EXPLANATION:
The delay model specified was determined to be unusable and as a result, it was de-
registered from Encounter Tests global data repository as a valid delay model. This is
done so that only valid delay models can be selected from the Encounter Test GUI.
USER RESPONSE:
INFO M(TDM-112):
Model audit information: auditInformation
EXPLANATION:
This delay model contains audit information from when it was created. Use this
information to verify that the correct version of the delay model was used.
USER RESPONSE:

WARNING (TDM-113): [Severe] Delay Model was created against a different design
model. It cannot be loaded. Rebuild the delay model for this circuit.
EXPLANATION:
An attempt was made to load a delay model that was built against a different Encounter
Test design model than the one being used by the current process.
The Delay Model cannot be loaded
USER RESPONSE:
Verify that the correct Delay Model was chosen and if so, rebuild the Delay Model against
the currently selected Encounter Test design model.
INFO (TDM-114): Delay Model codeType code version is codeVersion.

EXPLANATION:
This message provides code version information to be communicated to EncounterTest
development if a program error occurs.
USER RESPONSE:
WARNING (TDM-115): Attempting to load a delay model created by a different testmode.

This might result in incorrect delays across cell boundaries.
EXPLANATION:
The program attempted to access a delay model that was created using a different test
mode. The potential for differing clock definitions in the two test modes may produce
incorrect results.
USER RESPONSE:
Rebuild the delay model with the current test mode.
INFO (TDM-200): Loading cell template information.

EXPLANATION:
The cell delay template database is being loaded. The database is located in the
directory specified by the TEMPLATEPATH parameter, or if no such parameter is
specified, the Encounter Test workdir directory is used.
USER RESPONSE:


WARNING (TDM-201): [Severe] Could not readOrWrite lock the cell delay template
database.
EXPLANATION:
The cell delay template could not be locked correctly, and cannot be accessed as a
result.
USER RESPONSE:
Ensure that the file access permissions are correct for the cell delay template database
and verify that a user is not currently locking the file for exclusive access.
INFO (TDM-202): Cell template database was not found. Continuing without it.
EXPLANATION:
The cell delay template database does not currently exist. If it is needed by Delay Model
Build, it will be created.
USER RESPONSE:
If you intended to use a cell delay template database, make sure that it exists and can
be read. Otherwise, no response is required.
WARNING (TDM-203): [Severe] Delay template database has been corrupted. It will not
be used.
EXPLANATION:
The cell delay template database has become corrupted. The information contained in it
cannot be loaded and used.
USER RESPONSE:
Delete or rebuild the cell delay template database (refer to your documentation for more
details).
WARNING (TDM-204): Delay template database version version is not supported.

Database will not be used.
EXPLANATION:

The cell delay template database was written with a newer version of Encounter Test and
cannot be read. The information contained in it will not be used.
USER RESPONSE:
Delete or rebuild the cell delay template database using the proper version of Encounter
Test (refer to your documentation for more details).
INFO (TDM-205): numCellTemplates cell templates were loaded successfully.

EXPLANATION:
The cell delay template database has been successfully loaded and its cell definitions
are ready for use in the current Encounter Test model.
USER RESPONSE:
INFO (TDM-206): Cell template database has been updated successfully.

numCellTemplates cell templates are currently in the database
numVerificationRules cell verification rules are currently in the database
EXPLANATION:
The cell delay template database was updated with new definitions or replacements
were made to existing definitions. The total number of cell delay templates are displayed
as well as the total number of DELAYS_VERIFIED_FOR rules.
USER RESPONSE:
WARNING (TDM-207): [Severe] Template parse error: errorType

Line: lineNumber
Last token: lastTokenParsed
EXPLANATION:
An error occurred parsing the current template file.
USER RESPONSE:
Correct the error and try to compile the templates again.
WARNING (TDM-208): [Severe] Template parse error: Illegal character (character) on

line lineNumber.
EXPLANATION:

An unexpected character was specified in the template definition file.

USER RESPONSE:
Remove the erroneous character and compile the templates again.
WARNING (TDM-209): [Severe] Unable to access input file: fileName

EXPLANATION:
The input file could not be opened or read. It will be skipped.
USER RESPONSE:
Verify that the file exists and can be read by the current user.
INFO (TDM-210): Processing input file: fileName

EXPLANATION:
The cell delay template compiler is reading the file specified.
USER RESPONSE:
INFO (TDM-211): Rule matched with cellsMatched cells in this model.

EXPLANATION:
The rules specified in the given file matched with the specified number of cell definitions
present in the currently selected Encounter Test model.
USER RESPONSE:
WARNING (TDM-212): Template rule cannot be applied to matching cell.

Cell Name: cellName
Delay Type: delayType
From pin: fromPin
From transition: fromTransition
To pin: toPin
To transition: toTransition
Reason: pinAtFault pin not
found in Encounter Test model
EXPLANATION:
The template source file specified a cell definition that matched a cell definition in the
current Encounter Test model, however, one or more pins specified in one of the delays

in the template could not be matched with a pin on the appropriate cell in the Encounter
Test model. The delay template containing this problem will be ignored.
USER RESPONSE:
Verify that the cell matching rule is not under-specified (allowing more matches than
were intended) and that the pins specified in the delay templates are spelled correctly.
INFO (TDM-213): rulesUpdated cell rules created/updated.

EXPLANATION:
The cell rules have been created or updated in the cell delay template database as
specified.
USER RESPONSE:
INFO (TDM-214): Writing human-readable cell template database to fileName.

EXPLANATION:
You requested to print out a human-readable version of the current cell delay template
database using the printtemplates option. This data is being written to the stream
you specified.
USER RESPONSE:
WARNING (TDM-215): Multiple template definitions were found for the same cell. Definition
from the current input file was ignored.
Cell name: cellName
EXPLANATION:
More than one of your input files defines delay templates for the given cell type. This can
be a result of overly liberal use of wildcarding or a duplicated or modified copy of a given
definition.
USER RESPONSE:
Verify that the correct definition was used. No response is required
.INFO (TDM-216): numCellRules cell verification rules were loaded successfully.

EXPLANATION:

The cell delay template database has been successfully loaded and it contained one or
more DELAYS_VERIFIED_FOR rules. These rules will be applied for this session.
USER RESPONSE:
WARNING (TDM-217): [Severe] Pin specified in template definition was not found.
Pin name: pinName
Line number: lineNumber
EXPLANATION:
A pin is listed in the template definition file that does not exist in the cell in question of the
currently loaded part.
USER RESPONSE:
Ensure the pin name is correctly specified and verify that the correct design model is
being used.
INFO (TDM-218): numRules rules were not applicable to this design model.
EXPLANATION:
This message displays the number of template definitions that could not be applied to
the current design model because the cells named in the definition are not present.
USER RESPONSE:
ERROR (TDM-300): Template generator source file (fileName) was not found.
EXPLANATION:
A source file was specified (using the geninstdatafile parameter), but could not be
located by build_celldelay_template.
USER RESPONSE:
Make sure that the file name specified actually exists and can be read by the current user.
ERROR (TDM-301): Unable to create temporary directory for delay template generation.
Directory name: directoryName
EXPLANATION:
build_celldelay_template was unable to create a temporary directory for the
prototype design model.

USER RESPONSE:
Correct the file access permissions so that a directory can be created in the location
specified.
WARNING (TDM-302): [Severe] Gen Instance Data File contained a syntax error on line
lineNumber. Line was ignored and processing continues.
EXPLANATION:
The source file specified by the geninstdatafile parameter contained a syntax error.
The cell delay template requested on this erroneous line will not be generated.
USER RESPONSE:
Fix the syntax error on the line specified of the source file.
WARNING (TDM-303): [Severe] Line was too long in the Gen Instance Data File. Line
lineNumber was ignored.
EXPLANATION:
build_celldelay_template encountered a line that was more than 2000 characters
long and could not process the information on this line as a result.
USER RESPONSE:
Correct the problem and run build_celldelay_template again. Refer to
"build_celldelay_template" in the Encounter Test: Reference: Commands.
ERROR (TDM-304): Unable to run Encounter Test design import. Unable to continue.
Attempted command: command
EXPLANATION:
The Delay Template Generator attempted to create a prototype Encounter Test design
but failed. The given command line was attempted, but the command failed to execute.
USER RESPONSE:
Ensure that the executable named in the command line exists in the PATH and can be
executed and rerun build_celldelay_template. Refer to
"build_celldelay_template" in the Encounter Test: Reference: Commands.
INFO (TDM-305): Building design model containing prototype cells.

EXPLANATION:

The Delay Template Generator is in the process of creating a prototype Encounter Test
design model for the purpose of analyzing which timing arcs will be needed.
USER RESPONSE:
INFO (TDM-306): Messages from build_model are written below, indented with "==>".
EXPLANATION:
Some error messages were generated during the creation of the prototype design model.
These messages will be printed after this point, indented as indicated. These messages
most likely indicate that a serious problem has occurred during the creation of the model
and that it will be incomplete if it is created at all. When build_celldelay_template
goes to access this model later in the run, it will be report what it found to be missing.
USER RESPONSE:
Refer to "build_model" for the meaning of the various messages resulting from design
import.
ERROR (TDM-307): Encounter Test design import failed. Unable to continue.

EXPLANATION:
The creation of the prototype design model has failed because critical errors were issued
from build_model. Delay template generation cannot continue without this prototype
design model.
USER RESPONSE:
Examine the errors issued by build_model and refer to "build_model" for suggestions
on how to fix these problems.
ERROR (TDM-308): Unable to load prototype design model. Unable to continue.

EXPLANATION:
The prototype design model was created, but could not be loaded by the Delay Template
Generator.
USER RESPONSE:
Ensure that enough disk space is available to create the prototype model in your workdir
directory and that no errors have occurred during the creation of the prototype model.
INFO (TDM-309): Verifying prototype model.

EXPLANATION:
The prototype design model was created and loaded successfully. The Delay Template
Generator is in the process of checking if all of the cells it requested to be created have,
in fact, been created.
USER RESPONSE:
WARNING (TDM-310): [Severe] Prototype model did not contain a required cell instance.
EXPLANATION:
The Delay Template Generator attempted to create a prototype design model containing
the cell specified, but the resulting model did not contain this cell.
USER RESPONSE:
Check the previously reported error messages for possible explanations as to why this
may have happened. Most likely there were errors running build_model. Refer to
"build_model" for suggested solutions.
INFO (TDM-311): Setting up test mode in prototype model.

EXPLANATION:
The Delay Template Generator is creating a test mode for the prototype design model
that it just created. A test mode is necessary in order to record which pins carry clock
signals, so that SETUP, HOLD, and WIDTH delays can be determined correctly.
USER RESPONSE:
WARNING (TDM-312): [Severe] Test mode initialization failed for prototype design.
Continuing without a test mode.
EXPLANATION:
The test mode that was created for the prototype design model could not be loaded and
initialized. The Delay Template Generator will attempt continue processing without the
use of the test mode. This will mean that no clocks will be detected correctly and delay
generation will be incomplete.
USER RESPONSE:

Refer to any previous messages that could indicate what lead to this problem. If there are
no such messages, contact customer support (see Contacting Customer Service on
page 23).
WARNING (TDM-313): [Severe] Unexpected output value returned by the test generator
while creating recommended IOPATH delays.
Input pin: inPinName
Input transition: inPinTrans
Output pin: outPinName
Value from test generator: testGenVal
EXPLANATION:
While attempting to determine which IOPATH timing arcs exist in a given cell, an
unexpected value was returned by the test generator.
USER RESPONSE:
Please report all of this information to the technical support team by contacting customer
ERROR (TDM-314): No cells or cell instances were specified for delay template generation.
Nothing to do.
EXPLANATION:
No work was specified for build_celldelay_template to do.
USER RESPONSE:
Specify either the geninstdatafile parameter, the genallinstances parameter,
or one or more items for the gencellinstances or genspecificinstances
parameters. If the geninstdatafile is specified, then ensure that it is not blank.
WARNING (TDM-315): Requested delay generation for non-existent cell.

Cell name: cellName
EXPLANATION:
A cell name was specified in the gencellinstances parameter that cannot be located
in the design model.
USER RESPONSE:
Verify that the cell name was spelled properly and rerun
build_celldelay_template.

WARNING (TDM-316): Requested delay generation for non-existent block.

EXPLANATION:
A block instance name was specified in the genspecificinstances parameter that
could not be located in the design model.
USER RESPONSE:
Verify that the instance name was spelled properly and rerun
WARNING (TDM-317): Requested delay generation for an OPCG block.

EXPLANATION:
A block instance name was specified in the genspecificinstances parameter that
that exists in OPCG logic and is not observable in the testmode. No delay generation is
performed for this instance.
USER RESPONSE:
Verify that the instance name was properly spelled and rerun
ERROR (TDM-318): Circuit contains a net driving greater than 64,000 sinks, add repowering
logic and rerun. The name of the highest level net is: 'netNames'
EXPLANATION:
A net driving greater than 64,000 sinks can not be processed.
USER RESPONSE:
Add repowering logic to reduce the number of sinks per net.

22
TDR - Tester Description Rule Messages
TDR-002 through TDR-600 on page 599

TDR-601 through TDR-683 on page 612
TDR-002 through TDR-600

ERROR (TDR-002): dynamic memory allocation error
EXPLANATION:
An invalid argument has been entered as input to a command line program.
USER RESPONSE:
Specify the -h option to get a list of valid parameters for the program, then try running
again with valid parameters. Refer to the Encounter Test: Reference: Commands for
ERROR (TDR-003): invalid argument(s): -argument

EXPLANATION:
An invalid argument has been entered as input to a command line program.
USER RESPONSE:
Specify the -h option to get a list of valid parameters for the program, then try running
again with valid parameters. Refer to the Encounter Test: Reference: Commands for
INFO (TDR-050): read_tester_description_rule force option has been

specified.The existing TDR, tdr_name, is being overwritten.
EXPLANATION:
The existing TDR is replaced with the new specification and flagged as invalid.

USER RESPONSE:
ERROR (TDR-501): TDR syntax error on line: line number TDR statement
EXPLANATION:
Incorrect syntax has been specified for the TDR statement on the line specified in this
message.
USER RESPONSE:
Consult user documentation for the proper syntax for this command and correct the
syntax. Refer to "Tester Description Rule (TDR) Reference in the Encounter Test:
Guide 2: Testmodes for additional information.
ERROR (TDR-503): Cannot resolve file TDR file name.

EXPLANATION:
The input TDR file cannot be found using the TDR source file search path specified.
USER RESPONSE:
Correct either the TDR name or the TDRPATH.
ERROR (TDR-504): Cannot Open file TDR file name.

EXPLANATION:
File open failed trying to open the TDR file specified in the message.
USER RESPONSE:
Check that the file is not empty. If it is not empty, contact customer support (see
ERROR (TDR-506): The version of Encounter Test you are currently running is older than
the TDR data in the globalData file. To continue with this version of Encounter Test, you are
required to re-import the design. This may result in the loss of some data. Running the later
version of Encounter Test which produced this globalData file will allow you to continue
without the loss of any data, or the need to re-import.
EXPLANATION:
The version of Encounter Test you are currently running is older than the TDR data in the
globalData file.
USER RESPONSE:

To continue with this version of Encounter Test, you are required to re-import the design.
This may result in the loss of some data. Running the later version of Encounter Test
which produced this globalData file will allow you to continue without the loss of any data,
or the need to re-import.
PRPG_DEFINITION statement is missing the DATA TYPE specification.
(TDR-507): Cannot resolve file TDR file name. Check TDRPATH variable. This TDR is
already defined on the globalData file. Processing continues using the previously defined
TDR.
EXPLANATION:
The input TDR file cannot be found using the TDR source file search path specified, but
this TDR is already defined on the globalData file. Processing continues assuming that
the existing TDR is still valid.
USER RESPONSE:
None required, but if the default action is not adequate, correct the TDRPATH and rerun.
ERROR (TDR-508): The version of Encounter Test you are currently running is newer than
the TDR data in the globalData file. To continue with this version of Encounter Test, you are
required to re-import the design. This may result in the loss of some data. Running the
previous version of Encounter Test which produced this globalData file will allow you to
continue without the loss of any data, or the need to re-import.
EXPLANATION:
The version of Encounter Test you are currently running is newer than the TDR data in
the globalData file.
USER RESPONSE:
To continue with this version of Encounter Test, you are required to re-import the design.
This may result in the loss of some data. Running the previous version of Encounter Test
which produced this globalData file will allow you to continue without the loss of any data,
or the need to re-import.
WARNING (TDR-509): Converting TDR data version version number to version

version number. All of the TDR information on file in the globalData is found to be back-
level, and is being migrated to the current level. As a result of this migration, you will not be
able to use this globalData with earlier versions of Encounter Test.
EXPLANATION:

All of the TDR information on file in the globalData is found to be back-level, and is being
migrated to the current level. As a result of this migration, you will not be able to use this
globalData with earlier versions of the code.
USER RESPONSE:
ERROR (TDR-550): TDR_DEFINITION statement is missing the OWNER specification.

EXPLANATION:
The OWNER field is required on the TDR DEFINITION statement.
USER RESPONSE:
Modify the TDR_DEFINITION statement to include the OWNER specification. Refer to
"Tester Description Rule (TDR) Reference in the Encounter Test: Guide 2:
Testmodes for additional information.
ERROR (TDR-551): TDR_DEFINITION statement is missing the TESTER specification.

EXPLANATION:
The TESTER field is required on the TDR DEFINITION statement.
USER RESPONSE:
Modify the TDR_DEFINITION statement to include the TESTER specification. Refer to
"Tester Description Rule (TDR) Reference in the Encounter Test: Guide 2:
ERROR (TDR-552): TDR_DEFINITION statement is missing the DATE specification.

EXPLANATION:
The DATE field is required on the TDR DEFINITION statement.
USER RESPONSE:
Modify the TDR_DEFINITION statement to include the DATE specification. Refer to
"Tester Description Rule (TDR) Reference" in the Encounter Test: Guide 2:
ERROR (TDR-554): TEST_PINS statement is missing the STORED_PATTERN_DEPTH

specification.
EXPLANATION:
The STORED_PATTERN_DEPTH field is required on the TEST_PINS statement.

USER RESPONSE:
Modify the TEST_PINS statement to include the STORED_PATTERN_DEPTH
specification. Refer to "Tester Description Rule (TDR) Reference" in the Encounter
Test: Guide 2: Testmodes for additional information.
ERROR (TDR-555): TEST_PINS statement is missing the CLOCK_PINS specification.

EXPLANATION:
The CLOCK_PINS field is required on the TEST_PINS statement.
USER RESPONSE:
Modify the TEST_PINS statement to include the CLOCK_PINS specification. Refer to
ERROR (TDR-556): TEST_PINS statement is missing the SCAN_IN_PINS specification.

EXPLANATION:
The SCAN_IN_PINS field is required on the TEST_PINS statement.
USER RESPONSE:
Modify the TEST_PINS statement to include the SCAN_IN_PINS specification. Refer to
Testmodes.
ERROR (TDR-557): TEST_PINS statement is missing the

STORED_PATTERN_SCAN_DEPTH specification.
EXPLANATION:
The STORED_PATTERN_SCAN_DEPTH field is required on the TEST_PINS
statement.
USER RESPONSE:
Modify the TEST_PINS statement to include the STORED_PATTERN_SCAN_DEPTH
Test: Guide 2: Testmodes.
ERROR (TDR-560): Neither the PER_PIN nor SHARED_RESOURCE keywords were

specified on the PIN_TIMING statement.
EXPLANATION:

You must specify either PER_PIN or SHARED_RESOURCE on the PIN_TIMING

statement.
USER RESPONSE:
Modify the PIN_TIMING statement to include either PER_PIN or
SHARED_RESOURCE. Refer to "Tester Description Rule (TDR) Reference" in the
Encounter Test: Guide 2: Testmodes
ERROR (TDR-561): PIN_TIMING statement is missing the MAX_PULSES specification.

EXPLANATION:
MAX_PULSES is required on the PIN_TIMING statement.
USER RESPONSE:
Modify the PIN_TIMING statement to include MAX_PULSES. Refer to "Tester
Description Rule (TDR) Reference" in the Encounter Test: Guide 2: Testmodes
ERROR (TDR-562): PIN_TIMING statement is missing the MAX_STIMS specification.

EXPLANATION:
MAX_STIMS is required on the PIN_TIMING statement.
USER RESPONSE:
Modify the PIN_TIMING statement to include MAX_STIMS. Refer to "Tester Description
Rule (TDR) Reference" in the Encounter Test: Guide 2: Testmodes
ERROR (TDR-563): PIN_TIMING statement is missing the MAX_MEASURES specification.

EXPLANATION:
MAX_MEASURES is required on the PIN_TIMING statement.
USER RESPONSE:
Modify the PIN_TIMING statement to include MAX_MEASURES. Refer to "Tester
ERROR (TDR-564): PIN_TIMING statement is missing the MIN_CYCLE_TIME

specification.
EXPLANATION:
MIN_CYCLE_TIME is required on the PIN_TIMING statement.
USER RESPONSE:

Modify the PIN_TIMING statement to include MIN_CYLCE_TIME. Refer to "Tester

ERROR (TDR-565): PIN_TIMING statement is missing the MAX_CYCLE_TIME

specification.
EXPLANATION:
MAX_CYCLE_TIME is required on the PIN_TIMING statement.
USER RESPONSE:
Modify the PIN_TIMING statement to include MAX_CYCLE_TIME. Refer to "Tester
ERROR (TDR-566): PIN_TIMING statement is missing the MIN_PULSE_WIDTH

specification.
EXPLANATION:
MIN_PULSE_WIDTH is required on the PIN_TIMING statement.
USER RESPONSE:
Modify the PIN_TIMING statement to include MIN_PULSE_WIDTH. Refer to "Tester
ERROR (TDR-567): PIN_TIMING statement is missing the MAX_PULSE_WIDTH

specification.
EXPLANATION:
MAX_PULSE_WIDTH is required on the PIN_TIMING statement.
USER RESPONSE:
Modify the PIN_TIMING statement to include MAX_PULSE_WIDTH. Refer to "Tester
ERROR (TDR-568): PIN_TIMING statement is missing the MIN_PULSE_OFF specification.

EXPLANATION:
MIN_PULSE_OFF is required on the PIN_TIMING statement.
USER RESPONSE:
Modify the PIN_TIMING statement to include MIN_PULSE_OFF. Refer to "Tester

ERROR (TDR-569): PIN_TIMING statement is missing the LEADING_PADDING

specification.
EXPLANATION:
LEADING_PADDING is required on the PIN_TIMING statement.
USER RESPONSE:
Modify the PIN_TIMING statement to include LEADING_PADDING. Refer to "Tester
ERROR (TDR-570): PIN_TIMING statement is missing the TRAILING_PADDING

specification.
EXPLANATION:
TRAILING_PADDING is required on the PIN_TIMING statement.
USER RESPONSE:
Modify the PIN_TIMING statement to include TRAILING_PADDING. Refer to "Tester
ERROR (TDR-571): PIN_TIMING statement is missing the ACCURACY specification.

EXPLANATION:
ACCURACY is required on the PIN_TIMING statement.
USER RESPONSE:
Modify the PIN_TIMING statement to include ACCURACY. Refer to "Tester Description
Rule (TDR) Reference" in the Encounter Test: Guide 2: Testmodes
ERROR (TDR-572): PIN_TIMING statement is missing the RESOLUTION specification.

EXPLANATION:
RESOLUTION is required on the PIN_TIMING statement.
USER RESPONSE:
Modify the PIN_TIMING statement to include RESOLUTION. Refer to "Tester
ERROR (TDR-575): MEASURE statement is missing the HIGH_Z specification.

EXPLANATION:

HIGH_Z is required on the MEASURE statement.

USER RESPONSE:
Modify the MEASURE statement to include the HIGH_Z specification. Refer to "Tester
ERROR (TDR-576): PRPG_DEFINITION statement is missing the DATA SIZE specification.

EXPLANATION:
The DATA SIZE field is required on the PRPG_DEFINITION statement.
USER RESPONSE:
Modify the PRPG_DEFINITION statement to include the DATA SIZE specification. Refer
to "Tester Description Rule (TDR) Reference" in the Encounter Test: Guide 2:
Testmodes
ERROR (TDR-577): SISR_DEFINITION statement is missing the DATA SIZE specification.

EXPLANATION:
The DATA SIZE field is required on the SISR_DEFINITION statement.
USER RESPONSE:
Modify the SISR_DEFINITION statement to include the DATA SIZE specification. Refer
Testmodes
WARNING (TDR-578): The maximum number of testers (7) is exceeded. Tester name
Tester name is ignored while processing continues. This tester name is not stored in the
TDR entry.
EXPLANATION:
The number of testers appearing in the TESTER specification of the TDR_DEFINITION
has exceeded 7. This TDR name will not be stored in the TDR. TDR will be saved to the
globalData file.
USER RESPONSE:
None necessary.
ERROR (TDR-579): The TDR name TDR already exists on the globalData, and a
discrepancy has been found. By default, you are prevented from redefining the TDR. By using
the overwriteTDR option of build_testmode, you may permanently change this TDR as it
exists on the globalData.

See "build_testmode in the Encounter Test: Reference: Commands for more

information.
EXPLANATION:
The TDR name specified for this test mode matches a TDR name used by a previous
test mode, but the two TDRs do not match. The old version of the TDR is kept on the
globalData file and the new version is ignored.
USER RESPONSE:
If the new version of the TDR is required, the test mode that created that TDR will have
to be rebuilt.
ERROR (TDR-580): TEST_PINS statement is missing the FULL_FUNCTION_PIN_LIMIT

specification.
EXPLANATION:
The FULL_FUNCTION_PIN_LIMIT field is required on the TEST_PINS statement.
USER RESPONSE:
Modify the TEST_PINS statement to include the FULL_FUNCTION_PIN_LIMIT
Test: Guide 2: Testmodes
ERROR (TDR-582): SIGNATURES statement error: RUNNING MINIMUM > RUNNING

MAXIMUM.
EXPLANATION:
The RUNNING MINIMUM value must be less than the RUNNING MAXIMUM value on
the TERMINATION statement.
USER RESPONSE:
Modify the SIGNATURES statement so that RUNNING MINIMUM is less than RUNNING
MAXIMUM. Refer to "Tester Description Rule (TDR) Reference" in the Encounter Test:
Guide 2: Testmodes
ERROR (TDR-583): PRPG_DEFINITION statement error: invalid DATA SIZE. A

PRPG_DEFINITION SIZE of 32 is required.
EXPLANATION:
Encounter Test supports only a length of 32 for Tester LFSRs.
USER RESPONSE:

Modify the PRPG_DEFINITION statement so that DATA SIZE is 32. Refer to "Tester
ERROR (TDR-584): PRPG_DEFINITION statement error: invalid SCAN SIZE. A

PRPG_DEFINITION SCAN SIZE of 32 is required.
EXPLANATION:
USER RESPONSE:
Modify the PRPG_DEFINITION statement so that SCAN SIZE is 32. Refer to "Tester
ERROR (TDR-586): SISR_DEFINITION statement error: invalid DATA SIZE. A

SISR_DEFINITION DATA SIZE of 32 is required.
EXPLANATION:
USER RESPONSE:
Modify the SISR_DEFINITION statement so that DATA SIZE is 32. Refer to "Tester
ERROR (TDR-587): SISR_DEFINITION statement error: invalid SCAN SIZE. A

SISR_DEFINITION SCAN SIZE of 32 is required.
EXPLANATION:
USER RESPONSE:
Modify the SISR_DEFINITION statement so that SCAN SIZE is 32. Refer to "Tester
ERROR (TDR-588): SISR_DEFINITION statement error: invalid MISR SIZE. A MISR SIZE
of 32 is required.
EXPLANATION:
The MISR SIZE field of the SISR_DEFINITION statement must be 32. on the
TERMINATION statement.
USER RESPONSE:

Modify the SISR_DEFINITION statement so that MISR SIZE is 32. Refer to "Tester
ERROR (TDR-590): PRPG_DEFINITION statement error: invalid WEIGHT tap position

specified. WEIGHT tap positions must be between 1 and 32.
EXPLANATION:
One or more weight tap positions specified in the WEIGHTS specification of the
PRPG_DEFINITION statement is invalid. Weight tap positions must be between 1 and
32. Refer to "Tester Description Rule (TDR) Reference" in the Encounter Test: Guide
2: Testmodes
USER RESPONSE:
Modify the WEIGHTS specification so that the tap positions are between 1 and 32.
ERROR (TDR-591): Hexadecimal SEED value seed is too large on line line number. A
maximum of 8 hex characters is allowed.
EXPLANATION:
The hexadecimal seed value exceeds 8 characters. Since the maximum length of a
PRPG or SISR is 32 cells, no more than 8 hex characters is required to seed the PRPG
or SISR.
USER RESPONSE:
Modify the SEED value to contain no more than 8 hexadecimal characters. Refer to
Testmodes
ERROR (TDR-592): ERROR: invalid number of weight taps weight taps on line line
number.
EXPLANATION:
Value specified for the number of weight tap positions in the WEIGHTS specification of
the PRPG_DEFINITION statement is invalid. 7 is the maximum.
USER RESPONSE:
Modify the value specified for number of weight tap positions in the WEIGHTS
specification to be between 1 and 7. Refer to "Tester Description Rule (TDR) Reference"
in the Encounter Test: Guide 2: Testmodes
WARNING (TDR-593): WARNING: too many weight taps specified on line line number.
EXPLANATION:

The number of tap positions in the WEIGHTS specification of the PRPG_DEFINITION

statement is incorrect. It should not exceed the number specified for the number of tap
positions. The first 7 taps will be used.
USER RESPONSE:
None required. This is a warning. If use of the first 7 taps specified is not sufficient, modify
the number of weight tap positions in the WEIGHTS specification to be equal to the
specification of the number of weight tap positions in the WEIGHTS command.
WARNING (TDR-594): The DATA_PINS value on the TEST_PINS statement will be

ignored. The FULL_FUNCTION_PIN_LIMIT value will be used as the number of pins
supported by the tester.
EXPLANATION:
The DATA_PINS specification in the TEST_PINS statement is obsolete.
FULL_FUNCTION_PIN_LIMIT and PMU_CAPACITY are used as the number of pins
supported by the tester.
USER RESPONSE:
None required.
WARNING (TDR-595): DOMINANCE keyword is not allowed when TERMINATION =

NONE. The DOMINANCE keyword will be ignored.
EXPLANATION:
The DOMINANCE specification of the TERMINATION statement is meaningless when
TERMINATION is set to NONE. The DOMINANCE parameter will be ignored.
USER RESPONSE:
None required.
ERROR (TDR-596): PIN_TIMING statement is missing the

MIN_TIME_LEADING_TO_LEADING specification.
EXPLANATION:
The PIN_TIMING statement requires MIN_TIME_LEADING_TO_LEADING
USER RESPONSE:
Modify the PIN_TIMING statement to include MIN_TIME_LEADING_TO_LEADING.
Refer to "Tester Description Rule (TDR) Reference" in the Encounter Test: Guide 2:
Testmodes

ERROR (TDR-597): PIN_TIMING statement is missing the

MIN_TIME_TRAILING_TO_TRAILING specification.
EXPLANATION:
The PIN_TIMING statement requires MIN_TIME_TRAILING_TO_TRAILING
USER RESPONSE:
Modify the PIN_TIMING statement to include MIN_TIME_TRAILING_TO_TRAILING.
Testmodes
INFO (TDR-600): The keyword option of the TDR statement statement is no longer
supported. Processing continues with the keyword option ignored.
EXPLANATION:
The keyword specified for the given TDR statement is no longer supported. The keyword
is ignored.
USER RESPONSE:
None required.
TDR-601 through TDR-683

ERROR TDR-(601): PRPG_DEFINITION statement is missing the DATA TYPE
specification.
EXPLANATION:
The DATA TYPE field is required on the PRPG_DEFINITION statement.
USER RESPONSE:
Modify the PRPG_DEFINITION statement to include the DATA TYPE specification. Refer
Testmodes
ERROR (TDR-602): PRPG_DEFINITION statement is missing the DATA POLYNOMIAL

specification.
EXPLANATION:
The DATA POLYNOMIAL field is required on the PRPG_DEFINITION statement.
USER RESPONSE:

Modify the PRPG_DEFINITION statement to include the DATA POLYNOMIAL

ERROR (TDR-603): The SCAN option of the PRPG_DEFINITION statement is missing the
TYPE specification.
EXPLANATION:
The SCAN option of the PRPG_DEFINITION statement requires the TYPE specification.
USER RESPONSE:
Modify the SCAN option of PRPG_DEFINITION statement to include the TYPE
POLYNOMIAL specification.
EXPLANATION:
The SCAN option of the PRPG_DEFINITION statement requires the POLYNOMIAL
specification.
USER RESPONSE:
Modify the SCAN option of PRPG_DEFINITION statement to include the POLYNOMIAL
ERROR (TDR-605): SISR_DEFINITION statement is missing the DATA TYPE specification.

EXPLANATION:
The DATA TYPE field is required on the SISR_DEFINITION statement.
USER RESPONSE:
Modify the SISR_DEFINITION statement to include the DATA TYPE specification. Refer
Testmodes
ERROR (TDR-606): SISR_DEFINITION statement is missing the DATA POLYNOMIAL

specification.
EXPLANATION:
The DATA POLYNOMIAL field is required on the SISR_DEFINITION statement.

USER RESPONSE:
Modify the SISR_DEFINITION statement to include the DATA POLYNOMIAL
SIZE specification.
EXPLANATION:
The SCAN option of the PRPG_DEFINITION statement requires the SIZE specification.
USER RESPONSE:
Modify the SCAN option of the PRPG_DEFINITION statement to include the SIZE
ERROR (TDR-608): The SCAN option of the SISR_DEFINITION statement is missing the
TYPE specification.
EXPLANATION:
The SCAN option of the SISR_DEFINITION statement requires the TYPE specification.
USER RESPONSE:
Modify the SCAN option of the SISR_DEFINITION statement to include the TYPE
POLYNOMIAL specification.
EXPLANATION:
The SCAN option of the SISR_DEFINITION statement requires the POLYNOMIAL
specification.
USER RESPONSE:
Modify the SCAN option of the SISR_DEFINITION statement to include the
POLYNOMIAL specification. Refer to "Tester Description Rule (TDR) Reference" in the
Encounter Test: Guide 2: Testmodes
SIZE specification.

EXPLANATION:
The SCAN option of the SISR_DEFINITION statement requires the SIZE specification.
USER RESPONSE:
Modify the SCAN option of the SISR_DEFINITION statement to include the SIZE
ERROR (TDR-612): The MISR option of the SISR_DEFINITION statement is missing the
POLYNOMIAL specification
EXPLANATION:
The MISR option of the SISR_DEFINITION statement requires the POLYNOMIAL
specification.
USER RESPONSE:
Modify the MISR option of the SISR_DEFINITION statement to include POLYNOMIAL.
Testmodes
ERROR (TDR-620): The DELAY_PROCESSING statement is missing the

DELAY_CALC_MODE specification.
EXPLANATION:
The DELAY_PROCESSING statement requires DELAY_CALC_MODE.
USER RESPONSE:
Modify the DELAY_PROCESSING statement to include DELAY_CALC_MODE. Refer to
Testmodes
ERROR (TDR-621): The DELAY_PROCESSING statement is missing the TEST_TYPES

specification.
EXPLANATION:
The DELAY_PROCESSING statement requires TEST_TYPES.
USER RESPONSE:
Modify the DELAY_PROCESSING statement to include TEST_TYPES. Refer to "Tester


TESTER_CONDITIONS specification.
EXPLANATION:
The DELAY_PROCESSING statement requires TESTER_CONDITIONS.
USER RESPONSE:
Modify the DELAY_PROCESSING statement to include TESTER_CONDITIONS. Refer
Testmodes

CLOCK_GATING_HOLD specification.
EXPLANATION:
The DELAY_PROCESSING statement requires CLOCK_GATING_HOLD.
USER RESPONSE:
Modify the DELAY_PROCESSING statement to include CLOCK_GATING_HOLD. Refer
Testmodes

CLOCK_GATING_SETUP specification.
EXPLANATION:
The DELAY_PROCESSING statement requires CLOCK_GATING_SETUP.
USER RESPONSE:
Modify the DELAY_PROCESSING statement to include CLOCK_GATING_SETUP.
Testmodes

CLOCK_GATING_PULSE_WIDTH specification.
EXPLANATION:
The DELAY_PROCESSING statement requires CLOCK_GATING_PULSE_WIDTH.
USER RESPONSE:

Modify the DELAY_PROCESSING statement to include

CLOCK_GATING_PULSE_WIDTH. Refer to "Tester Description Rule (TDR) Reference"
in the Encounter Test: Guide 2: Testmodes
ERROR (TDR-626): The PIN_TIMING statement is missing the HF_MIN_PULSE_WIDTH

specification.
EXPLANATION:
The PIN_TIMING statement requires HF_MIN_PULSE_WIDTH.
USER RESPONSE:
Modify the PIN_TIMING statement to include HF_MIN_PULSE_WIDTH. Refer to "Tester
ERROR (TDR-627): The PIN_TIMING statement is missing the TERM_TIME_TO_1

specification.
EXPLANATION:
The PIN_TIMING statement requires TERM_TIME_TO_1.
USER RESPONSE:
Modify the PIN_TIMING statement to include TERM_TIME_TO_1. Refer to "Tester
ERROR (TDR-628): The PIN_TIMING statement is missing the TERM_TIME_TO_0

specification.
EXPLANATION:
The PIN_TIMING statement requires TERM_TIME_TO_0.
USER RESPONSE:
Modify the PIN_TIMING statement to include TERM_TIME_TO_0. Refer to "Tester
ERROR (TDR-629): The PIN_TIMING statement is missing the STROBE_SETUP

specification.
EXPLANATION:
The PIN_TIMING statement requires STROBE_SETUP.
USER RESPONSE:

Modify the PIN_TIMING statement to include STROBE_SETUP. Refer to "Tester

ERROR (TDR-630): The PIN_TIMING statement is missing the STROBE_HOLD

specification.
EXPLANATION:
The PIN_TIMING statement requires STROBE_HOLD.
USER RESPONSE:
Modify the PIN_TIMING statement to include STROBE_HOLD. Refer to "Tester
ERROR (TDR-631): The PIN_TIMING statement is missing the MIN_SCAN_CYCLE_TIME

specification.
EXPLANATION:
The PIN_TIMING statement requires MIN_SCAN_CYCLE_TIME.
USER RESPONSE:
Modify the PIN_TIMING statement to include MIN_SCAN_CYCLE_TIME. Refer to
Testmodes
ERROR (TDR-632): The PIN_TIMING statement is missing the

MIN_SCAN_PULSE_WIDTH specification.
EXPLANATION:
The PIN_TIMING statement requires MIN_SCAN_PULSE_WIDTH.
USER RESPONSE:
Modify the PIN_TIMING statement to include MIN_SCAN_PULSE_WIDTH. Refer to
Testmodes
ERROR (TDR-633): The PIN_TIMING statement is missing the DC_CYCLE_TIME

specification.
EXPLANATION:
The PIN_TIMING statement requires DC_CYCLE_TIME.
USER RESPONSE:

Modify the PIN_TIMING statement to include DC_CYCLE_TIME. Refer to "Tester

ERROR (TDR-634): The PIN_TIMING statement is missing the DC_PULSE_WIDTH

specification.
EXPLANATION:
The PIN_TIMING statement requires DC_PULSE_WIDTH.
USER RESPONSE:
Modify the PIN_TIMING statement to include DC_PULSE_WIDTH. Refer to "Tester
ERROR (TDR-635): The PIN_TIMING statement is missing the MIN_STIM_STABLE

specification.
EXPLANATION:
The PIN_TIMING statement requires MIN_STIM_STABLE.
USER RESPONSE:
Modify the PIN_TIMING statement to include MIN_STIM_STABLE. Refer to "Tester
ERROR (TDR-636): The DELAY_PROCESSING statement requires that the PIN_TIMING

statement be specified.
EXPLANATION:
The DELAY_PROCESSING statement requires the PIN_TIMING statement.
USER RESPONSE:
Either remove the DELAY_PROCESSING statement or include the PIN_TIMING
statement. Refer to "Tester Description Rule (TDR) Reference" in the Encounter Test:
Guide 2: Testmodes
ERROR (TDR-650): The MEASURE statement is missing or invalid.

EXPLANATION:
The MEASURE statement is a required statement and is either missing or invalid.
USER RESPONSE:

If the statement is missing, include the MEASURE statement. If the statement is invalid,
refer to the preceding messages to determine the cause of the failure. Refer to "Tester
ERROR (TDR-651): The TERMINATION statement is missing or invalid.

EXPLANATION:
The TERMINATION statement is a required statement and is either missing or invalid.
USER RESPONSE:
If the statement is missing, include the TERMINATION statement. If the statement is
invalid, refer to the preceding messages to determine the cause of the failure. Refer to
Testmodes
ERROR (TDR-652): The TEST_PINS statement is missing or invalid.

EXPLANATION:
The TEST_PINS statement is a required statement and is either missing or invalid.
USER RESPONSE:
If the statement is missing, include the TEST_PINS statement. If the statement is invalid,
refer to the preceding messages to determine the cause of the failure. Refer to "Tester
ERROR (TDR-653): The TDR_DEFINITION statement is missing or invalid.

EXPLANATION:
The TDR_DEFINITION statement is a required statement and is either missing or invalid.
USER RESPONSE:
If the statement is missing, include the TDR_DEFINITION statement. If the statement is
invalid, refer to the preceding messages to determine the cause of the failure. Refer to
Testmodes
WARNING (TDR-654): The PMU_CAPACITY specification is less than the

PARAMETRIC_MEASURE_UNITS specification in the TEST_PINS statement. Processing
continues but it is recommended that the PMU_CAPACITY specification be corrected to be
greater than or equal to PARAMETRIC_MEASURE_UNITS.
EXPLANATION:

The PMU_CAPACITY field is less than the PARAMETRIC_MEASURE_UNITS field in

the TEST_PINS statement. However, the value is accepted and processing continues.
USER RESPONSE:
No response required. However, it is recommended that the PMU_CAPACITY field in the
TDR be corrected to be greater than or equal to the PARAMETRIC_MEASURE_UNITS
field. Refer to "Tester Description Rule (TDR) Reference" in the Encounter Test: Guide
2: Testmodes
WARNING (TDR-655): The TDR specified for Scan to MISR is not compatible with the TDR
used for Diagnostics. The values specified for the Test Pins statement options for the
Diagnostics TDR must be greater than or equal to the values specified for the Scan to MISR
TDR. The option that failed is TDR Test Pins Statement Option1.
EXPLANATION:
The Diagnostics TDR field is less than the Scan to MISR TDR field for the TEST_PINS
statement. However, the value is accepted and processing continues.
USER RESPONSE:
None required, but it is recommended that the values are corrected so that the
Diagnostic TDR value is greater than or equal to the Scan to MISR value. Refer to "Tester
WARNING (TDR-666): The TDR specification has changed since it was first read by
Encounter Test. These changes will be ignored.
EXPLANATION:
The TDR specification has changed since it was first read by Encounter Test. These
changes will be ignored.
USER RESPONSE:
No response required. However, if you want these changes to be recognized by
Encounter Test, then you must first remove all testmodes that currently reference this
TDR, and then redefine a testmode that references this TDR. Be aware that any data
created by Encounter Test that is associated with a testmode is deleted when a testmode
is removed or redefined.
WARNING (TDR-669): The TDR filename has changed since it was first imported by
Encounter Test. We will ignore this new modified version, and use the version previously
imported and currently available. If it is your intention to permanently change the TDR as it is
currently defined, then you must remove each Testmode that is presently referencing this

TDR. The removal of an existing Testmode will most likely result in the loss of data.
Specifically, any and all associated committed and uncommitted tests will be removed.
EXPLANATION:
The TDR specification has changed since it was first read by Encounter Test. The details
will accompany this message. The first items listed are the checksums for original
specification and new specification, followed by TDR statements that differ. If you see
differing checksums only, that means that the two TDR specifications are equivalent with
respect to everything except comments, blank and tab characters, or whitespace in
general.
USER RESPONSE:
None required. However, if you want these changes to be recognized by Encounter Test,
then you must first remove all testmodes that currently reference this TDR, and then
redefine a testmode that references this TDR. Be aware that any data created by
Encounter Test that is associated with a testmode is deleted when a testmode is
removed or redefined.
WARNING (TDR-670): A checksum could not be obtained for the TDR TDR file name.
EXPLANATION:
The program that determines the checksum for the TDR source file has either failed to
produce a valid checksum, or was unable to deliver it to the TDR parsing program.
USER RESPONSE:
None required. However, you need to be aware that there is no checksum available for
subsequent audit procedures.
ERROR (TDR-676): TDRreadByIndex failed: tdr = TDR index.

EXPLANATION:
Unable to read TDR data from globalData for the given index.
USER RESPONSE:
WARNING (TDR-680): TDR TDR name was not deleted. Use

report_tester_description_rule to verify TDR TDR names existence.
EXPLANATION:
delete_tester_description_rule was unable to delete the specified TDR.

USER RESPONSE:
Non response required. However, you can run report_tester_description_rule
to verify that the TDR does not exist. Rerun delete_tester_description_rule
with the correct TDR name.
INFO (TDR-681): TDR TDR name has been deleted.

EXPLANATION:
The specified TDR was successfully deleted.
USER RESPONSE:
ERROR (TDR-682): TDRopenByIndex(0) failed. globalData appears to have no TDR data.

EXPLANATION:
No TDR data was found in globalData.
USER RESPONSE:
ERROR (TDR-683): TDRreadByIndex failed: index = index.

EXPLANATION:
Unable to read TDR data from globalData for the given index.
USER RESPONSE:


23
TDS - Convert Vectors To Smartscan
Messages
TDS-001 - TDS-050 on page 625
TDS-001 - TDS-050
WARNING (TDS-001): [Severe] The TDS function, function, could not find file
filename.
EXPLANATION:
TDS attempted to open the file listed but the file does not exist. Processing terminates.
USER RESPONSE:
Determine the reason (wrong project entity, testmode, path, etc.), correct and rerun.
WARNING (TDS-002): [Severe] The TDS function, function, could not write data to file
filename.
EXPLANATION:
TDS attempted to write data to the listed file but could not. Processing terminates.
USER RESPONSE:
WARNING (TDS-003): [Severe] The TDS function, function, could not read data from
file filename.
EXPLANATION:
USER RESPONSE:

TDS - Convert Vectors To Smartscan Messages
WARNING (TDS-004): [Severe] The TDS function, function could not close file
filename.
EXPLANATION:
USER RESPONSE:
WARNING (TDS-005): [Severe] The TDS function, function, could not verify the file
header in file filename.
EXPLANATION:
MacroIsolationbin file may have been created with an old version of MSV.
USER RESPONSE:
WARNING (TDS-010): [Severe] The file, filename, is not registered in globalData

and therefore cannot be accessed.
EXPLANATION:
The MacroIsolationbin MSV output file was not registered.
USER RESPONSE:
WARNING (TDS-011): [Severe] The file, filename, is not writeable, therefore the
results of this TDS run cannot be saved.
EXPLANATION:
The permission bits for this file are not set to write.
USER RESPONSE:
MTG can be rerun.

WARNING (TDS-012): [Severe] The file, filename, is not readable, therefore the results
of this TDS run cannot be saved.
EXPLANATION:
The permission bits for this file are not set to read.
USER RESPONSE:
MTG can be rerun.
ERROR (TDS-013): [Internal] The master filename for the file filename could not be
constructed.
EXPLANATION:
USER RESPONSE:
WARNING (TDS-015): [Severe] The directory, directoryname, is not writeable,

therefore the results of this TDS run cannot be saved.
EXPLANATION:
The permission bits for the directory are not set to write.
USER RESPONSE:
writable.
WARNING (TDS-016): [Severe] The directory, directoryname, is not readable,

therefore the results of this TDS run cannot be saved.
EXPLANATION:
The permission bits for the directory are not set to read.
USER RESPONSE:
readable.
ERROR (TDS-018): [Internal] The directory name could not be constructed using
PROJECT = projectname, PARTID = partid.

EXPLANATION:
USER RESPONSE:
ERROR (TDS-020): [Internal] A non-zero return code was returned from Encounter Test
(TBD) function function. TDS processing terminates.
EXPLANATION:
USER RESPONSE:
WARNING (TDS-022): [Severe] No isolation data exists in the MacroIsolationbin file.

EXPLANATION:
The MSV run failed before any isolation data could be generated. Processing terminates.
USER RESPONSE:
Create valid isolation data before re-running MTG.
WARNING (TDS-024): [Severe] No group(s) to process.

EXPLANATION:
None of the groups listed in the selectgroup option exist in the isolation data or the
isolation data did not contain any groups. Processing terminates.
USER RESPONSE:
numbers, run TDS with the printgroups option. The group numbers listed are the valid
group numbers which can be used with the selectgroup option.
WARNING (TDS-030): [Severe] ETA-Advanced and ETT-Advanced licenses are required

to run convert_vectors_to_smartscan. The program was unable to obtain both
licenses.
EXPLANATION:
The program was unable to obtain the licenses required to run
convert_vectors_to_smartscan.

USER RESPONSE:
Ensure the availability of the necessary licenses.
WARNING (TDS-040): [Severe] No TDM files were found to be processed.

EXPLANATION:
The name of a core test data file must be specified using the tdminput keyword or a
directory name containing core test data files must be specified using the tdmpath
keyword.
USER RESPONSE:
Ensure the complete path and file name of the file containing the core test data or the
directory name containing core test data files is specified on the command line.
WARNING (TDS-050): [Severe] No TDM file name was found for core corename,
algorithm algname.
EXPLANATION:
When using the tdmpath keyword, a model attribute on the core must exist which
contains the algorithm name and test data file name.
USER RESPONSE:
Check that a model attribute for this core exists and contains the correct algorithm name
and test data file name.
WARNING (TDS-052): [Severe] TDM file filename was not found for core corename,
algorithm algname.
EXPLANATION:
The tdmpath keyword combined with the test data file name from the core's model
attribute for this algorithm formed a fully qualified path name to a file which does not exist.
USER RESPONSE:
Ensure the tdmpath entered on the command line is correct and that the file containing
the test data for this core exists.
WARNING (TDS-054): [Severe] No TDM files were found for any of the cores in group
groupnum, algorithm algname
EXPLANATION:

None of the core test data files were found using the tdmpath keyword and test data file
names retrieved from the core's model attribute.
USER RESPONSE:
Check that the tdmpath is correct and that the core test data files reside in the directory.
INFO (TDS-060): Processing group groupnum, algorithm algname, TDM file(s):

filename.
EXPLANATION:
This informational message provides the group number, algorithm name, and a list of
TDM files that will be processed for this group number.
USER RESPONSE:
WARNING (TDS-062): [Severe] Unable to open or process INEXPERIMENT file

tdmfile.
EXPLANATION:
The program was unable to open a INEXPERIMENT file or was not able to process the
file data.
USER RESPONSE:
Ensure that a valid INEXPERIMENT name was entered, the file exists in the directory,
and the directory has read permission. If the file is corrupt, re-create the file using
supported processes.
WARNING (TDS-070): [Severe] No PI Vector Application Objects.

EXPLANATION:
Each core test data file should contain information about the input pins on the core. This
information does not exist in the core test data file being processed.
USER RESPONSE:
Ensure the correct core test data file name is being processed from preceding messages
and that the core test data file is of the structure neutral format.
WARNING (TDS-072): [Severe] No PO Vector Application Objects.

EXPLANATION:

Each core test data file should contain information about the output pins on the core. This
information does not exist in the core test data file being processed.
USER RESPONSE:
Ensure the correct core test data file name is being processed from preceding messages
and that the core test data file is of the structure neutral format.
WARNING (TDS-080): [Severe] The input pin pinname does not have a correspondence
pin.
EXPLANATION:
The core test data requires that a stim value be applied to this pin on the core but the pin
does not have a corresponding pin on the package that can be used to apply the value
to the core.
USER RESPONSE:
Ensure the core input pin is listed in the Macro Isolation Control file for the algorithm
WARNING (TDS-082): [Severe] The output pin pinname does not have a
correspondence pin.
EXPLANATION:
The core test data requires that this pin on the core be measured but the pin does not
have a corresponding pin on the package that can be used to measure the value.
USER RESPONSE:
Ensure the core output pin is listed in the Macro Isolation Control file for the algorithm
WARNING (TDS-090): [Severe] A suitable operation was not found for event event . This
EXPLANATION:
USER RESPONSE:
Ensure that all pins exercised in this event are in the same operation in the Macro
WARNING (TDS-092): [Severe] A suitable operation was not found for events startevent
through endevent. These events will not be processed.

EXPLANATION:
There is no operation that has correspondence for all pins exercised in these events.
USER RESPONSE:
Ensure that all pins exercised in these events are in the same operation in the Macro
WARNING (TDS-100): [Severe] Pin pinname was stimmed to Z in event event but the
pin is not a bidirectional pin.
EXPLANATION:
A pin must be defined as an input pin and an output pin in the core test data before it can
be classified as a bidirectional pin. Only bidirectional pins can be stimmed to a value of Z.
USER RESPONSE:
Ensure that the core test data was created with this pin functioning as a bidirectional pin
and that the correct test data file is being used.
WARNING (TDS-102): [Severe] A correspondence pin was not found for pin pinname
which was stimmed to Z in event event, operation operation.
EXPLANATION:
To ensure that a core pin required to be set to a Z is not driven to a value by the package,
an output correspondence pin is required. If non is found, the stim Z on this pin is ignored.
USER RESPONSE:
For core pins that are stimmed to a Z in the core test data, ensure that an operation exists
that has output correspondence for these pins.
WARNING (TDS-104): [Severe] A correspondence pin was not found for pin pinname
which was measured at Z in event event, operation operation.
EXPLANATION:
The core test data requires that this pin be measured to a Z but the pin does not have a
corresponding pin on the package that can be used to measure this value.
USER RESPONSE:
Ensure the core output pin is listed in the Macro Isolation Control file for the operation

WARNING (TDS-106): [Severe] An input correspondence pin or required pin was not found
for pin pinname in event event, operation operation.
EXPLANATION:
The core test data requires that this pin be stimmed to a value but the pin does not have
a corresponding pin on the package or a required pin with the same value that can be
used.
USER RESPONSE:
Ensure the core input pin is listed in the Macro Isolation Control file for the operation
WARNING (TDS-108): [Severe] An output correspondence pin or assumed value pin was
not found for pin pinname in event event, operation operation.
EXPLANATION:
The core test data requires that this pin be measured at a value but the pin does not have
a corresponding pin on the package or an assumed value pin with the same value that
can be used.
USER RESPONSE:
Ensure the core output pin is listed in the Macro Isolation Control file for the operation
WARNING (TDS-110): [Severe] The event type eventtype is not supported.

EXPLANATION:
Core Test supports several event types but this is not one of them.
USER RESPONSE:
Ensure that the core test data was created using only supported processes. If the event
WARNING (TDS-112): [Severe] The event type eventtype is not supported in the core's
modeinit sequence
EXPLANATION:
The core's modeinit sequence is limited to a subset of event types. The event type called
out in the message is not included in this subset.
USER RESPONSE:

scanop sequence.
EXPLANATION:
The core's scanop sequences are limited to a subset of event types. The event type
USER RESPONSE:
test data.
EXPLANATION:
SmartScan supports several event types but this is not one of them.
USER RESPONSE:
Ensure that the SmartScan data was created using only supported processes. If the
event type referred to in the message was created by a supported process, contact
WARNING (TDS-118): The scan event eventtype at event event is within a pattern
loop.
EXPLANATION:
A scan event has been added to the output after a begin loop pattern and before the end
loop pattern. Scan events within loops can severely impact test time.
USER RESPONSE:
Ensure the core pins that change states within the pattern loop do not have latch
correspondence. This may require that the correspondence requirements for these pins
in the Macro Isolation Control (MIC) file be changed to CORRESP_TYPE=PIPO.
WARNING (TDS-120): [Severe] Unable to process eventtype event event due to

missing correspondence pins.
EXPLANATION:

USER RESPONSE:
Ensure that all pins exercised in this event are in a single operation in the Macro Isolation
Control file and that all pins were successfully isolated.
WARNING (TDS-122): [Severe] One or more measure Zs were encountered in event

event. These pins will be ignored.
EXPLANATION:
The measuring of a Z value at the core pin can only be accomplished if the pin is directly
connected to a corresponding pin on the package.
USER RESPONSE:
Currently the measuring of a Z value in the core's test data is not supported.
INFO (TDS-124): Bidirectional pin pinname in Measure_PO event event cannot be

measured because it is used by SmartScan. This pin will be ignored.
EXPLANATION:
The measuring of a bidirectional pin whose input is being used be SmartScan is not
allowed. These pins include SI and CME because they are being converted to serial
data, and the parallel access pin which is a dedicated SmartScan pin.
USER RESPONSE:
No action necessary.
ERROR (TDS-130): There are no sequence definitions in the Sequence Definitions file.
EXPLANATION:
The sequence definitions file is empty.
USER RESPONSE:
Reimport your sequence definitions and rerun.
ERROR (TDS-135): There are no sequence definition objects in the TBDbin file.
EXPLANATION:
Sequence definition objects in the TBDbin file are needed to load scan registers. None
are found in this TBDbin file.
USER RESPONSE:

Rebuild the testmode, ensuring that the TBDseq file contains a scanop to load scan
registers and rerun convert_vectors_to_smartscan.
WARNING (TDS-140): [Severe] Shared pins pinname and pinname are stimmed to
EXPLANATION:
Two core pins share the same correspondence pin on the package but the core test data
requires them to be stimmed to different values.
USER RESPONSE:
WARNING (TDS-142): [Severe] Pin pinname was pulsed without shared pin pinname
being pulsed in event event.
EXPLANATION:
requires one to be pulsed without the other one being pulsed.
USER RESPONSE:
WARNING (TDS-144): [Severe] Shared pins pinname and pinname were pulsed to
EXPLANATION:
causes them to be pulsed to different values.
USER RESPONSE:
WARNING (TDS-150): [Severe] Latch correspondence in the core modeinit sequence for
EXPLANATION:
USER RESPONSE:
exercised pins in the core's modeinit sequence.

WARNING (TDS-152): [Severe] Latch correspondence in a scanop sequence for event

EXPLANATION:
scan chain at the same time the core scan chain was being loaded. This would most
USER RESPONSE:
exercised pins in the core's scanop sequences.
WARNING (TDS-154): [Severe] Latch correspondence for event type eventtype is not
supported.
EXPLANATION:
Core pins that are pulsed, scanned in, or scanned out must not have latch
corrupt core data.
USER RESPONSE:
Choose the PIPO correspondence type in the Macro Isolation Control file for all pins that
will be pulsed or used as scan in or scan out pins.
WARNING (TDS-160): [Severe] The SERIAL_PIPE_DEPTH in the SmartScan Description

file must be less than or equal to the SMARTSCAN_MAX_SERIAL_PIPE_DEPTH. The run is
terminating.
EXPLANATION:
The SMARTSCAN_MAX_SERIAL_PIPE_DEPTH value in the SmartScan Description file
is used to calculate the number of starting frames the clock controller is programmed for.
The SERIAL_PIPE_DEPTH for any deserializer or serializer must not exceed this value.
USER RESPONSE:
Refer to the SmartScan Description file used for this run. Check that the
SMARTSCAN_MAX_SERIAL_PIPE_DEPTH and the SERIAL_PIPE_DEPTH have been
entered and that the all instances of the SERIAL_PIPE_DEPTH is less than or equal to
the SMARTSCAN_MAX_SERIAL_PIPE_DEPTH.
WARNING (TDS-170): The scan length of a stim or measure register in the TDM input file
is zero.

EXPLANATION:
The core test data file did not have a valid scan length for one of its registers.
USER RESPONSE:
Ensure that the core test data was created using only supported processes. If the core
test data was created by a supported process, contact customer support (see
WARNING (TDS-180): No scan loads were found within the core boundary for register
regnum.
EXPLANATION:
None of the stim register latch names listed in the core test data file for this register were
found within the core boundary.
USER RESPONSE:
If the core is a white box core and the macro tests were created using a supported
process, contact customer support (see Contacting Customer Service on page 23).
WARNING (TDS-182): No measure latches were found within the core boundary for register
regnum.
EXPLANATION:
None of the measure register latch names listed in the core test data file for this register
were found within the core boundary.
USER RESPONSE:
If the core is a white box core and the macro tests were created using a supported
process, contact customer support (see Contacting Customer Service on page 23).
WARNING (TDS-184): [Severe] Latch latchname cannot be loaded directly through the
package register in TDM file event event. The data for this latch will be ignored. Re-generate
the core test data using the normal load option.
EXPLANATION:
In order to load a core's skewed can load, it must be the first latch in a package stim
register.
USER RESPONSE:
Direct ATPG to create test data using normal loads.

WARNING (TDS-190): [Severe] A skewed scan load event has been created that
EXPLANATION:
In a skewed scan load event, the master and slave latches may not end up containing
the same data as they do in non-skewed events. Skewing apply data designed for a non-
skewed environment can lead to erroneous test results.
USER RESPONSE:
WARNING (TDS-192): [Severe] A Skewed_Scan_Unload event has been created that

EXPLANATION:
In a Skewed_Scan_Unload event, data is transferred from the master to the slave latch
before scanning out the data. Skewing expect data that is designed for non- skewed
environment can lead to erroneous test results.
USER RESPONSE:
WARNING (TDS-200): [Severe] The SmartScan mode initialization sequence named

seqname was not found in the TBD sequence file. Processing terminates.
EXPLANATION:
In order to convert vectors to SmartScan data, a custom mode initialization sequence
must be provided. This sequence must reside in the TBDseq.<testmode> file and the
name of the sequence must be supplied to the program. The named sequence was not
found in the TBD sequence file.
USER RESPONSE:
Ensure the correct name of the SmartScan mode initialization sequence has been
provided to the program and the sequence has been included in the
TBDseq.<testmode> file.
WARNING (TDS-210): [Severe] Unable to open or process the input TBDbin file with the
name filename.

EXPLANATION:
The program was unable to open the input file filename or was not able to process the
file data.
USER RESPONSE:
Ensure the TBDbin file with the testmode and input experiment names exists in the
directory, and the directory has read permissions. If the file is corrupt, re-create the file
using supported processes.
WARNING (TDS-214): [Severe] No deserializer registers were found on this part.

SmartScan designs without serializers must have a minimum of one deserializer register.
EXPLANATION:
When processing parts without serializers, there must be at least one deserializer.
USER RESPONSE:
Create a SmartScan description file and add deserializer and serializer mapping
information. This file is normally created by write_et_atpg.
WARNING (TDS-215): The order of the events in the scan sequence has been changed to
support SmartScan designs without deserializer update latches.
EXPLANATION:
When deserializer update latches are not present, the scan sequence events are
changed from Stim_PI/Measure_PO/Pulse to Stim_PI/Pulse/Measure_PO.
USER RESPONSE:
If update latches have been intentionally omitted, no action is necessary.
WARNING (TDS-216): [Severe] The maximum number of CME pipeline latches, according
to build_testmode, is cme_pipe_depth but the smartscan description file states the
number of pre-deserializer CME pipeline latches is deserializer_pipe_depth. Check
these values for correctness. The process terminates.
EXPLANATION:
The maximum number of CME pipeline latches must be equal to or greater than the
number specified in the smartscan description file using the
PRE_DESERIALIZER_PIPE_DEPTH statement.
USER RESPONSE:

Correct the number of CME pipeline latches in the build_testmode assign file or the
PRE_DESERIALIZER_PIPE_DEPTH statement in the smartscan description file.
WARNING (TDS-218): A pipeline latch has an expect value other than 'X' at event
event_ID but cannot be measured because it does not feed a serializer latch. The
measurement on this pipeline latch is ignored.
EXPLANATION:
Pipeline latches placed after the serializer cannot be measured. If a measure other than
'X' is expected, the value is lost.
USER RESPONSE:
Add pipeline latches that appear after the serializer to the ignore measure file and
regenerate the tests. Rerun convert_vectors_to_smartscan.
WARNING (TDS-219): The keyword maskloadcorruptspipe has been set indicating the
serializer scan out pipeline latches will be corrupted when loading the mask register.
Therefore, valid data in these pipeline latches will not be measured.
EXPLANATION:
The keyword maskloadcorruptspipe has been set to yes indicating the scan out
pipeline latches will be corrupted when loading the mask register through the
deserializer. Valid data has been detected in these latches but no measurements on the
data will be performed.
USER RESPONSE:
If the data loss is acceptable, no action is required and this message can be ignored. To
keep the measures on these pipeline latches, the clock to the latches must be gated off
during the mask load.
INFO (TDS-220): Stim PI event event_id sets TI pin pin_name to a stim_val1 value.
This conflicts with the SmartScan modeinit value of stim_val2. The stim value on this
pin will be changed to its SmartScan modeinit value when converting vectors.
EXPLANATION:
Certain SmartScan mode initialization pin values must not change during the test in
order to keep the part in the SmartScan mode of operation. These pins, if found in a
Stim_PI event, will be set back to their SmartScan mode initialization value.
USER RESPONSE:
No user response is necessary.

WARNING (TDS-222): Stim PI event event_id sets pin pin_name to a stim_val

value. This conflicts with the SmartScan modeinit value of stim_val2. This may result in
miscompares after converting the vectors.
EXPLANATION:
Certain pins in a Stim_PI event can change from their SmartScan mode initialization
value without affecting the test. If found in a Stim_PI event, these pins will not be set
back to their SmartScan mode initialization value.
USER RESPONSE:
If miscompares are detected in the SmartScan patterns during simulation, it is possible
that one of these pins could be at fault.
WARNING (TDS-224): [Severe] A Load_SR or UnLoad_SR event has been encountered

in the INEXPERIMENT TBDbin file. These events cannot be processed therefore the run
terminates.
EXPLANATION:
Load_SR and UnLoad_SR events cannot be processed as input events by this program.
These are only output event types.
USER RESPONSE:
The INEXPERIMENT value is most likely the cause of this error. Correct the
INEXPERIMENT and rerun convert_vectors_to_smartscan
WARNING (TDS-230): [Severe] This program supports test section types of logic ,scan,
iddq and path. The current test section type is not supported.
EXPLANATION:
Test section types logic and scan have specific pattern conversion methods. No other
test types are supported at this time.
USER RESPONSE:
Create patterns for test section type logic or scan only and rerun
WARNING (TDS-232): [Severe] One or more primary input pins designated as scan in pins
were stimmed during the test patterns. These pins can only be used for scanning and will be
ignored during the conversion process.
EXPLANATION:

During test section types logic and path, Stim_PI events should not include stims on
scan in pins as these are used for scanning only.
USER RESPONSE:
Create a linehold file with a HOLD statement for each scan in pin (ex: Hold Pin si1 = X)
and regenerate the logic or path tests. Rerun convert_vectors_to_smartscan.
WARNING (TDS-234): [Severe] This INEXPERIMENT contains more than one test section
type. Only one test section type can be converted at a time. The run terminates.
EXPLANATION:
Test section types logic, scan, iddq and path each have specific pattern conversion
methods. The combining of multiple test section types is not supported at this time.
USER RESPONSE:
Create patterns for either test section type 'logic' or 'scan' and rerun
WARNING (TDS-236): [Severe] This program only supports the test section type of 'scan'
if there are no serial or parallel pipelines. The run terminates.
EXPLANATION:
A test section type of 'scan' must not have serial pipelines before the deserializer scan
in or after the serializer scan out. It must also not have pre-deserializer or post-serializer
pipelines.
USER RESPONSE:
Bypass the serial and parallel pipelines and re-create patterns for test section type 'scan'
and rerun convert_vectors_to_smartscan.
WARNING (TDS-238): [Severe] A scan test section type cannot be combined with a test
section of a different type unless the scan test section has been created using the
format=simplified keyword. The run terminates.
EXPLANATION:
If a test section type of scan and a different test section type such as logic exists in the
same experiment, the scan test section must have been created using the
format=simplified keyword.
USER RESPONSE:
Recreate the scan test section using the format=simplified keyword and rerun

WARNING (TDS-240): A miscompare in Measure_PO event event_id, pin pin_name

was detected. Expected expect_val, measured meas_val.
EXPLANATION:
When running with debug=verify, a miscompare occurred on a measure pin.
USER RESPONSE:
Check for any TDS warning messages that could indicate a reason for the miscompare.
If none are found, it could be a problem with the pattern conversion process. In this case,
WARNING (TDS-242): A miscompare in Scan_Pipeline_State event event_id, pin

pin_name was detected. Expected expect_val, measured meas_val.
EXPLANATION:
When running with debug=verify, a miscompare occurred on a pipeline latch.
USER RESPONSE:
WARNING (TDS-244): A miscompare in Measure_Scan_Data event event_id

(UnLoad_SR pattern unload_event_id, sequence sequence_name, cycle cycle),
'pin pin_name' was detected. Expected expect_val, measured meas_val.
EXPLANATION:
When running debug=verify, a miscompare occurred on a scan out pin.
USER RESPONSE:
WARNING (TDS-245): A miscompare in Internal_Scan_Load event event_id,

'correlated latch latch_name was detected. Expected expect_val, measured
meas_val.
EXPLANATION:
When running debug=verify, a miscompare occurred at a channel latch after loading
the channels using the Load_SR event.

USER RESPONSE:
contact Customer Support (see Contacting Customer Service on page 23).
WARNING (TDS-246): A miscompare in Internal_Scan_Load event event_id, latch

latch_name was detected. Expected expect_val, measured meas_val.
EXPLANATION:
When running debug=verify, a miscompare occurred at a channel latch after loading
the channels using the Load_SR event.
USER RESPONSE:
WARNING (TDS-247): A miscompare in Load_OPCG_Controls event event_id, latch

latch_name was detected. Expected expect_val, measured meas_val.
EXPLANATION:
When running debug=verify, a miscompare occurred at a Load_OPCG_Controls
event.
USER RESPONSE:
contact Customer Support (see Contacting Customer Service on page 23).
WARNING (TDS-248): A miscompare in Diagnostic_Scan_Unload event event_id,

latch latch_name was detected. Expected expect_val, measured meas_val.
EXPLANATION:
When running debug=verify, a miscompare occurred at a channel latch after a parallel
load.
USER RESPONSE:

WARNING (TDS-249): A miscompare in Load_Channel_Masks event event_id, 'latch

latch_name' was detected. Expected expect_val, measured meas_val.
EXPLANATION:
When running debug=verify, a miscompare occurred at a Load_Channel_Masks
event.
USER RESPONSE:
INFO (TDS-250): Starting verification of the SmartScan output TBDbin file.

EXPLANATION:
This message is displayed if using the debug=verify keyword.
USER RESPONSE:
No user response necessary.
INFO (TDS-252): Verifying sequence sequence_odometer.

EXPLANATION:
This message prints the sequence odometer reading when verifying the output TBDbin
file.
USER RESPONSE:
Warning (TDS-254): [Severe] When processing SetScanData cycle cycle, unable to find
pin pinname in scan operation scan_operation.
EXPLANATION:
The pin returned from TBDgetFirstStim can appear in more than one scanop. The
program was unable to find this pin in the scanop being processed.
USER RESPONSE:
This is most likely due to an error in the FULLSCAN test mode sequence data, the target
test mode sequence data or the SmartScan definition file. Check these files for any
errors, rebuild the test modes and rerun convert_vectors_to_smartscan.

Warning (TDS-256): [Severe] When processing MeasureScanData cycle cycle, unable

to find pin pinname in scan operation scan_operation.
EXPLANATION:
The node returned from TBDgetFirstMeasure can appear in more than one scanop. The
program was unable to find this pin name in the scanop being processed.
USER RESPONSE:
This is most likely due to an error in the FULLSCAN test mode sequence data, the target
test mode sequence data or the SmartScan definition file. Check these files for any
errors, rebuild the test modes and rerun convert_vectors_to_smartscan.
INFO (TDS-259): Starting expansion of the SmartScan output TBDbin file.

EXPLANATION:
This message is displayed if using the debug=expandbin keyword.
USER RESPONSE:
INFO (TDS-262): Expanding sequence sequence_odometer.

EXPLANATION:
This message prints the sequence odometer reading when expanding the output TBDbin
file.
USER RESPONSE:
WARNING (TDS-270): [Severe] A Parallel Access pin that switches the part to the
SmartScan configuration was not found.
EXPLANATION:
A Parallel Access pin is used to switch the part to the SmartScan configuration. The
converted patterns may not work without this pin. Convert_vectors_to_smartscan
looks for a primary input pin or pseudo primary input pin name with the letters PAR
followed by the letters ACCESS. The name is case insensitive.
USER RESPONSE:
Ensure the Parallel Access pin's name consists of the characters PAR followed by the
characters ACCESS (ex: SMARTSCAN_PAR_ACCESS). If not, change the pin name
and re-build the part.

WARNING (TDS-280): [Severe] The mode initialization sequence was not found in the
TBD sequence file. This sequence type is needed because a sequence name was not
provided using the testsequence keyword. Processing terminates.
EXPLANATION:
If the testsequence keyword is not provided or the keyword is set to none, the target
mode initialization sequence will be used. This sequence was not found in the
TBDseq.<testmode> file. This sequence must be provided in order to continue.
USER RESPONSE:
If intending to use the target mode initialization sequence, rebuild the test mode and
rerun convert_vectors_to_smartscan.
WARNING (TDS-282): [Severe] The SmartScan mode initialization specified by the

testsequence keyword named seqname was not found in the TBD sequence file.
EXPLANATION:
The SmartScan mode initialization sequence provided with the testsequence keyword
was not found in the TBDseq.<testmode> file.
USER RESPONSE:
Ensure the SmartScan mode initialization sequence was added to the
TBDseq.<testmode> file using the sequencefile keyword and that the
testsequence keyword contains the correct sequence name. Make any updates and
rerun convert_vectors_to_smartscan.
WARNING (TDS-284): A Stim_PPI event has been added to the end of the modeinit
sequence setting the parallel access pin to its non-stability state. If this is not a Serial-Only
SmartScan part, setting the parallel access PPI pin to its non-stability state may not be
sufficient to place the part in the SmartScan configuration.
EXPLANATION:
When a custom SmartScan mode initialization sequence is not provided through the
testsequence keyword, convert_vectors_to_smartscan will create one using
the target modeinit sequence and the Parallel Access PI or PPI. Using just the PPI may
not work if the part is not Serial-Only.
USER RESPONSE:
Create a custom SmartScan mode initialization sequence where the PPI is set to its non-
stability state. Add this sequence to the TBD sequence file using sequencefile
keyword and rerun convert_vectors_to_smartscan.

WARNING (TDS-286): [Severe] A Parallel Access PI or PPI that switches the part to the
SmartScan configuration was not found. A Parallel Access pin is needed since no
testsequence was provided. Processing terminates.
EXPLANATION:
If the testsequence keyword is not provided or the keyword is set to none, the target
mode initialization sequence will be used. In addition to using this sequence, any Parallel
Access pins must be set to their non-stability state in order to switch to the SmartScan
configuration. To do this, the PI and PPI pin names are scanned for the characters PAR
followed by the characters ACCESS (ex: SMARTSCAN_PARALLEL_ACCESS). If found,
a pattern will be added to the mode initialization sequence setting this pin to its non-
stability state.
USER RESPONSE:
Ensure the Parallel Access pin exists and the name consists of the characters PAR
followed by the characters ACCESS (ex: SMARTSCAN_PARALLEL_ACCESS). If not,
change the Parallel Access pin name and re-build the part.
WARNING (TDS-288): [Severe] A Parallel Access PI or PPI that switches the part to the
SmartScan configuration was not found. A Parallel Access pin is needed since the test
sequence being used is type modeinit. Processing terminates.
EXPLANATION:
When using the modeinit sequence, any Parallel Access pins must be set to their non-
stability state in order to switch to the SmartScan configuration. To do this, the PI and PPI
pin names are scanned for the characters PAR followed by the characters ACCESS (ex:
SMARTSCAN_PARALLEL_ACCESS). If found, a pattern will be added to the mode
initialization sequence setting this pin to its non-stability state.
USER RESPONSE:
Ensure the Parallel Access pin exists and the name consists of the characters PAR
followed by the characters ACCESS (ex: SMARTSCAN_PARALLEL_ACCESS). If not,
change the Parallel Access pin name and re-build the part.
INFO (TDS-290): The sequence name sequence_name of sequence type

sequence_type will be used for the SmartScan mode initialization sequence.
EXPLANATION:
Based on the testsequence keyword, this sequence name and sequence type will be
used as the SmartScan mode initialization sequence. If the sequence type is modeinit,
the Parallel Access pin will automatically be added to the end of the sequence to switch
the part to the SmartScan configuration.

USER RESPONSE:
If this sequence name is not the one you expected, specify the correct test sequence
name using the testsequence keyword and rerun
WARNING (TDS-300): [Severe] Based on the testsequence name entered, its

sequence type of sequence_type is not supported. Only smartscan_modeinit,
modeinit and test sequence types are supported. Processing terminates.
EXPLANATION:
Based on the testsequence name provided, the sequence type with this sequence
name is not supported. Only sequence types of smartscan_modeinit, modeinit and
test are supported.
USER RESPONSE:
Ensure the test sequence with the name entered is of the proper type and rerun
INFO (TDS-400): Message number TDS-message_number has been printed

message_limit times and will no longer be printed or recorded for the rest of this run.
EXPLANATION:
Each message has a limit to the number of times it will be printed during the run. The
default is 1000 times. When this limit is reached, a TDS-400 message wil be printed
identifying the message number and the number of times it has been printed.
USER RESPONSE:
The number of times a message will be printed can be overridden by the messagecount
keyword. For example: messagecount=90=100,92=100 will limit the number of times
messages TDS-090 and TDS-092 are printed to 100.
WARNING (TDS-402): [Severe] Attempt to register experiment experiment_name on

the globalData file failed.
EXPLANATION:
There is a problem with the globalData file such that updates to the file are not possible.
The reason for the failure cannot be determined. Processing terminates.
USER RESPONSE:
Check TFW messages to determine the nature of the problem and take the appropriate
corrective action.

WARNING (TDS-404): [Severe] Attempt to register a dependency of

experiment|file against the mode|experiment on the globalData file failed.
EXPLANATION:
The reason for the failure cannot be determined. Processing terminates.
USER RESPONSE:
corrective action.
WARNING (TDS-406): [Severe] Attempt to register file file_name on the globalData file
failed.
EXPLANATION:
The file could not be registered on the globalData file for this test mode.
USER RESPONSE:
Determine why the file could not be registered.
WARNING (TDS-408): [Severe] Attempt to save file file_name in the globalData file
failed.
EXPLANATION:
The file could not be saved on the globalData file for this test mode.
USER RESPONSE:
Determine why the file could not be saved. Check write permissions and disk space.
ERROR (TDS-410): [Internal] Message number message_number has an incorrect

number of arguments.
EXPLANATION:
USER RESPONSE:
ERROR (TDS-420): [Internal] Error building generic message number

message_number.
EXPLANATION:


USER RESPONSE:
INFO (TDS-430): Message number TDS-message_number was printed

message_limit times out of a total of message_total.
EXPLANATION:
This message contains the number of times a message was printed out of a total number
USER RESPONSE:
Information only. No response required.
ERROR (TDS-500): [Internal] Unable to initialize TBD in preparation to open TDM file
tdmfile.
EXPLANATION:
USER RESPONSE:
ERROR (TDS-502): [Internal] Unable to initialize TBD with no model.

EXPLANATION:
USER RESPONSE:
ERROR (TDS-504): [Internal] Unable to open merged TDM file tdmfile.

EXPLANATION:
USER RESPONSE:
ERROR (TDS-510): [Internal] Invalid node ID (nodeid) for macro pin

macropinnodeid

EXPLANATION:
USER RESPONSE:
ERROR (TDS-512): [Internal] Invalid node ID (nodeid) for correspondence pin

corrpinnodeid.
EXPLANATION:
USER RESPONSE:
ERROR (TDS-520): [Internal] Core scanop sequence number seqnum was not found.
Unable to continue.
EXPLANATION:
USER RESPONSE:
ERROR (TDS-530): [Internal] Invalid subgroup subgroup.

EXPLANATION:
USER RESPONSE:
ERROR (TDS-535): [Internal] The TDS function, function_name, was called with an invalid
callback address. Processing terminates.
EXPLANATION:
USER RESPONSE:

ERROR (TDS-536): [Internal] The TDS function, function_name, reached the

maximum number of callbacks allowed. Processing terminates.
EXPLANATION:
USER RESPONSE:
ERROR (TDS-540): [Internal] The maximum number of LATCH save levels has been
exceeded.
EXPLANATION:
USER RESPONSE:
ERROR (TDS-550): [Internal] Node nodeid is not a valid scannable latch node. [end
TDS_550] \n
EXPLANATION:
USER RESPONSE:
ERROR (TDS-552): [Internal] Node node is not a valid measurable latch node.
EXPLANATION:
USER RESPONSE:
ERROR (TDS-560): [Internal] The maximum number of PI save levels has been exceeded.
EXPLANATION:
USER RESPONSE:

ERROR (TDS-562): [Internal] Invalid node nodeid passed to get PI bit position.
EXPLANATION:
USER RESPONSE:
ERROR (TDS-570): [Internal] The maximum number of PO save levels has been
exceeded.
EXPLANATION:
USER RESPONSE:
ERROR (TDS-580): [Internal] The core modeinit pin pinname has a required value that is
not the same as the value in the TDM file.
EXPLANATION:
USER RESPONSE:
ERROR (TDS-650): [Internal] The TDS function, function_name, was called with an
invalid latch node node_id. Processing terminates.
EXPLANATION:
USER RESPONSE:
Contact Customer Services.Contact customer support (see Contacting Customer
ERROR (TDS-651): [Internal] The TDS function, function_name was called with an
invalid scan in node scan_in_node_id. Processing terminates.
EXPLANATION:


USER RESPONSE:
ERROR (TDS-652): [Internal] The TDS function, function_name, was called with an
invalid skewed scan in node skewed_scan_in_node_id. Processing terminates.
EXPLANATION:
USER RESPONSE:
ERROR (TDS-653): [Internal] The TDS function, function_name, was called with a
skewed scan in node skewed_scan_in_node_id but the node is not flagged as a having
a skewed stim latch. Processing terminates.
EXPLANATION:
USER RESPONSE:
ERROR (TDS-660): [Internal] The function function_name has returned node 0 as the
deserializer latch node for scan in node scanin_node.
EXPLANATION:
USER RESPONSE:
ERROR (TDS-662): [Internal] The function function_name has returned node 0 as the
serializer latch node for scan out node scanout_node.
EXPLANATION:
USER RESPONSE:

ERROR (TDS-664): [Internal] The function function_name has returned a load node
of load_node for deserializer latch node des_node. This node is not a PI.
EXPLANATION:
USER RESPONSE:
ERROR (TDS-666): [Internal] The function function_name has returned an unload

node of unload_node for deserializer latch node ser_node. This node is not a PO.
EXPLANATION:
USER RESPONSE:
ERROR (TDS-670): [Internal] The TDS function, function_name, was called with node
node_id but this node does not yet have a value associated with it. Processing terminates.
EXPLANATION:
USER RESPONSE:


24
TDY - Delay Simulation Messages
TDY-001 through TDY-071 on page 659
TDY-001 through TDY-071

WARNING (TDY-001): Unrecognized simulation function
EXPLANATION:
A simulation function was not recognized. This particular block will be treated as an X
source. A logic primitive not supported by dynamic fault test generation was specified.
USER RESPONSE:
Ensure that logic primitives used are supported by Encounter Test. Rerun the part.
WARNING (TDY-002): Unsupported fault type

EXPLANATION:
A fault type not supported by test pattern generation was encountered. This particular
fault will be skipped. Test pattern generation does not handle non-DC faults.
USER RESPONSE:
Ensure that fault types are supported by Encounter Test. Rerun the part.
WARNING (TDY-003): Unknown termination value

EXPLANATION:
An unknown termination value for three-state devices was encountered.
USER RESPONSE:
Ensure that the termination value specified for three-state devices is specified correctly
and the rerun.

WARNING (TDY-004): Unable to get design context

EXPLANATION:
A call related to the logic model failed.
USER RESPONSE:
Ensure that the Encounter Test logic model files exist.
WARNING (TDY-005): Unable to load logic model

EXPLANATION:
The test pattern generator was unable to load the logic model.
USER RESPONSE:
Ensure that the Encounter Test logic model files exist. If not, import the part and continue
processing.
WARNING (TDY-006): Unable to set the test mode

EXPLANATION:
The test pattern generator was unable to set the test mode.
USER RESPONSE:
Ensure that the test mode has been defined and rerun.
WARNING (TDY-007): Unable to load model access methods

EXPLANATION:
The model access methods could not be loaded.
USER RESPONSE:
Ensure that the machine has sufficient memory and rerun.
WARNING (TDY-008): Unable to create buffer to hold model stats

EXPLANATION:
Memory allocation error.
USER RESPONSE:
Ensure that the workstation has sufficient memory and rerun.

WARNING (TDY-009): Unable to register the experiment

EXPLANATION:
The experiment name is not recognized.
USER RESPONSE:
Ensure that the experiment name is specified correctly and rerun.
WARNING (TDY-010): Unable to setup dependency

EXPLANATION:
The test pattern generator was not able to set one of the global dependencies.
USER RESPONSE:
Ensure that the experiment name is specified correctly and rerun.
WARNING (TDY-011): Unable to save global data

EXPLANATION:
The test pattern generator was not able to save the global data.
USER RESPONSE:
Ensure that you have write access permission to the directory or that you have sufficient
file space and rerun.
WARNING (TDY-012): Unable to access the fault model

EXPLANATION:
The test pattern generator was not able to access the fault model.
USER RESPONSE:
Ensure that the fault model file exists and rerun.
ERROR (TDY-013): [Internal] An internal program limit was exceeded

EXPLANATION:
An internal test pattern generator limit was exceeded.
USER RESPONSE:
assistance.

ERROR (TDY-014): [Internal] An internal program error occurred

EXPLANATION:
An error internal to the test pattern generator has occurred.
USER RESPONSE:
Contact customer support (see Contacting Customer Service on page 23). for
assistance.

EXPLANATION:
USER RESPONSE:
assistance.
WARNING (TDY-016): Error while accessing TBD

EXPLANATION:
The test pattern generator could not access the Encounter Test Data repository (TBD).
USER RESPONSE:
assistance.
WARNING (TDY-017): Error while accessing simulator

EXPLANATION:
The simulator could not be accessed.
USER RESPONSE:
assistance.

EXPLANATION:
An error internal to the test pattern generator occurred.
USER RESPONSE:

assistance.

EXPLANATION:
A limit internal to the test pattern generator was exceeded.
USER RESPONSE:
assistance.

EXPLANATION:
A limit internal to the test pattern generator was exceeded.
USER RESPONSE:
assistance.
WARNING (TDY-021): Memory allocation error

EXPLANATION:
The test pattern generator failed to allocate the required memory. Try killing unnecessary
processes or running the program on a machine with more memory.
USER RESPONSE:
assistance.
WARNING (TDY-022): Illegal memory access

EXPLANATION:
A memory segmentation violation occurred.
USER RESPONSE:
assistance.
WARNING (TDY-023): Page space exceeded

EXPLANATION:
The machine ran out of paging space.
USER RESPONSE:
Increase paging space and rerun.
WARNING (TDY-024): Error while specifying globalterm

EXPLANATION:
An illegal value for the globalterm was specified.
USER RESPONSE:
Ensure that the correct value is specified and rerun.

EXPLANATION:
USER RESPONSE:
assistance.

EXPLANATION:
USER RESPONSE:
assistance.
WARNING (TDY-027): Error reading/writing parameter bank

EXPLANATION:
Error while accessing test generation parameters.
USER RESPONSE:
assistance.

WARNING (TDY-028): Design has number asynchronous loop(s)

EXPLANATION:
The design has asynchronous loops. This may result in inaccurate results.
USER RESPONSE:
Ensure that the existence of asynchronous loops does not impact the desired test
generation results.
WARNING (TDY-029): Unable to retrieve line hold information

EXPLANATION:
The test pattern generator failed to retrieve line hold information.
USER RESPONSE:
Ensure that a linehold file exists or that it is created correctly and rerun. Refer to
Linehold File in the Automatic Test Pattern Generation User Guide for additional
information.
INFO (TDY-030): FaultID: number was tested

EXPLANATION:
Informational message indicating that the test pattern generator was able to generate a
test on a fault.
USER RESPONSE:
INFO (TDY-031): FaultID: number was untestable

EXPLANATION:
Informational message indicating that a specific fault was untestable.
USER RESPONSE:
INFO (TDY-032): FaultID: number was aborted

EXPLANATION:
Informational message indicated that a specific fault was aborted.
USER RESPONSE:

To reduce the count of aborted faults, increase the effort parameter.
INFO (TDY-033): FaultID: number was possibly tested

EXPLANATION:
The test pattern generator generated a test for a fault but was marked as possibly
detected by the simulator.
USER RESPONSE:
Ensure that this result is correct for the design.
INFO (TDY-034): FaultID: number was sim rejected

EXPLANATION:
The test pattern generator generated a test for a fault but was not detected by the
simulator.
USER RESPONSE:
If too many of such messages occur, contact customer support (see Contacting
WARNING (TDY-035): Unable to generate random patterns

EXPLANATION:
The test pattern generator was not able to generate pseudo-random patterns for the
design due to some internal error.
USER RESPONSE:
Rebuild the logic model and rerun.
INFO (TDY-036): Simulating Random Pattern Sequence #number ...

EXPLANATION:
USER RESPONSE:
assistance.
WARNING (TDY-037): Unable to obtain program license

EXPLANATION:
The program license is either expired or never purchased.

USER RESPONSE:
assistance.
INFO (TDY-038): Estimated sequential depth: number

EXPLANATION:
The program estimated the sequential depth of the design to be N; for example, in the
worst case, it may take N time images to initialize a latch to a given logic value.
USER RESPONSE:
INFO (TDY-039): Sequential depth greater than the depth limit .. random patterns
not simulated
EXPLANATION:
For designs with a high sequential depth, the random pattern coverage is typically very
low. Apart from increasing the fault simulation time for such designs, the overall pattern
count is increased compared to the case where no random patterns were used. For
designs whose depth is beyond an internally determined depth D (usually 8), the random
pattern simulation phase is automatically skipped.
USER RESPONSE:
WARNING (TDY-040): Unable to save audit data

EXPLANATION:
The computer may run out of space.
USER RESPONSE:
Make sure that there is sufficient space for the experiment. If the error keeps occurring,
assistance.
WARNING (TDY-041): No-Stim-Clocks option selected .. potential for sim rejects

EXPLANATION:
This may result in lower fault coverages.
USER RESPONSE:

Stop the experiment and select one of the Stim-Clock options. Then rerun the
experiment.
WARNING (TDY-042): Unknown error occurred

EXPLANATION:
Unclassified error occurred.
USER RESPONSE:
Let the experiment run, unless it is interrupted by this error. Contact customer support
(see Contacting Customer Service on page 23) to report the error.
WARNING (TDY-050): [Severe] The committed fault model file filename does not exist
and is required.
EXPLANATION:
Dynamic fault Analysis requires a fault model. Analysis can not be accomplished.
USER RESPONSE:
Build a fault model, then rerun dynamic fault analysis.
WARNING (TDY-060): StimClocks=No and Primary Inputs feed flush latches, Incomplete
Tests. Add StimClock=Yes to the command line.
EXPLANATION:
In order to control the race between the clock and Data feed by the PI the clocks leading
and trailing edges must be controlled independently of each other. This is done by
stimming each edge.
USER RESPONSE:
Add StimClock=yes to the TTCmain command line or menus.
WARNING (TDY-070): Unable to protect all unsafe dotts. Check your model or specify
contentionprevent=no.
EXPLANATION:
The test generator was unable to generate any pattern which protected all the unsafe
dotts.
USER RESPONSE:
Check your design and change it as needed, or specify contentionprevent=no.

WARNING (TDY-071): [Severe] Unable to protect all unsafe dotts within the test generation
processing limits. Increase maxfaultcputime and backlimit and rerun.
EXPLANATION:
The test generator was unable to generate any pattern which protected all the unsafe
dotts within the processing limits.
USER RESPONSE:
Increase maxfaultcputime and backlimit and rerun.


25
TDX - Dynamic Test Generation
Messages
TDX-001 through TDX-049 on page 671
TDX-001 through TDX-049

WARNING (TDX-001): [Internal] Unrecognized simulation function found for a block. Test
generator does not support the specified logic primitive. Use the correct logic primitives and
rerun the design. If only supported logic primitives were used, then contact customer support
for assistance (see Contacting Customer Service on page 23).
EXPLANATION:
Unrecognized simulation function found for a block in the design. Test generator does not
support the specified logic primitive.
USER RESPONSE:
Use the correct logic primitives and rerun the design. If only supported logic primitives
were used, then contact customer support for assistance (see Contacting Customer
WARNING (TDX-002): [Internal] The specified fault was not found in the fault model.
Contact customer support for assistance (see Contacting Customer Service on page 23).
EXPLANATION:
The fault being processed was not found in the fault model.
USER RESPONSE:
Contact customer support for assistance (see Contacting Customer Service on
page 23).
ERROR (TDX-005): Unable to load the design logic model. The logic model files might not
exist, or there might not be enough storage on the machine on which you are running the files.

TDX - Dynamic Test Generation Messages
Ensure that the Encounter Test logic model files exist, and that there is adequate storage on
the machine to be able to run the design.
EXPLANATION:
Delay Test was unable to load the logic model. The logic model files might not exist, or
there might not be enough storage on the machine on which you are running the files.
USER RESPONSE:
Ensure that the Encounter Test logic model files exist, and that there is adequate storage
on the machine to be able to run the design.
WARNING (TDX-006): Unable to load the test mode. Ensure that the test mode has been
defined.
EXPLANATION:
The test pattern generator was unable to load the test mode.
USER RESPONSE:
Ensure that the test mode has been defined.
WARNING (TDX-014): [Internal] An internal program error occurred. Processing will

continue. Test data produced is valid but coverage may be impacted. If the test coverage is
not acceptable, contact customer support (see Contacting Customer Service on page 23)
for assistance.
EXPLANATION:
An error internal to the test pattern generator has occurred. This error does not result in
corrupted data. However, it may impact the test coverage.
USER RESPONSE:
If the test coverage is not acceptable, contact customer support (see Contacting
WARNING (TDX-016): [Internal] The application encountered an error while accessing

vectors. Contact customer support (see Contacting Customer Service on page 23) for
assistance.
EXPLANATION:
The test pattern generator could not access the Cadence test vectors.
USER RESPONSE:

assistance.
WARNING (TDX-021): Memory allocation error. Kill unneccessary processes on the

machine, or run on a machine with more memory.
EXPLANATION:
The test pattern generator failed to allocate the required memory.
USER RESPONSE:
Kill unneccessary processes on the machine, or run on a machine with more memory.
WARNING (TDX-027): [Internal] Problem occurred while reading or writing parameter

bank. Contact customer support (see Contacting Customer Service on page 23) for
assistance.
EXPLANATION:
Error while processing test generation parameters.
USER RESPONSE:
assistance.
WARNING (TDX-028): Design has number asynchronous loop(s). This may result in
inaccurate results, which may impact test coverage. If test coverage is impacted, remove
asynchronous loops from the design.
EXPLANATION:
Design has asynchronous loops. This may result in inaccurate results.
USER RESPONSE:
generation results. If test coverage is impacted, redesign to remove asynchronous loops.
WARNING (TDX-029): Unable to retrieve line hold information. Ensure that the linehold file
exists and that it is created correctly.
EXPLANATION:
USER RESPONSE:
Ensure that a linehold file exists and that it is created correctly. Then rerun the design.

INFO (TDX-030): FaultID: number was tested

EXPLANATION:
Informational message indicating that the test pattern generator was able to generate a
test on a fault.
USER RESPONSE:
INFO (TDX-031): FaultID: number was untestable

EXPLANATION:
Informational message indicating that a specific fault was untestable.
USER RESPONSE:
INFO (TDX-032): FaultID: number was aborted

EXPLANATION:
Informational message indicating that a specific fault was aborted.
USER RESPONSE:
To reduce the count of aborted faults, increase the effort parameter.
INFO (TDX-034): Dynamic TG learning phase started using faultNumber faults.

Original CPU time per fault (maxfaultcputime) timeLimit
backtrack (backlimit) backLimit
Learning mode time learnTime and backtrack limit learnBackLimit.
EXPLANATION:
By default, the dynamic test generator automatically learns the optimum time it should
spend per fault. It does this whenever the effort changes or the number of aborted faults
becomes greater that 50 percent of the faults it now processing.
USER RESPONSE:
The parameters that control learning are dynlearn and dynlearntime.
INFO (TDX-035): Dynamic TG learning phase completed.

Resolved faults = resolved_faults

Aborted faults = aborted_faults
Total TG Time = tgTimeSeconds
Original CPU time per fault (maxcpuperfault) timeLimit
backtrack (backlimit) backLimit
New CPU time per fault (maxcpuperfault) newTimeLimit
backtrack (backlimit) newBackLimit
EXPLANATION:
By default, the dynamic test generator automatically learns the optimum time it should
spend per fault. It does this whenever the effort changes or the number of aborted faults
becomes greater that 50 percent of the faults it now processing.
USER RESPONSE:
The parameters that control learning are dynlearn and dynlearntime.
ERROR (TDX-036): Dynamic TG initialization Failed. See the previous message.

EXPLANATION:
During the initialization of the dynamic test generator, an error condition was found that
disallows the test generator from continuing.
USER RESPONSE:
Review the previous message to determine how to eliminate the error condition and
rerun.
WARNING (TDX-037): [Severe] Dynamic TG initialization imply failure at net netName.

View this net in the GUI logic schematic and look for conflicts such as conflicts between the
test constraint state and lineholds, and correct any conflicting requirements.
EXPLANATION:
During the initialization of the dynamic test generator, the required logic values caused
an unallowable condition at the specified net such as a conflict between the test
constraint state and a linehold.
USER RESPONSE:
Determine how to eliminate the error condition and rerun.

ERROR (TDX-038): Dynamic TG initialization imply failure at net netName due to 3-state
contention caused by required logic values. Analyze the 3-state contention to determine how
to eliminate the contention, and rerun.
EXPLANATION:
During the initialization of the dynamic test generator, the required logic values caused
an unallowable 3-state condition at the specified net.
USER RESPONSE:
Determine how to eliminate the error condition, and rerun.
ERROR (TDX-039): The logic values from the test sequence caused unallowable
conditions. Refer to the preceding TDX-037 or TDX-038 message for details.
EXPLANATION:
During the initialization of the dynamic test generator, the logic values from the test
sequence caused unallowable conditions.
USER RESPONSE:
Check the test sequence for problems.
Reffer to the preceding TDX-037 or TDX-038 message for the name of the failing net.
ERROR (TDX-040): Dynamic TG initialization failed. The test sequence is incorrect. The
dyamic pattern or scan_unload event may be missing, or the sequence may be too
complex. Add the missing events, or simplify the test sequence by removing pulses or adding
TG_IGNORE keywords.
EXPLANATION:
During the initialization of the dynamic test generators use of the specified
testsequence, it was determined that either the scan_unload event or dynamic
pattern is missing or that the specified test sequence is too complex. The test sequence
is not used to guide test generation.
USER RESPONSE:
Add the missing events and rerun. If the test sequence has numerous pulses, then
simplify the sequence by removing them or adding TG_IGNORE keywords. Refer to
Keyed Data in the Encounter Test: Reference: Test Pattern Formats for additional
information.
INFO (TDX-041): FaultID: number was unsuccessful, with an incomplete attempt.

EXPLANATION:

Test generation or analysis for the referenced fault was incomplete due to an insufficient
effort value.
USER RESPONSE:
Increase the effort setting to reduce the number of incomplete faults.
WARNING (TDX-042): The application encountered numberOfFaults faults, which

require more levels of latches or memory than can be handled under the current parameter
setting of allowedjustifytimeframes.
Additional test coverage may be possible by appending an additional test generation run with
allowedjustifytimeframes=number.
EXPLANATION:
This warning message states that test coverage may be improved by appending with
another test generation run with a different allowedjustifytimeframes parameter
setting.
USER RESPONSE:
To improve test coverage, run again and increase the allowedjustifytimeframes
value.
Execute the additional run by either appending to this experiment, or commit this
experiment and then do the additional run.
Also, consider specifying reprocessuntestable=yes for the additional run to
increase the run time.
Note that it is not recommended to rerun from scratch with a different
allowedjustifytimeframes specified, since the larger
allowedjustifytimeframes value can degrade performance.
INFO (TDX-044): number design constraints are being honored in this run.
EXPLANATION:
The message states the number of currently honored design constraints. A possible low
test coverage may be due to the design constraints.
USER RESPONSE:
No response required unless lower than expected test coverage is produced. In this
case, analyze the design contraints and determine whether they require modification.
INFO (TDX-045): Path number: number passed reconvergence check

EXPLANATION:
Informational message indicating that the test pattern generator checked this path for
conflicts between reconvergence in the path and required path sensitization, and did not
find any such conflicts.
USER RESPONSE:
INFO (TDX-046): Path fault index: number reconvergence check found requirements which
are invalid due to path reconvergence.
EXPLANATION:
Informational message indicating that fault analysis found conflicts between required
values for path sensitization and implied values due to path reconvergence.
USER RESPONSE:
ERROR (TDX-047): [Severe] Test sequence name does not have a scan load but the part
has scan chain(s). Processing will terminate. Correct the test sequence patterns, re-import
the test sequence, and rerun.
EXPLANATION:
Test sequence specified with the testsequence keyword does not contain a scan load
event.
Since the part contains scan chain(s), the sequence must have a scan load event.
USER RESPONSE:
Correct the test sequence patterns, reimport the test sequence, and rerun the command.
WARNING (TDX-048): [Severe] Test sequence name has more than 20 pulses. Only the
first 20 pulses will be used to drive test generation.
EXPLANATION:
The test sequence specified with the testsequence keyword has more than 20 pulses.
The test generator will use only the first 20 pulses, however all of the pulses will be
simulated.
USER RESPONSE:

However, if the test coverage is not sufficient and some needed clocks are not in the first
20 pulses, then you may reduce the number of pulses, re-import the test sequence, and
rerun.
INFO (TDX-049): FaultID: number was untestable with current active-compaction design
values.
EXPLANATION:
A specific fault was untestable with the current active-compaction design values.
USER RESPONSE:
INFO (TDX-050): [Severe] LOS patterns cannot be generated due to scan enables that are
constrained to the functional state. LOC patterns will be generated for some faults.
EXPLANATION:
The user request of LOS patterns cannot be generated due to scan enables that are
constrained to functional state.
USER RESPONSE:


26
TEI - Build Model Messages
TEI-001 through TEI-050 on page 681

TEI-001 through TEI-050

INFO (TEI-001): No help available for executable_name. This is not a stand-alone
executable. Proper invocation of Encounter Test Build Model is via build_model.
EXPLANATION:
An attempt was made to execute a Encounter Test Build Model binary executable that is
not intended to be independently run. It is only executed by other Encounter Test
programs. Encounter Test: Reference: CommandsUSER RESPONSE:
Run build_model to import a design into Encounter Test. Refer to "build_model" in the
ERROR (TEI-002): The cell cellname was not found in the design source file(s) specified.
Note that for Verilog, a change has been made to no longer automatically search the
directories for explicitly specified files. Therefore, it may now be necessary to add the
directory of this missing cell to build the complete design.
EXPLANATION:
The cell name shown in the message was referred to in at least one design source file,
but the cell definition could not be found in the specified design source/techlib files or
paths.

Note that for Verilog, the program is changed to no longer automatically search the
directories for explicitly specified files. Assume the following scenario as an example:
Assume a directory, mysource, that contains cells A.v and C.v and another
directory, othersource, that contains B.v and D.v and module A contains
instances of modules C, B, and D (that are defined in the verilog file with the
same name).
Specify the build_model search path with DESIGNSOURCE=mysource/
A.v,othersource
In the past, module C would have been found in mysource/C.v because the program
would have searched mysource/A.v, then mysource/*, then othersource/*.
Now, the program will only search explicitly specified files and directories. So, for this
example, it searches mysource/A.v, then othersource/* and will not find the
definition of module C. In order to find C, change the specification to:
DESIGNSOURCE=mysource/A.v,mysource,othersource.
USER RESPONSE:
Rerun Build Model with a corrected designsource or techlib parameter that
specifies the file or path for the missing cell definition.
INFO (TEI-003): The cell cellname was selected as the top cell.
EXPLANATION:
This message indicates that the top level cell was not specified. Build Model selects the
cell shown in the message as the top level cell.
USER RESPONSE:
If the cell selected by default is not the desired top level cell, rerun Build Model with the
cell parameter specifying with the desired top level cell.
ERROR (TEI-004): Output boundary model name identified by OUTPROJECT, OUTENTIY,

OUTVARIATION, and OUTITERATION is identical to the input model name identified by
PROJECT, ENTITY, VARIATION, and ITERATION. Boundary model is not allowed to overlay
input model. Respecify output boundary model parameters.
EXPLANATION:
You attempted to create a boundary model in the same directory as the existing full chip
model. Doing so would overwrite your full chip model.
USER RESPONSE:

Choose a different OUTPROJECT, OUTENTITY, OUTVARIATION or OUTITERATION so

that the boundary model will be built in a directory that is different from the full chip model.
ERROR (TEI-005): Unable to get read lock on input model filename. Check directory/file
permissions and/or directory/file existence. Build Boundary Model exits.
EXPLANATION:
Create a Boundary Model attempted to get a read lock on the model file specified, but
was unsuccessful. This failure may occur if you do not have access permission to read
the file, if the file does not exist, if you do not have write access to the locks directory, if
the locks directory does not exist, or if another application or user is already updating the
file.
USER RESPONSE:
Check to see if one of the conditions above is preventing access to the file. If so, correct
the condition and rerun Create a Boundary Model. If none of the error conditions listed
above exists, contact customer support (see Contacting Customer Service on page 23)
for assistance.
ERROR (TEI-006): Unable to load hierarchical model hiermodel. Refer to preceding

messages. Build Boundary Model terminates.
EXPLANATION:
Build Boundary Model failed to read the specified hierarchical model. This message is
preceded by messages which provide more detail.
USER RESPONSE:
Refer to preceding messages, take any necessary corrective action and then rerun.
ERROR (TEI-007): Build Flat Model did not successfully complete. Check preceding system
and/or TLM message(s).
EXPLANATION:
Build Flat Model failed. In many cases, it issues messages indicating the cause of the
failure. These messages usually have a prefix of TLM.
USER RESPONSE:
If there are preceding messages identifying the cause of the failure and it does not
appear to be a program failure, correct the condition causing the failure and rerun Build
Model. Otherwise, contact customer support (see Contacting Customer Service on

ERROR (TEI-008): Process intercommunication has terminated. Build Model terminates.

Contact customer support (see Contacting Customer Service on page 23) for assistance.
EXPLANATION:
Build Model relies on interprocess communication between multiple sub-processes. This
communication has been interrupted and processing terminates.
USER RESPONSE:
assistance.
WARNING (TEI-009): Unable to read lock access filename. Verify input WORKDIR or
check directory/file permissions and/or directory/file existence. Message overrides file
(TEImsgOverrides) not created.
EXPLANATION:
This application attempted to get a read lock on the file specified, but was unsuccessful.
This failure may occur if you do not have access permission to read the file, if the file does
not exist, if you do not have write access to the locks directory, if the locks directory does
not exist, or if another application or user is already updating the file.
USER RESPONSE:
Determine whether one of the conditions described above is preventing access to the
file. If so, correct the condition and rerun the application. If none of the error conditions
listed above exists, contact customer support (see Contacting Customer Service on
WARNING (TEI-010): The cell cellname has an unknown simulation function and has no
contents. The cell cellname will be defined as a blackbox.
EXPLANATION:
Build Model did not recognize the cell name shown in the message as a supported
primitive block and also could not find the definition of what is inside of the cell. The cell
will be included in the model with only its interface and nothing inside of it.
USER RESPONSE:
Make sure that this is what was intended. If not, specify the contents of the cell in the
design source and rerun Build Model.
INFO (TEI-011): Server cant bind socket port port number- switching to next port
number+1

EXPLANATION:
Build Model could not bind to the referenced port number for socket communication
between processes. The next port number will be tried.
USER RESPONSE:
WARNING (TEI-012): Unable to load model filename. Check preceding THM messages.
Message overrides file (TEImsgOverrides) not created.
EXPLANATION:
The program unsuccessfully attempted to open the specified hierarchical model file. This
failure may occur if you do not have access permission to read the file, if the file does not
exist, if you do not have write access to the locks directory, if the locks directory does not
exist, or if another application or user is already updating the file.
USER RESPONSE:
Determine whether one of the described conditions in in the explanation is preventing
opening the file. If so, correct the condition and rerun the application. If none of the error
conditions exists, contact customer support (see Contacting Customer Service on
WARNING (TEI-013): Unable to allocate filename. Errno is errorno. Check perror

message printed to stderr. Message overrides file (TEImsgOverrides) not created.
EXPLANATION:
The program attempted to create/update the referenced file, but was unsuccessful. The
reason for this failure is identified by the Errno code and a message printed to stderr.
USER RESPONSE:
Correct the condition causing the failure as identified by the Errno code and
accompanying message. If this is not possible, contact customer support (see
WARNING (TEI-014): Unable to successfully close filename. Errno is errorno. Check

error message printed to stderr. Message overrides file (TEImsgOverrides) is suspect.
EXPLANATION:
This application attempted to close the referenced file, but was unsuccessful. The reason
for this failure is identified by the Errno code and a message printed to stderr.
USER RESPONSE:

Correct the condition causing the failure as identified by the Errno code and
accompanying message. If this is not possible, contact customer support (see
WARNING (TEI-015): Errors occurred during creation of message overrides file

(TEImsgOverrides). Message overrides during Encounter Test applications will not occur.
Check preceding system and/or TEI message(s).
EXPLANATION:
Build Model detected that the TEImsgOverrides file has not been created. There
should be accompanying messages explaining why this file does not exist.
USER RESPONSE:
Attempt to correct the condition causing the failure as identified by the accompanying
messages. If this is not possible, contact customer support (see Contacting Customer
Service on page 23) for assistance.
WARNING (TEI-016): Active logic is cloaked. A CLOAK=YES attribute will be added to block
0.
EXPLANATION:
This message indicates that boundary model build has encountered cloaked logic during
processing. If one block in the external model is cloaked then the whole boundary model
must become cloaked.
USER RESPONSE:
Verify that the cloaked block is supposed to be in the boundary model. If the cloaked
block should not be there, verify your pin flags and rebuild this boundary scan external
mode on the original full structure design.
ERROR (TEI-017): Server cannot bind socket port port_number - quitting after max
attempts.
EXPLANATION:
Build Model could not bind to the referenced port number for socket communication
between processes. The maximum number of attempts of different port numbers has
been exceeded. Processing terminates.
The most likely cause is the IP (internet) address of the machine that Build Model is being
run on is not correctly set.
USER RESPONSE:

Correct the IP address on the machine and rerun Build Model or rerun Build Model with
the inet parameter set to the correct IP address of the machine. If this problem persists,
ERROR (TEI-018): Error - Client cannott create|connect|shutdown|close socket.

ERRNO=errno.
EXPLANATION:
Build Model is experiencing difficulty creating, connecting to, shutting down, or closing a
socket that is used for communication between the main process and sub-processes of
Build Model. Processing terminates.
USER RESPONSE:
Ensure the IP address on the machine is correctly set and rerun Build Model or rerun
Build Model with the inet parameter set to the correct IP address of the machine or try
running on a different machine. If this problem persists, contact customer support (see
INFO (TEI-019): Edit Model starting:

EXPLANATION:
The model edit program is starting.
USER RESPONSE:
NFO (TEI-020): Edit Model complete:

EXPLANATION:
The model edit program is completed.
USER RESPONSE:
ERROR (TEI-021): Build Model is unable to build hierarchical model. Maximum number of
expected input|output ports exceeded for cell cellname. Processing terminates. Cell
contents file: cellname.
EXPLANATION:
Build Model has exceeded the size of its internal tables for the specified cell, causing an
abnormal termination

USER RESPONSE:
ERROR (TEI-023): Build Model: unable to read file filename. Specify a valid file or path
name with proper permissions.
EXPLANATION:
Build Model was not able to find or open the referenced file. Processing terminates.
USER RESPONSE:
Review and ensure the following, then rerun:
The file exists in the directory specified. If not running in the directory, the file
name must be fully qualified or be relative to the current directory.
Permissions on the file allow read access.
The file is compressed you have included the file compression suffix (.Z or
.gz).
ERROR (TEI-024): [Tool] Build Model: unable to register industrycompatible keyword.

Keyword defaults for Build Fault Model will be incorrect. Possible causes are WORKDIR file
system access or the file system is full
EXPLANATION:
Build Model has abnormally terminated because keyword industrycompatible
registration has failed. Build Fault Model will be unable to retrieve keyword defaults
expected to be produced by this Build Model execution. Build Fault Model will be unable
to properly build an industry compatible fault model.
USER RESPONSE:
Investigate and resolve possible causes stated in the message. Contact customer
support (see Contacting Customer Service on page 23) if the condition persists.
ERROR (TEI-025):[Internal] Verilog data access issues caused the Verilog processing to
terminate.
EXPLANATION:
Build Model parser has failed and abnormally terminated because of data access issues.
One of the following is the probable cause of the failure:
VPI does not return a valid handle of trusted VPI function tray.

Version of VPI interface that build_model is using is not compatible with the
trusted version of VPI interface, provided by NC-sim to Encounter Test.
Unable to decrypt the trusted VPI function tray.
USER RESPONSE:
the input design files and log files.
ERROR (TEI-026): Edit Model failed.

EXPLANATION:
A failure occurred during model edit.
USER RESPONSE:
Correct problems and rerun.
INFO (TEI-027): Model Edits Previously Processed:

EXPLANATION:
The previously processed model edits are listed.
USER RESPONSE:
INFO (TEI-028): Model Edit Statements Processed:

EXPLANATION:
The currently processed model edits are listed.
USER RESPONSE:
INFO (TEI-031): Edit Model Reprocessing starting:

EXPLANATION:
Model Edit reprocess is starting.
USER RESPONSE:

INFO (TEI-032): Edit Model Reprocessing completed:

EXPLANATION:
The reprocessing of the model edits successfully completed.
USER RESPONSE:
ERROR (TEI-034): Internal program TEIsget | TEIsput error: pageNum exceeds

maxPages.
pageNum = pageNum, maxPages = maxPages, pageSize = pageSize, maxSize =
maxSize.
EXPLANATION:
Build Model logic design size capacity may have been exceeded.
USER RESPONSE:
ERROR (TEI-035): Internal program error: Net netname in cell cellname has too many
joineds. numJoinedsjoineds expected. Contact customer support. Cell contents file:
contentsfile.
EXPLANATION:
An internal program error has occurred where more pins have been joined to a net than
the maximum number that was originally calculated to be the maximum for storage
allocation purposes. Processing terminates.
USER RESPONSE:
ERROR (TEI-036): Memory capacity of machine reached. Memory is insufficient to create

hierarchical model. Build Model must quit. Current internals are: pageNum = pageNum,
maxPages = maxPages, pageSize = pageSize, maxSize = maxSize.
EXPLANATION:
Build Model is unable to allocate more memory for creation of the hierarchical model.
USER RESPONSE:
Rerun on a machine with more memory available. Contact customer support for
assistance, if required,

$ supplying failing log.
ERROR (TEI-039): Edit Model Reprocessing failed.

EXPLANATION:
The reprocessing of model edits failed. See previous messages for details.
USER RESPONSE:
Correct the problems identified by the previous messages and rerun.
INFO (TEI-040): Reprocessing Requested:

EXPLANATION:
The message states that model edit reprocessing has been requested.
USER RESPONSE:
INFO (TEI-049): Test Mode testMode was removed but not recreated. In order to process
the changes made to this test modes test function pin assignments (or other test mode
specific edits), you must specify assignfile=assignFile when recreating this test mode.
EXPLANATION:
The test function pin assignment changes made during model edit have been stored in
the specified assignFile. In order to process these changes, you must rerun Build Test
Mode using this assignFile.
USER RESPONSE:
Rerun Build Test Mode using the assignFile specified.
ERROR (TEI-050): Required parameter parameter was not specified. Edit Model exits.
EXPLANATION:
This parameter is required in order to edit the design.
USER RESPONSE:
Specify the required parameter and rerun Encounter Test Model Edit. Refer to
"edit_model" in the Encounter Test: Reference: Commands for additional
information.


ERROR (TEI-051): Filename filename could not be found. Edit Model exits.
EXPLANATION:
The specified file could not be found.
USER RESPONSE:
Make sure that file permissions allow processing of the specified file, and that the
filename is completely specified. Then rerun Encounter Test Model Edit.
ERROR (TEI-054): Required parameter parameter was not specified. Edit Model
Reprocessing exits.
EXPLANATION:
This parameter is required in order to reprocess the design.
USER RESPONSE:
Specify the required parameter and rerun Encounter Test Edit Model Reprocessing.
Refer to "edit_model_reprocess" in the Encounter Test: Reference: Commands for
INFO (TEI-055): The filetype file has been removed.

EXPLANATION:
The specified file and all of its dependencies have been removed.
USER RESPONSE:
None.
INFO (TEI-056): The filetype file has been recreated successfully.

EXPLANATION:
The specified file has been recreated.
USER RESPONSE:
None.
INFO (TEI-057): The filetype file does not exist.

EXPLANATION:

The specified file does not exist. It has not been removed.
USER RESPONSE:
INFO (TEI-058): Attribute attrName has been created in order to retain the Pseudo
Primary Input (PPI) and Cutpoint definitions for test mode testMode in the Boundary
Model. Attribute attrName must be added to the Test Function Pin Attribute (TFPA)
statement in any Mode Definition File which will be used to Build Test Modes for either this
Boundary Model or a higher level of package (typically MCM) which contains this Boundary
Model for which PPI and Cutpoints are required.
EXPLANATION:
In order to preserve Pseudo Primary Input (PPI) and Cutpoint definitions for a given
testmode when building a Boundary Model or higher level of package you must specify
the TB_modename_BDY in the Test Function Pin Attribute statement in the Mode
Definition File referenced by the test mode.
USER RESPONSE:
INFO (TEI-059): No test point data exists. The TSDL file filename will not be created.
EXPLANATION:
The TSDLFILE parameter was specified on the edit_model command line for
Encounter Test to write test point data into in TSDL format, but no test points were found.
The TSDL file will not be created.
USER RESPONSE:
WARNING (TEI-060): [Severe] Checksum for cell cellname is being set to ERROR. Cell
contents file: contentsfile.
EXPLANATION:
A mismatch has been detected between the checksum computed for the cell contents
file and the checksum recorded in the cell contents file for the cell name identified in the
message. This is an indication that the file has been edited since it was created, and will
result in the UNLEV being set to 0 in the LUF. Manufacturing audits will fail.
USER RESPONSE:

If the scenario described in the EXPLANATION section is a problem, investigate the cell
contents file.
Rebuild the model with unedited source files in order to pass the audit checking required
by Manufacturing. In order to regenerate a checksum for the new netlist, run CMOSChks
MCCsLVMain program prior to performing Build Model.
ERROR (TEI-069): Required input testmodes with SCAN TYPE

boundary=external,model and boundary=bypass do not exist.
build_core_migration_model terminates.
EXPLANATION:
build_core_migration__model requires one or more external,model and bypass
testmodes as input for determining the logic to include in the Core Migration Model.
USER RESPONSE:
Refer to the section Hierarchical Test Flow in Encounter Test: Flows.
ERROR (TEI-070): [Internal] PID pid_number PROGRAM ERROR: processing of input

data has failed.
EXPLANATION:
This error indicates a program error that only the Encounter Test team can fix. The input
source being processed when this error occurred immediately precedes this message.
USER RESPONSE:
Contact customer support (see Contacting Customer Service on page 23). Provide the
build_model log and the input source file identified.
ERROR (TEI-100): [Internal] Duplicate file definition: file edif_file.

EXPLANATION:
This message indicates a program bug during the Build Model process.
USER RESPONSE:
Contact customer support (see Contacting Customer Service on page 23). Please be
prepared to provide the following information:
The log from Build Model.

The design source files.
ERROR (TEI-101): [Internal] Duplicate library definition: library edif_library

EXPLANATION:
USER RESPONSE:
ERROR (TEI-102): [Internal] Duplicate cell definition: cell cellname

EXPLANATION:
USER RESPONSE:
ERROR (TEI-103): [Internal] Duplicate view definition: view edif_view of cell cell
EXPLANATION:
USER RESPONSE:
ERROR (TEI-104): Conflicting pin definitions: pin pinname of cell cellname. Cell
EXPLANATION

The design description for cell cellname contains two distinct pins that Encounter Test
interprets as having the same pin name. The build_model process is stopped, and the
hierarchical model is not built. Encounter Test Build Model creates scalar names for each
individual bit of a vectored pin. The generated name contains the bit number in square
brackets. For example, \x@yz[1].
The generated vectored pin name matches a scalar pin with the same name.
Example:
input [1:0] \x@yz ; Build Model generates names \x@yz[1] and \x@yz[0]. input
\x@yz[1] ; Build Model name is \x@yz[1], which conflicts.
This is not supported and is a documented limitation of Build Model.
USER RESPONSE
Update the design source contents file to remove the conflict.
ERROR (TEI-105): Duplicate instance definition: instance instance1 of cell

cellname1. Cell contents file: contentsfile.
EXPLANATION:
The design description for the referenced cell contains two distinct instances with the
same name. Build Model will connect all nets to the first instance, which is probably not
what was intended. The Build Model process is stopped, and the hierarchical model is
not built.
USER RESPONSE:
Update the design source contents file to remove the duplicate instance and rerun.
ERROR (TEI-106): Verilog Vectored Net Limitation: duplicate net definitions for net
netname of cell cellname. Cell contents file: contentsfile. Build Model generates
scalar names for each individual bit of a vectored net. The vectored net generated scalar
name netname matches a scalar net with the same name.
EXPLANATION:
The design description for cell cellname contains two distinct nets that Encounter Test
interprets as having the same net name. The build_model process is stopped, and the
hierarchical model is not built. Encounter Test Build Model generates scalar names for
each individual bit of a vectored net. The generated name contains the bit number in
square brackets. For example, \x@yz[1].
The generated vectored net name matches a scalar net with the same name.
Example:

wire [1:0] \x@yz ; Build Model generates names \x@yz[1] and \x@yz[0].
wire \x@yz[1] ; Build Model name is \x@yz[1] which conflicts.
This is not supported and is a documented limitation of Build Model.
USER RESPONSE:
Update the design source contents file to remove the conflict.
ERROR (TEI-107): [Internal] Pin pinname of cell cellname has no direction specified
- INOUT is assumed.
EXPLANATION:
USER RESPONSE:
INFO (TEI-108): No internal net is connected to input interface pin pinname of cell
cellname.
EXPLANATION:
The referenced cell contains the referenced input pin, but there is no net internally
connected to the port.
A externally connected net to this pin with no other sinks will become inactive.
USER RESPONSE:
Verify that this port is intended to be unused. This message indicates a possible
reduction in the amount of active logic identified by Encounter Test during the Test Mode
Definition process. If test mode definition determines that an inordinate amount of the
logic is inactive, use this message to help identify some of the causes for inactive logic.
ERROR (TEI-109): More than one net is connected to interface pin pinname of cell
cellname. The first two nets are netname1 and netname2. Cell contents file:
contentsfile.
EXPLANATION:

Internally to the cell cellname, there are at least two nets connected to the interface
pin pinname. The first two nets connected to the pin are netname1 and netname2.
Encounter Test will connect the pin to only the first of the nets, which is probably not what
was intended.
Build Model is stopped and the hierarchical model is not built.
USER RESPONSE:
Update the design source cell contents to remove all but one of the nets connected to
the refernced pin name and rerun.
WARNING (TEI-110): Pin pinname of cell cellname has not external net connectino for
any usage in the design. Cell contents file: contentsfile.
EXPLANATION:
Every time cell cellname is used, pin pinname is not connected to a net.
If the internal net of the cell is sourceless and there are no TIE properties on the net
inside the cell, the default TIE value will be used. Since the default TIE value is usually
X, then this connection to the net will probably become an X source.
If the internal net of the cell has a source and there are no other external connections for
the net, the logic is dangling and will become inactive logic.
USER RESPONSE:
Examine each usage of the cell to determine why the port is not used and rerun if
necessary. There are several possible situations:
The pin is an input pin, the net connected to the port has a TIE attribute, and it
is legal to leave the port unconnected. In this case, the message may be
ignored.
The pin is an output pin which may be left unconnected per the technology rules
for the cell. In this case, the message may be ignored.
The Encounter Test definition of the cell does not match the definition of the cell
used to create the design. In this case, either the Encounter Test model of the
cell or the design must be corrected.
The design which uses this cell is known to be incomplete, and not all pins are
connected. In this case, the message may be ignored, but this condition may
cause design rule violations and/or decreased test coverage.
WARNING (TEI-111): No pins found for cell cellname. Cell contents file: contentsfile.
EXPLANATION:

The referenced cell has no any input, output, or bidirectional ports.

Encounter Test will treat all the logic inside this cell as inactive logic. Since there are no
pins, this cell will not affect the rest of the Encounter Test model.
USER RESPONSE:
This message usually indicates that there is a problem with the definition of the
referenced cell. Correct the design source.
If this cell is intended to be an empty cell, add the attribute PD_BOOK=yes to avoid this
message.
INFO (TEI-112): No input pins found for cell cellname.

EXPLANATION:
The referenced cell has no input or bidirectional ports. This message is expected for cells
that produce constant values.
USER RESPONSE:
Verify whether the cell should have any input pin. If not, this message may be ignored.
INFO (TEI-113): No output pins found for cell cellname.

EXPLANATION:
The referenced cell has no output or bidirectional ports. This message is expected for
cells that terminate nets
USER RESPONSE:
Verify whether the cell should have any output ports. If not, this message may be ignored.
ERROR (TEI-114): [Internal] Instance instance1 refers to an undefined cell -

cellname
EXPLANATION:
USER RESPONSE:

INFO (TEI-115): No net connected to pin pinname on instance intance1 of cell

cellname1 withincell cellname2.
EXPLANATION:
Pin pinname on instance instance1 (an instance of cellname1) within
cellname2 is unconnected. If the net internal to the cell is sourceless and there are no
TIE properties on the net inside the cell, the default TIE value from Build Model will be
used. Since the default TIE value is usually X, then this connection to the net will probably
become an X source.
If the internal net of the cell has a source and there are no other external connections for
the net, the logic is dangling and will become inactive logic.
USER RESPONSE:
Examine the contents of cellname2 to determine why piname is unused. There are
several possible explanations:
The pin is an input pin, the net connected to the pin has a TIE attribute, and it
is legal to leave the port unconnected. In this case, the message may be
ignored.
The pin is an output pin which may be left unconnected per the technology ules
for the cell. In this case, the message may be ignored.
The design which uses this cell is known to be incomplete, and not all pins are
connected. In this case, the message may be ignored, but this condition may
cause design rule violations and/or decreased test coverage.
ERROR (TEI-116): More than one net in cell cellname defines a connection to pin
pinname on instance instance1.
A pin can only be connected to one net in a cell. The first two nets are netname1 and
netname2. Cell contents file: contentsfile.
EXPLANATION:
Nets netname1 and netname2 both specify a connection to pin pinname on
instance instance1. This violates the net list semantics - only a single net should
connect to an instance of a pin.
Encounter Test will connect the instance of the pin to only the first of the nets, which is
probably not what was intended. Build Model is stopped and the hierarchical model is not
built.
USER RESPONSE:

Update the design source to remove all but one of the nets connected to pin pinname
for instance instance1, then rerun.
ERROR (TEI-117): Net netname1 in cell cellname1 refers to an undefined instance,

instance1. Cell contents file: contentsfile.
EXPLANATION:
Net netname1 in cell cellname1 defines a connection to instance instance1 that
does not exist in the cell.
Since the intent of this design description is unclear, the Build Model process will stop,
and a hierarchical model will not be built.
USER RESPONSE:
Update the design source by either changing the name of the instance referred to by the
net, or by adding a new instance to match the instance name referred to by the net, and
then rerun.
ERROR (TEI-118): Net netname1 in cell cellname1 refers to an undefined pin

pinname on instance instance1 (usage of cell cellname2). Cell contents file:
cellname1 contentsfile. Cell contents file: cellname2 contentsfile.
EXPLANATION:
Net netname1 in cell cellname1 specifies a connection to a undefined pin for
cellname2. Since the intent of this design description is unclear, Build Model will stop
and a hierarchical model will not be built.
USER RESPONSE:
Determine whether cellname1 or cellname2 is incorrect.
Update the design source by either changing the list of pins defined for
cellname2 or by changing the pin referred to by net netname in cell
cellname1.
Rerun
ERROR (TEI-120): Net netname in cell cellname refers to an undefined interface pin
pinname. Cell contents file: contentsfile.
EXPLANATION:
Net netname in cell cellname specified a connection to an undefined interface pin.
Since the intent of this design description is unclear, Build Model will stop and a
hierarchical model will not be built.

USER RESPONSE:
Update the design source by either changing the name of the pin referred to by the net,
or by adding the pin to the interface.
If the design source format is EDIF 3 0 0, the error may be due to the use of globalPorts
in the design.
WARNING (TEI-121): _debug Net net in cell cell has no connections.

EXPLANATION:
This is a programmer debug message.
RESPONSE:
No response required. This message will only print when program debug is enabled.
INFO (TEI-122): _debug Net net in cell cell has no sources.

EXPLANATION:
RESPONSE:
INFO (TEI-123): _debug Net net in cell cell has no sinks.

EXPLANATION:
RESPONSE:
INFO (TEI-124): _debug Net net in cell cell has multiple sources.
EXPLANATION:
RESPONSE:
INFO (TEI-125): _debug Net net in cell cell has fanout of fanout.
EXPLANATION:


RESPONSE:
INFO (TEI-126): _debug Net net in cell cell has number connections.
EXPLANATION:
RESPONSE:
WARNING (TEI-127): No internal net is connected to output interface pin pinname of cell
cellname.
EXPLANATION:
No net is internally connected to pin pinname of cell cellname. When this cell is used,
any connection to this pin will be treated in a manner similar to the way that sourceless
nets are handled. It will be resolved in one of the following ways:
If there is a TIE attribute on the net, the TIE attribute value will drive this
connection.
If there are no TIE properties on the net inside the cell, the default TIE value
from Build Model will be used. Since the default TIE value is usually X, then this
connection to the net will probably become an X source.
USER RESPONSE:
This message indicates a possible reduction in the amount of active logic identified by
Encounter Test during the Test Mode Definition process as well as a potential X source.
If Tthe est Mode Define determines that an inordinate amount of the logic is inactive, use
this message to help identify some of the causes for inactive logic.
WARNING (TEI-128): Maximum Number (n) of Attributes to exclude reached. Attribute:

name will be included in hierAttributes.
EXPLANATION:
The file specified by the TEICONTROLATTR keyword contains a list of attributes that
Encounter Test should exclude when building a model. They are normally attributes used
by other applications, and are not used by Encounter Test. This is done to help reduce
the size of the hierAttributes file.

The number of attributes specified in the attribute control file exceeded the limit that
Encounter Test can process. Any attributes printed by this message are included in the
hierAttributes file. There is no processing error here, but the hierAttributes file might be
larger than it needs to be.
USER RESPONSE:
No user response is required. However, please contact customer support (see
Contacting Customer Service on page 23) to see if the limit should be increased.
WARNING (TEI-129): Unable to create filename. Included Attributes file not created.
system explanation. Included Attributes file not created.
EXPLANATION:
The TEIincludedAttr file could not be created due to the indicated reason.
The TEIincludedAttr file contains a list of the unique attributes placed in the
hierAttributes file. The hierAttributes file often contains attributes that are not
used by Encounter Test (and can be dropped during Build Model process). The purpose
of the TEIincludedAttr file is to a list the attributes in the hierAttributes file, which you
can use as a basis for excluding attributes in future Build Model runs, by using the
command line option TEICONTROLATTR.
USER RESPONSE:
Ideally, you should correct the problem identified by the message and rebuild the model.
However, failure to create the (TEIincludedAttr file in and of itself does not adversely
affect downstream applications, nor the creation of valid test data.
WARNING (TEI-130): Unable to open filename. The control attributes file will not be
processed.
EXPLANATION:
The file specified by the TEICONTROLATTR keyword could not be opened due to the
indicated reason.
USER RESPONSE:
Ideally, you should correct the problem identified by the message and rebuild the model,
as using the control attributes file can significantly reduce the size of the hierAttributes
file. However, failure to process it will not adversely affect downstream applications, nor
the creation of valid test data.
WARNING (TEI-131): Unable to locate TEIcontrolAttr file in $PATH. Control Attributes

file will not be processed.

EXPLANATION:
Encounter Test could not locate the TEIcontrolAttr file in the path specified by the
$PATH environment variable. This file is normally shipped with the Encounter Test
product and should be included in the install directory. The TEIcontrolAttr file is
used to identify certain attributes that can be excluded during Build Model (dropped from
the hierAttributes file).
USER RESPONSE:
There may be a problem with the installation of Encounter Test, or with the $PATH
environment variable, causing Encounter Test to be unable to locate the
TEIcontrolAttr file. The problem should be corrected, and the model rebuilt.
However, failure to build the model using the TEIcontrolAttr file will not adversely
WARNING (TEI-132): Length of attribute name in attribute control file filename, exceeds
maximum allowable size (n). Attribute will be included in hierAttributes.
EXPLANATION:
The attribute control file, specified by the TEICONTROLATTR keyword contains an
attribute whose length exceeds the maximum allowed by the attribute control processing.
This attribute is dropped from the control list and will therefore be included in the
hierAttributes file.
USER RESPONSE:
There may be an error in the specification of the attributes in the file, causing the
appearance of an attribute with an unusually long name. Failure to process attributes in
the control attributes file will not adversely affect downstream applications, nor the
creation of valid test data. If the length of the attribute actually exceeds the maximum,
please contact customer support (see Contacting Customer Service on page 23) to
see if the limit should be increased.
WARNING (TEI-133): Unable to create filename. Reason: system_explanation.

Excluded Attributes file not created.
EXPLANATION:
The TEIexcludedAttr file could not be created due to the indicated reason.
The TEIexcludedAttr file contains a list of the unique attributes which are excluded
during the creation of the hierAttributes file. These attributes are assumed to be not
needed by any Encounter Test applications. Attributes are dropped from the
hierAttributes file by specifying the TEICONTROLATTR keyword, or by default, using the

TEIcontrolAttr file installed with the Encounter Test product. To bypass the use of
the TEIcontrolAttr file,, specify the -k flag when running command line.
USER RESPONSE:
However, failure to create the TEIexcludedAttr file in and of itself does not adversely
WARNING (TEI-134): msg.

EXPLANATION:
An error was found processing the TEIcontrolAttr file.
USER RESPONSE:
Ideally you should correct the problem identified by the message and rebuild the model.
However, failure to do so will not adversely affect the quality of test data produced.
WARNING (TEI-135): When processing TEIcontrolAttr file filename, the first

statement implied that the file was for EXCLUDING attributes but a subsequent statement
attempted to INCLUDE an attribute. The INCLUDE attribute statement is ignored.
EXPLANATION:
The TEIcontrolAttr file is used to control the size of the hierAttributes file. You may
specify either a list of attributes to exclude from the hierAttributes file or a list of attributes
to include in the hierAttributes file but not both. The file contains statements requesting
that Build Model include some attributes and exclude others.
USER RESPONSE:
Ideally you should correct the TEIcontrolAttr file and rebuild the model. However,
failure to do so will not adversely affect the quality of test data produced.
WARNING (TEI-136): When processing TEIcontrolAttr file filename, the first

statement implied that the file was for INCLUDING attributes but a subsequent statement
attempted to EXCLUDE an attribute. The EXCLUDE attribute statement is ignored.
EXPLANATION:
The TEIcontrolAttr file is used to control the size of the hierAttributes file. You may
specify either a list of attributes to exclude from the hierAttributes file or a list of attributes
to include in the hierAttributes file but not both. The file contains statements requesting
that Build Model include some attributes and exclude others.
USER RESPONSE:

Ideally you should correct the TEIcontrolAttr file and rebuild the model. However,
failure to do so will not adversely affect the quality of test data produced.
WARNING (TEI-137): Unable to create filename.

Reason: system_explanation.
TEIsourceLibPath file not created.
EXPLANATION:
The TEIsourceLibPath file could not be created for the reason specified. The
TEIsourceLibPath file contains the paths for designsource files, techlib files
and the run directory RUNDIR from where the testpart was run (required when relative
source/techilb path is given).
USER RESPONSE:
However, failure to create the TEIsourceLibPath file in and of itself does not affect
downstream applications, nor the creation of valid test data.
WARNING (TEI-140): Pin direction OUTPUT converted to INOUT for pin pinname of cell
cellname. All similar pins of cell will also be converted. Cell contents file: contentsfile.
EXPLANATION:
Internal net for pin appears bidirectional to Build Model as it contains an internal OUTPUT
and INPUT or an internal INOUT. Build Model converts the pin direction to INOUT to
represent this topology.
USER RESPONSE:
To prevent occurrence of this message, either modify the pin direction to INOUT or modify
the cell design.
WARNING (TEI-142): All pins on net netname of cell cellname appear to be sources.
This may cause creation of Verilog patterns with scanformat=parallel to fail. Cell
EXPLANATION:
All pins on the referenced net appear to be driving the net and there are no sink pins,
based on the pin directions specified in the design source and the relationship of the pin
to the net (internal net of cell versus external net of cell). This may result in an hierarchical
model tracing problem in downstream applications, but the flatModel and any test data
should be acceptable if it is able to be created. Creating Verilog patterns

(write_vectors) with scanformat=parallel is one application that is known to

have problems with this situation.
USER RESPONSE:
Analyze the net to determine whether this situation is intentional. If not intended, modify
the pin direction on one of the pins on the net so that not all of the pins will be sources
on the net. Rerun if necessary.
WARNING (TEI-143): All pins on net netname of cell cellname appear to be sinks. This
may cause creation of Verilog patterns with scanformat=parallel to fail. Cell contents
file: contentsfile.
EXPLANATION:
All pins on the referenced net appear to be sinks on the net and there are no source pins,
based on the pin directions specified in the design source and the relationship of the pin
to the net (internal net of cell versus external net of cell). This may result in a hierarchical
model tracing problem in downstream applications but the flatModel and any test data
should be acceptable if it is able to be created. Creating Verilog patterns
(write_vectors) with scanformat=parallel is one application that is known to
have problems with this situation.
USER RESPONSE:
Analyze the net to determine whether this situation is intentional. If not intended, modify
the pin direction on one of the pins on the net so that not all of the pins will be sinks on
the net. Rerun if necessary.
WARNING (TEI-144): Net netname has an invalid connection to pin pinname of cell
cellname. The pin has an ET_UNCONNECTED=internal | both attribute that
indicates it is not to be connected internally. Disconnect the net from this pin, or remove the
attribute, and rerun Build Model. Cell contents file: contentsfile.
EXPLANATION:
The ET_UNCONNECTED attribute is attached to pins that are to be intentionally left
unconnected. In this case, the net specified in the message is connected to the pin inside
the cell and there is an ET_UNCONNECTED attribute attached to this pin. This may
indicate that the net should have been connected to a different pin.
USER RESPONSE:
Verify that the net (wire) is connected to the correct pin. If the net is improperly
connected, correct the module that contains the cell definition and rerun Build Model. If
the net is properly connected, remove/change the ET_UNCONNECTED pin attribute to
allow connection inside the cell and rerun Build Model.

WARNING (TEI-145): Net netname of cellname1 has an invalid connection to pin

pinname on instance instance1 (usage of cellcellname2). Cell cellname2 has an
ET_UNCONNECTED=external | both attribute that indicates the pin is not to be
connected externally. Disconnect the net from this pin and rerun Build Model. Cell contents
file: cellname1 contentsfile. Cell contents file: cellname2 contentsfile.
EXPLANATION:
The ET_UNCONNECTED attribute is attached to pins that are to be intentionally left
unconnected. In this case, the net specified in the message is connected to the pin in a
manner that violates the ET_UNCONNECTED attribute attached to this pin. This will cause
lower test coverage and may also indicate that the net should have been connected to a
different pin.
USER RESPONSE:
Verify that the net (wire) is connected to the correct pin. If the net is improperly
connected, correct the netlist and rerun Build Model. If the net is properly connected,
verify that the definition of the cell with the pin attribute was selected from the correct
library (check the output in the Build Model log to see where the cell was found). If the
wrong cell definition was selected, change the order of the sources in the build_model
designsource/techlib keywords or move the cell definition to the correct place and
rerun Build Model. If the correct cell definition was selected, contact the owner of the cell
definition to understand why the pin attribute is defined; then either disconnect the net in
the netlist or have the library cell owner remove/change the pin attribute. Point to the
updated library cell definition/netlist and rerun Build Model.

INFO (TEI-154): Unable to uncompress file filename.
EXPLANATION:
This informational message indicates that the model application was unable to
uncompress the specified file.
USER RESPONSE:
If subsequent messages indicate a failure attempting to read the file, they are possibly
caused by a failure to uncompress the file. Verify that there is enough disk space for an
uncompressed version of this file. If there is enough space, contact customer support
INFO (TEI-155): Unable to compress file filename.

EXPLANATION:

This informational message indicates that the model application was unable to compress
the specified file.
USER RESPONSE:
No response required, but if the specified file is uncompressed after program exit and this
is not desired, contact customer support (see Contacting Customer Service on
page 23).
WARNING (TEI-160): Instance instance1 refers to undefined cell cellname1. The cell
will be created since blackbox=yes or allowincompletemodules=yes was
specified. Cell contents file: contentsfile.
EXPLANATION:
This message indicates that the instance instance1 in cellname1 has specified a
reference to an undefined cell in the model. The build_model command will attempt
to create the cell definition based on net and port connections that refer to the cell. The
created cell will be a blackbox cell.
USER RESPONSE:
No response is required unless creation of missing cells is not desired. If creation of
missing cells is not desired, include the cell definition in the design source and rerun
build_model specifying blackbox=no, allowincompletemodules=no, and
include the cell definition in the design source.
WARNING (TEI-161): Net netname of cell cellname1 refers to an undefined pin

pinname of cell cellname2. The pin will be created since blackbox=yes or
allowincompletemodules=yes was specified. Cell contents file: contentsfile.
EXPLANATION:
This message indicates that the pin specified in the message is a reference to an
undefined pin in the model for the cell shown. The blackbox=yes or
allowincompletemodules=yes build_model command options were
specified, therefore build_model will attempt to create the pin definition based on net
connections that refer to the pin.
USER RESPONSE:
No response required, unless creation of missing pins is not desired. If creation of
missing pins is not desired, rerun build_model with
allowincompletemodules=no, blackbox=no, and include the include the proper
pin definition in the design source.

WARNING (TEI-167): [Severe] Usage blkname with defname defname in cell

cellname converted to a logic primitive. Errors may occur during build_delaymodel.
EXPLANATION:
The defname specified matches the Encounter Test logic primitive naming rules. The
usage block is converted to an Encounter Test logic primitive.
USER RESPONSE:
If this block was intended to be a usage of a technology cell, either rename the defname
to something that does not match the Encounter Test logic primitive name rules or rerun
build_model after exporting TEI_VIM_PRIMITIVES=burlington into the
environment. Converting the usage block into a logic primitive may cause missing delays
during Encounter Test Delay Model Build.
WARNING (TEI-168): DEF defname contains TEIPERIOD string period

substitution string. This may cause problems with processing of this name in
downstream applications. It is strongly recommended that TEIPERIOD be changed to
something other than period substitution string and rerun Build Model.
EXPLANATION:
The identified DEF contains a string matching the TEIPERIOD (embedded period
substitution string) input parameter to Build Model. The default for this keyword is _p_.
Subsequent applications will convert each piece of the object name matching the
TEIPERIOD string into a period (.) before attempting to use the name. This will most
likely cause errors when attempting to use the name.
USER RESPONSE:
Rerun Build Model with a different TEIPERIOD value that does not appear within any
DEF, proto pin, usage block, or net name in the VIM.
WARNING (TEI-169): DEF Pin|Usage Block|Net of cell cellname contains

TEIPERIOD string period substitution string. This may cause problems with
processing of this name in downstream applications. It is strongly recommended that
TEIPERIOD be changed to something other than period substitution string and
then rerun Build Model. Cell contents file: contentsfile
EXPLANATION:
The identified proto pin, usage block, or net name contains a string matching the
TEIPERIOD (embedded period substitution string) input parameter to Build Model. The
default for this keyword is _p_. Subsequent applications will convert each piece of the
object name matching the TEIPERIOD string into a period (.) before attempting to use
the name. This will most likely cause errors when attempting to use the name.

USER RESPONSE:
Rerun Build Model with a different TEIPERIOD value that does not appear within any
DEF, proto pin, usage block, or net name in the VIM.
INFO (TEI-170): Usage blockname with defname defname in cell cellname appears
to be a primitive but has either an incorrect number of input pins, output pins, or both. Build
Model continues expecting to find a user-specified definition for the cell. Cell contents file:
contentsfile.
EXPLANATION:
Usage has a defname that is recognized as a reserved Encounter Test primitive name.
However, the usage does not satisfy the Encounter Test primitive definition. If the
defname is not intended to be an Encounter Test primitive, a DEF and contents file
should be available for build_model for further processing.
USER RESPONSE:
If the usage is not intended to be an Encounter Test primitive and a DEF and contents file
are available, no action is necessary. Otherwise, correct the defname or the pin
specifications and rebuild the model.
WARNING (TEI-171): Usage blockname in cell cellname appears to be a RAM or ROM

primitive but PORT, PTYPE, or BIT attribute is not specified for all pins. This data must be
specified for all pins to correctly model the instance. Build Model continues and will attempt
to treat the instance as a hierarchical block. Cell contents file: contentsfile.
EXPLANATION:
The usage specified in the message has a cell name that begins with ram or rom. Build
Mode assumes that it is a RAM or ROM primitive and expects PORT, PTYPE, and BIT
attributes on the usages pins. These attributes were not found. Build Model will now
attempt to treat it as a hierarchical block and continue. If unsuccessful, additional error
messages should appear.
USER RESPONSE:
No response is required if the usage is truly a hierarchical block and not a RAM/ROM
primitive. The absence of additional error messages will mean that Build Model was able
to build the model assuming this usage is a hierarchical block. If additional errors occur,
they must be addressed. If the instance is intended to be a RAM/ROM primitive, specify
the PORT, PTYPE, and BIT attributes in the design source and rebuild the model.
WARNING (TEI-172): Usage blockname in cell cellname appears to be a LATCH

primitive but PTYPE is not specified for all pins. This data must be specified for all pins to

correctly model the instance. Build Model continues and will attempt to treat the instance as
a hierarchical block. Cell contents file: contentsfile.
EXPLANATION:
The usage block specified in the message has a defname that begins with latch. Build
Model assumes that it is a Latch primitive and expects the PTYPE attribute on the blocks
pins. The attribute was not found. Build Model will now attempt to treat it as a hierarchical
block and continue. If unsuccessful, additional error messages should appear.
USER RESPONSE:
No response is required if the usage is truly a hierarchical block and not a LATCH
primitive. The absence of additional error messages will mean that Build Model was able
to build the model assuming this usage is a hierarchical block. If additional errors occur,
they must be addressed. If the usage is intended to be a LATCH primitive, specify the
PTYPE attribute in the design source and rebuild the model.
WARNING (TEI-173): Usage blockname in cell cellname has a defname of

TSD|NFET|PFET but the PTYPE attribute is missing from the input pins on the Usage. This
attribute must be specified for a TSD|NFET|PFET to correctly model the Usage. Correct the
defname or add the PTYPE attribute. Build Model continues and stores the usage as a
hierarchical block. Cell contents file: contentsfile.
EXPLANATION:
The usage block specified in the message has a defname that begins with
TSD|NFET|PFET. Build Model assumes that it is a TSD|NFET|PFET primitive and
expects the PTYPE attribute on the blocks pins. The attribute was not found. Build Model
will now attempt to treat it as a hierarchical block and continue. If unsuccessful, additional
error messages should appear.
USER RESPONSE:
No response is required if the usage is truly a hierarchical block and not a
TSD|NFET|PFET primitive. The absence of additional error messages will mean that
Build Model was able to build the model assuming this usage is a hierarchical block. If
additional errors occur, they must be addressed. If the usage is intended to be a
TSD|NFET|PFET primitive, specify the PTYPE attribute in the design source and rebuild
the model.
INFO (TEI-174): Usage pin pinname on LATCH Usage blockname in cell cellname
has invalid PORT name portname specified. Correct PORT attribute and ensure PORT/
PTYPE attributes are also set for each pin on the Usage. These attributes must be specified
to correctly model the LATCH block. Build Model continues and stores the Usage as
modified cellname in the hierarchical model. Cell contents file: contentsfile.

EXPLANATION:
Usage has a defname (LATCH) that is recognized as a reserved Encounter Test primitive
name. However, the usage does not satisfy the Encounter Test primitive definition. The
PORT attribute has an invalid value.
Defname is modified and a DEF is generated to allow completion of the logic model.
This results in this usage being an X-generator.
USER RESPONSE:
Correct the PORT attribute and ensure all other LATCH requirements are met. Rebuild the
model.
does not have PTYPE attribute. This attribute must be specified for a LATCH to correctly model
the Usage. If this is a multi-port LATCH, a PORT attribute must also be specified on each input
pin. Build Model continues and stores the Usage as modified cellname in the
hierarchical model. Cell contents file: contentsfile.
EXPLANATION:
PTYPE attribute has not been specified. All pins on a LATCH must have the PTYPE
attribute specified as DATA or CLOCK to identify the function of the pin to correctly model
the Usage. If this is a multi-port LATCH, a PORT attribute must also be specified on each
input pin.
USER RESPONSE:
Correct all errors for this LATCH and rebuild the model.
has invalid PTYPE attribute value of ptypevalue. All pins on a LATCH must have the PTYPE
attribute specified as DATA or CLOCK to correctly model the Usage. If this is a multi-port
LATCH, a PORT attribute must also be specified on each input pin. Build Model continues and
stores the Usage as modified cellname in the hierarchical model. Cell contents file:
contentsfile.
EXPLANATION:

PTYPE attribute has been specified with an invalid value. All pins on a LATCH must have
the PTYPE attribute specified as DATA or CLOCK to identify the function of the pin to
correctly model the Usage. If this is a multi-port LATCH, a PORT attribute must also be
specified on each input pin.
USER RESPONSE:
INFO (TEI-177): Usage blockname in cell cellname has a defname of LATCH but does
not have the proper attributing of pins. All pins on a LATCH must have a PTYPE attribute
specified as DATA or CLOCK to correctly model the Usage. If this is a multi-port LATCH, a
PORT attribute must also be specified on each input pin. Build Model continues and stores the
Usage as modified cellname in the hierarchical model. Cell contents file:
contentsfile.
EXPLANATION:
name. However, the usage does not satisfy the Encounter Test primitive definition. All
pins on a LATCH must have the PTYPE attribute specified as DATA or CLOCK to identify
the function of the pin to correctly model the Usage. If this is a multi-port LATCH, a PORT
attribute must also be specified on each input pin.
USER RESPONSE:
INFO (TEI-178): Usage pin pinname on TSD|NFET|PFET Usage blockname in cell

cellname does not have PTYPE attribute. TSD|NFET|PFET blocks must have a PTYPE
attribute in each input pin to identify the function (either DATA or ENABLE|NGATE|PGATE)
of the pin. Specify PTYPE attribute and rerun. Build Model continues and stores the Usage as
EXPLANATION:
However, the usage does not satisfy the Encounter Test primitive definition. The PTYPE

attribute has not been specified. All pins must have the PTYPE attribute specified with the
appropriate values. A TSD must have DATA and ENABLE. A NFET must have DATA and
NGATE. A PFET must have DATA and PGATE.
USER RESPONSE:
Correct all errors for this Usage and rebuild the model.
INFO (TEI-179): Usage pin pinname on TSD|NFET|PFET Usage blockname in cell

cellname has invalid PTYPE attribute value of ptypevalue. TSD|NFET|PFET blocks
must have a PTYPE attribute in each input pin to identify the function (either DATA or
ENABLE|NGATE|PGATE) of the pin. Specify PTYPE attribute and rerun. Build Model
continues and stores the Usage as modified cellname in the hierarchical model. Cell
EXPLANATION:
However, the usage does not satisfy the Encounter Test primitive definition. The PTYPE
attribute has been specified with an invalid value. All pins must have the PTYPE attribute
specified with the appropriate values. A TSD must have DATA and ENABLE. A NFET must
have DATA and NGATE. A PFET must have DATA and PGATE.
USER RESPONSE:
INFO (TEI-180): Usage blockname in cell cellname has a defname of

TSD|NFET|PFET but does not have the proper attributing (DATA and
ENABLE|NGATE|PGATE) on its pins. Respecify PTYPE attributes and rerun. Build Model
EXPLANATION:
However, the usage does not satisfy the Encounter Test primitive definition. All pins must
have the PTYPE attribute specified with the appropriate values. A TSD must have DATA
and ENABLE. An NFET must have DATA and NGATE. A PFET must have DATA and
PGATE.

USER RESPONSE:
INFO (TEI-181): Usage pin pinname on RAM|ROM Usage blockname in cell cellname
does not have PORT or PTYPE attribute specified. RAM|ROM blocks must have a PORT and
PTYPE attribute for each input pin to identify the function of the pin. Specify PORT and PTYPE
attribute and rerun. Build Model continues and stores the Usage as modified cellname
in the hierarchical model. Cell contents file: contentsfile.
EXPLANATION:
However, the usage does not satisfy the Encounter Test primitive definition. The PORT
and PTYPE attributes have not been specified. All pins must have a PORT and PTYPE
attribute specified with the appropriate values.
USER RESPONSE:
has invalid PORT attribute value portvalue specified. Correct PORT attribute (1 to
maxports) and ensure PORT/PTYPE/BIT attributes are also specified for each pin on the
Usage. Build Model continues and stores the Usage as modified cellname in the
EXPLANATION:
However, the usage does not satisfy the Encounter Test primitive definition. An invalid
PORT value has been specified. All pins must have a PORT, PTYPE, and BIT attribute
specified with the appropriate values.
USER RESPONSE:

has invalid PTYPE attribute value ptypevalue specified. Correct PTYPE attribute (ADDR,
DATA, READ, CLOCK) and ensure PORT/PTYPE/BIT attributes are also specified for each pin
on the Usage. Build Model continues and stores the Usage as modified cellname in
the hierarchical model. Cell contents file: contentsfile.
EXPLANATION:
PTYPE value has been specified. All pins must have a PORT, PTYPE, and BIT attribute
specified with the appropriate values.
USER RESPONSE:
does not have a BIT attribute specified. This data must be specified for all address
(PTYPE=ADDR) and data (PTYPE=DATA) input pins. Build Model continues and stores the
contentsfile.
EXPLANATION:
However, the usage does not satisfy the Encounter Test primitive definition. A BIT
attribute value has not been specified. All pins must have a PORT, PTYPE, and BIT
USER RESPONSE:
has an invalid BIT attribute value bitvalue specified. Correct BIT attribute (0 to
maxbits) and ensure PORT/PTYPE/BIT attributes are also specified for each pin on the
Usage. Build Model continues and stores the Usage as modified cellname in the

EXPLANATION:
BIT attribute value has been specified. All pins must have a PORT, PTYPE, and BIT
USER RESPONSE:
does not have PORT, PTYPE, or BIT attributes specified. RAM|ROM blocks must have a
PORT/PTYPE/BIT attribute for each output pin to identify the function of the pin. Specify
PORT/PTYPE/BIT attributes and rerun. Build Model continues and stores the Usage as
EXPLANATION:
However, the usage does not satisfy the Encounter Test primitive definition. The PORT/
PTYPE/BIT attributes have not been specified. All output pins must have a PORT/
PTYPE/BIT attribute specified with the appropriate values.
USER RESPONSE:
INFO (TEI-187): Usage blockname in cell cellname is a multi-port RAM/ROM with

conflicting PORT definitions. PORT portnumber has numaddr1 address inputs which
conflicts with numaddr2 address inputs defined for the previous PORTs. Respecify usage
and rerun. Build Model continues and stores the Usage as modified cellname in the
EXPLANATION:
However, the usage does not satisfy the Encounter Test primitive definition. The
specified PORT/PTYPE/BIT attributes have created a conflict between PORTs.


USER RESPONSE:

conflicting PORT definitions. PORT portnumber has numdata1 data inputs which conflicts
with numdata2 data inputs defined for the previous PORTs. Respecify usage and rerun.
Build Model continues and stores the Usage as modified cellname in the hierarchical
model. Cell contents file: contentsfile.
EXPLANATION:
USER RESPONSE:
INFO (TEI-189): Usage blockname in cell cellname is a multi-port RAM/ROM with an

invalid PORT definition. PORT portnumber has number readenable|writeclock
inputs defined. There should only be 1 defined. Respecify usage and rerun. Build Model
EXPLANATION:
However, the usage does not satisfy the Encounter Test primitive definition. There are
too many read enable input pins defined for a PORT.
USER RESPONSE:

conflicting PORT definitions. PORT portnumber has numdata1 data outputs which
conflicts with numdata2 data outputs defined for the previous PORTs. Respecify usage and

rerun. Build Model continues and stores the Usage as modified cellname in the
EXPLANATION:
USER RESPONSE:

conflicting PORT definitions. num1 data inputs have been defined which conflicts with num2
data outputs for the PORTs. Respecify usage and rerun. Build Model continues and stores the
contentsfile.
EXPLANATION:
USER RESPONSE:
WARNING (TEI-192): Cell cellname appears to be a primitiveTye, but

reasonString.
EXPLANATION:
The indicated cell name is recognized as a reserved Encounter Test primitive or primitive
type, however the cell name does not satisfy the Encounter Test primitive definition.
The accompanying reason string identifies the failing condition.
This results in all usages of this cell name to be treated as a blackbox.
USER RESPONSE:

If necessary, correct this condition and rebuild the model.
WARNING (TEI-193): Cell cellname fails port name checking. reasonString.

EXPLANATION:
The indicated cell name is recognized as a reserved Encounter Test primitive name
requiring specific port naming conventions, however the cell name does not satisfy the
Encounter Test primitive definition.
The accompanying reason string identifies the failing condition.
This results in all usages of this cellname to be treated as a blackbox.
USER RESPONSE:
If necessary, correct this condition and rebuild the model.
INFO (TEI-195): Build Model - Controller starting:

EXPLANATION:
Build Model Controller controls the flow through the many steps of build_model.
USER RESPONSE:
No user response is required.
INFO (TEI-196): Build Model - Hierarchical Model Build starting:

EXPLANATION:
Collection of input design information has completed. The process of creating the
hierarchical model is beginning.
USER RESPONSE:
INFO (TEI-197): Build Model - Hierarchical Model Build completed.

EXPLANATION:
The process of creating the hierarchical model is complete.
USER RESPONSE:
INFO (TEI-198): Build Model - Flat Model Build starting:

EXPLANATION:
The process of creating the flattened model is beginning.
USER RESPONSE:
INFO (TEI-199): Build Model - Flat Model Build completed.

EXPLANATION:
The process of creating the flattened model is completed.
USER RESPONSE:
INFO (TEI-200): Build Model: Controller completed.

EXPLANATION:
Build model has completed.
USER RESPONSE:
INFO (TEI-201): Build core migration model completed.

EXPLANATION:
Build Core Migration Model has completed processing.
USER RESPONSE:
WARNING (TEI-204): [Severe] Verilog parser: Unrecognized syntax on line

line_number :text
EXPLANATION:
The Verilog parser has found a character or character sequence that it does not
understand or support on the line number shown. The file name being parsed should
have been displayed in a previous message.
USER RESPONSE:

Fix the syntax error and re-run Build Model. If you believe the syntax is valid and should
be supported, contact customer support (see Contacting Customer Service on
page 23).
WARNING (TEI-205): [Severe] Attribute data will not be included in the logic model. File
filename contains only Encounter Test format attributes which are not processed when
vlogparser=IEEEstandard is used on the build_model command line. Add
IEEEstandard attributes to the file or remove vlogparser from the command line.
EXPLANATION:
Encounter Test attribute syntax //! attr="value" has been found in the Verilog file
without any IEEEstandard Verilog attribute syntax, (* attr="value" *).
Encounter Test attribute syntax is not processed when vlogparser=IEEEstandard.
This results in missing attribute data in the logic model.
USER RESPONSE:
Verify if this attribute data is required for processing of the logic model. If so, either add
the IEEEstandard attributes to the file, or remove keyword vlogparser from the
build_model command line to include these attributes in the logic model.
ERROR (TEI-206): Usage of parameter parameter name with value parameter

value found on line line number of file Verilog file name. A positive integer value
is expected. Processing terminates.
EXPLANATION:
Build Model expects a positive integer value for this usage of the referenced parameter.
The current value of the parameter creates an ambiguity that cannot be resolved to allow
building of a correct model and causes Build Model to terminate.
USER RESPONSE:
Redefine the value of the parameter to be an integer value or remove the parameter and
replace it with a positive integer value and then rerun Build Model.
WARNING (TEI-207): Parameter parameter name with a real number value found on
line line number of file Verilog file name. A positive integer is expected.
Processing continues using parameter value for the parameter value.
EXPLANATION:
Build Model expects a positive integer value for the referenced parameter. A real number
was specified for the value. Build Model truncates the decimal portion of the real number
and uses the integer portion of the value. Processing continues using the truncated value
of the parameter.

USER RESPONSE:
Ensure that the result is as expected. If not, redefine the value of the parameter to be a
positive integer value or remove the parameter and replace it with a positive integer value
and then rerun Build Model if necessary.
ERROR (TEI-208): Invalid operation encountered on line line number of file Verilog
file name. A positive integer value is expected as the output of this operation. Processing
terminates.
EXPLANATION:
The Verilog parser expects a positive integer value of the operation performed on the line
referred to in the message. The invalid operation could be one of the following:
Operation resulting in a negative integer value.
Division by zero.
Usage of a non-supported mathematical operator. The supported mathematical
operators are Addition, Subtraction, Multiplication, Division, and Modulus.
Usage of a non-supported type with mathematical operators. Only parameters
can be used with mathematical operators.
USER RESPONSE:
Correct the operation to get a positive integer value or remove the parameter and replace
it with an integer value and rerun Build Model.
ERROR (TEI-209): Invalid multi-concatenation operation encountered on line line

number of file Verilog file name. Processing terminates.
EXPLANATION:
The multiConcatenation operation performed on the parameter on the line referred
to in the message is invalid. The multiplication factor should be one of the following:
A parameter: Only the leftmost multiplication factor can be a parameter.
Integer
Hexadecimal/Octal
The right-most operand can only be a binary value.
USER RESPONSE:
Correct themultiConcatenation operation per the guidelines in the preceding
explanation to get a valid parameter value and rerun Build Model.

INFO (TEI-210): Resolving interface for cellname from file filename.

EXPLANATION:
The Verilog parser has found an instance of a cellname. In order to bind the instance
of the cellname with the cell definition, the Verilog parser must find the definition of
cellname. cellname cell was not defined in the same Verilog file as the higher level
cell, but the Verilog parser found a definition of the lower level cell in the referenced
filename.
USER RESPONSE:
WARNING (TEI-211): Failed to resolve interface for cell cellname.

EXPLANATION:
The Verilog parser has found an instance of a lower level cell, cell, cellname. In order
to bind the instance of the cell with the cell definition, the Verilog parser must find the
definition of the cell. The lower level cell was not defined in the same Verilog file as the
higher level cell. The Verilog parser has checked the directory which the higher level cell
comes from for files of the form cellname.v, cellname.v.Z, cellname, and
cellname.Z, but no such file exists.
The Verilog parser will attempt to continue by assuming that all pins of the lower level cell
are bidirectional pins. In the case where the original instance of the cell uses positional
binding, the Verilog parser will create pin names for the lower level cell arbitrarily.
The resulting hierarchical model is probably incorrect.
USER RESPONSE:
Add a definition of at least the interface for the specified cell in the same directory as the
higher level cell, and rebuild the model.
WARNING (TEI-212): Module cellname defined on line linenumber of file filename

was defined previously.
EXPLANATION:
The Verilog parser found a Verilog module for which a definition had already been found.
The second (and subsequent) definitions of the module will be ignored.
USER RESPONSE:
Check the Verilog files used for this design to determine if the duplicate definitions for cell
are different. If they are different, make sure that the correct definition of cell is used first
by the Verilog parser.

WARNING (TEI-213): A gate instantiation of TRAN on line linenumber of file filename

from cell cellname cannot be modeled. substituteCell will be substituted.
EXPLANATION:
Cell cell has an instance of a Verilog TRAN gate, which is defined in Verilog as a bi-
directional transistor. Encounter Test does not support bi-directional transistors. A uni-
directional buffer primitive (shown in the message) will be substituted for the TRAN gate
in the Encounter Test model.
USER RESPONSE:
Analyze cell to determine the effects of converting a bidirectional transistor into a uni-
directional transistor. If the effects are significant,change the modeling of the cell to
explicitly model both the forward and reverse path through the transistor with uni-
directional transistor primitives.
WARNING (TEI-214): A gate instantiation of RTRAN on line linenumber of file

filename from cell cellname cannot be modeled. substituteCell will be substituted.
EXPLANATION:
Cell cell has an instance of a Verilog RTRAN gate, which is defined in Verilog as a bi-
directional transistor. Encounter Test does not support bi-directional transistors. A uni-
directional primitive (shown in the message) will be substituted for the RTRAN gate in the
USER RESPONSE:
Analyze the cell to determine the effects of converting a bidirectional transistor into a uni-
directional transistor. If the effects are significant, change the modeling of the cell to
WARNING (TEI-215): A gate instantiation of TRANIF0 on line linenumber of file

EXPLANATION:
Cell cellname has an instance of a Verilog TRANIF0 gate, which is defined in Verilog
as a bi-directional transistor. Encounter Test does not support bi-directional transistors.
A uni-directional primitive (shown in the message) will be substituted for the TRANIF0
gate in the Encounter Test model.
USER RESPONSE:

WARNING (TEI-216): A gate instantiation of RTRANIF0 on line linenumber of file

EXPLANATION:
Cell cellname has an instance of a Verilog RTRANIF0 gate, which is defined in Verilog
A uni-directional primitive (shown in the message) will be substituted for the RTRANIF0
gate in the Encounter Testmodel.
USER RESPONSE:
WARNING (TEI-217): A gate instantiation of TRANIF1 on line linenumber of file

EXPLANATION:
Cell cellname has an instance of a Verilog TRANIF1 gate, which is defined in Verilog
A uni-directional primitive (shown in the message) will be substituted for the TRANIF1
gate in the Encounter Test model.
USER RESPONSE:
WARNING (TEI-218): A gate instantiation of RTRANIF1 on line linenumber of file

EXPLANATION:
Cell cellname has an instance of a Verilog RTRANIF1 gate, which is defined in Verilog
A uni-directional primitive (shown in the message) will be substituted for the RTRANIF1
gate in the Encounter Testmodel.
USER RESPONSE:

directional transistor primitives..
WARNING (TEI-219): Parameterized instances not supported in Encounter Test. Line

linenumber of file filename, cell cellname1 usage of cell cellname2.
EXPLANATION:
Cell cellname1 uses cell cellname2 and attempts to alter the definition of
cellname2 through the use of Verilog parameters. Encounter Test does not support
such a usage. The parameters will be ignored.
USER RESPONSE:
Remove paramaterized modules from your Verilog library. Replace them with expanded
versions of the module.
WARNING (TEI-220): [Severe] Verilog Parse Problem: problem

Input line number : linenumber
Input File : filename
Working on cell : cellname
Last String Processed: string
EXPLANATION:
The Encounter Test Verilog parser encountered an unrecognized or invalid Verilog
syntax while trying to parse file filename. The syntax error occurred on line
linenumber of file filename. The last recognized name while parsing was
string.
The Verilog parser will skip the rest of the cell definition for this cell and look for another
cell in the same file.
If several consecutive errors are encountered, the Verilog parser will stop attempting to
parse the file.
USER RESPONSE:
Check the syntax of the Verilog in file filename at line linenumber. If the syntax is
not correct, fix the Verilog file and rebuild the model. If the syntax is correct, contact


WARNING (TEI-221): Invocation of an XOR with greater than 256 input pins.. Cell
cellname may be left undefined.
EXPLANATION:
The Verilog contains an instance of an XOR gate that has more than 256 input pins.
Encounter Test restricts XOR primitives to 256 or less input pins. The Verilog parser has
created cell cellname, but has not defined its contents. If no definition of the contents
of cell appears in the Import search order, the cell will be treated as a behavioral.
USER RESPONSE:
Create a definition of the cell which provides the necessary XOR function, and make sure
the definition of the cell appears in the Build Model search order.
ERROR (TEI-222): Usage of defparam and specparam is not supported on line line
number of file Verilog file name. Only module parameters are expected. Processing
terminates.
EXPLANATION:
Usage of defparam or specparam for defining parameters is not supported and causes
Build Model to terminate.
USER RESPONSE:
Change the type of parameter from defparam or specparam to a module parameter
and rerun Build Model.
INFO (TEI-223): Pin pinname declared as input|output|inout on line

linenumber of file filename did not appear in the cellname module header list.
EXPLANATION:
Pin pinname appears in an input, output, or inout statement at line linenumber of
file filenumber and did not appear in the module statement for the module.
Encounter Test will create the pin despite the inconsistency.
USER RESPONSE:
Ensure that the pin is an I/O pin of the module. Update the definition of the module to
avoid this message in the future.
WARNING (TEI-224): Module cellname1 is instantiated in module cellname2 but has

not been defined.

EXPLANATION:
Module cellname2 instantiates a usage of cell cellname1, but the Verilog parser
could not find a definition for cellname1. The Verilog parser will attempt to create an
interface for cellname1 to bind the usage.
USER RESPONSE:
Ensure that at least the interface for each cell used in a Verilog file is defined in the same
directory as the original file.
WARNING (TEI-225): Instance instance1 of module cellname1 from cellname2

position pinposition connects net netname to an undefined pin. Creating new pin
pinname for cell cellname1.
EXPLANATION:
Cell cellname2 contains an instance of cell cellname1 which refers to the pins of
cellname1 positionally. In the definition of cellname1, there is no pin in position
pinposition. In order to completely bind from cellname2 to cellname1, the
Verilog parser must create a new pin for position pinposition. The Verilog parser will
create a pin named pinname with a direction of inout in an attempt to continue.
The pin that the Verilog parser creates will allow Build Model to continue, but is probably
incorrect.
USER RESPONSE:
Fix either the instance instance1 in cell cellname2 or the definition of cell
cellname1 so that the number of pins matches and then rebuild the model.
WARNING (TEI-226): Instance instance1 of module cellname1 from cellname2

fails to reference pin pinname.
EXPLANATION:
Cell cellname2 contains instance instance1 of cell cellname1, in which the
usage of pins in cellname1 are referred to positionally. There are more pins defined in
the definition of cell cellname1 than appear in the instance instance1.
The Verilog parser leaves the remaining pins of cellname1 unconnected, which is
probably incorrect.
USER RESPONSE:
Fix either the instance instance1 in cell cellname2 or the definition of cell
cellname1 so that the number of pins matches and then rebuild the model.

WARNING (TEI-227): Reference to arrayed port specifies more nets than bus entries. From
module cellname1 to instance instance1 to cellname2 port reference
arrayed_port. Failed on net netname.
EXPLANATION:
Cell cellname1 contains instance instance1 of cell cellname2, in which a
bussed net connects to arrayed port arrayed_port. There are more nets in the
bussed net than members of arrayed_port. Encounter Test connects as many
strands of the bussed net to the arrayed port as possible.
However, a strand net of the bussed net cannot be connected to a port.
USER RESPONSE:
Change either the number of ports in arrayed_port in the definition of cell
cellname2 or change the number of strands in the bussed net in cellname1 so that
they match and then rebuild the model.
WARNING (TEI-228): Instance instance1 in cell cellname1 refers to an undefined pin

pinname of cell cellname2. A bidirectional pin will be created.
EXPLANATION:
Instance instance1of cell cellname1 refers to explicit pin names of cell
cellname1. Instance instance1has referred to pin pinname which is not defined
by cell cellname2.
Encounter Test will create a new pin with name pinname and a pin direction of inout
in order to complete the binding process. This is probably incorrect.
USER RESPONSE:
Change either the definition of cellname2 to the pin pinname or change the instance
instance1 to remove the reference to pin pinname and then rebuild the model.
INFO (TEI-229): The Verilog source contains Verilog compiler directives to modify the faults
created. Build Model ignores these directives.
EXPLANATION:
The Verilog compiler directives for modifying faults are not supported. They will be
ignored during Build Model.
USER RESPONSE:
None required. To modify Encounter Test faults, use the Encounter Test properties and/
or define pattern faults. Refer to the Encounter Test: Guide 1: Models for details.

WARNING (TEI-230): [Severe] Design source path search_path is VIM, but the VIM
design source language is not supported on the SunOS Solaris platform. The VIM path is not
processed.
EXPLANATION:
The Build Model VIM parser is not supported on SunOS Solaris platform. The VIM path
in the message is not used to build the model.
Build Model attempts to continue but most likely will not be able to build the model due
to missing cells from the VIM. If blackbox=yes is specified, the missing cells will be
created as blackboxes.
USER RESPONSE:
Choose an Encounter Test platform that supports VIM to build a VIM model.
WARNING (TEI-232): [Severe] File filename1 was found when searching for cell
cellname1. Input source type of EDIF is no longer supported. File is ignored. Processing
continues.
EXPLANATION:
An input file of EDIF source was found when searching for cellname1. EDIF is no
longer supported as an input source type. EDIF file is ignored. Processing continues to
look for another source type for cellname1. This may result in a failing condition, or a
blackbox being built for cellname1.
USER RESPONSE:
None required unless the EDIF source identified is expected to be required to provide
contents description for cellname1. If so, please provide an alternate description of
cellname1 using a source type that is supported by Encounter Test.
WARNING (TEI-240): [Severe] Processing User Defined Primitive udpname, simulation

of state table row rownumber, input states state1 resulted in a value of value1. A value
of value2 was specified in the state table. Generated logic or User Defined Primitive state
table may be incorrect.
EXPLANATION:
The User Defined Primitive (UDP) state table is simulated using the gate-level model that
was created during Build Model. Row rownumber specified that an input state of
state1 should result in the logic value value1, but a value of value2 was produced
instead. This may be caused by the following reasons:
A conflict exists in the state table. Two rows specify the same input states, but
a different output value.

Incorrect entries exist in the state table. Enough of the state table is correct to
derive the gate-level representation properly, but a few entries specify behavior
inconsistent with the rest of the table.
Encounter Test cannot model the desired function using Encounter Test
primitives. One example of this is a function that produces a 1 whenever the
input is at a known state (0 or 1), and produces a 0 when the input is at X.
There is a limitation or bug in the algorithm that creates the logic from the UDP.
USER RESPONSE:
View the generated logic using the Encounter Test Graphical User Interface and
determine whether the error is in the generated logic or in the User Defined Primitive
(UDP) state table. If the error is in the UDP, state table, correct the UDP and rebuild the
model. If the generated logic is incorrect, and the function cannot be modeled using
Encounter Test primitives, you can override the generated logic by creating a black-box
cell with the same name as the UDP (using an design source format such as Verilog or
EDIF), and including it ahead of the UDP in the Import search order. If the logic can be
modeled correctly using Encounter Test primitives please contact customer support (see
WARNING (TEI-241): Processing User Defined Primitive udpname, simulation of state

table row rownumber, input state state1 resulted in a value of X. A value of value1 was
specified in the state table. Generated logic may be pessimistic.
EXPLANATION:
The User Defined Primitive (UDP) state table is simulated using the gate-level model that
was created during Build Model. Row rownumber specified that an input state of
state1 should result in the logic value value1, but a value of X was produced instead.
This may be caused by the following reasons:
By default, Encounter Test produces logic models that avoid redundancy and at
times may be pessimistic. An example of this is a 2-1 MUX. If the UDP contains
a row that produces a known value for the MUX when the select pin is at X, the
logic necessary to model this behavior is redundant with the rest of the logic and
is not included in the model by default.
Incorrect entries exist in the state table. Enough of the state table is correct to
derive the gate-level representation properly, but a few entries specify behavior
inconsistent with the rest of the table.
Modeling of sequential UDPs uses Encounter Test latch primitives. In
Encounter Test, a latch may produce an X in cases such as when clocks to two
or more ports are active at the same time but their data values differ, or when a
clock is at X and the data value on the port does not match the previous value

in the latch. This modeling may be inconsistent with the UDP state table
specification.
Encounter Test cannot model the desired function completely using Encounter
Test primitives.
There is a limitation or bug in the algorithm that creates the logic from the UDP.
USER RESPONSE:
determine whether there is an error in the generated logic, there is an error in the User
Defined Primitive (UDP) state table, or the logic generated is pessimistic. If there is an
error is in the UDP state table, correct the UDP and rebuild the model. If the generated
logic is pessimistic, you may be able to generate a non-pessimistic version of the logic
by using the command line option udppessimistic. If the generated logic is not
modeled correctly, please contact customer support (see Contacting Customer Service
on page 23).
WARNING (TEI-242): Processing User Defined Primitive udpname, state table row
rownumber1, input states state1, output value value1, and state table row
rownumber2, input states state2, output value value2, appear to conflict when the input
state is state3. Generated logic or User Defined Primitive state table may be incorrect.
EXPLANATION:
When processing the User Defined Primitive (UDP) state table, values of X are replaced
where possible with both 0 and 1. Row rownumber1 contains Xs that were replaced,
creating state state3 with an output value of value1. Row rownimber2 contains
Xs that were replaced creating the same state, but with output value value2.
The apparent conflict may cause additional warnings or severe errors when processing
the UDP.
USER RESPONSE:
determine if there is an error in the generated logic, or if there is an error in the User
Defined Primitive (UDP) state table. If there is an error is in the UDP state table, correct
the UDP and rebuild the model. If the generated logic is correct, you may ignore this
message. If the generated logic is not modeled correctly, please contact customer
ERROR (TEI-243): Design contains n1 levels of hierarchy. A maximum of n2 is allowed.

Remove enough levels of hierarchy to fit within the limit and rebuild the model.
EXPLANATION:

Encounter Test allows n2 levels of hierarchy in a design. This design contains n1 levels.
The hierarchy of the cells that exceed the Encounter Test limit is listed along with the
message. Starting with the top level cell, each cell used (instanced) by the top level cell
that causes the limit to be exceeded is listed. Its contents are also listed (only those cells
within it that also cause the limit to be exceeded) the first time that cell is referenced in
the hierarchy.
USER RESPONSE:
Determine where the hierarchy can be flattened to fit within the Encounter Test limit.
Update the design source appropriately and rebuild the model.
INFO (TEI-244): Modeling constraint attribute: expression as instance instance1 of

cell constraintcellname within cell containingcellname.
EXPLANATION:
Build Model has detected a CONSTRAINT=expression attribute on cell
containingcellname. The constraint expression has been modeled in a cell named
constraintcellname and a usage (instance) if this cell has been added to cell
containingcellname. Refer to Constraints Files in the Encounter Test: Guide
1: Models for additional information.
USER RESPONSE:
WARNING (TEI-245): Cannot parse constraint attribute: expression on cell cellName.

Constraint attribute is ignored.
EXPLANATION:
The constraint attribute could not be processed, most likely due to a syntax error in the
definition of the attribute. The constraint specified by the attribute is not modeled in the
design.
USER RESPONSE:
Correct the error and rebuild the model.
INFO (TEI-246): Cell cellname read from file filename

EXPLANATION:
This message provides specific information about the source file for a Verilog cell.
USER RESPONSE:

WARNING (TEI-247): Cell cellname contained an error. Resuming on line linenumber

of file filename
EXPLANATION:
An error occurred while processing the Verilog source for the cell specified. The Verilog
parser will skip the rest of this cell definition, and continue parsing the Verilog file at the
specified line number.
USER RESPONSE:
Check for previous messages which give more detail about the error. Correct the error
and rebuild the model.
WARNING (TEI-248): Assignment statement on line linenumber of file filename does

not have the same number of strands on the left side of the equals sign as the right side. Net
netname will not be connected.
EXPLANATION:
An assignment statement in Verilog causes a logical connection between two busses or
nets. In this case, there were either more strands of the bus on the left hand side of the
equals sign than the right hand side, or vice versa. Encounter Test will connect all
matching strands, but some strands will remain unconnected.
USER RESPONSE:
Check the Verilog source in the specified file and line number, and correct the
assignment statement so that the number of strands on the left side of the equals sign is
the same as the number of strands on the right side.
INFO (TEI-249): Interface for cell cellname derived from primitive declaration on line
linenumber of file filename
EXPLANATION:
More information on the source of a user defined primitive.
USER RESPONSE:
INFO (TEI-250): Interface for cell cellname derived from usage on line linenumber of
file filename
EXPLANATION:
More information on the source of a gate level cell or the usage of a module which is not
defined in Verilog.

USER RESPONSE:
WARNING (TEI-251): Module cellname1, instance instance1 of cell cellname2

position pinposition pin pinname is not connected.
EXPLANATION:
In the Verilog source, a bussed net in cellname1 is connected to a bussed pin of
cellname2, but there are more strands defined for the bussed pin of cell cellname2
than there are strands of the net in cell cellname1. Encounter Test will leave the extra
strands of the bussed pin, defined by pinname, unconnected.
USER RESPONSE:
Check the Verilog source to determine why there are a different number of strands in the
net of cellname1than the number of strands of the bussed pin cellname2. Correct
the problem, and rebuild the model.
WARNING (TEI-252): Module cellname1, instance instance1 of cell cellname2

position pinposition net netname is not connected.
EXPLANATION:
In the Verilog source, a bussed net in cellname1 is connected to a bussed pin of the
cellname2, but there are more strands defined for the bussed net of cellname1 than
there are strands of the pin in cellname2. Encounter Test will leave the extra strands
of the bussed net, defined by netname, unconnected.
USER RESPONSE:
net of cellname1 than the number of strands of the bussed pin in cellname2.
Correct the problem and rebuild the model.
WARNING (TEI-253): Module cellname1 instance instance2 of cell cellname2 pin

pinname is not connected.
EXPLANATION:
In the Verilog source, a bussed net in cellname1 is connected to a bussed pin of
cellname2, but there are more strands defined for the bussed net of cellname1 than
there are strands of the pin in cellname2. Encounter Test will leave the extra strands
of the bussed net, defined by netname, unconnected.
USER RESPONSE:

net of cellname1 than the number of strands of the bussed pin in cellname2.
Correct the problem and rebuild the model.
WARNING (TEI-254): [Severe] While attempting to determine correlation for pin

pinname1, An invalid CORRELATE attribute value was found on pin pinname2 of cell
cellname.
The first character of the value must be either a +/1 or -/0 indicating whether the correlated
pin is in phase (+/1) or out of phase (-/0) with its representative pin. The attribute is ignored.
Cell contents file: contentsfile.
EXPLANATION:
Invalid CORRELATE attribute encountered. First character of value is incorrect. First
character of value is required to indicate the relationship between the correlated pin
(having the CORRELATE attribute) and its representative pin (pinname specified as value
of CORRELATE attribute). If the two pins are to be treated identically, specify +/1 to
indicate the correlated pin is "in phase" with its representative. If the correlated pin is to
be treated opposite its representative, specify -/0 to indicate the correlated pin is "out
of phase" with its representative. Since CORRELATE attribute was specified for the pin, it
is assumed to be required for the pin. Property is ignored to allow creation of the model.
USER RESPONSE:
Respecify CORRELATE attribute and rerun. Refer to Specifying Differential I/O and Other
Correlated Pins in the Encounter Test: Guide 1: Models for additional information.
Important
THIS ERROR SHOULD BE CORRECTED BEFORE CONTINUING.

pinname1, An invalid CORRELATE attribute value was found on pin pinname2 of cell
cellname. Pin pinname3 is not defined for the cell. The attribute is ignored. Cell contents
file: contentsfile.
EXPLANATION:
Invalid CORRELATE attribute encountered. pinname3 does not identify a pin on the cell
boundary or the pin directions of pinname3 and pinname2 do not match. Since
CORRELATE attribute was specified for the pin, it is assumed to be required for the pin.
Property is ignored to allow creation of the model.
USER RESPONSE:

Respecify or remove the CORRELATE attribute and rerun. Or you may specify a
CORRELATE attribute on the Primary Input/Output itself. If a CORRELATE attribute is
specified on the Primary Input/Output pin, the invalid CORRELATE attribute will be
ignored. Refer to Specifying Differential I/O and Other Correlated Pins in the
Encounter Test: Guide 1: Models for additional information.
Important

pinname1, CORRELATE attribute value was found on pin pinname2 of cell cellname.
Pin pinname3 is not connected to a Primary Input or Output so pin pinname1 cannot be
correlated. The attribute is ignored. Cell contents file: contentsfile.
EXPLANATION:
Invalid CORRELATE attribute encountered. pinname3 is not connected to a Primary
Input/Output of the design so the pin pinname1 cannot be correlated. Since
Property is ignored to allow creation of the model.
USER RESPONSE:
Respecify or remove the CORRELATE attribute and rerun. You may also specify a
CORRELATE attribute on the Primary Input/Output itself. If a CORRELATE attribute is
specified on the Primary Input/Output pin, the invalid CORRELATE attribute will be
ignored. Refer to Specifying Differential I/O and Other Correlated Pins in the
Important
WARNING (TEI-257): [Severe] Pin pinname1 is being correlated to two different pins.
Conflicting CORRELATE properties occur on pin pinname2 of cell cellname1 with a value
of value1, and pin pinname3 of cell cellname2 with a value of value2. The latter
attribute is ignored. Cell contents file: cellname1 contentsfile. Cell contents file:
cellname2 contentsfile.
EXPLANATION:
Since the Primary Input/Output is connected to more than one pin that contains a
CORRELATE attribute, it is impossible to determine which attribute to use. Therefore one
attribute is ignored.

USER RESPONSE:
Respecify or remove the incorrect CORRELATE attribute and rerun. Or you may specify
a CORRELATE attribute on the Primary Input/Output itself in addition to the conflicting
properties. If a CORRELATE attribute is specified on the Primary Input/Output pin, the
other conflicting properties will be ignored. Refer to Specifying Differential I/O and
Other Correlated Pins in the Encounter Test: Guide 1: Models for additional
information.
Important
WARNING (TEI-258): Excluding attribute value from the model per TEIcontrolAttr file
filename, but this attribute may be required by Encounter Test.
EXPLANATION:
You excluded the referenced attribute from the Encounter Test model via the
TEIcontrolAttr file, but this attribute may be needed by Encounter Test or one of its
downstream applications.
USER RESPONSE:
Determine whether the attribute is needed. If not needed, ignore this message and
continue. If the attribute is needed, remove its EXCLUDE statement from the
TEIcontgrolAttr file and rerun Build Model.
INFO (TEI-259): Period (.) found in DEF name defName. During the Build Model process,
ALL periods in all DEF names will be converted to string. Applications after Build Model
will once again refer to the name using the period (.).
EXPLANATION:
The referenced name contained a period. Encounter Test uses periods to denote levels
of hierarchy and therefore cannot tolerate periods in its simple names during the Build
Model process.
The period is converted to the specified string only during Build Model. After Build Model
is complete, subsequent applications (Build Test Mode, Verify Test Structures, and son
on) will refer to the name using the period instead of the conversion string. Input files
(such as the mode definition file) should refer to the name with the period.
USER RESPONSE:

No response is necessary. Messages produced by Build Model will use the conversion
string in the name instead of the period, so a name like X_p_Y may really refer to an
object called X.Y.
INFO (TEI-260): Period (.) found in DPIN name dpinname for cell cellname. During the
Build Model process, ALL periods in all DPIN names will be converted to string.
Applications after Build Model will once again refer to the name using the period (.).
EXPLANATION:
Model process.
is complete, subsequent applications (Buid Test Mode, Verify Test Structures, and son
on) will refer to the name using the period instead of the conversion string. Input files
(such as the mode definition file) should refer to the name with the period.
USER RESPONSE:
object called X.Y.
INFO (TEI-261): Period (.) found in PPIN name ppinname for cell cellname. During the
Build Model process, ALL periods in all PPIN names will be converted to string.
EXPLANATION:
Model process.
is complete, subsequent applications (Build Test Mode, Verify Test Structures, and so on)
will refer to the name using the period instead of the conversion string. Input files (such
as the mode definition file) should refer to the name with the period.
USER RESPONSE:
object called X.Y.

INFO (TEI-262): Period (.) found in pin name pinname in block block in cell cellname.
During the Build Model process, ALL periods in all pin names will be converted to string.
EXPLANATION:
Model process.
USER RESPONSE:
string in the name instead of the period, so a name like X_p_Y may really be refer to an
object called X.Y.
INFO (TEI-263): Period (.) found in block name blockname in cell celname. During the
Build Model process, ALL periods in all block names will be converted to string.
EXPLANATION:
Model process.
USER RESPONSE:
object called X.Y.
INFO (TEI-264): Period (.) found in net name netname in cell cellname. During the Build
Model process, ALL periods in all net names will be converted to string.

EXPLANATION:
Model process.
USER RESPONSE:
object called X.Y.
INFO (TEI-265): Period (.) found in CELL name cellname1. During the Build Model
process, the name will be converted to cellname2.
EXPLANATION:
Input cellname1 contains a period. Encounter Test uses periods to denote levels of
hierarchy and therefore cannot tolerate periods in its simple names during the Build
Model process. The cell name is converted to cellname2.
After Build Model is complete, subsequent applications (Build Test Mode, Verify Test
Structures, and so on) will refer to the name using the period instead of the conversion
string. Input files (such as the mode definition file) should refer to the name with the
period.
USER RESPONSE:
object called X.Y.
INFO (TEI-266): Period (.) found in ENTITY name entityname1. During the Build Model
process, the name will be converted to entityname2.
EXPLANATION:

Input entityname1 contains a period. Encounter Test uses periods to denote levels
Model process. The ENTITY name is converted to entityname2.
After build_model is complete, subsequent applications (Build Test Mode, Verify Test
string. Input files (such as the mode definition file) should refer to the name with the
period.
USER RESPONSE:
object called X.Y.
INFO (TEI-267): Illegal comma in block name blockname in cell cellname. ALL commas
in ALL block names are converted to _c_.
EXPLANATION:
The referenced block name contained a comma. Encounter Test does not allow the use
of commas embedded in block names. The comma will be converted to the substring
_c_ and the block will subsequently be referred to using the converted name.
USER RESPONSE:
string in the name instead of the comma, so a name like X_c_Y may really refer to an
object called X,Y in the design source.
INFO (TEI-268): Illegal equal sign in usage name usage1 in cell cellname. ALL equal
signs in ALL block names are converted to _e_.
EXPLANATION:
The referenced usage name contains an equal sign. Encounter Test does not allow the
use of equal signs embedded in usage names. The equal sign will be converted to the
substring _e_ and the block will subsequently be referred to using the converted name.
USER RESPONSE:
string in the name instead of the equal sign, so a name like X_e_Y may really refer to an
object called X=Y in the design source.
WARNING (TEI-269): [Severe] String string found in name name on line

linenumber. During the Build Model process, ALL periods in all names will be converted
to period substitution string based on the setting of the TEIPERIOD parameter.

This may cause problems with processing of this name by downstream applications. It is
recommended that TEIPERIOD be changed to something other than period
substitution string and rerun Build Model.
EXPLANATION:
The referenced name contained a string that matches the TEIPERIOD period
substitution string specified as an input parameter to Build Model (default is _p_).
Encounter Test uses periods to denote levels of hierarchy and therefore cannot tolerate
periods in its simple names during the Build Model process. Periods in names get
converted to the TEIPERIOD period substitution string internally in the model. After
Build Model is complete, subsequent applications (Build Test Mode, Verify Test
string. In this case, however, the referenced string will be incorrectly converted to a
period resulting in an incorrect name and probable errors in the application attempting to
use the name.
USER RESPONSE:
Rerun Build Model, specifying a different string for TEIPERIOD that does not appear
within any block, pin, or net names.
WARNING (TEI-270): [Severe] operator not supported on line number.

EXPLANATION:
The Encounter Test Verilog parser does not support the operator specified on this line.
The net on the left hand side of the assignment is left unconnected.
USER RESPONSE:
Modify the design source to express the function using Verilog primitives and rerun
Encounter Test Create New Circuit. Also contact customer support (see Contacting
Customer Service on page 23) to inform them of the need to support this function.
ERROR (TEI-271): While processing constraints, net netname in cell cellname could
not be found. Cell contents file: contentsfile.
EXPLANATION:
You placed a constraint on net netname in cell cellname and net netname does not
exist.
USER RESPONSE:
Modify the constraint to specify the correct net or remove the constraint and rerun Build
Model.

ERROR (TEI-272): While processing constraint constraintname, block instance1 in

cell cellname could not be found. Cell contents file: contentsfile.
EXPLANATION:
You placed a constraint on instance instance1 in cell cellname and the instance
name does not exist.
USER RESPONSE:
Modify the constraint to specify the correct net or remove the constraint and rerun Build
Model.
WARNING (TEI-273): While processing constraints file constraint file name, end-
of-file was encountered while inside a multi-line /* comment. Possible missing end of
comment */.
EXPLANATION:
While parsing the constraint file shown in the message, build_model encountered the
begin multi-line comment syntax /*, but end-of-file was encountered before the end of
multi-line comment syntax */. This may be an error of omission that results in lines not
being parsed that were intended to be parsed.
USER RESPONSE:
If the end of comment was not intentionally omitted, edit the constraint file to place the
*/ end comment syntax in the correct place and rerun build_model.
WARNING (TEI-274): End-of-file was encountered while inside a multi-line '/*' comment.
Possible missing end of comment '*/'.
EXPLANATION:
While parsing the Verilog (or other) file shown in the message, build_model
encountered the begin multi-line comment syntax '/*', but end-of-file was encountered
before the end of multi-line comment syntax '*/'. This may be an error of omission that
results in lines not being parsed that were intended to be parsed.
USER RESPONSE:
If the end of comment was not intentionally omitted, edit the file to place the '*/' end
comment syntax in the correct place and re-run build_model.
WARNING (TEI-275): Mixed signal strengths not supported on line line_number.

EXPLANATION:

The Encounter Test Verilog parser does not support the specification of mixed (strong
versus weak) signal strengths for the drive 0 and drive 1 signal strengths on output pins.
Strong signal strengths will be assumed.
USER RESPONSE:
Modify the design source to have non-conflicting signal strengths on the pin and rerun
Build Model. If the specified signal strength is pull0 or pull1, another alternative is to
specify the build_model keyword values pull=strong or pull=weak.
WARNING (TEI-279): [Severe] String string found in name name in input hierModel
filename. During the Build Model process, ALL periods in all names will be converted to
period_substitution_string based on the setting of the TEIPERIOD parameter.
This may cause problems with processing of this name by downstream applications. It is
recommended that TEIPERIOD be changed to something other than
period_substitution_string and rerun Build Model.
EXPLANATION:
The name specified contained a string that matches the TEIPERIOD period substition
string specified as an input parameter to build_model (default is _p_). Encounter Test
uses periods to denote levels of hierarchy and therefore cannot tolerate periods in its
simple names during the Build Model process.
Periods in names get converted to the TEIPERIOD period substitution string internally in
the model. After build_model is complete, subsequent applications (BuildTest Mode,
Verify Test Structures and so on) will refer to the name using the period instead of the
conversion string. In this case, however, the string referred to in the message will be
incorrectly converted to a period resulting in an incorrect name and probable errors in the
application attempting to use the name.
USER RESPONSE:
Rerun build_model be run again with TEIPERIOD set to a different string that does
not appear within any block, pin, or net names.

WARNING (TEI-280): [Severe] Unable to bind cell cellname1 net netname to instance
blockname of cell cellname2, position pinposition strand strandOffset. Cell
contents file: cellname1 contentsfile. Cell contents file: cellname2
contentsfile.
EXPLANATION:

The input netlist specified that the indicated net should connect to a pin of cellname1,
specifically at the referenced pin position and the strand offset. However, Build Model
was unable to find the referenced position/strand in the definition of cellname2. The
net will NOT be joined as requested.
USER RESPONSE:
Compare the definition of the block in cellname1 with the definition of the interface of
cellname2. Ensure that Encounter Test is using a definition of cellname2 specified
in either Verilog or MTV. (Encounter Test does not support positional binding with cells
defined in other languages.) Ensure that the ordinal position of the net in the higher level
block matches the expected ordinal position of the pin in the interface for cellname2.
Ensure that the number of bits specified in the block matches the number of bits in the
bussed pin of cellname2. Rerun if necessary.
WARNING (TEI-281): [Severe] Unable to bind cell cellname1 net netname to instance
blockname of cell cellname2, position pinposition. Cell contents file: cellname1
contentsfile. Cell contents file: cellname2 contentsfile.
EXPLANATION:
The input netlist specified that the indicated net should connect to a pin of cellname2,
specifically at the referenced pin position. Build Model was unable to find the specified
position in the definition cellname2. The net will NOT be joined as requested.
USER RESPONSE:
Compare the definition of the block in cellname1 with the definition of the interface of
cellname2. Ensure that Encounter Test is using a definition of the lower level cell
specified in either Verilog or MTV. (Encounter Test does not support positional binding
with cells defined in other languages.) Ensure that the ordinal position of the net in the
higher level block matches the expected ordinal position of the pin in the interface of
cellname2.
ERROR (TEI-282): The parser detected a token that exceeds a maximum length of
maxLength. The first 25 characters of this token are: tokenString.
EXPLANATION:
The parser restricts the maximum length of a token. The encountered token exceeds the
restricted length.
USER RESPONSE:
Check to see if there is a missing statement delimiter. If the maximum token length needs
to be increased, contact customer support (see Contacting Customer Service on

ERROR (TEI-283): The TEIinitSocket routine expects a valid internet address as its first
parameter. problemString.
EXPLANATION:
The TEIinitSocket routine relies on a valid internet address so it can establish a
socket connection to build_model. The internet address may be obtained by using the
TEIgetInet command.
USER RESPONSE:
Run TEIinitSocket with a valid internet address. See "build_model in the Encounter
ERROR (TEI-284): The TEIinitSocket routine failed on a call to the system socket
routine.
Errno = errorNumber. The system reason is: problemString.
EXPLANATION:
The TEIinitSocket routine calls a system socket routine to establish a socket. This
routine failed. The program will terminate since a socket is required for establishing
communications between the Import and Test Synthesis.
USER RESPONSE:
See the system reason for information.
INFO (TEI-285): The TEIinitSocket routine failed on a call to the system bind routine.
Attempt to bind port# port1 failed. The port will be switched to port# port2. Another bind
on port# port2 will be attempted.
EXPLANATION:
The TEIinitSocket routine calls a system listen routine to detect that another socket
wants to communicate with it.
This routine failed. The program will terminate since a connection is required for
establishing communications between the Import and Test Synthesis.
USER RESPONSE:
ERROR (TEI-286): The TEIinitSocket routine failed on a call to the system listen
routine.

EXPLANATION:
The TEIinitSocket routine calls a system listen routine to detect that another socket
wants to communicate with it.
USER RESPONSE:
ERROR (TEI-287): The TEIdftsVIM routine requires a socket to be established prior to its
invocation. The socket is established via a call to the TEIinitSocket routine. Ensure that
the TEIinitSocket has been successfully invoked prior to invoking TEIdftsVIM.
EXPLANATION:
TEIdftsVIM can only be run if a valid socket was established by the TEIinitSocket
routine.
USER RESPONSE:
Ensure that the TEIinit routine was run successfully prior to running TEIdftsVIM.
Contact customer support (see Contacting Customer Service on page 23) if the
problem persists.
ERROR (TEI-288): The TEIdftsVIM routine failed on a call to the system accept routine.
EXPLANATION:
The TEIdftsVIM routine calls a system accept routine to finalize the connection to the
other socket (TEIcntl).
USER RESPONSE:
INFO (TEI-289): build_model hieronly=yes has been specified. The flatModel will not
be produced.
EXPLANATION:
The hieronly option allows a hierarchical model to be produced which contains
missing cell definitions. As a consequence, no flatModel is produced.

USER RESPONSE:
When all required definitions are available, remove the hieronly=yes keyword
specificaiton from the command line and rerun build_model.
WARNING (TEI-290): Warning - cellname cellname cannot be found. The build_model

hieronly option has been specified which allows the hierarchical model to be produced
without all cells defined. Processingcontinues.
EXPLANATION:
Typically, a missing cell is a terminating condition for build_model. However, this
behavior is being overridden by the specification of the hieronly option. The
hierarchical model will be built using the available cell definitions.
USER RESPONSE:
When all required definitions are available, remove the hieronly=yes keyword
specificaiton from the command line and rerun build_model.
WARNING (TEI-291): [Severe] A problem occurred reading include file include file
name. Processing continues without the include file. The system error follows:
EXPLANATION:
The include file specified in the design source was unable to be opened. The fopen
system command error message is printed. The most likely cause is that the file, as
specified, does not exist or a fully qualified file name is required to find it.
USER RESPONSE:
Processing continues.Verify this was the expected response. If not, correct all problems
and rerun build_model.
WARNING (TEI-292): [Severe] A problem occurred reading include file include file
name. Too many levels of include files. Only 10 levels of include file nesting is supported.
Processing continues without the include file.
EXPLANATION:
The specified include file in the design source was unable to be processed because there
are too many levels of nested include files. Only10 levels of nesting are supported. This
can be corrected by reducing the number of levels of nested include files to be less than
10.
USER RESPONSE:

WARNING (TEI-293): Cell cellname has no unit level (UNLEV) attribute.

EXPLANATION:
This error indicates that the cell name specified is missing the UNLEV attribute. It is an
E level message because other cells exist that have the attribute. If at least one cell has
the UNLEV attribute, all cells are expected to have a matching UNLEV to verify that all
design cells are from the same iteration of the design. This error will result in a blank
UNLEV being reported to manufacturing.
USER RESPONSE:
WARNING (TEI-294): Cell cellname has an UNLEV mismatch - unlve1 vs. unlev2.
EXPLANATION:
This error indicates a mismatch of UNLEV properties between the first UNLEV found and
the current cells UNLEV. This indicates that different iterations of the design cells are
being used. A blank UNLEV will be reported to manufacturing.
USER RESPONSE:
WARNING (TEI-295): UNLEV checking for design cell cellname detected number
error(s). An UNLEV of defaultUNLEV is assigned to the design.
EXPLANATION:
This error indicates that TEI-293 or TEI-294 errors have occurred and shows the UNLEV
that is assigned to the design and that will be reported to manufacturing.
USER RESPONSE:
and rerun build_model Refer to UNLEV Property in the Encounter Test: Guide 1:
Models for related information.
INFO (TEI-296): Cell cellname has unit level (UNLEV) attribute value.
EXPLANATION:

This informational message shows the UNLEV attribute for the cell name shown in the
message. This message is issued only when the environment variable
TEI_ADV_UNLEV_CHECK has been enabled requesting advanced UNLEV checking.
USER RESPONSE:
Processing continues. No response required.
INFO (TEI-297): Cell cellname has no unit level (UNLEV) attribute.

EXPLANATION:
This error indicates that the cell name specified is missing the UNLEV attribute. It is an
INFO level message because no other cells exist that have the attribute. Normally no
messages get printed if UNLEV properties are not in use in any of the design cells. This
message is issued only when the environment variable TEI_ADV_UNLEV_CHECK has
been enabled requesting advanced UNLEV checking.
USER RESPONSE:
Processing continues. No response required.
WARNING (TEI-298): [Severe] Attempted to define alias alias name of cell cellname
on line linenumber of file filename, but cell cellname was not previously defined.
EXPLANATION:
This error indicates that an alias was specified (in the MTV source) for a cell that was not
defined in the MTV source. Processing will continue and the alias will be ignored.
USER RESPONSE:
Processing continues. Determine whether this is a problem. If it is a problem, include the
definition of the missing cell and re-run Build Model.
INFO (TEI-299): Support for the original Encounter Test Verilog Parser (vlogparser=et)
will be REMOVED for ET 15.1. For ET 15.1, all input Verilog will be processed using the NC
IEEE Standard Parser (ncvlog).
EXPLANATION:
The original Encounter Test Verilog Parser is obsolete and is being removed from use.
USER RESPONSE:
There could be a loss of attribute data if the input Verilog is using the "//!" syntax for
specifying attribute input to Encounter Test. The "//!" syntax is processed as comments
by the NC IEEE Standard Parser and will not result in any data being saved in the
Encounter Test Logic Model. To process such Verilog in ET 15.1 and beyond, convert the

"//!" syntax into the Verilog 2001 Standard for specification of attributes using the "(*
attr="value" *)" syntax.
ERROR (TEI-300): Failed to obtain a license for product productname. Run terminates.
EXPLANATION:
USER RESPONSE:
Ensure the availability of the required license then rerun.
WARNING (TEI-301): [Severe] Cell cellname1 has a TYPE or CELLTYPE attribute of

level1, but contains an instance of cell cellname2 which has hierarchical level level2.
The hierarchical level of cell cellname1 is being changed from level1 to level3. Cell
contentsfile.
EXPLANATION:
cellname1 has an attribute that defines its intended hierarchical level (CELL, MACRO,
and so on) to be cellname2 is contained within cellname1, but is a higher
hierarchical level than level1. The hierarchical level for cellname1 is being changed
from level1 to level3.
An example of this condition is if cellname1 contains a TYPE=CELL attribute (or is
defined as a cell via the Verilog celldefine directive), but it contains an instance of
cellname2 which is a MACRO.
For True-Time Test, delays are defined for technology cells, and they should contain only
primitives and other cells. The fact that a CELL contains a MACRO indicates there is likely
to be a problem matching the delay data (in the SDF) to the logic model.
USER RESPONSE:
The cell that is defined as a MACRO most likely should be identified as a CELL by using a
Verilog celldefine directive or by adding a TYPE=CELL attribute. Also, the cells in the
model must be aligned with the cells that have delays expressed in the SDF.
Rebuild the model after taking corrective action.
Refer to Specifying the Cell Level for Graphical Display in the Encounter Test: Guide
1: Models for more information on TYPE attributes.
WARNING (TEI-302): Cell cellname1 has a TYPE or CELLTYPE attribute of level1, but
contains an instance of cell cellname2 which has hierarchical level level2. The

hierarchical level of cell cellname1 is being changed from level1 to level3. Cell
contentsfile.
EXPLANATION:
cellname1 has an attribute that defines its intended hierarchical level (CELL, MACRO,
and so on) to be level1. cellname2 is contained within cellname1, but is a higher
hierarchical level than cellname1. The hierarchical level for cellname1 is being
changed to level3.
An example of this condition is if cellname1 contains a TYPE=CELL attribute (or is
defined as a cell via the Verilog celldefine directive), but it contains an instance of
cellname2 which is a MACRO.
For industry-compatible fault modeling, buffers are added to the model as necessary to
guarantee the proper faults exist at technology cell pins. Incorrect specification of the
technology cells may lead to a discrepancy in the fault counts.
USER RESPONSE:
If cellname2 is defined as a MACRO, cellname2 most likely should be identified as
a CELL by using a Verilog celldefine directive or by adding a TYPE=CELL attribute.
The important issue is to ensure the technology cells are properly identified.
Rebuild the model after taking corrective action.
For more information on TYPE attributes, refer to Specifying the Cell Level for Graphical
Display in the Encounter Test: Guide 1: Models .
WARNING (TEI-303): [Severe] Cell cellame contains primitives, but is not a technology
cell. It has a hierarchical level of level1. A TYPE or CELLTYPE attribute may be incorrectly
specified. Cell contents file: cellname contentsfile.
EXPLANATION:
Each hierarchical cell in the model is assigned a level (PRIMITIVE, CELL, MACRO, and
so on). This is assigned by Build Model , but may be explicitly specified by using a TYPE
or CELLTYPE attribute, or by using a celldefine directive in Verilog (equates to
TYPE=CELL). Cell cellname is defined as level1, and should not contain instances
of primitives. Only CELLS should contain primitives. Incorrectly specified hierarchical
levels are likely to cause problems correlating delays (specified in the SDF) to the
technology cells in the model.
USER RESPONSE:
If the cell should be defined as a technology cell, specify a TYPE=CELL attribute on the
cell definition, or code a celldefine directive (Verilog). It may also be necessary to

replace the primitive instances with technology cells so that delay information can be
obtained for them. Rebuild the model.
WARNING (TEI-304): [Severe] Cell cellname1 contains primitives, but is not a

technology cell. It has a hierarchical level of level1 because it contains an instance of cell
cellname2 which is a level2. A TYPE or CELLTYPE attribute may be incorrectly
specified. Cell contents file: cellname1 contentsfile. Cell contents file: cellname2
contentsfile.
EXPLANATION:
Each hierarchical cell in the model is assigned a level (PRIMITIVE, CELL, MACRO, and
so on). This is assigned by Build Model, but may be explicitly specified by using a TYPE
or CELLTYPE attribute, or by using a celldefine directive in Verilog (equates to
TYPE=CELL). Cell cellame1 is defined as level1, and should not contain instances
of primitives.
Only CELLS should contain primitives. Incorrectly specified hierarchical levels are likely
to cause problems correlating delays (specified in the SDF) to the technology cells in the
model. Cell cellname1 is most likely a level1 because it contains an instance of
cellname2 which is a level2.
USER RESPONSE:
If the cells (cellname1 and cellname2) should be defined as technology cells,
specify a TYPE=CELL attribute on the cell definitions, or code a celldefine directive
(Verilog). It may also be necessary to replace the primitive instances with technology
cells so that delay information can be obtained for them. Rebuild the model.
WARNING (TEI-305): [Severe] Cell cellname1 has a TYPE or CELLTYPE attribute of

level1, which causes cell cellname1 to exceed the maximum hierarchy depth of max
depth supported for TYPE=level1. Cell cellname1 contains an instance of cell
cellname2 which is defined with the maximum hierarchy depth of max depth.
Cell cellname1 is defined to keep its TYPE=level1 specification to allow completion of

the model. This model may not be correct for all downstream applications (that is, some
features within the GUI). Cell contents file: cellname1 contentsfile. Cell contents file:
cellname2 contentsfile.
EXPLANATION:

Cell cellname1contains an instance of cellname2. cellname2 has TYPE=level1

and is defined with the maximum number of hierarchy levels (maxdepth) supported for
TYPE=level1. Ths causes cellname1 to exceed the maximum number of hierarchy
levels (maxdepth) supported for TYPE=level1.
The GUI schematic view, particularly for performing Isolate on a multiple selection may
not correctly display. The Minimum Hierarchical Level When Tracing feature also
may not correctly work and displaying of the levels may not work.
Processing continues but it is highly recommended to evaluate this condition to
determine whether it will be a problem.
USER RESPONSE:
Determine whether the GUI problem will be a problem for this design. If so, flatten the
design (reduce the levels of hierarchy) so that there will be no more than the specified
maxdepth levels of TYPE=level1.
Rerun Build Model with the altered design source.
For more information on TYPE/CELLTYPE attributes, refer to Specifying the Cell Level
for Graphical Display in the Encounter Test: Guide 1: Models .
WARNING (TEI-369): Name string within module moduleName in file fileName

contains period substitution string (keyword TEIPERIOD=teiperiod value).
It is anticipated this will cause problems with processing of this name in downstream
applications. Change the TEIPERIOD to something other than teiperiod value
and rerun Build Model. Other occurrences may exist within this module, but only one
message is issued per module.
EXPLANATION:
The name specified contained a string that matches the TEIPERIOD period substitution
string specified as an input parameter to build_model (default is
TEIPERIOD=_d0t_). The string referred to in the message will be converted to a
period, changing the name. This is expected to create errors in an application attempting
to use the changed name.
USER RESPONSE:
It is recommended to rerun the build_model with a different TEIPERIOD value that
does not appear within any block, pin, or net name.
ERROR (TEI-400): Build Model FAILED:
Refer to TEI-280 messages.

EXPLANATION:
Build Model is unable to complete the creation of the logic model. Analyze the reason(s)
given.
USER RESPONSE:
Fix the problem(s) identified and rerun build_model. Contact Customer Support if more
assistane is required. Refer to Contacting Customer Service on page 23.
ERROR (TEI-500): [Internal] PROGRAM ERROR: debug_data

EXPLANATION:
A program error has occured. Internal table data has been corrupted.
Debug data has been printed to help customer support in analysis.
USER RESPONSE:
Provide customer support with the input design files and log file. Refer to Contacting
Customer Service on page 23.
ERROR (TEI-501): [Internal] PROCESSING LIMIT: Namespace overflow while processing

CELL cellname INSTANCE | NET objectNumber objectName.
EXPLANATION:
An internal processing limit has been reached. Encounter Test can only support 4
gigabytes of name data for each cell. Logic model cannot be built.
USER RESPONSE:
If running build_model, cell identified must be redesigned hierarchically. If running
build_boundary_model, rerun with -i option to create internal names using indexes
only.
ERROR (TEI-502): [Internal] PROCESSING LIMIT: Namespace overflow while processing

CELL cellname after X_number_of instances and Y_number_of nets.
EXPLANATION:
An internal processing limit has been reached. Encounter Test can only support 4
gigabytes of name data for each cell. Logic model can not be built. Number of instances
and nets are provided for information purposes only.
USER RESPONSE:

If running build_model, cell identified must be re-designed hierarchically. If running

build_boundary_model, rerun with -i option to create internal names using indexes
only.
severity (TEI-800): secondary_severity Verilog data access issue occurred in

routine routineName
visa_dev_msg
fileInformation
EXPLANATION:
The problem identified in the message was found while processing the Verilog.
USER RESPONSE:
Fix the problem and rerun build_model. Contact customer support (see Contacting
Customer Service on page 23) if more information is required.

routine routineName
visa_dev_msg
fileInformation
EXPLANATION:
USER RESPONSE:

routine routineName
visa_dev_msg
fileInformation
EXPLANATION:
USER RESPONSE:


routine routineName
visa_dev_msg
fileInformation
EXPLANATION:
USER RESPONSE:

routine routineName
visa_dev_msg
fileInformation
EXPLANATION:
USER RESPONSE:

routine routineName
visa_dev_msg
fileInformation
EXPLANATION:
USER RESPONSE:

routine routineName
visa_dev_msg
fileInformation
EXPLANATION:

USER RESPONSE:

routine routineName
visa_dev_msg
fileInformation
EXPLANATION:
USER RESPONSE:

routine routineName
visa_dev_msg
fileInformation
EXPLANATION:
USER RESPONSE:

routine routineName
visa_dev_msg
fileInformation
EXPLANATION:
USER RESPONSE:

WARNING (TEI-810): Build Model NC Sim (IEEE 2001 Standard) Verilog Parser:
construct not supported for Build Model on line lineNumber of file fileName.
EXPLANATION:
The Verilog construct listed in the message is not supported by Build Model.
USER RESPONSE:
Determine whether this will cause an incorrect model to be built. If not, no response is
required. If so, change the construct to one that is supported, such as an integer, binary,
or hexadecimal constant and rerun. Contact customer support (see Contacting
Customer Service on page 23) and inquire whether the submitted Verilog construct can
be supported in the future.
WARNING (TEI-811): [Severe] Build Model NC Sim (IEEE 2001 Standard) Verilog
Parser:operator operator not supported for Build Model on line lineNumber of file 'fileName'.
EXPLANATION:
The Verilog operator listed in the message is not supported by Build Model. Most likely
behavioral Verilog is being used, which is not supported by Encounter Test.Processing
continues with possible sources of X on certain nets.
USER RESPONSE:
Remove the behavioral constructs or create structural Verilog and rerun Build Model.
WARNING (TEI-812): Build Model NC Sim (IEEE 2001 Standard) Verilog Parser: return
code of return_code received from ncvlog process. Parsing has failed. ncvlog
messages indicating disk quota problems or file creation problems may indicate a need for
more space in the directory shown in the message or WORKDIR.
EXPLANATION:
The ncvlog process that parses the input Verilog file may have failed. If the ncvlog
message indicates a problem with file creation problems, such as *W,DLSYNC Disk
quota exceeded, or *E,DLWRTF: Write of intermediate file... failed,
or Unable to create INCA libs - invalid path, more space may be required
in the directory shown in the message. If no directory or file name is shown in the
message, the WORKDIR may need more space. If WORKDIR was not specified, the files
may be written to /tmp on the machine the job was run on and /tmp may not have
enough space. You may control where these files are created by setting
TB_PERM_SPACE to a directory name and export into the environment.
USER RESPONSE:
Correct the problem and rerun Build Model.

WARNING (TEI-812): Build Model NC Sim (IEEE 2001 Standard) Verilog Parser: return
code of return code received from ncvlog process. Parsing has failed.
EXPLANATION:
The ncvlog process that parses the input Verilog file may have failed. If the ncvlog
message indicates a problem with file creation problems, such as*W,DLSYNC Disk
quota exceeded, or *E,DLWRTF: Write of intermediate file... failed, or Unable to create
INCA libs - invalid path, more DASD may be required in the directory shown in the
message. If no directory or file name is shown in the message, WORKDIR may need
more space. If WORKDIR was not specified, the files may be written to /tmp on the
machine the job was run on and /tmp may not have enough space. To control where
these files are created, TB_PERM_SPACE can be set to a directory name and exported
into the environment.If the verilog file is encrypted using ncprotect, and ncvlog returns
the error:
NCPROTECT_KEYDB environment variable not set
You must rerun build_model with the keyword option ncencryptkey that specifies
the path of the verilog encryption key(s) directory/directories.
USER RESPONSE:
Correct the problem and re-run Build Model.
WARNING (TEI-813): [Severe] Build Model NC Sim (IEEE 2001 Standard) Verilog Parser:
return code of return_code received from ncvlog process. It is recommended to check
for ncvlog messages in the Build Model log.
EXPLANATION:
The ncvlog process that parses the input Verilog file had a syntax error that may be
severe enough to cause Build Model to fail. If Build Model does not fail, an incomplete
model may exist.The NC Verilog Parser messages should be investigated.
These messages are in a different format than Encounter Test and are not included in
the Build Model message summary at the end of the Build Model log. Examples of the
messages are *W,DLSYNC, *E,DLWRTF, or *E,EXPLPA.
USER RESPONSE:
Check for these messages in the Verilog parsing portion of the Build Model log, analyze,
and if necessary correct the Verilog design source and rerun Build Model.
ERROR (TEI-899): Verilog data access issues (routine = routine_identifier)

caused the Verilog processing to terminate.
EXPLANATION:

The Verilog data could not be accessed. See preceding messages for details.
USER RESPONSE:
Correct the data access issues and rerun.
severity (TEI-900): secondary_severity Verilog data access issues (routine =

routine_identifier) caused the Verilog processing to terminate.
EXPLANATION:
Data access issues have caused the parser to fail.
USER RESPONSE:
If the secondary severity is [Internal], this is a programming error that should be
reported to Cadence customer support (see Contacting Customer Service on
page 23).
Otherwise, review previous messages, correct the reported data access issues, and
rerun.
WARNING (TEI-998): Unable to allocate storage for instance pin checking (TEI-110, TEI-
115, and TEI-145 messages). The build_model command continues.
EXPLANATION:
The build_model command was unable to access any additional storage for processing.
TEI-110, TEI-115, and TEI-145 checking is bypassed.
USER RESPONSE:
This checking is not critical to the success of build_model and does not alter the model
in any way. If checking for these errors is needed, rerun build_model on a machine
with more memory.
ERROR (TEI-999): [Internal] An unexpected condition occurred in the Encounter(R) Test

model code. Contact Cadence Customer Support to report this error and provide the following
information:
An error occurred on line line_number of source file file_name: variable_text

EXPLANATION:
USER RESPONSE:

This will allow the programmer to find and fix the problem more quickly. Refer to

27
TFA - Deterministic Fault Analysis
Messages
TFA-001 through TFA-050 on page 767

TFA-051 through TFA-089 on page 782
TFA-001 through TFA-050

INFO (TFA-001): Fault faultId (Fault Type,Circuit Affiliation) is
untestable due to a conflict detected while attempting to propagate the fault effect.
Possible Cause(s) were encountered which may be the cause.
EXPLANATION:
A conflict was discovered while attempting to propagate the fault effect to an observation
point. The conflict is such that the gating conditions required for fault propagation cannot
be achieved. To successfully propagate a fault effect to an observable location, gating
conditions must be set up on blocks that are fed by the fault site. The gating conditions
for a particular block fed by the fault site require that inputs not fed by the fault site be set
to non-controlling values (logic 1 for AND blocks and logic 0 for OR blocks). Deterministic
Fault Analysis considers the following elements to be observe points:
Primary Output (including Common I/O)
Scannable latch; (for example, L1, L2)
Non-scannable latch; (for example, L5)
Random Access Memory (RAM)
The fact that no sensitizable path exists from the fault site to any of the above elements
indicates the presence of blocking condition(s) in the logic fed by the fault site.
The possible cause for the violation may be one of the following:
Three-State contention

TFA - Deterministic Fault Analysis Messages
Values required to test the fault cause three-state contention. This is considered
an unacceptable state and thus deemed unachievable.
Multiple Clock conflict(s)
Two (or more) clocks are required to be activated simultaneously in order to test
the fault. This is considered an unacceptable state and thus deemed
unachievable. This condition can exist when clock ANDing is present.
Test Inhibit value(s)
Values required to test the fault are unachievable due to logic values which
originate from Test Inhibit flagged Primary Inputs.
User Linehold value(s)
originate from user-specified lineholds. These may be values which originate
from Linehold (LH) flagged pins, or HOLD statements specified by way of a
linehold file.
X-Source(s)
One or more X-Sources were encountered while attempting to achieve values
required to test the fault. Examples of an X-Source are: TIE X, unterminated
internal three-state, ROM with unknown contents, feedback, single-port
memory element with clock tied off.
Simultaneous output switching conflict(s)
The test for the fault requires that a clock be pulsed while an Output Inhibit (OI)
flagged pin is held to the enabling (non-stability) value. With the SOS option in
effect, this is considered un unacceptable state and thus deemed unachievable.
USER RESPONSE:
Select the specific message from the Specific Message List Window. The schematic
display is updated to show Fault faultId, along with the logic necessary to determine why
the fault is untestable.
Use the graphical user interface to assist in the analysis of the message. Refer to
"Actions on the View Schematic Window" in the Encounter Test: Reference: GUI.
You can also use the Deterministic Fault Analysis Logic Values displayed and the
information in the Details to help analyze the message.
Refer to Linehold File in the Automatic Test Pattern Generation User Guide for


untestable due to a conflict detected while attempting to activate the fault. Possible
Cause(s) were encountered which may be the cause.
EXPLANATION:
Logic values required to activate the faults could not be achieved due to the presence of
a conflict. Fault excitation is the process of establishing the necessary logic values at a
given fault site which expose the particular defect.
For stuck faults, the required logic values depend on the stuck-at value of the fault,
whether the fault is on an input pin or output pin of the block, and the particular simulation
function of the block.
linehold file.
X-Source(s)

Note: The Details window includes the activation requirements for a fault.
USER RESPONSE:
display is updated to show Fault faultId, along with the logic necessary to determine
why the fault is untestable.
information in the Details to help analyze the message.

untestable due to a conflict which prevents the establishment of required design values.
Possible Cause(s) were encountered which may be the cause.
EXPLANATION:
Logic values that MUST be established in order to test the fault could not be achieved
due to a conflict. The logic values may be required to activate the fault or to propagate
the fault effect to an observe point.


linehold file.
X-Source(s)
USER RESPONSE:
display is updated to show Fault faultId, along with the logic necessary to determine
why the fault is untestable.
information in the Details. window to help analyze the message.
INFO (TFA-006): Fault faultId (Fault Type,Circuit Affiliation) is an

untestable clock-not-chopped fault as it cannot be observed at a Primary Output. Possible
Cause(s) were encountered which may be the cause.
EXPLANATION:
A forward (topological) trace from the fault site determined that no path exists to a
Primary Output. A clock-not-chopped fault must be observed at a Primary Output
because it cannot be detected at a latch (or RAM) without violating design-for-test
restrictions.
If the fault site topologically feeds primary output(s), the associated paths must be
blocked in some manner.

linehold file.
X-Source(s)
USER RESPONSE:
display display is updated to show the Clock Chopper network associated with this
specific fault site.
Use the graphical user interface to assist in further analysis of the message. Refer to
"Actions on the View Schematic Window" in the Encounter Test: Reference: GUI. You
can use the Trace Forward function to display the logic fed by the fault site to determine
why there is no path to a Primary Output.

information in the Details window to help analyze the message.

untestable due to non-local conflict(s). Possible Cause(s) were encountered which
may be the cause.
EXPLANATION:
A test could not be developed for this fault due to conflicts detected during Fault Analysis.
All possible input combinations were tried.
linehold file.
X-Source(s)

USER RESPONSE:
Since there is no analysis support currently provided for TFA-007 messages, it is
recommended that any testability problems identified by other TFA messages be
addressed first. It is possible that when the resolutions associated with other TFA
messages are applied, this may eliminate some or all of the TFA-007 messages as well.
Resolutions may entail changes to:
The logic model description
The test function pins defined for the test mode
The user-specified lineholds
All of the above
Once the necessary resolutions have been applied, Deterministic Fault Analysis (and
prerequisites) should be rerun. If no TFA-007 messages exist, no further action is
required. Refer to Linehold File" in the Automatic Test Pattern Generation User
Guide for additional information.

untestable due to multiple forward propagation conflicts. Possible Cause(s) were
encountered which may be the cause.
EXPLANATION:
Attempts were made to propagate the fault effect forward through the logic to an
observation point. Each attempt resulted in the identification of a conflict that prevented
forward propagation.


linehold file.
X-Source(s)
USER RESPONSE:
Since there is no analysis support currently provided for the TFA-008 messages, it is
Resolutions may entail changes to:
The logic model description
The test function pins defined for the test mode
The user-specified lineholds
All of the above
required. Refer to Linehold File in the Automatic Test Pattern Generation User
INFO (TFA-009): Fault faultId (Fault Type,Circuit Affiliation) is an

untestable clock-stuck-off fault which feeds only single-port memory element(s).

EXPLANATION:
A test could not be developed for this fault because the fault effect holds the clock input
of the memory element(s) Off. This condition prevents the memory element(s) from
being initialized to a known logic value.
If the fault site topologically feeds primary output(s), the associated paths must be
blocked in some manner. The following could result in blocking conditions:
Tied logic (TIE 1, TIE 0, TIE X)
Logic values originating from Test Inhibits
Logic values originating from user-specified lineholds
Logic values originating from constant value nets
USER RESPONSE:
Provide an observation point(s) that can be used to detect the fault or accept the reduced
test coverage.
information in the Details window to help analyze the message.

redundant due to a conflict detected while attempting to propagate the fault effect.
EXPLANATION:
A conflict was discovered while attempting to propagate the fault effect to an observation
point. The conflict is such that the gating conditions required for fault propagation cannot
be achieved. To successfully propagate a fault effect to an observable location, gating
conditions must be set up on blocks that are fed by the fault site. The gating conditions
for a particular block fed by the fault site require that inputs not fed by the fault site be set
to non-controlling values (logic 1 for AND blocks and logic 0 for OR blocks). Deterministic
Fault Analysis considers the following elements to be observe points:
Primary Output (including Common I/O)
Scannable latch; (for example, L1, L2)
Non-scannable latch; (for example, L5)
Random Access Memory (RAM)
The fact that no path exists from the fault site to any of the above elements indicates the
presence of blocking condition(s) in the logic fed by the fault site.
The following could result in blocking conditions:

Logic values originating from constant value nets

Logical redundancy along propagation path(s)
USER RESPONSE:
Select the specific message from the Specific Message List Window. The
schematic display is updated to show the fault site associated with Fault
faultId, along with the logic necessary to determine why the fault is
untestable.
Use the graphical user interface to assist in the analysis of the logic displayed.
Refer to "Actions on the View Schematic Window" in the Encounter Test:
Reference: GUI. You can also use the Deterministic Fault Analysis Logic
Values displayed and the information in the Details window to help with the
analysis.
If the resultant display consists of Constant Value Nets (+/1, -/0) due to logical
redundancy, additional circuit tracing may be required to view the redundant
logic that results in the constant value. Generally, selecting the block whose
output is at constant value and tracing back a few levels should display the
redundancy.
You can also use the Deterministic Fault Analysis Logic Values displayed and
the information in the Details window to help with the analysis.
Refer to Linehold File" in the User Guide for additional information.

redundant due to a conflict detected while attempting to activate the fault.
EXPLANATION:
Logic values required to activate the faults could not be achieved due to the presence of
a conflict. Fault excitation is the process of establishing the necessary logic values at a
given fault site which expose the particular defect.
For stuck faults, the required logic values depend on the stuck-at value of the fault,
whether the fault is on an input pin or output pin of the block, and the particular simulation
function of the block.
USER RESPONSE:
untestable.

Reference: GUI. You can also use the Deterministic Fault Analysis Logic
Values displayed and the information in the Details window to help with the
analysis.
redundancy.

redundant due to a conflict which prevents the establishment of required design values.
EXPLANATION:
Logic values that MUST be established in order to test the fault could not be achieved
due to a conflict. The logic values may be required to activate the fault or to propagate
the fault effect to an observe point.
USER RESPONSE:
untestable.
Reference: GUI.
redundancy.
the information in the "Details" window to help analyze the message.


redundant due to non-local conflict(s).
EXPLANATION:
All possible input combinations were tried.
USER RESPONSE:
Resolutions for redundant faults must consist of changes to the logic model description.
required.

redundant due to multiple forward propagation conflicts.
EXPLANATION:
Attempts were made to propagate the fault effect forward through the logic to an
observation point. Each attempt resulted in the identification of a conflict that prevented
forward propagation.
USER RESPONSE:
Resolutions for redundant faults must consist of changes to the logic model description.
required.
INFO (TFA-030): Fault faultId (Fault Type,Circuit Affiliation) was

aborted with an EFFORT setting of effort.
EXPLANATION:

The Fault Analysis (test generation) process was aborted while attempting to justify
design values in an effort to generate a test for the fault.
USER RESPONSE:
schematic display is updated to show Fault faultId.
To eliminate the message, increase the Deterministic Fault Analysis Effort
parameter. This should enable the Fault Analyzer to resolve the testability of this
(and other aborted faults).
See "Deterministic Fault Analysis Options" in the Encounter Test: Reference: GUI for
more information.

unresolved. Fault Analysis was inconclusive due to GLOBALTERM.
EXPLANATION:
None.
USER RESPONSE:

unresolved. Fault Analysis was inconclusive due to scannable latch conflict(s).
EXPLANATION:
While searching for a test for the indicated fault, the test generator encountered one or
more instances where scannable latch states consistent with a test could not be applied
by way of a load operation due to conflicts stemming from latch adjacency. The scan-
based test generator used for Fault Analysis will only establish values in scannable
latches by way of normal or skewed load operation. The indicated fault has not been
proven testable or untestable.
USER RESPONSE:
No response required if either the test coverage is acceptable, or the contribution of TFA-
032 faults to the overall number of untested faults is insignificant.
Otherwise, a clean-up run of sequential-based Stored Pattern Test Generation may be
required to resolve these faults during the ATPG phase.

unresolved. Fault Analysis was inconclusive due to multiple time-frame conflict(s).

EXPLANATION:
Fault Analysis is performed by the scan-based Stored Pattern Test Generator which has
limited support for sequential designs. Specifically, the scan-based Test Generator has
limited ability to remake decisions across time-frames. Consequently, when the test
generator successfully activates and propagates a sequential fault within its time-frame
(region containing fault site, partially or completely bounded by non-scan memory
elements), but is unable to complete the test (say due to conflicts), rather than trying
alternative decisions within the original time-frame, the fault is abandoned. Since this is
not a complete search for a test, the test generator cannot conclude the fault is
untestable, although it may be.
USER RESPONSE:
No response required if either the test coverage is acceptable, or the contribution of TFA-
033 faults to the overall number of untested faults is insignificant.
Otherwise, a clean-up run of sequential-based Stored Pattern Test Generation may be
required to resolve these faults during the ATPG phase.
WARNING (TFA-034): Fault faultId (Fault Type,Circuit Affiliation) is

unresolved. A test was generated and simulated, but no detection resulted.
EXPLANATION:
Fault Simulation did not find this fault to be tested. This may be due to the pessimistic
approach the simulator takes to tolerate race conditions in the design and still maintain
its high speed. Refer "Verify Test Structures" in the Encounter Test: Guide 3: Test
Structures.
USER RESPONSE:
No response is required if either the test coverage is acceptable, or the contribution of
TFA-034 faults to the overall number of untested faults is insignificant.
Otherwise, a clean-up run of sequential-based Stored Pattern Test Generation may
resolve these faults during the ATPG phase. If the number of TFA-034 faults after the
ATPG phase is unacceptable (poor test coverage), contact customer support (see
WARNING (TFA-035): Fault faultId (Fault Type,Circuit Affiliation)

previously classified as Redundant was subsequently detected by the fault simulator. It is
therefore considered testable.
EXPLANATION:
A fault determined to be redundant was marked detected by fault simulation. This
indicates an error by either (or both) fault simulation or test generation.

USER RESPONSE:
If significant numbers occur, please contact customer support (see Contacting
WARNING (TFA-036): Fault faultId (Fault Type,Circuit Affiliation)

previously classified as Untestable was subsequently detected by the fault simulator. It is
therefore considered testable.
EXPLANATION:
A fault determined to be untestable was marked detected by fault simulation. This
indicates an error by either (or both) fault simulation or test generation.
USER RESPONSE:
If significant numbers occur, please contact customer support (see Contacting

testable.
EXPLANATION:
Deterministic Fault Analysis has determined that this fault is testable.
USER RESPONSE:
ERROR (TFA-050): WORKDIR was not specified and is a required parameter. Deterministic
Fault Analyzer ends.
EXPLANATION:
The Deterministic Fault Analysis WORKDIR parameter was not detected. This parameter
is required for identification of the device under test (circuit) to be run.
USER RESPONSE:
Specify a WORKDIR parameter with a valid project and rerun. Refer to "analyze_faults in
TFA-051 through TFA-089

ERROR (TFA-051): ENTITY/VARIATION/ITERATION are required, but are not specified.
The run will terminate.

EXPLANATION:
ENTITY/VARIATION/ITERATION parameters were not detected. These parameters
(ENTITY at a minimum) are required to identify the design.
USER RESPONSE:
Specify valid ENTITY/VARIATION/ITERATION parameters (which correspond to an
existing design) and then rerun.
ERROR (TFA-052): TESTMODE was not specified and is a required parameter. The run will
terminate.
EXPLANATION:
The TESTMODE parameter was not detected. This parameter is required to identify the
design.
USER RESPONSE:
Specify a valid TESTMODE parameter and rerun. Refer to "analyze_faults in the
ERROR (TFA-053): Failed to obtain a Deterministic Fault Analyzer license. Deterministic

Fault Analyzer ends.
EXPLANATION:
A failed attempt was made to obtain a Deterministic Fault Analysis license. The license
is required to perform the associated action. This message can occur if:
A Deterministic Fault Analysis license has not been purchased
There are not enough available license(s)
License(s) are currently unavailable (all in use)
USER RESPONSE:
Ensure that a Deterministic Fault Analysis license of sufficient capacity is available and
rerun.
ERROR (TFA-054): Failed to obtain a lock_type lock on the target. Deterministic Fault
Analyzer ends.
EXPLANATION:
A file lock required to run Deterministic Fault Analysis could not be obtained. This
indicates that a file which Deterministic Fault Analysis requires exclusive use of, is

currently being used by one of the following processes being run against the same part/
testmode:
Another Deterministic Fault Analysis process
TFA messages being analyzed under the Graphical User Interface
Previous messages should indicate the process number which has exclusive use of the
file.
USER RESPONSE:
Ensure no other process has exclusive use of the file and rerun Deterministic Fault
Analysis.
WARNING (TFA-055): [Severe] Failed to free the Deterministic Fault Analyzer license.
EXPLANATION:
An attempt was made to free a Deterministic Fault Analysis license which was never
obtained. This is an indication of a program error.
USER RESPONSE:
Please contact customer support (see Contacting Customer Service on page 23).
ERROR (TFA-056): Invalid EFFORT specification detected. Deterministic Fault Analyzer

ends.
EXPLANATION:
An invalid setting was detected for Deterministic Fault Analysis Effort parameter. Allowed
settings are:
Minimum (least effort)
Low
Medium (default setting)
High
Maximum (most effort)
USER RESPONSE:
Specify a valid setting for Effort or remove the option and rerun. Refer to "analyze_faults
in the Encounter Test: Reference: Commands for additional information.

ERROR (TFA-057): Invalid MAXUNTESTABLES value detected - must be 0-100.

Deterministic Fault Analyzer ends.
EXPLANATION:
An invalid setting was detected for the Deterministic Fault Analysis MAXUNTESTABLES
parameter. An integer from 0 to 100 is expected. This number represents the percentage
of untestable faults identified (relative to the total number of faults), that are permitted
before the run is terminated.
USER RESPONSE:
Specify a valid integer for MAXUNTESTABLES or remove the option and rerun. Refer to
"analyze_faults in the Encounter Test: Reference: Commands for additional
information.
ERROR (TFA-058): Invalid setting detected for ENDTIME. Deterministic Fault Analyzer
ends.
EXPLANATION:
An invalid setting was detected for Deterministic Fault Analysis End Time(CPU
MINUTES) parameter. An integer representing the total number of CPU minutes for the
Deterministic Fault Analysis run is expected.
USER RESPONSE:
Specify a valid integer for End Time(CPU Minutes) or remove the option and rerun. Any
integer less than 99999 is a valid setting. Refer to "analyze_faults in the Encounter
Test: Reference: Commands for additional information.
ERROR (TFA-059): Invalid REPORT option option detected. Deterministic Fault Analyzer
ends.
EXPLANATION:
An unrecognized Deterministic Fault Analysis reporting option was detected.
USER RESPONSE:
The supported Deterministic Fault Analysis reporting options can be determined by
running the following command from an operating system command line:
analyze_faults -help
Correct or remove the unrecognized reporting option and rerun. Refer to "analyze_faults
in the Encounter Test: Reference: Commands for additional information.
INFO (TFA-060): ENDTIME of time has been reached. Deterministic Fault Analyzer ends.

EXPLANATION:
The run limit for ENDTIME is reached. Run terminates.
USER RESPONSE:
INFO (TFA-061): MAXUNTESTABLES of numuntestables%% has been reached.

Deterministic Fault Analyzer ends.
EXPLANATION:
The run limit for MAXUNTESTABLES is reached. Run terminates.
USER RESPONSE:
ERROR (TFA-062): Input experiment experiment does not exist. Deterministic Fault
Analyzer ends.
EXPLANATION:
The INEXPERIMENT specified does not exist. Run terminates.
USER RESPONSE:
Specify an existing INEXPERIMENT, either by exporting or on the command line, and
rerun.
ERROR (TFA-063): Logic model file filename does not exist. Deterministic Fault Analyzer
ends.
EXPLANATION:
The named file does not exist. Run terminates.
USER RESPONSE:
ERROR (TFA-064): Test mode of testmode does not exist. The run will terminate.
EXPLANATION:
The specified TESTMODE and is causing the run to terminate.
USER RESPONSE:
Specify a valid TESTMODE and rerun.

ERROR (TFA-065): Error(s) occurred during random pattern simulation. Deterministic Fault
Analyzer ends.
EXPLANATION:
An error occurred during random pattern simulation. Run terminates.
USER RESPONSE:
Refer to the previous messages issued by the simulator.
ERROR (TFA-066): Error(s) occurred during linehold processing. Deterministic Fault

Analyzer ends.
EXPLANATION:
An error occurred while processing the lineholds. Run terminates.
USER RESPONSE:
Refer to the previous messages issued by the linehold utility.
INFO (TFA-080): Reason The fault site is displayed.

EXPLANATION:
Analysis is not provided for the specified fault. The reason could be any of the following:
No analysis has been provided for messages of this type.
The fault resides in an entity which is cloaked.
Analysis is provided for static faults only.
USER RESPONSE:
Since there is no analysis support currently provided for this fault, it is recommended that
any testability problems identified by other TFA messages be addressed first.
INFO (TFA-085): The minimum hierarchical tracing level is set higher than primitive.
Deterministic Fault Analysis results can only be displayed at the primitive level.
EXPLANATION:
Deterministic Fault Analysis is only supported at the primitive level. All displays will be in
terms of Encounter Test primitives. Any additional circuit tracing you perform will be at
the level you have set with Circuit Tracing Options.
USER RESPONSE:

ERROR (TFA-086): The required WORKDIR parameter was not specified. The run will
terminate.
EXPLANATION:
The WORKDIR parameter was not detected. This parameter is required to identify the
design.
USER RESPONSE:
Specify a valid WORKDIR and rerun.
ERROR (TFA-087): No input parameters specified. The run will terminate. Run
analyze_deterministic_faults -h for help.
EXPLANATION:
The analyze_deterministic_faults command requires that keywords
analyzefaults=yes (default) or justify be specified.
USER RESPONSE:
Specify one of the required options and then rerun.
ERROR (TFA-088): Failure to initialize the test generation utilities. The run will terminate.
EXPLANATION:
The test generator is required and failed to initialize. The
analyze_deterministic_faults command requires test generation utilities.
USER RESPONSE:
ERROR (TFA-089): INEXPERIMENT inexperiment does not exist. The run will
terminate.
EXPLANATION:
The specified INEXPERIMENT does not exist and causes the run toterminate.
USER RESPONSE:
Specify a valid INEXPERIMENT name and rerun.
INFO (TFA-090): No testpoints identified.

EXPLANATION:

analyze_deterministic_faults did not identify any testpoints.

USER RESPONSE:
INFO (TFA-091): No Untested faults to analyze.

EXPLANATION:
analyze_deterministic_faults did not have any untested faults to process.
USER RESPONSE:
INFO (TFA-092): No inactive control logic identified.

EXPLANATION:
analyze_deterministic_faults did not identify any inactive control logic.
USER RESPONSE:
INFO (TFA-093): No Inactive faults to analyze.

EXPLANATION:
analyze_deterministic_faults did not find any inacative faults to analyze.
USER RESPONSE:
INFO (TFA-094): Keyword inactive=yes was specifed and fault faultId is not an
inactive fault. This fault will be ignored.
EXPLANATION:
During analyze_deterministic_faults when the keyword inactive=yes is
specified, only inactive faults will be processed. This fault is active and will be ignored.
The run will continue if other inactive faults have been specified.
USER RESPONSE:
INFO (TFA-121): Fault index, type on pin pn untestable: linehold|testmode inhibits fault
control: \n

EXPLANATION:
The specified fault cannot be tested because testmode or linehold signals prohibit
activating the fault. The message lists the signals that are preventing activation.
USER RESPONSE:
To allow ATPG to test the fault, you may need to adjust the lineholds or testmode
constraints (TI, TC pins) preventing activation of the fault.
INFO (TFA-122): Fault index, type on pin pn untestable: linehold|testmode inhibits fault
observe:
EXPLANATION:
The specified fault cannot be tested because testmode or linehold signals prohibit
observing the fault. The message lists the signals that are preventing observation.
USER RESPONSE:
To allow ATPG to test the fault, you may need to adjust the lineholds or testmode
constraints (TI, TC pins) preventing observation of the fault.
INFO (TFA-131): Fault index, type on pin pn inactive: Tied|TI|TC logic.

EXPLANATION:
The specified fault cannot be tested because testmode signals or tied nets prohibit
activating the fault. The message lists the signals that are preventing activation.
USER RESPONSE:
To allow ATPG to test the fault, you may need to adjust the testmode constraints (TI, TC
pins) preventing activation of the fault.
INFO (TFA-132): Fault index, type on pin pn inactive: dangling logic. \n

EXPLANATION:
The specified fault cannot be tested because the fault is on dangling (unconnected) logic,
possibly feeding a black box.
USER RESPONSE:
To allow ATPG to test the fault, the logic needs to be connected to an observable point
in the circuit.
INFO (TFA-133): Fault index, type on pin pn inactive: blocked.

EXPLANATION:

The specified fault cannot be tested because testmode signals prohibit observing the
fault. The message lists the signals that are preventing observation.
USER RESPONSE:
To allow ATPG to test the fault, you may need to adjust the testmode constraints (TI, TC
pins) preventing observation of the fault.
INFO (TFA-141): Fault index, type on pin pn: fault_status.

EXPLANATION:
Detailed analysis information is not available for the fault. The fault status from ATPG is
reported.
USER RESPONSE:
None
WARNING (TFA-150): The option analyzefaults will be obsolete in the next release, please
update your command line keywords accordingly. It will be replaced with the following two
options: testpoints - will provide suggested testpoints analyze - will provide analysis for
obstructed faults
EXPLANATION:
Analyze_deterministic_faults has been enhanced to provide analysis
information in addition to providing test points for faults. This will requires changing the
keywords to accurately reflect the behavior requested by the user. In a future release,
analyzefaults (which identifies test points) will no longer be allowed to avoid confusion
with the analyze keyword which provides analysis for untested faults.
USER RESPONSE:
Modify your command line to use the new keyword(s).


28
TEM - Insert Embedded Test Messages
TEM-039 through TEM-100 on page 793

TEM-039 through TEM-100

INFO (TEM-039): No memory cells to BIST. No target memory cells or instances provided
in the configuration file.
EXPLANATION:
There is no specification to insert a memory BIST engine to a memory element in the
netlist.
USER RESPONSE:
Verify intent to not provide target blocks.

INFO (TEM-040): Module location moduleName for the target BIST engine is used multiple
times and has numberOfInstances instances. All instances will be modified to insert the
BIST engine.
EXPLANATION:
The module selected as the BIST engine location for a target group has multiple
instances in the netlist. Inserting a BIST engine in a module will modify all instances of
a module unless each module in the netlist is uniquely instantiated (uniquified).
USER RESPONSE:
Verify that the indicated number of instances of the module that are listed in the text of
this message agree with the expected value.
INFO (TEM-041): Module location locModuleName for the target bist engine has a single
instance. Instance will be modified to insert the BIST engine.
EXPLANATION:
The module selected as the BIST engine location for a target group has a single
instance.
USER RESPONSE:
Verify the indicated number of instances of the module agree with the expected value.
INFO (TEM-045): No BIST engine inserted. Thus no JTAG attention pin associated with the
mbist engine found. Verify no BIST engines are to be inserted.
EXPLANATION:
A JTAG attention pin associated with a memory BIST engine was not detected in the
netlist and therefore no BIST engine is inserted into the netlist.
USER RESPONSE:
Verify that no BIST engines are to be inserted into the netlist.
INFO (TEM-046): No memory BIST engine inserted. Thus no TDO pin associated with the
mbist engines scan chain found. Ensure no BIST engines are to be inserted.
EXPLANATION:
Test Data Output (TDO) pin associated with a memory BIST engine was not detected
and therefore no BIST engines are inserted into the netlist.
USER RESPONSE:

INFO (TEM-047): No BIST engine is inserted. Thus no TDI pin associated with the mbist
engines scan chain is found. Ensure no BIST engines are to be inserted.
EXPLANATION:
A Test Data Input (TDI) pin related to the memory BIST engines scan chain was not
detected and thus no BIST engines are inserted into the netlist.
USER RESPONSE:
INFO (TEM-048): System clock source net netName is found in the user core hierarchical
block. Clock source net is used as clock input to the associated target groups BIST engine(s)
EXPLANATION:
The indicated system clock net for the target group was found in the user core
hierarchical block.
USER RESPONSE:
Verify that the indicated system clock net for the target group is expected to be found in
the user core hierarchical block.
INFO (TEM-049): System clock source net netName is found in module %2$s. Clock
source net is used as a clock input to the associated target groups BIST engine(s).
EXPLANATION:
The indicated system clock net is found in the referenced module.
USER RESPONSE:
Verify that the indicated system clock net for the target group is expected to be found in
the module referenced in the message.
INFO (TEM-050): No target memory instance to bist. Check the configuration file for target
groups and ignore groups. Ignore groups have priority over the target groups. Also check for
any previous messages regarding not fully specified memory cell.
EXPLANATION:
A BIST engine is not inserted. Either the targeted memory cells are also part of the
ignore group in the configuration file or not all the information regarding a memory cell
can be extracted from the memorys .lib file. In the latter case, the WARNING message
is printed in the log file along with the memorys cell name. If the targeted memory cell is
also part of the ignore group then ignore is given priority over the target.

USER RESPONSE:
Review the memory element statistics in the log file to confirm the status of each memory
cell found during the programs analysis phase.
INFO (TEM-051): The synthesis phase of the processing completed with the highest
severity of returnSeverity. Check the log file to verify no rules or assumptions are
violated.
EXPLANATION:
The message indicates the completion of the programs synthesis processing along with
the highest severity message incurred during the processing.
USER RESPONSE:
Review the log file for additional messages to verify that known rules or assumptions
have not been violated.
INFO (TEM-052): Program progName completed with the highest severity of

SeverityVal.
EXPLANATION:
The message specifies highest severity that program encountered during its processing.
The programs messages are mainly divided into three categories: INFO, WARNING,
and ERROR.
USER RESPONSE:
Review the log file, especially if the referenced severity is WARNING or ERROR.
INFO (TEM-053): Completed writing hdlFormatType output netlist file

absoluteFileName. Check for any preceding WARNING messages to ensure the files
format and contents are as intended.
EXPLANATION:
The output netlist is written in the format specified in the message text. In addition, the
program attempts to retain the hierarchy per the original netlist.
USER RESPONSE:
Verify the intended output type and functionality is produced for the output file.
INFO (TEM-054): Created temporary directory tempDirName for the programs internal
processing. No response required.
EXPLANATION:

The referenced directory has been temporarily created as part of internal processing and
is located in temporary file system space.
USER RESPONSE:
INFO (TEM-055): The format of the input netlist file ipNetListFileName is assumed
to be FormatType. Ensure the assumed HDL format is as expected.
EXPLANATION:
The program supports VHDL, EDIF, and Verilog formats and extracts the format from the
netlist file extension. The accepted extensions are:
.vhd or .vhdl indicate VHDL
.edif indicates EDIF
Verilog is assumed if neither of the preceding categories is detected.
USER RESPONSE:
Verify that the extracted format of the netlist is as expected.
INFO (TEM-056): No target groups found in the configuration file. The memory BIST engine
is not inserted. Ensure no target groups are intended.
EXPLANATION:
Target groups were not found in the configuration file. As there were no memories to
target, no further processing was performed.
USER RESPONSE:
Verify whether an empty configuration input file is intended.
INFO (TEM-057): No functional net is attached to pin pinName on memory instance

instName of memory cell type cellName in the module/entity moduleName. Ensure no
functional net is assumed to be connected.
EXPLANATION:
The program attempts to put a mux on the net feeding the memory pin to isolate the test
path from the functional one. As no functional net was connected to the referenced pin,
functional path of the mux was left unconnected.
USER RESPONSE:
Verify that no functional net is stitched to the referenced pin.

WARNING (TEM-060): No corresponding write enable pin found for a write enable mask
pinName|busname on a memory cell memCellName. Ensure a write enable exists for
each corresponding memory port with a write enable mask.
EXPLANATION:
The program verifies that each port with a write enable mask also has an associated
write enable pin or bus.
USER RESPONSE:
Verify each port of the referenced memory cell with a write enable mask also has an
associated write enable pin or bus.
WARNING (TEM-061): Cannot determine the size of the address bus for memory cell
memCellName from the default cell name format. Memory BIST will not be inserted. Ensure
the cell name either conforms to the default format or the address size is specified in the
configuration file.
EXPLANATION:
The program cannot infer the size of the address bus from the memory cell name. Either
the address size of a memory cell is not explicitly defined in the configuration file or the
memory cell name is not compatible to the default cell name format.
USER RESPONSE:
Ensure either the address of the memory cell is explicitly defined in the configuration file
or the memory cell name complies with the default format.
Refer to Inserting Memory Built-In-Self-Test Logic in Design For Test in Encounter
RTL Compiler for information on specifying the memory size in the configuration file and
the default memory cell name template.
WARNING (TEM-062): Cannot find instanceName moduleName in the module/Entity

fullInstName, while searching for the target instance instance | pin | net |
port. The memory BIST will not be inserted. Correct the target specification.
EXPLANATION:
The program is unable to locate the intermediate instance in the
referenced module/entity while searching for a target instance.
USER RESPONSE:
Ensure the target memory location is correctly specified. Specifically, check the
existence of the intermediate instance in the specified module.

WARNING (TEM-063): The memory cell memCellName contains no redundancy

information but the target group has redundancy enabled. Redundancy analysis will not be
possible on this memory cell. Ensure the memory cells redundancy information is provided
in the configuration file, if it exists.
EXPLANATION:
The configuration file contains no redundancy information regarding the specified
memory cell. If no redundancy parameters are specified for the rows and columns of a
memory cell, the program assumes no redundancy. In the current scenario, the target
group in the configuration file is required to have the redundancy analysis, but the
memory cell targeted by the group contains no redundancy information.
USER RESPONSE:
Verify the redundancy information for the specified memory cell is contained in the
configuration file. Refer to Inserting Memory Built-In-Self-Test Logic in Design For
Test in Encounter RTL Compiler for information related to the definition of redundancy
information of the memory cell in the configuration file.
WARNING (TEM-064): Memory cell memCellName has a zero length address bus
Memory BIST is not inserted for this cell. Correct file liberty_file and rerun if
necessary.
EXPLANATION:
The program detected the address bus of zero length for the referenced memory cell.
USER RESPONSE:
Verify the length of the address bus of the referenced cell is zero.
WARNING (TEM-065): The program cannot determine the exact address size of memory
cell memCellName because the cells max address value is maxAddrVal and the
computed address value is calculatedAddrVal. Memory BIST is not inserted for this
cell. Specify the address explicitly in the configuration file.
EXPLANATION:
The calculated address is greater than the maximum address that can be supported by
the memory cell. No instances of the memory cell have memory BIST inserted.
USER RESPONSE:
Ensure either the memory cell name conforms to the documented default cell name
template or the exact address of a memory cell is specified in the configuration file using
the documented syntax Refer to Inserting Memory Built-In-Self-Test Logic in Design
For Test in Encounter RTL Compiler.

WARNING (TEM-066): Instance instName in the target search path pathName is either
a blackbox or a standard technology cell instance found in module moduleName. Memory
BIST cannot be inserted in this instance. Ensure the hierarchical target path contains no
blackbox or technology cell.
EXPLANATION:
The program is unable to verify the hierarchical target instance because the target name
contains either a blackbox or a technology cell instance name.
USER RESPONSE:
Ensure the hierarchical target path contains no blackbox or technology cell.
WARNING (TEM-067): Memory cell memCellName is redefined in liberty file

libFileName. The previous cell definition found in liberty file usedlibFileName is
ignored. Ensure either only one definition is provided for each memory cell or the desired
definition is provided last.
EXPLANATION:
The Memory cell was last defined in the referenced liberty file. If the memory cell is
redefined by another liberty file, the program ignores the previous definition of the cell.
USER RESPONSE:
Ensure only one definition of the memory cell is provided or that the last cell definition
provided to the program is the desired one and rerun if necessary.
WARNING (TEM-068): Cannot BIST redefined memory instance memInstName of

memory cell memCellName. The ignore group in configuration file has a priority over target
group.
EXPLANATION:
A memory instance is defined multiple times in the configuration file. The instance should
be either part of an ignore group or part of a target group. If an instance is part of both
groups, then the ignore group is given a priority over the target group. The instance can
be redefined in the configuration file by defining an instance name or memory cell name
multiple times. The cell name in the target group implies to insert BIST to each and every
instance of a memory cell. Similarly, a cell name in ignore group prevents inserting BIST
to any instance of a memory cell.
USER RESPONSE:
Ensure the referenced memory instance is defined only once in the configuration file and
rerun if necessary.

WARNING (TEM-069): The number of clock pins associated with bist enable pin
bistEnPinName, of memory cell memCellName, is inconsistent. Check the .lib file
libFileName to ensure there are two clocks related to bist enable pin only if memory
supports test wrapped clock port. Otherwise functional clock should be the only related clock
to bist enable pin.
EXPLANATION:
A BIST enable pin is used to switch memory port operation from functional mode to test/
BIST mode. If the memory cells port has only functional clock pin and no test wrapped
clock pin then bist enable is required to only relate to functional clock pin. If a port has
both functional clock and test wrapped clock pins, functional and test wrapped clock pins
should be the only clocks related to bist enable pin in the liberty file.
USER RESPONSE:
Check the liberty file to ensure that the BIST enable pin is only related to functional and
test wrapped clocks that exist for a port and rerun.
WARNING (TEM-070): Multiple clock pins are associated with bist enable pin
bistEnPinName, of memory cell memCellName. Clock pins are not evenly divided
among test wrapped and non test wrapped clocks. Check .lib file libFileName to ensure
that functional and test clocks are related to specified bist enable pin.
EXPLANATION:
A BIST enable pin is used to switch memory port operation from functional mode to test/
BIST mode. If the memory cells port has only functional clock pin and no test wrapped
clock pin then bist enable is required to only relate to functional clock pin. If a port has
both functional clock and test wrapped clock pins, functional and test wrapped clock pins
should be the only clocks related to bist enable pin in the liberty file. The specified bist
enable pin is related to multiple clocks pins and the number of related test wrapped clock
pins is not equal to number of functional clock pins.
USER RESPONSE:
Check the liberty file to ensure that the BIST enable pin is only related to functional and
test wrapped clocks that exist for a port and rerun.
WARNING (TEM-071): Cannot find the clock pin related to pin/bus pinName | busName
of memory cell memCellName. Check .lib file libFileName for a related clock pin
attribute for the referenced pin/bus. Cannot insert BIST to any instances of memory cell
memCellName.
EXPLANATION:

It is required to have an individual clock pin per memory port. Unique clock pins per
memory cell are used to determine the number of ports on a memory cell and also to
relate pins/buses to their corresponding ports using the related clock attribute in the
liberty (.lib) file. For the referenced pin/bus, no related clock attribute was found in the .lib
file. The program also attempted to check if the referenced pin is used as related pin to
some other pin of a same port, but no other pin/bus of a same port used the referenced
pin/bus as a related pin. Thus port association for a referenced pin/bus cannot be
determined.
USER RESPONSE:
Check the liberty file to ensure the related clock pin attribute is specified for the
referenced pin/bus and rerun.
WARNING (TEM-072): Cannot connect pin pinName of memory instance instName to

memory by-pass logic instance byPassInstName. No functional net is connected to the
specified pin in module moduleName. Ensure a functional net exists for the pin to be
connected to logic bypass instance.
EXPLANATION:
The program inserts memory bypass logic to enable test pattern generation of faults
inside the input cone of a memory cell.
Memory bypass logic enables propagation of faults from the input data bus to the output
data bus. Bypass logic also adds scannable flops to improve testability of faults on the
address bus and control lines of the memory cell.
Since there is no functional net for the referenced pin, the pin is not connected to the logic
bypass for this memory cell.
USER RESPONSE:
Ensure a functional net is connected to referenced pin so that it can be connected to
memorys logic bypass instance. Refer to Inserting Memory Built-In-Self-Test Logic in
Design For Test in Encounter RTL Compiler.
WARNING (TEM-073): Redundancy analysis is not supported for cell cellName. Check
the documentation for supported memory types for redundancy analysis and determine
whether the specified cell can be replaced by the supported memory cells.
EXPLANATION:
The program performed redundancy analysis to determine rows and/or columns which
should be replaced to avoid known failures. Redundancy analysis computes the
minimum number of rows and columns that must be replaced for the memory cell to
correctly function. Currently, the program supports limited types of memory cells for

redundancy analysis. The referenced cell is not one of the supported types; therefore
redundancy analysis is not performed for this cell.
USER RESPONSE:
Ensure the referenced memory cell is among the supported memory cells for
redundancy analysis.
WARNING (TEM-074): The premodel attribute file contains a keyword and value that are
ignored. The file containing the keyword is: premodelFile. Keyword keyword with value
value is not be used because it conflicts with the value required by the
insert_embedded_test command. This value can not be changed.
The value required by insert_embedded_test is %4$s.

EXPLANATION:
The program requires certain keywords to be set to specific values for synthesis to
successfully complete. These required values cannot be changed.
USER RESPONSE:
Ensure the values required by insert_embedded_test will not cause problems for the
design during the synthesis process.
WARNING (TEM-080): Memory instance memInstanceName of memory cell

memCellName is specified multiple times in the configuration file. The last specification in
the file, or the ignore group, is used. Ensure only one BIST requirement is specified per
memory instance
EXPLANATION:
If there are multiple BIST requirements for a memory instance, the last provided BIST
requirement is used for that memory instance, unless one of the specifications is in an
ignore group. BIST requirements may be defined multiple times either by having the
same instance or a memory cell name as part of multiple ignore and/or target groups.
Another way to define multiple requirements for a memory instance is by first setting it
using an instance name and later setting it to different requirement using a cell name or
vice-versa.
USER RESPONSE:
Verify that the last defined requirement for a memory instance is the intended
requirement. Note the ignore group in the configuration file has priority over the target
group.

WARNING (TEM-081): Unable to determine all the BIST-related details for the memory cell
memoryCell. Memory BIST is not inserted for any instances of this cell. Verify all previous
messages related to the memory cell are resolved.
EXPLANATION:
The program was unable to completely exploit the details of the referenced memory cell
and will ignore the BIST insertion on all its instances.
USER RESPONSE:
Ensure that previous messages related to the referenced memory cell are resolved.
WARNING (TEM-083): Inserted a two input OR gate on net netName which was originally
connected to JTAG pin pinName. Ensure an addition of a logic gate on the JTAG attention
path is a desired result.
EXPLANATION:
To connect a memory BIST attention signal to the referenced pin, the program first
checks if there is already another source connected to the pin. If so, the program inserts
an OR gate to the MBIST attention signal with the referenced net. If no other source is
connected to the referenced pin then the MBIST engines attention is directly stitched to
the output pin.
USER RESPONSE:
Verify the new JTAG connection is the desired result.
WARNING (TEM-084): Multiple sink pins are connected to net netName. Sink pin
pinName of instance instanceName is used to connect the MBIST engines output signal
mbistJTAGSignal of JTAG connection type JTAGConnType. Ensure the referenced
sink pin can be used for the specified JTAG connection type.
EXPLANATION:
The referenced net has multiple sink pins connected to it. To determine a proper sink pin
to which the memory BIST engines output can be connected, the program traverses
through all the sinks to find whether a sink pin is contained by an instance whose name
has JTAG_ as part of its name.
The referenced sink pin is one of the pins that are contained by an instance that has
JTAG_ as part of its name. The program will connect the specified MBIST engines output
signal to the sink pin.
If the net had only one sink pin, the program would have stitched the MBIST engines
output to the sink pin without having to compare the instance name for JTAG_.

USER RESPONSE:
Verify that the selected JTAG pin is the correct pin for this connection.
WARNING (TEM-085): No write enable pin associated with write clock clockName was
found for memory cell memCellName. Chip select/enable pin pinName associated with the
write clock is used as the ports write enable pin. Ensure no memory vendor guidelines are
violated.
EXPLANATION:
The memory cell contains separate read and write ports. To connect the write enable pin
of the BIST engine to the write enable signal of the memorys write port, the program first
looks for the write enable pin associated with memorys write clock. If the write enable
pin on the memorys write port is found, the pin is connected to the write enable of the
BIST engine. If the memorys write port does not have a write enable pin associated with
it, the chip select or chip enable pin associated with the write clock is used as a write
enable pin. In the latter case, the write enable pin of the memory BIST engine is
connected to the chip select or chip enable pin of the memorys write port.
USER RESPONSE:
Verify that the memorys write port does not have an explicit write enable pin associated
with it. In addition, verify that using a chip select or chip enable as a write enable does
not conflict with the memory vendors guidelines.
WARNING (TEM-086): No read enable pin associated with read clock clockName was
found for memory cell memCellName. Chip select or chip enable pin pinName associated
with the read clock is used as the ports read enable pin. Ensure no memory vendor
guidelines are violated.
EXPLANATION:
The memory cell contains separate read and write ports. To connect the read enable
signal of the BIST engine to read the enable signal of the memorys read port, the
program first looks for a read enable pin associated with the memorys read clock. If a
read enable pin on memorys read port is found, the pin is connected to the read enable
signal of the memory BIST engine. If the memorys read port does not have a read
enable pin associated with it, the chip select or chip enable pin associated with the read
clock is used as a read enable pin. In the latter case, the read enable pin of the memory
BIST engine is connected to the chip select or chip enable pin of the memorys read port.
USER RESPONSE:
Verify the memorys read port does not have an explicit read enable pin associated with
it. In addition, verify that using the chip select or chip enable as a read enable does not
conflict with the memory vendors guidelines.

WARNING (TEM-087): Pin pinName of memory cell memCellName is set to clock either
by the user or based on the default naming convention, but the liberty (.lib) file does not have
an associated clock statement. The pin is treated as a clock. Verify the referenced pin is
supposed to be a clock pin. If so, add the clock statement to the pin definition in the
corresponding .lib file.
EXPLANATION:
A conflict was detected between the clock definitions of the referenced pin in the liberty
(.lib) file and the definition extracted either from the user or from the default naming
convention. The user or naming convention suggests the pin to be a clock pin, but no
clock statement found in the liberty file for the referenced pin.
USER RESPONSE:
Ensure the liberty (.lib) file contains the proper clock definition for the referenced pin.
INFO (TEM-088): Input pin pinName on memory instance memInstName of memory cell
memCellName is left unconnected. Ensure the pin is required to be left unconnected.
EXPLANATION:
The referenced scalar pin is not connected to the BIST engine due to one of the following
causes:
The pin has been explicitly set to unconnected through a port action.
A default action for the unknown pin is set to unconnected in a configuration file
for the corresponding memory cell module specification.
USER RESPONSE:
Verify the referenced pin of a given instance is required to be unconnected.
INFO (TEM-089): Input bus busName of the memory cell instance memCellName is left
unconnected. Ensure the bus is required to be left unconnected.
EXPLANATION:
The referenced bus is not connected to the BIST engine due to one of the following
causes:
The bus has been explicitly set to unconnected through a port action.
A default action for the unknown pins is set to unconnected in a configuration
file for the corresponding memory cell module specification.
USER RESPONSE:

Verify the referenced pin of a given instance is required to be unconnected and rerun if
necessary.
INFO (TEM-090): Ignoring an internal bus busName of the memory cell memCellName.
Ensure the bus is an internal bus.
EXPLANATION:
The program ignores internal bus(es). Only required input and output buses are used to
connect the memory BIST logic to the memory under test. Any input or output bus that
does not need to connect to the BIST engine should be either tied or left unconnected
using the port action or the port alias statements in the memory module section of the
configuration file.
USER RESPONSE:
Verify the referenced bus is an internal bus.
INFO (TEM-091): Ignoring an internal pin pinName of the memory cell memCellName.
Ensure the specified pin is an internal pin.
EXPLANATION:
The program ignores all the internal scalar pins of a memory cell. Only required input and
output pins are used to connect the memory BIST logic to the memory under test. Any
input or output pin that does not need to connect to the BIST engine should be either tied
or left unconnected using the port action or the port alias statements in the memory
module section of the configuration file.
USER RESPONSE:
Verify the referenced pin name is a non-input pin.
INFO (TEM-093): Pin pinName of the memory cell memCellName is tied to logic
tieVal. Ensure the pin is tied to a required value.
EXPLANATION:
The referenced pin is marked as a clock in the liberty (.lib) file. All the pins that relate to
the referenced pin as a clock signal in the .lib file are either tied to a constant value or left
unconnected. As the referenced pin is not a synchronous signal to any pin or bus
connected to the BIST engine, the pin is tied to a specified logic value.
USER RESPONSE:
Verify the referenced pin is tied to a desired value.

WARNING (TEM-094): Memory BIST insertion supports synchronous static rams. Ignoring
the memory cell memCellName.
EXPLANATION:
The program does not process asynchronous static rams or synchronous non-static
rams.The only supported memory cell group is synchronous static rams.
USER RESPONSE:
Verify the referenced memory cell is not a synchronous static ram.
WARNING (TEM-095): Unable to find the number of port(s) on the memory cell
memCellName. Memory BIST is not inserted for this cell. Ensure each port has a distinct
address bus and a clock pin.
EXPLANATION:
The program determines the number of ports of the memory cell by using the number of
individual address buses and distinct clock pins feeding a memory cell. An address bus
and a clock pin associated with a memorys port are extracted from the liberty file.
USER RESPONSE:
Verify that an individual address bus and a distinct clock pin feed each port of a
referenced memory cell in the liberty file.
WARNING (TEM-096): Data bus busName of memory cell memCellName is not a

supported type of bus. Memory BIST is not inserted for this cell. Ensure the data bus type is
one of the supported ones.
EXPLANATION:
The program supports a data bus which performs either a read or a write operation.
Other types of data operations are not currently supported.
USER RESPONSE:
Ensure the data bus performs either a read or a write operation.
WARNING (TEM-097): Cannot determine the initial and final bus indices of the bus
busName of the memory cell memCellName. Memory BIST is not inserted for this cell.
Verify the indices are specified in the liberty file.

EXPLANATION:
The program is unable to determine the start and the end indices of the referenced bus.

USER RESPONSE:
Ensure the initial and final bus indices are included in the liberty file.
WARNING (TEM-098): Cannot determine type and or functionality of pin pinName of

memory cell memCellName. Memory BIST is not inserted for this cell. Verify the pin type is
valid.
EXPLANATION:
The program was unable to recognize the type or the functionality of the referenced pin.
RTL Compiler.
USER RESPONSE:
Ensure the referenced pin type is input, output, or internal. Refer to Inserting Memory
Built-In-Self-Test Logic in Design For Test in Encounter RTL Compiler.
WARNING (TEM-099): Cannot determine type and or functionality of pin pinName of

memory cell memCellName. Memory BIST is not inserted for this cell. Verify the pin type is
valid.
EXPLANATION:
The program was unable to recognize the type or the functionality of the referenced pin.
RTL Compiler.
USER RESPONSE:
Ensure the clock input to the memory cell is active high.
WARNING (TEM-100): Could not open input file filename. Ensure the path and file name
are correct.
EXPLANATION:
The configuration file could not be found when the application attempted to open it for
input.
USER RESPONSE:
Ensure the path and file name are correct.


WARNING (TEM-110): Lexical analyzer error at line linenum.column message.
Correct the problem identified by the detailed message.
EXPLANATION:
The lexical analyzer has detected an error in the configuration file at the specified line
and column number.
USER RESPONSE:
Correct the problem identified by the detailed message. Refer to Inserting Memory Built-
In-Self-Test Logic in Design For Test in Encounter RTL Compiler.
WARNING (TEM-111): Lexical analyzer error at line.start column-end column

linenum.start_column-end_column message. Correct the problem identified by
the detailed message.
EXPLANATION:
The lexical analyzer has detected an error in the configuration file at the specified line
and column numbers.
USER RESPONSE:
WARNING (TEM-112): Configuration file line line.column linenum.column message.

Correct the problem identified by the detailed message.
EXPLANATION:
The parser has detected an error in the configuration file at the specified line and column
number.
USER RESPONSE:
WARNING (TEM-113): Configuration file line.start column-end column

linenum.start_column-end_column message. Correct the problem identified by
the detailed message.
EXPLANATION:

The parser has detected an error in the configuration file at the specified line and column
number.
USER RESPONSE:
ERROR (TEM-114): Configuration file parsing detected

memory_allocation_error_count memory allocation errors. Check the system for
the load and available memory.
EXPLANATION:
The parser has detected error(s) during dynamic memory allocation and cannot continue
processing.
USER RESPONSE:
Check the system for memory issues prior to attempting execution again.
WARNING (TEM-115): Configuration file filename contains no valid target group

configuration for inserting memory BIST. Ensure that at least one valid target group exists.
EXPLANATION:
The configuration file does not contain valid target group configurations, implying that no
target memory devices have been selected for BIST insertion.
USER RESPONSE:
Ensure that at least one valid target group configuration exists to enable memory BIST
insertion to proceed, then retry.
WARNING (TEM-116): Configuration file module group specification at line linenum re-
specifies memory module memory_module. It is ignored. Verify all the memory related
information is provided in a single module group.
EXPLANATION:
Memory modules can be defined in only a single module group specification statement.
The referenced memory module name appears in more than one module group
specification.
USER RESPONSE:
Ensure that all information related to any memory module is contained in a single module
group specification.

WARNING (TEM-117): Configuration file module group specification at line linenum

contains only re-specified memory modules. It is ignored. Verify all the memory related
information is provided in a single module group.
EXPLANATION:
Memory modules can be defined in only a single module group specification statement.
This module group specification contains only reused memory module names and is
removed from consideration.
USER RESPONSE:
Ensure that all information related to any memory module is contained in a single module
group specification.
WARNING (TEM-118): Configuration file module address partition specification at line

linenum contains a non-zero least significant column address bit column_lsb. Ensure
column keyword contains at least one zero-valued address index.
EXPLANATION:
Memory module address partition specifications must include a column keyword with at
least one address bit index value being zero. The address partition statement at the
specified line number does not satisfy this requirement.
USER RESPONSE:
Correct the memory module address partition specification statement to include a
column keyword with at least one zero-valued address index.

linenum contains an order keyword with too many address values. Ensure the number of
values in the address partition are less than or equal to the column address. Consult the
reference document regarding the module address partition specification.
EXPLANATION:
Memory module address partition specifications may include an order keyword
indicating the physical address sequence within the column address portion of the
memory module address space under the following restrictions:
The number of values must be a power of two
The number of values must be less than or equal to the number of column
addresses
Each address within the range must be specified once.
USER RESPONSE:

Modify the memory module address partition specification statement to include the
correct number of order address values.

linenum contains an order keyword with non-power of two address values. Ensure the
order size is a power of two. Consult the reference document regarding the module address
partition specification.
EXPLANATION:
addresses
USER RESPONSE:
correct number of order address values. Refer to Inserting Memory Built-In-Self-Test
Logic in Design For Test in Encounter RTL Compiler.

linenum contains an order keyword with invalid or missing address values. Consult the
reference document for memory module address partition specification.
EXPLANATION:
addresses
USER RESPONSE:
correct number of order address values. Refer to Inserting Memory Built-In-Self-Test
Logic in Design For Test in Encounter RTL Compiler.


linenum contains an invalid least significant row address bit row_lsb. Ensure the least
significant row address bit is one greater than the columns most significant bit.
EXPLANATION:
Memory module address partition specifications may include a row keyword indicating
the address bit(s) used within the row address portion of the memory module address
space under the following restriction:
The row least significant address bit must be one greater than the column most
significant bit.
USER RESPONSE:
correct row least significant address bit.

linenum contains an invalid least significant bank address bit bank_lsb. Verify the bank
least significant address bit is one greater than the rows most significant bit.
EXPLANATION:
Memory module address partition specifications may include a bank keyword indicating
the address bit(s) used within the bank address portion of the memory module address
space under the following restriction:
The bank least significant address bit must be one greater than the row most
significant bit.
USER RESPONSE:
correct bank least significant address bit.
WARNING (TEM-124): Memory cell memcell not found in netlist.

EXPLANATION:
The referenced memory cell was specified in the configuration file, but was not found in
the netlist.
USER RESPONSE:
Either correct the memory module specification in the configuration file to a valid memory
cell name or remove the memory module specification and rerun if necessary.

INFO (TEM-203): Writing design_state VHDL | Verilog | EDIF output netlist of

test macro macro_name to file vhdl_output_file.
EXPLANATION:
This information message indicates that VHDL output net list file is being written.
USER RESPONSE:
INFO (TEM-204): Deleting unconnected ports on program generated module full_name.

EXPLANATION:
This information message indicates that unconnected ports are being deleted.
USER RESPONSE:
INFO (TEM-206): Synthesis/Timing ran successfully for module: full_name.

EXPLANATION:
This information message indicates that synthesis successfully completed.
USER RESPONSE:
INFO (TEM-207): Synthesis ran successfully for module: full_name.

EXPLANATION:
This information message indicates that synthesis successfully completed.
USER RESPONSE:
INFO (TEM-210): Directory dirName was not found. Creating directory dirName.
EXPLANATION:
The specified directory does not exist. The program is creating the specified directory.
USER RESPONSE:

INFO (TEM-211): Checking the existence of file filename.

EXPLANATION:
The program is determining whether the required input file exists.
USER RESPONSE:
ERROR (TEM-217): [Tool] Cannot create directory directoryname for internal

processing. Ensure you can write to /tmp and that there is available disk space in the
directory. Fix the problem and rerun.
EXPLANATION:
The application could not create the specified directory. The application will terminate.
USER RESPONSE:
The directory is used for internal, temporary processing files. Ensure file permissions for
/tmp allow you to write data into it. Ensure there is enough disk space available in the
/tmp directory. Once the space and/or permissions have been corrected, rerun.
ERROR (TEM-218): [Tool] Cannot create directorydirectoryname for storing

generated output. Check the WORKDIR specification to ensure the file permissions allow
creation of directories and that there is available disk space. Fix the environment and rerun.
EXPLANATION:
The application could not create the specified directory. The application will terminate.
USER RESPONSE:
The directory is a sub-directory of the workdir used for permanent output files. Verify that
you specified a good WORKDIR to use for the process. It must have file permissions that
allow you to write data into it; and must have enough disk space available to contain the
output of the Encounter Test processes.
See Encounter Test: Release: Whats New for guidelines on disk space
requirements.
ERROR (TEM-219): [Tool] Cannot copy file source_file to target_file. Check the
source file to ensure it exists; check the file permissions and the available disk space to
ensure you have the ability to create the copy, and then rerun.
EXPLANATION:

The application creates copies of the macro netlist at various stages of the processing,
technology independent, technology mapped, and then scan inserted. This message
indicates that the current copy could not be made. The application will terminate.
USER RESPONSE:
Verify the source file exists, the permissions allow you to create files, and there is
adequate space is available to perform the copy, and then rerun.
INFO (TEM-220): Starting Synthesis of an embedded test macro: full_name.

EXPLANATION:
This informational message lists the name of the embedded test macro that is
undergoing synthesis.
USER RESPONSE:
INFO (TEM-221): Embedded test macro macro_name is targeted to run at

clock_frequency Mhz
EXPLANATION:
This informational message lists the target clock frequency for the embedded test macro
being synthesized.
USER RESPONSE:
ERROR (TEM-250): [Internal] Name of internally generated macro was not provided by the
calling application. Contact Cadence customer support.
EXPLANATION:
USER RESPONSE:

If there is a potential workaround suggested in the message, you may try it to continue
experimenting. However, it is required to rerun the command once a fix is provided by
customer support.

ERROR (TEM-251): [Internal] Name of internally generated macro macro_name was not
alphanumeric. Contact Cadence customer support.
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-252): [Internal] Full module name for an internally generated embedded
test macro macro_name was not provided by the calling application. Contact Cadence
Customer Support.
EXPLANATION:
USER RESPONSE:

customer support.
ERROR (TEM-253): [Internal] Full module name full_name was not specified as
alphanumeric. Contact Cadence Customer Support.
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-254): [Internal] Cannot find the internally generated macro macro_name
in the internal synthesis database. Contact Cadence Customer Support.
EXPLANATION:
USER RESPONSE:
customer support.

ERROR (TEM-255): [Internal] The program generated tie value for port portName to be
deleted was macroName, this is not a valid value. Contact Cadence Customer Support.
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-256): [Internal] Port portName was not found on an internally generated
embedded macro macroName. Contact Cadence Customer Support.
EXPLANATION:
USER RESPONSE:
customer support.
WARNING (TEM-258): [Severe] Timing optimization failed to achieve zero negative slack
for module fullModuleName at target frequency targetFrequencyValue Mhz.
Frequency achievableFrequency Mhz can be achieved. Specify at most
achievableFrequency Mhz as a target frequency in the configuration file and rerun.
EXPLANATION:

Timing failed to achieve the target frequency with zero negative slack. The referenced
embedded macro is expected to run at maximum frequency (achievableFreq) for
the given target technology.
USER RESPONSE:
Specify the achievable frequency to synthesis and timing in the configuration file and
rerun.
ERROR (TEM-259): [Internal] Internally generated file fileName was not found. Contact
Cadence Customer Support.
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-261): [Internal] The program generated clock frequency for macro
macroname: clock_frequency was not valid. Contact Cadence Customer Support.
EXPLANATION:
USER RESPONSE:
customer support.

INFO (TEM-300): This script performs an analysis of the insert_embedded_test

generated diagnostic patterns.
EXPLANATION:
The script calculates how many miscompares are expected and how many occurred.
USER RESPONSE:
INFO (TEM-301): Parsing the test data register mapping file filename
EXPLANATION:
The program has started parsing the referenced test data register mapping file.
USER RESPONSE:
INFO (TEM-302): Analyzing data for:

MBIST Engine: engine
Target Memory: target
EXPLANATION:
The insert_embedded_test engine number and target memory number being
analyzed are displayed. The target memory number relates to the netlist summary at the
bottom of the insert_embedded_test log.
USER RESPONSE:
INFO (TEM-303): Expected SA0 faults: sa0faults

Expected SA1 faults: sa1faults
Total Expected Failures: totalfaults
EXPLANATION:
The predicted number of stuck-at-0 and stuck-at-1 faults and the total number of
predicted failures are displayed.
USER RESPONSE:

INFO (TEM-304): Total Failures Analyzed: totalFails

EXPLANATION:
The total number of analyzed failures are displayed. The displayed bit fail map table
represents the failing address and bit locations as determined from the input data.
USER RESPONSE:
INFO (TEM-305): Calculated rows/cols to be repaired match actual rows/cols (from

patterns).
EXPLANATION:
The calculated rows and columns (address and bits) determined from the algorithm
match the rows and columns identified by the patterns.
USER RESPONSE:
INFO (TEM-306): This utility does analysis on the repair simulation patterns. These patterns
consist of diagnostic patterns and repair patterns.
The following steps are done on the pattern set:

1. Analyze the diagnostic patterns to determine the addresses/bits that are indicated as
failing.
2. Use the addresses/bits identified in step 1 to determine if the fails can be repaired, and
if so, the addresses and bits that require repair.
3. Analyze the repair patterns to determine what address/bit combinations were selected
to be repaired.
4. Verify the addresses/bits from step 2(those calculated that need to be fixed) match the
addresses/bits from step 3 (those identified by the patterns).
If the address/bit combinations identified by the repair patterns match the address/bit
combinations indicated by the diagnostic patterns, then there is a match, else they do not
match.
EXPLANATION:
The function of the script and available options are explained.
USER RESPONSE:

INFO (TEM-307): Redundancy analysis summary: string repairable

Recommended rows/columns to fix: fixrowscols:
Redundancy capability defined: rowcolcapdefined
Redundancy capability unused: unusedrowcol
EXPLANATION:
This is a summary of the redundancy capabilities of the target device, and an indication
if all failures can be fixed. The recommended rows and columns to fix are identified along
with the devices capabilities and unused capability.
USER RESPONSE:
INFO (TEM-308): Parsing the insert_embedded_test log file filename.

EXPLANATION:
The program is parsing the referenced insert_embedded_test log file. The netlist
summary at the bottom of the log is utilized.
USER RESPONSE:
INFO (TEM-309): Parsing the chip pad pattern (cpp) file filename.
EXPLANATION:
The program is parsing the referenced chip-pad-pattern file. The file is used to determine
where the failures for the device have occurred.
USER RESPONSE:
INFO (TEM-310): Parsing the pattern file filename.

EXPLANATION:
The program is parsing the referenced pattern file name. The file contains patterns which
are analyzed to determine where the first Measure_PO event occurs
USER RESPONSE:

INFO (TEM-311): Parsing the simulation log file filename.

EXPLANATION:
The program is parsing the simulation log file to the referenced file name. The file
contains miscomparing patterns which identify specific elements of the test data
registers.
USER RESPONSE:
INFO (TEM-312): Parsing the Verilog file filename.

EXPLANATION:
The program is parsing the Verilog file that contains the diagnostic and repair patterns.
USER RESPONSE:
INFO (TEM-313): The repair patterns identified the following rows and columns need to be
fixed:
Rows: rows
Columns: columns
EXPLANATION:
The repair patterns identified the required rows and columns that require correction.
USER RESPONSE:
INFO (TEM-314): Successfully analyzed failures. Output file is: fileName.

EXPLANATION:
Analysis of diagnostic patterns successfully completed. The output log name is given.
USER RESPONSE:
INFO (TEM-315): This program performs either repair or diagnostic analysis of the
create_embedded_test generated patterns.
EXPLANATION:

This program allows for either diagnostic or repair analysis of the

create_embedded_test patterns.
USER RESPONSE:
INFO (TEM-316): No injected faults found in filename.

EXPLANATION:
Injected faults were not found in the referenced file.
USER RESPONSE:
INFO (TEM-317): Actual failures identified by the simulation results match the expected
number of fails.
EXPLANATION:
The number of failures identified by the simulation results match the expected number of
fails.
USER RESPONSE:
INFO (TEM-318): The address and bit locations where faults were manually inserted match
the address and bit locations determined by the simulation patterns for engine engine.
EXPLANATION:
The simulation patterns identify address and bit locations where faults were manually
injected. These locations match the locations where faults were manually inserted.
USER RESPONSE:
INFO (TEM-319): Chip: chipname

Total Failures Analyzed: totalFails
EXPLANATION:
The bit fail map table listed below represents the failing address and bit locations as
determined from the input data.
USER RESPONSE:

INFO (TEM-320): The address locations where faults were manually inserted match the
address locations determined by the simulation patterns for engine engine target memory
target.
EXPLANATION:
The simulation patterns identify address locations where faults were manually injected.
These locations match the locations where faults were manually inserted.
USER RESPONSE:
WARNING (TEM-321): Netlist summary information not found in the

insert_embedded_test log. Ensure the netlist summary is at the end of the file specified
with ietlog.
EXPLANATION:
The insert_embedded_test log does not contain any netlist summary information.
Netlist summary information is used to determine each memory type.
USER RESPONSE:
Inspect the file specified with ietlog and make sure the netlist summary table is printed
at the end of the log.
WARNING (TEM-322): The algorithm calculated rows/columns that require correction to

resolve all failures, do not match the rows/columns identified by the repair patterns. The
algorithm and repair patterns must identify the same rows/columns.
EXPLANATION:
The calculated rows and columns (addresses and bits) determined by the algorithm do
not match the rows and columns determined by the patterns.
USER RESPONSE:
Correct one of the following conditions and rerun:
The rows and columns identified by the patterns are incorrect.
The calculated rows and columns are incorrect.
WARNING (TEM-323): A simulation log was given as input, but the location of the injected
faults could not be determined. The simulation log is: simLog. All entries in the output table
will be marked with a *** to indicate they could not be confirmed as a valid fault location.

EXPLANATION:
The messages in the simulation log indicat where injected faults could not be correctly
processed. Verify the messages are valid.
USER RESPONSE:
Correct the messages appearing in the simulation log and then rerun.
WARNING (TEM-324): No failing patterns found in file file, so diagnostic analysis cannot
be performed. The chip-pad-pattern file may contain invalid data or no data (no failures).
Verify the contents of file.
EXPLANATION:
The cpp file may contain invalid data or no data (no failures). Failing patterns are
required to perform diagnostic analysis.
USER RESPONSE:
Verify the cpp file contains valid data, if it does not, then rerun with a valid cpp file.
WARNING (TEM-325): Excessive failures are detected. Unable to fix all failures.
EXPLANATION:
While utilizing the redundancy capabilities of the target device, the program was unable
to fix all of the row and column (address and bit) failures.
USER RESPONSE:
Too many fails exist for the device to be fixed.
WARNING (TEM-326): Number of unique fails greater than device capability. The device
supports maxuniquefails unique fails, found numuniquefailsfound unique fails.
Unique fails are: uniquefails.
EXPLANATION:
The number of unique failures for the device exceeds the redundancy capabilities of the
device.
USER RESPONSE:
There are too many unique fails to fix. Resolve some of the failures, or use a device with
a higher amount of redundancy and rerun.
WARNING (TEM-327): All row redundancy bits used. Unable to fix any more rows. During
repair analysis, more failing rows exist than the device can support.

EXPLANATION:
All of the row redundancy bits were used, and more failing rows exist.
USER RESPONSE:
There are too many unique rows to fix. Resolve some of the failures or use a device with
a higher amount of row redundancy, and then rerun.
WARNING (TEM-328): All column redundancy bits used. Unable to fix any more columns.
During repair analysis, more failing columns exist than the device can support.
EXPLANATION:
All of the column redundancy bits were used, and more failing columns exist.
USER RESPONSE:
There are too many unique columns to fix. Resolve some of the failures or use a device
with a higher amount of column redundancy, and then rerun.
WARNING (TEM-329): One or more engines did not finish executing the selected
algorithms. Engines: engines. Rerun create_embedded_test with the failurelimit
keyword set to a higher value for diagnostic patterns. Also check to make sure the clock is
properly connected and operational at the engines.
EXPLANATION:
One or more engines did not finish executing the selected algorithms for all target
devices. This may indicate that the test did not run long enough, or that there is a problem
with the clock connection to the engines.
USER RESPONSE:
Make sure the clock is properly connected to the engines indicated. Also, rerun
create_embedded_test with the keyword failurelimit set to a higher value (for
diagnostic patterns).
WARNING (TEM-330): Could not determine the EAWoffset value for the failure data
being analyzed. The EAWoffset value is used to determine what diagnostic read loop is
being executed.
EXPLANATION:
Could not determine the EAWoffset value for the failure data being analyzed. The
EAWoffset value is used to determine what diagnostic read loop is being executed. This
information can be used to print a summary table indicating when each engine has
finished.

USER RESPONSE:
To ensure the EAWoffset information is printed out, execute the contrib script
add_eawoffset.sed. This will update the patterns and cause them to print out the
EAWoffset.
WARNING (TEM-331): X values detected during simulation. PMBIST analysis may produce
unusual results. Fix the issue causing the X values.
EXPLANATION:
X values detected during simulation. These X values may produce unusual results by
analyze_embedded_test.
USER RESPONSE:
Determine the root cause for the X values and fix. Ensure that clocks are connected
properly and are running as desired.

WARNING (TEM-341): [Severe] Unable to determine pattern number for line:
lineNumber. The pattern identification may be missing or incorrect in the filetype file
filename. Data on this line is skipped. Verify the pattern identification in the specified line
is correct.
EXPLANATION:
The program was unable to determine the pattern number for the miscomparing line
while processing the simulation log file.
USER RESPONSE:
Verify the line referenced in the simulation log is correct.
WARNING (TEM-342): [Severe] Unable to determine missingfield value for line:

line. The missingfield value may be missing or incorrect in the filetype file
filename. The missingfield value is required for bitmap patterns. Data on this line is
skipped. Verify if the missingfield value in the specified line is correct.
EXPLANATION:
The program was unable to determine a required value for the miscomparing line while
processing the file.
USER RESPONSE:

Verify if the line referenced in the file is correct.
WARNING (TEM-343): [Severe] Actual failures identified by the simulation results do not
match the expected number of fails. The most likely cause is that the simulation results do not
match the engine and target being analyzed. Verify the simlog keyword points to the correct
results file and rerun.
EXPLANATION:
The number of failures identified by the simulation results do not match the expected
number of fails.
A possible cause is that the patterns do not identify the correct number of actual failures.
USER RESPONSE:
Make sure the simulation results are correct for the engine and target being analyzed. If
the simulation results look right, an error may exist in the formula used to determine the
expected number of failures; contact customer support (see Contacting Customer
Service on page 23) in this case.
WARNING (TEM-344): [Severe] The address and bit locations where faults were manually
inserted do not match the address and bit locations determined by the simulation patterns for
engine engine target memory target.
EXPLANATION:
The analyzed simulation patterns identify address and bit locations that failed. These
failing locations do not match where faults were manually injected.
USER RESPONSE:
Verify simulation results are correct, resimulate if necessary, then rerun this application.
WARNING (TEM-345): [Severe] The address locations where faults were manually
inserted do not match the address and bit locations determined by the simulation patterns for
engine engine target memory target.
EXPLANATION:
The analyzed simulation patterns identify address locations that failed. These failing
locations do not match where faults were manually injected.
USER RESPONSE:

WARNING (TEM-346): [Severe] Data bit redundancy enabled for device. The bit locations
where faults were manually inserted do not match the bit locations determined by the
simulation patterns for engine engine target memory target.
EXPLANATION:
The analyzed simulation patterns identify bit locations that failed. These failing locations
do not match where faults were manually injected.
USER RESPONSE:
ERROR (TEM-351): No test data register file specified. If insertion was done using
insert_dft mbist, use diagtdr or repairtdr to specify the filename and rerun. If
insertion was done using insert_dft pmbist, use chktdr to specify the filename and
rerun.
EXPLANATION:
The test data register (tdr) file is a required input. For insert_dft mbist, when
performing diagnostic analysis, use diagtdr=filename to specify the tdr file and when
performing repair analysis, use repairtdr=filename to specify the tdr file. For
insert_dft pmbist, use chktdr=filename to specify the tdr file.
USER RESPONSE:
Specify a tdr file using the syntax diagtdr=filename or repairtdr=filename or
chktdr=filename and rerun.
ERROR (TEM-352): Input file filename does not exist. Verify the file exists and is spelled
correctly, then rerun.
EXPLANATION:
The referenced input file was not found.
USER RESPONSE:
Verify the file exists and is correctly spelled, then rerun.
ERROR (TEM-353): No simulation log or chip-pad-pattern file specified. Failing patterns to

analyze must be specified using a simulation, or cpp file. Use simlog=filename or
cpp=filename to specify the failures.
EXPLANATION:
Either a simulation log file or a chip-pad-pattern (cpp) file is required as input.These files
describe the failing patterns that will be analyzed.

USER RESPONSE:
Specify a simulation log file using simlog=filenam or a cpp (chip-pad-pattern) file
using cpp=filename, then rerun.
ERROR (TEM-354): No Verilog taskdef file specified. The verilog file containing the
diagnostic patterns are required as input. Use diagpatterns=filename to specify the
file.
EXPLANATION:
The taskdef file containing diagnostic patterns is a required input.
USER RESPONSE:
Specify a verilog taskdef file that contains the diagnostic patterns using the syntax
diagpatterns=filename, then rerun.
ERROR (TEM-355): No insert_embedded_test log file specified. The

insert_embedded_test log is required input when analyzing simulation failures. Use
ietlog=filename to specify an insert_embedded_test log.
EXPLANATION:
An insert_embedded_test log is a required input when analyzing simulation failures.
The netlist summary at the bottom of the log is utilized.
USER RESPONSE:
Specify an insert_embedded_test log file using the syntax ietlog=filename,
then rerun..
ERROR (TEM-356): No Verilog file specified. Specify a Verilog file that contains execution
of the diagnostic and repair patterns using repair= filename. This is required when
analyzing the repair patterns.
EXPLANATION:
A Verilog file that contains execution of the diagnostic and repair patterns is a required
input. The Verilog file is necessary for the second phase of repair analysis.
USER RESPONSE:
Specify a Verilog file using repair= filename and rerun.
ERROR (TEM-357): Error opening file filename for reading. Verify the file name is correct
and ensure read permission for the file.
EXPLANATION:

The program was unable to open the referenced file for reading.
USER RESPONSE:
Validate the filename is correct, and that it exists, then rerun.
ERROR (TEM-358): Error opening file filename for writing. Verify the file name is correct
and ensure write permission for the file.
EXPLANATION:
The program was unable to open the referenced file for writing.
USER RESPONSE:
Verify sufficient disk space is available and that file permissions are correct, then rerun
ERROR (TEM-359): No failing diagnostic | repair patterns found in file

filename. The specified file must contain failing patterns if diagnostic analysis is to be
performed. Verify the contents of the file.
EXPLANATION:
No failing patterns were located in the simulation output. Failing patterns are required to
perform diagnostic analysis. Simulation may have ended abruptly.
USER RESPONSE:
Verify simulation can be run on this machine and that enough disk space is available,
then rerun.
ERROR (TEM-360): Failing odometer does not match expected measure odometer for the
power on patterns.
Failing odometer: failingodometer
Measure odometer: measureodometer

EXPLANATION:
The failing odometer does not match the expected measure odometer for the power on
patterns.
USER RESPONSE:
Verify simulation results are for poweron patterns, and rerun create_embedded_test
if necessary.

ERROR (TEM-361): No Measure_PO events found in file fileName. At least one

Measure_PO event must be in the file. Verify the file contents are correct.
EXPLANATION:
The program found no Measure_PO events n the Verilog taskdef file.
USER RESPONSE:
Validate the Verilog taskdef file, then rerun.
ERROR (TEM-362): Unable to determine engine/target from simulation log. The simulation
log requires engine_target as part of the file name.
EXPLANATION:
The program was unable to determine the engine and/or target from the simulation log.
USER RESPONSE:
Specify a valid simulation log that identifies the engine and target, then rerun.
ERROR (TEM-363): Unsupported port type, must be 1 or 2 port. Current target port type is
porttype.
EXPLANATION:
The port type of the target memory is unsupported. Currently only 1 and 2 port memories
are supported.
USER RESPONSE:
Use a supported memory type and rerun.
ERROR (TEM-364): Actual fails did not match expected fails. Check logfile filename for
more information.
EXPLANATION:
The actual number of failures, as determined from the simulation output, does not match
the expected number of fails, as predicted by the injected faults.
USER RESPONSE:
Verify the accuracy of the simulation results and the prediction of the expected number
of fails, then rerun.
ERROR (TEM-365): Excessive failures are detected. Unable to fix all failures.
EXPLANATION:

While utilizing the redundancy capabilities of the target device, the program was unable
to fix all of the row and column (address and bit) failures.
USER RESPONSE:
Too many fails exist for the device to be fixed.
ERROR (TEM-366): Invalid failing pad (measure port) found in CPP data. Failing pad found:
failingPad. Valid pads are: validPads.Possible mismatch between the following: CPP
data, stclkstep (or mtclkstep) chosen, pattern control file and bitmaptdr. Ensure
that all inputs are consistent with the specified experiment.
EXPLANATION:
An invalid failing pad was found in the CPP file.
USER RESPONSE:
Ensure that all the inputs used for analysis are correct, and consistent with this
experiment, and then rerun. These files include CPP data, pattern control file, and
bitmaptdr in addition to the stclkstep (or mtclkstep) keyword value.
ERROR (TEM-367): Number of unique fails greater than device capability. The device
supports maxUniqueFails unique fails, found numUniqueFailsFound unique fails.
Unique fails are: uniqueFails.
EXPLANATION:
The number of unique failures for the device exceeds the redundancy capabilities of the
device.
USER RESPONSE:
There are too many unique fails to fix. Resolve some of the failures, or use a device with
a higher amount of redundancy, then rerun.
ERROR (TEM-368): All row redundancy bits used. Unable to fix any more rows.
EXPLANATION:
All of the row redundancy bits were used, and more failing rows exist.
USER RESPONSE:
There are too many unique rows to fix. Resolve some of the failures, or use a device with
a higher amount of row redundancy, then rerun.
ERROR (TEM-369): All column redundancy bits used. Unable to fix any more columns.
During repair analysis, more failing rows exist than the device can support.

EXPLANATION:
All of the column redundancy bits were used, and more failing columns exist.
USER RESPONSE:
There are too many unique columns to fix. Resolve some of the failures, or use a device
with a higher amount of column redundancy, then rerun.
ERROR (TEM-370): Unable to determine redundancy capabilities for MBIST engine

engine target memory target. This information is required to do repair analysis.
EXPLANATION:
The program was unable to determine the redundancy capabilities for the memory
device. This information should be in the insert_embedded_test test data register
mapping file.
USER RESPONSE:
Verify the test data register mapping file contains the redundancy information, then rerun.
ERROR (TEM-371): No diagnostic failures identified. Repair analysis first identifies the
failures, before trying to fix them. Specify failures to be analyzed using cpp=filename or
simlog=filename.
EXPLANATION:
Diagnostics failures have not been identified. Repair analysis first identifies the failures
before trying to fix them.
USER RESPONSE:
Specify failures cpp=filename or simlog=filename, then rerun.
ERROR (TEM-372): Overflow bit identified by the patterns, this indicates too many failures
for this device.
EXPLANATION:
The repair patterns indicated that overflow occurred and all failures can not be fixed.
USER RESPONSE:
Possibly too many fails exist for the device to be fixed.
ERROR (TEM-373): The repair patterns did not identify any rows or columns that require
correction. The patterns must identify either rows or columns that can be fixed to resolve all
failures.

EXPLANATION:
The repair patterns did not identify any rows or columns that require correction.
USER RESPONSE:
Verify the correct patterns are specified using cpp=filename or simlog=filename
and rerun.
ERROR (TEM-374): No pattern control file specified. The pattern control file is required input
when analyzing simulation failures. Use pattercontrolfile=filename to specify a
pattern_control file and then rerun.
EXPLANATION:
A pattern_control file is a required input when analyzing simulation failures. This file
is generated by insert_embedded_test, and is located in the <workdir>/
testresults/testmode_data directory.
USER RESPONSE:
Specify a pattern_control file using the syntax pattercontrolfile=filename
and then rerun.
ERROR (TEM-375): Unable to locate filename. Specify a valid installation point with
install=location.
EXPLANATION:
The program was unable to locate the specified file or directory. This file must be
detected for this program to correctly execute.
USER RESPONSE:
Specify a valid installation point using install=location and rerun.
ERROR (TEM-376): Unable to determine failing engine/target from simulation log.

Simulation may have ended abruptly. Last failure processed correctly on line line_number.
EXPLANATION:
The failing engine and/or failing target could not be determined from the current failure
being processed.
USER RESPONSE:
The failure data may be incorrect. Refer to the indicated line number in the message text
to determine the last line of the failure data that was correctly processed.

ERROR (TEM-377): Could not determine cell type for memory memory_name. This
information comes from the netlist summary information found in the
insert_embedded_test log.
EXPLANATION:
The program was unable to determine the memory cell type. This information is needed
for failure analysis.
USER RESPONSE:
Check the netlist summary information in the insert_embedded_test log and check
to see if the specified memory instance is contained in the table. If not present, an error
has occurred during insert_embedded_test. Contact customer support (see
Contacting Customer Service on page 23). for assistance.
ERROR (TEM-378): Could not determine first measure location from pattern control file.
EXPLANATION:
The program was unable to determine the first measure location from the pattern control
file.
USER RESPONSE:
Contact customer support (see Contacting Customer Service on page 23). for
assistance.
ERROR (TEM-379): Invalid failing TBD odometer found in CPP data. Failing TBD odometer
found: failingTBDodometer. Possible mismatch between the following: CPP data,
stclkstep (or mtclkstep) chosen, pattern control file and bitmaptdr. Ensure all inputs
are consistent with the specified experiment.
EXPLANATION:
An invalid failing TBD odometer was found in the CPP file.
USER RESPONSE:
ERROR (TEM-380): Invalid failing slice index value calculated from failing TBD odometer in
CPP data. Failing slice index value calculated: failingSliceIndex. Maximum valid slice
index value: maxValidSliceIndex. Possible mismatch between the following: CPP
data, stclkstep (or mtclkstep) chosen, pattern control file and bitmaptdr. Ensure all
inputs are consistent with the specified experiment.

EXPLANATION:
An invalid failing slice index value was calculated from the failing TBD odometer in the
CPP file.
USER RESPONSE:
ERROR (TEM-381): Multiple algorithms specified on a device with bitmap analysis

requested. Bitmap analysis supports only 1 algorithm at a time. Algorithms specified:
algorithms. Recreate patterns using create_embedded_test, and specify only 1
algorithm.
EXPLANATION:
Analysis of bitmap patterns supports only 1 algorithm at a time.
USER RESPONSE:
Recreate patterns using create_embedded_test, and specify only 1 algorithm.
ERROR (TEM-382): No devices found for stepType stepValue scheduling group

selected. Specify a valid group using either the stclkstep or mtclkstep keywords.
EXPLANATION:
Invalid scheduling group specified on the command line.
USER RESPONSE:
Specify a valid scheduling group using either the stclkstep or mtclkstep keywords
ERROR (TEM-383): Multiple algorithms found for devices in scheduling group specified.
Algorithms found: algorithms. All devices within the scheduling group must have the
same algorithm specified. Specify only one algorithm for the devices.
EXPLANATION:
All devices within the scheduling group must have the same algorithm specified.
USER RESPONSE:
Specify only one algorithm for the devices.

ERROR (TEM-384): Bit index out of range for tdr mapping file specified. Bit index:
bitIndex. Possible mismatch between the following: CPP data / simulation input, pattern
control file and tdr mapping file. Ensure all inputs are consistent with the specified experiment.
EXPLANATION:
An invalid bit index was found in the CPP file.
USER RESPONSE:
Ensure all the inputs used for analysis are correct, and consistent with this experiment,
and then rerun. These files include CPP data, pattern control file, and tdr mapping file.
ERROR (TEM-385): Multiple failures detected for poweron patterns. At most, there should
be only one failing pattern for poweron patterns. Verify the simulation (or cpp) data is correct.
EXPLANATION:
For poweron patterns, there is a single measure event. Multiple failures should not be
present in either simulation results or a CPP file.
USER RESPONSE:
Verify simulation results (or CPPdata) are for poweron patterns, and rerun
create_embedded_test if necessary.
ERROR (TEM-386): This analysis type is not currently supported for insert_dft
pmbist. Only production analysis is supported at this time.
EXPLANATION:
The selected analysis type is not currently supported for insert_dft pmbist. Only
production analysis is supported at this time.
USER RESPONSE:
If analyzing production patterns for insertion is done using insert_dft pmbist, then
use the analysis=production keyword.
ERROR (TEM-387): When analyzing patterns that were generated for insertion using
insert_dft pmbist, the chktdr and testdeffile keywords must be used to specify
the mbistchk tdr mapping file and the test definition file, respectively.
ERROR (TEM-387): When analyzing either production or diagnostic patterns that were
generated for insertion using insert_dft pmbist, the chktdr and testdeffile
keywords must be used to specify the mbistchk tdr mapping file and the test definition file,
respectively. For diagnostic patterns, the diagtdr keyword must be used to specify the
mbistdiag tdr mapping file, the schtdr keyword must be used to specify the mbistsch tdr

mapping file, and the amrtdr keyword must be used to specify the mbistamr tdr mapping
file.
EXPLANATION:
The mbistchk tdr mapping file and test definition file are required inputs when analyzing
either production or diagnosticpatterns that were generated for insertion using
insert_dft pmbist. For diagnostic patterns, the mbistdiag, mbistsch and
mbistamr tdr mapping files are also required.
USER RESPONSE:
Use the chktdr and testdeffile keywords to specify the mbistchk tdr mapping file,
and the test definition file. Use the diagtdr, schtdr and amrtdr keywords to specify
the mbistdiag, mbistsch and mbistamr tdr mapping files for diagnostic patterns.
ERROR (TEM-388): Actual fails did not match expected fails. The nolog option has been
specified, therefore no log file is generated. Check the output from
analyze_embedded_test for more information.
EXPLANATION:
The actual number of failures, as determined from the simulation output, does not match
the expected number of fails, as predicted by the injected faults.
USER RESPONSE:
Verify the accuracy of the simulation results and the prediction of expected number of
fails, then rerun.

INFO (TEM-400): Beginning to merge outputType repair files for definer: definer.
EXPLANATION:
The program is beginning to merge individual repair files for the specified definer name.
Merging is required before simulation can be properly run.
USER RESPONSE:
INFO (TEM-401): Successfully created merged repair file: filename.

EXPLANATION:

Analyze Embedded Test has successfully merged the individual repair and diagnostic
patterns.
USER RESPONSE:
INFO (TEM-402): Beginning to merge outputType diagnostic files for definer: definer.
EXPLANATION:
The program is beginning to merge individual diagnostic files for the specified definer
name. Merging is required before simulation can be properly run.
USER RESPONSE:
INFO (TEM-403): Successfully created merged diagnostic file: filename.

EXPLANATION:
Analyze Embedded Test has successfully merged the individual diagnostic patterns.
USER RESPONSE:
INFO (TEM-404): Processing interface file: filename. Data is being gathered from the
referenced interface file.
EXPLANATION:
The program is reading the contents of the specified interface file.
USER RESPONSE:
INFO (TEM-405): Processing ROM load file: filename. Verifying the contents of the
referenced ROM load file.
EXPLANATION:
The program is reading the contents of the specified ROM load input file. The file is being
analyzed to ensure it meets Artisan or Virage standards. Data for Artisan memories is
stored in a binary format; data for Virage memories is stored in a hex format.
USER RESPONSE:

INFO (TEM-406): Beginning to merge outputType retention files for definer: definer.
EXPLANATION:
The program is beginning to merge individual production files for the pattern sets
identified by the specified definer name. Merging is required before retention simulation
can be properly run.
USER RESPONSE:
INFO (TEM-407): Successfully created merged retention file: filename.

EXPLANATION:
create_embedded_test has successfully merged and created retention patterns.
USER RESPONSE:
INFO (TEM-408): Created simulation script filename for definer definer for simtype
simulation.
EXPLANATION:
A simulation script has been created for simulating the specific type of patterns for the
referenced definer.
USER RESPONSE:
INFO (TEM-409): The retention experiment experiment_Name has been split up into three
separate experiments.
These experiments are:

testmode_Name_RUN - contains mode init sequence, and sequences up to the
continue loop
testmode_Name_CONTINUE - contains the continue loop (loop value = 1)
testmode_Name_DIAGNOSE - the diagnose sequence after the continue loop
Use the write_vectors command and the testmode testmode_Name to choose the
experiments.

EXPLANATION:
The default retention experiment has been split up into three unique experiments.
USER RESPONSE:
INFO (TEM-411): interfacefiledir not specified, defaulting to: path.

EXPLANATION:
The interfacefiledir keyword was not specified on the command line; using the
default value. This keyword is used to search for interface files to be processed.
USER RESPONSE:
INFO (TEM-412): Processing pattern control file: filename.

EXPLANATION:
The program is reading the contents of the specified pattern control file.
USER RESPONSE:
INFO (TEM-413): Bsdl input not specified, defaulting to: path.

EXPLANATION:
The bsdlinput keyword was not specified on the command line; using the default
value.
USER RESPONSE:
INFO (TEM-414): create_embedded_test complete, highest return code is: rc.

EXPLANATION:
create_embedded_test has finished, the highest return code is printed.
USER RESPONSE:

INFO (TEM-415): Executing generated script filename. This script is used to run
build_testmode to create a testmode which can be used for MBIST pattern generation.
EXPLANATION:
The generated script being executed will create a testmode for MBIST pattern
generation. Experiments associated with this testmode will be created, and then
write_vectors can be used to generate patterns in the desired format.
USER RESPONSE:
INFO (TEM-416): Could not access the output directory for the specified patterns. The
output directory is: dirname. Looking for pattType patterns. Make sure the proper pattern
output type is specified.
EXPLANATION:
Could not read the referenced directory. This directory should exist when patterns are
generated by insert_embedded_test or create_embedded_test.
USER RESPONSE:
INFO (TEM-417): Changing pattType scheduling number for engine engine target
target. See previous constraint violation messages for possible causes. New pattType
scheduling number is step.
EXPLANATION:
Diagnostic pattern scheduling must conform to the following constraints:
RAMs and ROMs must be in separate scheduling groups.
The following applies For RAM groups:
The read_delay values must be the same.
The diagaddrbusval values must be the same.
The number of slices must be the same.
Production pattern scheduling must conform to the following constraint:
Devices targeted by different clocks can not be grouped together.

Violations of any of these constraints forces the specific engine and target to placed in a
different scheduling group. A new pattern control file is written which contains the
updated schedule.
By default, the pattern control file is located in the <workdir>/testresults/
testmode_data directory.
USER RESPONSE:
INFO (TEM-418): A new pattern control file has been created due to the creation of new
scheduling groups. These new groups are due to a specific scheduling request using the
prodschedule or diagschedule keywords, or because of constraint violations that have
been fixed. If there were constraint violations, see previous messages for an explanation of
why new scheduling groups have been created. Pattern control files are located in the
<workdir>/testresults/testmode_data directory.
Original file saved as: origPatternControlFile
Updated file: updPatternControlFile
EXPLANATION:
A new pattern control file has been created due to changes in the original scheduling
groups. The changes to the scheduling groups have occurred because of a specific
scheduling option requested via the prodschedule or diagschedule keywords, or
because of constraint violations that were fixed.
USER RESPONSE:
INFO (TEM-419): The scheduling groups are valid.

EXPLANATION:
The scheduling groups for the selected pattern type have been verified.
USER RESPONSE:
INFO (TEM-420): The experiment experimentName has been created, and is available
for vector generation. Use write_vectors and the testmode testmodeName to choose
the experiment.
EXPLANATION:

An experiment to be used for vector generation is created.

USER RESPONSE:
WARNING (TEM-421): An internal test enable pin has been specified. Ensure that the
hierarchical TE is properly controlled.
Test enable pin: testEnablePin
EXPLANATION:
The test enable pin has been specified as an internal pin. Make sure the pin is properly
controlled.
USER RESPONSE:
Modify any assign files and/or sequence files to control the pin properly and then rerun
if necessary.
WARNING (TEM-422): Patterns are being generated for block level memory BIST and no
scan enable has been specified in the pattern control file. If scan insertion has been
performed on this design, memory BIST patterns may not execute properly until the relevant
scan enable signals are controlled inactive. Modify the pattern control file scan_enable
entry with the proper information and rerun create_embedded_test.
EXPLANATION:
The scan enable pin was not found in the pattern control file. For block level pattern
generation, this pin needs to be controlled inactive.
USER RESPONSE:
Modify the pattern control file scan_enable entry with the proper information and rerun
create_embedded_test.
WARNING (TEM-423): Bitmap patterns were requested for a group containing only ROM
devices. Bitmap patterns are not supported for ROMs and will not be generated for group
number step.
EXPLANATION:
Bitmap patterns cannot be generated for ROM devices.
USER RESPONSE:
Modify any assignfiles and/or sequence files to properly control the pin and rerun if
necessary.

WARNING (TEM-424): Algorithm list is empty for engine engine target target for
pattType patterns in the pattern control file. No pattType patterns will be generated for
this target.
EXPLANATION:
The algorithm list for the specified engine and target is empty for the pattern type.
USER RESPONSE:
Ensure this is the desired behavior, or modify the pattern control file to run the desired
algorithms.
WARNING (TEM-425): Generating poweron patterns for flowType level design, but no
monitor port found. Ensure this is the desired behavior. If a measure is desired, look in the
pattern file for the statement ## Place measure routine here, and add the appropriate routine.
Filename: filename
EXPLANATION:
Unable to measure poweron pattern results, as no monitor port was specified.
USER RESPONSE:
Ensure this is the desired behavior, or modify the pattern control file to have a monitor
pin. If a measure is desired, look in the pattern file for the statement ## Place measure
routine here, and add the appropriate routine
WARNING (TEM-426): An internal scan enable pin has been specified. Ensure that the
hierarchical SE is properly controlled. Scan enable pin: scanEnablePin.
EXPLANATION:
The scan enable pin has been specified as an internal pin. Make sure the pin is properly
controlled.
USER RESPONSE:
Modify any assignfiles and/or sequence files to control the pin properly.
WARNING (TEM-427): Internal pin internalPin has been specified for pinType.
Patterns will be generated without this pin being controlled. Ensure this is the desired
behavior.
EXPLANATION:
The pin has been specified as an internal pin. Make sure the pin is properly controlled.

USER RESPONSE:
Modify any assignfiles and/or sequence files to control the pin properly.
WARNING (TEM-428): Cannot satisfy requested schedule for directschedule keyword.

Requested schedule: requestedSchedule. missingPin pin is unavailable. Changing
directschedule to : newSchedule.
EXPLANATION:
The requested schedule type for directschedule keyword could not be satisfied due
to a missing pin. The schedule has been changed to a valid value.
USER RESPONSE:
Ensure the new schedule is acceptable.
WARNING (TEM-429): Can not satisfy requested schedule for requestschedule

keyword. The TDR (tester description rule) and maxsupportedclocks and
maxclockpulses keywords do not allow the requested schedule type to be satisfied.
Requested schedule: requestedSchedule.
TDR supported number of clocks: TDRsupportedClocks
maxsupportedclocks (keyword): maxsupportedclocks
TDR supported pulses per clock: TDRsupportedPulses
maxclockpulses (keyword): maxclockpulses
Number of clocks: numberofclocks
Max number of pulses required: maxpulsesrequired
Changing schedulekeyword to: newschedule.

EXPLANATION:
The requested schedule type could not be satisfied. The combination of values in the
TDR and values specified by the maxsupportedclocks and maxclockpulses
keywords does not satisfy the number of clocks and/or the maximum number of clock
pulses required. The schedule has been changed to a valid value.
USER RESPONSE:

Ensure the new schedule is acceptable. If a different schedule is desired, either specify
larger values for the maxsupportedclocks and maxclockpulses keywords, or
specify a new TDR using the testerdescriptionrule keyword.
WARNING (TEM-430): Missing information in the pattern control file.

The keyword blockORtopshell was specified on the command line, but
the controlFileSection section of the pattern control file is missing information.
Unable to create JTAG patterns.
EXPLANATION:
Information required for the tap_interface type is missing from the pattern control
file. For block level patterns, the tap_output section is required, and for topshell level
patterns, the tap_input section is required.
USER RESPONSE:
Ensure the desired patterns are created. If the patterns are not generated, rerun
insert_dft mbist to generate a pattern control file that contains the necessary
information.
WARNING (TEM-431): Missing information in the pattern control file.

pattType patterns were requested, but the portName port was not found in the
pattern control file. pattType patterns will not be created. If the patterns are desired,
then rerun insert_dft mbist with the pin defined.
EXPLANATION:
The port required for the requested pattern type is missing from the pattern control file.
Patterns will not be generated for the requested pattern type.
USER RESPONSE:
If the patterns are desired, then rerun insert_dft mbist after defining the pin (using
define_dft mbist_direct_access).
WARNING (TEM-432): Unable to generate bitmap patterns due to internal clock source.Can
not generate bitmap patterns when an internal clock has been specified. Turning off bitmap
patterns.
EXPLANATION:
Bitmap patterns cannot be created when an internal clock source has been specified.
USER RESPONSE:
No respone required, bitmap pattern generation has been turned off.

WARNING (TEM-433): Invalid clock ratio found for bitmap pattern group. Can not generate
bitmap patterns when the clock ratio between the port and hookup pin is not 1:1. Turning off
bitmap patterns for clocks: clock.
EXPLANATION:
Bitmap patterns can not be created for clock groups that do not have a 1:1 clock ratio
between the port and hookup pin.
USER RESPONSE:
No response required, bitmap pattern generation has been turned off for the specified
clocks.
WARNING (TEM-437): Diagnostic patterns requested and programmed ROM testplans

found with romdiag algorithm. The requested diagnostic pattern schedule is for parallel
execution. This is not supported for diagnostic ROM patterns, and the schedule will be forced
to a serial SIU and serial target schedule.
EXPLANATION:
Can not execute a parallel schedule for ROM diagnostic patterns, they must be run in a
serial fashion. The schedule will be overriden for ROMs only, RAMs will execute as
initially requested.
USER RESPONSE:
Verify the modified schedule is acceptable for ROMs.
WARNING (TEM-441): [Severe] No diagnostic patterns found. Diagnostic patterns were

requested to be generated, but none were found to merge. Check for errors during pattern
generation.
EXPLANATION:
No diagnostic patterns could be found for merging. Diagnostic patterns were requested,
but none were found.
USER RESPONSE:
Check for errors during pattern generation and resolve, then rerun.
WARNING (TEM-442): [Severe] No repair patterns found. Repair patterns were requested
to be generated, but none were found to merge. Check for errors during pattern generation.
EXPLANATION:
No repair patterns could be found for merging. Repair patterns were requested however
none were detected.

USER RESPONSE:
Check for errors during pattern generation and resolve, then rerun.
WARNING (TEM-443): Scheduling constraint violated when attempting to create diagnostic

patterns for step step ID. Different device types cannot be scheduled together. Engine
eng1 target tar1 is a type1 type, and engine eng2 target tar2 is a type type2.
EXPLANATION:
The step id is located in the pattern control file. By default, pattern control files are
located in the <workdir>/testresults/testmode_data directory. Different
device types can not be scheduled in the same group (same step).
USER RESPONSE:
Ensure all device types for a specific group are of the same type and rerun.
WARNING (TEM-444): Scheduling constraint violated when attempting to create diagnostic

patterns for step stepID. Parameter values are different. The value for engine eng1
target tar1 is val1, and the value for engine eng2 target tar2 is val2.
EXPLANATION:
located in the <workdir>/testresults/testmode_data directory. RAM
devices scheduled in the same group must have the following parameters as same:
read_delay value
diagaddrbus value
number of slices
USER RESPONSE:
Schedule the engine and target pairs in different groups and rerun.
WARNING (TEM-445): Scheduling constraint violated when attempting to create patterns

for step stepID. Different clocks can not be grouped together. The value for engine eng1
target tar1 is val1, and the value for engine eng2 target tar2 is val2.
EXPLANATION:
located in the <workdir>/testresults/testmode_data directory. Devices
which are fed by different clocks cannot be in the same group.
USER RESPONSE:


for step stepID. 2p2rw devices cannot be grouped with other devices for specific algorithms.
The device class for engine eng1 target tar1 is dc1, and the algorithm is alg1. The device
class for engine eng2 target tar2 is dc2, and the algorithm is alg2.
EXPLANATION:
located in the workdir/testresults/testmode_data directory. 2rw devices and
non 2rw devices can not be in the same group for the following algorithms:
checkerboard, march_c and port_interaction.
USER RESPONSE:

for step stepID in testplan testplan. Different clocks can not be grouped together. The value
for amu amu1 siu siu1 dcu dcu1 target tar1 is val1, and the value for amu amu2 siu
siu2 dcu dcu2 targ:et tar2 is val2.
EXPLANATION:
located in the <workdir>/testresults/testmode_data directory. Devices
which are fed by different clocks can not be in the same group.
USER RESPONSE:
Schedule the devices in different groups.

for step stepID in testplan testplan. Dcus can only execute one target at a time. amu
amu1 siu siu1 dcu dcu1 target tar1 and amu amu2 siu siu2 dcu dcu2 target tar2
must be scheduled in different groups.
EXPLANATION:
located in the <workdir>/testresults/testmode_data directory. Multiple
targets can not be executed by the same dcu.
USER RESPONSE:
Schedule the targets on the same dcu in different groups.


for step stepID in testplan testplan. Request latency must be the same for all targets on
an siu. amu amu1 siu siu1 dcu dcu1 target tar1 has a vale of val1 and amu amu2 siu
siu2 dcu dcu2 target tar2 has a value of val2. These must be scheduled in different groups.
EXPLANATION:
located in the <workdir>/testresults/testmode_data directory. Request
latency must be the same for all targets on an siu.
USER RESPONSE:
Schedule the targets on the same siu in different groups.
ERROR (TEM-450): A block or usercore must be specified. Specify a block using

block=name or a usercore using usercore=name and rerun.
EXPLANATION:
The command requires either a block or usercore be specified.
USER RESPONSE:
Specify either the block or usercore option and rerun.

ERROR (TEM-451): Unable to determine pattern number of first Measure_PO event for:
definer. The first Measure_PO event could not be located in the diagnostic patterns.
Resolve previous ERROR/WARNINGs and rerun.
EXPLANATION:
The first Measure_PO event could not be located in the diagnostic patterns. The pattern
ID and the current targeted engine are used when merging the diagnostic patterns to
indicate when simulation should stop.
USER RESPONSE:
Ensure the diagnostic patterns have been correctly generated and contain a
Measure_PO event, then rerun.
ERROR (TEM-452): Unable to determine engine number for definer. The referenced
definer name must contain the engine and target number.
EXPLANATION:

The target engine number could not be determined from the definer name. The pattern
ID of the first Measure_PO and the current targeted engine are used when merging the
diagnostic patterns to indicate when simulation should stop.
USER RESPONSE:
Ensure the definer name is correctly generated, then rerun.
ERROR (TEM-453): The total length of all segments is not equal to the length of
MBISTREAD TDR. These lengths must be equal. Verify the measure ports specified for
MBIST insertion are correct.
The length of the MBISTREAD TDR is: tdrLength
The length of all segments is: totalLength

EXPLANATION:
The length of all the segments created using one or more measure ports must be
equivalent to the length of the MBISTREAD TDR.
USER RESPONSE:
Verify the measure ports specified to the MBIST insertion command are correct. If the
pattern control file has been manually modified, ensure the ports specified in the
measure field for the bitmap pattern section is correct.
ERROR (TEM-455): Multiple interface files specified: interfaceFiles Only a single

interface file of each type is supported. Specify a single interface file of each required type.
EXPLANATION:
More than one interface file found for this type, only a single file is supported.
USER RESPONSE:
Specify a single interface file for each required type.
ERROR (TEM-456): Specified interface file does not exist: interfaceFile. Ensure the
interface file exists at the specified location.
EXPLANATION:
The specified interface file does not exist.
USER RESPONSE:
Ensure the interface file exists at the specified location.

ERROR (TEM-457): Pattern control file(s) not specified. The pattern control file is required
input for the create_embedded_test command. Use the keywords interfacefiledir
and interfacefilelist to specify a pattern control file.
EXPLANATION:
One or more pattern control files are required for the create_embedded_test
command.
USER RESPONSE:
Specify a pattern control file. By default, pattern control files are searched for in the
workdir/testresults/testmode_data directory. This can be overridden with the
interfacefiledir and interfacefilelist keywords.
ERROR (TEM-458): Unable to locate any filename files. This file is required input for the
create_embedded_test command. Use the interfacefiledir and interfacefilelist to specify
the filename file.
EXPLANATION:
One or more of the specified files are required for the create_embedded_test
command.
USER RESPONSE:
Specify the specified file. By default, the files are searched for in the
<workdir>testresults/testmode_data directory. This can be overridden by
using the interfacefiledir and interfacefilelist keywords.
ERROR (TEM-459): Could not gather information about any engine/target pairs from the
pattern control file. Verify the contents of the file are correct.
EXPLANATION:
The pattern control file contains information about specific engine/target pairs. The
program could not determine any pairs from the current pattern control file being
processed.
USER RESPONSE:
Verify the contents of the pattern control file are correct and rerun.
ERROR (TEM-460): Could not locate valid ROM load data file for cell romCellName.
Verify a valid ROM load data file is specified using the rompath and romcontentsfile
keywords. The names of the vendor-provided ROM data/contents files must begin with
romCellName in order for create_embedded_test to find them.

EXPLANATION:
ROM cells which are targeted must have a corresponding ROM load data file specified.
USER RESPONSE:
Specify a valid ROM load data file using the rompath and romcontentsfile
keywords and rerun.
ERROR (TEM-461): ROM load data file for cell: romCellName contains non zero value in
top level addresses. The top numAddresses addresses need to be 0, as they are reserved
for the MISR seed.
EXPLANATION:
For MDA (direct access) patterns, the top level addresses need to be 0. These
addresses are reserved for the MISR seed.
USER RESPONSE:
Ensure the ROM load data file contents are correct.
ERROR (TEM-462): Could not determine a least common multiple for all clock periods. This
value is used to determine the tester cycle period. Dynamic patterns can not be generated.
Choose clock frequencies which allow for a common multiple to be determined.
EXPLANATION:
For MDA (direct access) patterns, a tester cycle period needs to be established which
takes into all clock periods. The chosen clock frequencies can not be used, as a common
multiple of the periods could not be found. seed.
USER RESPONSE:
Choose valid clock frequencies.
ERROR (TEM-463): Number of lines of data in ROM load file do not match the determined
size of the ROM.
ROM load file name is filename.
The ROM load file must contain the same number of lines as the size of the ROM.
Number of lines in ROM file: numROMfileLines.
Size of the ROM: romSize.
EXPLANATION:
The ROM load file must contain the same number of lines as the size of the ROM.
USER RESPONSE:

Verify the name and contents of the ROM load data file and rerun.
ERROR (TEM-464): Width of data in ROM load file does not match the determined width of
the ROM.
ROM load file name is filename.
The width of the data in the ROM load file must match the width of the ROM.
Width of ROM: romWidth.
EXPLANATION:
The width of the data in the ROM load file must match the width of the ROM. Example
file name: ROM32X17 - Width of lines in ROM file must be 17.
USER RESPONSE:
Verify the name of the ROM load data file and rerun. Also, delete any blank lines at the
end of the ROM load data file, as this may cause a mismatch in the expected width of the
data.
ERROR (TEM-464): Width of data in ROM load file does not match the determined width of
the ROM.
ROM load file name is: fileName
The width of the data in the ROM load file must match the width of the ROM
Width of ROM: romWidth
EXPLANATION:
The width of the data in the ROM load file must match the width of the ROM.
Example file name: ROM32X17 - Width of lines in ROM file must be 17.
USER RESPONSE:
Verify the name of the ROM load data file and rerun. Also, delete any blank lines at the
end of the ROM load data file, as this may cause a mismatch in the expected width of the
data.
ERROR (TEM-465): Unable to locate ROM load file for ROM romName. Specify ROM load
files using the rompath and romcontentsfile keywords.
EXPLANATION:
The program was unable to locate the ROM load file for the referenced ROM. ROM load
files must be specified.
USER RESPONSE:

Verify/specify the name of the ROM load data file and rerun.
ERROR (TEM-466): Missing information in the pattern control file. The interface type is
specified as interfaceType, but the controlFileSection section of the pattern
control file is missing information.
EXPLANATION:
file.
USER RESPONSE:
Specify the missing information in the pattern control file and rerun MBIST insertion to
generate a valid pattern control file.
ERROR (TEM-467): Incompatible pattern control file version supplied. The pattern control
file specified is not valid with the current level of create_embedded_test, and needs to be
re-generated using a compatible level of MBIST insertion.
EXPLANATION:
An Incompatible pattern control file version was specified .
USER RESPONSE:
Rerun MBIST insertion with the current level of software to generate a valid pattern
control file.
ERROR (TEM-468): Incorrect clock name found in pattern control file.

Found pin: pinName.
Hierarchical pin names are not supported. Specify the correct port name for the specified pin,
and rerun create_embedded_test.
EXPLANATION:
The command detected an incorrect clock name in the pattern control file.
USER RESPONSE:
Specify the correct port name for the specified pin and then rerun
ERROR (TEM-469): Unable to generate cycleInfo data file using write_vectors. For
those devices with data bit redundancy enabled, a memory mapping file is created. This
mapping file contains cycle information that comes from the cycleInfo file.
Contact Cadence Customer Support for assistance.

EXPLANATION:
The program is unable to generate a cycleInfo file with the write_vectors
command. This information is required when memories have data bit redundancy
enabled and memory mapping files are to be generated.
USER RESPONSE:
Contact customer support (see Contacting Customer Service on page 23). Be
prepared to provide an example which allows application developers to recreate and
diagnose the problem.
ERROR (TEM-470): Cannot generate bitmap patterns for a block-level design. Either do not
specify bitmap patterns to be generated, or do not specify a block and then rerun.
EXPLANATION:
The create_embedded_test command does not support generating bitmap patterns
for a block-level design.
USER RESPONSE:
Do not specify bitmap patterns, or specify a dfferent usercore and topshell.
ERROR (TEM-471): Can not force directschedule to a serial (engine) schedule

because a pin does not exist.
EXPLANATION:
It is necessary to force the schedule to a serial (engine) schedule. See previous
message for why the schedule needed to be changed.
USER RESPONSE:
Ensure the requested schedule type is correct.
ERROR (TEM-472): Either a block or topshell must be specified. These keywords are
mutually exclusive. Specify either a block using block=name or a topshell using
topshell=name and rerun.
EXPLANATION:
The create_embedded_test command requires either a block or topshell to be specified.
These keywords are mutually exclusive, and only one can be specified on the command
line.
USER RESPONSE:
Use the block=<block> or topshell=<topshell> options to specify one of them.

ERROR (TEM-473): Missing information in the pattern control file. The keyword
blockORtopshell was specified on the command line, but the controlFileSection
section of the pattern control file is missing information.
EXPLANATION:
file. For block level patterns, the tap_output section is required, and for topshell level
patterns, the tap_input section is required.
USER RESPONSE:
Rerun MBIST insertion to generate a valid pattern control file.
ERROR (TEM-474): Missing information in the pattern control file. pattType patterns were
requested, but the portName port was not found in the pattern control file. Either rerun
insertion with the pin defined, or rerun create_embedded_test and do not request the
pattern type.
EXPLANATION:
The port required for the requested pattern type is missing from the pattern control file.
USER RESPONSE:
Either rerun insertion after defining the pin (using define_dft
mbist_direct_access), or rerun create_embedded_test and do not request the
pattern type.
ERROR (TEM-475): Missing information in the pattern control file. pattType patterns were
requested, but the instructionName instruction was not found in the pattern control file.
Either rerun insertion with the instruction defined, or rerun create_embedded_test and do
not request the pattern type.
EXPLANATION:
The instruction required for the requested pattern type is missing from the pattern control
file.
USER RESPONSE:
Either rerun insertion after defining the instruction or rerun create_embedded_test
and do not request the pattern type.
ERROR (TEM-476): Missing information in the pattern control file.

pattType patterns were requested, but the registerName register was not found
in the pattern control file. Either rerun insertion with the register defined, or rerun
create_embedded_test and do not request the pattern type.
EXPLANATION:
The register required for the requested pattern type is missing from the pattern control
file.
USER RESPONSE:
Either rerun insertion after defining the register or rerun create_embedded_test and
do not request the pattern type..
ERROR (TEM-477): Unable to generate any patterns. See previous messages that explain
why the pattern types requested were unable to be created.
EXPLANATION:
Unable to generate any patterns.
USER RESPONSE:
See previous messages that explain why the pattern types requested were unable to be
created, and fix the issues.
ERROR (TEM-478): Missing instruction in the BSDL file.

Instruction: instructionName
Ensure the instruction is present in the BSDL file specified, and not declared as private.
Rerun create_embedded_test with the instruction properly defined.
EXPLANATION:
The instruction required for the requested pattern type is missing from the BSDL file.
USER RESPONSE:
Ensure the instruction is present in the BSDL file specified, and not declared as private
and rerun create_embedded_test.
ERROR (TEM-479): Unable to determine net associated with internal pin.

Internal pin:internalPinName
An internal pin was detected in the pattern control file, and the associated net could not be
found. Ensure the pin is properly connected and rerun create_embedded_test.
EXPLANATION:

The net associated with the internal pin name could not be found. This net is necessary
in order to create a cutpoint.
USER RESPONSE:
Ensure the pin is properly connected and rerun create_embedded_test.
ERROR (TEM-480): Syntax error found in the pattern control file.

Line number: line_number
Token number: token_number
Character: character
Correct the syntax error and rerun.
EXPLANATION:
Syntax error found while parsing the pattern control file.
USER RESPONSE:
Corrent the syntax error and rerun.
ERROR (TEM-481): Syntax error found in file.

Column number: col_number
EXPLANATION:
Syntax error found while parsing the file.
USER RESPONSE:
ERROR (TEM-482): Syntax error found in file.

Starting column number: start_col_number
Ending column number: end_col_number
EXPLANATION:


USER RESPONSE:
ERROR (TEM-483): Error parsing file. error_msg

EXPLANATION:
USER RESPONSE:
ERROR (TEM-484): No test conditions found in the file.

File: fileName
Specify the proper test conditions and rerun.
EXPLANATION:
No test conditions found in the file.
USER RESPONSE:
ERROR (TEM-485): The specified algorithm is already defined.

Algorithm: algorithmName
Ensure to use a unique name for each algorithm.
EXPLANATION:
The specified algorithm is already defined.
USER RESPONSE:
Make sure that either the name does not conflict with the names reserved for the pre-
defined algorithms or it is not defined multiple times. Ensure to use a unique name for
each algorithm.
ERROR (TEM-486): Improper test conditions found in the input file. Algorithm:
algorithmName. Specify the proper test conditions and rerun.

EXPLANATION:
Improper test conditions found in the input file.
USER RESPONSE:
ERROR (TEM-487): User specified algorithm limit is less than the required algorithm limit
for programmed algorithms. User specified algorithm limit:
user_specified_alg_limit
Required algorithm limit: req_alg_limit
Specify a larger algorithm limit in the algorithm constraints section of the configuration file and
rerun insertion mbist and then create_embedded_test.
EXPLANATION:
The algorithm limit specified in the algorithm constraints section is not large enough to
support the programmed algorithms being used.
USER RESPONSE:
Either specify a larger algorith limit in the algorithm constraints section of the
configuration file used for insertion and rerun, or change the programmed algorithms so
they meet the algorithm limit.
ERROR (TEM-488): The interface files specified were generated with the insert_dft
pmbist command. An advanced MBIST license is required for generating patterns. Ensure an
advanced MBIST license is available and rerun create_embedded_test.
EXPLANATION:
An advanced license is required for generating patterns when insert_dft pmbist has
been used to do the insertion.
USER RESPONSE:
Ensure an advanced MBIST license is available and rerun create_embedded_test.
ERROR (TEM-489): Register name used in pattern control file expression not found in the
IMAP Register Assignment section.
Register name: registerName
Ensure the register name is spelled correctly, and defined in the IMAP Register Assignment
section in the pattern control file.
EXPLANATION:

Register name used in pattern control file expression not found in the IMAP Register
Assignment section.
USER RESPONSE:
Ensure the register name is spelled correctly, and defined in the IMAP Register
Assignment section in the pattern control file.
ERROR (TEM-490): Register name used in pattern control file expression not found in the
IMAP Register Definition section.
Ensure the register name is spelled correctly, and defined in the IMAP Register Definition
EXPLANATION :
Register name used in pattern control file expression not found in the IMAP Register
Definition section.
USER RESPONSE:
Ensure the register name is spelled correctly, and defined in the IMAP Register Definition
ERROR (TEM-491): Value specified for IMAP register is not valid.

Value specified: valueSpecified
Valid values: validValues
Specify a valid value.
EXPLANATION:
Value specified for IMAP register is not valid.
USER RESPONSE:
Specify a valid value.
ERROR (TEM-492): Unable to locate any <usercore>_test_def.txt files. The mbist

test definition file is required input for the create_embedded_test command when
creating patterns for insert_dft pmbist. Use the Interfacefiledir and interfacefilelist
keywords to specify the mbist test definition file.
EXPLANATION:
The mbist test definition file is required for the create_embedded_test command
when creating patterns for insert_dft pmbist.

USER RESPONSE:
Specify a mbist test definition file. By default, mbist test definition files are searched for in the
<workdir>/testresults/testmode_data directory. This can be overridden by using
the interfacefiledir and interfacefilelist keywords.
ERROR (TEM-493): Duplicate entry found for data_order at line:

line_number. Remove the duplicate entry from the pattern control file and rerun.
EXPLANATION:
USER RESPONSE:
ERROR (TEM-494): Unable to determine the standard instruction name for user instruction
name found in the bsdl file. User instruction name: userInstructionName. Ensure the
instruction names in the bsdl and pattern control file are correct and rerun.
EXPLANATION:
While processing the bsdl file, a user specified instruction name was found. This
instruction name should be present in the pattern control file. From the pattern control
file, the standard instruction name is determined.
USER RESPONSE:
Ensure the instruction names specified in the bsdl file and the pattern control file are
correct.
ERROR (TEM-495): An execution step value must be specified for each testplan.
Amu: amuNum Siu: siuNum Dcu: dcuNum Target: targetNum
Pattern group: patternType
testplan_list value: testplanValue
clkstep_list value: clkstepValue
Update the pattern control file and specify an execution step for each testplan. Look for
the specified pattern group for the target mentioned.
EXPLANATION:
The pattern control file contains invalid testplan and execution step values for the entry.

USER RESPONSE:
If the pattern control file was generated by insert_dft pmbist, this error should be
reported to customer service. If the pattern control file has been modified, ensure an
execution step value is specified for each testplan.
ERROR (TEM-496): A testplan with read only algorithms was found. This indicates a
testplan used to target ROM devices. Testplan: testplan Missing information which is
required when generating patterns for ROM devices. Required information:
<design>_mbistrom_tdr_map.txt interface file.
The JTAG_INSTRUCTION_DECODE_MBISTROM pin in the tap_output
section of the pattern control file (for block level flows).
The MBISTROM instruction in the pattern control file.
The MBISTROM register in the pattern control file.
Supply the missing information and run the command again.

EXPLANATION:
Missing required information for testing ROM devices.
USER RESPONSE:
Supply the missing information or modify the testplan as to not have read only
algorithms.
ERROR (TEM-497): A testplan with read only algorithms was found. This indicates a
testplan used to target ROM devices. Testplan: testplan . Only RAM devices found being
targeted by this testplan. Modify the testplan to target ROMs or modify the algorithms in the
testplan to contain algorithms with both read and write operations.
EXPLANATION:
A testplan with read only algorithms found where only RAM devices are being targeted.
USER RESPONSE:
Modify the testplan to target ROMs or modify the algorithms in the testplan to contain
algorithms with both read and write operations.
ERROR (TEM-498): A testplan with read and write algorithms was found. This indicates a
testplan used to target RAM devices. Testplan: testplan Only ROM devices found being
targeted by this testplan. Modify the testplan to target RAMs or modify the algorithms in the
testplan to contain algorithms with only read operations.

EXPLANATION:
A testplan with read and write algorithms found where only ROM devices are being
targeted.
USER RESPONSE:
Modify the testplan to target RAMs or modify the algorithms in the testplan to contain
algorithms with only read operations.
ERROR (TEM-499): A hardwired testplan with read only algorithms was found. This
indicates a testplan used to target ROM devices. Missing ROM load file used during insertion:
romLoadFile Testplan: testplan This ROM load file must be in the location specified
by the interfacefiledir keyword. Make sure the ROM load file used during insertion is
located in the proper directory.
EXPLANATION:
A ROM only hardwired testplan was found, but the ROM load file was not found in the
interfacefiledir. This ROM load file is used along with ROM load file specified on
the command line to create_embedded_test to ensure that the files are the same.
USER RESPONSE:
Place a copy of the ROM load file used during insertion in the interfacefiledir
location.
INFO (TEM-500): Parsing the pattern_control file fullFileName

EXPLANATION:
The program has started parsing the referenced pattern_control file.
USER RESPONSE:
INFO (TEM-501): Data bit redundancy enabled for device. The locations where faults were
manually inserted match the bit locations determined by the simulation patterns for engine
engine target memory target.
EXPLANATION:
The simulation patterns identify bit locations where faults were manually injected. These
locations match the locations where faults were manually inserted.
USER RESPONSE:

INFO (TEM-502): Successfully analyzed failures. The nolog option has been specified,
therefore no log file is generated.
EXPLANATION:
Analysis of diagnostic patterns completed successfully. The nolog option was
specified, so no output log was generated.
RESPONSE:
INFO (TEM-503): No failing devices detected, repair analysis cannot be done.

EXPLANATION:
No failing devices detected, repair analysis cannot be done.
RESPONSE:
INFO (TEM-504): Beginning repair analysis.

EXPLANATION:
Starting to perform repair analysis.
RESPONSE:
INFO (TEM-505): Repair summary:

EXPLANATION:
The summary for repair analysis is displayed in a table.
RESPONSE:
INFO (TEM-506): Engine completion summary:

EXPLANATION:
A summary table for engine completion status is displayed.
USER RESPONSE:

INFO (TEM-507): Parsing the test definition file filename.

EXPLANATION:
The program has started parsing the referenced test definition file.
USER RESPONSE:
INFO (TEM-600): File fullFileName already exists, application will not overwrite.
EXPLANATION:
The referenced file exists from an earlier run. The file will not be overwritten. This file is
usually updated manually.
USER RESPONSE:
Verify that the manual file updates are current.
INFO (TEM-601): No input BSDL file was specified, using default.

EXPLANATION:
An input BSDL file was not found in the expected location. A default BSDL file will be
used instead.
USER RESPONSE:
Verify that an input BSDL file was not expected or desired.
INFO (TEM-602): The Insert Embedded Macro verification package has built with a return
code of returnCode.
EXPLANATION:
This information message indicates successful completion of the programs required
verification package generation.
USER RESPONSE:
Review the log file for WARNING or WARNING [Severe] level messages to verify that no
known rules or assumptions are violated.
INFO (TEM-603): Memory Target and Bist Engine Summary.

EXPLANATION:

The table describes each memory in the netlist, and the insertion status and associated
inserted MBIST engine.
USER RESPONSE:
Review the table to understand how each memory was handled and to ascertain if errors
occurred while attempting to insert MBIST.
INFO (TEM-604): Generated default mode init sequence. File name: filename.
EXPLANATION:
A default mode initialization sequence has been created for generating the MBIST
patterns.
USER RESPONSE:
The default sequence can be modified to include any required custom setup. Rerun
create_embedded_test and specify the custom mode initialization sequence as
input.
INFO (TEM-605): Using user specified mode init sequence.

File name: filename
EXPLANATION:
A user specified mode init sequence is being used instead of the default mode init
sequence. This is usually done to allow for special customizations of the initialization
sequence.
USER RESPONSE:
No response needed, the specified sequence is being used.
INFO (TEM-606): Created memory mapping file: file_name.

EXPLANATION:
A memory mapping file has been created for devices which have data bit redundancy.
USER RESPONSE:
INFO (TEM-607): Group summary table for experiment: experiment_name.

EXPLANATION:

The table provides a summary of the engines and target devices which are being
executed in the experiment.
USER RESPONSE:
INFO (TEM-608): Bitmap MBISTREAD TDR segment summary table. \n\
Total number of segments: numberOfSegments
Longest segment length: longestSegmentLength

EXPLANATION:
The table provides a summary of the bitmap MBISTREAD TDR segments created based
on the measure ports used for bitmap patterns
USER RESPONSE:
INFO (TEM-609): The length of all segments is equal to the length of MBISTREAD TDR. \n\
The length is: totalLength

EXPLANATION:
The length of all segments created by the measure ports is equivalent to the length of
the MBISTREAD TDR segments.
USER RESPONSE:
INFO (TEM-610): Created ROM load data file: filename. This ROM load data file should
be used for all subsequent processing, including simulation and verification.
EXPLANATION:
A ROM load data file has been created which contains the MISR seed signature in the
top addresses.
USER RESPONSE:
Use the new ROM load data file for all further processing.
INFO (TEM-611): Generated default mode init sequence for testmode used to create direct
access patterns. File name: filename

EXPLANATION:
A default mode init sequence has been created for generating the MBIST patterns
which use direct access.
USER RESPONSE:
The default sequence can be modified to include any custom setup that needs to be
done.
Re-run create_embedded_test and specify the custom mode init sequence as
input using the seqdefdirect keyword.
INFO (TEM-612): A new pattern control file has been created due to additional information
that has been added. This information includes the occurrence of the first Measure_PO
events for the respective pattern groups. That information is utilized by the
analyze_embedded_test command when processing simulation or CPP output. Pattern
control files are located in the <workdir>/testresults/testmode_data directory.
Original file saved as: origPatternControlFile. Updated file:
updPatternControlFile.
EXPLANATION:
A new pattern control file has been created due to additional information being added to
the file.
USER RESPONSE:
None needed.
INFO (TEM-613): Changing pattType scheduling number for amu amu siu siu dcu dcu
target target for test plan testplan. See previous constraint violation message for an
explanation of why this happened. New pattType scheduling number is step.
EXPLANATION :
Production pattern scheduling must conform to the following constraints:
Devices targeted by different clocks can not be grouped together.
Dcus can only execute one target at a time.
Request latency must be the same for all targets on an siu.
Violations of any of these constraints forces the specific devices to be placed in a
different scheduling group. A new pattern control file is written out which contains the
updated schedule.

By default, the pattern control file is located in the <workdir>/testresults/testmode_data

directory.
USER RESPONSE:
None needed.

for step stepID in testplan testplan. The entry amu amu1 siu siu1 dcu dcu1 target
tar1 is a deviceType device. The testplan contains algorithms with operations
operations. This entry will be disabled for the testplan.
EXPLANATION:
located in the <workdir>/testresults/testmode_data directory. RAM devices
can not be scheduled for testplans that contain algorithms with only read operations, and
ROM devices can not be scheduled for testlpans that contain read and write operations.
USER RESPONSE:
The target will be disabled for the testplan.

for step stepID in testplan testplan. Fail delay must be the same for all targets. amu
amu1 siu siu1 dcu dcu1 target tar1 has a value of val1 and amu amu2 siu siu2 dcu
dcu2 target tar2 has a value of val2. These must be scheduled in different groups.
EXPLANATION:
located in the <workdir>/testresults/testmode_data directory. Fail delay must be the
same for all targets.
USER RESPONSE:
Schedule the targets in different groups.

for step stepID in testplan testplan. Different size ROMs on can not be scheduled
together. amu amu1 siu siu1 dcu dcu1 target tar1 has a value of val1 and amu amu2
siu siu2 dcu dcu2 target tar2 has a value of val2. These must be scheduled in different
groups.
EXPLANATION:

located in the <workdir>/testresults/testmode_data directory. Different size
ROMs can not be scheduled together.
USER RESPONSE:

for step stepID in testplan testplan. Different diagnostic types can not be scheduled
together. amu amu1 siu siu1 dcu dcu1 target tar1 has a value of val1 and amu amu2
siu siu2 dcu dcu2 target tar2 has a value of val2. These must be scheduled in different
groups.
EXPLANATION:
located in the <workdir>/testresults/testmode_data directory. Different
diagnostic types can not be scheduled together.
USER RESPONSE:

for step stepID in testplan testplan. Read delay must be the same for all targets. amu
amu1 siu siu1 dcu dcu1 target tar1 has a value of val1 and amu amu2 siu siu2 dcu
dcu2 target tar2 has a value of val2. These must be scheduled in different groups.
EXPLANATION:
located in the <workdir>/testresults/testmode_data directory. Read delay
must be the same for all targets.
USER RESPONSE:
ERROR (TEM-650): Memory Allocation failed. Unable to allocate enough memory for the
application to continue. Verify enough memory is available and rerun.
EXPLANATION:
Dynamic memory allocation has failed and the application cannot continue processing.
USER RESPONSE:
Check the system for memory issues prior to attempting execution again.

ERROR (TEM-651): Unable to open file filename. The file could not be found. Verify the
file name and permissions are correct.
EXPLANATION:
The program could not open the referenced file.
USER RESPONSE:
Ensure the file name and location are correct and rerun.
ERROR (TEM-652): Invalid OPCODE for BSDL instruction instruction_name on TDR

tdrname. A zero length OPCODE was found for the instruction. Verify the BSDL file has the
correct OPCODE for the instruction.
EXPLANATION:
The application detected an invalid OPCODE when building the test patterns.
USER RESPONSE:
Verify BSDL file has the correct OPCODE value in the IEEE 1149.1 TAP controller
INSTRUCTION_OPCODE attribute.
ERROR (TEM-653): No more IEEE 1149.1 TAP controller instruction decodes available for
OPCODEs. Expand the IEEE 1149.1 TAP controller INSTRUCTION_LENGTH attribute in the
BSDL file and rerun.
EXPLANATION:
An OPCODE of the IEEE 1149.1 TAP controller was requested and denied due to the
unavailability of additional decodes.
USER RESPONSE:
Check the input BSDL file and expand the IEEE 1149.1 TAP controller
INSTRUCTION_LENGTH attribute, and rerun.
ERROR (TEM-654): Clock Pin clkPinName not found in the BSDL. The clock was
specified in the configuration file, but could not be found in the BSDL. Correct the clock pin
name and rerun.
EXPLANATION:
The program compares clock pins specified in the configuration file against the names
found in the BSDL.
USER RESPONSE:

Verify the pin name is correctly specified in the configuration file, and/or the proper BSDL
file is being used.
ERROR (TEM-655): A hardwired testplan with read only algorithms was found. This
indicates a testplan used to target ROM devices. The ROM load file used during insertion
does not match the ROM load file specified on the command line. The ROM load file used
during insertion: insertionRomLoadFile. The ROM load file specified on the command
line: cmdLineRomLoadFile. Testplan: testplan. These ROM load files must match for
hardwired testplans. Make sure the correct ROM load files have been specified.
EXPLANATION:
The ROM load file used during insertion must be the same as that specified on the
command line for a hardwired testplan.
USER RESPONSE:
Make sure the correct ROM load files have been specified.
ERROR (TEM-656): ROM signatures for hardwired testplan do not match. Testplan:
testplan Step: step. Algorithm: algorithm. Hardwired signature vector connections
: srublock[upperIndex:lowerIndex ]. ROM signature (calculated during insertion)
insertionSignature. ROM signature (calculated using ROM load files from the
command line): newSignature If the ROM load files have changed since insertion has
been done, then changes must be made to the hardware to support the new signature. If the
ROM load files have not changed, ensure the proper ROM load files have been specified on
the command line.
EXPLANATION:
ROM signatures do not match.
USER RESPONSE:
If the ROM load files have changed since insertion has been done, then changes must
be made to the hardware to support the new signature. If the ROM load files have not
changed, ensure the proper ROM load files have been specified on the command line.
ERROR (TEM-658): Direct access pin not found in compliance enable section of the bsdl.
Pin name: pinName
Pin is required in order to initialize the direct access logic properly.
EXPLANATION:
When direct access logic has been inserted and JTAG patterns are requested, certain
pins are required to be present in the compliance enable section of the bsdl in order to
properly intialize the direct access logic.

USER RESPONSE:
Provide bsdl with the missing pin.
ERROR (TEM-659): The MDA reset pin must be defined as active low when also being used
as the JTAG reset pin. Pin name: pinName
By definition, the JTAG reset pin must be active low.
EXPLANATION:
If the same pin is used for JTAG reset and MDA reset, the MDA reset must be defined as
active low.
USER RESPONSE:
Either do not share the same pin for jtag reset and mda reset, or define the mda reset
pin as active low.
ERROR (TEM-662): Direct access pin set to wrong value in compliance enable section of
the bsdl. When executing JTAG patterns in the presence of direct access logic, the direct
access pins must be set to appropriate values in order to disable it. mda_reset must be set
active, and mda_tdi must be set inactive. The active values of the direct access pins are
defined during insertion by the define_dft pmbist_direct_access command.
Pin name: pinName
Pin polarity: pinPolarityDefined (as defined by define_dft
pmbist_direct_access)
Pin polarity: pinPolarityBsdl (in the bsdl)
EXPLANATION:
When direct access logic has been inserted and JTAG patterns are requested, certain
pins are required to be present in the compliance enable section of the bsdl and at
particular values in order to properly intialize the direct access logic.
USER RESPONSE:
Ensure the direct access pin has been defined properly and the bsdl is correct.

for step stepID in testplan testplan. The same step number can not be used in different
testplans for the same AMU. amu amu1 siu siu1 dcu dcu1 target tar1 must be scheduled
in a different group.
EXPLANATION:
targets can not be executed together in different testplans on the same AMU.

USER RESPONSE:

for step stepID in testplan testplan. Redundancy analysis and self repair patterns are
not supported at the logical wrapper level of a multiple view memory. amu amu1 siu siu1
dcu dcu1 target tar1 will be turned off.
EXPLANATION:
targets can not be executed together in different testplans on the same AMU.
USER RESPONSE:
ERROR (TEM-665): A programmed testplan contains a test condition value not supported
by the algorithm constraints section in the test definition file.
Amu: amu
Testplan: testplan
Test condition type: testConditionType
Unsupported test condition value: testConditionValue
Specify a supported test condition and re-run create_embedded_test. If additional test
condition values are required, add them to the testplan definitions in the config file, re-run
insert_dft pmbist and then create_embedded_test.
EXPLANATION:
The test condition value in one or more of the programmed testplans is not supported by
the algorithm constraints section.
USER RESPONSE:
Either choose a valid test condition type in the test definition file and re-run
create_embedded_test, or if additional test condition values are required, add them
to the testplan definitions in the config file, re-run insert_dft pmbist and then
ERROR (TEM-666): Unable to successfully load hierModel file. additional

information about what caused the error
EXPLANATION:

A model access routine was unable to load the model file shown in the message.
Additional information about the error may be provided. This is mainly for use by
Customer Support.
USER RESPONSE:
Check that the file exists.
Check file permissions and ensure the machine being used has enough memory.
If file exists and machine has enough memory:
If the hierModel is missing or tables couldn't be loaded from the file, re-build
the model using build_model. Otherwise, contact Cadence Customer
Support for additional help (see Contacting Customer Service on page 23).
INFO (TEM-700): Parsing the pattern file filename.

EXPLANATION:
The program is parsing the referenced pattern file. The file is analyzed to look for the
MBISTFailDataSync Keyed_Data.
USER RESPONSE:

INFO (TEM-701): Chip name chipname being processed. [end TEM_701] \n
EXPLANATION:
The specified chip name is being processed.
USER RESPONSE:
INFO (TEM-702): Single instruction set found for chip.

EXPLANATION:
A single instruction set was found for the chip name being processed.
USER RESPONSE:

ERROR (TEM-703): Cannot create the diagnostics Test Data Register map file
fullFileName. Fix the file permissions and/or the available disk space and rerun.
EXPLANATION:
A diagnostic TDR file is created to document the interaction between a BIST engine and
the memory element(s). In addition, the file also expresses how the BIST engines are
chained together to form an overall mbistdiag TDR. The program terminated as it was
unable to create the referenced file either due to the file permissions or the lack of
available disk space.
USER RESPONSE:
Check for appropriate permissions and disk quota, then rerun the program.
INFO (TEM-704): Pattern file found for chip chip. Pattern file name: filename
EXPLANATION:
The pattern file has been located for the chip.
USER RESPONSE:
INFO (TEM-705): Keyed_Data section analyzed and verified in pattern file for chip chip.
Pattern file name: patternfile
Analysis type: analysis_type
Clock type: clock_type
Step: step
Testblockname: testblockname
Pattern control file: patterncontrolfile
Algorithm list: algorithm_list
Clock step vector: clock_step_vector

EXPLANATION:
The Keyed_Data section of the pattern file has been verified.
USER RESPONSE:

INFO (TEM-706): Pin correlation file found. File name: filename

EXPLANATION:
The pin correlation file has been located.
USER RESPONSE:
INFO (TEM-707): Created <testblockname>.FBI file. File name: filename

EXPLANATION:
The <testblockname>.FBI file has been created.
USER RESPONSE:
INFO (TEM-708): Created FDD_name.idx file. File name: filename

EXPLANATION:
The FDD_name.idx file has been created.
USER RESPONSE:
INFO (TEM-709): Created FABIAN.idx file. File name: filename

EXPLANATION:
The FABIAN.idx file has been created.
USER RESPONSE:
INFO (TEM-710): Created CPP (chip pad pattern) file for testblock: testblockname
CPP file: cppfile
EXPLANATION:
The CPP file for the testblock mentioned, has been created.
USER RESPONSE:

INFO (TEM-711): Processing FDS log file. File: fdslogfile

EXPLANATION:
The FDS log file is being processed.
USER RESPONSE:
WARNING (TEM-741): Chip name from failure data log does not match chip name from root
directory. Chip name (failure data log): chipname_failure_data_logChip name
(root directory): chipname_rootdir
EXPLANATION:
The chip name from the failure data log does not match the chip name from the root
directory.
USER RESPONSE:
Make sure the failure data log corresponds to the root directory being analyzed.
WARNING (TEM-742): FDS log file specified in faildatalogfile does not exist. File:
faildatalog
EXPLANATION:
The FDS log file found in the file specified by the faildatalogfile keyword does not
exist. This file will not be analyzed.
USER RESPONSE:
Make sure the file name is spelled correctly, and exists at the specified location.
WARNING (TEM-743): Could not locate a valid pattern file for testblockname
testblockname. Failure data log file being analyzed: failuredatalogfile.
EXPLANATION:
Could not locate a valid pattern file for the specified testblockname. The
testblockname was found in the failure data log mentioned.
USER RESPONSE:
Ensure the failure data log is correct, and the patterns are located in the proper directory.
WARNING (TEM-744): A pattern offset value of patternoffset cycles has been

specified on the command line. The pattern offset will be applied to all pattern files processed.

Ensure that this value is correct, and the failure data being analyzed corresponds to the
pattern files.
EXPLANATION:
A pattern offset value has been specified and will be used as a starting cycle count for
all patten files processed.
USER RESPONSE:
Ensure the patten offset value is correct, and the patterns correspond to the failure data
being analyzed.
ERROR (TEM-751): Error while executing command. Command: command Log: log
EXPLANATION:
The prepare_memory_failset command failed while executing the command
mentioned.
USER RESPONSE:
Ensure all input files have been specified properly.

ERROR (TEM-752): Keyed_Data could not be found while analyzing the pattern file. Pattern
file: patternFile.
EXPLANATION:
Could not find the Keyed_Data information in the pattern file specified. This information
is required to correlate the patterns, failing data and interface files to properly perform
analysis.
USER RESPONSE:
Ensure all the patterns were written out using write_vectors and the
keyeddata=yes option.
ERROR (TEM-752): Keyed_Data could not be found while analyzing the pattern file.
Pattern file:patternFile.
EXPLANATION:

Could not find the Keyed_Data information in the pattern file specified. This information
is required to correlate the patterns, failing data and interface files to properly perform
analysis.
USER RESPONSE:
Ensure all the patterns were written out using write_vectors and the
keyeddata=yes option.
ERROR (TEM-753): CDNS_info directory not found under root directory. Root directory:
rootdirectory.
EXPLANATION:
Could not find the CDNS_info directory under the root directory. This directory is
required, and must contain one or more sub-directories for each of the instruction sets
for the product being analyzed.
USER RESPONSE:
Ensure the proper root directory was specified with the rootdirectory keyword.
ERROR (TEM-754): No valid chip directories found under the CDNS_info directory.
Directory being analyzed: directory.
EXPLANATION:
One or more sub-directories under the CDNS_info directory must exist for each
instruction set being analyzed.
USER RESPONSE:
Ensure the proper root directory was specified with the rootdirectory keyword.
ERROR (TEM-755): No valid patterns found in directory: directory

EXPLANATION:
Valid patterns must be located in the directory mentioned.
USER RESPONSE:
Ensure the patterns are located in the directory mentioned.
ERROR (TEM-756): The testblockname from the pattern file name does not match the
value in the Keyed_Data.
Pattern file: patternfile
Value from the pattern file name: testblockname_pattern

Value from the Keyed_Data: testblockname_keyeddata

EXPLANATION:
The testblockname derived from the pattern file name does not match the
testblockname value extracted from the Keyed_Data section in the pattern file.
USER RESPONSE:
Ensure the pattern file name and the Keyed_Data sections are correct.
ERROR (TEM-757): The pattern control file name based on the pattern file location, does
not match the value in the Keyed_Data.
Pattern file: patternfile
Value from the pattern file location: patterncontrolfile_pattern
Value from the Keyed_Data: patterncontrolfile_keyeddata

EXPLANATION:
The pattern control file name based on the pattern file location does not match the value
extracted from the Keyed_Data section in the pattern file.
USER RESPONSE:
Ensure the pattern file name and the Keyed_Data sections are correct.
ERROR (TEM-758): Could not locate required interface file.

Directory searched: directory
Required interface file name: interface_file_name
EXPLANATION:
Could not locate a required interface file name. This file is required to perform analysis
on the failing data.
USER RESPONSE:
Ensure all of the required interface files are present in the mentioned directory.
ERROR (TEM-759): Could not locate the pin correlation file in the root directory.
Root directory: rootdirectory
Pin correlation file name: pincorrelationfile

EXPLANATION:
Could not locate the pin correlation file. This file is required to perform analysis on the
failing data.
USER RESPONSE:
Ensure the pin correlation file is present in the root directory.
ERROR (TEM-760): Could not locate a valid pattern file for testblockname
testblockname. Failure data log file being analyzed: failuredatalogfile
EXPLANATION:
Could not locate a valid pattern file for the specified testblockname. The
testblockname was found in the failure data log mentioned.
USER RESPONSE:
Ensure the failure data log is correct, and the patterns are located in the proper directory.
ERROR (TEM-761): Found more than one pattern file for testblockname
testblockname.
Failure data log file being analyzed: failuredatalogfile
Pattern files found: patternfiles
EXPLANATION:
More than one pattern file found for the specified testblockname. The testblockname
was found in the failure data log mentioned. Only one pattern file for the testblockname
is supported.
USER RESPONSE:
Ensure the failure data log is correct, and the patterns are named properly.
ERROR (TEM-762): No valid FDS logs specified. If the faildatalogfile keyword was
used to specify a file containing locations of FDS logs, make sure the locations and file names
are correct.
EXPLANATION:
Could not locate any valid FDS logs.
USER RESPONSE:
Ensure valid FDS logs are specified on the command line with the faildataloglist
keyword, or the faildatalogfile keyword.

ERROR (TEM-763): Missing data from the failure data log file containing the chip
information. The chip name is: chipname Data lines containing the chip information contain
the character string CI followed by the chip information. This information includes the wafer
number, the wafer x and y coordinates along with a serial number. An example of this data
line is: FDS-DATA00000018CI23022030serialno, where the wafer number is 23, the wafer x
coordinate is 022, the wafer y coordinate is 030 and the serial number is serialno.
EXPLANATION:
Missing the data lines in the failure data log that indicate the chip information. This data
is used to extract the wafer number, the wafer x coordinate, the wafer y coordinate and
the serial number. These data lines contain the character string CI.
USER RESPONSE:
Ensure the failure data log contains the correct data lines and rerun the command.

ERROR (TEM-801): [Internal] Length of the target memory list is not equal to the defined
value. Contact Cadence Customer Support for assistance.
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-802): [Internal] Illegal target memory configuration configNum. Contact

Cadence Customer Support for assistance.
EXPLANATION:

USER RESPONSE:
customer support.
ERROR (TEM-803): [Internal] Length of the ignore memory list is not equal to the defined
value. Contact Cadence Customer Support for assistance.
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-804): [Internal] Illegal ignore memory configuration configNum. Contact

EXPLANATION:
USER RESPONSE:

Contact thecustomer support team using your normal process; SourceLink, email, or
customer support.
ERROR (TEM-805): [Internal] Internal target lengths are not equal. The different length
values are firstLen and secondLen. Contact Cadence Customer Support for
assistance.
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-806): [Internal] Error in computing the memory maximum address. The
computed address value powAddr is less than the expected value maxAddr. Contact
EXPLANATION:
USER RESPONSE:

customer support.
ERROR (TEM-808): [Internal] Memory cell BIST status is not initialized. Contact Cadence
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-809): [Internal] Failed to find an internal memory element of memory cell
ramCellName. Contact Cadence Customer Support for assistance.
EXPLANATION:
USER RESPONSE:
customer support.

ERROR (TEM-810): [Internal] Cannot determine the memory type of the memory cell
ramCellName. Contact Cadence Customer Support for assistance.
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-812): [Internal] Cannot extract the number of different types of ports on the
memory cell ramCellName. Contact Cadence Customer Support for assistance.
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-813): [Internal] Cannot find the memory instance name in all instances of
the multiply used module. Contact Cadence Customer Support for assistance.
EXPLANATION:

USER RESPONSE:
customer support.
ERROR (TEM-814): [Internal] Cannot create vector nets to propagate buses. Contact
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-815): [Internal] Cannot create vector ports to propagate buses. Contact
EXPLANATION:
USER RESPONSE:

customer support.
ERROR (TEM-816): [Internal] Cannot find the pin/port pin/portName. Contact

EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-817): [Internal] Instance instName busName busName does not contain
bus busName. Contact Cadence Customer Support for assistance.
EXPLANATION:
USER RESPONSE:

customer support.
ERROR (TEM-818): [Internal] Port portName does not exist on module moduleName.
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-819): [Internal] Net netName does not exist in module moduleName.
EXPLANATION:
USER RESPONSE:
customer support.

ERROR (TEM-822): [Internal] Cannot locate memory memInstName in module

moduleName. Contact Cadence Customer Support for assistance.
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-823): [Internal] Cannot find pin pinName on the memory instance
ramInstName in module moduleName. Contact Cadence Customer Support for
assistance.
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-824): [Internal] Cannot find Instance instName in module moduleName.

EXPLANATION:

USER RESPONSE:
customer support.
ERROR (TEM-825): [Internal] Pin pinName is not found on instance instName in

module moduleName. Contact Cadence Customer Support for assistance.
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-828): [Internal] The length of instance internal representation is below the
default value. Contact Cadence Customer Support for assistance.
EXPLANATION:
USER RESPONSE:

customer support.
ERROR (TEM-829): [Internal] No common parent module found to compute the hierarchy.
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-830): [Internal] The number of read ports greater than the expected value.
EXPLANATION:
USER RESPONSE:

customer support.
ERROR (TEM-831): [Internal] Comparators expected data bus busName is not found in
the module moduleName. Contact Cadence Customer Support for assistance.
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-833): [Internal] Internal entity number error. Contact Cadence Customer
Support for assistance.
EXPLANATION:
USER RESPONSE:
customer support.

ERROR (TEM-834): [Internal] Bus net busName is not connected to BIST engine
bistEngInstName. Contact Cadence Customer Support for assistance.
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-835): [Internal] Memory bus is already connected to BIST engine using net
netName. Contact Cadence Customer Support for assistance.
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-836): [Internal] No net is connected to pin pinName of BIST engine

bistEngineName. Contact Cadence Customer Support for assistance.
EXPLANATION:

USER RESPONSE:
customer support.
ERROR (TEM-837): [Internal] Memory Write Data port is already connected to net
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-839): [Internal] Clock port associated with a read bus is different than
expected. Contact Cadence Customer Support for assistance.
EXPLANATION:
USER RESPONSE:

customer support.
ERROR (TEM-841): [Internal] Comparator data port is already connected to the net
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-843): [Internal] Comparators output port is already connected to the net
EXPLANATION:
USER RESPONSE:

customer support.
ERROR (TEM-844): [Internal] Pin is already connected to the net netName. Error code
errCodeNum. Contact Cadence Customer Support for assistance.
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-845): [Internal] Chip select/enable port is already connected to net

EXPLANATION:
USER RESPONSE:
customer support.

ERROR (TEM-846): [Internal] Cannot find the chip select/enable pin associated with the
memorys read-write port. Contact Cadence Customer Support for assistance.
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-847): [Internal] Cannot find the write enable mask pin on the memory cell
memCellName. Contact Cadence Customer Support for assistance.
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-848): [Internal] Write enable pin is already connected to net netName.
EXPLANATION:

USER RESPONSE:
customer support.
ERROR (TEM-849): [Internal] Vector write enable is already connected to net netName.
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-850): [Internal] Read Enable data is already connected to net netName.
EXPLANATION:
USER RESPONSE:

customer support.

ERROR (TEM-851): [Internal] The clock pin is already connected to net netName.
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-852): [Internal] Mux select pin is already connected to net netName.
EXPLANATION:
USER RESPONSE:

customer support.
ERROR (TEM-853): [Internal] Output enable pin is not found on memory cell
memCellName. Contact Cadence Customer Support for assistance.
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-854): [Internal] Cannot find embedded macro module moduleName.

EXPLANATION:
USER RESPONSE:
customer support.

ERROR (TEM-855): [Internal] Cannot find expected instance instanceName in module

moduleName. Contact Cadence Customer Support for assistance.
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-856): [Internal] The number of comparators numOfCmps is not equal to the
expected value expectedCmps. Contact Cadence Customer Support for assistance.
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-857): [Internal] Memory is in a higher hierarchical block memInstLoc in

the netlist than its associated BIST engine bistEngineLoc. Contact Cadence Customer
EXPLANATION:

USER RESPONSE:
customer support.
ERROR (TEM-859): [Internal] Unexpected BIST engine instance location. Contact

EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-860): [Internal] Cannot stitch the clock pin from the target memory cell to
the associated BIST engine. Contact Cadence Customer Support for assistance.
EXPLANATION:
USER RESPONSE:

customer support.
ERROR (TEM-862): [Internal] Cannot match the internal string for the logic test memory
bypass. Contact Cadence Customer Support for assistance.
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-863): [Internal] Error occurred while creating the logic test memory bypass
for memory cell ramName. Contact Cadence Customer Support for assistance.
EXPLANATION:
USER RESPONSE:

customer support.
ERROR (TEM-866): [Internal] Cannot find the collar mux input functional net for stitching.
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-867): [Internal] Cannot stitch JTAG pins to the BIST engine due to the
internal length mismatch. Contact Cadence Customer Support for assistance.
EXPLANATION:
USER RESPONSE:
customer support.

ERROR (TEM-868): [Internal] Cannot connect pins sourcePinName and

sinkPinName. Contact Cadence Customer Support for assistance.
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-869): [Internal] Cannot determine the number of read ports from the
internal format. Contact Cadence Customer Support for assistance.
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-871): [Internal] Internal failure while organizing a read bus. Contact
EXPLANATION:

USER RESPONSE:
customer support.
ERROR (TEM-873): [Internal] No diagnostics support for slice and index in the TDR file.
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-874): [Internal] Cannot find the memory instance ramInstName in the
module moduleName. Contact Cadence Customer Support for assistance.
EXPLANATION:
USER RESPONSE:

customer support.
ERROR (TEM-875): [Internal] Cannot find the net netName. Contact Cadence Customer
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-876): [Internal] Cannot file Instance instName in module moduleName.

EXPLANATION:
USER RESPONSE:

customer support.
ERROR (TEM-879): [Internal] Unable to initialize the target BIST package. Contact
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-880): [Internal] Unsupported memory type memCellName. Error Code

errorCodeNum. Contact Cadence Customer Support for assistance.
EXPLANATION:
USER RESPONSE:
customer support.

ERROR (TEM-881): [Internal] Cannot determine the memory BIST TDR contents. Contact
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-882): [Internal] Cannot find the programs tcl library file fileName in the
installed search path searchPath. Contact Cadence Customer Support for assistance.
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-883): [Internal] Cannot find the programs tcl library path. Contact Cadence
EXPLANATION:

USER RESPONSE:
customer support.
ERROR (TEM-884): [Internal] Cannot open the temporarily created file fileName for the
programs internal processing. Contact Cadence Customer Support for assistance.
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-885): [Internal] Cannot find the embedded macro file fileName in the
installed search path searchPath. Contact Cadence Customer Support for assistance.
EXPLANATION:
USER RESPONSE:

customer support.
ERROR (TEM-886): [Internal] Cannot find internal details of module moduleName.

EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-887): [Internal] Internal error. Cannot find output bus busName. Contact
EXPLANATION:
USER RESPONSE:

customer support.
ERROR (TEM-889): [Internal] Internal error. Cannot find input bus busName. Contact
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-890): [Internal] Cannot determine the work directory. Contact Cadence
EXPLANATION:
USER RESPONSE:
customer support.

ERROR (TEM-891): [Internal] Internal error. Cannot determine the current directory.
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-892): [Internal] Array boundary exceeded. Internal size currentVal

reference size referenceVal. Contact Cadence Customer Support for assistance.
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-893): [Internal] Internal error. Cannot find input scalar pin pinName.
EXPLANATION:

USER RESPONSE:
customer support.
ERROR (TEM-894): [Internal] The number of address buses numAddrBuses is not

equal to the number of ports numPorts on memory cell memCellName. Contact Cadence
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-895): [Internal] Comparators enfail port is already connected to the net
EXPLANATION:
USER RESPONSE:

customer support.
ERROR (TEM-896): [Internal] Cannot determine the corresponding TIE pin. Contact
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-897): [Internal] The number of instances numInstances is not equal to

the expected value expectedVal. Contact Cadence Customer Support for assistance.
EXPLANATION:
USER RESPONSE:

customer support.
ERROR (TEM-898): [Internal] Module/Entity entityName is already loaded in the

design. Contact Cadence Customer Support for assistance.
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-899): [Internal] Cannot find net corresponding to JTAG pin pinName.
EXPLANATION:
USER RESPONSE:
customer support.

WARNING (TEM-900): Memory BIST insertion supports read or write data bus. The
direction or functionality of data bus busName of memory cell memoryCell is not
compatible. Cannot BIST instances of memory cell memoryCell.
EXPLANATION:
The program supports a data bus to be either read or write and not both read and write.
The direction of the data bus is expected to be input or output and not inout/bidirectional.
USER RESPONSE:
Check the liberty file to ensure that referenced bus is either input or output. Also verify
functionality/purpose of bus and rerun.

WARNING (TEM-902): Cannot determine the associated test wrapped address bus for
system write bus wrBusName of memory cell memCellName. No instances of this memory
cell have BIST inserted. Ensure the test wrapped address bus exists and is related to the
same clock, in the .lib file, as the system address bus and rerun.
EXPLANATION:
The program attempts to associate pins on a memory cell to a particular port, using the
related clock attribute specified in the liberty (.lib) file for each pin on a memory cell.
The program expects each port to have a unique clock pin. In addition to the mentioned
attribute, for each port of a test wrapped memory the test wrapped address bus is
distinguished from the system address bus using the naming convention specified in the
reference manual.
USER RESPONSE:
To insert BIST in the referenced memory cell, ensure the test wrapped address bus
corresponding to the system address bus is related to the same clock, and follows the
test wrapped naming convention. Refer to Inserting Memory Built-In-Self-Test Logic in
Design For Test in Encounter RTL Compiler.
WARNING (TEM-905): The number of the individual clock pins numClkPins is not equal
to the number of ports numPorts of the memory cell memCellName. No instances of this
memory cell have BIST inserted. Verify each port on the memory cell has a unique clock pin
and rerun.
EXPLANATION:

relate control pins/buses to their corresponding ports using the related clock attribute in
the liberty (.lib) file.
USER RESPONSE:
To insert BIST in the referenced memory cell, verify each port of the referenced memory
cell has a separate clock pin associated with it and rerun.
WARNING (TEM-906): Cannot find an address bus associated with the clock pin
clkPinName for the memory cell memCellName. No instances of this memory cell have
BIST inserted. Ensure each port has a unique clock pin and an associated address bus and
rerun.
EXPLANATION:
Each memory cell port is required to have an address bus related to a clock feeding the
port. The program supports memory cells that have an individual clock pin and an
associated address bus per port to read data from or write data to a memory location.
USER RESPONSE:
To insert BIST in the referenced memory cell, verify the address bus is associated with
a referenced clock pin and rerun.
WARNING (TEM-907): Cannot find a write data bus associated with the clock pin
clkPinName of memory cell memCellName. Ensure each write port has a unique clock
and a related write data bus.
EXPLANATION:
Each write port of a memory cell is required to have a write data bus associated with a
clock feeding the port. The program supports memory cells that have a unique clock and
an individual write data bus related to each write or read-write to perform the write
operation.
USER RESPONSE:
Verify the write data bus is associated with a referenced clock pin and rerun
WARNING (TEM-908): Cannot find a read bus associated with clock pin clkPinName of
memory cell memCellName. No instances of this memory cell have BIST inserted. Ensure
each read or read-write port has a unique clock and a related read data bus and rerun.
EXPLANATION:
Each read port of a memory cell is required to have a read data bus associated with a
clock feeding the port. The program supports memory cells that have a unique clock and

an individual read data bus related to each read or read-write to perform the read
operation.
USER RESPONSE:
To insert BIST into the referenced memory cell, verify the read data bus is associated
with a referenced clock pin.
WARNING (TEM-909): Cannot find a chip select/enable pin associated with clock pin
clkPinName of the memory cell memCellName. No instances of this memory cell have
BIST inserted. Ensure the chip enable pin exists for the port and is related to the referenced
clock and rerun.
EXPLANATION:
Each port on a read-write memory is required to have a chip select or a chip enable pin
associated with a clock feeding the port. In a read-write memory configuration, each
memory port should have an individual clock per memory port and a separate chip
enable pin to turn on or turn off the port.
USER RESPONSE:
To insert BIST in the referenced memory cell, verify the chip select or chip enable pin is
associated with a referenced clock pin and rerun.
WARNING (TEM-910): Cannot find a write enable pin associated with clock pin
clkPinName for memory cell memCellName. No instances of this memory cell have BIST
inserted. Ensure the write enable pin exists for each write or read-write port and is related to
the referenced clock and rerun.
EXPLANATION:
Each read-write or write port on a memory cell is required to have a write enable pin
associated with a clock feeding the port. A memory port should have an individual clock
and a separate write enable pin per read-write/write port to turn on or turn off the data
write through the port.
USER RESPONSE:
To insert BIST in the referenced memory cell, verify the write enable pin is associated
with a referenced clock pin and rerun.
WARNING (TEM-912): Cannot find a read enable pin associated with the clock pin
clkPinName for the memory cell memCellName. No instances of this memory cell have
BIST inserted. Ensure the read enable pin exists for each read port and is related to the
referenced clock and rerun.
EXPLANATION:

Each read port on a memory cell is required to have a read enable pin associated with a
clock feeding the port. A memory port should have an individual clock and a separate
read enable pin per read port to turn on or turn off the data read from a port.
USER RESPONSE:
To insert BIST in the referenced memory cell, verify the read enable pin is associated
with a referenced clock pin and rerun.
WARNING (TEM-914): Cannot determine the associated clock and address pin related to
read bus readBusName of memory cell memCellName. No instances of this memory cell
have BIST inserted. Verify both the address and read bus for the port use the same related
clock attribute and rerun.
EXPLANATION:
The program attempts to relate each pin to a particular port using the related clock
attribute listed in the .lib file. The program assumes that each port of the cell is clocked
by a unique pin on the memory cell. To relate the address bus and read data bus to the
same clock, the related clock attribute in the .lib file should be same for both buses.
USER RESPONSE:
To insert BIST in the referenced memory cell, ensure the address bus corresponding to
the specified read port uses the same related clock and rerun.
WARNING (TEM-915): The number of address port(s), numPorts, is not equal to the
number of clock pins, numClks, on memory cell memCellName. No instances of this
memory cell have BIST inserted. Ensure the number of address ports and clock pins match
and rerun.
EXPLANATION:
The program verifies there is an address bus and a unique clock pin for each port of a
memory cell. Control pins on a memory cell are associated to each port based on the
related clock attribute defined in the .lib file.
USER RESPONSE:
To insert t BIST in the referenced memory cell, ensure there is a unique address bus and
distinct clock pin specified for each memory port and rerun.
WARNING (TEM-916): Cannot BIST any instance of targeted memory cell memCellName.
Refer to the previous message(s) and resolve the conflicts for the referenced memory cell and
rerun.
EXPLANATION:

The program is unable to completely exploit the details of the referenced memory cell
and ignores the BIST insertion in all instances of the memory cell. This message only
prints for memory cells that were targeted for BIST insertion.
USER RESPONSE:
To insert BIST into referenced memory cell, resolve the conflicts mentioned previously in
the log file and rerun.
ERROR (TEM-917): Instance instanceName in the hierarchical name hierName is

either a blackbox or a technology cell instance in module moduleName. Ensure the
hierarchical name, specified in the configuration file, is not contained in any blackboxes or
technology cells and rerun.
EXPLANATION:
The hierarchically referenced name contains either a blackbox or a technology cell
instance name. This location, specified in the configuration file, cannot be verified,
causing the program to terminate.
USER RESPONSE:
Ensure the specified net, pin, or instance is not contained in a blackbox or technology
cell and rerun.
ERROR (TEM-918): Object instanceName|netName|pinName in the hierarchical

name hierName is not found in module moduleName. Correct the referenced name in the
configuration file and rerun.
EXPLANATION:
The referenced object in the hierarchical name cannot be located in the netlist. The
program is unable to verify the existence of the specified location, causing the program
to terminate.
USER RESPONSE:
Specify a correct hierarchical name in the configuration file and rerun.
WARNING (TEM-930): No test wrapped address bus found that corresponds to clock
clkPinName and system address bus addrPinName of memory cell memCellName. No
instances of this memory cell have BIST inserted. Ensure a test wrapped address bus exists
for each system address bus in the test wrapped memory and rerun.
EXPLANATION:
The program is unable to find a test wrapped address bus related to the system address
bus for a port clocked by the referenced clock pin. Ensure the related clocks for the

system and test wrapped address bus are set properly. Also make sure the test wrapped
bus uses the default naming convention or is aliased in the configuration file.
USER RESPONSE:
To insert BIST in the referenced memory cell, verify a test wrapped address bus exists
for each system address bus in the referenced test wrapped memory. Refer to Inserting
Memory Built-In-Self-Test Logic in Design For Test in Encounter RTL Compiler.
WARNING (TEM-931): No test wrapped output enable pin found that corresponds to system
output enable pin outputEnPinName for the port of memory cell memCellName clocked
by pin clkPinName. No instances of this memory cell have BIST inserted. Ensure a test
wrapped output enable pin exists for each system output enable pin on a test wrapped
memory and rerun.
EXPLANATION:
The program is unable to find a test wrapped output enable pin that corresponds to a
specified system output enable pin for a port clocked by the referenced clock pin. Ensure
the related clocks for the system and test wrapped enable pin are set properly. Also make
sure the test wrapped enable pin uses the default naming convention or is aliased in the
configuration file.
USER RESPONSE:
To insert BIST in the referenced memory cell, verify a test wrapped output enable pin
exists for each non-test wrapped output enable pin in a test wrapped memory and rerun.
RTL Compiler.
WARNING (TEM-932): Specified synthesis string synthesisPath does not match the
version requirements. Ensure the specified path to BuildGates Extreme contains version
greater than or equal to 5.14.
EXPLANATION:
Encounter Test Architect is packaged with BuildGates version 5.14 - 32 bit. In cases of
large designs that require 64 bit BuildGates, specify the path to 64 bit version of Build
Gates, if available, and include the string -. Encounter Test Architect also requires the
BuildGates Extreme with (bgx) with a minimum version of 5.14.
USER RESPONSE:
Verify the specified BuildGates Extreme version is at the minimum required version of
5.14. Ensure the string usersyn=bgx_shell -64 is specified with the location of the
BuildGates Extreme, if 64 bit synthesis is required.

WARNING (TEM-933): Library file libFileName appears to be .srule format instead

of the required .lib format and is ignored. Replace the file with a .lib format and type and
rerun.
EXPLANATION:
The synlib keyword requires the library files be liberty (.lib) format. The specified
library file contains a .srule extension which indicates the file may have a format of
type .srule. The library file with the srule extension is not evaluated and is ignored
during further processing.
USER RESPONSE:
Specify a .lib file format and type for the synlib keyword and rerun.
WARNING (TEM-935): Test wrapped read bus testReadBus is not related to same clock
pin clockPin as functional read bus funcReadBus of memory cell memCellName.
Ensure each port of a test wrapped memory cell has a unique clock pin and that the functional
read bus and test wrapped read bus are related to same clock pin.
EXPLANATION:
relate pins/buses to their corresponding ports using the related clock attribute in the
liberty (.lib) file. In case of a test wrapped memory cell, it is required to have both test
wrapped and functional pins/buses associated with same port to relate to same clock pin.
For a specified test wrapped memory cell, a test wrapped read bus did not relate to the
same clock pin as functional read bus.
USER RESPONSE:
Check the liberty file to ensure that test wrapped read bus is related to the same clock
pin as the corresponding functional read bus associated with the port and rerun if
necessary.
ERROR (TEM-950): [Internal] Cannot find the sink BIST engine pin corresponding to
source JTAG pin pinName. Contact Cadence Customer Support for assistance.
EXPLANATION:
USER RESPONSE:

customer support.
ERROR (TEM-951): [Internal] Unable to trace pin pinName. Error code

errorCodeNum. Contact Cadence Customer Support for assistance.
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-952): [Internal] Cannot find instance instanceName of cell cellName.

EXPLANATION:
USER RESPONSE:

customer support.
ERROR (TEM-953): [Internal] Insert embedded test internal program error. Error code
errCodeNum. Contact Cadence Customer Support for assistance.
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-954): [Internal] Cannot determine the output enable pin structure
associated with the read bus readBusName of memory cell memCellName. Contact
EXPLANATION:
USER RESPONSE:
customer support.

ERROR (TEM-998): [Internal] An unexpected condition occurred in the Encounter Test

progName code. Contact customer support to report this error and give them the following
information: errorCode | errorInfo
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TEM-999): [Internal] An unexpected condition occurred in the Encounter Test

progName code. workaround if any
Contact customer support to report this error and give them the following information: error
occurred on line linenumber of source file filename.
Additional data: otherdata

EXPLANATION:
USER RESPONSE:
customer support.


29
TFL - Failure Data Messages
TFL-001 through TFL-050 on page 937

TFL-001 through TFL-050

INFO (TFL-001): application started.
EXPLANATION:
This informational message indicating start of the application.
USER RESPONSE:
INFO '(TFL-002): application ended with a return code of return_code.

EXPLANATION:
This is an informational message indicating completion status of the application.
USER RESPONSE:
No response is necessary unless the return code indicates an error was detected.
Generally, an error is detected if the return code is greater than 1. In that case, refer to
preceding messages for more details.
INFO (TFL-003): A total of number_of_failures failures will be processed.

EXPLANATION:

This message identifies the number of failures that will be processed by the run. When
this number is less than the total number of failures in the specified failset, see the
preceding messages for detailed explanation.
USER RESPONSE:
INFO (TFL-004): command_name ended - CPU time=CPU_time, Elapsed

time=elapsed_time.
EXPLANATION:
This message indicates command completion and the associated CPU and elapsed
times.
USER RESPONSE:
WARNING (TFL-005): [Severe] Could not read diagnostic clock gating information from file
file_name, attempting to read file_section_name. The error code was
error_number : error_string.
EXPLANATION:
The referenced file should contain clock gating information. An error occurred attempting
to read the specified file_section_name. The error code from the system read and the
text associated with that error code is included in the message. The file is probably
corrupted. No clock gating data is available.
USER RESPONSE:
Rerun the prepare_diagnostic_clock_gating command with replace=yes
specified, and then rerun the command that produced this error.
WARNING (TFL-006): [Severe] Could not write diagnostics clock gating information to file
file_name, attempting to write file_section_name. The error code was
error_number : error_string.
EXPLANATION:
An error occurred attempting to write the file_section_name of the referenced file.
The error code from the system write and the text associated with that error code is
included in the message. The file is probably corrupted. No clock gating data is available.
USER RESPONSE:

Attempt to resolve any obvious problem, and rerun the

prepare_diagnostic_clock_gating command with replace=yes specified. If
the problem persists, contact Customer Support (see Contacting Customer Service on
page 23) to report this error.
INFO (TFL-008): Mapped failures summary (number of failures and core cell name):
EXPLANATION:
This informational message states that a summary of mapped failures totals for the run,
by specific core cell name is produced.
USER RESPONSE:
WARNING (TFL-009): A total of number_of_failures of the processed failures did not

map to an embedded core.
EXPLANATION:
This message identifies the number of failures that did not map to an embedded core and
are, therefore, associated with the wrapper logic.
USER RESPONSE:
Failures associated with the wrapper logic should be diagnoseable with the existing
Encounter Test model. Therefore, diagnose them with Encounter Diagnostics.
ERROR (TFL-010): Failset FAILSET was not created because it already exists and is
currently in use.
EXPLANATION:
Specifying the name of an existing failset to Read Failures will cause that failset to be
overwritten. In this case, the failset could not be overwritten because it was in use.
USER RESPONSE:
Either rerun with a different failset name or rerun when the referenced failset is no longer
in use.
ERROR (TFL-011): Unable to open failset FAILSET. File file_name does not exist.
Processing ends.
EXPLANATION:
The failure data associated with the FAILSET was not found in file file_name as this file
does not exist.

USER RESPONSE:
Recreate the failset using read_failures.
WARNING (TFL-012): Unable to read failset FAILSET. The file file_name exists but is
not readable. Processing continues.
EXPLANATION:
The failure data associated with failset FAILSET is in file file_name, but this file is
not readable.
USER RESPONSE:
Resolve any file permission problems and rerun.
WARNING (TFL-013): Unable to open failset FAILSET. File file_name exists, but is not
registered. Processing continues.
EXPLANATION:
The failure data associated with failset FAILSET exists in the referenced file name, but
this file is not registered with Encounter Test.
USER RESPONSE:
No response is required unless subsequent errors are encountered. In that case,
recreate the failset using read_failures.
ERROR (TFL-014): Unable to open failset FAILSET. File file_name exists, but is
unavailable because it is being updated. Processing continues.
EXPLANATION:
The failure data associated with FAILSET is in the indicated file, but this file is not
available because it is currently being updated.
USER RESPONSE:
Rerun when the failset is available.
ERROR (TFL-015): Unable to read failset FAILSET. File file_name exists but is
corrupted. Processing ends.
EXPLANATION:
The failure data associated with FAILSET is in the indicated file, but the information is not
in the expected format. This indicates the file has likely been corrupted making the failure
data unavailable.

USER RESPONSE:
Recreate the failset using read_failures.
WARNING (TFL-016): Unable to open failset FAILSET because the associated experiment
experiment could not be opened. Processing continues.
EXPLANATION:
The application could not access the failure data associated with FAILSET because the
indicated experiment could not be opened.
USER RESPONSE:
Ensure the correct EXPERIMENT was specified. If the correct EXPERIMENT was
specified, refer to preceding messages to determine why the indicated experiment could
not be opened.
WARNING (TFL-017): count failure specifications in the input file indicate a measured
value of X.
EXPLANATION:
The specification of X in the measured value of a failure record prevents read_failures
from ensuring that the measured value is different from the expected value in the
associated test vectors. The miscompares will still be imported and used, but
read_failures cannot verify that the failures are related to the test vectors.
If the failures were collected using the associated test vectors, Encounter Diagnostics will
generate correct results. Otherwise, but the results will be incorrect.
USER RESPONSE:
If the measured values can be collected and specified in the failure data, adding them to
the failure data will improve confidence in any diagnostic result.
If not, verify that the failure data was derived from the test vectors specified before
accepting the diagnostic result.
ERROR (TFL-018): The testmode testmode defines the presence of output compression,
yet Diagnostic Measure events do not exist in the input test vectors. These events are
required for diagnosing failures associated with this type of test data.
EXPLANATION:
Diagnostic measure events are required for diagnosing failures when output
compression exists.
USER RESPONSE:

Resimulate the vectors using diagnosticmeasures=100 to create the diagnostic

measure events and rerun.
ERROR (TFL-019): An invalid adminuser name has been specified. The name
user_name exceeds the maximum length of maximum_length.
EXPLANATION:
The specified adminuser name cannot exceed the maximum length identified in the
message.
USER RESPONSE:
Respecify adminuser name and rerun.
ERROR (TFL-020): An invalid diagnostic database name has been specified. The name
database_name exceeds the maximum length of maximum_length Respecify the
diagnostic database name and rerun.
EXPLANATION:
The specified diagnostic database name cannot exceed the maximum length identified
in the message.
USER RESPONSE:
Respecify a valid database name and rerun.
ERROR (TFL-021): The specified diagnostic database name database_name is invalid

because the name is reserved. Specify the diagnostic database name and rerun.
EXPLANATION:
The names test, mysql, mysql. errlog, mysql.pid, and xor are reserved, and
cannot be used as diagnostic database names.
USER RESPONSE:
Specify a valid database name and rerun.
ERROR (TFL-022): Failed to start the diagnostic database server. See error log file
error_log.
EXPLANATION:
The instantiation of the database server failed. Subsequently, no volume diagnostic data
will be stored in the database. The error log file identified in the message should contain
additional information. One cause may be that a diagnostic database server is already
running on this host.

USER RESPONSE:
Refer to the error log for further action.
ERROR (TFL-024): The failset name cannot be created because it already exists.
EXPLANATION:
The referenced failset already exists. Encounter Test will not overwrite an existing failset.
USER RESPONSE:
Either specify a different failset name or delete the existing failset before creating the new
failset with this name.
ERROR (TFL-025): Could not create failset FAILSET due to failure to open the associated
test vector file.
EXPLANATION:
Encounter Test was unable to create failset FAILSET because it could not open the
associated test vector file. This message is preceded by additional detailed messages
related to this problem.
USER RESPONSE:
Refer to preceding messages, take any necessary corrective action, and then rerun.
WARNING (TFL-026): Writing new failures for failset FAILSET into file file_name, but
the file already exists. The file will be overwritten.
EXPLANATION:
Encounter Test is attempting to write failure data for failset FAILSET to the indicated file
but this file already exists. Encounter Test will replace the information in this file with
FAILSET data.
USER RESPONSE:
ERROR (TFL-027): Unable to create failset FAILSET due to failure to write to file
file_name. Processing ends.
EXPLANATION:
While attempting to write the failure data for the referenced failset into the referenced file
name, Encounter Test encountered an error. Processing ends and the FAILSET is not
created.

USER RESPONSE:
Determine the cause of the problem writing to the specified file. It may be a problem with
the available disk space for the file, or a file permission problem. Rerun after resolving
the problem.
ERROR (TFL-028): Unable to create failset FAILSET due to failure to register file
file_name. Processing ends.
EXPLANATION:
While attempting to create FAILSET, the application encountered an error when trying to
register the indicated file with Encounter Test. Processing ends and the FAILSET is not
created. This message is preceded by messages that provide more detail.
USER RESPONSE:
See preceding messages, take any necessary corrective action, and then rerun.
WARNING (TFL-029): Unable to create failset FAILSET due to failure to register a

dependency on experiment experiment.
EXPLANATION:
While attempting to create FAILSET, the application encountered an error when trying to
register a dependency on the associated test vectors contained in the indicated
experiment. This message is preceded by other messages that provide more detail.
USER RESPONSE:
(severity) (TFL-030): Unable to create file file_name due to failure to obtain a write
lock.
EXPLANATION:
Prior to writing to the indicated file, Encounter Test attempted to obtain a write lock to
ensure there is no contention for the file. In this case, the write lock could not be
obtained, therefore the file was not generated.
USER RESPONSE:
This message should be preceded by other messages which identify the reason why the
write lock could not be obtained. Depending on the reason and the severity of this TFL-
030 message, you may need to take corrective action.
If for example, the reason indicates a file permissions problem, and severity_code
is ERROR, this most likely requires a corrective action. However, if the reason indicates

that another process already obtained a write lock (therefore was generating the file),
and severity_code is WARNING, this most likely does not require corrective action.
ERROR (TFL-031): Input/Output error encountered while writing failset FAILSET.

EXPLANATION:
A file I/O error was encountered while writing the failure to disk.
USER RESPONSE:
Determine the cause of the problem while writing to the associated file. It may be a
problem with the available disk space for the file, or a file permission problem. Rerun after
resolving the problem.
ERROR (TFL-032): Deletion of failset FAILSET failed. The Failset is in use.

EXPLANATION:
The application could not delete the referenced failset because it is currently in use.
USER RESPONSE:
Wait until the fail is no longer in use and then rerun.
WARNING (TFL-033): An unexpected condition occurred while deleting failset FAILSET.

File file_name does not exist. Processing continues.
EXPLANATION:
The failure data associated with failset FAILSET should reside in the indicated file.
However, such a file does not exist. Failset deletion proceeds regardless of this condition.
USER RESPONSE:
No response is required if failset deletion completes successfully with no additional
messages. Otherwise, refer to the additional messages, take any necessary corrective
action, and then rerun.

File file_name exists, but is not readable. Processing continues.
EXPLANATION:
The data associated with failset FAILSET resides in the indicated file. However, this file
was not readable during failset deletion. Failset deletion proceeds regardless of this
condition.
USER RESPONSE:



File file_name exists, but is not registered. Processing continues.
EXPLANATION:
The data associated with failset FAILSET resides in the indicated file. However, this file
is not registered with Encounter Test. Failset deletion proceeds regardless of this
condition.
USER RESPONSE:

Failed to remove dependency on experiment experiment. Processing continues.
EXPLANATION:
Failset deletion includes the removal of Encounter Test dependency data which denotes
the relationship between a failset and associated test vectors stored in the indicated
experiment. The application could not remove the dependency data either because it
was not present, or because an error occurred during removal. In case of an error, this
message is preceded by messages that provide more detail. Failset deletion proceeds
regardless of this condition.
USER RESPONSE:

Failed to unregister file file_name. Processing continues.
EXPLANATION:
Failset deletion includes the removal of Encounter Test file registration data which should
be automatically saved when a failset is created. The registration data could not be
removed either because it was not present, or because an error occurred during removal.
In case oi an error, this message is preceded by other detailed messages. Failset
deletion proceeds regardless of this condition.

USER RESPONSE:
messages. Otherwise, see additional messages, take any necessary corrective action,
and then rerun.
ERROR (TFL-038): Could not create the diagnostic clock gating file for committed test
patterns for testmode testmode. Unable to register file file_name.
EXPLANATION:
The program is attempting to create a diagnostics clock gating file for the committed test
pattern data for the specified testmode. The clock gating file, file_name, must be
registered in the globalData file. However, the program was unable to register this file.
This message is preceded by messages that provide more detail.
USER RESPONSE:
Review the preceding messages, take any necessary corrective action, and then rerun.
ERROR (TFL-039): Could not create the diagnostics clock gating file for test patterns in
experiment experiment for testmode testmode. Unable to register file filename.
EXPLANATION:
The program is attempting to create a diagnostics clock gating file for the experimental
test pattern data for the specified experiment for the specified testmode. The clock gating
file, file_name, must be registered in the globalData file. However, the program was
unable to register this file. This message is preceded by messages that provide more
detail.
USER RESPONSE:
Check the preceding messages, take any necessary corrective action, and then rerun.
ERROR (TFL-040): Unable to create file file_name due to failure to obtain a write lock.
EXPLANATION:
Prior to creating file file_name, Encounter Test attempted to obtain a write lock to
ensure there is no contention for the file. The write lock could not be obtained and the file
was not generated. This message is preceded by other messages that provide more
detail.
USER RESPONSE:
Check the preceding messages, take any necessary corrective action, and then rerun.

ERROR (TFL-041): Could not create diagnostic clock gating file. Unable to register a
dependency on experiment experiment.
EXPLANATION:
Encounter Test is attempting to create a diagnostics clock gating file associated with the
specified experiment, and is attempting to register this dependency in the globalData file,
but was not successful. This message is preceded by other messages that provide more
detail.
USER RESPONSE:
WARNING (TFL-042): [Severe] The following failure was rejected - expected value
failure_expected_observe_value does not match test vector value
test_vector_expected_observe_value
EXPLANATION:
A discrepancy was detected when attempting to add the indicated failure to the failset.
The expected observe value associated with the failure does not match the expected
observe value in the corresponding Encounter Test vector data. The failure is not added
to the failset.
USER RESPONSE:
There are several possible causes for this discrepancy. The most probable causes are:
Incorrect specification of the associated Encounter Test vectors. The test
vectors must match those used to derive the failure data. Correct values for
TESTMODE and EXPERIMENT (if any), must be provided.
Incorrect failure data. When importing text Chip_Pad_Pattern format, it is vital
that the pattern and offset specifications correctly resolve to the
Encounter Test vectors.
Investigate the possible causes and take any necessary corrective action before
rerunning.
WARNING (TFL-043): [Severe] The following failure was rejected - expected value
expected_value matches measured value failure_description.
EXPLANATION:
The indicated failure specification was rejected and therefore not included in the resultant
failset. As the failing value matches the expected value for the associated measure, this
failure specification is not valid.

USER RESPONSE:
Correct the failure specification and rerun.
INFO (TFL-044): The following failure was rejected - measured value of Z is allowed for only
3-state Primary Outputs associated with Measure_PO events.
failure
EXPLANATION:
failset. A measured value of Z was specified, however this value is acceptable only for 3-
state Primary Outputs associated with Measure_PO events.
USER RESPONSE:
No response is required, however you may correct the ignored failure specification and
rerun.
WARNING (TFL-045): A syntax error was detected on line line_number. Failure:

failure_detail
EXPLANATION:
A syntax error was detected on the referenced line number of the failure file being read.
This line in the file contains the errant failure specification which is also included in this
message. This failure specification is ignored, and processing continues. Causes of
syntax errors include incomplete specifications, invalid values and a specification which
spans multiple lines. The user documentation includes a complete description of the
failure data syntax.
USER RESPONSE:
To include the desired failure in the failset, correct the failure specification and rerun.
Refer to Processing Failure Data in the Encounter Test: Guide 7: Diagnostics for
ERROR (TFL-046): Could not create the diagnostic clock gating file. Unable to open test
vector file.
EXPLANATION:
Encounter Test was unable to create the diagnostics clock gating file because it was
unable to open the associated test vector file. This message is preceded by additional
detailed messages related to this problem.
USER RESPONSE:

WARNING (TFL-047): [Severe] The file parent_file_name has changed since the
dependent file child_file_name was created. The diagnostics clock gating data will not
be used.
EXPLANATION:
The diagnostics clock gating file depends on the data in the test pattern file, but the test
pattern file has changed since the diagnostics clock gating file was created. Therefore,
information that currently exists in the clock gating file is incorrect, and will not be used.
USER RESPONSE:
Diagnostic results without the diagnostics clock gating information will still be valid, so
this message may be ignored. However, any performance and accuracy benefits from
the clock gating information will be lost. To realize these benefits, recreate the diagnostic
clock gating file using the prepare_diagnostics_clock_gating command with
replace=yes, and then rerun.
WARNING (TFL-048): The diagnostics clock gating file, file_name exists, and will be
deleted, but was not previously registered. Processing continues.
EXPLANATION:
The data associated with the diagnostics clock gating resides in file file_name. Such
a file exists, and will be deleted, but is not registered in the Encounter Test globalData file.
USER RESPONSE:
No response is required. This message indicates a potential problem with the globalData
file.
WARNING (TFL-049): Unable to remove the dependency of the diagnostics clock gating file
on experiment experiment. Processing continues
EXPLANATION:
The process of removing the diagnostics clock gating file involves removing the
globalData information that shows that the file is dependent on its associated
experiment. Such dependency information could not be removed from the globalData,
either because it never existed or because there was a problem updating the globalData
file.
USER RESPONSE:
file.

ERROR (TFL-050): The diagnostic database control file should not reside in the database
directory. Processing ends.
EXPLANATION:
The command line arguments indicate the diagnostic database control file has to be
created in the database directory. As the database directory does not have read
permission for any user other than the owner of the directory, the database control file
should not be kept in the database directory. Instead, the file should be stored at a
location that has read permission for all volume diagnostics users.
USER RESPONSE:
Specify a different location for the database control file and rerun.

WARNING (TFL-051): Multiple specifications of condition name condition_name were
detected for device device. Only the first specification will be used.
EXPLANATION:
The indicated condition name appears multiple times in a Chip-Lot-Wafer record for the
indicated device in the failures being read. This ambiguity is resolved by accepting only
the first specification.
USER RESPONSE:
If the first specification is not the intended one, modify the input by specifying a single
instance of the indicated condition name in the Chip-Lot-Wafer record for the indicated
device and rerun.
WARNING (TFL-052): Maximum length of maximum_length characters exceeded for

the name|value of condition named condition_name on line line_number. This
condition specification is ignored.
EXPLANATION:
The specified line contains a Chip-Lot-Wafer specification in which a condition name
and/or value which exceeds the maximum supported length for this field. Processing
continues with the indicated condition name and value being ignored.
USER RESPONSE:
To include the desired condition in the failset, correct the specification and rerun.

WARNING (TFL-053): [Severe] Unable to add failure to failset FAILSET. A measure

location could not be determined from the offset or position and pattern specifications.
Failure: failure_detail
EXPLANATION:
The indicated failure could not be added to the FAILSET because of an inconsistency
between the specified offset or position, and the pattern. Either the pattern corresponds
to a Scan Unload event and the offset or position is -1, or the pattern corresponds to a
Measure PO event and the offset or position is not -1.
USER RESPONSE:
Modify the appropriate specification and rerun. Both the offset and position specify the
relative bit position with respect to the scan out pin. Note that offset is zero-origined,
while position starts at 1. For PO failures, offset or position must be specified as -1.
WARNING (TFL-054): An invalid diagnostics database name has been specified. The
specified name has been modified to modified_database_name to meet diagnostic
database naming rules.
EXPLANATION:
Volume diagnostics database names should not contain upper case letters. The
specified volume diagnostics database name contains upper case letters, hence it is
automatically modified to a new name by converting the upper case letters to lower case.
USER RESPONSE:
No response is required. The modified diagnostic database name must be used for
referencing the database.
INFO (TFL-055): FailSet FAILSET created containing number_of_failures failures

on number_of_devices devices read_details
EXPLANATION:
The specified failset was created successfully.
USER RESPONSE:
WARNING (TFL-056): A subset of resultant_number_of_failures failures has

been selected from the total set of total_number_of_failures failures due to
device_specification_testrange_specification failures being associated
with embedded cores.

EXPLANATION:
The currently specified values for device and/or testrange have resulted in a subset
of the input failure data to be processed.
USER RESPONSE:
No response is required if this condition is expected. Otherwise, modify the appropriate
specifications and rerun.
INFO (TFL-057): Ignored number_of_failures_ignored specifications associated

with MISR observes.
EXPLANATION:
Input failures contained PO measures that represent MISR signatures and are not
considered failing measures. Hence they are not included in the failset.
USER RESPONSE:
WARNING (TFL-058): [Severe] The following failure was rejected - Interval/Iteration was
specified, but the measure location does not resolve to a channel scan event.
Failure: failure
EXPLANATION:
The indicated failure could not be added to the failset because it specifies an interval and/
or iteration but the measure event corresponding to this failure is not a Channel Scan
event. Failures containing interval and iteration are only supported for Channel Scan
events.
USER RESPONSE:
Modify the indicated failure to ensure it is associated with a Channel Scan event, and
rerun.
WARNING (TFL-060): [Severe] The following failure was rejected - identifier of

value is invalid.
failure_specification
EXPLANATION:
failset. Because an invalid value was specified for the indicated identifier, this failure
specification is not valid.
USER RESPONSE:

WARNING (TFL-061): [Severe] Unable to add failure to failset FAILSET -

identifier of value is invalid.
EXPLANATION:
The application rejected the indicated failure specification and therefore did not include
it in the resultant failset. As an invalid value was specified for the indicated identifier, this
failure specification is not valid.
USER RESPONSE:
WARNING (TFL-062): The Chip-Lot-Wafer statement on line line_number exceeds the

maximum number of conditions of maximum_conditions. The remaining conditions are
ignored.
EXPLANATION:
The line specified contains a Chip-Lot-Wafer specification which exceeds the maximum
number of supported conditions for a single device. Conditions up to the maximum
supported will be used, but the remaining conditions will be ignored.
USER RESPONSE:
No action is required if the remaining conditions are not required. Otherwise, contact
Cadence Customer Support with this issue (see Contacting Customer Service on
page 23).
ERROR (TFL-063): Attempt to stop the volume diagnostics server failed since the
connection could not be established with the server.
EXPLANATION:
The attempt to stop the volume diagnostics server could not be completed because of a
failure to connect to the server with the necessary authority.
USER RESPONSE:
Refer to preceding messages which offer additional details on the connection failure.
INFO (TFL-064): Shutdown of the diagnostic database server was successful.

EXPLANATION:
This informational message indicates successful shut down of the diagnostic database
server.

USER RESPONSE:
ERROR (TFL-065): Unable to update diagnostic database control information. Error reading
control file file_name.
EXPLANATION:
The application could not access and therefore update the indicated diagnostic database
control file. This message is preceded with other messages providing details on
diagnostic database control file access error.
USER RESPONSE:
Refer to preceding messages, take any corrective action, then rerun.
INFO (TFL-066): The specified administrator user and password match the current values.
No update of the diagnostic database control information is performed.
EXPLANATION:
The diagnostic database control information was not updated because the specified
administrator user and password match the existing values.
USER RESPONSE:
No action is required if the existing administrator user and password are desired.
Otherwise, rerun with a different adminuser or adminpassword.
ERROR (TFL-067): Unable to update diagnostic database control information. Error writing
control file file_name.
EXPLANATION:
The application could not write and and therefore update the referenced diagnostic
database control file. While the inability to write the control file could have several
possible causes, the most likely cause is insufficient file access permissions.
USER RESPONSE:
Ensure appropriate file access permissions and rerun.
INFO (TFL-068): ): The volume server file is written to file_name.

EXPLANATION:
This informational message indicates that the volume server file is written to
the indicated location.

USER RESPONSE:
INFO (TFL-069): The diagnostic database control file was successfully updated.
EXPLANATION:
This informational message indicates that the diagnostic database control file was
successfully updated with the specified access control information.
USER RESPONSE:
ERROR (TFL-070): The diagnostic database control information was not updated.
EXPLANATION:
The application could not update the diagnostic database control information. This is
preceded by other messages providing more detail on why the update failed.
USER RESPONSE:
Refer to preceding messages, and take any necessary corrective action, then rerun.
ERROR (TFL-072): A volume diagnostics server is already running on a different host

host_name.
EXPLANATION:
A volume diagnostics server is already running on a different host. To start the server on
this host, specify a different databasedirectory or please request the owner of the
database directory to stop the server on the specified host and restart on the current
host.
USER RESPONSE:
Log in the reported host name and rerun the command.
ERROR (TFL-073): Failed to start the diagnostic database server. A diagnostic database
server is already running on host host_name.
EXPLANATION:
An attempt to start a diagnostic database server was made for the indicated host where
a diagnostic database server is already running. This is not supported.
USER RESPONSE:

Log in to an alternate host to start an additional diagnostic database server.
ERROR (TFL-074): Failed to start the diagnostic database server. The directory
directory_name to save database initialization file could not be created.
EXPLANATION:
An attempt to start a volume diagnostics server failed because the indicated directory
could not be created. This is most likely a permissions problem.
USER RESPONSE:
Ensure appropriate permissions to create the indicated directory and rerun.
ERROR (TFL-075): Failed to start the diagnostic database server. Unable to establish
diagnostic database server administrator user user_name.
EXPLANATION:
An attempt to start a diagnostic database server failed because the indicated user could
not be established with administrative authority. This is preceded by additional messages
with details on the problem.
USER RESPONSE:
Refer to the preceding messages, take any necessary corrective action, and then rerun.
ERROR (TFL-076): Failed to start the diagnostic database server. Unable to obtain a license
for product product_name.
EXPLANATION:
The application could not obtain the required license for the indicated product. The
diagnostic database server cannot be started without the required license. Refer to
Encounter Test and Diagnostics Product License Configuration in Encounter Test:
Release: Whats New.
USER RESPONSE:
Ensure the availability of the required license and then rerun.
ERROR (TFL-077): The diagnostic database server is being stopped.

EXPLANATION:
The diagnostic database server process is being stopped. This message is preceded by
additional messages with further details.
USER RESPONSE:

Refer to the preceding messages, take any necessary corrective action, then rerun .
WARNING (TFL-078): [Severe] Mismatch detected between the specified design and
diagnostic database. Primary Output pin pin_name does not match information in the
diagnostic database.
EXPLANATION:
A sanity check is performed to ensure that the diagnostic database is consistent with the
design being processed. The check ensures the Primary Outputs identically match,
including their relative order. In this case, the check determined a mismatch that
indicates the design and database are incompatible. Consequently , information from the
current design cannot be stored in the referenced diagnostic database. This condition is
most likely the result of a change to the design subsequent to the creation of the
USER RESPONSE:
The design and the referenced diagnostic database are incompatible, create a new
database for the design. Complete the project setup process for this design and then
rerun.
WARNING (TFL-079): [Severe] Mismatch detected between the specified design and
diagnostic database. Scan chain register register_number, bit bit_number does not
match information in the diagnostic database.
EXPLANATION:
A sanity check is performed to ensure that the diagnostic database is consistent with the
design being processed. The check that the scan flip-flops identically match, including
their relative order. In this case, the check determined a mismatch that indicates the
design and database are incompatible. Consequently , information from the current
design cannot be stored in the referenced diagnostic database. This condition is most
likely the result of a change to the design subsequent to the creation of the diagnostic
database.
USER RESPONSE:
The design and the referenced diagnostic database are incompatible, create a new
database for the design. Complete the project setup process for this design and then
rerun.
INFO (TFL-080): Added failures from die_count failing die to the diagnostic database.
Time used (CPU/Elapsed) CPU_time/elapsed_time.
EXPLANATION:

This message indicates the number of die added to the diagnostic database.
USER RESPONSE:
WARNING (TFL-081): Error detected in control file file_name. Attempting to connect to

the volume diagnostics server using default values.
EXPLANATION:
An error was detected when reading access information from the indicated volume
server file. Necessary information was not present in the file. It is possible the file has
been corrupted in some manner. Processing continues with an attempt to connect to the
volume diagnostics server using default access values.
USER RESPONSE:
No response is required if the subsequent connection attempt is successful. Otherwise,
contact Cadence Customer Support (see Contacting Customer Service on page 23) to
report this information.
WARNING (TFL-082): Error reading control file file_name. Attempting to connect to the
diagnostic database server using default values.
EXPLANATION:
An error was detected when attempting to read the indicated control file. Consequently,
the necessary access information could not be obtained. It is possible the file
permissions are not set to enable access. Processing continues with an attempt to
connect to the diagnostic database server using default access control values.
USER RESPONSE:
No response is required if the subsequent connection attempt is successful. Otherwise,
verify the file exists and the appropriate permissions are set, then rerun.
WARNING (TFL-083): [Severe] Failed to connect to the volume diagnostics server on host
server_name and port port_number with administrative authority. ensure that you have
started the volume diagnostics server by running the start_volume_server command.
EXPLANATION:
An error was detected when attempting to connect to the diagnostic database server on
the indicated host and port with administrative authority. The attempted operation
requires administrative authority to be completed.
USER RESPONSE:

Check with your volume diagnostics server administrator to gain the necessary access
authority and rerun.
WARNING (TFL-084): [Severe] Failed to connect to the volume diagnostics server on host
server_name and port port_number for database database_name.
EXPLANATION:
An error was detected when attempting to connect to the diagnostic database server on
the indicated host and port for the indicated database. The attempted operation on the
diagnostic database cannot be completed.
USER RESPONSE:
ensure that you have started the volume diagnostics server by running the
start_volume_server command.
WARNING (TFL-085): [Severe] Failed to connect to the diagnostic database server.

Unable to read the design information from the ET database.
EXPLANATION:
An error was detected when attempting to connect to the diagnostic database server.
The design information could not be read from the ET globalData database to derive the
volume database connection information for this design.
USER RESPONSE:
Ensure the indicated file exists and has appropriate permissions to enable read access,
then rerun.
WARNING (TFL-086): [Severe] The request to update the diagnostic database

database_name cannot be satisfied.
EXPLANATION:
An error was detected when attempting to update the indicated diagnostic database.
This message is preceded by another message related to a problem connecting to the
diagnostic database server.
USER RESPONSE:
Respond to the preceding message related to a diagnostic database connection
problem.
WARNING (TFL-087): [Severe] Unable to update the diagnostic database because

multiple failing die information is present for device device_name.
EXPLANATION:

The indicated device appears in multiple Chip-Lot-Wafer records in the failures being
read. This is an ambiguous specification which is invalid and prevents updating of the
USER RESPONSE:
Ensure the indicated device is contained in a single Chip-Lot-Wafer record and rerun.
WARNING (TFL-088): [Severe] The request to update the diagnostic database cannot be
satisfied connectivity to the database is not established.
EXPLANATION:
The request to update the diagnostic database can not be satisfied. This is likely
because a diagnostic database has not been specified for this project through the Setup
form or the diagnostic database has been disconnected from the project.
USER RESPONSE:
If running with the project disconnected from a diagnostic database is desired, then this
message can be ignored. In this case, allow the updatediagnosticdatabase option
to default and rerun.
Otherwise, specify a diagnostic database through Setup form (Click File-Setup-
Options-Diagnostics Database)_and rerun.
INFO (TFL-089): Replaced failures from die_count failing die in the diagnostic database.
Time used (CPU/Elapsed) CPU_time/elapsed_time.
EXPLANATION:
This message indicates the number of die replaced in the diagnostic database. This
replacement not only removes the failure information from the diagnostic database, but
also any associated results from diagnose_failset_logic.
USER RESPONSE:
WARNING (TFL-090): [Severe] Unable to update the diagnostic database. Only Chip-Pad-
Pattern and STIL formats are supported when updating the diagnostic database.
EXPLANATION:
The failures being read were determined to not be of the Chip-Pad-Pattern or STIL
formats. Only failures derived from reading Chip-Pad-Pattern or STIL may be written to
the diagnostic database.
USER RESPONSE:

Either convert the failures to the required format and rerun, or rerun with
updatediagnosticdatabase=no.
WARNING (TFL-091): [Severe] The Chip-Lot-Wafer record was not present for device
device.
EXPLANATION:
The Chip-Lot-Wafer record is required to create volume diagnostics related information
for this failing die. For the reported device, this information is not available.
USER RESPONSE:
Modify the failure file to include the missing die information and reimport the failures.
ERROR (TFL-092): Failset FAILSET was created using a later version of Encounter Test,
and is not compatible with this version. Processing ends.
EXPLANATION:
The indicated failset is incompatible with the version of Encounter Test being used. This
can occur when a later version of Encounter Test is used to read failures, then an attempt
is made to process the resultant failset using an earlier version of Encounter Test.
USER RESPONSE:
Rerun using a version of Encounter Test that is compatible with the failset.
WARNING (TFL-093): Device device failed the test_type. Processing continues

because the testrange specification does not include the test_type.
EXPLANATION:
The indicated device has failed either the scan chain test or the LSSD Flush test.
However, Diagnose Failset Logic assumes that the scan chains are functional. As the
current testrange specification does not include the scan chain test or LSSD Flush
test, processing continues.
USER RESPONSE:
None required. However, this device is a likely candidate for Diagnose Failset Scan
Chain.
INFO (TFL-094): Device device is ignored because it failed the test_type.

EXPLANATION:

The indicated device has failed the LSSD Flush test and/or scan chain test, and is also
specified for Diagnose Failset Logic. Diagnose Failset Logic assumes that the scan
chains are functional. Therefore, the fail data associated with this device is ignored.
USER RESPONSE:
No response is required. However this device is a likely candidate for Diagnose Failset
Scan Chain. Diagnose Failset Logic may still be performed for this device by specifying
a testrange that does not include the Scan Chain or LSSD Flush tests.
INFO (TFL-095): The file_name file is being migrated to its latest version.
EXPLANATION:
The current version of the indicated file is at a back level and will be migrated to be
compatible with this version of Encounter Test.
USER RESPONSE:
INFO (TFL-096): A subset of resultant_number_of_failures failures has been

selected from the total set of total_number_of_failures failures, by the
device_specification/testrange_specification specification.
EXPLANATION:
The current device and/or testrange specifications have resulted in a subset of failures
to be processed.
USER RESPONSE:
ERROR (TFL-097): FAILSET file file_name is in conflict with input file file_name.
EXPLANATION:
The indicated file has been previously read, but the current failset name is in conflict with
the previously used FAILSET.
USER RESPONSE:
The expected name is derived from the concatenation of the following:
$WORKDIR/TBDfail.$TESTMODE.$EXPERIMENT.$FAILSET.
Specify options consistent with the input file name and rerun.

(TFL-098): INFO FailSet FAILSET has been registered.

EXPLANATION:
The registration of the indicated failset has completed successfully.
USER RESPONSE:
(TFL-099): ERROR The parent_file_name file has changed since the dependent
child_file_name file was created. Processing continues.
EXPLANATION:
There is a dependency relationship between the files listed, and one of these files has
been changed since the dependency was first established. This discrepancy is most
likely the result of some action performed by a user such as manually replacing one of
the files.
USER RESPONSE:
The discrepancy may be resolved by either restoring the files to their previous state, or
by removing the dependent data files. It is recommended that any data removal be
performed using Encounter Test function. For example, to remove failsets, one should
use the Encounter Test GUI, or the delete_failset command.
For the GUI, refer to Delete Failset in the Encounter Test: Reference: GUI.
For command line invocation, refer to "delete_failset in the Encounter Test:
Reference: Commands.
ERROR (TFL-100): Failed to disconnect the project from diagnostic database

specified_database_name. Project is currently connected to diagnostic database
connected_database_name.
EXPLANATION:
The project is currently not connected to the specified diagnostic database and therefore
no disconnection occurred. The message identifies the name of the currently connected
USER RESPONSE:
Rerun with the name of the currently connected diagnostic database specified.


ERROR (TFL-101): Migration of the following file could not be completed because existing
failsets dependent on this file are incompatible with the current version of Encounter Test:
file_name
EXPLANATION:
The indicated file was detected as back level and therefore considered for migration.
Also, one or more Scan Unload or Skewed Scan Unload events were detected in the
associated Encounter Test vectors. Since one or more existing failsets were detected
(created using a previous version of Encounter Test) and these are dependent on the
indicated file, migrating the file would render the failsets unusable. The migration was
therefore not performed.
USER RESPONSE:
Take one of the following courses of action:
Continue to use the previous version of Encounter Test.
Migrate the existing failsets using the current version. This can be
accomplished by writing the existing failsets using the previous version of
Encounter Test, then reading the resultant text files back into Encounter Test
using the current version.
ERROR (TFL-102): command unable to establish a flat model context.

EXPLANATION:
The flat model access methods returned an error return code. This will be preceded by
messages which further explain the problem.
USER RESPONSE:
Refer to preceding messages for further information.
ERROR (TFL-103): command unable to load the flat model.

EXPLANATION:
USER RESPONSE:

ERROR (TFL-104): command unable to load testmode TESTMODE.

EXPLANATION:
USER RESPONSE:
ERROR (TFL-105): command unable to load latch methods.

EXPLANATION:
USER RESPONSE:
ERROR (TFL-106): command unable to load failset FAILSET.

EXPLANATION:
The failure data access methods returned an error return code.
USER RESPONSE:
Refer to preceding messages and resolve the problem.
ERROR (TFL-107): command unable to sort failset FAILSET.

EXPLANATION:
The failure data access methods returned an error return code.
USER RESPONSE:
Refer to preceding messages and resolve the problem.
ERROR (TFL-108): command unable to close the flat model.

EXPLANATION:
The flat model access methods returned an error return code.
USER RESPONSE:

Information has been accessed from the flat model, but this error indicates that
something has gone wrong attempting to close the flat model. Refer to preceding
messages, and resolve the problem.
WARNING (TFL-109): Multiple Chip-Lot-Wafer records were specified for device device.
Only the first specification will be used.
EXPLANATION:
The indicated device appears in multiple Chip-Lot-Wafer records in the failures being
read. This ambiguity is resolved by accepting only the first specification.
USER RESPONSE:
If the first specification is not the intended one, ensure the indicated device is specified
in a single Chip-Lot-Wafer record and rerun.
WARNING (TFL-110): command is unable to close failset FAILSET.

EXPLANATION:
The failset has been successfully opened and accessed, but an error occurred when
closing the failset. If the failset is being created, the create was unsuccessful.
USER RESPONSE:
If the failset was being created, resolve the problem and repeat create task. Otherwise,
no response is required.
WARNING (TFL-111): The diagnostic clock gating file file_name was deleted, but could
not be unregistered. Processing continues.
EXPLANATION:
The data associated with the diagnostic clock gating resides in file file_name. This
information is registered in the globalData file. Normally, while attempting to delete the
clock gating file, Encounter Test will remove the registration information as well. In this
case, Encounter Test was unable to remove the registration information, either because
it never existed or because there was a problem updating the globalData file.
USER RESPONSE:
file.
WARNING (TFL-112): [Severe] File seek error while reading file file_name section
file_section_name. The system error code is error_number: error__text
EXPLANATION:

An error occurred while attempting to seek the specified file_section_name in the

specified file_name. The system error number and error text are included in the
message.
USER RESPONSE:
Attempt to resolve any obvious problem, and rerun the
prepare_diagnostic_clock_gating command with replace=yes specified. If
the problem persists, contact Cadence Customer Support (see Contacting Customer
Service on page 23) to report this error.
ERROR (TFL-113): Unable to create failset FAILSET.

EXPLANATION:
The desired failset could not be created. This message is preceded by additional detailed
messages related to this problem.
USER RESPONSE:
Refer to preceding messages, take any necessary corrective action, and then rerun.
WARNING (TFL-114): Input pattern pattern does not contain a measure event for device
device_name.
EXPLANATION:
The input failure references the indicated pattern. However the corresponding test vector
does not contain a measure event.
USER RESPONSE:
Ensure the input failure data corresponds to the test vectors and rerun.
INFO (TFL-115): Ignoring line line_number: Chip chip pad pad pattern pattern
offset offset value value
EXPLANATION:
This message is preceded by other messages providing more detail. Because of the
problem, the indicated failure will not be included in the failset.
USER RESPONSE:
WARNING (TFL-116): Input pattern number pattern does not contain a Scan Unload
event.

EXPLANATION:
The input failure references a scan latch measure for the indicated pattern, however, the
corresponding test vector does not contain a Scan Unload event.
USER RESPONSE:
Ensure the input failure data corresponds to the test vectors, and rerun.
INFO (TFL-117): Pattern pattern_number is an event_type event at location

experiment.procedure.section.loop.sequence.pattern.event.
EXPLANATION:
This message provides detail about the test vector associated with the indicated pattern.
USER RESPONSE:
WARNING (TFL-118): Unrecognized measured value of measured_value

EXPLANATION:
The input contains a measured value that was not recognized by Read Failures. An X
value will be used for the associated failure.
USER RESPONSE:
Correct the input and rerun.
WARNING (TFL-119): Error occurred while adding a failure to the failset.

EXPLANATION:
Encounter Test was unable to add a failure to the failset. This message is preceded by
messages other providing detail.
USER RESPONSE:
INFO (TFL-120): The diagnostics clock gating file will not be used because the
useclockgating keyword was specified.
EXPLANATION:
The developer keyword useclockgating was specified on this command line with a
value of no. The diagnostics clock gating information will not be used for this command.

All tracing will be performed with the pessimistic assumption that no clock gating exists
on the design.
USER RESPONSE:
No response is required assuming that the diagnostics clock gating information should
not be used. To use the diagnostic clock gating information, either remove the
useclockgating keyword, or specify a value of yes.
WARNING (TFL-121): [Severe] Scan_out pin pin_name does not exist in the design.
EXPLANATION:
The failure input includes one or more failures that reference the indicated scan-out pin.
However, this pin was not found in the design.
USER RESPONSE:
Either the failure input is not associated with this design, or the pin name in the failure
input is incorrect. If the failure input is not associated with this design, determine the
correct design, and rerun. If the pin name is incorrect, modify the failure input to correctly
identify the scan-out pin, and rerun.
ERROR (TFL-122): Value of scanenablereset used in

convert_vectors_to_smartscan could not be determined, the smartscan vector
conversion was done with pre - 13.1.100 release. Please redo the conversion with 13.1.100
or any subsequent versions of Encounter Test before running
convert_smartscan_failures.
EXPLANATION:
Value of scanenablereset keyword used in convert_vectors_to_smartscan
determines the type of Unload_SR event. Hence convert_smartscan_failures
should be aware of how the converted vectors were generated.
USER RESPONSE:
Run convert_vectors_to_smartscan with 13.1.100 or a post 13.1.100 version of
Encounter Test before running convert_smartscan_failures.
ERROR (TFL-123): The specified failset is created by the previous version of Encounter
Test and contains unsupported content. Processing ends.
EXPLANATION:
The failset specified to this command is created by previous version of Encounter Test.
This failset contains information that is unsupported by the current version and hence the
command could not proceed further.

USER RESPONSE:
Reimport the failures that were used to create the failset using read_failures and
proceed with diagnostics.
INFO (TFL-124): Logic failset FAILSET containing number_of_failures non-scan

failures is created with device name device.
EXPLANATION:
The specified FAILSET was created successfully.
USER RESPONSE:
INFO (TFL-125): A new device device with number_of_failures non-scan failures

has been added to the existing logic failset FAILSET.
EXPLANATION:
The specified device has been added to the the logic failset successfully.
USER RESPONSE:
WARNING (TFL-126): The specified logic device device exists in logic failset FAILSET.
The existing failures in this device are replaced with the newly identified
number_of_failures non-scan failures.
EXPLANATION:
The specified logic device exists in the logic failset specified. The program has identified
non-scan failures and these newly identified failures replace the existing failures in the
logic device.
USER RESPONSE:
WARNING (TFL-127): Failure specification ignored because Pin pin_name is not a scan-
out in the specified testmode. See succeeding message for details on the ignored failure.
EXPLANATION:
A failure specification includes the identified pin. While this pin was found in the
Encounter Test model, it was not identified as a scan-out in the specified testmode. The
failure specification identifies a scan event, but the pin is not a scan out pin. Therefore

the failure specification is ignored. This message should be followed by an additional

message with details of the ignored failure.
USER RESPONSE:
The most probable cause is that the specified testmode does not match the testmode
used when creating the test patterns from which this failure specification was derived. If
this is the case, rerun specifying the correct testmode.
ERROR (TFL-128): Deletion of the diagnostics clock gating file failed. The clock gating file
is in use.
EXPLANATION:
Encounter Diagnostics was requested to delete the diagnostic clock gating file. The
deletion could not be performed because the clock gating file is currently in use.
USER RESPONSE:
Wait until the clock gating file is no longer in use and then rerun.
ERROR (TFL-129): Could not delete the diagnostic clock gating file. Write permission could
not be obtained for file file_name.
EXPLANATION:
Encounter Test failed to obtain write permissions for the indicated file when attempting
to delete it.
USER RESPONSE:
Correct the file permissions and rerun.
WARNING (TFL-130): Failing device device_name has previously been partitioned, and
the diagnostic database has potentially been updated with results from the previous partition.
Since the number of partitions generated match the number of partitions previously
generated, the partitions are assumed to be equivalent. If this is not the case, the current
diagnostic database results are invalidated, and running diagnose_failset_logic on
the current partitions will produce invalid results as well.
EXPLANATION:
prepare_failset_partition has been previously run on the indicated device and
has generated the same number of partitions in both the current and the previous run.
While prepare_failset_partition has overwritten the output failset as it
regenerated the output failset, the assumption is that the current results are identical to
the previous results, and that no update to the diagnostic database is necessary as a

result of the current run. However, this assumption may be wrong because the number
of partitions may be the same, but the contents of each partition may be different.
USER RESPONSE:
No response is required unless it is known that the results of the current partitioning are
different from the results of the previous partitioning. When the results are different, reset
the database entries by reimporting the unpartitioned failures and rerun
prepare_failset_partition to produce valid database entries, then proceed using
diagnose_failset_logic.
WARNING (TFL-131): [Severe] Failing device device_name has previously been

partitioned into previous_partition_count partitions, and the diagnostic database
has been updated with the results from the previous partition. The current invocation of
prepare_failset_partition has produced current_partition_count
partitions and will not update the database. Subsequent invocations of
diagnose_failset_logic against the new partitions will not be allowed to update the
database.
EXPLANATION:
prepare_failset_partition has been previously run on the indicated device and
has produced different results. If the target failset is the same for the current and previous
invocations of prepare_failset_partition, the output failset is overwritten.
Because existing database entries are based on the previous partitioning, incorrect
database entries would result if the current partitioning was allowed to update the
database.
USER RESPONSE:
No response is required unless the current partitioning is preferred over the previous
partitioning. When the the current partitioning is preferred, reset the database entries by
reimporting the unpartitioned failures and rerun prepare_failset_partition to
produce valid database entries,then proceed using diagnose_failset_logic.
WARNING (TFL-132): [Severe] Could not read the diagnostics clock gating information
from file file_name due to failure to obtain a read lock.
EXPLANATION:
A diagnostics clock gating file exists, but a read lock could be obtained on this file, most
likely because some other process is writing to this file. Processing continues with the
pessimistic assumption that no clocks are gated.
USER RESPONSE:

If results are acceptable, no response is required. If the clock gating information is

required, wait for all prepare_diagnostics_clock_gating commands to
complete, and then rerun.
ERROR (TFL-133): Could not write the diagnostics clock gating file. Write permission could
not be obtained for file file_name.
EXPLANATION:
A diagnostics clock gating file exists, but this process does not have the permission
required to write to the specified file.
USER RESPONSE:
Determine why write permission is not available for the specified file, correct the problem,
and then rerun.
WARNING (TFL-134): [Severe] Could not read the diagnostics clock gating file. Read
permission could not be obtained for file file_name.
EXPLANATION:
A diagnostics clock gating file exists, but this process does not have the permission
required to read from the specified file. Processing continues with the pessimistic
assumption that no clocks are gated.
USER RESPONSE:
If results are acceptable, no response is required. If the clock gating information is
required, determine why read permission is not available for the specified file, correct the
problem, and then rerun.
ERROR (TFL-135): Could not write diagnostic clock gating information to file file_name,
attempting to write file_section_name because the maximum file size has been
reached.
EXPLANATION:
The diagnostic clock gating file is almost at its maximum file size of 4 gigabytes. Writing
new data to the file will exceed this limit. Processing will stop at this point.
USER RESPONSE:
No specific action is required. Invocatin of the prepare_diagnostic_clock_gating
command with the replace=yes option will continue to produce this message. It is
possible to rerun the prepare_diagnostic_clock_gating command with the
replace=yes option to delete the current clock gating file and collect clock gating
information for a different set of sequences.

INFO (TFL-136): Tracing was restricted because latchLevelsperpulse limit was

exceeded in trace_count traces.
EXPLANATION:
Tracing was suspended because the trace utility traced through more latches in a single
phase of a Pulse event than is allowed by the specification of keyword
latchlevelsperpulse. The default for latchlevelsperpulse is 1000 but the
keyword can be specified with an alternate value. Tracing is suspended only for the Pulse
event where the limit was reached.
USER RESPONSE:
No response is required. A possible action is to review the current setting of
latchlevelsperpulse and specify a different value. A lower
latchLevelsPerPulse value may significantly decrease runtime, but may also reduce
diagnostics accuracy. A lower setting of latchLevelsPerPulse is recommended
when this is consistent with the operation of the design because in this case, there is no
loss in diagnostics accuracy.
INFO (TFL-137): Start of failure data summary report:

EXPLANATION:
This report contains summary of failures for each device read by read_failures
command. Information on the below fields is listed for each device present in the failure
data file:
Number of failures
Number of failing logic sequences
Number of failing scan sequences (If non zero, defect is assumed to be in scan
chain)
Highest failing scan offset for last failing sequence (Indicates the failure data
collection limits)
Defect Type (Logic Defect/Scan Defect)
Chip Information (Availability of Lot name, Wafer name, Wafer Co-Ordinates)
Device Name
USER RESPONSE:
This message indicates a high level summary of the failures on a per device basis. It is
also helpful to understand the nature of defect present in the chip.

WARNING (TFL-139): [Severe] Failed to correlate

number_of_excluded_failures of number_of_total_failures failures to
the output vectors beginning at event odometer. These failures are excluded from failset
FAILSET.
EXPLANATION:
Simulation has detected miscompares and is attempting to generate a failset. One or
more of the failures could not be correlated to the output vectors, and as a consequence,
these failures will be excluded from the failset. The input vector file most likely contains
loop constructs. The generation of failsets has a limitation with respect to loop constructs.
Failures that occur after a loop is encountered cannot be correlated to the output vectors.
The resultant failset is truncated.
USER RESPONSE:
In cases where a small percentage of failures are excluded, the failset should be useful,
and this message can be ignored. Otherwise, a complete failset can be generated by
running insert_vector_pipeline_sequence on the input vectors to expand the
loops, and then running test simulation on the manipulated vectors.
INFO (TFL-140): Mapping failures from experiment from_experiment to experiment

to_experiment.
EXPLANATION:
This informational message indicates that failure mapping has started.
USER RESPONSE:
ERROR (TFL-141): Invalid or incorrect cross-reference information in experiment

experiment.
EXPLANATION:
In order to map failure data from one experiment to another, the to_experiment must
have key data attributes which define which events in the to_experiment were
mapped from the from_experiment. In this case, these key data attributes are either
missing, or contain incorrect values.
USER RESPONSE:
Check both the from_experiment and to_experiment to make sure that the
to_experiment was derived from the from_experiment. If it was, examine the
to_experiment and check the key data to make sure the cross-reference information

is correct If not, contact customer support (see Contacting Customer Service on

INFO (TFL-142): number_of_mapped_failures failures mapped from experiment

source_experiment to experiment target_experiment failset FAILSET.
EXPLANATION:
This informational message indicates successful failure mapping.
USER RESPONSE:
INFO (TFL-143): No experiment specified using committed vectors.

EXPLANATION:
This application operates on a vector set, which can either be the committed vectors or
an uncommitted set. When INEXPERIMENT is unspecified, the committed vectors are
used.
USER RESPONSE:
If the committed vectors are the correct choice, no response is required. Otherwise, rerun
specifying the correct INEXPERIMENT.
INFO (TFL-144): Traced through more than ten latch levels in a single Pulse event in
trace_count traces. Performance may be improved by specifying
latchLevelsPerPulse less than ten.
EXPLANATION:
While tracing back from a failure, more than ten levels of latches were traced through in
a single phase of a pulse. It is not likely that the user intended a single pulse to enable a
signal to pass through ten different latches (or five flip-flops). The long trace may result
in very slow diagnostic simulation performance, inability to create diagnostic partitions,
or degraded accuracy for scan chain diagnostics.
The default for latchlevelsperpulse is 1000, but a different value for
latchlevelsperpulse may be specified.
USER RESPONSE:
No response is required. A possible action is to review the current setting of
latchlevelsperpulse and specify a different value. Lower latchLevelsPerPulse
values may significantly decrease runtime, but may also reduce diagnostics accuracy. A

lower setting of latchLevelsPerPulse is recommended when this is consistent with

the operation of the design because in this case, there is no loss in diagnostics accuracy.
INFO (TFL-145): The test mode in which failure data is collected is identified as:
mode_type.
EXPLANATION:
Program has identified the specified mode by analyzing the failure data.
USER RESPONSE:
None.
WARNING (TFL-146): Input offset offset is less than the pipe line depth
pipe_line_depth_at_scan_out_pin at scan out pin scan_out_pin_name. This
failure is detected in internal pipeline and it will be ignored.
EXPLANATION:
The input failure references the indicated offset at given scan out pin (pad) lies in internal
pipe line. All failures detected in internal pipeline will be ignored. This message will be
reported, only for testmode with XOR compression.
USER RESPONSE:
Ensure the input failure data corresponds to the test vectors and rerun.
ERROR (TFL-147): Both databasedirectory and disconnect=no are not specified.

The setup information remains unchanged.
EXPLANATION:
The setup_volume_database command has been invoked with disconnect=no,
but no volume diagnostics database directory has been specified. The volume database
directory is required for all invocations of setup_volume_database other than
disconnects.
USER RESPONSE:
Rerun the setup_volume_database command specifying either disconnect=yes
if a disconnect is required, or specify databasedirectory=<directory name> if
not disconnecting.
INFO (TFL-148): The project has been disconnected from volume diagnostics database
database_name.
EXPLANATION:

The setup_volume_database command has been invoked with disconnect=yes.

Further invocations of analyze_volume_trends and Volume Analysis GUI will fail
since the project is disconnected to the volume diagnostics server.
USER RESPONSE:
No response is required if running diagnostics disconnected is desired. Otherwise to
reconnect this project to the volume diagnostics database, invoke the
setup_volume_database command.
WARNING (TFL-149): This project is not connected to a volume diagnostics database. The
attempt to disconnect was not successful.
EXPLANATION:
The setup_volume_database command has been invoked with disconnect=yes,
but this project was not connected to a volume diagnostics database. The project
remains disconnected from a volume diagnostics database.
USER RESPONSE:
Ensure the correct project has been specified and if not, re-specify the correct project
and re-run.
WARNING (TFL-150): [Severe] Inconsistent time and date information detected between
the design and the diagnostic database. Diagnostic database database_name will not be
updated.
EXPLANATION:
Encounter Test checks that the diagnostic database is compatible with the design by
verifying consistent time and date information. An inconsistency indicates a potential
incompatibility.
USER RESPONSE:
If the diagnostic database and design are incompatible, create a new diagnostic
database. Otherwise, specify overridediagnosticdatabase=yes and rerun.

INFO (TFL-151): File file_name content is recognized as failure_format failure
format.
EXPLANATION:
This informational message indicates the failure format is recognized by Read Failures.

USER RESPONSE:
ERROR (TFL-152): Failed to recognize the failure data format contained in file
file_name.
EXPLANATION:
Read Failures scans the import file to determine which format of failure data resides in
that file. In this case, the failure data format was not recognized.
USER RESPONSE:
Check the importfile specification to ensure it identifies a file containing failure data
in one of the formats recognized by Encounter Test.
ERROR (TFL-153): The backup of the diagnostic database failed. The project is not
connected to a diagnostic database.
EXPLANATION:
The request to backup the diagnostic database cannot be satisfied. This is likey because
a diagnostic database has not been specified for this project through Project Setup, or
the diagnostic database has been disconnected from the project.
USER RESPONSE:
Ensure that this project (WORKDIR) is connected to a diagnostic database, and that the
database server that manages that database is running correctly.
INFO (TFL-154): Read Failures scanning file file_name to determine the failure format.
EXPLANATION:
Read Failures is determining the failure format of the indicated file.
USER RESPONSE:
ERROR (TFL-155): Unable to read file file_name.

EXPLANATION:
Read Failures was unable to read the specified import file.
USER RESPONSE:

Check the file permission of the file specified through the importfile keyword. Obtain
read permission on the file, and rerun.
INFO (TFL-156): Diagnostic database diagnostic_database_name has been restored

from backup file file_name.
EXPLANATION:
The diagnostic database has been succesfully restored from the specified backup file.
Database updates and analysis will continue from the backed up database state.
USER RESPONSE:
ERROR (TFL-158): The back up of volume diagnostics database

diagnostic_database_name failed. No data is present in the database.
EXPLANATION:
The database connected to this project does not contain any data.
USER RESPONSE:
If data is expected in the volume diagnostics database, check to make sure the project
is connected to the expected database. If not, run setup_volume_database or use
the Project->Setup menu on the user interface to connect this project to the intended
diagnostic database, and rerun.
WARNING (TFL-160): Pin pin_name was not found in the Encounter Test model. Line
line_number of the importfile will be ignored.
EXPLANATION:
A failure description references a pin that does not exist in the Encounter Test model.
Therefore, this failure is not included in the failset.
USER RESPONSE:
position position value value
EXPLANATION:
This message is preceded by other messages providing more detail. Because of this

USER RESPONSE:
WARNING (TFL-162): Pin pin_name does not identify a measure location in the
Encounter Test model. Line line_number of the importfile will be ignored.
EXPLANATION:
A failure description references a pin that is not a valid measure location in the Encounter
Test model. Therefore, this failure is not included in the failset. A valid measure location
is either a Primary Output or a measurable latch.
USER RESPONSE:
ERROR (TFL-163): The back up of diagnostic database diagnostic_database_name

failed. Error in the generation of backup file.
EXPLANATION:
An error has been encountered while generating the backup file for the diagnostics
database.
USER RESPONSE:
See preceding messages, take necessary corrective action and then rerun.
ERROR (TFL-164): The back up of diagnostic database diagnostic_database_name

failed. Write permission could not be obtained for back up file file_name.
EXPLANATION:
This process does not have the permission required to write to the specified back up file.
USER RESPONSE:
Determine why write permission is not available for the specified file, correct the problem,
and rerun.
ERROR (TFL-165): The restore of the diagnostic database

diagnostic_database_name failed.
EXPLANATION:
An error has been encountered while restoring the diagnostic database from the backup
file database.
USER RESPONSE:

See preceding messages, take necessary corrective action and then rerun.
INFO (TFL-166): convert_smartscan_failures scanning file file_name to

determine the failure format.
EXPLANATION:
convert_smartscan_failures is determining the failure format of the indicated file.
USER RESPONSE:
INFO (TFL-167): The file containing converted failures is generated at path of file containing
converted failures.
EXPLANATION:
The message gives the path at which the converted failure file is generated
USER RESPONSE:
The smartscan failure file has been converted to respective XOR compression failure file.
User can proceed with diagnostics but he has to make sure experiment used for
diagnostics is the one which was generated by ATPG before conversion of vectors to
smartscan vectors.
Message severity INFO (TFL-168): SmartScan Failures Conversion Summary: failure

conversion stats End of SmartScan Failures Conversion Summary.
EXPLANATION:
Message contains the summary of conversion process.
USER RESPONSE:
Message contains the response based on it severity.
ERROR (TFL-169): Smartscan description file is not correct

EXPLANATION:
The file containing information for smartscan hardware is not correct.
USER RESPONSE:
Make sure the file which was used to convert XOR vectors to smartscan vectors is
provided to the command.
ERROR (TFL-170): The format of smartscan failure file could not be determined.

EXPLANATION:
The command currently supports CPP , STIL and TBD failure format. The importfile does
not have the data in the required format.
USER RESPONSE:
User should convert the failure file to CPP, STIL and TBD format. For more information
on the supported failure formats, refer to the Failure Data in Chip-Pad-Pattern (CPP)
Format in Encounter Test: Guide 7: Diagnostics.
WARNING (TFL-171): Few warnings or severe warnings occured while converting failures,
refer to earlier messages printed in the log for more information.
EXPLANATION:
Some failures were not converted properly due to syntax or some other problem
USER RESPONSE:
User can go through preceding warning messages in log file which tell why a particular
failure was not read.
INFO (TFL-172): Started the reporting of summary of failing chips.

EXPLANATION:
Informational message indicating the start of summary of failing chips.
USER RESPONSE:
ERROR (TFL-174): Failed to connect to the specified database name. The specified
database name database_name is already connected to design workdir.
EXPLANATION:
The specified database name is already in use for a different design and hence it can not
be used for the current design.
USER RESPONSE:
Specify a new database name if this is the first invocation of this command on this design.
If not, specify a valid database name and rerun.
ERROR (TFL-175): Invalid diagnostic database name, database_name specified. Name

cannot contain /, \\, or . characters. Respecify the diagnostic database name and rerun.
EXPLANATION:

A specified diagnostic database name cannot contain the UNIX or Windows pathname
separators, nor can it contain the . character because it is the separator used by the
diagnostic datatbase.
USER RESPONSE:
Respecify the database name and rerun.
message_severity (TFL-176): message_info
EXPLANATION:
The message indicates the presence of tester failures from multiple OPMISR unload
modes. Message severity (WARNING OR ERROR) is decided Internally by the program
based on various use cases.
USER RESPONSE:
Use readmisrfails keyword to filter failures from desired OPMISR unload modes.
INFO (TFL-177): Started reading volume files and populating volume diagnostic database.
EXPLANATION:
Informational message indicating the start of population of volume diagnostic database
from the volume files.
USER RESPONSE:
INFO (TFL-178): Completed reading volume files for number_of_chips runs and
populating volume volume diagnostics database. Volume analysis results from the command
line and from the GUI will be performed on the updated database. Execution Time:
loadtime_string
EXPLANATION:
Informational message indicating the completion of population of volume diagnostic
database from the volume files.
USER RESPONSE:
INFO (TFL-179): Report of categorization of failing chips by categorization_type.

EXPLANATION:

Informational message indicating the reporting of the failing chips based on the specified
categorization type.
USER RESPONSE:
INFO (TFL-181): Started the reporting of fail_callout_physical data analysis

results.
EXPLANATION:
Informational message indicating the start of specified data analysis results.
USER RESPONSE:
INFO (TFL-182): Completed the reporting of fail_callout_physical data analysis

results.
EXPLANATION:
Informational message indicating the completion of specified data analysis results.
USER RESPONSE:
INFO (TFL-183): No new volume files are available for updating the diagnostic database.
Volume analysis results will be reported on the current contents of diagnostic database.
EXPLANATION:
Informational message indicating the completion of processing the volume files. In this
case, the program could not find any new volume files to be updated into the diagnostic
database. Hence, the volume analysis results reported by this program are generated
from the current contents of the diagnostic database.
USER RESPONSE:
ERROR (TFL-184): Unable to find primary output associated with net net_name.
EXPLANATION:
A failure description references a net that either does not exist in the Encounter Test
model, or does not correspond to a Primary Output as expected. Therefore, this failure
is not included in the failset.

USER RESPONSE:
INFO ((TFL-185): number_removed of the number_requested failsets have been

removed.
EXPLANATION:
This Delete Failset summary indicates the number of failsets deleted.
USER RESPONSE:
ERROR (TFL-186): Failed to obtain a license for product product_name. Processing

ends.
EXPLANATION:
USER RESPONSE:
Ensure the availability of the required license then rerun.
INFO (TFL-187): Database schema was already created for the specified database name
database_name.
EXPLANATION:
The database schema was already created for the specified database name. This
happens when the setup_volume_database command was previously invoked with
the same database name. No action is performed by this current invocation of
setup_volume_database.
USER RESPONSE:
If the specified database name is incorrect or if you wish to create a new volume
diagnostics database for this design, rerun by specifying a different database name.
Otherwise, no response is required.
INFO (TFL-188): Failed to create database schema for the specified database name
database_name. See preceding error messages for corrective action.
EXPLANATION:

The database schema for the specified database name could not be created. This
message is accompanied by error messages containing the source of the problem.
USER RESPONSE:
Check the preceding messages containing the information that caused this error
condition. Take a corrective action and rerun.
INFO (TFL-189): Database schema is successfully created for the specified database name
database_name.
EXPLANATION:
The database schema is successfully generated. You can proceed to next step in volume
diagnostics and run using analyze_volume_trends command.
USER RESPONSE:
INFO (TFL-190): Successfully created faildata volume files for num_devices devices. You
can now run analyze_volume_trends to perform volume analysis.
EXPLANATION:
The faildata volume analysis files have been generated.
USER RESPONSE:
Proceed to volume analysis using analyze_volume_diagnostics command or
Encounter Test GUI.
WARNING (TFL-191): [Severe] Failset FAILSET has not been deleted. See preceding
messages for details.
EXPLANATION:
An error occurred while deleting the indicated failset. This message is preceded by other
messages providing more detail.
USER RESPONSE:
Reffer to the preceding messages, take any necessary corrective action, and then rerun.
INFO (TFL-192): Failset FAILSET has been deleted.

EXPLANATION:
The indicated failset was successfully deleted.

USER RESPONSE:
INFO (TFL-193): Copying device device from failset source_FAILSET to failset

target_FAILSET.
EXPLANATION:
This informational message indicates the copy of the indicated device.
USER RESPONSE:
INFO (TFL-194): Device device does not exist in failset FAILSET.

EXPLANATION:
This informational message indicates that the device does not exist in the indicated
failset.
USER RESPONSE:
INFO (TFL-195): Deleting device device from failset FAILSET.

EXPLANATION:
This informational message indicates the deletion of the indicated device.
USER RESPONSE:
ERROR (TFL-196): The design contains XOR compression MSS , multiscanfile needs
to be specified for converting MSS failures.
EXPLANATION:
The design contains XOR compression MSS , multiscanfile needs to be specified
for converting MSS failures. This is the same file which is provided for converting XOR
patterns to multiscan patterns.
USER RESPONSE:
Provide multiscanfile and rerun the command.

INFO (TFL-197): The devices specified for removal encompass all of the devices in the
failset. The entire failset will be deleted.
EXPLANATION:
The failset is deleted because the removal of all devices in the failset results in an empty
failset.
USER RESPONSE:
INFO (TFL-198): Target failset FAILSET does not exist. It will be created.
EXPLANATION:
This informational message indicates that the edit_failset_devices needs to
create the target FAILSET.
USER RESPONSE:
ERROR (TFL-199): The source and target failset names cannot be the same.
EXPLANATION:
edit_failset_devices does not allow the source and target failset names to be the
same.
USER RESPONSE:
Respecify either failset, and rerun.
INFO (TFL-200): Specified devices already exist in the target failset and neither append (-
a) nor replace (-r) was specified. Processing ends.
EXPLANATION:
edit_failset_devices has determined the specified devices already exist in the
target FAILSET and cannot determine how to proceed. The specific devices are
identified in the preceding messages.
USER RESPONSE:
Specify either append or replace option and rerun.
INFO (TFL-201): Specify either append (_a) or replace (_r), but not both.
EXPLANATION:

edit_failset_devices does not allow you to specify both append and replace
options.
USER RESPONSE:
Specify either the append or replace option and rerun.
INFO (TFL-202): The copy will not be performed.

EXPLANATION:
edit_failset_devices encountered a condition that prevents the copying of
devices. This message is preceded by other messages providing more detail.
USER RESPONSE:
INFO (TFL-203): The move will not be performed.

EXPLANATION:
edit_failset_devices encountered a condition that prevents the moving of devices.
This message is preceded by other messages providing more detail.
USER RESPONSE:
INFO (TFL-204): Device device already exists in failset FAILSET.

EXPLANATION:
edit_failset_devices has determined the indicated device already exists in the
target failset.
USER RESPONSE:
WARNING (TFL-205): Reason why a particular failure was ignored for

the conversion process.
EXPLANATION:
USER RESPONSE:
User should ensure that warnings are valid and try to minimize them.

WARNING (TFL-206): Multiscan keyword has been specified for FULLSCAN MSS mode,
since it is not needed it will be ignored.
EXPLANATION:
There is no conversion of patterns in FULLSCAN MSS mode therefore multiscan
information is not required by the command. The conversion process will continue but
the file will not be read and used.
USER RESPONSE:
User should ensure no multiscanfile is provided for conversion of failures in
FULLSCAN MSS mode.
ERROR (TFL-207): Merge String not specified.

EXPLANATION:
The Merge String is a required argument to the program, and was not specified. The
program terminates.
USER RESPONSE:
Specify merge=regular_expression and rerun.
WARNING (TFL-208): Warnings for failures which are not ignored but
have some anomalies.
EXPLANATION:
USER RESPONSE:
User should ensure that warnings are valid and try to minimize them.
WARNING (TFL-209): Writing new converted failure file Converted_Failure_File

but the file already exists. The file will be overwritten.
EXPLANATION:
While writing the converted failure data to the indicated file, it was detected that the file
already exists. The existing file will be replaced with the contents of the new file.
USER RESPONSE:
INFO (TFL-210): Merging device device.

EXPLANATION:
Informational message indicating the name of the device being merged.
USER RESPONSE:
WARNING (TFL-211): [Severe] No device names matched the merge specification of

merge_specification. Processing ends.
EXPLANATION:
The specified failset contains no devices that match the merge specification. Therefore,
no devices are merged.
USER RESPONSE:
INFO (TFL-212): merged_device_count devices merged into device

merge_string_argument
EXPLANATION:
Informational message summarizing the devices that were merged.
USER RESPONSE:
INFO (TFL-213): Writing logic failures in to failset device device FAILSET, but the device
already exists. The failures associated with this device will be replaced.
EXPLANATION:
The program has identified non-scan failures and these failures will be added in to the
failset and device specified. The device specified already exists and the failures
associated with this device will be replaced with the non-scan failures.
USER RESPONSE:
message_severity (TFL-214): Multiscan Failures Conversion Summary:

failure_conversion_statsn End of Multiscan Failures Conversion Summary.
EXPLANATION:
Message contains the summary of conversion process.

USER RESPONSE:
Message contains the response based on it severity.
WARNING (TFL-215): Offset value of offset_value exceeds the scan chain length. The
scan chain associated with scanout pin pin_name has a length of scan_chain_length.
EXPLANATION:
The input failure references the indicated pin and offset, however, the corresponding
scan chain length is less than the offset. The failure is not added to the failset.
USER RESPONSE:
WARNING (TFL-216): Cycle offset and observed data exceeds chain length by
amount_exceeding_scan_chain_length. The scan chain associated with scanout
pin pin_name has a length of scan_chain_length.
EXPLANATION:
The input failure references the indicated pin and offset, however, the corresponding
scan chain length is less than the offset. The failure is not added to the failset.
USER RESPONSE:
WARNING (TFL-217): Line line_number of the importfile will be ignored.

EXPLANATION:
The indicated line number in the importfile will be ignored. This message is preceded
by other messages which fully explain the cause.
USER RESPONSE:
ERROR (TFL-218): No FAILSET created.

number_of_lines_read specifications read number_of_lines_failed failed
number_of_lines_ignored ignored
EXPLANATION:
The specified failset was not created.
USER RESPONSE:

Refer to accompanying messages, resolve the problem, and rerun.
WARNING (TFL-219): Pad name pad_name could not be found in the Encounter Test
model. Line line_number of the importfile will be ignored.
EXPLANATION:
The input describes a failure associated with the specified pad. However, the associated
pin name does not appear in the Encounter Test model. Therefore, the failure is not
added to the failset.
USER RESPONSE:
value value
EXPLANATION:
This message is preceded by other messages providing more detail. Because of this
USER RESPONSE:
WARNING (TFL-221): Pattern pattern contains an unrecognized measure event type.

EXPLANATION:
The indicated pattern references an unrecognized measure event type.
USER RESPONSE:
WARNING (TFL-222): Pattern pattern contains a measure PO event which conflicts with
the specified offset.
EXPLANATION:
The indicated pattern references a Measure PO event which conflicts with the specified
offset.
USER RESPONSE:

WARNING (TFL-223): Pattern pattern contains a Scan Unload event which conflicts with
the specified offset.
EXPLANATION:
The indicated pattern references a Scan Unload event which conflicts with the specified
offset.
USER RESPONSE:
WARNING (TFL-224): The test vectors are incompatible with this version of Encounter Test.
EXPLANATION:
The test vectors are incompatible with the version of Encounter Test being used.
USER RESPONSE:
Run TBDmigrate with the -w to migrate the test vectors to the current version of
Encounter Test, and then rerun.
WARNING (TFL-225): Pattern pattern contains a Compressed Output Stream event

which conflicts with the offset specification.
EXPLANATION:
The pattern specification references a Compressed Output Stream event. This is
inconsistent with the corresponding offset specification of -1, which should be used
only in conjunction with a Measure PO event.
USER RESPONSE:
Refer to the subsequent message which identifies the incorrect failure specification.
Either modify the pattern in that specification to identify one which contains a Measure
PO event, or modify the offset specification so it applies to the Compressed Output
Stream event, and rerun.
WARNING (TFL-226): Pattern pattern contains a Scan Unload event but the testmode
expects scan measures only on Compressed Output Stream events.
EXPLANATION:
The pattern specification references a Scan Unload event. This conflicts with the
testmode which specifies linear compression. All failing measures for such a testmode
should occur in either Compressed Output Stream or Measure PO events.
USER RESPONSE:

See the subsequent message which identifies the incorrect failure specification. Modify
the pattern in that specification to identify one which contains a Compressed Output
Stream event, and rerun.
WARNING (TFL-227): Pattern pattern contains a Compressed Output Stream event but
the testmode does not support linear output compression.
EXPLANATION:
The pattern specification references a Compressed Output Stream event. This conflicts
with the testmode which does not specify linear compression. All failing measures for
such a testmode should occur in either Scan Unload or Measure PO events.
USER RESPONSE:
the pattern in that specification to identify one which contains a Scan Unload event, and
rerun.
WARNING (TFL-228): Pattern pattern does not contain a Compressed Output Stream
event.
EXPLANATION:
The pattern specification references a pattern that does not contain a Compressed
Output Stream event. The testmode specifies linear compression, therefore all failing
scan measures should occur in Compressed Output Stream events.
USER RESPONSE:
the pattern in that specification to identify one which contains a
Compressed_Output_Stream event, and rerun.
WARNING (TFL-231): [Severe] Unable to open alternate fault model

fault_model_name.
EXPLANATION:
The specified alternate fault model could not be opened. This will be preceded by
USER RESPONSE:
INFO (TFL-232): Started the reporting of the Volume Database statistics.

EXPLANATION:

Informational message indicating the start of the Volume Database statistics report.
USER RESPONSE:
INFO (TFL-233): End of reporting of the Volume Database satistics. Execution Time:
timestring_summary
EXPLANATION:
Informational message indicating the completion of reporting of the Volume Database
statistics.
USER RESPONSE:
WARNING (TFL-234): [Severe] The following failure was rejected - reason

failure
EXPLANATION:
A program was unsuccessful adding failure information to FAILSET for the reason
stated. This error is an indication that the input failure data is either inconsistent with the
vector data, or contains an invalid device name. The problem lies in the construction of
the input failure data.
USER RESPONSE:
Modify the input failure data to resolve the conflict and rerun.
WARNING (TFL-235 ) [Severe] The following failure was rejected - expected vector value
of X causes failure to be ignored. failure
EXPLANATION:
A program attempted to add failure information to FAILSET, but the expected value
defined in the vector data for the associated measure is X. This failure will not be added
to the failset.
USER RESPONSE:
This condition should not occur. This could happen due to an error in the fail data
collection at the tester or due to an error in the fail data translation process that converts
tester logs to Encounter Test supported fail data format. This error has to be debugged
to avoid unreliable diagnostics results on this failset.

ERROR (TFL-236): The specified directory name directory_name is not a valid volume
diagnostics database directory. Processing Ends.
EXPLANATION:
The program requires a valid volume diagnostics database directory to proceed.
Inspection of the specified database directory is performed to ensure the specified
directory is created by the start_volume_server command. The inspection process
checks for some files and contents of the directory that have to exist if the directory is
created by start_volume_server command. In this case, this checking failed
indicating that the directory is not created by start_volume_server command.
Hence, the processing ends.
USER RESPONSE:
Rerun the command with a valid volume diagnostics database directory created by
INFO (TFL-237): Failures associated with device device are not read due to the device
keyword specification.
EXPLANATION:
When the device keyword is used, Read Failures processes only failures associated
with the device keyword specification. Failures associated with the indicated device are
not read.
USER RESPONSE:
ERROR (TFL-240): Could not find the volume database directory for the design.Run
start_volume_server, followed by setup_volume_database to create and register a
database directory with the design if you have not already done so.
EXPLANATION:
The volume database directory is created by the start_volume_database
command. The directory is registered with the design by the
setup_volume_database command. In this case, it was either not created or was not
registered by running setup_volume_database.
USER RESPONSE:

ERROR (TFL-241): Could not determine the volume diagnostics database name to which
the design is connected. Run setup_volume_database to create a volume diagnostics
database and register it with the desgin.
EXPLANATION:
The volume diagnostics database name is used to locate the data for volume analysis. It
is created and registered with the design by the setup_volume_database command.
In this case, a database name registered with the design could not be found.
USER RESPONSE:
INFO (TFL-242): Connected to volume diagnostics database server host_name on port

port_number for database name database_name.
EXPLANATION:
The volume diagnostics database server and database name is used to perform volume
diagnostics.
USER RESPONSE:
INFO (TFL-247): Printing selection query Report

EXPLANATION:
Information message from analyze_volume_trends
USER RESPONSE:
WARNING (TFL-249): Added failure on MISR flop flop_name to the failset. Failure:
failure_detail
EXPLANATION:
The indicated failure is detected on a MISR flop and added to the FAILSET. $ Failures
are usually expected on scan-flops during scan chain unload process. $ In this case, the
indicated failure is detected on a MISR flop. This failure $ is still added to the FAILSET
and usual diagnosis is performed on these failures. $ This warning message aids in
flagging these fails for user's further analysis.
USER RESPONSE:
No response is required if this condition is expected.

INFO (TFL-250): The pattern cross reference file pattern_cross_reference_file

is out of sync with the pattern database file pattern_database_file. Existing pattern
cross reference file is removed and rebuilt according to the new pattern information.
EXPLANATION:
This scenario could occur in 2 cases:
a. User has copied a new ET pattern database file over the existing pattern database
file.
b. The patterns have been modified since the existing pattern cross reference file was
created.
USER RESPONSE:
No response is required as pattern cross reference file is updated automatically.
ERROR (TFL-251): The parent_file_name file has changed since the dependent
child_file_name file was created. Automatic update of dependecy file is not allowed
since the FAILSET is opened in append mode. Processing Ends. [end TFL_251] \n\n
EXPLANATION:
There is a dependency relationship between the files listed, and one of these files has
been changed since the dependency was first established. This discrepancy is most
likely the result of some action performed by a user such as manually replacing one of
the files. Usually, the dependecy file file is updated to sync it with the contents of the
parent file. In this case, the FAILSET which is in append mode, already contains failures
created from previous invocations of this commands. Adding new failures in the failset
may lead to failures synchronizing with the two versions of the parent file. This may
corrupt the older failures present in the FAILSET. To prevent thisccident, processing ends
without updating dependency file to newer version of parent file.
USER RESPONSE:
The discrepancy may be resolved by either restoring the files to their previous state, or
by removing the dependent data files. It is recommended that any data removal be
performed using Encounter Test commands. For example, to remove failsets, one should
use the Encounter Test Graphical User Interface, or the delete_failset command.
If user wants to perform this command invocation in append mode, user has to write
failures of FAILSET with older parent file and rerun this command invocation in write
mode.
INFO (TFL-252): This FAILSET contains failure data collected from below unload modes:
list_of_misr_unload_modes_present_in_failset.

The program will only read MISR failures unloaded in FULLSCAN mode due to
readmisrfails=auto specification.
EXPLANATION:
With readmisrfails=auto specification, following is the behavior:
For FAILSETs with just one mode of failures, all the failures will be processed.
When there are failures from multiples unload modes, only the failures unloaded in
FULLSCAN mode will be processed.
USER RESPONSE:
No response is required if user intends to process the failures unloaded in FULLSCAN
mode. For processing failures from other modes, rerun the command with appropriate
option for readmisrfails keyword.
INFO (TFL-253): The failset contains unsupported failures collected on diagnostics

patterns. The program will filter unsupported failures.
EXPLANATION:
The failset contains failures collected on normal diagnostics patterns (non xor segment
scan patterns, such as logic tests and scan pattern tests). The program does not support
these type of failures. It supports failures from xor segment scan patterns and will filter
out all unsupported failures.
USER RESPONSE:
Run respective diagnostics command to perform diagnostics on unsupported failures or
filter them out manully with different device name and re-run diagnostics command on
them.
INFO (TFL-254): The failset contains unsupported failures collected on xor segment scan
patterns. The program will filter unsupported failures.
EXPLANATION:
The failset contains failures collected on xor segment scan patterns (special patterns
created by create_diag_tests_scanchain_xorsegments command invocation.
The program does not support these type of failures. It supports failures from scan and
logic patterns and will filter out all unsupported failures.
USER RESPONSE:
Run diagnose_failset_scanchain_xorsegments command to perform
diagnostics on unsupported failures or filter them out manully with different device name
and re-run diagnostic command on them.

INFO (TFL-255): Successfully initialized MISR to scan flop correspondence information.

Time used CPU_time/elapsed_time.
EXPLANATION:
Informational message indicates the successfull initilization of MISR to scan flop
correspondence information. This correspondence infromation is used during fault
selection and fault simulation.
USER RESPONSE:
WARNING (TFL-257): Pin pin_name was not a pin on measure latch in the Encounter Test
model. Line line_number of the importfile will be ignored.
EXPLANATION:
A failure description references a pin that was not a measure latch pin in the Encounter
Test model. In TBDfail (ASCII) format, pin name is allowed at measure latch location for
non measure_po event. Therefore, this failure is not included in the failset.
USER RESPONSE:

ERROR (TFL-323): The specified binary failure file is not present in the Encounter Test
database directory. Processing Ends.
EXPLANATION:
You are currently importing the binary failure file using read_failures process. This
is not a standard use-model and it is not recommended. To import the binary failure files
using read_failures, following process must be followed:
a. Copy the TBDfail into the Encounter Test database directory (tdbata). Let's say the
TESTMODE is FULLSCAN and FAILSET name is FAILS_DESIGN_X. The TBDfail
name will be TBDfail.FULLSCAN.FAILS_DESIGN_X.gz and this file has to be
copied into the tbdata directory.
b. Run read_failures command. Example:- read_failures TESTMODE=WAFER_OPP

FAILSET=FAILS_DESIGN_X importfile=./tbdata/
TBDfail.FULLSCAN.FAILS_DESIGN_X.gz
USER RESPONSE:

Copy or move the binary TBDfail file into Encounter Test database directory and rerun
the command with the new path of the TBDfail file.
INFO (TFL-324): Start of testmode and design information report.

EXPLANATION:
Informational message indicating the start of specified report.
USER RESPONSE:
WARNING (TFL-341): [Severe] A scan operation sequence does not exist. Assuming a
standard scan clocking scheme.
EXPLANATION:
A scan operation sequence is typically defined when a testmode is built. However
because a scan operation sequence is not present, it is assumed that all Primary Inputs
flagged with the AC attribute are skewed load clocks, all Primary Inputs flagged with the
BC attribute are skewed unload clocks, and all Primary Inputs flagged with AC, BC, or
EC attributes are scan clocks.
USER RESPONSE:
No response is required if the outlined assumptions are valid. Otherwise, rebuild the
testmode specifying a valid scan operation sequence and then rerun.
ERROR (TFL-342): Unable to find the last pattern in the scan_sequence_type

sequence.
EXPLANATION:
In order to trace back from a failure, the trace routine must understand which clocks will
get pulsed during the scan load and unload events. This information is determined from
the scan operations in the TBDseq file. A scan operation sequence was found, but
contained no patterns.
USER RESPONSE:
Rebuild the testmode to reinitialize the TBDseq file.
ERROR (TFL-343): Unable to find the last event in the scan_sequence_type

sequence.
EXPLANATION:

In order to trace back from a failure, it is required to understand which clocks will get
pulsed during the scan load and unload events. This information is determined from the
scan operations in the TBDseq file. A scan operation sequence was found which
contains one or more patterns, but a pattern was found with no events.
USER RESPONSE:
Rebuild the testmode to reinitialize the TBDseq file.
WARNING (TFL-344): Tracing detected scan_sequence_type event at odometer-

this event type is ignored. Results of tracing may be suspect.
EXPLANATION:
Stimulate Clock events are unexpected because they allow clocks to be out of stability
other than during Pulse events. Processing continues with the assumption that clocks
have not been stimulated, and remain at their stability value unless pulsed. While this
assumption is generally valid, results may be suspect.
USER RESPONSE:
No response is required if results are valid. Otherwise, you can avoid this message by
rerunning with a testrange that excludes the tests containing Stimulate Clock events.
INFO (TFL-350): Tracing was restricted because pulselimit was exceeded at

event_type event odometer.
EXPLANATION:
The trace routine was called with a pulselimit, and that pulselimit was reached. Back
tracing is discontinued.
USER RESPONSE:
No response is required. To include more logic in the back cone trace, increase the value
for pulselimit.
ERROR (TFL-351): Unable to update the diagnostic database for partitions because wafer
information for the source die could not be found for device device.
EXPLANATION:
The program attempted to partition a specific device in a failset and update the diagnostic
database for the results of that partition. This was not completed because the diagnostic
database does not contain lot, wafer, waferx, wafery information for the source failset and
device.
USER RESPONSE:

Either reimport the source failset to update the diagnostic database for the source, or run
the partition process with keyword value updatediagnosticdatabase=no to prevent
attempts to update the diagnostic database for the partition.
INFO (TFL-352): The volume diagnostics server is running and ready for use.
EXPLANATION:
The volume diagnostics server has been started. The start_volume_server
command will continue to run until the server is stopped using stop_volume_server
command.
USER RESPONSE:
ERROR (TFL-358): The host on which the PostgreSQL database has been started is
server_host and is different from the host on which stop_volume_server is invoked.
Program terminates.
EXPLANATION:
To stop a PostgreSQL server, the stop_volume_server command must be invoked
from the same host server that the start_volume_server was invoked. In this case,
the host names differ and caused the program to terminate.
USER RESPONSE:
Log in to the hostname specified and set the Encounter Test environment and rerun the
command.
WARNING (TFL-359): [Severe] Unable to read volume diagnostics server access

information from the directory database_dir_name. The volume diagnostics database
will not be updated.
EXPLANATION:
The files necessary for accessing the volume diagnostics database volume server file
could not be read . This prevents the program from connecting to the volume diagnostics
database and updating the database.
USER RESPONSE:
Make sure that the volume database directory is properly created by the
start_volume_server command and that you have read permissions on it.

ERROR (TFL-360): Failed to start the diagnostic database server. Read the extended help
for possible causes of the problem.
EXPLANATION:
The instantiation of the database server failed. Subsequently, no volume diagnostic data
will be stored in the database. This could be probably because of the following reasons:
A database server is already running on this machine. Run ps -ef | grep
postmaster to check if a diagnostic database server is already running. If you find
any of the above processes running under you name or some other user's name,
the database server cannot be started on the machine. The volume diagnostics
methodology allows only one database server to be running on a machine. If
another database server is running, this server needs to be stopped if you wish to
start a new database server on this machine else rerun this command on a different
machine so that a new database server is created on that machine.
If the database server is manually killed using system kill command, a residual
hidden file with the name .s.PGSQL.5432.lock will be left out in the /tmp
directory. If this file is not removed after killing the database server with kill
command, this will not allow other users to start a database server. Remove this file
if present in the /tmp directory and rerun the command.
Check the hard drive space and make sure sufficient space is available.
RESPONSE:
Check for any possible causes mentioned in the explanation section and take necessary
corrective action.
INFO (TFL-361): Volume Diagnostics Server Information:

Host Name : hostname
Port Number : serverport
Database Directory: databasedirectory
EXPLANATION:
Informational message containing the details of volume diagnostics server host name
and database directory.
USER RESPONSE:
None. Save the details reported in the message for future reference.
ERROR (TFL-362): Cannot restart server on this machine since a volume server is already
running on this machine.
EXPLANATION:

The volume server file specification identifies a volume diagnostics server that is already
running on the indicated host. The Volume Diagnostics solution supports invoking a
single server on a single host name.
USER RESPONSE:
If you are the owner of the volume diagnostics server that is current running on the host,
it is recommended not to start a new server. If you are not the owner of the volume
diagnostics server that is current running on the host, log in to a different host and rerun
the command.
ERROR (TFL-363): Failed to stop the volume diagnostics server on host server_name
and port port_number for the specified database directory database_name.
EXPLANATION:
An error was detected when attempting to stop the server on the indicated host and port
for the indicated database. The operation being attempted against the volume
diagnostics database cannot be completed. Ensure that the server is running with the
specified database directory on current host.
USER RESPONSE:
Check that the volume diagnostics server is running on the specified machine with the
specified database directory and rerun.
ERROR (TFL-364): The specified directory name database_directory already exists

and it is not a valid volume diagnostics database directory. Processing Ends.
EXPLANATION:
If you are starting the server for the first time, you have to specify a directory name that
does not exist or you can make the directory yourself and specify this directory name
which does not have any files in it. If you are restarting the server, you have to specify a
directory name that was created by previous successful invocation of
start_volume_server command. In this case, you specified a directory that exists
and it contains other files that do not belong to volume diagnostics database.
USER RESPONSE:
If you are starting the server for the first time, specify a directory which does not exist or
an empty directory, then rerun the command. If you are restarting the server, rerun the
command with a directory that is created by previous successful invocation of
INFO (TFL-702): Report of failures and sequences selected for requested devices:

EXPLANATION:
Informational message indicating the start of fail data selection report for selected failing
devices. All the devices that are requested to be processed by the user and marked as
failing in the input FAILSET will be reported.
USER RESPONSE:
End of report of failures and sequences for requested devices. Time used CPU_time/
elapsed_time.
EXPLANATION:
Informational message indicating the completion of fail data selection report for
requested failing devices.
USER RESPONSE:
ERROR (TFL-708): No device specifications found in the device control file. Processing
Ends.
EXPLANATION:
After parsing the device control file, the program has identified that there are no devices
specified in the device control file. Hence, the processing ended.
USER RESPONSE:
Specify the devices of interest in the device control file and rerun the command. If you
wish to diagnose all the failing devices in the FAILSET, rerun the command by removing
the devicecontrolfile specification.
WARNING (TFL-709): Multiple entries for device device_name are present in device
control file. Last entry for the device will be taken as actual user request.
EXPLANATION:
Multiple entries for given device are present in device control file. All the remaining
keywords related to the given device will be reset to the last given option for the device.
Multiple entries for device in device control file may lead to some confusion in user's mind
for actual option taken by program for given device.
USER RESPONSE:
Remove multiple entries for device in device control file and rerun diagnostics.

WARNING (TFL-710): The device device_name specified in device control file is not
present in the FAILSET. Hence, the device specification associated with this device is
ignored.
EXPLANATION:
The report device does not exist in the FAILSET and hence this device could not be
diagnosed in this run.
USER RESPONSE:
If you do not want to diagnose the reported device, no response is required. If the device
name reported is spelled incorrectly, update the device control file with a correct device
name and rerun.
WARNING (TFL-711): The device device_name specified in device_control_file

|failset failed the scan integrity test. Hence, this device can not be diagnosed by this
command.
EXPLANATION:
This command can diagnose the failing devices which pass the scan integrity test. In this
case, the reported device failed the scan integrity test and hence this device specification
is ignored.
USER RESPONSE:
To diagnose the reported device, run diagnose_failset_scanchain command. To
avoid this warning message in subsequent runs, remove the devices that fail the scan
integrity test in the device control file.
WARNING (TFL-712): Multiple entries of keyword keyword are specified for device
device_name in device control file. Last specification will be used as the user requested
specification for this keyword.
EXPLANATION:
Multiple entries of reported keyword are specified for reported device. In this case,
program will treat the last specification of this keyword as user requested specification.
USER RESPONSE:
If the last specification is the specification you intended to specify to the program, no
response is required. Otherwise, update the device control with the valid specification
and re-run. In general, specify a single valid specification for each keyword in each
device specification.

WARNING (TFL-713): [Severe] The device name device_name already exists in

FAILSET failset_name. The new failures for this device will not be appended to the
FAILSET.
EXPLANATION:
The given device name already exists in the given FAILSET. The new failures for this
device will not be appended to the FAILSET.
USER RESPONSE:
WARNING (TFL-714): Writing new failures for failset FAILSET into file file_name, but
the file already exists and append=yes is specified. The file will be appended.
EXPLANATION:
While writing failure data for FAILSET to the indicated file, it was detected that the file
already exists and append=yes is specified. The failure data in this file will be
appended.
USER RESPONSE:
INFO (TFL-715): Failset FAILSET updated containing number_of_failiures failures

on number_of_devices device s read_details
EXPLANATION:
The specified failset was opened in append mode and updated successfully.
USER RESPONSE:
INFO (TFL-716): A subset of resultant_number_of_failures failures has been

selected from the total set of total_number_of_failures failures, by the
device_specification|testrange_specification specification for the device
device_name.
EXPLANATION:
The current device and/or testrange specification has resulted in a subset of the failures
to be processed.
USER RESPONSE:

WARNING (TFL-717): Device device_name specified in device control file is ignored

because it has no failures present in failset.
EXPLANATION:
The user has specified a device in device control file, which is a valid and recognised
device in failset. But it has no failures present in failset. Ignoring this device in device
selection summary. This may happen, when a user specified a volume information of
given device with no failure data or when all of the failures regarding given device ignored
during read_failures.
USER RESPONSE:
Remove these devices from the device control file. and rerun
diagnose_failset_logic.
ERROR (TFL-718): Unable to proceed when no devices are selected.

EXPLANATION:
Terminating message indicating there are no devices selected for multiple device
diagnostics simulation. This can occur when:
no or invalid devices are given
testrange specification filter out all failures
USER RESPONSE:
Examine testrange, device specifications in device control file and make necessary
corrections.
ERROR (TFL-726): The testmode contains multiple active migrated core instances. The
coreinstance=migrated_core_instance_value specification has invalid value.
Program ends.
EXPLANATION:
The testmode contains multiple active migrated core instances. User has specfied invalid
core instance through coreinstance keyword specification.
USER RESPONSE:
Specify a valid core instance value to the 'coreinstance' keyword and rerun.
ERROR (TFL-727): The testmode contains multiple active migrated core instances. Specify
coreinstance keyword to select a core instance. Program ends.
EXPLANATION:

The testmode contains multiple active migrated core instances. The program needs $ a
coreinstance keyword specification to select any one core instance.
USER RESPONSE:
Specify coreinstance keyword specification with a valid core instance value and
rerun.
ERROR (TFL-998): [Internal] An unexpected condition occurred in the diagnostic clock

gating processing code. Contact Cadence Customer Support to report this error and give
them the following information:
An error occurred on line line_number of source file file_name:

variable_text
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TFL-999): [Internal] An unexpected condition occurred in the Encounter Test

failure data processing code.
information:
An error occurred on line line_number of source file file_name

EXPLANATION:
USER RESPONSE:

Contact the customer support team using your normal process; Cadence online
customer support, email, or direct call to the customer support line, and provide the
complete text of the message. This will allow the programmer to find and fix the problem
more quickly.
customer support.

30
TFM - Fault Model Messages
TFM-002 through TFM-050 on page 1015

TFM-002 through TFM-050

WARNING (TFM-002): [Severe] Dynamic memory allocation problem.
EXPLANATION:
There was a problem allocating enough memory to run the fault model application.
USER RESPONSE:
If the workstation where the application was running is loaded with other
processing, wait and rerun the fault model application when there is more
memory available.
If the workstation where the application was running does not have more
memory available, run the fault model application on a different workstation.
WARNING (TFM-003): [Severe] Fault model file filename does not exist or could not be
opened as new|existing file.
EXPLANATION:
This indicates there was a problem trying to open the fault model file. See previous
EDAM error messages for details of the problem.
USER RESPONSE:

Resolve the problem(s) identified in previous EDAM error messages. If you do not see
the previous messages, or do not know what to do, contact customer support (see
WARNING (TFM-004): [Severe] Problem attempting to close fault model file (EDAMfcls).
EXPLANATION:
A problem occurred when trying to close the fault model file. See previous EDAM error
messages for details of the problem.
USER RESPONSE:
WARNING (TFM-005): [Severe] Problem attempting to open a storage area in the fault
model file (EDAMsopn)..
EXPLANATION:
A problem occurred when trying to open a storage area in the fault model file. See
previous EDAM error messages for details of the problem.
USER RESPONSE:
WARNING (TFM-006): [Severe] Problem attempting to close a storage area in the fault
model file (EDAMscls).
EXPLANATION:
A problem occurred when trying to close a storage area in the fault model file. See
USER RESPONSE:
WARNING (TFM-007): [Severe] Problem attempting to read a storage area in the fault
model file (EDAMsget).
EXPLANATION:

A problem occurred when trying to obtain a storage area from the fault model file. See
USER RESPONSE:
WARNING (TFM-008): [Severe] Problem attempting to write data to the fault model file
(EDAMsput).
EXPLANATION:
A problem occurred when trying to put a storage area into the fault model file. See
USER RESPONSE:
WARNING (TFM-009): [Severe] Problem attempting to close the EDAM Paging Manager
(EDAMterm).
EXPLANATION:
A problem occurred when trying to terminate an internal program function called the
EDAM Paging Manager. See previous EDAM error messages for details of the problem.
USER RESPONSE:
USER RESPONSE:
ERROR (TFM-010): [Internal] Error loading model (TLMgetContext error).

EXPLANATION:
A problem occurred when accessing the logic model. See previous messages from logic
model utilities for details of the problem.
USER RESPONSE:

Resolve the problem(s) identified in previous utility error messages. If you do not see the
previous messages, or do not know what to do, contact customer support (see
ERROR (TFM-011): [Internal] Error unloading model (TLMfreeContext error.

EXPLANATION:
A problem occurred when accessing the logic model See previous messages from logic
USER RESPONSE:
WARNING (TFM-012): [Severe] Problem loading model (TLMloadModel).

EXPLANATION:
A problem occurred when loading the logic model. See previous messages from logic
USER RESPONSE:
WARNING (TFM-013): [Severe] Problem unloading model (TLMunloadModel).

EXPLANATION:
A problem occurred when unloading the logic model. See previous messages from logic
USER RESPONSE:
WARNING (TFM-014): faultModel file fully qualified filename does not exist or
could not be opened.
EXPLANATION:
The indicated faultModel file does not exist or could not be opened.

USER RESPONSE:
If you are running from the command line, ensure that this is for the right design.
(WORKDIR specifications are accurate).
If you are running from the graphical used interface, the most likely cause of the error is
forgetting to run Build Fault Model. You must build the fault model before you can run any
applications that require it. Use build_faultmodel or use the Build Fault Model form
on the Graphical User Interface.
If the file exists, there should be messages preceding this message that indicate why the
file could not be opened. Review these messages, resolve any problems, and rerun if
necessary.
WARNING (TFM-015): faultStatus file fully qualified filename does not exist or
EXPLANATION:
The faultStatus file indicated in the message does not exist or could not be opened.
USER RESPONSE:
If you are running from the command line, ensure you are using the right design
(WORKDIR and TESTMODE specified as input are accurate). If the input is correct, or
you are running from the graphical user interface, the problem is probably one of the
following:
The application that should have created the faultStatus file failed. Check your
log to determine if build_fault_model, or build_testmode failed.
The faultStatus file has been removed with one of the Encounter Test processes
(delete_testmode).
The faultStatus file has been removed manually. Use build_faultmodel or
use the Build Fault Model form on the Graphical User Interface. If the file exists,
there should be messages preceding this message that indicate why the file
WARNING (TFM-016): Experiment file fully qualified filename does not exist or
EXPLANATION:
The uncommitted faultStatus file indicated in the message does not exist.
USER RESPONSE:

Ensure the WORKDIR, TESTMODE, and EXPERIMENT specified as input are accurate.
If the input is correct, or you are running from the graphical user interface, the problem
is probably one of the following:
log to determine if a test generation run failed.
The faultStatus file has been removed with one of the Encounter Test processes
(delete_testmode or delete_tests).
The faultStatus file has been removed manually. Rerun the application or tool
that created the experiment. If the file exists, there should be messages
preceding this message that indicate why the file could not be opened.
ERROR (TFM-017): [Internal] Open request incompatible with current open state.
EXPLANATION:
The application tried to open the fault model file and it was currently open.
USER RESPONSE:
If you have multiple applications that process faults running simultaneously it
may be that you need to wait until one of them is done and then submit the other
one.
If you do not understand what is causing the error and it is not resolved y by
resubmitting the application, contact customer support (see Contacting
Customer Service on page 23) group.
WARNING (TFM-018): [Severe] Invalid function parameter: parameter

EXPLANATION:
An invalid parameter has been specified as input to one of the programs, and is shown
in the message.
USER RESPONSE:
Correct the invalid parameter according to the help text available for the executable
program and reinvoke the program. To get the help for "build_faultmodel , invoke the
program with the -h parameter.
WARNING (TFM-019): Testmode testmode_name data does not exist in the fault model.
EXPLANATION:
Information related to the indicated testmode does not exist in the fault model.

USER RESPONSE:
Ensure that the TESTMODE parameter is specified correctly and that it exists.
ERROR (TFM-020): Code and data levels are incompatible. Rebuild or migrate fault model
files.
EXPLANATION:
The fault model being used as input to the application was created with a back level (pre-
release 12.1) version of the fault model programs. These files can be read but cannot be
updated in release 12.1 without rebuilding or migrating them to release 12.1.
USER RESPONSE:
Either rebuild the faultModel in release 12.1 or run the command "build_faultmodel
migratefaultstatus=yes" to migrate the existing master faultStatus file to release 12.1
format, then re-run the command that got the TFM-020.
WARNING (TFM-021): [Severe] faultModel file younger than faultStatus file.

Rebuild all faultStatus files.
EXPLANATION:
The currently existing faultModel was built after the faultStatus file.
USER RESPONSE:
Ensure that the WORKDIR, TESTMODE, and EXPERIMENT values are accurate.
Rerun Build Fault Model to reinitialize the faultStatus file (build_faultmodel
overwrite=yes). This will cause all test generation data to be removed.
Repeat any previous test generation runs.
WARNING (TFM-022): [Severe] Testmode data is younger than experiment. Rebuild the
experiment file.
EXPLANATION:
The fault model data for the testmode was created after the experiment you are trying to
process.
USER RESPONSE:
Ensure the WORKDIR, TESTMODE, and EXPERIMENT specified as input are
accurate.
Remove the faultStatus.experiment file and rerun the application that
created it.

ERROR (TFM-023): [Internal] Program error while trying to delete a file (EDAMfdel).
EXPLANATION:
There was a program error in an internal EDAM utility while trying to delete a file.
USER RESPONSE:
See preceding EDAM messages to understand the actual problem. If you are unable to
resolve the problem, contact your customer support (see Contacting Customer Service
on page 23) group.
ERROR (TFM-024): [Internal] Program error while attempting to perform a checkpoint

(EDAMckpt).
EXPLANATION:
There was a program error in an internal EDAM utility while trying to perform a
checkpoint
USER RESPONSE:
resolve the problem, contact customer support (see Contacting Customer Service on
page 23) group.
ERROR (TFM-025): [Internal] Program error while trying to free storage (EDAMsfre).
EXPLANATION:
There was a program error in an internal EDAM utility while trying to free storage.
USER RESPONSE:
resolve the problem, contact customer support, (see Contacting Customer Service on
page 23) group.
ERROR (TFM-026): [Internal] An invalid number of XOR inputs has been specified
EXPLANATION:
The XOR in the logic model has an invalid number of inputs.
USER RESPONSE:
If build_model completed successfully, then this is a program problem that needs
analysis by customer support (see Contacting Customer Service on page 23).

ERROR (TFM-027): [Internal] An invalid number of LATCH inputs has been specified
EXPLANATION:
A Latch block specified in the logic model has an invalid number of inputs.
USER RESPONSE:
ERROR (TFM-028): [Internal] An invalid number of TSD inputs has been specified
EXPLANATION:
A TSD in the logic model has an invalid number of inputs.
USER RESPONSE:
WARNING (TFM-029): [Severe] Logic model younger than fault model. Rebuild all fault
model files.
EXPLANATION:
According to the dates stored in the files, the fault model was built before the logic model.
If you rebuild the logic model it should remove the fault model. Therefore, this error
should not occur under normal circumstances.
USER RESPONSE:
If you have been copying files from one directory to another, and think you may have
accidentally caused this problem, rebuild the fault model. Note that any existing test data
will be invalid with the new fault model.
If you think Encounter Test created this problem, contact customer support (see
WARNING (TFM-030): [Severe] Logic model create date cannot be verified

EXPLANATION:
The Fault Model Build program is unable to verify the logic models creation date. Either
the specified logic model files do not exist, or they have been damaged.
USER RESPONSE:
Review the log for this run and fix problems associated with any previous errors.

Review the log for build_model. If it indicates severe errors, correct the
problems, rebuild the model and rerun build_faultmodel.
If there were no problems indicated prior to this message (in either
build_model or build_faultmodel), contact customer support (see
WARNING (TFM-031): [Severe] Fault model file filename contains no header

information. Rebuild the file.
EXPLANATION:
There is something wrong with the indicated fault model file. Most likely, the process that
attempted to generate the fault model file ended abnormally before it properly closed the
file. Another possibility is that during the creation of the fault model file, the capacity of
the file system was exceeded.
USER RESPONSE:
If the file indicated is faultModel or faultStatus, review messages from Build
Fault Model, fix any problems and rerun Build Fault Model.
If the file indicated is faultStatus.testmode.experiment, review messages from
Test Generation to determine why the file isnt valid. Rerun the test generation
experiment that created the file.
If the file indicated is faultStatus.testmode, review the messages from Commit
to determine why the file isnt valid. Depending on why the problem occurred,
you may be able to recover by rerunning Commit or you may have to rerun test
generation and Commit.
WARNING (TFM-032): [Severe] syntax error in file file name on line number:
string: line of text containing the syntax errror
EXPLANATION:
The pattern fault file being processed has a syntax error on the indicated line number. If
the error string is "ENTITY", and the fault rule contains more than one ENTITY
statement, the problem is most likely that a set of braces, { }, is missing around the fault
rule statements associated with the ENTITY. These are required only if there is more
than one ENTITY statement in the fault rule file. If "Possible missing ENTITY statement"
appears in the string portion of the the message, and the fault rule statement is not
NOFAULT or FAULTONLY, and does not appear to have any syntax errors, message, and
the fault rule statement is not NOFAULT or FAULTONLY, and does not appear to have any
syntax errors, then most probably the syntax specified requires an ENTITY statement to
identify the name of the containing block (Verilog module) that the fault rule is associated
with, and no ENTITY statement was found. ENTITY must precede the statement with the

syntax error. Processing continues but no statements after the failing statement will be
processed.
USER RESPONSE:
Look up the correct Fault Rule File Syntax for the pattern fault in the documentation,
correct the data in the file and rerun Build Fault Model.
WARNING (TFM-033): ENTITY name: entity_name in Fault File: filename does not
match the name of the entity in the logic model: cell name that pointed to it.
EXPLANATION:
The pattern fault filename is pointed to from a specific entity (cell) in the logic model. The
cell name in the design source (or library data model source) for that entity (cell) must
match the name in the ENTITY= parameter in the pattern fault file. These names didnt
match.
USER RESPONSE:
Compare the entity name to the logic model cell_name given in this message. If you
can tell that this is the correct pattern fault for the logic model entity (for example, there
is a minor error in the name), change the name in the pattern fault file to match the name
in the logic model. Rerun Build Fault Model with the updated pattern fault file.
If the names are completely different:
Check the pattern fault file to determine if this is the correct pattern fault with the
wrong name (for example, you copied an existing pattern fault to create this one and
forgot to change the name)! If it is, change the name in the pattern fault file and
rerun Build Fault Model. If this is truly the wrong pattern fault for the entity, you will
have to change the filename in the logic source. Rerun Build Model to create a new
model, rerun any applications you have already run (for example, Define a Test
Mode) and then rerun Build Fault Model.
WARNING (TFM-034): Cannot open rules file pattern_fault_filename

EXPLANATION:
The pattern fault file exists but Build Fault Model was unable to open it. Generally this
means the user name that started Build Fault Model does not have permission to read
the file.
USER RESPONSE:
Ensure you specified the correct FAULTPATH (specified with an environment
variable $FAULTPATH, the FAULTPATH keyword, or Fault Path from the

Graphical User Interface). It may be that the file exists in multiple directories and
you do not have access to the one you specified.
If the FAULTPATH is correct, ensure you have read authority for the file.
NFS: Use ls -l filename to list the file permissions for owner, group, user
(you must have at least r (read) permission) Use groups to find out what group
youre in.
Use chmod, chgrp, or chown to change the file permissions, groups, or
ownership.
AFS: Use fs listacl to list the directorys access list (you must have at least
rl (read and lookup) permission. Use pts to find out the membership of a
group.
Use fs setacl to change the directorys access list.
WARNING (TFM-035): Cannot resolve filename filename specified on FAULTS=

keyword in cell cellname. Check the path variable name environment variable.
EXPLANATION:
The pattern fault filename specified in the logic model source does not exist in the
specified Fault Path.
USER RESPONSE:
If the pattern fault is part of the library data, you may have been unaware that a
FAULTPATH needed to be specified. If this is the case, you need to determine
where the pattern fault information is installed (it is probably in the same
directory structure as other library data, but may be in a different sub-directory).
Look for the filename indicated in the message.
Specify the correct directory path using one of the following methods):
Set the environment variable $FAULTPATH to the correct path (this may be set
in the et file).
If using the command line to invoke Build Fault Model (for example,
build_faultmodel), use the FAULTPATH= keyword.
If using the Graphical User Interface, set the Fault Rule Path by clicking
Setup on the Build Fault Model form.
WARNING [Severe] (TFM-036): Unable to parse file filename

EXPLANATION:

The pattern fault file indicated in the message had syntax errors.
USER RESPONSE:
Fix specific syntax errors and rerun Build Fault Model.
WARNING (TFM-037): The fault model is suspected to be incomplete. Rebuild all fault
model files
EXPLANATION:
When the fault model was built, there were errors that did not cause the process to fail
but may have caused the fault model to be incomplete. The most common reason for this
is that there were user-specified pattern faults that were not resolved.
USER RESPONSE:
Review the messages from Build Fault Model to determine what errors
occurred.
Fix the problems indicated by the messages and rerun Build Fault Model.
ERROR (TFM-038): [Internal] Error applying tested status along with untestable status to
fault fault_number.
EXPLANATION:
An application tried to mark a fault tested and untestable. Since a fault cannot be both
untestable and tested, there is a problem in the test generation application.
USER RESPONSE:
Since this indicates a program problem, contact your customer support (see Contacting
WARNING (TFM-039): [Severe] Invalid argument(s): unrecognized_arguments

EXPLANATION:
A problem was detected in the string of single character arguments.
USER RESPONSE:
Review the correct syntax of the report_fault_statistics, report_faults or
build_faultmodel command in the Encounter Test: Reference: Commands, or
use -h to get a listing of the valid arguments. Rerun using valid command syntax. Refer
to the Encounter Test: Reference: Commands for additional information.

WARNING (TFM-040): [Severe] Unable to obtain a read lock on the specified design.
framework services return code (number)
EXPLANATION:
In order to process the fault model, the program must be able to read the information for
the design.
USER RESPONSE:
Ensure that the parameters you specified for WORKDIR are correct.
Ensure that you have read permission to the directory containing the design
and to the individual files in that directory.
If multiple applications were running simultaneously on the same design, try
resubmitting this application.
If you cant figure out why the design cannot be read, and rerunning does not
resolve the problem, contact customer support (see Contacting Customer
WARNING (TFM-041): [Severe] The fault model will not be built because the specified
design contains no primary outputs.
EXPLANATION:
Build Fault Model does its processing by tracing back from Primary Outputs. Since this
design has no Primary Outputs, the fault model cannot be built.
USER RESPONSE:
Review the messages from Build Model to determine why the design has no Primary
Outputs (output ports on the top cell).
WARNING [Severe] (TFM-042): Problems occurred during processing of user-specified

fault rule statements. Processing terminates.
EXPLANATION:
One or more problems were detected while processing statements contained in a fault
rule file. This message should be preceded by other messages which describe the
problems in more detail. Processing continues without any statements associated with
the ENTITY statement that has the erroneous statement. This means that if more than
one ENTITY statement exists in the fault rule file, just the statements associated with the
ENTITY that has the problem statements will be omitted. NOFAULT statements are not
associated with the ENTITY construct and are processed differently. Any failing

NOFAULT statement will not be processed, but any NOFAULT statements that can be
processed will still apply.
USER RESPONSE:
Refer to the preceding messages to determine the nature of the problems encountered
during processing of the fault rule statements. Address problems and rerun Build Fault
Model.
WARNING (TFM-043): PIN name conflict
Fault rule: entity_name, line number: fault_rule_line_number Logic model:

cell_name Pin name: pin_name
EXPLANATION:
The pin name used in the pattern fault did not exist on this cell in the logic model.
USER RESPONSE:
Check the name specified in the pattern fault file. Ensure it is a valid pin name for the
specified entity (one thing to check is whether it is a PIN name or a NET name -- net
names are allowed, but you must specify NET= instead of PIN=). Correct the pattern fault
file and rerun Build Fault Model.
WARNING (TFM-044): NET name conflict
Fault rule: entity_name, line number: fault_rule_line_number Logic model:

cell_name Net name: net_name
EXPLANATION:
The net name used in the pattern fault did not exist on this cell in the logic model.
USER RESPONSE:
Check the name specified in the pattern fault file. Ensure it is a valid net name for the
specified entity (one thing to check is whether it is a NET name or a PIN name -- pin
names are allowed, but you must specify PIN= instead of NET=). Correct the pattern fault
file and rerun Build Fault Model.
WARNING (TFM-045): Comet comet name does not exist.

EXPLANATION:
The comet name specified as a parameter to the report_faults or
report_fault_statistics program is invalid.
USER RESPONSE:

Check the comet name for spelling, or verify that the specified comet has been defined.
ERROR (TFM-046): Fault Model level is pre-Encounter Test 2.2. Migration to Encounter Test
2.2 is necessary but the environment variable TFM_FAULTMODEL_MIGRATE_NO indicates no
migration should take place. Processing terminates without migration to Encounter Test 2.2.
EXPLANATION:
No further explanation required.
USER RESPONSE:
The required response is described in the message.
WARNING (TFM-047): Block name block name does not exist. Fault rule: fault rule
file name Line number: fault rule file line number
EXPLANATION:
The block name used in the pattern fault did not exist on this cell in the logic model.
USER RESPONSE:
Check the name specified in the pattern fault file. Ensure it is a valid block name for the
specified entity. Correct the pattern fault file and rerun Build Fault Model.
ERROR (TFM-048): Write Ignore Faults: Fault rule file or directory name specified is not
writeable.
EXPLANATION:
Either the directory name specified in the OUTFAULTDIR parameter or the existing fault
rule file that the program is attempting to update is not writabl permission to the file /
directory is otherwise not allowed.
USER RESPONSE:
Check permissions of the fault rule file or directory and modify to allow write access.
ERROR (TFM-049): Write Ignore Faults: Unable to open fault rule file name for
append|write.
EXPLANATION:
The attempt to open the fault rule file for either append or write failed. The fault rule file
that the program is attempting to update is not writeable or permission to the file/directory
is otherwise not allowed.
USER RESPONSE:

Check permissions of the fault rule file or directory to see if write access exists. Check
the DASD volume quota for the fault rule file directory.
WARNING (TFM-050): [Severe] Unable to open logic model.

EXPLANATION:
This indicates there was a problem opening the logic model. See previous messages
from logic model utilities for details of the problem.
USER RESPONSE:

ERROR (TFM-051): [Internal] Updates to the fault model application data can only be
made when the fault model experiment file is open for update. This is a programming error.
EXPLANATION:
This indicates that an application attempted to update fault model application data on an
uncommitted faultStatus file (via call to TFMputAppData) when the file was not open for
update.
USER RESPONSE:
This is an internal program error. Contact customer support (see Contacting Customer
Service on page 23). The responsible programmer for the violating application should
make sure the experiment file is open for update before writing application data.
ERROR (TFM-052): [Internal] The application Id appId is not registered with the fault
model. Updates to unregistered application data areas are not permitted. This is a
programming error.
EXPLANATION:
This indicates that an application attempted to update fault model application data on an
uncommitted faultStatus file (via call to TFMputAppData) for an application ID that has
not been assigned.
USER RESPONSE:

Service on page 23). The responsible programmer for the violating application should
contact fault model developers to have an application ID assigned to his application.
WARNING (TFM-053): Attempt to mark Fault fault ID redundant is rejected. It is tested

in another test mode.
EXPLANATION:
This message indicates that a test generator concluded that fault (fault ID) is redundant.
However, the fault has been marked tested in another test mode and thus should not be
classified as redundant. This indicates an incorrect classification for the fault, which in
most cases should be classified as untestable due to test mode constraints. The fault
classification is left as untested. There is no loss in fault coverage, but test generator
efficiency will appear to be reduced.
USER RESPONSE:
There is no user response required. If it is important to obtain the correct classification
for this fault and it is possible to send the design to allow Encounter Test development to
resolve this design-dependent problem, contact customer support (see Contacting
ERROR (TFM-054): report_faults cannot be used on a checkpointed faultstatus

file.
EXPLANATION:
The experimental faultstatus file for which a fault list has been requested is in a
checkpointed state. report_faults cannot be used due to the exposure of another
checkpoint occurring before it has completed, thereby corrupting the data that is being
printed. The program exits.
USER RESPONSE:
WARNING (TFM-055): [Severe] Experimental faultstatus file is in a checkpointed

state. The file cannot be opened for update.
EXPLANATION:
An application attempted to open a checkpointed uncommitted faultstatus file for
update. This is not allowed. TFMrestart must be used.
This is a severe internal program problem. An invalid Fault Model handle will be returned
by TFMopenExperiment.

USER RESPONSE:
Contact customer support (see Contacting Customer Service on page 23). The
application programmer can correct the problem by using TFMrestart instead of
TFMopenExperiment when attempting to open a checkpointed faultstatus file.
WARNING (TFM-056): [Severe] Unable to open checkpointed version of faultStatus

file for checkpoint ID checkpoint ID.
EXPLANATION:
An application attempted to open a checkpointed uncommitted faultStatus file but
the version specified (checkpoint ID) does not exist. This is a severe internal program
problem. An invalid Fault Model handle will be returned by TFMrestart.
USER RESPONSE:
You may not restart the experiment. Rerun the experiment from the beginning. If any
additional problems are encountered, contact customer support (see Contacting
WARNING (TFM-057): Unable to resolve usage of fault pin name fault type on
usage block block_name.
EXPLANATION:
prepare_fault_subset was unable to resolve the fault described in the message for
the particular usage block that the fault pin name resolved to.
Processing continues. This is just a warning. It may be that the fault is inactive in the test
mode being processed. If deemed necessary, investigate the fault.
USER RESPONSE:
None required. If using report_faults to produce the input fault list, be sure that the
faultlocation=pin and faultsubset=yes keyword pairs were specified.
If the preceding was done and it appears that the fault exists and should have been
included in the fault subset, contact customer support (see Contacting Customer
WARNING (TFM-058): pin name fault type could not be resolved. No faults
processed.
EXPLANATION:
prepare_fault_subset was unable to find any valid usages of the fault described in
the message which came from the input user fault list. Processing continues. This is just

a warning. No faults were included in the fault subset for this entry in the user fault list. It
may be that the fault(s) is/are inactive in the test mode being processed. Determine
whether to investigate the fault.
USER RESPONSE:
If it appears that the fault(s) exist(s) and should have been included in the fault subset,
WARNING (TFM-059): problem description. Fault pin name fault type not
processed.
EXPLANATION:
prepare_fault_subset was unable to find a pin corresponding to the pin name
specified or the pin name specified was not a valid pin name. Processing continues. This
is just a warning. No faults were included in the fault subset for this entry in the user fault
list. If deemed necessary, investigate the fault.
USER RESPONSE:
If it appears that the pin name was valid, contact customer support (see Contacting
ERROR (TFM-060): prepare_fault_subset error: problem description.

Program exits.
EXPLANATION:
A prepare_fault_subset terminating error condition occurred. No valid output will
be produced by prepare_fault_subset.
USER RESPONSE:
Use the message error description to correct the condition. Correct the problem and
rerun prepare_fault_subset. Contact customer support (see Contacting Customer
Service on page 23) if requiring additional assistance.
WARNING (TFM-061): prepare_fault_subset warning: problem description.

EXPLANATION:

prepare_fault_subset encountered a problem warranting a warning message. The

warning condition is described and processing continues. All output of
prepare_fault_subset will be valid. If deemed necessary, investigate the fault
USER RESPONSE:
No response is required. The problem escription does not require any action. All output
of prepare_fault_subset will be valid. If deemed necessary, use the message error
description to correct the condition to investigate and correct the problem.
INFO (TFM-062): Experimental test vector file is registered and assumed to exist.
prepare_fault_subset will not create a test vector file.
EXPLANATION:
prepare_fault_subset normally tries to create an empty experimental TBDbin (test
vector) file that is to be used to store test vector information if a test generation run is
appended to the experiment created by prepare_fault_subset. If the test vector file
is already registered on the globalData file, it is assumed that it exists and should be
retained. Therefore, prepare_fault_subset continues without test vector file
creation.
USER RESPONSE:
ERROR (TFM-063): Input faultlist file file_name could not be opened. Program exits..
EXPLANATION:
The fault list file specified as input to prepare_fault_subset via the
faultlist=option could not be opened and caused the program to exit.
USER RESPONSE:
Rerun prepare_fault_subset with a valid fault list name specified.
ERROR (TFM-064): Fault Model commit error: error description.

EXPLANATION:
The fault models commit function failed and caused a program exit. The error description
will indicate the problem. Possibilities include: fault model not opened for a commit, or
the uncommitted faultStatus file has been flagged as being invalid for a commit.
USER RESPONSE:
If the reason for the failure is that the fault model was not opened for a commit, this is an
internal program error - contact customer support (see Contacting Customer Service

on page 23). If the reason for the failure is that the experiment is invalid for a commit, a
commit cannot be performed on this experiment.
WARNING (TFM-065): prepare_fault_subset:None of the faults in the input fault list

were successfully processed. The fault subset will be empty.
EXPLANATION:
The specified fault list file input file did not contain any statements that could be
processed by prepare_fault_subset. The most likely problem is that the input list of
faults was not in a form that could be parsed. Processing continues but the fault subset
will be empty.
USER RESPONSE:
Check the input fault list. It should be similar in format to the output of report_faults.
Use report_faults with the faultlocation=pin option (display fault pin name) to
create the fault list. Refer to "report_faults" in the Encounter Test: Reference:
WARNING (TFM-066): TFMcheckpoint program warning: checkpoint attempted on

temporary faultStatus file. Checkpointing a temporary file is not allowed.
EXPLANATION:
An attempt was made to checkpoint the uncommitted faultStatus file, but the file was
opened as a temporary file. Processing continues with no checkpoint performed.
USER RESPONSE:
No response required. The application programmer can eliminate this message by not
calling TFMcheckpoint when TFMopenExperiment was called with the
TFM_OPEN_TEMPEXP flag set.
WARNING (TFM-067): Net names are supported only for sourceless nets. Net name is
not a sourceless net. Processing continues.
EXPLANATION:
A net name was encountered in the input fault list that was not a sourceless net. Net
names can only be processed for sourceless nets.
USER RESPONSE:
Modify the input fault list to specify the pin name for the pin driving the net referred to in
the message. If the input fault list was generated using report_faults, rerun and
specify the report_faults faultlocation=pin command option.

WARNING (TFM-068): Pattern fault specification in fault rule file FRULE name for entity
entity name contains a propagation net/pin that is on a RAM or ROM. This is not
supported. Propagation pin name = pin name Propagation net name = net name
Processing continues. The fault will not be included in the fault model.
EXPLANATION:
A ROM or RAM propagation net or pin name was encountered in a fault rule specification
in the fault rule file shown in the message.
Faults are not allowed to be created on RAM or ROM primitives. The offending net and
pin names are displayed.
USER RESPONSE:
Remove the fault specification from the fault rule file and rerun Build Fault Model, or if
there is a buffer block or an L5 latch fed by the RAM/ROM in question, the output net/pin
of the buffer or L5 can be made the propagation net/pin. If a buffer or L5 does not exist,
they can be inserted into the logic model. This would require re-import of the design,
rebuilding of test modes and rebuilding of the fault model.
ERROR (TFM-069): [Internal] Mode Id for test mode test mode name is outside of
range allowed by Fault Model Build.
EXPLANATION:
The mode ID number returned by TTMmodeNumber exceeds the maximum allowed by
Fault Model Build. The Fault Model cannot process this mode ID. Either the number of
modes has exceeded this limit or the number of redefinitions of the test modes has
caused the mode ID numbers to go beyond this limit.
USER RESPONSE:
This is an internal program error and should be reported to customer support (see
Contacting Customer Service on page 23). Most likely, the design will have to be re-
imported and test modes and fault model rebuilt to recover from this problem.
WARNING (TFM-070): Unable to build fault model data for test mode test mode name.
EXPLANATION:
Fault Model Build was unable to build test mode data for the test mode specified. The
Fault Model will not contain valid data for the test mode.
USER RESPONSE:
Review any messages preceding this message and take the action specified in the
messages. This may include rebuilding the test mode or re-importing the design. If you

are unable to determine the action to take or there are no preceding messages, contact
WARNING (TFM-071): Experiment experiment_name is not registered.

EXPLANATION:
The experiment indicated in the message is not registered on the globalData.
USER RESPONSE:
is probably that the application that should have created the experiment failed.
Check your log to determine if the application failed.
WARNING (TFM-072): Unable to open Experiment file fully_qualified_filename.

EXPLANATION:
The uncommitted faultStatus file indicated in the message was unable to be opened for
processing.
USER RESPONSE:
Check for previous messages that indicate why the file was unable to be opened. If this
doesnt help, some things to check for:
accurate, especially if you are trying to work with an existing experiment.
If this is a new experiment, check to see that enough DASD is available to
create the file.
ERROR (TFM-073): TESTMODE was not specified and is a required parameter when used
in conjunction with the -m flag.
EXPLANATION:
TESTMODE specifies the name of a predefined test mode and is a required parameter
when used with the -m flag.
USER RESPONSE:
Specify TESTMODE on the command line or as an exported variable. Refer to
build_faultmodel in the Encounter Test: Reference: Commands for additional
information.

INFO (TFM-074): Hierarchical block level hier block name exceeds highest level of
hierarchy. The highest level will be used.
EXPLANATION:
The level specified in the hierblocks or hierstart command for report_faults or
report_fault_statistics exceeds the top level of the hierarchy of the design. The
run will continue using the highest level of the hierarchy.
USER RESPONSE:
ERROR (TFM-075): Invalid hierarchical block name or index hier block name
specified.
EXPLANATION:
The hierarchical block name or index specified in the hierblocks or hierstart command for
report_faults or report_fault_statistics could not be found in the logic
model. The program exits.
USER RESPONSE:
Specify a valid hierarchical block name or index and rerun. Acceptable forms of the name
are proper name or short name.
ERROR (TFM-076): Unable to open fault rule file fault_rule_filename during fault
rule creation.
EXPLANATION:
The fault rule write API could not open/create the fault rule file.
USER RESPONSE:
Check for directory permissions or not enough DASD.
WARNING (TFM-077): Unable to remove file fault_rule_filename during fault rule

creation.
EXPLANATION:
The fault rule write API could not remove the specified fault rule file at the end of
processing.
USER RESPONSE:
Check for directory permissions.

INFO (TFM-078): Processing fault rule data from stdin. No fault rule auditing will take place.
All other means of fault rule input will be ignored.
EXPLANATION:
This information message indicates that the keyword faultrulefile=STDIN has
been specified to build_faultmodel to indicate fault rule data is being piped in
through stdin.
USER RESPONSE:
WARNING (TFM-079): Build Alternate Fault Model proceeding on a subset of test modes.
The resultant alternate fault model can be used only for those test modes specified with the
testmodelist keyword.
EXPLANATION:
The keyword testmodelist=list_of_test_modes has been specified for
build_alternate_faultmodel to indicate fault status information is to be initialized
only for the specified test modes. The resultant alternate fault model can be
subsequently used only for those test modes having initialized fault status information.
USER RESPONSE:
WARNING (TFM-081): A cell boundary fault model was requested for a model that was not
built with industrycompatible=yes.
EXPLANATION:
A cell boundary fault model was requested, however the logic model was not built with
the industrycompatible=yes option. The intent of this message is to provide an
alert that the fault model may have faults on the inputs/outputs of primitives on the cell
boundaries rather than on the cell inputs/outputs. This may result in a fault model with
more faults than expected due to fanout from the cell inputs..
USER RESPONSE:
If this condition is undesirable, rerun build_model with industrycompatible=yes
specified. Otherwise, no action is necessary.
WARNING (TFM-082): Cell boundary fault type at pin name cannot be assigned to a
single primitive pin. The fault is added to all connected primitives inside the cell.
EXPLANATION:

A fault being read in is identified by a cell boundary pin that cannot be mapped to a
unique primitive pin. When a cell boundary fault model is created that is not industry
compatible, some faults may be assigned to the cell boundary that do not directly
correlate to a primitive pin. This occurs when there is fanout from a technology cell input
pin or when there is fanout inside the cell that feeds a technology cell output pin.
USER RESPONSE:
If you did not intend to create faults on all connected primitive pins, specify the primitive
pin(s) where faults should be created, rather than the cell boundary pin, and then rerun.
WARNING (TFM-083): A full fault model was requested (cellfaults=no) for a logic
model that was built with industrycompatible=yes.
EXPLANATION:
A fault model with faults on logic internal to cells was requested with the
cellfaults=no option and the logic model was built with the
industrycompatible=yes option. This message provides an alert that the fault
model will have faults on the inputs/outputs of primitives on the cell boundaries and
internal to the cell in addition to the faults on the cell inputs/outputs. This may result in a
fault model with more faults than expected.
USER RESPONSE:
If this condition is undesirable, rerun build_model with industrycompatible=no
specified or rerun build_faultmodel with cellfaults=yes, which is the default
when industrycompatible=yes. Otherwise, no action is necessary.
WARNING (TFM-084): Report Faults keyword ignored=yes was specified but Fault Model
was not built with includeignore=yes.
EXPLANATION:
Report Faults was run with the option ignored=yes to list the ignored faults but the fault
model was not built with option includeignore=yes, so not all of the ignored faults
were included in the fault model and will not be in the Report Faults output. If not
requested to be included, most ignored faults are left out of the fault model to save space,
but for an industry compatible fault model, the default is includeignore=yes.
USER RESPONSE:
If this condition is undesirable, rerun build_faultmodel with includeignore=yes
specified. Otherwise, no action is necessary.

WARNING (TFM-089): Fault Rule file: fault rule file name, specifies entity: fault
rule entity name, which does not exist in the logic model. Processing continues using
the top level cell as the entity.
EXPLANATION:
The ENTITY name specified in the fault rule file shown in this message cannot be found
in the logic model. Build Fault Model will attempt to continue using the top level cell,
which may or may not work.
USER RESPONSE:
If more warning or error messages follow, indicating an inability to resolve statements
inside the ENTITY construct, fix the ENTITY statement in the fault rule file to have a valid
technology cell name and re-run Build Fault Model.
WARNING (TFM-090): User-specified fault rule files have not been processed. See
previous messages for details.
EXPLANATION:
An problem occurred trying to open a fault rule file or resolve a file name or an entity
name within a fault rule. This message should be preceded by other messages which
describe the errors in more detail.
USER RESPONSE:
Refer to the preceding messages to determine the nature of the problems encountered
during processing of the fault rule statements. Address any problems and rerun Build
Fault Model.
ERROR (TFM-091): [Internal] Fault Rule(s) for entity: fault rule entity name,
pattern fault net table entry count exceeded capacity limit of 4G (2G with excludescanmode).
Program exits. Fault Model cannot be built.
EXPLANATION:
An internal program limit has been exceeded. During processing of fault rule data an
internal table capacity limit has been reached. Too many nets/pins have been specified
in the required and progagation values for the entity (cell) shown in the message.
USER RESPONSE:
Edit the fault rule file for the entity shown in the message to reduced the amount of
pattern fault data specified, then rerun Build Fault Model. Contact customer support (see
Contacting Customer Service on page 23) for a possible future enhancement to
support more pattern fault data.

WARNING (TFM-092): Duplicate entity statements found while processing fault rule file
fault_rule_file_name. Processing continues. Some data may be lost.
EXPLANATION:
The entity statement encountered in the fault file file shown in the message has already
been processed via another fault rule file or previously in this fault rule file. It is
recommended that all fault rule data associated with a single entity be specified in a
single entity statement to ensure that no data is lost (overwritten). It is also possible that
the same fault rule has been passed in more than once which can result in duplicate fault
definitions.
USER RESPONSE:
Determine if all fault data has been processed correctly. If not, combine the data into one
entity statement and rerun Build Fault Model.
ERROR (TFM-093): Build Fault Model exiting at user request due to errors in fault rule
processing. See previous messages for details. The fault model has not been created.
EXPLANATION:
Syntax errors occurred during fault rule processing and the user has specified
stoponsyntaxerror=yes, therefore Build Fault Model exits without creating the fault
model file. Preceding messages tell the error that occurred and the name and line
number of the fault rule file.
USER RESPONSE:
Correct the errors in the fault rule file(s) and rerun Build Fault Model. encountered during
processing of the fault rule statements. Address any problems and rerun Build Fault
Model.
INFO (TFM-098): Build Fault Model: now processing fault rule file
fault_rule_file_name.
EXPLANATION:
Build Fault Model is processing the fault rule file shown in the message.
USER RESPONSE:
INFO (TFM-099): Fault Model Build started.

EXPLANATION:
The Fault Model Build program has been invoked.

USER RESPONSE:
INFO (TFM-100): faultModel file filename exists and will not be overwritten.
EXPLANATION:
The faultModel file already exists.
USER RESPONSE:

INFO (TFM-101): Reinitializing faultStatus file filename
EXPLANATION:
The faultStatus file indicated in the message is being reinitialized.
USER RESPONSE:
INFO (TFM-102): Creating faultModel file filename.

EXPLANATION:
The indicated faultModel file is being created.
USER RESPONSE:
INFO (TFM-103): Creating faultStatus file filename.

EXPLANATION:
The indicated faultStatus file is being created.
USER RESPONSE:
ERROR (TFM-108): Fault model test mode processing is unable to continue. See the
preceding messages.

EXPLANATION:
While processing the faults in a test mode, a program error occurred. There should be
preceding messages to indicate the exact cause of the problem.
USER RESPONSE:
Correct the problems indicated in previous messages. If you are unable to determine the
cause of the error, contact customer support (see Contacting Customer Service on
page 23).
(severity)(TFM-109): Fault model build has completed with highest level severity
message of highest severity.
EXPLANATION:
You now have a ffaultModel and a faultStatus file containing the fault model.
USER RESPONSE:
INFO (TFM-110): A TIED value causes a DRIVER objective of objective value on

block block name to be untestable. This fault fault index is omitted from the fault
model.
EXPLANATION:
USER RESPONSE:
INFO (TFM-111): A TIED value causes a RECEIVER objective of objective value on block
block name to be untestable. This fault fault index is omitted from the fault model.
EXPLANATION:
USER RESPONSE:
INFO (TFM-112): No faults were found which met the selection criteria.
EXPLANATION:

USER RESPONSE:
INFO (TFM-113): Command option nottested=abort has been changed to

status=aborted. Change your command input for future runs since the old option will be
dropped in the next release of Encounter Test. Run continues with status=aborted.
EXPLANATION:
Refer to the message text.
USER RESPONSE:
INFO (TFM-114): Command option status=nottested is obsolete. The aborted option

is now a status option. Change your command input for future runs since the
status=nottested option will be dropped in the next release of Encounter Test. Run
continues with status=nottested.
EXPLANATION:
USER RESPONSE:
INFO (TFM-115): Migrating committed faultStatus file from version 3.1 to 6.1. Structures in
the committed faultStatus file have been enlarged. faultStatus file will not be usable in an
earlier Encounter Test version than 2.2 without rebuilding the faultStatus file using that
version.
EXPLANATION:
USER RESPONSE:
INFO (TFM-116): Migrating uncommitted faultStatus file from version 3.1 to 6.1. Structures
in the committed faultStatus file have been enlarged.
Experimental faultStatus file will not be usable in an earlier Encounter Test version than
2.2.
EXPLANATION:


USER RESPONSE:
INFO (TFM-117): No implied Fault Rule files found for processing.

EXPLANATION:
The cellnamefaultrules=yes option of build_faultmodel was specified but no
fault rule files were found for any component cells. Processing continues without
inclusion of faults from any fault rule files.
USER RESPONSE:
None required, but if a fault rule was intended to be included, ensure the FAULTPATH
variable is set to the proper fault rule file directory and verify the correct fault rule files
exist in the directory.
WARNING (TFM-118): IGNORE|PTAB|DETECTED|REDUNDANT fault processing is

unable to locate PATTERN pattern number on block block name.
EXPLANATION:
An IGNORE/PTAB/DETECTED/REDUNDANT statement was encountered in a fault rule
file with a pattern fault ID on a block for which no corresponding pattern fault could be
found. Processing continues without any faults being flagged ignored by this statement.
USER RESPONSE:
None required, but if desired, report_faults can be invoked to list the pattern faults
on a block and will list pattern fault IDs for each block. This can be used to verify that the
pattern fault ID listed in the message does not exist for the block listed in the message.
If it does exist, contact customer support (see Contacting Customer Service on
page 23).
INFO (TFM-119): Static|Dynamic faults are not assigned to logic within blocks
hierarchical_block_name, specified in Nofault statement.
EXPLANATION:
Build Fault Model did not assign Static|Dynamic faults to logic contained within the
hierarchical blocks shown in the message because those block was specified in
Nofault statements contained in a fault rule file.
USER RESPONSE:


unable to locate SA0|SA1|SR|SF fault on pin pin number.
EXPLANATION:
file for either a stuck-at-0, stuck-at-1, slow-to-rise, or slow-to-fall fault for which no
corresponding fault could be found. Processing continues without any faults being
flagged ignored by this statement.
USER RESPONSE:
None required, but if desired, report_faults can be invoked to list all faults on a pin
to verify that this fault does not exist. If it does exist, contact customer support (see
INFO (TFM-121): User pattern fault on pin|net pin|net_name, index

hier_pin|net_index exists on unmodeled logic and is ignored.
EXPLANATION:
A pattern fault has been defined on logic that has been removed from the flat model due
to logic model optimization or being in unmodeled logic. As a result, information
regarding correlation of the flat model to the hierarchical model will be incomplete in the
fault listing.
USER RESPONSE:

unable to locate SA0|SA1|SR|SF fault on net net name.
EXPLANATION:
file for either a stuck-at-0, stuck-at-1, slow-to-rise, or slow-to-fall fault for which no
corresponding fault could be found. Processing continues without any faults being
flagged ignored by this statement.
USER RESPONSE:
None required, but if desired, report_faults can be invoked to list all faults on a net
to verify that this fault does not exist. If it does exist, contact customer support (see
INFO (TFM-123):Static|Dynamic Faults are being assigned ONLY to logic within

block hierarchical_block_name, specified in a FaultOnly statement.

EXPLANATION:
Build Fault Model assigned Static|Dynamic faults to logic contained within the
hierarchical block shown in the message because the block was specified in a Fault or
FaultOnly statement contained in a fault rule file. Automatic faults for other hierarchical
blocks are not created, but any user defined faults will be included.
USER RESPONSE:
INFO (TFM-124): Write Ignore Faults: IGNORE statements written: IGNORE statement
count PTAB statements written: PTAB statement count DETECTED statements
written: DETECTED statement count REDUNDANT statements written: REDUNDANT
statement count.
EXPLANATION:
This informational message indicates the number of IGNORE statements, PTAB
statements, DETECTED statements, and REDUNDANT statements created by this
invocation of prepare_ignore_faults.
USER RESPONSE:
INFO (TFM-125): OUTFAULTDIR directory name does not exist. Now attempting to
create it.
EXPLANATION:
This informational message indicates that the directory specified for the fault rule file (the
output file of prepare_ignore_faults) to be written to does not exist, and therefore
the directory will be created. Message TFM-126 indicates where the file was written.
USER RESPONSE:
INFO (TFM-126): Prepare Ignore | Prepare Detected | Prepare Core

Migration Faults: output file written to directory name/file name.
EXPLANATION:
This informational message tells where the fault rule file was written, specifying the fully
qualified file name (directory name and file name).
USER RESPONSE:

WARNING (TFM-127): Problem trying to get top level cell name. IGNORE will be used as
the Ignore/Detected Fault file name.
EXPLANATION:
An problem occurred when attempting to get the top level cell name of the design from
the Model. This is ordinarily the name that will be given to the fault rule file (output file of
prepare_ignore_faults/prepare_detected_faults) which will contain the
IGNORE/PTAB/DETECTED statements. Processing continues with the file named
IGNORE.
USER RESPONSE:
None required, but if the file is intended to be used as input to Build Fault Model, it must
have the cell name, so contact customer support (see Contacting Customer Service on
page 23).
INFO (TFM-128): Prepare Ignore/Detected Faults: fault rule file directory name/file
name opened for append.
EXPLANATION:
The fault rule file specified in the message exists and is being appended.
USER RESPONSE:
INFO (TFM-129): Experiment File is in a checkpointed state. Checkpoint ID=checkpoint

Id.
EXPLANATION:
The uncommitted faultStatus file for which statistics are being printed is checkpointed
state. The checkpoint ID is provided.
USER RESPONSE:
INFO (TFM-130): prepare_fault_subset: Creating uncommitted faultStatus file:

project/entity/faultStatus.testmode.experiment
EXPLANATION:
This informational message indicates the name of the uncommitted faultStatus file being
created.

USER RESPONSE:
INFO (TFM-131): Append specified but uncommitted faultStatus file does not exist. File will
be created.
EXPLANATION:
This informational message indicates that the append option has been specified but the
uncommitted faultStatus file does not exist. The file will be created and processing
continues.
USER RESPONSE:
INFO (TFM-132): Now creating test mode information for Stuck Driver Test Verification
alternate fault model.
EXPLANATION:
This informational message indicates that an alternate fault model exists for Stuck Driver
Test Verification and it will now have test mode data created for the current test mode
being built. The test mode fault statistics that follow this message are for the SDT Verify
alternate fault model.
USER RESPONSE:
INFO (TFM-133): No faults are active for test mode testmode.

EXPLANATION:
This informational message indicates that there are no active faults in the test mode just
created.
USER RESPONSE:
INFO (TFM-134): Unable to uncompress file fileName.

EXPLANATION:
This informational message indicates that the fault model application was unable to
USER RESPONSE:

If subsequent messages indicate a problem attempting to read the file, they are possibly
caused by a problem uncompressing the file. Verify that there is enough disk space for
an uncompressed version of this file. If there is enough space, contact customer support
INFO (TFM-135): Unable to compress file fileName.

EXPLANATION:
This informational message indicates that the fault model application was unable to
compress the specified file.
USER RESPONSE:
No response required, but if the specified file is uncompressed after the program ends
and this is not desired, contact customer support (see Contacting Customer Service on
page 23).
WARNING (TFM-136): No scan sections found. No apriori fault markoff will be performed.
EXPLANATION:
No scan sections were found in the scan test mode specified as input to
prepare_apriori_faults. Therefore no apriori fault markoff can be done.
USER RESPONSE:
Re-run prepare_apriori_faults with a scan test mode that has at least one scan
section.
WARNING (TFM-140): Fan-out was detected from the source of the net for the pin specified
in the PROP statement, on line #line number. The source of the net will be treated as the
propagation point.
EXPLANATION:
This warning message indicates that a propagation was specified from a node with fan-
out from the source of the net. The source of the net will be treated as the propagation
point.
USER RESPONSE:
WARNING (TFM-141): A conflict has been detected between the Fault Machine (FM) value
specified for the pin/net in the PROPAGATION statement on line #line number of fault
rule file fileName and the FM value specified for the same pin/net in the INITIAL |

REQUIRED statement. The FM value in the INITIAL | REQUIRED statement will be

converted to X.
EXPLANATION:
If the same pin/net is specified in an INITIAL or REQUIRED statement and a
PROPAGATE statement, the Fault Machine value (the value on the right side of the slash,
that is, GM/FM where FM is the Fault Machine value) must be the same in all
specifications or be left as a dont care value (X) in the INIT/REQ statement. Build Fault
Model will convert it to X in the initial/required value. Failure to make this change would
result in an untestable fault due to conflicting FM values.
USER RESPONSE:
If the same pin/net is specified in an INITIAL or REQUIRED statement and a
PROPAGATE statement, the Fault Machine value (the value on the right side of the slash,
that is, GM/FM where FM is the Fault Machine value) must be the same in all
specifications or be left as a dont care value (X) in the INIT/REQ statement. Build Fault
Model will convert it to X in the initial/required value. Failure to make this change would
result in an untestable fault due to conflicting FM values.
USER RESPONSE:
None required, but to eliminate the message, change the FM value in the INITIAL/
REQUIRED statement for the pin/net that is the same pin/net as the PROPAGATE pin/net
so that it does not conflict with the FM value in the PROPAGATE statement. A value of X
is recommended.
WARNING (TFM-142): End-of-file was encountered while inside a multi-line '/*' comment.
Possible missing end of comment '*/'.
EXPLANATION:
While parsing a fault rule file, build_fault_model encountered the begin multi-line
comment syntax '/*', but end-of-file was encountered before the end of multi-line
comment syntax '*/'. This may be an error of omission that results in lines not being
parsed that were intended to be parsed.
USER RESPONSE:
If the end of comment was not intentionally omitted, edit the file to place the '*/' end
comment syntax in the correct place and re-run build_fault_model.
INFO (TFM-144): Block hierarchical_block_name specified in NOFAULT |

FAULTONLY BLOCK statement is not instance specific and will be skipped.
EXPLANATION:

NOFAULT BLOCK <block name> or FAULTONLY BLOCK <blockname> was

specified with a block name that was not instance specific. The block name must be an
instance specific hierarchical block name.
USER RESPONSE:
Correct the block name to be an instance specific name or use the syntax that supports
non-instance specific blocks, NOFAULT/FAULTONLY CELL, or NOFAULT/FAULTONLY
INSTANCE <name> IN CELL <name>.
INFO (TFM-145): Processing fault detection data from: file_name.

EXPLANATION:
Informational message reporting the input fault detection data is being processed from
the indicated source.
USER RESPONSE:
INFO (TFM-146): Prepared a total of total_fault_rules fault rules

(number_of_static_fault_rules static and
number_of_dynamic_fault_rules dynamic) in total_OR_groups OR groups for
cell cell_name.
EXPLANATION:
Informational message reporting the final statistics for the cell internal fault rules
prepared for the specified cell.
USER RESPONSE:
INFO (TFM-150): Delete Fault Model started.

EXPLANATION:
The Delete Fault Model command has been invoked. All faultModel and faulttatus
files will be deleted. All objectiveModel and objectiveStatus files will also be
deleted unless overridden with keyword option sdtsnt=no.
USER RESPONSE:
INFO (TFM-151): Removing file file_name and its dependent files.

EXPLANATION:
The referenced file is being deleted along with any files registered as dependent on this
file, and all registration records on the globalData file. For a faultModel file, the
dependent files are the faultStatus file and the experimental faultStatus files.for
an objective model file, the dependent files are the objectiveStatus file and the
experimental objectiveStatus files.
USER RESPONSE:
INFO (TFM-152): File file_name not found. Proceeding with attempts to remove
dependent files and registration records.
EXPLANATION:
The referenced file shown was not found by the delete_faultmodel command but
processing will continue to remove files registered as dependent on this file, and to
remove all registration records on the globalData file.
USER RESPONSE:
ERROR (TFM-153): File file_name could not be deleted. See preceding messages.
EXPLANATION:
The referenced file could not be deleted. An internal program error message should have
been issued. Processing ends without removing dependent files or registration records.
The most likely reason for the failure is that another process is accessing the file and has
a lock on it. Another possibility is there is a permissions problem with the file.
USER RESPONSE:
Correct the error in the preceding message and rerun delete_faultmodel.
If there is no preceding message, contact customer support (see Contacting Customer
NFO (TFM-155): Delete Fault Model completed.

EXPLANATION:
The Delete Fault Model program has completed. If there are no error messages
preceding this message, all faultModel and faultStatus files have been deleted.

All objectiveModel and objectiveStatus files have also been deleted unless
overridden with keyword option sdtsnt=no.
USER RESPONSE:

INFO (TFM-376): TFMprint is no longer supported. Use report_fault_statistics to
display Fault Model Statistics. Use report_faults to display Fault Descriptions.
EXPLANATION:
USER RESPONSE:
INFO (TFM-461): Program Name started.

EXPLANATION:
The Fault Model program specified in the message has been invoked.
USER RESPONSE:
INFO (TFM-462): Program Name completed.

EXPLANATION:
The Fault Model program specified in the message has completed.
USER RESPONSE:
INFO (TFM-701): Hierarchical | <blank> Fault Statistics for Global |

Testmode Testmode_name Experiment Experiment_name:
EXPLANATION:
Test Coverage Definitions:
Testmode: Test coverage for a specific test mode.

Global: Test coverage for all faults, independent of any test modes
Total: Number of Active Faults (observable).
Tested: Number of Active Faults marked tested.
Possibly: Number of Active Faults marked possibly tested
(good value is 0 or 1; fault value is X)
Redundant: Number of Active Faults untestable due to redundancy.
Untested: Number of Active Faults untested.
TCov (%Test Coverage): Tested / Total
ATCov (%Adjusted TCov): Tested / (Total-Redundant)
PCov (%Possibly Detected Coverage) : (Tested+Possibly) / Total
APCov (%Adjusted PCov): (Tested+Possibly) / (Total-Redundant)
USER RESPONSE:
None.
INFO (TFM-702): Possibly Testable at Best Fault Statistics and Reasons Report for Global
| Testmode Testmode_name Experiment Experiment_name:
EXPLANATION:
PTAB (Possibly Tested At Best) Coverage Definitions:
Testmode: test coverage for a specific test mode.
Global: test coverage for all faults, independent of any test modes.
3-state: Number of faults classified as 3-state PTAB.
TIE X: Number of faults classified as TIE X PTAB.
CSO: Number of faults classified as Clock-stuck-off PTAB.
USER RESPONSE:
None.
INFO (TFM-704): Maximum Global Test Coverage Statistics:

EXPLANATION:

Statistics for faults that are not active in any test modes and maximum test coverage
attainable with the current set of test modes:
Definitions:
#Faults : Number of Faults defined (independent of test modes).
#Active : Number of Faults Active in at least one mode.
#Inactive: Number of Faults Inactive in all modes.
%%Active : #Active/#Faults = Maximum Test Coverage attainable.
USER RESPONSE:
None.
INFO (TFM-705): Global | Testmode Testmode name Experiment

Experiment name Fault List:
EXPLANATION:
Status key: ^ = inactive r = reduced (uncollapsed)
I= ignored (unclassified)
IT = ignored (tied)
IU = ignored (unconnected)
IB = ignored (blocked)
* = redundant q = iddq tested
u = untested p = possibly tested
T = tested t = tested in another mode
! = ATPG Untestable:
!ud = undetermined reason !co = clock-stuck-off
!3s = 3-state contention !nt = non-terminated 3 state
!mc = multi-clock !so = SOS conflict
!cc = clock-not-chopped !pm = PMU conflict
!lh = user linehold !tg = Test gen constraint
!xs = X-source !cp = correlated pin

!st = TG state !nc = non-contacted pin

!sq = sequential conflict !g0 = global term 0
!g1 = global term 1 !gn = global term none
!cz = clock req at Z !ac = delay or timing constraint
!fb = feedback !cl = clocking constraint
!nl = flush non-scan latch !ti = tied value
!nr = not controllable (a priori)
!no = not observable (a priori)
!nd = no delay test path (a priori)
!tl = tester load (a priori)
A = Aborted
P = 3-state possibly tested at best (PTAB)\n\
X = Tie-X PTAB\n\
C = clock-stuck-off PTAB\n\
Type key:
& = AND Grouped | = OR Grouped
ISA0 = stuck-at-zero fault on an input pin
ISA1 = stuck-at-one fault on an input pin
ISR = slow-to-rise fault on an input pin
ISF = slow-to-fall fault on an input pin
OSA0 = stuck-at-zero fault on an output pin
OSA1 = stuck-at-one fault on an output pin
OSR = slow-to-rise fault on an output pin
OSF = slow-to-fall fault on an output pin
DPAT = dynamic pattern fault
SPAT = static pattern fault
DRV0 = driver fault driving stuck-at-0

DRV1 = driver fault driving stuck-at-1

RCV0 = receiver fault receiving stuck-at-0
RCV1 = receiver fault receiving stuck-at-1
PSH0 = net shorted to 0 fault
PSH1 = net shorted to 1 fault
IDDQ0= Iddq logic 0 fault
IDDQ1= Iddq logic 1 fault
QPAT = Iddq pattern fault
USER RESPONSE:
None.
INFO (TFM-706): Global | Testmode Testmode name Experiment

Experiment name Path Fault List: \n
EXPLANATION:
Status key: Not Processed = Fault has not yet been processed
Tested Hazard Free = Fault tested as hazard free
Tested Robust = Fault tested as robust
Tested Near Robust = Fault tested as nearly robust
Tested Non-Robust = Fault tested as non-robust
Aborted = ATPG aborted
Untestable = No test possible for this fault
Untestable Near Robust = Nearly robust ATPG tried and failed
Untestable Robust = Robust ATPG tried and failed
Untestable Hazard Free = Hazard free ATPG tried and failed
USER RESPONSE:
None.
INFO (TFM-707): Prepare Core: Migration Faults: OMIT statements written to core fault rule:
%ld

OMIT statement count

EXPLANATION:
This informational message indicates the number of OMIT statements created by this
invocation of prepare_core_migration_faults. This represents core EXTEST
faults that have been tested at the core level which do not need to be tested again at the
chip level, and thus will be omitted from the chip level fault model.
USER RESPONSE:
None.
INFO (TFM-708): Prepare Core Migration Faults: Fault count statements written to macro
fault rule:
EXPLANATION:
This informational message indicates the fault count statements created by this
invocation of prepare_macro_migration_faults. This represents core INTEST
faults whose counts will be migrated from the core level to the chip level fault model. The
faults will not exist at the chip level.
USER RESPONSE:
None.
ERROR (TFM-709): Prepare Core Migration Faults: Unable to load Core Migration Model
data. Probable cause: Core migration model does not exist. Run
build_core_migration_model.
EXPLANATION:
This message indicates that prepare_core_migration_faults was unable to load
data required to figure out which faults are in the core migration model. The most likely
cause is that the core migration model has not been built.
USER RESPONSE:
If core migration model does not exist, Run build_core_migration_model,
the re-run prepare_core_migration_faults. Otherwise, contact Customer
Support (see Contacting Customer Service on page 23).
INFO (TFM-712): No domain clock |clock_pairs | faults found for testmode

| test_sequence | clock_constraints_file |
dynamic_sequence_filter name.
EXPLANATION:

No faults were able to be identified for the domain search criteria entered.
USER RESPONSE:
Choose different clock constraints file or test sequence or dynamic sequence filter and
run the report again. Make sure that the test mode has clocks defined.
WARNING (TFM-717): During commit operation on this core migration fault model, num
faults tested in other test modes faults have been found to be tested by patterns in this
experiment that are already tested in another test mode. Migration pattern count may be
excessive.
EXPLANATION:
This message indicates that the commit process saw faults marked tested by patterns in
this experiment that are known to be tested in another test mode. Steps are being taken
to prevent double counting of faults during the core to chip migration process, but this is
an indication that more patterns will be migrated than are necessary, if the other mode is
a migration mode, resulting in an inflated pattern count at the chip level. This is most
likely caused by running a test generation experiment in one test mode and not
committing the experiment before starting another test generation experiment in another
test mode.
USER RESPONSE:
It is recommended, but not required, to commit tests for one core migration test mode
before running test generation in another migration test mode.
ERROR (TFM-718): Core migration fault processing cannot be done. Test mode test
mode name is not a core migration test mode.
EXPLANATION:
This message indicates that prepare_core_migration_faults was run on a test
mode that is not a core migration test mode. A core migration test mode is a test mode
built with a modedef statement indicating scan type boundary=migrate.
USER RESPONSE:
Re-run prepare_core_migration_faults on a core migration test mode.
ERROR (TFM-719): Core migration fault processing cannot be done. Attempting to append
to a coreFaultRule file for test mode test mode name that has already been migrated.
EXPLANATION:
In order for the chip fault counts to be correct, it is required that each core migration test
mode be prepared for migration only once. If any migration test mode needs to be re-

processed, append=no should be specified and

prepare_core_migration_faults will need to be run again on each migration test
mode.
USER RESPONSE:
Re-run prepare_core_migration_faults on this test mode with append=no or
with a core migration test mode that has not been processed yet (with append=yes).
WARNING (TFM-721): [Severe] Chip level migration of core instance tested statistics
cannot be done. Experiment | Test Mode statistics not available.
EXPLANATION:
The core instance fault statistics do not exist. It is possible that the test pattern migration
utility was run on a chip that does not contain cores with migration data prepared.
USER RESPONSE:
Make sure the test pattern migration utility was run on a chip that contains core with
migration data prepared. Otherwise, contact customer support (see Contacting
cannot be done. Core instance block index hierarchical block index is not flagged
as a migration core.
EXPLANATION:
An internal program error has occurred. It is possible that the test pattern migration utility
was run on a chip that contains cores that have not had migration data prepared.
USER RESPONSE:
migration data prepared. Otherwise, contact customer support (see Contacting
cannot be done. No core instance fault statistics found for Core instance block index
hierarchical block index.
EXPLANATION:
An internal program error has occurred. It is possible that the test pattern migration utility
was run on a chip that contains cores that have not had migration data prepared.
USER RESPONSE:

migration data prepared. Otherwise, contact customer support(see Contacting
WARNING (TFM-724): Static | Dynamic |Global Static | Global

Dynamic migrate tested fault count migrate tested fault count for core instance
block index hierarchical block index name: previously migrated tested
count, when added to existing tested count, exceeds maximum allowed based on core
committed data. Maximum count of core committed fault count will be used
instead.
EXPLANATION:
Migration of patterns for the core instance shown is exceeding the tested count that was
committed at the core level. The committed count at the core level is the count that will
be used in order to prevent going over 100% tested for this hier block.
USER RESPONSE:
Verify that the same set of test patterns are not being migrated more than once.
WARNING (TFM-725): coreFaultRule file core migration path file name not
found.
EXPLANATION:
The coreFaultRule specified in the message was not found. This is a file that should
reside in the core migration directory that was created by
prepare_core_migration_faults on a core model whose migration model is
included in the chip that this build_faultmodel run is being run on. The most
probable cause is that COREMIGRATIONPATH was not specified correctly. It must be the
path to the directory containing the Core Verilog Module Name subdirectories that
contain the core migration data, not including the actual module name in the path. Refer
to the help text for the COREMIGRATIONPATH keyword for more details.
USER RESPONSE:
Correct the COREMIGRATIONPATH keyword and re-run build_faultmodel on the
chip.
ERROR (TFM-726): Errors occurred in core migration fault rule filename processing.
See previous messages for details. The fault model has not been created.
EXPLANATION:
Hierarchical Test Chip-level Build Fault Model core migration fault rule processing
encountered syntax or semantic errors. Since the file is created with

prepare_core_migration_faults at the core level, there should not be any errors.

Therefore Build Fault Model ends without creating the fault model, rather than creating a
fault model with missing data. The most likely cause is specifying an incorrect
COREMIGRATIONPATH.
USER RESPONSE:
Correct the errors shown in the previous messages (especially any problems with
COREMIGRATIONPATH) and re-run build_faultmodel on the chip.
INFO (TFM-731): Remove Alternate Fault Model(s) started.

EXPLANATION:
Remove Alternate Fault Model has been invoked to remove the specified alternate fault
models.
USER RESPONSE:
ERROR (TFM-732): Remove Alternate Fault Model(s) requires the altfault keyword to
identify an alternate fault model to be deleted.
EXPLANATION:
Remove Alternate Fault Model will only delete user-specified alternate fault models.
USER RESPONSE:
Identify the alternate fault model using the altfault=altfault argument and rerun.
WARNING (TFM-733): [Severe] Alternate fault models cannot be opened for commit.
ALTFAULT=alternate_fault_model_name.
EXPLANATION:
The commit operation is intentionally prevented for experimental data derived from
alternate fault models.
USER RESPONSE:
INFO (TFM-734): Alternate fault model alternate_fault_model_name has been

removed.
EXPLANATION:
The specified alternate fault model has been successfully deleted.

USER RESPONSE:
WARNING (TFM-735): [Severe] Alternate fault model

alternate_fault_model_name has NOT been removed. See preceding message(s)
for details.
EXPLANATION:
The specified alternate fault model has NOT been successfully deleted.
USER RESPONSE:
Ensure that you have the correct permissions to the directory containing the design and
to the individual files in that directory.
WARNING (TFM-736): [Severe] Alternate fault model

alternate_fault_model_name does not exist.
EXPLANATION:
The specified alternate fault model does was not found, and therefore cannot be deleted.
USER RESPONSE:
Ensure the specified alternate fault model is correctly spelled and then rerun.
(highest return code for the run) (TFM-737): Encounter Test Remove Alternate
Fault Model has removed number_removed of the number_requested requested fault
models.
EXPLANATION:
This summary of the alternate fault model remove operation is provided upon
completion.
USER RESPONSE:
WARNING (TFM-750): Unable to obtain hier block stats for block hier index
EXPLANATION:
The program is unable to compute the hierarchical block statistics for the identified block.
Processing continues for any additional hierarchical blocks remaining to be printed.
USER RESPONSE:

The most likely cause of this problem is an internal program problem which can be
reported to customer support (see Contacting Customer Service on page 23).
ERROR (TFM-751): Hierarchical Block TG Effectiveness fault statistics not supported.

EXPLANATION:
Test Generation Effectiveness fault statistics are not supported for hierarchical blocks.
USER RESPONSE:
Re-run without specifying the hierblocks or hierstart command or without the TG
Effectiveness option (remove -f).
ERROR (TFM-752): Hierarchical Block fault statistics not supported for Comets.
EXPLANATION:
Hierarchical Block fault statistics are not supported for Comets. The program exits.
USER RESPONSE:
Rerun without specifying the hierblocks or hierstart command or without the comet
command.
ERROR (TFM-753): [Internal] Bad return code received from TFMcometStatistics.

EXPLANATION:
A program error occurred during computation of Comet fault statistics. Processing
terminates.
USER RESPONSE:
ERROR (TFM-754): Only one value for keyword reporttype can be selected - static,
dynamic, or iddq for Hierarchical Block fault statistics.
EXPLANATION:
report_fault_statistics Hierarchical Fault Statistics is only supported for one of
the three values for reporttype keyword: static or dynamic and these values are
not allowed simultaneously.
USER RESPONSE:
Rerun with reporttype=static or reporttype=dynamic or reporttype=iddq.

ERROR (TFM-755): Rows parameter must be totalstatic, totaldynamic or iidq

for Hierarchical Block fault statistics.
EXPLANATION:
report_fault_statistics Hierarchical Fault Statistics is only supported for
rows=totalstatic or rows=totaldynamic or iddq.
USER RESPONSE:
Rerun with rows=totalstatic or rows=totaldynamic or rows=iddq.
WARNING (TFM-757): Iddq is not allowed with other fault types on the faulttype keyword.
Processing continues using iddq only.
EXPLANATION:
iddq faults cannot be included with other faults in the same fault list. They must be listed
by themselves, primarily because there are no unique faults created for Iddq testing.
They are represented by the static fault set with a separate fault status for Iddq. The run
continues with just iddq selected.
USER RESPONSE:
No response is necessary. Specify faulttype=iddq alone to get rid of this message.
INFO (TFM-758): Fault Model Build excluded total Scan Faults excluded
(uncollapsed) scan faults.
The number of static (uncollapsed) faults excluded = static scan faults excluded.
The number of dynamic (uncollapsed) faults excluded = dynamic scan faults
excluded.
EXPLANATION:
This message defines how many scan faults were excluded from the fault model. These
are faults that are deemed testable via the scan chain test. The first number shown is the
total number of faults excluded. The next two lines show the breakdown of static and
dynamic faults excluded. The total number is the sum of the static and dynamic numbers.
USER RESPONSE:
WARNING (TFM-760): These fault statistics are not accurate because some of the tests are
removed and the experiment has not yet been resimulated. Rerun fault simulation on this
experiment to obtain accurate statistics.
EXPLANATION:

Some command (such as delete_testrange) has removed some tests from the
experiment, but the experiment has not yet been rerun through fault simulation. The test
vectors no longer match the fault coverage statistics.
USER RESPONSE:
the fault coverage. If the experiment was committed (via the force option), run
simulate_vectors or analyze_vectors on the committed tests.
INFO (TFM-770): fileName has invalid file format. reason Processing continues without
the fileName data.
EXPLANATION:
Named file appears to have incorrect or unexpected data. Processing continues without
the use of this files data.
USER RESPONSE:
ERROR (TFM-771): [Internal] message text

EXPLANATION:
This programming error message is being printed to aid in programmer debug. An
unexpected flow has occurred, but processing is unaffected.
USER RESPONSE:
the design for analysis.
ERROR (TFM-777): All fault type filtering keywords have been set or defaulted to no. No
fault list can be produced. Set one or more of the type keywords to yes and rerun
report_faults.
EXPLANATION:
One or more type-related keywords (for example, typestatic) has been specified to
no and all unspecified type-related keywords default to no. Therefore, no faults will be
included in the fault list and the program exits.
USER RESPONSE:
Change the specification of at least one of the type-related keywords to yes and rerun
report_faults.

WARNING (TFM-778): Could not obtain write lock to fileName file. Not written nor
removed.
EXPLANATION:
File permissions would not allow a write lock on the named file or another program has
the file in use. The file cannot be written or removed.
USER RESPONSE:
Refer to previous TFW message to understand why lock could not be obtained.
WARNING (TFM-779): Problem opening file fileName. The file is not written.
EXPLANATION:
fopen failed on the named file.
USER RESPONSE:
Obtain the necessary file permissions.
WARNING (TFM-801): Program bug: incorrect LPRA width found for LPRA NNN
EXPLANATION:
Program bug
USER RESPONSE:
ERROR (TFM-803): Invalid parameters specified. See previous TFW messages.

EXPLANATION:
See TFW messages about invalid input specifications.
USER RESPONSE:
Correct input.
ERROR (TFM-809): Unable to load the model for tracing.

EXPLANATION:
Application was not able to load the model. The program exits.
USER RESPONSE:

Determine and fix whatever caused the application to fail when attempting to load the
model and then rerun the application.
WARNING (TFM-810): Problem deleting file fileName.

EXPLANATION:
Deletion of specified file was not successful. A text string following the message should
provide a hint as to why this failed. The file may have been deleted by accident or the file
access permissions may not allow the deletion of the file.
USER RESPONSE:
Take appropriate action based on the information text string and rerun if necessary.
WARNING (TFM-811): pipelinedepth parameter pipelinedepth value exceeded

while processing measure register measure register number, testmode OPMISR
test mode name. No core found. Moving on to the next measure register.
EXPLANATION:
For each testmode specified in the rowtestmodes keyword, measure registers are
processed to locate the core instances for the modules specified. The pipelinedepth
keyword controls how many bits of the measure register to process without successfully
locating a core instance before giving up and moving on to the next measure register.
USER RESPONSE:
Determine if a valid core instance is being missed for processing. Increase the
pipelinedepth or make sure that valid core module(s) have been specified either via
ET_CORE=PG attributes on module definitions in the model or via the coremodules
keyword.
ERROR (TFM-812): No fault data processing was done in row 1 testmode name. No
markoff will be performed in subsequent rows.
EXPLANATION:
No fault data processing was done for row 1. Therefore no markoff will be done in the
subsequent rows.
USER RESPONSE:
Check for previous messages, fix the problem and re-run. Check for valid specification
of rowtestmodes, coremodules, and pipelinedepth keywords. Make sure that the
first test mode specified is the row 1 test mode that has committed ATPG fault status.

INFO (TFM-813): Fault fault id (relative node node id relative to hier

block, relative fault fault id relative to flat node) is not active in row test
mode row test mode name, therefore no has been status applied.
EXPLANATION:
A fault that was processed and had either tested, possibly tested, or redundant status in
the row 1 test mode was found to be inactive in the subsequent row test mode shown.
Therefore this same relative fault in the same column in a subsequent markoff row test
mode will not have the status applied to it in that particular core instance.
USER RESPONSE:
None required, purely informational. However if this is unexpected, examine the test
mode definition to figure out why an inactive fault is inactive. Look for Test Inhibits. If the
fault is ignored, check for tie blocks or unconnected logic.
INFO (TFM-814): No use of scan-out pin Scan-out pin name was found in row test
mode row test mode name.
EXPLANATION:
In the column associated with the scan-out pin name shown, no core instance was found
in the row test mode shown.
USER RESPONSE:
None required, purely informational. However if this is unexpected, examine the logic
model or row test mode to see if a core instance has a problem with the scan chain
measure register.
ERROR (TFM-815): In row test mode row test mode name, scan out pin Scan-out
pin name is used by core block core instance block name but was not used in a
prior row.
EXPLANATION:
For rows 2 - n, it is expected that if a row does not have a core instance in a particular
column (identified by the scan-out pin) that exists in row 1, then all subsequent rows will
also not have a core instance in that same column. If a core instance is encountered it
will be identified as an error by this message and will not be processed for fault markoff.
USER RESPONSE:
Fix the core instance problem(s) and re-run copy_row_faultstatus.
ERROR (TFM-816): No valid core modules have been specified.

EXPLANATION:
Core modules can be identified either by attribute ET_CORE=PG on a module definition
or by the coremodules keyword (one or the other, not both). If neither of these options
is specified, there will not be anything to process and the run will end without any fault
markoff.
USER RESPONSE:
Either specify the core module(s) to be processed via the coremodules keyword of this
command or place ET_CORE=PG attributes on the module definition(s) in the logic model.
ERROR (TFM-817): No signature observation test mode found for MISR observe row test
mode row test mode name.
EXPLANATION:
For the row test mode name shown that was specified as one of the test modes on the
rowtestmodes keyword, it is expected that this is a MISR observe test mode that will
have a signature observation (child) mode, but no signature observation mode was
found. The signature observation mode is used to locate the core instances by going
through the measure register bits and ascending the hierarchy to find the core module.
Without this information the core instances cannot be located and fault markoff cannot
be performed. If this row test mode is for rows 2 - n, this row will be skipped and
subsequent rows will be attempted to be processed. If the row test mode is for row 1,
the run will end with no processing done since row 1 is the ATPG markoff testmode to be
propagated to the other rows.
USER RESPONSE:
Build a signature observation test mode for the MISR observe test mode shown or make
sure that the correct test modes have been specified on the rowtestmodes keyword,
then re-run copy_row_faultstatus.
WARNING (TFM-818): Unrecognized value attribute value for ET_CORE attribute for
module module name.
EXPLANATION:
copy_row_faultstatus looks for ET_CORE attributes on module definitions if the
coremodules keyword is not specified. The expected value is PG. A module definition
was found for a module definition but with a different value shown in this message. The
module will not be processed.
USER RESPONSE:
Determine if this was a module that was intended to be processed. If so, correct the
attribute value and re-run copy_row_faultstatus.

ERROR (TFM-819): Only one row was specified in the rowtestmodes keyword. No
markoff will be performed in any rows.
EXPLANATION:
Only the row 1 testmode was specified, which is the row that is expected to have the
committed ATPG fault status that is to be migrated to the other row test modes' core
instances.
USER RESPONSE:
Re-run copy_row_faultstatus specifying at least 2 testmodes. The first should be
the ATPG row with committed fault status. The subsequent row test modes are the rows
that are to have fault status migrated to.
INFO (TFM-850): Scan Corrupted memory found. blockName This may result in lower
dynamic test coverage.
EXPLANATION:
Memories that can be clocked during the scan operation are harder to test because the
scan chains cannot be reloaded between memory operations. The
create_logic_delay_tests command reloads between memory operations if
singleload=no is specified.
USER RESPONSE:
Disable the memory during scan to allow scans between memory operations.
INFO (TFM-851): Memory blockName was not built by build_memory_model

Encounter Test version 6.2.4 or later is required to perform this function, No faults from this
ram will be included in the fault subset.
EXPLANATION:
For a fault subset to select the memory input and output faults, the memory model must
be built with Encounter Test version 6.2.4 or later and include a ram primitive(s).
USER RESPONSE:
Rebuild the memory model using Encounter Test version 6.2.4 or later and include a ram
primitive(s).
INFO (TFM-852): No fault subset was created.

EXPLANATION:
No memories were generated. Use Encounter Test version 6.2.4 or later and include a
ram primitive.

USER RESPONSE:
Rebuild the memory model using Encounter Test version 6.2.4 or later and include a ram
primitive(s).
WARNING (TFM-900): [Severe] Unable to obtain storage required for random fault list.
EXPLANATION:
The program is trying to generate a random list of untested faults. In order to create this
list, Build Fault Model requires more storage than what is available.
USER RESPONSE:
If other applications are running on the same CPU as Build Fault Model, try to rerun Build
Fault Model when there is more storage available.
INFO (TFM-901): Fault Status Statistics for faults included in this fault list:
EXPLANATION:
Summary of the status of the faults shown in the fault list based on the criteria provided
to create the fault list. This is only for the faults in the list. It is NOT a summary of all
faults in the design.
USER RESPONSE:
None.
WARNING (TFM-999): PTAB fault being marked tested. Fault ID: fault index
EXPLANATION:
This is a software debug message strictly intended for development use.
USER RESPONSE:


31
TFS - Test Simulation Messages
TFS-001 through TFS-454 on page 1077

TFS-001 through TFS-454

INFO (TFS-001): Simulator run controls:
EXPLANATION:
This message is intended to provide information and does not indicate an error condition.
All simulator control options are listed, both those which were specified and those which
were defaulted.
USER RESPONSE:
INFO (TFS-002): Heartbeat number, Time of day, Date, TBD location, Status counts.
EXPLANATION:
This message is intended only to provide information and does not denote an error
condition. It is a "how goes it" or "Heartbeat" message whose purpose is to let the user
monitor the progress of an General Purpose simulation run. The message appears each
n minutes, and is controlled by the heartbeat=n General Purpose simulation keyword.
The default is heartbeat=6, which gives 10 messages per hour of elapsed time. The
first TFS002 message of each run prints an explanation of the short abbreviations used
in the 1 line message. SC, for SimCalls, is the number of time the core simulator has
been invoked. SC increments by 1 for a stim event, by 2 for a pulse event. FG, for fault
group, is the fault pass or fault group number. An active RAM word is a RAM
word(address) which has been written into.

USER RESPONSE:
Use the Heartbeat stats to predict how long the run will take.
INFO (TFS-003): GPsim CheckPoint checkpoint_number taken at time

EXPLANATION:
This message is intended to provide information and does not indicate an error condition.
The sequence number and time-of-day of General Purpose simulation checkpoint
information is recorded.
USER RESPONSE:
INFO (TFS-004): End TBD entity

EXPLANATION:
The first 4 columns give the number of simcalls at which n nets were at a given value. A
stim event is 1 simcall; a pulse is 2 simcalls. For example if column 1 (#0) is 4 that could
mean that 1 net was at Logic 0 for 4 simcalls, or that 2 nets were at Logic 0 for 2 simcalls,
etc.
Columns 5 and 6 count the number of net transitions form 0 to 1, and 1 to 0.
USER RESPONSE:
INFO (TFS-005): Net Activity List

EXPLANATION:
Net activity listing sorted by flat net index. The first 4 columns give the number of simcalls
at which a net was at a given value. A stim event is 1 simcall; a pulse is 2 simcalls. For
example if line 7 has a 4 in column 1 it means that net 7 was at logic for 4 simcalls,
Columns 5 & 6 count the number of net transitions form 0 to 1, and 1 to 0.
USER RESPONSE:
INFO (TFS-098): The total number of RAM words is number of RAM words. The total
number of RAM bits is number of RAM bits.
EXPLANATION:

The message states the number of RAM words and bits during the run. This information
is produced if a messagelevel greater than 2 is specified.
USER RESPONSE:
INFO (TFS-100): START or RESTART the GP Simulator at time .

EXPLANATION:
General purpose simulation is beginning.
USER RESPONSE:
INFO (TFS-101): Loaded RAMs or Latches from the Contents File.

EXPLANATION:
The message indicates the data loaded from the RAM or Latches Contents file.
USER RESPONSE:
INFO (TFS-102): Wrote RAMs or Latches into the Contents File.

EXPLANATION:
The message indicates the RAM or Latches data written to the Contents file.
USER RESPONSE:
INFO (TFS-222): A linehold violation has caused a test pattern to be removed.

EXPLANATION:
One or more linehold violations has resulted in the test pattern in which it was found to
be removed from the TBDbin data. Message TFS-223 describes the violation.
USER RESPONSE:
Review message TFS-223 for details of the linehold violation(s).
WARNING (TFS-223): Linehold violation at net_name (hierIndex at

input_TBD_odometer).

EXPLANATION:
The message indicates that a linehold was not honored in the stimulus at a PI or latch.
This may occur on compression test modes with input decompression.
USER RESPONSE:
If needed, correct the linehold violation and rerun; otherwise, no response is required.
WARNING (TFS-285): [Severe] This 1149.1 mode requires an update_dr operation in the
form of load suffix patterns. A Scan_Load or Skewed_Scan_Load was found that was not
followed by the required load suffix patterns.
EXPLANATION:
Based on the mode statistics, each pattern containing a Scan_Load or
Skewed_Scan_Load event must be followed by the update_dr operation. This is
indicated by patterns with the load suffix pattern sequence attribute. This message is
printed each time the required patterns are missing.
USER RESPONSE:
If this error occurs during simulation of a user-imported Vectors file, ensure that the load
suffix sequence patterns follow each pattern containing a Scan_Load or
Skewed_Scan_Load event, and re-import the patterns to correct the problem.
If user-imported data is not being simulated contact customer support (see Contacting
INFO (TFS-301): The dynamic type constraint placed on netname (flatmodel index
nodeID) has been violated.
EXPLANATION:
The simulator detected that the specified model object violated the constraint placed on
it. The test pattern will either be removed or the design fed by the object will be ignored
by simulating X. Message TFS-302 or TFS-303 will describe the action taken as a result
of this violation.
USER RESPONSE:
INFO (TFS-302): A constraint violation has caused portions of the design to be ignored.
EXPLANATION:
One or more constraint violations has resulted in the design fed by the object to ignored
by simulating X. Message TFS-301 describes the constraint violated.

USER RESPONSE:
INFO (TFS-303): A constraint violation has caused a test pattern to be removed.

EXPLANATION:
One or more constraint violations has resulted in the test pattern in which it was found to
be removed from the Vectors data.
USER RESPONSE:
WARNING (TFS-395): The Fault Selection Word specified that TFS load IDDQ faults. But
since TFS does not simulate IDDQ faults, they were not loaded.
EXPLANATION:
The Fault Selection Word (FSW) passed to the GP simulator specifies that simulator read
in the IDDQ faults. Since the simulator does not handle IDDQ faults, reading them in
would be a waste of time & space. The FSW is set by the user with the GUI. This
message is intended to warn the user that a requested fault type was not simulated.
USER RESPONSE:
WARNING (TFS-401): [Severe] The following number of active clock nets

Primary Inputs clocks were active during Stim or Pulse event at odometer. Simulation will be
done with the clocks overlapped. There may be incorrect results if there are races in the
design.
list of violating clocks

EXPLANATION:
USER RESPONSE:

There are two different approaches that can be taken:

INFO (TFS-405): The Fault Selection Word specified that General Purpose simulation load
IDDq faults. General Purpose simulation does not simulate IDDq faults and they were not
loaded.
EXPLANATION:
This message indicates that the IDDq fault type was requested however General
Purpose simulation does not simulate IDDq faults and no IDDq faults were loaded.
USER RESPONSE:
INFO (TFS-406): Start fault group a fault group number of total number of
fault groups. Selected number of faults in this group faults for simulation.
EXPLANATION:
General Purpose simulation includes a multipass capability that adjusts the simulator
memory requirements according to the available memory. This message indicates that a
subset of the faults is being simulated against the current pattern set.
The fault group number field indicates which fault pass is about to start.
The total fault group number field indicates how many fault passes will be
required to simulate all the faults against the current pattern set (typically a test
procedure).
The number of faults field indicates how many faults will be simulated in this
pass.
USER RESPONSE:
INFO (TFS-407): Start good machine pass. All faults have either been detected or otherwise
dropped from the simulation.
EXPLANATION:

This message appears during a fault simulation when no faults remain to be simulated.
This can occur if all the faults have been either detected or dropped from simulation. A
typical reason for dropping a fault (aside from detection) would be that the fault was
consuming too much memory and/or run time.
USER RESPONSE:
INFO (TFS-408): Start good machine pass.

EXPLANATION:
This message appears when a good machine only simulation is being performed.
USER RESPONSE:
INFO (TFS-409): Start overflow pass number. Selected number overflowed faults for
simulation.
EXPLANATION:
This message appears when the simulator was unable to completely simulate all the
faults against the current set of patterns in the predicted number of passes due to a lack
of memory. Additional passes are performed against the overflowed faults. The pass #
field specifies the number of this overflow pass. The # faults field specifies how many
overflowed faults will be attempted in this pass.
USER RESPONSE:
INFO (TFS-410): End fault group fault pass(group) number. Completed number
of faults this pass faults. Total number of faults thus far.
EXPLANATION:
General Purpose simulation includes a multipass capability in order to adjust the
simulator memory requirements to the available memory. This message indicates that a
subset of the faults has completed simulating against the current pattern set. The pass
# field indicates which fault pass has completed. The # pass faults field indicates
how many faults were completed in this pass. The # total faults field indicates how
many faults have been completed for all passes performed thus far.
USER RESPONSE:

INFO (TFS-411): End good machine pass.

EXPLANATION:
A good machine only simulation of fthe current pattern set has completed.
USER RESPONSE:
INFO (TFS-412): Simulation results will be appended to experiment name of

experiment.
EXPLANATION:
This message is only intended to provide information and does not denote an error
condition.
USER RESPONSE:
INFO (TFS-415): Starting simulation of a tsect type TEST SECTION at TBD location
tbd location. The test type is test type. The tester termination is tester term.
domination term
EXPLANATION:
The message indicates that simulation of a test section is about to begin, and denotes
some attributes of the test section.
USER RESPONSE:
INFO (TFS-419): Test Procedure Test procedure number is empty (no test
sequences).
EXPLANATION:
The referenced test procedure has no test sequences to simulate.
USER RESPONSE:
Verify the test procedure by printing the input vectors.
INFO (TFS-420): Starting simulation of the pattern group at TBD location tbd
location. reset boundary information
EXPLANATION:

The message indicates that simulation of a group of patterns is about to begin. The
pattern group field denotes what the group consists of, for example, a test
procedure.
A pattern group is the set of patterns on which multipass simulation is
performed.
The TBD location indicates where in the input vector the pattern group is
located.
Reset boundary indicates where if any memory exists in the input vectors.
USER RESPONSE:
WARNING (TFS-430): FaultSim was SUSPENDED at input TBD location tbd

location/iteration due to Key Word Keyed Data with an iteration count of
iteration.
EXPLANATION:
This message is a reminder that the input patterns contain a suspend fault simulation
control on a Test Sequence.
<suspendFaultSimulation=n> will cause fault simulation to be suspended at the nth
iteration of a Test Sequence. If the control is used on a non looping sequence, the
iteration number should be set to 1.
This control results in inaccurate fault and incomplete fault simulation.
USER RESPONSE:
WARNING (TFS-431): FaultSim was RESUMED at input TBD location tbd location/
iteration due to Key Word Keyed Data with an iteration count of iteration.
EXPLANATION:
This message is a reminder that the input patterns contain a resume fault simulation
control on a Test Sequence. <resumeFaultSimulation=n> will cause fault simulation to be
resumed at the nth iteration of a Test Sequence. If the control is used on a non looping
sequence, the iteration number should be set 1.
This control results in inaccurate fault & incomplete fault simulation.
USER RESPONSE:

No response required,
INFO (TFS-450): Initial Simulator State restored from file name.

EXPLANATION:
condition. The message indicates that the design state has been restored from the
uncommitted file filename.
USER RESPONSE:
INFO (TFS-451): Final Simulator State saved to file name.

EXPLANATION:
condition. The message indicates that the General Purpose simulation design state has
been saved to the uncommitted file filename.
USER RESPONSE:
WARNING (TFS-452): [Severe] Restore States error. diagnostic.

EXPLANATION:
This message means that an error was detected while reading TFSstate (the saved state
file) for an General Purpose simulation restore state operation. The diagnostic field
indicates the nature of the error. Typically, errors are introduced into the saved state file
when the file is edited.
USER RESPONSE:
First, verify that the file filename does exist. The error might be as simple as entering
the wrong name. If not, and the saved state file was edited, use the diagnostic message
to determine where the error was introduced. Then correct the problem in the file and run
the simulation again. If the saved state file has not been edited since it was created by
the simulator and your filename is correct, contact customer support (see Contacting
WARNING (TFS-453): Save States error. diagnostic. Save not done.

EXPLANATION:

A failure occurred while attempting to create or write to the simulator save state file
TFSstate. The diagnostic field indicates the nature of the error.
USER RESPONSE:
Check the WORKDIR directory and ensure that you have sufficient access authority to
create files therein.
ERROR (TFS-454): Unexpected End of Restore File. Processing terminates.

EXPLANATION:
The end of the saved state file (TFSstate) was encountered prematurely during an
General Purpose simulation restoreState. Expected data is missing.
USER RESPONSE:
The TFSstate file was corrupted, probably by a user edit of the file. If so, the user should
attempt to repair the damage with another edit. Consider creating a backup file before
doing an edit. If the saved state file was not edited since it was created by the simulator,
please contact customer support (see Contacting Customer Service on page 23).

ERROR (TFS-500): The value parameter value specified for control parameter parm
is not valid. Valid values for this parameter are value range. The default is value.
EXPLANATION:
The value specified for the simulator parameter parm is not an acceptable value.
USER RESPONSE:
Specify a different value for the indicated parameter in the range value range. Refer to
"analyze_vectors in the Encounter Test: Reference: Commands for additional
information.
ERROR (TFS-501): Unrecognized keyword keyword following parm simulator

option Processing terminates.
EXPLANATION:
The keyword specified for the simulator parameter parm was not recognized by General
Purpose simulation.
USER RESPONSE:

Use correct keyword (possibly messageCount=)
ERROR (TFS-503): Net watching cannot be performed in conjunction with ineffective

pattern removal. Please turn pattern removal off (writepatterns=all), and run the
simulation again. Processing terminates.
EXPLANATION:
You specified a watchnetsfile or watchallnets in order to record waveform data
for a set of nets. Use of this feature is incompatible with performing ineffective pattern
removal.
USER RESPONSE:
Disable pattern removal
(contentionRemove=no,removeXpo=no,removeXlatch=0
removeIneffective=no) Turn the pattern removal features off and run again. Or, if
you wish to remove patterns and do net watching, make 2 runs. The first run to do pattern
removal, the second to generate watch data.
ERROR (TFS-506): Insufficient memory to continue simulation. Processing terminates.

Failed allocation: allocation name.
EXPLANATION:
There is not enough memory to run this simulation.
USER RESPONSE:
Run the simulation on a machine with more memory or increase the amount of memory
available on this machine.
ERROR (TFS-507): Unable to load the flat design model while action being
performed. Processing terminates.
EXPLANATION:
The simulator was unable to load the design model.
USER RESPONSE:
Verify that the specified settings are correct and that the design model does exist (file
name flatModel). If both are true and the problem persists, contact customer support
WARNING (TFS-509): An unknown primitive type was encountered. The type is block
type, and was found on block block name. The block output(s) will be held at X.
EXPLANATION:

A block function not supported by General Purpose simulation was found on block
block name. The block will not be simulated and its outputs will always be assumed
to be at X. The test coverage achieved for this design may be adversely affected.
USER RESPONSE:
If the specified block type was mistakenly specified, correct the error and run the
simulation again. If the block type was intentionally specified, be aware that the test
coverage predicted may be inaccurate. You may wish to consider modeling the block as
a series of Encounter Test primitives.
WARNING (TFS-510): An invalidly specified primitive type was encountered. The type is
type name, and was found on block block name. The block output(s) will be held at X.
EXPLANATION:
A function type name not supported by General Purpose simulation was found on block
to be at X. The test coverage achieved for the design may be adversely affected.
USER RESPONSE:
If the specified type name was mistakenly specified, correct the error and run the
simulation again. If the type name was intentionally specified, be aware that the test
coverage predicted may be inaccurate.
WARNING (TFS-511): An unsupported primitive type was encountered. The type is block
EXPLANATION:
A block function not supported by General Purpose simulation was found on block
to be at X. The test coverage achieved for this design may be adversely affected.
USER RESPONSE:
ERROR (TFS-513): RAMmach user input error. The number of data bits in the preceding user
input record is not the same as the number of bits in the flat model. The flat model has
data_bits data bits for flat index block_index.
EXPLANATION:

The number of data bits in the input RAMmach record differs from the number in the
flatmodel.
USER RESPONSE:
Correct the RAMmach input record and rerun.
ERROR (TFS-514): The flat index in the preceding ramMach record is not a RAM.
EXPLANATION:
The specified index for a ramMach record is not a RAM.
USER RESPONSE:
ERROR (TFS-515): The data bit(s) in the preceding ramMach record is/are set to an invalid
value.
EXPLANATION:
Valid data bit values are 0, X , 1, or a filler character -.
Example of a valid 6 bit string: 0011X-
Example of a invalid 6 bit string: 0-011Z-
USER RESPONSE:
ERROR (TFS-516): RAMmach user input error. The number of words in the preceding user
input record exceeds the number of words for that RAM in the flat model. The flat model
shows number_of_words words in RAM RAM_net_Index.
EXPLANATION:
The specified number of words in the input RAMmach record exceeds the number in the
flatmodel.
USER RESPONSE:
WARNING (TFS-520): Unable to create the diagnostic failset failset name. No TBDfail
file will be produced by this run. Ensure that the part parameters specified are correct, that
there is sufficient space in the file system and that file permissions are set correctly.
EXPLANATION:

The simulator was unable to create a diagnostic failset for recording miscompare data.
The creation of this data results in a TBDfail file that enables the use of the Encounter
Test and Diagnostics failure analysis tools. The use of these tools will not be possible for
any miscompares that are encountered in this run.
USER RESPONSE:
Ensure that the part parameters specified are correct, that there is sufficient space in the
file system and that file permissions are set correctly. If problems persist, please contact
WARNING (TFS-530): The input TBD has a Tester_Loop with the

procedures_have_memory attribute that contains a Test_Procedure that does not have the
sequences_have_memory attribute. The simulator will proceed as if the
sequences_have_memory attribute were present.
Test_Procedure tbd loc.
EXPLANATION:
It is contradictory to have procedures_have_memory and not sequences_have_memory.
procedures_have_memory implies that the design state is not reset at Test_Procedure
boundaries. However, if sequences_have_memory is not present, the design state will
be reset at every test sequence boundary, i.e., the first Test_Sequence in each
Test_Procedure, which is effectively at the Test_Procedure boundary.
USER RESPONSE:
If the patterns were manually generated, ensure that it is truly the intent to specify
procedures_have_memory. If so, modify your patterns to also specify
sequences_have_memory. If these patterns were generated by a Encounter Test
automatic test generator, please contact customer support (see Contacting Customer
INFO (TFS-550): The table name table overflowed and was reallocated in Memory.
EXPLANATION:
Some TFS table sizes are unpredictable. If the allocated table size is about to be
exceeded, TFS will allocate a larger area, copy the data from the old table to the new and
free the old area.
USER RESPONSE:
If you notice that the reallocation takes place frequently, notify customer support (see
Contacting Customer Service on page 23) so that the initial allocation can be increased
to reduce the chance of overflow and reallocation.

INFO (TFS-575): The following nets and pins will have all change events recorded for them
for the input test pattern range of greater or equal than tbd location and less than tbd
location.
EXPLANATION:
condition. Note that the Stop Odometer setting is adjusted upward from the number
originally entered. This was done for programming simplicity.
USER RESPONSE:
INFO (TFS-576): The following nets and pins will have all change events recorded for them
for the input test pattern range(s) as specified by the input TBD:
EXPLANATION:
condition. The message tells you which nets and pins the simulator will be watching, and
that the starting and stopping of watching will be controlled by WATCH=ON,
WATCH=OFF statements in the input TBD.
USER RESPONSE:
ERROR (TFS-577): There was a READ failure while reading the WatchNets file. The file
may be empty.
EXPLANATION:
The GP simulator run options specified a file which lists the watch nets.The routine which
reads the file returned a bad return code.
USER RESPONSE:
Verify that the watch nets exists and that the file is not empty.
INFO (TFS-580): A watch list was specified but no watch start point was given. Net watching
will begin at location 1.1.1.1 (i.e., the beginning) in the input test patterns.
EXPLANATION:
condition.
USER RESPONSE:

INFO (TFS-585): Net watching action TBD location TBD loc.

EXPLANATION:
condition. The message indicates that General Purpose simulation has either started or
stopped recording net change information (a waveform) at the specified TBD location. If
the start or stop point printed does not exactly match your specified watchstart or
watchstop specification, it means that the location you specified does not exist in the
TBD. Starting or stopping occurs at the next greater location.
USER RESPONSE:
INFO (TFS-600): The GP simulator ended, return code(0). Timestamp: date/time

TFS checksum: TFS_check_sum
EXPLANATION:
condition.
The message indicates that General Purpose Simulation is complete.
USER RESPONSE:

WARNING (TFS-602): The GP simulator ended, return code(2).
WARNINGS were issued during the simulation.
Review the preceding messages to determine the cause.
EXPLANATION:
This message indicates that simulation has completed, but that error messages were
issued during the run.
USER RESPONSE:
Review the error messages that were issued and insure that they do not represent an
unacceptable condition for your test strategy.

WARNING (TFS-603): The GP simulator ended, return code(3).

ERRORS were issued during the simulation.
EXPLANATION:
This message indicates that the simulation did not complete successfully. There were no
valid simulation results generated.
USER RESPONSE:
Review the error messages generated and determine the cause of failure. Take the
appropriate action to correct the error.
WARNING (TFS-604): [Severe] The GP simulator ended, return code(4).

SEVERE ERRORS were issued during the simulation.
EXPLANATION:
condition.
USER RESPONSE:
ERROR (TFS-605): The GP simulator ended, return code(5).

The simulation failed.
EXPLANATION:
condition.
USER RESPONSE:
WARNING (TFS-700): A good machine oscillation was detected on net net name at TBD
location tbd location.
The good machine logic value is set to X on this net.
EXPLANATION:

The indicated net changed value more times than the specified Good Machine
Oscillation limit, gmOsc, for a single event. Typically this indicates that the given net is
part of an oscillating feedback circuit. In rare cases, the specified net may not actually be
oscillating and may legitimately need to change value more times than the gmOsc
parameter.
USER RESPONSE:
If you believe that the design cannot oscillate, try increasing the gmOsc parameter. The
largest possible value for this parameter is 65535.
Simulation run time may increase when this parameter is increased.
INFO (TFS-701): A fault machine osc was detected on net net name hier index
text, fault index fault index, TBD location tbd location.
EXPLANATION:
A fault was detected as causing an oscillation. The faults logic value was set to X to
dampen the oscillation. If increasing fmOsc removes the oscillation, then it was a false
oscillation. False oscillations can reduce test coverage.
This message prints only if the specified msgLevel value is greater than 3.
USER RESPONSE:
If false oscillations are suspected, increase the value for fmosc and rerun.
WARNING (TFS-710): [Severe]| Blank One or more miscompares were detected for
the event_type event at TBD location tbd_location sequence loop ID
pattern loop ID
EXPLANATION:
states expressed in the input TBD patterns vs. design states predicted by General
Purpose simulation. Miscompares may come about in two ways.
First, if the input TBD includes Expect events, General Purpose simulation will compare
the design node values in the Expect event to those currently in General Purpose
simulations design state. If they do not match, a miscompare message is issued.
Second, if the Compare at Measure Commands option is selected, General Purpose
simulation will compare the values in the input TBDs Measure Events to the measure
values that will be produced for the same measure event by General Purpose simulation.
A difference results in a miscompare message.

occurred. The Expected logic val is the value that was predicted in the input TBD event.
The Found logic val is the value that General Purpose simulation achieved.
If this message is generated while using the gmach keywords, it is a non-SEVERE
WARNING since miscompares are expected in this case.
USER RESPONSE:
source of the input patterns and the reason for performing the simulation. A known case
where miscompares are not of concern is when resimulating a set of patterns that
contain a scan chain LSSD flush test. If the patterns were previously simulated with the
high speed scan based simulator, the flush patterns will contain measure events at X,
since that simulator does not simulate the LSSD flush test. General Purpose simulation,
however, does simulate the LSSD flush test, and hence X vs. known miscompares are
likely to occur.
In most cases, miscompare messages do warrant investigation to determine their cause.
WARNING (TFS-720): Hard 3-state contention was detected on net name hier model
index TBD location tbd location,
EXPLANATION:
A 3-state net with multiple sources (i.e., a wired or dotted net) is being driven by
contending strong values - 0 vs. 1 or 1 vs. 0. The design may be damaged by this
condition.
USER RESPONSE:
The keyword contentionremove may be invoked to remove the patterns.
WARNING (TFS-721): Soft 3-state contention was detected on net name at TBD location
tbd location model index
EXPLANATION:
A 3 state net with multiple sources (i.e., a wired or dotted net) is being driven by an X and
a strong known value - X vs. 1 or X vs. 0. The design may be damaged by this condition.
USER RESPONSE:
The keyword contentionrRemove may be invoked to remove the patterns.
INFO (TFS-722): All X 3-state contention was detected on net name at TBD location tbd
location, net index

EXPLANATION:
A 3-state net with multiple sources (i.e., a wired or dotted net) is being driven by all Xs.
The design may be damaged by this condition.
USER RESPONSE:
The keyword contentionremove may be invoked to remove the patterns.
WARNING (TFS-723): The Mode Init TBD Proc caused 3 State contention.
contentionRemove was in effect. But Patterns were *not* removed.
EXPLANATION:
The test data would be invalid if the Mode Init TBD Proc were removed.
USER RESPONSE:
If the Init Proc was generated automatically, contact customer support (see Contacting
Customer Service on page 23). Otherwise, correct the Init Proc to remove the
contention.
INFO (TFS-725): Simulation of the current TesterLoop or Proc was stopped at Proc
or Seq number sequence number because of contentionRemove.
The TesterLoop or Procs have memory.
EXPLANATION:
The named Pattern Group has 3-state contention, contentionRemove is yes and the
group has memory. The simulator deletes the named group and returns for another
Pattern group.
USER RESPONSE:
WARNING (TFS-726): Hard 01Hot was detected on net name at TBD location tbd
location net index
EXPLANATION:
A three-state net with multiple sources (i.e. a wired or dotted net) is being driven by
contending strong values - 0 vs. 1 or 1 vs. 0. The design may be damaged by this
condition.
USER RESPONSE:
Use keyword contentionRemove to remove the patterns.

WARNING (TFS-727): Soft 01Hot was detected on net name at TBD location tbd
location net index
EXPLANATION:
A three-state net with multiple sources (i.e. a wired or dotted net) is being driven by an X
and a strong known value - X vs. 1 or X vs. 0. The design may be damaged by this
condition.
USER RESPONSE:
INFO (TFS-728): All X 01Hot was detected on net name at TBD location tbd
location, net index
EXPLANATION:
A three-state net with multiple sources (i.e., a wired or dotted net) is being driven by all
Xs. The design may be damaged by this condition.
USER RESPONSE:
INFO (TFS-730): Fault # fault index (mach # machine number) was dropped for
exceeding machinesize.
EXPLANATION:
A fault machines size is the number of nets on which the fault machine logic value differs
from the good machine logic value. Each difference costs runtime & storage.
The named faults size exceeded the machinesize limit and was dropped from the
simulation. The fault will no longer be eligible to be detected by this simulation run. By
dropping faults of this type, significant simulation performance gains may be achieved.
If the value of the machinesize keyword exceeds the number of flat model nets, no
faults will be dropped.
USER RESPONSE:
Typically, none. If you are concerned that the dropped faults may be affecting your test
coverage, increase the value for the machinesize keyword and run the simulation
again.
INFO (TFS-731): Fault # fault index (mach # machine number) was dropped for
exceeding osclim.

EXPLANATION:
If the number of times a fault effect changes a net in a given event exceeds a threshold
(fmosc), the net is said to be oscillating. The net is set to logic value X to stabilize the
circuit. If the same fault effect oscillates on more than a certain threshold of patterns it is
increasingly unlikely that the fault will be marked tested. The threshold is a percentage
of the total number of patterns simulated when the oscillation was detected. This
percentage will not be applied until the first 100 patterns have been simulated. Continued
simulation of such faults costs runtime and storage. The named fault effect oscillated in
excess of the osclim limit and was dropped from the simulation. The fault will no longer
be eligible to be detected by this simulation run. By dropping faults of this type, simulation
performance gains may be achieved.
USER RESPONSE:
Typically, no response is required. If you are concerned that the dropped faults may be
affecting your test coverage, increase the value for the development keyword osclim
and run the simulation again.
WARNING (TFS-740): The Measure event at input TBD odometer measured an X on

net name net type, net index
EXPLANATION:
latchXremove and/or poXremove are/is set and a measure X was detected. The patterns
causing the measure X are not written out.
USER RESPONSE:
Analyze the situation to determine if additional patterns are needed.
WARNING (TFS-741): The function TBDgenerateMasks() returned a bad return code at

TBD location input TBD odometer.
EXPLANATION:
The program was unable to generate channel masks at the given TBD location.
USER RESPONSE:
Analyze the situation to find and remove the problem.
ERROR (TFS-799): While Watching Nets an implicit Measure was needed. The pattern at
TBD location tbd_location. tried to generate an implicit Measure, as directed by the
TDR. Doing so would cause the Scope Data File and TBD to lose synchronization.
EXPLANATION:


USER RESPONSE:
A work-around is to make 2 TFS runs: the first run with no Watch Nets will insert the
implicit Measures into the Output TBD; the second run can use the output TBD from the
first run as input and do the Net Watching.
ERROR (TFS-800): Input pattern error encountered. The Begin Loop pattern at TBD
location tbd location. contains no repeat event to specify the number of loop iterations.
EXPLANATION:
USER RESPONSE:
performed.
ERROR (TFS-805): Input pattern error encountered. The Begin Loop pattern at TBD
location tbd location. contains an event other than the repeat event.
This is an invalid construct. Processing terminates. Correct the pattern and run the
simulation again.
EXPLANATION:
USER RESPONSE:
specified.
WARNING (TFS-810): [Severe] Input pattern error encountered. The design was not left in
the stability state at the end of an independent test. The independent test is the test
entity at TBD location tbd location. Invalid test data may result. The following nets
were in error:
EXPLANATION:
When a test mode specifies test function pins and their stability values, these pins must
be at their stability value at certain boundaries in the test patterns. These boundaries are
determined by the attribute procedures_have_memory on the Tester Loop and
sequences_have_memory on the Test Procedure. When such a boundary is
encountered (the start of an independent test - i.e., a test that begins with a reset to

stability), the simulator assumes that the design is in the stable state. If this is not true,
then correct simulation measures will not be achieved. For this reason, the run is
terminated when this condition is detected. The message indicates the pin type and its
name, its stability value and the current value seen by General Purpose simulation.
USER RESPONSE:
The input patterns must be corrected to leave the design in stability state at the end of
each independent test (i.e., Test Procedure or Test Sequence, depending on the setting
of your "_have_memory" attributes). If these are manually generated patterns, use the
"pins in error" information to correct the patterns. If these patterns were generated by a
Encounter Test automatic test generator, please contact customer support (see
WARNING (TFS-812): [Severe] Input pattern error encountered. The design was not in the
stability state when an event requiring a scan operation was encountered. The event is the
scan event at TBD location TBD loc. Invalid test data may result. The following nets
were in error:
EXPLANATION:
The scan operation is designed to take the design from the test generation (TG) stability
state to the scan state, prior to the actual scan. If the design is not in the TG stability state
when the scan operation is invoked, the design may not scan correctly. The nets that are
not at their stability value are listed in the message. The message indicates the pin name,
its stability value and the current value seen by General Purpose simulation.
USER RESPONSE:
The input patterns must be corrected. If these are manually generated patterns, use the
"pins in error" information to correct the patterns.
If these patterns were generated by a Encounter Test automatic test generator, please
WARNING (TFS-815): Input pattern error encountered. Unrecognized event type event
type encountered at TBD location tbd location. The event is ignored.
EXPLANATION:
The event specified in the message is not supported by General Purpose simulation.
Processing will continue, but the event is ignored.
USER RESPONSE:
If the patterns were manually generated, be aware that the specified event will not
influence the simulation results. If these patterns were generated by a Encounter Test

WARNING (TFS-820): Unsupported TEST SECTION type tsect type was encountered
at TBD location tbd location. Events in the TEST SECTION will not be simulated.
EXPLANATION:
General Purpose simulation does not support this type of test section.
USER RESPONSE:
General Purpose simulation will pass the data in the Test Section to the output TBD with
no simulation.
ERROR (TFS-825): Unsupported test type tsect type was encountered at TBD location
tbd location. Processing terminates. Eliminate this test section from the input patterns
EXPLANATION:
General Purpose simulation does not support this test type.
USER RESPONSE:
Eliminate this test section from the input patterns or use a different simulator that
supports a test section of this type.
WARNING (TFS-830): The termination domination value on the test section at TBD location
tbd location conflicts with the value in the Tester Description Rule. The TDR
specification is term dom, but the TBD specifies term dom.
term dom domination will be assumed by the simulator.

EXPLANATION:
See the message text. The term dom field denotes that either the Tester or Product
termination will dominate.
USER RESPONSE:
Ensure that you wish to override the termination domination as specified by the Tester
Description Rule.
WARNING (TFS-831): [Severe] The user parm measurepo=all conflicts with the TDR.
EXPLANATION:
The condition sets an audit violation flag.

USER RESPONSE:
The run proceeds.
WARNING (TFS-834): [Severe] A Test Inhibit (TI) pseudo-primary input was pulsed away
from its stability value at TBD location TBD loc. The TI is pin name. The stability value is
logic val.
EXPLANATION:
See the message text. This error results in an audit violation flag being set in the global
statistics data. This flag may be used by manufacturing sites to evaluate the validity of
the data.
USER RESPONSE:
If the patterns were manually generated, consider whether it was truly the intent to
override a Test Inhibit pin. If these patterns were generated by a Encounter Test
WARNING (TFS-835): [Severe] A Test Inhibit (TI) primary input was stimmed away from its
stability value at TBD location tbd location. The TI is pin name. The stim value is
stim logic value and the stability value is stability logic value.
EXPLANATION:
statistics data. This flag may be used by certain manufacturing sites to evaluate the
validity of the data.
USER RESPONSE:
If the patterns were manually generated, consider whether or not it was truly the intent
to override a Test Inhibit pin. If these patterns were generated by a Encounter Test
WARNING (TFS-836): [Severe] A Test Inhibit (TI) primary input was pulsed away from its
stability value at TBD location tbd location. The TI is pin name. The stability value is
stability logic value.
EXPLANATION:
the data.

USER RESPONSE:
to override a Test Inhibit pin. If these patterns were generated by a Encounter Test
WARNING (TFS-840): [Severe] The global termination value on the test section at TBD
location tbd_location violates Tester Description Rule specified constraints. The TDR
specification is term, whereas the TBD specifies term. A termination of term will be
assumed by the simulator.
EXPLANATION:
USER RESPONSE:
to override the Tester Description Rule termination. If these patterns were generated by
an Encounter Test automatic test generator, please contact customer support(see
INFO (TFS-841): There is a sequence at TBD location odometer which does not contain
any target fault information and measures=targeted was specified. Since it cannot be
determined which measure points are being targeted by this sequence, all measures will be
recorded.
EXPLANATION:
The TBD patterns contain a sequence without target fault information. One use of this
information is to identify to simulation which measurable nets in the cicuit are being
targeted by this sequence. Without this information, simulation will record expect values
and (if fault simulating) detect faults at all measurable points on this sequence.
USER RESPONSE:
Certain test sequences such as the scan chain tests or the shorted nets test do not
contain target fault information. Therefore this message is expected for these sequences
if measures=targeted is specified. If this is a resimulation of existing patterns which
were imported from report_vectors output, ensure that report_vectors was run
with targetfault=yes specified.

WARNING (TFS-845): [Severe] TBD location tbd location stims two uncontacted PIs
within a Test Sequence and only 1 PMU is available. The first PI is PI netname. The second
PI is PI netname. Both stims were simulated.
EXPLANATION:
When the number of Full Function tester pins plus the number of tester PMUs
(parametric measuring units) is less than the number of product pins, Encounter Test
assumes that only 1 of the unknown number of PMUs can be assigned to an uncontacted
PI for a Test Sequence.
The messages means that a second uncontacted PI is being stimmed within the
TestSequence. Therefore, Encounter Test cannot guarantee the availability of the tester
pin.
USER RESPONSE:
If the patterns were manually generated, consider whether it was truly the intent to violate
Tester Description Rule (TDR) tester pins limits. If these patterns were generated by a
WARNING (TFS-846): [Severe] TBD location tbd location stims a non-contacted pin
but no PMUs are available. The PI is PI netname. The stim was simulated.
EXPLANATION:
When the number of Full Function tester pins is less than the number of product pins and
there are no PMUs (parametric measuring units) available, the patterns may not stim an
uncontacted PI.
USER RESPONSE:
Tester Description Rule (TDR) tester pins limits. If these patterns were generated by a
WARNING (TFS-847): TBD location tbd location changes the Output Inhibit state and
stims other pins. The OI is PI netname
EXPLANATION:
The Output Inhibit control pin is being changed in the same pattern as other primary
inputs. The changing of Output Drivers can generate sufficient electrical noise to corrupt
latch values in the part.
USER RESPONSE:

If the patterns were manually generated and it is believed to be not a potential problem,
no change is needed. If the patterns were generated by a Encounter Test automatic test
generator, please contact customer support (see Contacting Customer Service on
page 23).
WARNING (TFS-848): [Severe] TBD location tbd location changes a Clock with the
Output Inhibit pin(s) not at stability value. The clock is PI netname
EXPLANATION:
This allows the Output Drivers to change at the same time as clocks. The electrical noise
from the changing drivers could lead to unpredictable latch values.
USER RESPONSE:
If the patterns were manually generated, change them to put the clock and Output Inhibit
changes in separate patterns. If the patterns were generated by a Encounter Test
WARNING (TFS-850): An unrecognized stim value was found in the stim event at TBD
location tbd location. The stim is set to X. The stim point is logic value.
EXPLANATION:
A primary input or latch stim value was encountered that was not 0, 1, X, H, L, or Z for a
PI, or 0 or 1 for a latch. The stim value is assumed to be X. The output TBD file will
contain the original stim value and not the assumed X. This error results in an audit
violation flag being set in the global statistics data. This flag may be used by certain
manufacturing sites to evaluate the validity of the data.
USER RESPONSE:
If the patterns were manually generated, you should correct the unrecognized stim value.
If these patterns were generated by a Encounter Test automatic test generator, please

WARNING (TFS-851): An invalid stim value of stim logic value was found in the PPI
stim event at TBD location tbd location. A PPI may only be stimmed to 0 or 1. The stim
is set to X. The stim point is pin name.

EXPLANATION:
A pseudo-primary input (PPI) stim value was encountered that was not 0, or 1. The stim
value is assumed to be X. The output TBD file will contain the original stim value and not
the assumed X. This error results in an audit violation flag being set in the global statistics
data. This flag may be used by certain manufacturing sites to evaluate the validity of the
data.
USER RESPONSE:
If the patterns were manually generated, you should correct the invalid stim value. If
these patterns were generated by a Encounter Test automatic test generator, please
WARNING (TFS-855): A non-three-state PI is stimmed to an illegal value. The stim value of

invalid logic value has been converted to valid logic value. The stim event is at TBD
location tbd location. The PI is pin name.
EXPLANATION:
A primary input stimulus value was encountered that was H, L, or Z. It is converted to a
1, 0, or X, respectively.
USER RESPONSE:
generated by a Encounter Test automatic test generator, please contact customer
WARNING (TFS-860): In the stim or pulse event at TBD location tbd location, the stim
value on correlated PI pin id is not the value required by the correlation. Other conflicts
may exist in this event. Processing continues.
EXPLANATION:
The stim value on the correlated PI is different from the value required by the correlation.
The value on the correlated PI will not be changed to the value required by correlation.
USER RESPONSE:
value on the correlated PI is correct. If the value is not correct, change the value.
WARNING (TFS-863): The Stop_Osc event at TBD location TBD loc specifies a quiescent
state value of quiescent val, which differs from the stability value of stab val. The PI
is set to quiescent val. The PI is pin name.

EXPLANATION:
The net in a Stop_Osc event is typically a clock PI, which should have an associated
stability (off state) value. In this case, the value specified to restore the oscillator was
something other than the stability value for the pin.
USER RESPONSE:
Ensure that the specified Stop_Osc event is intended to restore the oscillator to some
value other than stability. If not, change the Stop_Osc event to utilize the stability value.
WARNING (TFS-864): There are active PI oscillators at the end of the setup sequence at
TBD location TBD loc. These primary inputs will be set to X at the beginning of each
subsequent test sequence, regardless of any event that may set them to a known value during
any test sequence. The active PI oscillators are as follows:
EXPLANATION:
One or more primary inputs were the subject of a Start_Osc event in the setup sequence
for the current test procedure, causing them to become active oscillators. The oscillators
on these PIs, however, were not deactivated (via a Stop_Osc or other stim event) prior
to the end of the setup sequence. Since sequences do not have memory for this test
procedure, each of these PIs will be set to X at the start of each test sequence, even if
they are stimmed or deactivated during the course of some test sequence. This is
USER RESPONSE:
Ensure that you really wished to leave the oscillator PIs active at the end of the setup
ERROR (TFS-865): The FORCE command at TBD location tbd location is incorrectly
specified. The proper syntax is: FORCE = logic value netname, for example FORCE =
1 RegA_Latchpoint
Note that the net name may not contain blanks.
Correct the FORCE command in the TBDpatt file, import the TBDpatt file, and run the
simulation again.
EXPLANATION:
The message states incorrect specification of the FORCE command and provides an
example of correct syntax.
USER RESPONSE:
Correct the syntax and rerun.

WARNING (TFS-866): At TBD location Input TBD location, PI block name is used
by a WaitOsc without having been referenced by a StartOsc. Flat flat index
EXPLANATION:
A PI cannot be used in a WaitOsc unless it has been defined as an Osc by a StartOsc
TBD command.
USER RESPONSE:
If the patterns were manually generated, modify the StartOsc or WaitOsc. to agree. If
these patterns were generated by an automatic test generator, please contact customer
supports.
ERROR (TFS-870): The either FORCE or RELEASE command at TBD location TBD
location contains an unrecognized net name. The net name is: net name. Correct the
net name in the TBDpatt file, import the TBDpatt file, and run the simulation again.
EXPLANATION:
USER RESPONSE:
Correct the net name
ERROR (TFS-875): The RELEASE command at TBD location TBD location is

incorrectly specified. The proper syntax is: RELEASE = netname e.g., RELEASE =
RegA_Latchpoint Note that the net name may not contain blanks. Correct the RELEASE
command in the TBDpatt file, import the TBDpatt file, and run the simulation again.
EXPLANATION:
USER RESPONSE:
Correct the RELEASE command
ERROR (TFS-880): The FORCE command at TBD location TBD location had an
incorrectly specified logic value. Correct the FORCE logic value in the TBDpatt file, import the
TBDpatt file, and run the simulation again.
EXPLANATION:
USER RESPONSE:
Use a logic value of 0,1,X or Z

WARNING (TFS-884): The FORCE on FORCEd Name of FORCEed net at TBD

location TBD location is FORCEing an already FORCEed net. The FORCE is ignored.
EXPLANATION:
A redundant FORCE is ignored because a net already FORCEd cannot be changed.
This condition arises if there is a FORCE command inside a pattern loop.
USER RESPONSE:
No response required. See "Force" in the Encounter Test: Reference: Test Pattern
Formats for related information.
INFO (TFS-885): FORCE (FORCE type, can be either temp or hold)

command(s) to a non-X values at TBD location TBD location.
The test data produced by this run may be invalid since FORCE commands are not
applied at the tester. FORCES are as follows:
EXPLANATION:
The FORCE (hold) endures until a reset or a RELEASE command. The FORCE (temp)
endures only for the FORCE event. This message will not print if the FORCE is to X, since
X in the simulator will not cause a simulator/tester miscompare.
USER RESPONSE:
WARNING (TFS-894): TBD tbd location. unFORCEd net net name was
RELEASEd.
EXPLANATION:
This message identifies the TBD location of the unFORCED net.
USER RESPONSE:
If this is intentional, no change is required. If not intentional, then either add a FORCE, or
delete the RELEASE.
ERROR (TFS-895): The input pattern at tbd locationis FORCEing a compressed net.
netname Flatx: net index
EXPLANATION:
The net being forced does not exist in the compressed simulator model.
USER RESPONSE:

Rerun the simulator, specifying keyword compress=no.
ERROR (TFS-902): TBD file open error. TFS is unable to open TBDgenerateMasks()
EXPLANATION:
TBDgenerateMasks() is a OpMisr++ function. The probable cause of the failure is lack of
space.
USER RESPONSE:
Run the job an a workstation with more space.
If problems persist, please contact customer support (see Contacting Customer
ERROR (TFS-903): Test data output integrity error. Unable to write a tbd entity into the
output test data file. Processing terminates. The failing file is file name.
EXPLANATION:
A failure occurred attempting to write test data to the file file name.
USER RESPONSE:
Ensure that sufficient space exists in the file system. If problems persist, please contact
ERROR (TFS-904): Test data output error. Unable to initialize an output test data repository.
Processing terminates. Initialization attempted with these parameters: Project = parm 1 Part
Entity/Iteration/Variation = parm 2 Test Mode = parm 3 Experiment = parm 4
EXPLANATION:
USER RESPONSE:
file system and that file permissions are set correctly. If problems persist, please contact
ERROR (TFS-905): Test data output integrity error. Unable to copy attribute data from the
tbd entity at input TBD location tbd location to the output test data. Processing
terminates.
EXPLANATION:


USER RESPONSE:
INFO (TFS-907): The tester proc type Test Procedure at input TBD location TBD
location was copied from the input TBD to the output TBD without simulation.
EXPLANATION:
A reminder that not all Test Procs are simulated. The Test Mode Init Proc is not simulated
by TFS unless the parm SimModeInit=yes. The user might want to sim the ModeInit
if the Procs have memory and fault simulation will be performed. In this case the fault
machines will be simulated during mode init. If the Procs have no memory, TFS simulates
the Mode Init gmOnly because the design state will be reset at Proc boundaries. The
ECID (electronic chip ID) is never simulated by TFS. It is always copied directly to the
output
USER RESPONSE:
Information only, no response required.
ERROR (TFS-911): [Internal] PROGRAM ERROR ENCOUNTERED. Processing

terminates. Error in file file name at line line number. diagnostic message
EXPLANATION:
This message indicates a program failure.
USER RESPONSE:
ERROR (TFS-915): Unable to register the output experiment experiment name in the
globalData file. Processing terminates. No output test data was produced.
EXPLANATION:
USER RESPONSE:
ERROR (TFS-916): Unable to update the globalData file. Processing terminates. Check
permissions for the workdir directory and globalData file.
EXPLANATION:


USER RESPONSE:
ERROR (TFS-922): GP simulator command line Fault Index fault_index is not valid.
There is no Fault Index fault_index among the faults loaded by the Simulator.
EXPLANATION:
A fault index in gMACH= or gMACH= or faultList= was not loaded by the simulator.
Typical causes or this are: the fault is not in the test mode; the fault is tested and the type=
specifies only untested faults; the fault is dynamic and simDynamic=no.
USER RESPONSE:
Ensure that the command line specifies only faults which are being loaded. One way to
do this is to run report_faults with the parameters set to list only the fault types which
will be loaded. Type report_faults -h | pg for help with View Fault List or refer to
""report_faults" in the Encounter Test: Reference: Commands.
ERROR (TFS-925): Fault simulation was requested but no fault model exists. Processing
terminates. Ensure that a fault model is built for this design and run the simulation again.
EXPLANATION:
USER RESPONSE:
ERROR (TFS-930): A non-static fault was requested for simulation. General Purpose
simulation supports only static fault types. The erroneous fault index is fault index.
Specify a static fault index and run the simulation again.
EXPLANATION:
See message text.
USER RESPONSE:
Specify a static fault index and run the simulation again.

ERROR (TFS-931): A fault index is out-of-range. The fault index does not exist. The
erroneous fault index is fault index. Probably a mistake with <faultRange=> or
<MACH=> run controls.
EXPLANATION:
See message text.
USER RESPONSE:
Specify a static fault index which is in the flat model.
ERROR (TFS-932): There are no faults within the specified range of fault index to
fault index. Likely causes: asking for fault simulation but no untested faults remaining;
a mistake using <FaultRange=> or <MACH=>.
EXPLANATION:
Fault range, if used for more than 1 fault, loads only untested faults. There are no
untested faults in the range given.
USER RESPONSE:
Pick different faults
ERROR (TFS-933): <MACH=> fault index collision on flat block block index. Fault index
fault index is on the same block as fault index fault index
EXPLANATION:
<MACH=> is limited to naming 1 fault on a simulation primitive block within any
composite MACH. The message means that the <MACH=> definition for a multiple fault
machine (a composite machine) references a block more than once. For example, if the
list were <MACH=2,4,20,10/2,100> and 2 & 4 were on the same block that would be a
fault index collision within the first group.
USER RESPONSE:
Correct the <MACH=> list.
ERROR (TFS-934): General Purpose simulation control parameter problem. watchMACH=

refers to an fMACH=, but an fMACH has not been defined.
EXPLANATION:
WatchMACH may refer to an fMACH. For example <watchMACH=0,fMACH>. But there
must be an fMACH defined, for example, fMACH=2,4,9.
USER RESPONSE:

Either remove the fMACH reference from watchMACH= or define an fMACH=.
ERROR (TFS-935): General Purpose simulation control parameter problem. watchMACH=

cannot have fault machines in addition to fMACH.
EXPLANATION:
WatchMACH= contains the string <fMACH> plus additional faults. But when running
fMACH=, the only faults which may be simulated are those defined by fMACH=.
USER RESPONSE:
Either remove the fMACH reference from watchMACH= or remove the additional faults.
ERROR (TFS-936): Initialization for recording data for scoping was not completed. See
proceeding messages for more information.
EXPLANATION:
USER RESPONSE:


32
TFW - Encounter Test Framework Utilities
Messages
TFW-001 through TFW-050 on page 1117

TFW-001 through TFW-050

INFO (TFW-001): Message MessagePrefixMessageNumber was not found.
EXPLANATION:
The specified message could not be displayed for several possible reasons, including
The system is out of memory and is unable to load the message catalog.
There are too many open files.
The LANG variable is set to C or is not set at all.
The application is using a message that does not exist in the catalog.
USER RESPONSE:
For resource-related problems, other Encounter Test messages may be generated that
are symptoms of the same problem. If not, run the locale command in the Encounter Test
environment to see the current value of the LANG variable and the LC_MESSAGES
variable. In most cases, they should be set to en_US. You may also need to run locale -
a to list all of the available languages, to ensure that en_US is available on your system.
For more assistance, please contact customer support (see Contacting Customer

TFW - Encounter Test Framework Utilities Messages
INFO (TFW-002): Increased data ulimitfor current process to value.

EXPLANATION:
The ulimit is increased to the indicated value.
USER RESPONSE:
Contact customer support ((see Contacting Customer Service on page 23)), if
necessary.
WARNING (TFW-003): Increasing ulimit failed: data

EXPLANATION:
A system limitation or other element in the operating environment may be preventing the
ulimit increase.
USER RESPONSE:
ERROR (TFW-004): Opening fileName failed: reason.

EXPLANATION:
The opening of the file failed for the reason specified.
USER RESPONSE:
Analyze the reason for the failure and correct the problem if possible.
WARNING (TFW-005): Insufficient storage to satisfy TFWsmMalloc for mallocNumber

(size) bytes. number bytes in use by TFWsm.
EXPLANATION:
There does not appear to be enough storage to satisfy a memory allocation request.
USER RESPONSE:
Consider doing the following:
Are there any other jobs running that may be requiring storage?
Are there other machines available to run this job on?
If the problem occurs frequently, contact customer support (see Contacting
Analyze the reason for the failure and correct the problem if possible.

INFO (TFW-006): There are currently number unavailable TFWsmMallocs.

EXPLANATION:
The storage manager is keeping track of how many mallocs are not freed. This does NOT
mean that they need to be freed immediately or that they wont be freed later. This is just
an informational "count" for you to consider.
USER RESPONSE:
INFO (TFW-007): error number of error_string

EXPLANATION:
The message is produced frmo an unknown source.
USER RESPONSE:
INFO (TFW-008): NULL pointer passed to TFWsmFree # number.

EXPLANATION:
The storage manager detected that a NULL pointer was attempted to be freed. This
indicates that the pointers integrity should be questioned. Only valid pointers (pointers
malloced and uncorrupted) should be freed.
USER RESPONSE:
Analyze the pointer in question and correct the situation.
WARNING (TFW-009): Encounter Test created a symbolic link for the file fileName, but
of the directories supplied by directory=directory, there werent any directories with
the minimum space needed of number megabytes. The directory directory has the
most space available with number megabytes and will be used to create the symbolic link.
EXPLANATION:
To avoid filling the file system where the working directory resides, Encounter Test allows
users to specify additional directories for output files.
Symbolic links are created to access these directories. The directories are specified in
the environment variables TB_PERM_SPACE and TB_TEMP_SPACE. Encounter Test
created a symbolic link of an output file, but it could not find a directory that had the free
space Encounter Test needs. Encounter Test uses the directory with the most free space
and continues processing.

See Options Setup in the Encounter Test: Reference: GUI for detail on these
environment variables.
USER RESPONSE:
Encounter Test continues processing but the TB_PERM_SPACE or TB_TEMP_SPACE
environment variable should be updated with a directory that has the free space needed
for future runs.
WARNING (TFW-010): Encounter Test did not create a symbolic link for the file fileName.
Of the directories supplied by directory=directory, there no directories with the
minimum space needed of number megabytes. The working directory directory has
the most space available with number megabytes, so no symbolic link was created.
EXPLANATION:
To avoid filling the file system where the working directory resides, Encounter Test allows
users to specify additional directories for output files.
Symbolic links are created to access these directories. The directories are specified in
the environment variables TTB_PERM_SPACE and TB_TEMP_SPACE.. Encounter Test
did not create a symbolic link of the output file, because it could not find a directory that
had the free space Encounter Test needed. Encounter Test just used the working
directory because it has the most free space of all the directories and continues
processing.
See Options Setup in the Encounter Test: Reference: GUI for detail on these
environment variables.
USER RESPONSE:
Encounter Test continues processing but the TB_PERM_SPACE or TB_TEMP_SPACE
environment variable should be updated with a directory that has the free space needed
for future runs.
INFO (TFW-011): Invalid address address passed to TFWsmFree #number_free (not

a multiple of 8).
EXPLANATION:
An invalid pointer was provided to the utility that frees storage.
USER RESPONSE:
INFO (TFW-012): Invalid address address passed to TFWsmFree #number_free (not

in TFWs range of storage).

EXPLANATION:
An invalid pointer was provided to the utility that frees storage.
USER RESPONSE:
WARNING (TFW-013): The environment variable GlobalVariableName had an invalid

value of value, it has been defaulted to defaultValue.
EXPLANATION:
Some Encounter Test application parameters can be specified as environment variables.
Some are checked for invalid values and defaulted to a value if an invalid value is found.
USER RESPONSE:
Correct the value of the environment variable if the default is not satisfactory.
Note: The use of environment variables is discouraged since unpredictable results can
occur. If you are in the Tcl environment, you can use set_global or update_project
to set/reset the value of a keyword that is to be used globally.
WARNING (TFW-014): The path environment variable GlobalVariableName=value

contains the directory directoryName which is not readable.
EXPLANATION:
The Encounter Test application path environment variable contains a directory that is not
readable to the Encounter Test application.
USER RESPONSE:
Check that the directory name is spelled correctly. Check that the file permissions are set
correctly.

contains the file fileName specified in its path.
EXPLANATION:
The Encounter Test application path environment variable contains a regular file and not
a directory.
USER RESPONSE:
Remove the file name from the Encounter Test application path environment variable.


contains the directory directoryName which does not exist or is not readable.
EXPLANATION:
The Encounter Test application path environment variable contains a directory that does
not exist or is not readable to the Encounter Test application.
USER RESPONSE:
Check that the directory name is spelled correctly. Check that the file permissions are set
correctly.
INFO (TFW-017): The TFW storage log (logEntries entries for logBytes total bytes)
has been reset.
EXPLANATION:
This message is for Encounter Test application debug only.
USER RESPONSE:
This message is for Encounter Test application debug only.
WARNING (TFW-018): Encounter Test can not find the command which shows available
space in the directory directory_name.
EXPLANATION:
Encounter Test uses the NFS command df, the AFS commands fs and vos and the
DFS command fts to get the available space in a file system. The command was not
found in the path environment variable.
USER RESPONSE:
Check your path environment variable and make sure the directory for the df/fs/vos/fts
commands are included.
WARNING (TFW-019): Encounter Test is unable to determine the free space of the directory
directory_name.
EXPLANATION:
Encounter Test uses the NFS command df, the AFS commands fs and vos and the
DFS command fts to get the available space in a file system. The command that was
found, is not returning the expected output.
USER RESPONSE:

Check your path environment variable and make sure the directory for the df/fs/vos/fts
commands are ahead of any conflicting directories (a directory with its own df/fs/vos/fts
executable, one might be the X11 font server command (fs) ).
(severity) (TFW-020): ) (invalid_flags) The flags Encounter

Test_application are not valid for the command command line.
EXPLANATION:
Encounter Test applications keep track of what flags are valid for its command line. One
or more flags were specified on the command line and are not valid flags for that
Encounter Test application.
USER RESPONSE:
Refer to the Encounter Test application command line help to see what flags are valid.
You may set the environment variable TB_CONTINUE=yes to allow the Encounter Test
application to continue with a warning.
message_severity (TFW-021): The keyword invalid_keyword is not valid for the

application command line.
EXPLANATION:
Each Encounter Test application keeps track of what keywords are valid for its command
line. This keyword was specified on the command line and is not a valid keyword for the
application.
USER RESPONSE:
Refer to the application command line help (help, -h, or -H) or refer to the Encounter
Test: Reference: Commands to determine what flags are valid for this command line.
A common problem may be an incorrectly spelled keyword.
INFO (TFW-022): TFWsm is scouring partial segments for any available storage.
EXPLANATION:
The application has exhausted all full-sized (256-meg) memory-mapped segments
available. TFW is searching for partial segments to satisfy the applications memory
request.
USER RESPONSE:
None, but watch for additional messages (especially TFW-005 or TFW-023).
INFO (TFW-023): TFWsm was able to get amount bytes (segment base
address=address) to satisfy a request for request bytes.

EXPLANATION:
After searching for partial segments (see TFW022), the TFW storage manager found
enough storage to satisfy the applications memory request.
USER RESPONSE:
INFO (TFW-024): NULL pointer passed to TFWsmStrdup().

EXPLANATION:
The storage manager detected that a NULL pointer was attempted to be strduped. This
indicates that the pointers integrity should be
questioned. Only valid pointers (to a valid null-terminated string) should be strduped.
USER RESPONSE:
WARNING (TFW-025): psdanger() reports freePaging 4K pages (freeMeg currently

free. There are totalPaging 4K pages (totalMeg Meg) total paging space.
EXPLANATION:
See the explanation for TFW-005, which accompanies this message.
USER RESPONSE:
See the response for TFW-005, which accompanies this message.
WARNING (TFW-026): Bad pointer (0xpointer) passed to TFWsmFree # number.

EXPLANATION:
The storage manager detected that a "bad" pointer was attempted to be freed. This
indicates that the pointers integrity should be questioned. Only valid pointers (pointers
malloced and uncorrupted) should be freed.
USER RESPONSE:
INFO (TFW-027): number storage audits done (number mallocs, number frees)
EXPLANATION:

The storage manager is reporting how many storage audits have been done. An "audit"
checks every piece of allocated storage for overwrites and other problems. One audit is
done for every TFWsmMalloc and TFWsmFree. The audit count is only informational and
can be used to speed up similar runs by exporting TFWAUDITBEGIN before starting the
run, allowing you to no-op that many audits before actually beginning the time-
consuming checking.
USER RESPONSE:
WARNING (TFW-028): The command which shows available space in the directory
directory_name cannot be executed. Ensure that this directory is mounted.
EXPLANATION:
Encounter Test uses the NFS command df, the AFS commands fs or vos or the DFS
command fts to get the available space in a file system. One of the commands did not
complete sucessfully.
USER RESPONSE:
Verify the referenced the directory is mounted for the df/fs/vos/fts commands to be
executed.
INFO (TFW-030): command will delete status_record_count status records

EXPLANATION:
This message indicates the number of status records in the globalData file that will be
deleted.
USER RESPONSE:
INFO (TFW-031): filename was reduced by byte_count bytes, or

percent_difference.
EXPLANATION:
This message indicates the amount of reduction for the globalData file.
USER RESPONSE:
INFO (TFW-032): command ended with a return code of return_code..

EXPLANATION:
This message indicates the completion status of the command.
USER RESPONSE:
No response is necessary unless the return code indicates an error was detected.
Generally, an error was detected if the return code is greater than 1. In that case, refer
to preceding messages for more details.
INFO (TFW-033): There are no status records to delete.

EXPLANATION:
There are no status records in the globalData file to delete.
USER RESPONSE:
WARNING (TFW-048): Unable to remove zero_length lock file:

filename
EXPLANATION:
An error was encountered when removing a zero-length lock file
USER RESPONSE:
Check the object name passed to TFWrmLockFile function
ERROR (TFW-049): [Internal] Empty lockable object name is detected when trying to
remove the associated zero-length lock file from the locks directory.
EXPLANATION:
An error was encountered when removing a zero-length lock file
USER RESPONSE:
Check the object name passed to TFWrmLockFile function
ERROR (TFW-050): ERROR locking globalData: filename.

EXPLANATION:
An error was encountered locking the globalData file.
USER RESPONSE:
Check the following:

Does the globalData file exist?

Do you have the correct permission on the globalData file?
Is there a current process running that requires exclusive use of the globalData
file?

INFO (TFW-051): Deleted the file filename dependent on object.
EXPLANATION:
The file was successfully deleted.
USER RESPONSE:
WARNING (TFW-052): [Severe] Error deleting the file filename dependent on

object.
EXPLANATION:
An error was encountered deleting file and the file still exists. Error identification will not
occur if the file does not exist.
USER RESPONSE:
Determine whether you have the correct permission on the file.
WARNING (TFW-053): [Severe] Unable to lock object : reason.

EXPLANATION:
An error was encountered when attempting to place a read lock on a data record in the
globalData file.
USER RESPONSE:
Is there a current process running that requires exclusive use of the data?

WARNING (TFW-054): [Severe] A backlevel globalData file exists. Remove and rebuild the
globalData file.
EXPLANATION:
A backlevel globalData file was detected during globalData file build. This should only
occur on a release boundary.
USER RESPONSE:
Remove and rebuild the globalData file.
INFO (TFW-055): Process processId on node nodeName already has a lockType

lock.
EXPLANATION:
The node has already been locked by another process.
USER RESPONSE:
None required unless this becomes a problem. The process should eventually release
the lock and process should continue.
WARNING (TFW-058): [Severe] Invalid dependency in the globalData file: filename

EXPLANATION:
The globalData file contains a dependency record that is incomplete. Data is missing in
the globalData file.
USER RESPONSE:
Rebuild the part and rerun all applications. If the problem occurs again, contact customer
support (see Contacting Customer Service on page 23) for assistance.
WARNING (TFW-059): [Severe] ERROR synchronizing globalDataFile:

errorReason.
EXPLANATION:
An error was encountered synchronizing the file for listed reason.
USER RESPONSE:
Check error reason supplied within the message.
Does the file exist?
Do you have the correct permissions for the file?

If the problem cannot be resolved, note the reason specified for the failure and contact
WARNING (TFW-060): [Severe] ERROR reading globalDataFile: errorReason.

EXPLANATION:
An error was encountered reading the globalData file
USER RESPONSE:
Did a process abnormally terminate?
If this problem persists, the globalData file may be corrupted. It needs to be rebuilt.
INFO (TFW-061): Request for program status not supported by this application.
EXPLANATION:
The application requested status (heartbeat) from a framework utility that does not
provide that information.
USER RESPONSE:
WARNING (TFW-062): [Severe] ERROR writing globalData: filename.

EXPLANATION:
An error was encountered writing the globalData file.
USER RESPONSE:
Is there sufficient space in the directory where the globalData file resides.
Correct any of the above problems if they exist, otherwise contact customer support (see

WARNING (TFW-063): [Severe] ERROR closing globalData: filename.

EXPLANATION:
An error was encountered closing the globalData file.
USER RESPONSE:
Is there a current process running that requires exclusive use of the file?
Is there sufficient space in the directory that the globalData file resides?
WARNING (TFW-064): [Severe] Unable to unlock objectName : reasonText.

EXPLANATION:
An error was encountered attempting to unlock a data record in the globalData file.
USER RESPONSE:
Do you have the correct permission on the globalData file? of the file?
WARNING (TFW-065): [Severe] Unable to write lock "objectName" : reasonText.

EXPLANATION:
An error was encountered attempting to write lock a data record in the globalData file.
USER RESPONSE:
Is there a current process running that has a read or write lock on the data
record you are trying to lock?

WARNING (TFW-067): A problem occurred while read locking the filename file. The
system reason for this message is >>reason<,<. Processing continues.
EXPLANATION:
An error was encountered attempting to read lock a data record in the globalData file, the
error is not considered severe. Potential reasons for this message are:
Another routine may have obtained a lock prior to this one.
The specified file or directory may not have the proper ACLs set.
USER RESPONSE:
Correct any problems if they exist, otherwise contact customer support (see Contacting
Customer Service on page 23) if problems persist.
WARNING (TFW-068): [Severe] Unable to read locking the file: fileName. The system
reason for this error is >>reason<<. Another possibility is that some other application has a
write lock on this file.
EXPLANATION:
An error was encountered attempting to read lock an object in the globalData file. This
error is considered severe. Potential reasons for this message are:
Another routine may have obtained a write lock prior.
The specified file or directory may not have the proper ACLs set.
Note: The globalData file may be invalid as a result of improper locking.
USER RESPONSE:
Check for the potential reasons and correct any problems if they exist, otherwise contact
customer support (see Contacting Customer Service on page 23) if problems persist.
WARNING (TFW-069): [Severe] A severe problem occurred while write locking the
filename. The system reason for this message is reason. Write locking has failed. If you
are using the Encounter Test GUI on this same project, it may be using resources that are
needed to run this application. If so, press the Unlock GUI Resources button on the main
window toolbar and rerun this application.
EXPLANATION:

An error was encountered attempting to write lock the named file or object. The following
are potential reasons for this message are:
The Encounter Test GUI may have the desired resource in use. If you are
currently using the GUI on the same project as the failed command, and have
been using some of the analysis tools (for example, Schematic View), the
resource that this command is attempting to recreate may still be in use by the
GUI. To determine if this is the case, do the following:
hierModel If the write lock could not be obtained for

"hierModel" and any GUI analysis tools have been
used for this project, then the GUI will still have
the hierModel in use. Click the Unlock GUI
Resources button on the main window toolbar.
test mode If the write lock could not be obtained for the "test
mode" and the Analysis Context window has
Test mode set to the same value the failed
command was attempting to lock, then the GUI
has the needed test mode in use. You may clear
the Test mode entry field and click the Apply
button in the Analysis Context window in order
to unlock only the test mode and any dependent
resources. Alternatively, you may click the
Unlock GUI Resources button on the main
window toolbar to unlock all resources in use by
the GUI.
experiment If the write lock could not be obtained for the
"experiment"and the Analysis Context window
has Experiment set to the same value the failed
command was attempting to lock, then the GUI
has the needed experiment in use. You may clear
the Experiment entry field and click the Apply
button in the Analysis Context window in order
to unlock only the experiment and any dependent
resources. Alternatively, you may click the
Unlock GUI Resources button on the main
window toolbar to unlock all resources in use by
the GUI.
Refer to Appendix B. Sharing of Resources with Other Encounter Test Applications in

the Encounter Test: Reference: GUI for related information.

If, in any case, the Unlock GUI Resources button is not available to be clicked, it means
the GUI does not have any resources locked at this time. In this case, check the reasons
that follow:
Another command may have the desired resource locked. This could be a
command that you are currently running or that a colleague is running on this
same project. It is also possible that a colleague is currently using the
Encounter Test GUI to perform analysis on this project. Determine the
colleague that is running on this project and resolve with them the need to
recreate the resource in question.
The specified file or directory may not have its permissions set appropriately.
Check the permissions for the current project working directory and locks
directory, and ensure that you have authority to create and update files within
them.
USER RESPONSE:
WARNING (TFW-070): [Severe] The objectName object could not be lockType

locked because it could not be found in the globalData file. Potential reasons for this message
are:
The input data to the application may not match that of the part.
Ensure that the WORKDIR, mode name, and experiment name match that of
the part.
The object was not registered in the globalData file.
The globalData file may be corrupted.
EXPLANATION:
An error was encountered attempting to lock an object in the globalData file. The object
does not exist in the globalData file. The error is severe. The lock could not be obtained.
USER RESPONSE:
WARNING (TFW-071): The specified Perm Space script, permSpaceScript, is not

executable. Verify that TB_SPACE_SCRIPT is properly set and that the file to which it points
is a valid executable.

EXPLANATION:
The Perm Space algorithm checks the value of the TB_SPACE_SCRIPT for the name of
an executable file. If the file is not executable, it will default to using its own script.
USER RESPONSE:
Ensure the value of TB_SPACE_SCRIPT is correct. Refer to Options Setup in
the Encounter Test: Reference: GUI for details.
Ensure the permissions and ACLs on the file will permit the file to be executed.
WARNING (TFW-072): [Severe] The default Perm Space script is not available. This
indicates an installation problem.
EXPLANATION:
Encounter Test ships a default Perm Space script, which is used if the
TB_SPACE_SCRIPT variable is not set, or set to a non-executable file. If this default
script is not available, an installation/packaging error has occurred and Perm Space can
not function.
USER RESPONSE:
INFO (TFW-073): The filename fileName was returned from the user script, but it is not a
valid directory name.
EXPLANATION:
The Perm Space routines received a directory name (ending in a forward slash) that
does not exist. Perm Space will not create directories if they do not exist.
USER RESPONSE:
If the directory is correct and desired, before exiting the script, create the directory. If this
message is in error, or you have not overridden the default Perm Space script by using
the TB_SPACE_SCRIPT environment variable, contact customer support (see
WARNING (TFW-074): The filename fileName was returned from the default script, but
it is not a valid directory name. The file will reside in the part directory.
EXPLANATION:
The Perm Space routines received a directory name (ending in a forward slash) from the
shipped Perm Space script that does not exist.

USER RESPONSE:
INFO (TFW-075): Resource named file_name could not be read_or_write locked.

This process will begin waiting for this lock.
EXPLANATION:
Read and Write locking of various resources/files is required to ensure data is not
corrupted. The current process will wait until the specified resource becomes available.
USER RESPONSE:
This is normal when multiple processes are running against the same part. If the process
owning the resource is a long-running task, the current process may stay held up until
that resource is released.
INFO (TFW-100): License checking has been disabled. Password expires in number of
days day(s).
EXPLANATION:
License checking was disabled at your request.
USER RESPONSE:

INFO (TFW-100): License checking has been disabled. Password expires in
number_of_days day(s).
EXPLANATION:
USER RESPONSE:
WARNING (TFW-101): [Severe] Network License Functions not Operating...

EXPLANATION:
License functions are not operational.

USER RESPONSE:
WARNING (TFW-102): License for product (ID=productID) has been lost!

EXPLANATION:
USER RESPONSE:
WARNING (TFW-103): [Severe] Error occurred trying to set ALARM signal!

EXPLANATION:
USER RESPONSE:
WARNING (TFW-104): All (license_name) licenses are in use for the following product:
product_name
The waiting period has expired.

EXPLANATION:
USER RESPONSE:
WARNING (TFW-105): All (license_name) licenses are in use for the following product:
product_name
User is not willing to wait for a license to become availability.

EXPLANATION:
USER RESPONSE:

WARNING (TFW-106): No licenses for the following product have been purchased:
product_name
Request to run this application is denied.

EXPLANATION:
USER RESPONSE:
WARNING (TFW-107): Application programming error: Attempting to release a license for

product (ID=idNumber) which was never obtained!
EXPLANATION:
An error was encountered attempting to release a license for a product. It is apparent that
the license that is being released was never obtained.
USER RESPONSE:
Check the license server machine. If it had gone down after a license was obtained and
prior to its release, this message is legitimate. Otherwise contact customer support (see
INFO (TFW-108): Waiting for a license name license to become available...

EXPLANATION:
The program must obtain a license prior to execution and is currently awaiting license
availability.
USER RESPONSE:
INFO (TFW-109): All (license count) licenses are in use for the following product:
application name
The following lists known current users of this product:

EXPLANATION:
The message states number of currently utilized licenses for the referenced application
and lists the current users of the licenses.

USER RESPONSE:
WARNING (TFW-111): [Severe] Trouble checking for licenses due to system errors.
Product: system error message cannot be run due to these problems.
EXPLANATION:
A system error is preventing the program from determining available licenses.
USER RESPONSE:
Review and resolve the referenced system error message and rerun.
WARNING (TFW-112): Waiting for license server to respond. If a license server is not
available on the network, the licensing function will fail within 10 minutes. You may wish to
cancel this process if you know that a network license server is not currently available.
EXPLANATION:
The program is waiting for a license server to respond. The licensing function runs for 10
minutes before terminating.
USER RESPONSE:
Cancel the process if it is determined the license server is unavailable; otherwise let the
licensing function run until either the license is acquired or the license function
terminates.
WARNING (TFW-113): License to run application not available.

EXPLANATION:
A license required to run the referenced application is unavailable.
USER RESPONSE:
Cancel the process if it is determined the license server is unavailable; otherwise let the
licensing function run until either the license is acquired or the license function
terminates.
WARNING (TFW-150): [Severe] TFWsocket::setBlocking() for socket

socketFileDescriptor:reasonText
EXPLANATION:
Encounter Test socket services were unable to put a socket file descriptor (used for inter-
process communication) into blocking mode.

USER RESPONSE:
Probable programming error. Note your version of UNIX, TCP/IP, then contact customer
WARNING (TFW-151): [Severe] TFWsocket::setNonblocking() for socket

socketFileDescriptor: reasonText
EXPLANATION:
Encounter Test socket services were unable to put a socket file descriptor (used for inter-
process communication) into non-blocking mode.
USER RESPONSE:
WARNING (TFW-152): [Severe] TFWsocket::accept() for socket

EXPLANATION:
Encounter Test socket services were unable to connect a socket file descriptor (used for
inter-process communication).
USER RESPONSE:
WARNING (TFW-153): [Severe] TFWsocket::recv() for socket

EXPLANATION:
Encounter Test socket services were unable to read from a socket file descriptor (used
for inter-process communication).
USER RESPONSE:
INFO (TFW-180): TFWhostInfo did not recognize model number machineID.

EXPLANATION:

Encounter Test reports machine model numbers in its output. You have an unrecognized
model number.
USER RESPONSE:
Contact customer support (see Contacting Customer Service on page 23) and report
this message, along with your machines model number.
WARNING (TFW-269): [Severe] Unable to remove dependencies on the objectName.

EXPLANATION:
Dependencies on the object cannot be removed, probably due to a corrupt globalData
file.
USER RESPONSE:
Rebuild the globalData file and retry. If the problem persists, contact customer Service
INFO (TFW-273): Unable to find file name for the following reason: system error
message.
EXPLANATION:
The referenced file could not be accessed by the application.
USER RESPONSE:
Review and resolve the system error message, and rerun.
INFO (TFW-275): Circuit directory directory name has been removed, it was empty.
EXPLANATION:
The referenced directory has been removed.
USER RESPONSE:
WARNING (TFW-279): [Severe] Unable to unregister the experiment.

EXPLANATION:
An attempt to unregister an experiment failed. The experiment may not exist in the
globalData file or the globalData file may be corrupted.
USER RESPONSE:

Rebuild the globalData file and retry. If the problem persists, contact customer support
expe(TFW-280): riment has been removed for object testmode.

EXPLANATION:
The experiment pertaining to the testmode has been removed.
USER RESPONSE:
INFO (TFW-281): Unable to obtain write lock for experiment object, make sure it
exists and that it is not in use.
EXPLANATION:
An error was encountered attempting to write lock the object in the globalData file. This
is NOT considered severe.
USER RESPONSE:
Contacting Customer Service on page 23) should this problem persist.
WARNING (TFW-284): [Severe] An error occurred writing the dataArea to the

globalData file. The attempted write failed and corrupted the globalData file. The backup
globalData file will replace the corrupted globalData file.
EXPLANATION:
Writing to the globalData file failed. The globalData file is now corrupted and therefore
will be replaced by a backup globalData file. This could possibly be an internal code
problem.
USER RESPONSE:
Check for the following:
Space availability in the part directory.

File system related problems.

Correct any of the above problems if they exist and retry. Otherwise contact customer
support (see Contacting Customer Service on page 23) should this problem persist.
WARNING (TFW-285): [Severe] Unable to obtain a write lock on the object, make sure it
exists and that it is not in use.
EXPLANATION:
An error was encountered attempting to write lock the object in the globalData file. This
is considered severe.
USER RESPONSE:
Contacting Customer Service on page 23)
WARNING (TFW-286): An error occurred writing the globalDataBACKUP file. As a result,

there will not be any recourse to restore the globalData file should it be necessary.
EXPLANATION:
Writing to the globalDataBACKUP file failed. This file is used as a backup file in case the
original globalData file is written to improperly. Without the globalDataBACKUP we
cannot protect against globalData write problems. Processing will continue.
USER RESPONSE:
Correct any of the above problems if they exist and retry. Contact customer support (see
Contacting Customer Service on page 23) should this problem persist.
WARNING (TFW-287): The globalDataBACKUP file does not exist, restoration failed.
EXPLANATION:

Since writing to the globalDataBACKUP file failed, we could not use it to replace the
current globalData file that encountered a bad write.
Processing will continue.
USER RESPONSE:
Correct any of the above problems if they exist and retry. Contact customer
support (see Contacting Customer Service on page 23) should this problem
persist.
WARNING (TFW-288): [Severe] An error occurred while trying to restore the globalData
file. An attempt to read the globalData BACKUP file FAILED. system errorReason. The
globalData file must be re-built.
EXPLANATION:
Restoring the globalDataBACKUP file to the globalData file failed due to a read or write
problem. At this point both the globalData file and the globalDataBACKUP file are
corrupted.
USER RESPONSE:
Check for the following before rebuilding the globalData file:
Correct any of the above problems if they exist before retrying. Contact customer support
(see Contacting Customer Service on page 23) should this problem persist.
WARNING (TFW-289): The experiment experimentName does not exist for testmode
testModeName.
EXPLANATION:
The experiment for the testmode was not found on the part.
USER RESPONSE:
Check for spelling errors in the part name, testmode name, and experiment name.


INFO (TFW-600): Waiting 10 seconds to retry a operation to be tried again
operation.
The previous attempt failed due to reason (retry # current_number_tries of
total_number of tries)..
EXPLANATION:
This message states that a retry of an I/O operation has taken place.
USER RESPONSE:
WARNING (TFW-601): An I/O operation failed due to network problems.

EXPLANATION:
An I/O operation failed due to network problems.
USER RESPONSE:
Retry when the network is stable.
ERROR (TFW-602): The application is shutting down to avoid corrupting data.

EXPLANATION:
This message is produced with TFW601 to inform that the current application is
terminating to prevent data corruption.
USER RESPONSE:
Retry when the network is stable.
INFO (TFW-603): Licenses for license_name exist but all licenses are in use. This
command will wait until a license is available.
EXPLANATION:
Other invocations of this or other commands are currently using all instances of the
specified licenses. This command must wait for one of the other commands to finish and
release a license before it can continue.
USER RESPONSE:

The elapsed time for this command will include waiting for a license. To improve elapsed
times, either run this command when other commands are not using licenses, or
increase the number of available licenses.
INFO (TFW-604): License for license_name was obtained after waiting for
time_waited (hh:mm:ss.ss elapsed time). Processing continues.
EXPLANATION:
One of the other invocations of this or some other command that requires the specified
license has completed, and the license is now available. The total elapsed time spent
waiting for this license is indicated in the message.
USER RESPONSE:
To avoid waiting for the specified elapsed time, either run this command when other
commands are not using licenses, or increase the number of available licenses.
severity (TFW-901): Required keyword keyword must be specified.

EXPLANATION:
The keyword indicated in the message was not specified on the input command line.
This keyword must be specified.
USER RESPONSE:
Use the help or -h keyword to determine the valid keywords for this command. Correct
the command line and rerun.
(severity) (TFW-902): Required keyword keyword must have a value specified.

EXPLANATION:
The required keyword indicated in the message was specified on the command line
without a value. This keyword requires a specified value in the form keyword=value.
USER RESPONSE:
Use the help or -h keyword to determine the valid values for this keyword. Correct the
command line specification and rerun the application.
INFO (TFW-903): Help for keyword keyword.

EXPLANATION:
This message is followed by the help text for the indicated keyword.

USER RESPONSE:
(severity) (TFW-904): There is no registered globalData_object_definition

data.
EXPLANATION:
The globalData contains no registration of the referenced object. The object is
identified using one or more qualifiers. Examples are testmode and experiment.
USER RESPONSE:
Ensure that build_model and build_testmode tasks completed successfully and
that the workdir contains modeinfo.<testmode> data for the required testmode. In
addition, ensure that all other qualifiers are correctly specified, and then rerun.
severity (TFW-905): The keyword=value specification has an invalid value.

EXPLANATION:
The indicated value was specified for the indicated keyword. This is not a valid value for
the keyword.
USER RESPONSE:
Use help=keyword, help, or -h to determine the valid values for this keyword on this
command line. Correct the command line and rerun.
(severity) (TFW-906): The path specified by keyword=value does not exist.

EXPLANATION:
The path specified on the command line for the indicated keyword is invalid. One or more
directories in the path do not exist or are not readable.
USER RESPONSE:
Correct the path specification for the keyword or the permissions on the specified
directories and rerun.
(severity) (TFW-907): The input file specified by keyword=filename does not exist.
EXPLANATION:
The file specified for the indicated keyword does not exist. This input file must exist prior
to invocation of the application.
USER RESPONSE:

Correct the filename or create the file and rerun this application.
(severity) (TFW-908): The keyword=value specification can have only one value
specified.
EXPLANATION:
Multiple values were specified for the indicated keyword. Only one value is allowed.
USER RESPONSE:
Correct the command line specification and rerun.
(severity) (TFW-909): The keyword keyword specified in keyword=value is not a

valid keyword for this command.
EXPLANATION:
The indicated keyword was specified on the command line. It is not a valid keyword for
this command.
USER RESPONSE:
Correct the command line specification and rerun.
(severity) (TFW-910): The input file filename does not exist.

EXPLANATION:
The referenced file must exist prior to invocation of the application.
USER RESPONSE:
Ensure that the WORKDIR is correctly specified and that the file exists. If the file does not
exist, complete the prerequisite processing that is needed to create the file and then
rerun.
(severity) (TFW-911): The file filename is not writeable.

EXPLANATION:
The referenced file is not writable.
USER RESPONSE:
Change the permission of the referenced file so that it may be written and rerun.
INFO (TFW-912): keyword=value description

EXPLANATION:

Format string for "preamble" output

USER RESPONSE:
INFO (TFW-913): keyword/flag

EXPLANATION:
Format string for preamble output
USER RESPONSE:
(severity) (TFW-914): keyword and its alias alias have different values specified.
EXPLANATION:
You specified a keyword and its alias to different values. Since we do not know how to
set the value for the application, the program terminates.
USER RESPONSE:
Specify either the keyword or its alias and rerun.
(severity) (TFW-915): The input file specified by keyword=filename exists but is not
readable.
EXPLANATION:
The specified input file must be readable in order to run the application.
USER RESPONSE:
Correct the file access permission so the file may be read and rerun.
(severity) (TFW-916): The output file specified by filename=keyword cannot be

written.
EXPLANATION:
The specified output file cannot be written. Either the permissions on the existing file do
not allow it to be rewritten or the permissions on the directory do not allow the file to be
created.
USER RESPONSE:
Correct the permissions of file and/or the directory and rerun.

(severity) (TFW-917): The directory specified by directory=keyword does not

exist.
EXPLANATION:
The specified input directory does not exist.
USER RESPONSE:
Correct the directory name and rerun.
(severity) (TFW-918): The directory specified by directory=keyword exists but is

not readable.
EXPLANATION:
The specified input directory must be readable to run the application.
USER RESPONSE:
Correct the permission of the directory and rerun.
(severity) (TFW-919): The directory specified by directory=keyword exists but is

not writable.
EXPLANATION:
The specified directory must be writable to run the application.
USER RESPONSE:
Correct the permission of the directory and rerun.
(severity) (TFW-920): The directory specified by directory=keyword cannot be

created.
EXPLANATION:
The specified directory cannot be created because the application lacks write permission
for the parent directory.
USER RESPONSE:
Correct the permission of the parent directory and rerun.
(severity) (TFW-921): Keyword keyword requires other keyword(s) which were not
specified.
EXPLANATION:

The specified keyword has dependency requirements that were not met.
USER RESPONSE:
Use the information provided in the message, or help=keyword, help, -h to
determine the valid input. Correct the command specification and rerun.
(severity) (TFW-922): The keyword1_specification and

keyword2_specification are mutually exclusive and cannot be specified on the same
command line.
EXPLANATION:
The keyword specifications cannot be used together. This may be due to the keywords
being incompatible or the specified values not being compatible.
USER RESPONSE:
Correct the command specification and rerun.
INFO (TFW-923): TB_CHECKONLY=yes was specified. No syntax errors were detected.

Processing ends.
EXPLANATION:
This message informs that the syntax checking has completed and no errors were
detected. Processing ends because TB_CHECKONLY=yes was specified.
USER RESPONSE:
WARNING (TFW-924): TB_CHECKONLY=yes was specified. Syntax errors were detected.

Processing ends.
EXPLANATION:
This message informs that the syntax checking has completed and syntax errors were
detected. Processing ends because TB_CHECKONLY=yes was specified. Preceding
messages identify the syntax errors.
USER RESPONSE:
Correct the command line syntax errors and rerun.
WARNING (TFW-925): TB_CONTINUE=yes was specified. Syntax errors were detected.

Processing continue in the presence of the syntax errors.
EXPLANATION:

This message informs that syntax errors were detected, but processing will continue
because TB_CONTINUE=yes was specified. Running with syntax errors can produce
indeterminate results.
USER RESPONSE:
No response is required however it is not generally recommended to run with
TB_CONTINUE=yes.
ERROR (TFW-926): Syntax checking detected terminating errors. Correct the errors noted
in preceding messages and rerun.
EXPLANATION:
This message indicates that syntax errors have been detected and processing ends.
USER RESPONSE:
Correct the errors noted in the preceding messages and rerun.
ERROR (TFW-927): A syntax error was detected in the Encounter ATPG simulation options
in the vector file at Test Section test_section. keyword=value is invalid.
EXPLANATION:
A syntax error was detected in the Encounter ATPG simulation options in the vector file
and cause abnormal termination. This most likely occurred as a result of manually editing
of the simulation options.
USER RESPONSE:
Either rerun without specifying useatpgsimoptions=yes or correct the syntax error
in the ATPG sumulation options in the vector file and rerun.
WARNING (TFW-928): The command command_name is obsolete and will be removed in

a future release. recommended_replacement_command
EXPLANATION:
The command identified in the message is no longer supported. It will continue to work
in this release, but will be removed in a future major release.
USER RESPONSE:
If a replacement command is identified in the message, change your script(s) to use the
replacement command in order to avoid this message. When the command is removed
in the future release, only the replacement will be available and must be used for
processing. If no replacement command is provided, follow other recommendations that
accompany the message.

WARNING (TFW-929): The keyword keyword is obsolete for command_name and will be
removed in a future release.optional_text
EXPLANATION:
The keyword identified in the message is no longer supported. It will continue to work in
this release, but will be removed in a future major release.
USER RESPONSE:
If a replacement keyword is identified in the message, change your script(s) to use the
replacement keyword in order to avoid this message. When the keyword is removed in
the future release, only the replacement will be available and will have to be used for
processing. If no replacement keyword is provided, follow other recommendations that
accompany the message.
(severity) (TFW-930): Interactive help is disabled.

EXPLANATION:
Requests for interactive help from a Encounter Test program can only be honored from
a command-line prompt. This message appears when interactive help has been
specified from within a script.
USER RESPONSE:
Remove all occurrences of help from within your shell scripts and rerun if necessary.
WARNING (TFW-931): The interface_description is obsolete and will be removed

in a future release. recommended_replacement_command
EXPLANATION:
The interface identified in the message is no longer supported. It will continue to work in
this release, but will be removed in a future major release.
USER RESPONSE:
If a replacement interface is identified in the message, change your script(s) to use the
replacement in order to avoid this message. When the interface is removed in the future
release, only the replacement will be available and must be used for processing. If no
replacement interface is provided, follow other recommendations that accompany the
message.
(severity) (TFW-932): The file filename is not readable.

EXPLANATION:
The specified file is not readable.

USER RESPONSE:
Correct the permission to make the file readable and rerun.
ERROR (TFW-933): The command command_name is not a user executable. Use the
help all command to obtain a list of valid commands.
EXPLANATION:
The command identified in the message is obsolete and cannot be directly invoked. a
WARNING message indicatgeing the replacement command was issued in the previous
release.
USER RESPONSE:
If you do not remember the replacement command, either use the command help all
to print a list of all the valid commands, or invoke the previous release and execute the
same command to view the message stating the replacment command.
INFO (TFW-937): Test Section test_section ATPG simulation options:

EXPLANATION:
This informational message reports the ATPG simulation options for the referenced test
section.
USER RESPONSE:
INFO (TFW-938): Shared Memory Key collision occured.

EXPLANATION:
This Informational message reports that a Shared Memory key collision occured. In this
case, the application tries to create a different key to avoid the collision.
USER RESPONSE:
INFO (TFW-939): Shared memory request failed: : error_shm

EXPLANATION:
This is an informational message which indicates that the Shared Memory is not created
because of the reason mentioned in the message. The application will use regular
memory instead of shared memory.
USER RESPONSE:

Memory usage may be improved by sharing memory across multiple Encounter Test
processes. If the reason for the failure is due to a machine limitation (typically shmall or
shmmax), see your system administrator for assistance raising the limit(s).
WARNING (TFW-940): Failed to check Shared Memory header. Created or attached to a

new shared memory segment for function_name.
EXPLANATION:
This message indicates there is a copy of the design information in the shared memory
that is not compatible with the current version of Encounter Test. In such cases, a new
copy of the design information will be created in the shared memory by the process that
first identifies this problem. Subsequent processes attach to this shared memory or
create their own shared memory if required.
USER RESPONSE:
This message indicates that the same design information can be stored in multiple
copies as described in the explanation section. If it is required to run two different
versions of Encounter Test that have the shared memory incompatibity issues, no
response is needed. Otherwise, switching to a different machine or using a single version
of Encounter Test will prevent this message from being issued.
INFO (TFW-941): Successfully closed the Shared Memory Segment and semaphore for the
file filename.
EXPLANATION:
This Informational message reports the successful closing of the Shared Memory and
associated semaphore.
USER RESPONSE:
WARNING (TFW-942): [Severe] Keyword keyword is a developer keyword and will no

longer be allowed for general use in a future release. Processing continues in this release but
remove this keyword from your scripts.
EXPLANATION:
The specified keyword is a developer keyword and is not intended for general use. In a
future release the run will terminate.
USER RESPONSE:

Remove the keyword from the command and any scripts since in a future release the
keyword will terminate the application. If this keyword is required please contact
Cadence Customer Support (see Contacting Customer Service on page 23).
ERROR (TFW-964): There is insufficient access authority to perform the specified

processing on this part. Processing ends.
EXPLANATION:
The current part was built with restricted access authority, thus requiring the specification
of an appropriate authorization password (AUTHPASSWORD) which permits the specified
processing.
USER RESPONSE:
Ensure a valid authorization password is specified via AUTHPASSWORD. If this does not
permit required processing, consult with the Encounter Test database (tbdata) provider
to obtain necessary access authority.
SEVERITY (TFW-965): The input file or the pipe specified by filename=keyword exists
but is not readable.
EXPLANATION:
The specified input file or named pipe must be readable to run the program.
USER RESPONSE:
Correct the access permission for the file or the named pipe and rerun this program.
SEVERITY (TFW-966): The input file or the pipe specified by filename=keyword does
not exist.
EXPLANATION:
The input file or the pipe specified for the indicated keyword does not exist. This input file
or named pipe must exist to invoke the program.
USER RESPONSE:
Correct the file name or create the file or named pipe and rerun this program.
SEVERITY (TFW-967): The output file specified by filename=keyword cannot be

written.
EXPLANATION:
The specified output file or the named pipe cannot be written. Either the file does not
have the write permission or the permissions on the directory do not allow creating a file.

USER RESPONSE:
Correct the permissions of the file or the named pipe and/or the directory and rerun.
ERROR (TFW-999): [Internal] An unexpected condition occurred in Encounter Test.

Contact Cadence Customer Support (see Contacting Customer Service on page 23) to
report this error and give them the following information:
An error occurred on line line_number of source file file_name. variable_text

EXPLANATION:
This error indicates a program error that only the Encounter(R) Test team can fix. The
information provided in
this message is not intended to be meaningful to you; but it will allow the programmer to
find and fix the error
more quickly.
USER RESPONSE:

33
TGD - GlobalData Audit Messages
TGD-001 through TGD-110 on page 1157

TGD-111 through TGD-161 on page 1164
TGD-001 through TGD-110

WARNING (TGD-001): [Severe] Test Pattern Audits/Statistics record on globalData file is
back-leveled against current program level.
EXPLANATION:
The Test Pattern Audits/Statistics record being accessed from the globalData file is
incompatible with the current program level which is accessing the information. This is a
severe error. No valid Test Pattern Audits/Statistics record will be returned to the
application calling this TGD access routine. It is up to the application using the TGD
access routine to determine whether or not this is a terminating condition.
USER RESPONSE:
If the Test Pattern Audits/Statistics record is for an experiment, the experiment will have
to be rerun. If the Audits/Stats record is for a Test Mode, the Test Mode will have to be
rebuilt. If rerunning the experiment or rebuilding the Test Mode does not solve the
problem, contact customer support (see Contacting Customer Service on page 23).
WARNING (TGD-002): [Severe] Error: Null experiment name not allowed as input into
TGDputPattAuditStats.
EXPLANATION:
This is an internal program error. The application that invokes TGDputPattAuditStats did
not pass in a required parameter (experiment name). The Test Pattern Audits/Statistics
record for this experiment will not be saved to the globalData file. This is a severe error.
It is up to the application using the TGD access routine to determine whether or not this
is a terminating condition.
USER RESPONSE:

Ensure that an experiment name was specified as input to the executable program that
you ran or the EXPERIMENT environment variable is set. If it is, contact customer
WARNING (TGD-003): Bad return code received from TFWputStats trying to

store|commit Test Pattern Audits/Statistics for experiment experiment name.
EXPLANATION:
This is an internal program error. The Test Pattern Audits/Statistics record will not be
saved to the globalData file. It is up to the application using the TGD access routine to
determine whether or not this is a terminating condition.
USER RESPONSE:
WARNING (TGD-004): Error registering dependency for the uncommitted|committed Test

Pattern Audits/Stats on experiment|mode experiment name|test mode name.
EXPLANATION:
This is an internal program error. The Test Pattern Audits/Statistics record was saved to
the globalData file but the proper dependency on the experiment or test mode was not
registered successfully. It is up to the application using the TGD access routine to
USER RESPONSE:
Contact your customer support (see Contacting Customer Service on page 23).
WARNING (TGD-005): [Severe] Invalid argument(s): -string of single

character arguments found to be in error
EXPLANATION:
One or more of the arguments you used as input to the TGD application were invalid. The
invalid data is indicated in the message. The application stops.
USER RESPONSE:
Look up the correct syntax for the TGD executable application. Refer to
report_processing_status in the Encounter Test: Reference: Commands, or use -h
to get a listing of the valid arguments. Rerun using valid command syntax.
WARNING (TGD-006): [Severe] NULL TGDhandle received by program_name.

EXPLANATION:

processed by this routine due to an invalid pointer to the data. It is up to the application
using the TGD access routine to determine whether or not this is a terminating condition.
USER RESPONSE:
WARNING (TGD-007): [Severe] Error: Null test mode name not allowed as input into
TGDputMasterPattAuditStats.
EXPLANATION:
This is an internal program error. The application that invokes
TGDputMasterPattAuditStats did not pass in a required parameter (test mode
name). The Test Pattern Audits/Statistics record for this experiment will not be saved to
the globalData file. This is a severe error.
USER RESPONSE:
WARNING (TGD-008): Bad return code received from TFWputStats in

TGDputMasterPattAuditStats.
EXPLANATION:
saved to the globalData file. It is up to the application using the TGD access routine to
USER RESPONSE:
WARNING (TGD-010): [Severe] Clock Group Table record on globalData file is back-
leveled against current program level.
EXPLANATION:
The Clock Group Table record being accessed from the globalData file is incompatible
with the current program level which is accessing the information. This is a severe error.
No valid Clock Group Table record will be returned to the application calling this TGD
access routine. It is up to the application using the TGD access routine to determine
whether or not this is a terminating condition.

USER RESPONSE:
The Clock Group Table record will have to be rebuilt through Verify Test Structures. If
rerunning Verify Test Structures does not solve the problem, contact customer support
WARNING (TGD-012): [Severe] Error: Null handle not allowed as input into
TGDputCGT|TGDgetBestGroupForClock|TGDgetClockGroupList.
EXPLANATION:
This is an internal program error. The application that invokes the CGT did not pass in a
required parameter (Clock Group Table handle). The Clock Group Table record for this
Test Mode will not be saved to the globalData file. This is a severe error. It is up to the
application using the TGD access routine to determine whether or not this is a
terminating condition.
USER RESPONSE:
Ensure that a handle was specified as input to the executable program that you ran. If it
is, contact customer support (see Contacting Customer Service on page 23).
WARNING (TGD-013): Bad return code received from TFWputStats trying to store Clock
Group Table.
EXPLANATION:
This is an internal program error. The Clock Group Table record will not be saved to the
globalData file. It is up to the application using the TGD access routine to determine
USER RESPONSE:
WARNING (TGD-014): Error registering dependency for the committed Clock Group Table
on mode test mode name.
EXPLANATION:
This is an internal program error. The Clock Group Table record was saved to the
globalData file but the proper dependency on the test mode was not registered
successfully. It is up to the application using the TGD access routine to determine
USER RESPONSE:

WARNING (TGD-015): Bad return code received from TFWputStats in

TGDresetMasterPattAuditStats.
EXPLANATION:
saved to the globalData file.
USER RESPONSE:
WARNING (TGD-016): Stats for experiment name already exist.

TGDresetMasterPattAuditStats will not overlay the existing experiment stats with the
committed pattern Audit Stats for the testmode.
EXPLANATION:
An experiment already exists for the experiment passed into
TGDresetMasterPattAuditStats. The code will not overlay the existing uncommitted audit
stats with the existing committed pattern audit stats. It is up to the application using the
TGD access routine to determine whether or not this is a terminating condition.
USER RESPONSE:
Pick another experiment name and make sure that there is no existing experiment
matching the chosen name. Re-run the application passing in the new experiment name.
page 23).
WARNING (TGD-100): Errors exist on the model which could result in the production of bad
test data.
EXPLANATION:
The model has errors that could cause the test generator to create bad patterns.
USER RESPONSE:
Resolve WARNING [Severe] messages in the build_model log and rerun.
WARNING (TGD-101): Errors occurred while defining Test Mode testmode which could
cause pessimistic results.
EXPLANATION:

During build_testmode WARNINGs were generated for conditions that will cause
pessimistic simulation.
USER RESPONSE:
Resolve WARNING messages in the build_testmode log and rerun.
WARNING (TGD-102): Errors occurred while defining Test Mode testmode which could
result in the production of bad test data.
EXPLANATION:
During build_testmode WARNINGs were generated for conditions that could cause
the test data to be invalid.
USER RESPONSE:
Resolve WARNING [Severe] messages in the build_testmode log and rerun.
WARNING (TGD-103): Patterns were found with Test Inhibits overridden during fault
simulation. This could result in the production of bad test data.
EXPLANATION:
Test inhibit values were overridden during simulation..
USER RESPONSE:
Review and resolve simulate_vectors or analyze_vectors logs for WARNING
messages indicating this condition and rerun.
WARNING (TGD-104): Patterns were found with multiple clocks away from stability during
fault simulation. This could result in the production of bad test data.
EXPLANATION:
During simulation, multiple clocks were not at stability. Multiple clocks may
simultaneously be present in those vectors.
USER RESPONSE:
Review and resolve simulate_vectors or analyze_vectors logs for WARNING
messages indicating this condition and rerun.
WARNING (TGD-105): Unknown states propagated into one or more signature registers
during simulation which will cause signatures to become unknown.
EXPLANATION:

During test generation/simulation, an X was captured in a signature register which will

invalidate the signature.
USER RESPONSE:
Review and resolve the signature-based test generation log WARNING messages
indicating this condition and rerun.
WARNING (TGD-106): Value specified for globalterm during test generation or fault
simulation violates the TDR TERMINATION specification. This could result in the production
of bad test data.
EXPLANATION:
The globalterm value conflicted with the TDR value during test generation/simulation.
USER RESPONSE:
Review and resolve the test generation and simulation logs WARNING messages
indicating this condition and rerun.
WARNING (TGD-107): Hard 3-state (good machine) contention problems occurred during
simulation which could result in the production of bad test data.
EXPLANATION:
Hard three-state contention was detected during simulation.
USER RESPONSE:
Review and resolve the test generation and simulation log contention messages and
rerun.
WARNING (TGD-108): Soft 3-state (good machine) contention problems occurred during
simulation which could result in the production of bad test data.
EXPLANATION:
Soft three-state contention was detected during simulation.
USER RESPONSE:
rerun.
WARNING (TGD-109): Unknown 3-state (good machine) contention problems occurred

during simulation which could result in the production of bad test data.
EXPLANATION:

Three-state contention was detected during simulation.

USER RESPONSE:
rerun.
WARNING (TGD-110): Test patterns were simulated with risky assumptions regarding
glitches on keeper devices.
EXPLANATION:
During test generation, the MEASUREPO value was specified differently than in the TDR.
USER RESPONSE:
TGD-111 through TGD-161

WARNING (TGD-111): A signature interval value is specified which is not between min/max
for running signatures.
EXPLANATION:
During test generation, the signature interval was specified outside the allowable range.
USER RESPONSE:
WARNING (TGD-112): The fastforward option specified in the TDR is overriden.

EXPLANATION:
During test generation, the fastforward value was specified differently from the value
in the TDR.
USER RESPONSE:
WARNING (TGD-113): The MEASUREPO option specified in the TDR is overridden.

EXPLANATION:
During test generation, the MEASUREPO value was specified differently from the value in
the TDR.

USER RESPONSE:
WARNING (TGD-114): Patterns with 3-state contention exist in the output test data.
EXPLANATION:
Patterns with 3-state contention were created and not removed.
USER RESPONSE:
Resimulate the patterns using contentionreport=hard|soft|all and
contentionremove=yes.
WARNING (TGD-115): Patterns were found during simulation which produce good machine
oscillations
EXPLANATION:
Patterns with good machine oscilations were detected during simulation.
USER RESPONSE:
Review and resolve test generation/fault simulation log messages related to oscillations
and rerun.
INFO (TGD-120): The Scan/Flush tests have been generated.

EXPLANATION:
Scan and Flush tests have been created.
USER RESPONSE:
INFO (TGD-120): The Driver and Receiver test has been generated.
EXPLANATION:
Driver and Receiver tests have been created.
USER RESPONSE:
INFO (TGD-122): The IDDq test has been generated.

EXPLANATION:

IDDq tests have been created.

USER RESPONSE:
INFO (TGD-123): The Interconnect tests have been generated.

EXPLANATION:
Interconnect tests have been created.
USER RESPONSE:
INFO (TGD-124): No 3-state contention checking was performed during simulation.

EXPLANATION:
Three-state contention checking was disabled because contentionreport=none
was specified for simulation.
USER RESPONSE:
No response required if this is the intent; otherwise, rerun with
contentionreport=hard|soft contentionreport=hard | soft | all|all.
INFO (TGD-125): The type Test Section exists in the test data.
EXPLANATION:
The identified Test Section exists so that the referenced type of data has been created.
USER RESPONSE:
INFO (TGD-126): TBDbin file was created on a structure-neutral model.

EXPLANATION:
The test vectors were created for a structure-neutral model. A structure-neutral model is
used for test data migration.
USER RESPONSE:
INFO (TGD-127): Missing poly found from retrieved polyTable, new poly polynomial is
assigned for nodeid index.

EXPLANATION:
The polynomial is missing.
USER RESPONSE:
Ensure the polynomial definition is as intended and rerun if necessary.
WARNING (TGD-140): Not all required TSV tests were run for the default test methodology.
EXPLANATION:
The required Verify Test Structures tests were not run.
USER RESPONSE:
Review the verify_test_structures log for indications that checking aborted, that
the command line deselected one or more required tests, or that the run ended before
completion (ERROR messages or was killed). Rerun if necessary.
WARNING (TGD-141): Test Structure Verification has determined that Infinite X simulation
is required for latches. Results may be pessimistic.
EXPLANATION:
Verify Test Structures detected problems that will require the simulators to use infinite-X
simulation.
USER RESPONSE:
Review the verify_test_structures log for indications that infinite-X (or
pessimistic) simulation is required. Rerun if necessary.
WARNING (TGD-142): Test Structure Verification has determined that Infinite X simulation
is required for PIs. Results may be pessimistic.
EXPLANATION:
Verify Test Structures detected problems that will require the simulators to use infinite-X
simulation.
USER RESPONSE:
Review the verify_test_structures log for indications that infinite-X (or
pessimistic) simulation is required. Rerun if necessary.
WARNING (TGD-143): [Severe] TThe highest severity message received from Test
Structure Verification was WARNING [Severe]. This could result in the production of bad
test data.

EXPLANATION:
Verify Test Structures produced WARNING [Severe] messages. The test generation
results are not guaranteed to work at the tester.
USER RESPONSE:
Review and resolve verify_test_structures WARNING [Severe] log messages
and rerun.
WARNING (TGD-144): The highest severity message received from Test Structure
Verification was WARNING. This could cause pessimistic results.
EXPLANATION:
Verify Test Structures produced WARNING messages. These can cause pessimistic
results and lower test coverage.
USER RESPONSE:
Review the verify_test_structures WARNING log messages and rerun if
necessary.
WARNING (TGD-160): The number of type pins defined is greater than the TDR can
support for test mode testmode.
EXPLANATION:
The number of pins on the product that were used for test generation is greater than the
maximum number the Tester Description Rule (TDR) indicates the tester can support.
USER RESPONSE:
Change the number of pins in the TDR or select a different TDR in the test mode
definition file, or use test function BDY to select fewer pins to be included in the test, rerun
build_testmode and then rerun test generation.
WARNING (TGD-161): A test type is defined that is not supported by the TDR for test mode
testmode.
EXPLANATION:
The selected test type is not supported by the TDR.
USER RESPONSE:
Change the test type or select a different TDR in the test mode definition file and then
rerun build_testmode.



34
TGI - RPCT Boundary Scan Interconnect
Test Messages
TGI-100 through TGI-889 on page 1171
TGI-100 through TGI-889

INFO (TGI-100): Starting I/O Wrap|Interconnect Test Generation..
EXPLANATION:
The program is starting.
USER RESPONSE:
INFO (TGI-101): I/O Wrap|Interconnect Test Generation Complete.

EXPLANATION:
The program has ended.
USER RESPONSE:
INFO (TGI-103): Fault simulation of the Shorted Nets Tests is not supported. Good machine
simulation will be performed.
EXPLANATION:
Shorts between all possible external nets are not modeled as either traditional faults or
alternate pattern faults. The 2log(N) algorithm used to generate the tests requires that all
of the patterns be simulated to achieve some detects.
USER RESPONSE:

TGI - RPCT Boundary Scan Interconnect Test Messages
The Shorted Nets Tests will be fault simulated against the logic faults during reverse
simulation if fault simulation was requested. If reversesim=no and/or gmonly=yes, a
separate analyze_vectors run can be used to fault simulate the Shorted Nets Tests.
Contact customer support if there is a concern (see Contacting Customer Service on
page 23).
WARNING (TGI-104): No Shorted Nets Tests were generated because no active objective
was defined for this mode.
EXPLANATION:
The Objective pattern values for the Shorted Nets tests are created during the process
which creates the Stuck Driver Objectives for the same test mode. Some additional
processing occurs which determines the ability to control and observe the values
associated with the patterns. If there are no Stuck Driver Objectives or there is no control
and observability of the values, then no SNTs are produced.
USER RESPONSE:
Use a test mode which has static Stuck Driver Objectives defined which can be
controlled and observed.
Contact customer support if there is a concern (see Contacting Customer Service on
page 23).
INFO (TGI-201): SNT Test Generation is using the Minimal Diagnosis Algorithm
(sntmdi): log(N)+2|Partial Diagnosis Algorithm (sntpdi):
2log(N)|Complete Diagnosis Algorithm (sntcdi): (N)+1");.
EXPLANATION:
Shorted Nets Tests may be generated using one of three algorithms: log(N)+2, 2log(N)
or (N)+1 where N is the number of nets participating in the Shorted Nets Test. Each of
the three algorithms offers complete detection of shorts for the nets participating in the
test.
The differences between the three algorithms is the level of diagnosis offered by each.
The log(N)+2 generates the fewest number of SNT test vectors (sequences), provides
the lowest level of diagnosis and requires the least CPU time. The (N)+1 generates the
most number of SNT test vectors, provides the highest level of diagnosis and requires
the most CPU time. The 2log(N) algorithm is the default algorithm.
USER RESPONSE:

WARNING (TGI-202): The Vector Neutral Path

Sensitization|DriveNetsToValue phase of the SNT screening process has
discarded number of the SNT target nets. The maxsntnetdiscard rate (number%%) has
been reached. The Vector Neutral Path Sensitization|DriveNetsToValue
phase of the SNT screening processing terminates.
EXPLANATION:
Shorted Nets Test Generation begins by examining the target nets to determine if there
are possible SNT testability problems for each of the nets individually and as a collection
of nets. This is called the SNT screening process. The SNT screening process
progresses in phases and will prematurely terminate a screening phase if the
maxsntnetdiscard rate has been reached by that phase. This does not terminate the SNT
test generation process unless all target nets have been deemed untestable. The SNT
process will continue and attempt to generate SNT vectors (sequences) for those target
nets which have not been discarded by the screening process. It is likely that some or
SNT vectors will not be generated.
USER RESPONSE:
This message is an indicator that the design has insufficient or poor boundary scan
design. The expert parameter maxsntnetdiscard may be set to a higher number in an
attempt to let the SNT screening process complete without prematurely terminating. The
reporting option report=untestednets will show which nets have SNT testability
problems.
INFO (TGI-300): SDT|SDT DIAGNOSTIC|SNT Target Nets:

EXPLANATION:
This message provides a list of nets which are targeted for SDT, SDT Diagnostic, or SNT
test generation. You may control the reporting of target nets via the reporting option
report=targetnets
USER RESPONSE:
INFO (TGI-301): SDT|SDT DIAGNOSTIC|SNT Untested Nets:

EXPLANATION:
This message provides a list of nets which were targeted for SDT, SDT Diagnostic, or
SNT test generation but for which no tests were generated. For example, a net appearing
in the list of untested SDT nets has had none of the static or dynamic SDT objectives
associated with that net tested. A net appearing in the list of untested SNT nets has been

discarded due to possible SNT testability problems. You may control the reporting of
untested nets via the reporting option report=untestednets.
USER RESPONSE:
INFO (TGI-302): Ignore Nets (#IgnoreNets=number):

EXPLANATION:
This message provides a list of interconnect nets which will be ignored for interconnect
or IOWRAP test generation. An ignore reason is also listed for each net ignored.
Interconnect nets may be ignored automatically and or manually via the ignore facility in
a netsfile specification. You may control the reporting of ignore nets via the reporting
option report=ignorenet.
USER RESPONSE:
WARNING (TGI-303): [Severe] A netfile was specified however, the netfile does not
contain either an ignore or target facility.
EXPLANATION:
This message indicates that the user has requested that interconnect or IOWRAP test
generation be performed with a list of target nets and or ignore nets yet the netfile
specified does not contain any ignore or target net facilities.
USER RESPONSE:
If Interconnect or IOWRAP test generation is to be performed with a list of ignore an or
target nets, the ensure that the desired netfile is specified and that the netfile contains
the appropriate ignore and or target facilitie(s)
ERROR (TGI-304): An observefile was specified however, the file does not contain any valid
observe points.
EXPLANATION:
This message indicates that the user has requested that interconnect or IOWRAP test
generation use the specified list of observe latches for the shorted nets test yet the file
specified does not contain any valid observe points within a RECEIVER_OBSERVE
facility.
USER RESPONSE:

Ensure that the desired observefile is specified and that the file contains valid observe
point specifications.
ERROR (TGI-305): Cannot resolve receiver to a receiver node.

EXPLANATION:
The observefile specified a receiver which could not be correlated to an objectives
receiver node.
USER RESPONSE:
Ensure that the desired receiver correlates to an objectives receiver node.
ERROR (TGI-306): Cannot resolve observePoint to an observe point for receiver

receiver.
EXPLANATION:
The observefile specified an observe point which cannot be correlated to an observe
point for the associated receiver.
USER RESPONSE:
Ensure that the desired observe point correlates to a receiver node.
INFO (TGI-307): Static|Dynamic SDT test generation has adjusted the ranking of
observe points for the following (number) receivers using information contained in the user
defined observe file.
EXPLANATION:
USER RESPONSE:
INFO (TGI-600): No DC|DC Diagnostic|Unknown objectives defined for processing.

EXPLANATION:
This message indicates that there no SDT objectives defined for test generation.
USER RESPONSE:
This message may appear when there are no target nets identified for test generation. It
may be that possible target nets have been ignored and or that there really are no target
nets. For example, there may be no target interconnect tri-state multi-source nets which
are normally targeted by SDT Diagnostic test generation.

ERROR (TGI-860): [Internal] TTCtgi detected a null pointer for a TBDtestSectionID or

TBDtesterLoopID.
EXPLANATION:
This messages indicates that an unexpected application error has occurred. Processing
will continue if possible.
USER RESPONSE:
ERROR (TGI-889): [Internal] Application error detected: TGIsdtTestGen:

Unexpected SDT objective type passed|TGIsdtTestGen: Unexpected
SDT objective logic state|TGIsdtTestGen: Unexpected/Unsupported
logic primitive feeds multisource net|TGIsntObjL: Unexpected
SNT target net| TGIsntTestGen: Unexpected SNT vector Net value.
EXPLANATION:
This messages indicates that an unexpected application error has occurred.
USER RESPONSE:

35
TGR - Test Simulation and Manipulate
Tests Messages
TGR-006 through TGR-050 on page 1177

TGR-006 through TGR-050

INFO (TGR-006): Processing of the vectors file will proceed direction.
EXPLANATION:
This message is intended to clarify which direction the vectors file is being processed.
USER RESPONSE:
ERROR (TGR-007): There is no input experiment specified. The input experiment

(INEXPERIMENT) or the master file flag (-m) must be specified.
EXPLANATION:
The analyze_vectors command needs an input experiment name or a master flag to
be able to determine the names of the input files.
USER RESPONSE:
Rerun and provide the input experiment name or indicate a master by using a flag. Refer
to "analyze_vectors in the Encounter Test: Reference: Commands for additional
information.
ERROR (TGR-008): There is no output experiment (EXPERIMENT) specified. Since the

input experiment is the master bin file and the master bin file cannot be overwritten with the
experiment data, an output expereiment (EXPERIMENT) must be specified.

TGR - Test Simulation and Manipulate Tests Messages
EXPLANATION:
The analyze_vectors command requires a specified output experiment since the
input experiment is the master bin file which cannot be overwritten because it is
committed data.
USER RESPONSE:
Specify an output experiment name and rerun. Refer to "analyze_vectors in the
ERROR (TGR-009): You must specify either an input experiment (INEXPERIMENT) or an

output experiment (EXPERIMENT) or both according the to following guidelines:
1. Set the INEXPERIMENT and EXPERIMENT to write the output to EXPERIMENT. The
INEXPERIMENT bin file will not be updated.
2. Set INEXPERIMENT and do not set EXPERIMENT to write the output to be written out to
the same name as INEXPERIMENT.
Note: The INEXPERIMENT bin file will be overwritten.
3. Not setting INEXPERIMENT and setting EXPERIMENT will assume the master bin file is
the INEXPERIMENT. The Output will be written to the EXPERIMENT file. If the master bin
file does not exist, another error message will be produced.
EXPLANATION:
analyze_vectors requires either an input experiment or output experiment to
determine the name of the output file.
USER RESPONSE:
Specify an input or output experiment and rerun based on the guidelines stated in the
message text. Refer to "analyze_vectors in the Encounter Test: Reference:
ERROR (TGR-010): Unable to get circuit model context pointer. Review and resolve flat
model error messages.
EXPLANATION:
The analyze_vectors command requested the flat model services to return the
context pointer. It was returned as zero. analyze_vectors cannot proceed. There
should be messages from the flat model services that indicate the problem.
USER RESPONSE:
Resolve the flat model error condition and rerun.

ERROR (TGR-011): Unable to open the design model. Review and resolve flat model error
messages.
EXPLANATION:
The analyze_vectors command requested the flat model services to load the flat
model. It has indicated that there was a problem with loading. There should be messages
from the flat model services that indicate the problem.
USER RESPONSE:
ERROR (TGR-012): Unable to select the specified test mode. Review and resolve test mode
error messages.
EXPLANATION:
The analyze_vectors command requested the flat model services to set the test
mode. It has indicated that there was a problem with setting. There should be messages
from the flat model services that indicate the problem.
USER RESPONSE:
ERROR (TGR-013): Unable to load methods to access the circuit. Review and resolve test
mode error messages.
EXPLANATION:
The analyze_vectors command requested the flat model services to load the model
methods. It has indicated that there was a problem with loading. There should be
messages from the flat model services that indicate the problem.
USER RESPONSE:
ERROR (TGR-014): The compact_vectors command cannot sort input vectors by test
sequence. It is trying to sort by test procedure but cannot use the value defined for the
reorderkeys keyword. Remove reorderkeys from the command specification, specify
reorder=coverage and reordercoverage=both and rerun.
EXPLANATION:
The input vectors contain a setup sequence which requires us to compact vectors at the
test procedure level. The reorderkeys keyword contains something other than
static or dynamic which cannot be processed when sorting by test procedure.

USER RESPONSE:
Remove reorderkeys from the command specification, specify reorder=coverage
and reordercoverage=both and rerun.
ERROR (TGR-018): The specified EXPERIMENT must be the same as INEXPERIMENT

when updateonly=yes is specified. Specify identical names and rerun.
EXPLANATION:
For an updateonly run, the EXPERIMENT and INEXPERIMENT must be identical. If
only one is specified, the program will set the other equal.
USER RESPONSE:
Specify identical EXPERIMENT and INEXPERIMENT names the same or let the program
default one of them and then rerun.
WARNING (TGR-019): License to run Encounter Test is not available. Contact your site
license manager. If your site has licenses available, contact Cadence Customer support.
EXPLANATION:
The program was unable to obtain a license for the type of run which is being made.
USER RESPONSE:
Contact your system administrator to verify the license is present and available, If
licenses are available, contact customer support (see Contacting Customer Service on
page 23).
ERROR (TGR-031): Unable to obtain a lock on the hier model at this time. This generally
indicates that another application is updating information in the hier model files (usually
globalData). Wait until the other application is done. If there is no other application running
on this same part, look for the locks in the sub-directory under the tbdata directory, remove
the locks and rerun.
EXPLANATION:
The application failed to obtain a read lock in the hier model. This generally indicates that
another application is updating information in the hier model files (usually globalData).
USER RESPONSE:
Wait until the other application is done with the model file and rerun this application. If no
other application running on this same part, look in the working directory for a sub-
directory named locks, remove it and rerun.

ERROR (TGR-032): Unable to obtain a read lock on the testmode (testmode) at this time.
This generally indicates that another application is updating information for the testmode.
Wait until the other application is done. If there is no other application running on this same
part, look for the locks sub-directory under tbdata directory, remove it and rerun.
EXPLANATION:
The application failed to obtain a read lock on the testmode files.The testmode cannot
be accessed and processing stops. This generally indicates that another application is
updating information for the testmode.
USER RESPONSE:
Wait until the other application is done with the testmode and rerun this application. If
there is no other application running on this same testmode, look in the part directory for
a subdirectory named locks, remove it and rerun.
ERROR (TGR-034): Failed to get a read lock on experiment experiment. The experiment
is not registered in the globalData or the wrong experiment is specified. Verify the
experiment is valid and registered in globalData.
EXPLANATION:
The analyze_vectors command has attempted to obtain a read lock on this
experiment and the return indicates that the experiment is not registered in the
globalData.
USER RESPONSE:
Specify an existing experiment and rerun.
WARNING (TGR-035): [Severe] Failed to get a read lock on experiment experiment.

The experiment is already in use by another application. Wait until the other application is
done. If there is no other application running on this same part, look for the locks sub-
directory under the tbdata directory, remove it and rerun.
EXPLANATION:
The analyze_vectors command has attempted to obtain a read lock on the
experiment and the return indicates that the experiment is in use.
USER RESPONSE:
Rerun after the experiment is free to be used.
ERROR (TGR-036): Failed to get a write lock on experiment experiment in parent

testmode parent testmode. The return code indicates that it is already in use. Wait until

the other application is done. If there is no other application running on this same part, look
for the locks sub-directory under the tbdata directory, remove it and rerun.
EXPLANATION:
The analyze_vectors command has attempted to obtain a write lock on the
experiment and the return indicates that the experiment is in use.
USER RESPONSE:
Rerun after the experiment is free to be used.
INFO (TGR-037): The comparemeasures keyword has been been turned off. The input
experiement has deleted tests and has memory. This will result in different values at measure
latches.
EXPLANATION:
An audit of the input experiment indicates that the vectors have been deleted and a tester
loop attribute indicates that memory exists. The output of simulation will result in different
values at measure latches than the input experiments measure latches. The high-speed
scan based and general purpose simulators will not compare measure latches since
differences are expected.
USER RESPONSE:
ERROR (TGR-040): Unable to open the experimental fault model file experiment. This
may be due to insufficient access authority, insufficient space in the output directory, or a
conflict with another experiment with the same name. Verify that all these conditions are
resolved before rerunning.
EXPLANATION:
The fault model for the specified EXPERIMENT could not be opened. This may be due to
insufficient access authority, insufficient space in the output directory, or a conflict with
another experiment with the same name.
USER RESPONSE:
Ensure that you have write access to the working directory (WORKDIR) and any
directories pointed to with TB_PERM_SPACE. If you have sufficient authority, ensure that
there is sufficient space in one of the directories for the new
faultStatus.testmode.experiment file. If the authorizations and space are
sufficient, ensure that you did not have another experiment with the same name for the
same test mode running at the same time. Rerun after verifying or resolving the
preceding conditions.

ERROR (TGR-041): Unable to open existing experimental fault model file for experiment
experiment. The append keyword is set to yes, so a fault model should exist. Verify that
a fault model exists. If not, remove the append specification and rerun.
EXPLANATION:
The append keyword specification indicates indicates that the specified experiment
should exist. Since the fault model program did not open it, the program has assumed it
does not exist.
USER RESPONSE:
If the intent is not to append to an existing experiment, deselect the GUI Append to
Existing Experiment option or specify append=no and then rerun.
If the intent is to append to an existing experiment, ensure that the EXPERIMENT is
correctly specified and rerun if necessary.
If the experiment name is correct, ensure that the previous run with that experiment
name successfully completed and that the faultStatus.testmode.experiment
still exists in the part directory. If necessary, rerun after examining these conditions.
ERROR (TGR-042): Unable to open existing input experiment fault model. Ensure that input
experiment (INEXPERIMENT) named inexperiment_name is a valid existing experiment.
EXPLANATION:
The fault model program did not sucessfully open the specified INEXPERIMENTs fault
model.
USER RESPONSE:
Ensure the input experiment name exists and is registered and then rerun.
ERROR (TGR-043): Unable to initialize the simulator. Respond to the simulators messages.
EXPLANATION:
The simulator was called to setup its initialization. The return indicates that it has failed.
USER RESPONSE:
Review and resolve the simulation messages and then rerun.
ERROR (TGR-044): Unable to open TBD binary file for read. Respond to TBD messages.
EXPLANATION:
TBD has been called to open and read the input binary file. The return indicates that it
has not happened.

USER RESPONSE:
Review and resolve the TBD messages and then rerun.
ERROR (TGR-045): Unable to initialize input TBD for read. Respond to TBD messages.
EXPLANATION:
TBD is called to initialize the vector file, but has failed.
USER RESPONSE:
Review and resolve the TBD messages and then rerun.
WARNING (TGR-046): Unable to save globalData. Output files may exist but are not
registered.
EXPLANATION:
analyze_vectors has asked that the globalData be saved. The return from this action
globalData file is suspect.
USER RESPONSE:
WARNING (TGR-046): Error attempting to save globalData. Output files may exist but are
not registered.
EXPLANATION:
analyze_vectors has asked that the globalData be saved. The return from this action
globalData file is suspect.
USER RESPONSE:
INFO (TGR-047): compact_vectors will reorder test vectors by coverage at the test
procedure level. The input vector is either WRP or LBIST patterns or contains a setup
sequence.
EXPLANATION:
Test vectors cannot be reordered at the test sequence level since WRP/LBIST patterns
have loopable test sequences. The test coverage information is only available at the test

procedure level. Setup sequences cannot be reordered since they initialize data for the
subsequent tests.
USER RESPONSE:
INFO (TGR-048): There is memory between test procedures. Test vectors will be reordered
in forward direction at test procedure level.
EXPLANATION:
Test vectors cannot be reordered at test sequence since memory exists between a test
procedure or a tester loop.
USER RESPONSE:
INFO (TGR-049): Copying untestable fault status from the input experiment experiment
to the output experiment experiment.
EXPLANATION:
The verbose flag is on and analyze_vectors is informing of its current phase.
USER RESPONSE:
WARNING (TGR-050): Experiment experiment to which program is to append does not

exist. The run will continue without appending.
EXPLANATION:
An append has been specified to an experiment which is not registered. The run will
continue with using the experiment name without append.
USER RESPONSE:
Specify an existing experiment name and rerun if an append is desired.

ERROR (TGR-052): ScanType1149 test vectors can only run with simulation options
hsscan, gp or delaysim. The simulation keyword is probably set to signature.
Specify simulation to hsscan, gp or delaysim and rerun.

EXPLANATION:
The ScanType1149 runs correctly only with hsscan, gp or delaysim.
USER RESPONSE:
Specify a valid option for the simulation keyword and rerun.
WARNING (TGR-053): Test section of type test_section_type encountered.

Simulator=simulator_type does not simulate this type of test section
additional information. The run continues with the next test section.
EXPLANATION:
analyze_vectors will not send a test section to a simulator if it is not capable of
simulating this type. analyze_vectors will continue with the next test section and send
it to the simulator if it is an acceptable type.
If the test_section_type is signature-based, the simulation will need to include channel
simulation.
USER RESPONSE:
Accept if okay. Else plan to use another type simulator, or select just the skipped section
and simulate with another type of simulator. If the skipped section was signature-based,
ensure that channelsim=yes was specified on the command line. From the GUI, click
the Advanced button on the Analyze Vectors form, then click the Simulation tab to
set options for Signature-Based Simulation (Channel Simulation).
WARNING (TGR-054): Test section, test_section_type, cannot be simulated with

testpercent parameter. The run continues with the next test section.
EXPLANATION:
Analyze Vectors does not support the testpercent keyword for WRP and LBIST
patterns. The testpercent keyword is only applicable to stored pattern test sections.
USER RESPONSE:
Use the testrange keyword with (interval,iteration) in the odometer syntax for
subsetting WRP or LBIST patterns. If conversion to stored pattern is desired, use the
seqsample keyword to limit the iteration.
ERROR (TGR-060): An invalid keyword value was specified: keyword=parm_value.

Run ends.
EXPLANATION:

A keyword value cannot be checked by the keyword parser because it includes

<string>.
This message gives additional informatin on the keyword failure.
USER RESPONSE:
Specify a valid keyword value and rerun. Refer to "analyze_vectors in the Encounter
Test: Reference: Commands for additional information.
ERROR (TGR-065): altfault=##TB_SDT must also be specified when the keyword value
simictnets=pkgio|nonpkgio is specified.
EXPLANATION:
The use of Package I/O or Non-Package I/O nets requires the use of the alternate fault
model ##TB_SDT.
USER RESPONSE:
Run with a specified alternate fault model. Specify build_alternate_faultmodel
overwrite=yes sdtsnt=only with the current release of Encounter Test to rebuild
the alternate fault model with the correct data to support this use of simictnets, OR,
modify the command line so simictnets=all will be used.
ERROR (TGR-066): The keyword simictnets=pkgio|nonpkgio is specified, but the

faultModel does not contain information to enable fault simulating only Package I/O
Nets|Non-Package I/O Nets.
EXPLANATION:
Only faults on Package I/O nets (simictnets=pkgio) or Non-Package I/O nets
(simictnets=nonpkgio) were requested to be fault simulated.
The alternate fault model, which is used by the fault simulator, was built with a prior
release of Encounter Test, and does not contain the information required to distinguish
between Package I/O and Non-Package I/O nets.
Therefore, the run terminates.
USER RESPONSE:
Run build_faultmodel overwrite=yes sdtsnt=only with the current release of
Encounter Test to have the alternate fault model rebuilt with the correct data to support
this use of simictnets, OR, modify the command line so simictnets=all will be used.
ERROR (TGR-070): [Internal] Fault simulation failed. type_area failed with a return
code of return_code. Contact Cadence Customer Support for assistance.

EXPLANATION:
The simulator was called to process some part of the vectors file.The type_area gives
the part of the vectors file that is being processed, and the return_code is the value
given by the simulator.
USER RESPONSE:
WARNING (TGR-071): Test patterns are being reordered (manipulated). The logic test
signature type is RUNNING/FINAL, but recomputesignatures=no was specified which
may produce a wrong final signature. recomputesignatures=yes is forced for this run.
EXPLANATION:
Force to recompute the signature if logic test signature type is RUNNING/FINAL and test
patterns are being manipulated.
USER RESPONSE:
No response required, however to avoid this message, specify
recomputesignatures=yes.
WARNING (TGR-072): The logic test signature type is RUNNING/FINAL,

removeXlatch=yes is forced to remove tests which produce UNKNOWN in measurable
latches..
EXPLANATION:
Force to remove the test which produces UNKNOWN in measurable latches.
USER RESPONSE:
No response required, however to avoid this message, specify removexlatch=yes.
ERROR (TGR-079): Cannot use delay simulator to resimulate WRP or LBIST patterns.
Rerun with simulation=signature or manipulate=convert2sp.
EXPLANATION:
WRP or LBIST can only be run with simulation=signature or
manipulate=convert2sp.
USER RESPONSE:
Rerun using simulation=signature or manipulate=convert2sp.

ERROR (TGR-080): Failed getting the Audit Statistics. Check and respond to audit (TGD)
messages.
EXPLANATION:
analyze_vectors has attempted to obtain the pattern audit statistics. The return
indicates that this was unsuccessful. analyze_vectors cannot continue.
USER RESPONSE:
See the Audit messages, resolve and rerun.
ERROR (TGR-081): Cannot delete a file file_name. Check for system messages.
Otherwise, contact Cadence Customer Support.
EXPLANATION:
analyze_vectors has unsuccessfully attempted to remove the file. The run
terminates.
USER RESPONSE:
Review and resolve system messages that accompany this message and then rerun.
ERROR (TGR-082): Error attempting to rename file file_name to file_name. Check

for system messages. Otherwise, contact Cadence Customer Support.
EXPLANATION:
analyze_vectors has attempted to renane the first file name to the second file name.
The action was unsuccessful. The run terminates.
USER RESPONSE:
Review and resolve system messages that accompany this message and then rerun.
ERROR (TGR-083): The Input Vectors file of an earlier release is not compatible with the
current release.
EXPLANATION:
Starting with release 0401 the assumptions on the state of the PIs is different than
before. The two may not be compatible with each other.
USER RESPONSE:
Use the TBDmigrate function to the order of the PI commands. Or use the
oldbin=yes to simulate the old order. There may be differences in the simulation values
between the two levels.

ERROR (TGR-086): The input vector file has a test section which has not been simulated,
and therefore no signatures exist. recomputesignatures=no was specified, which is not
allowed when there is a test section that has not been simulated. Remove the
recomputesignatures keyword specification and rerun.
EXPLANATION:
recomputesignatures=no has been specified to save run time. However, the
signatures have not been computed in a test section because it was not simulated. The
input vector file is probably a manual patterns file.
USER RESPONSE:
Remove the recomputesignatures keyword and rerun.
ERROR (TGR-087): testpercent is not allowed on test vectors that have memory.
Remove the testpercent keyword and rerun.
EXPLANATION:
The program cannot process a certain test percentage of test of each test procedure if
the test vectors have memory.
USER RESPONSE:
Rerun without the testpercent keyword.
severity (TGR-099): secondary message severity End of analyze_vectors.

EXPLANATION:
This message indicates the end of the application
USER RESPONSE:
INFO (TGR-100): Processing testsection typ test section with test type test type
begins.
EXPLANATION:
As analyze_vectors is reading the input Vectors file it prints this informational
message to note the place in the log where it encountered each test section type in the
input Vectors file. Both start and end.
USER RESPONSE:


INFO (TGR-101): Processing testsection typ test section with test type test type
completed.
EXPLANATION:
As analyze_vectors is reading the input Vectors file it prints this informational
message to note the place in the log where it encountered each test section type in the
input Vectors file. Both start and end.
USER RESPONSE:
INFO (TGR-102): Set globalterm to global term value {0,1,z,x} if no

globalterm was used in the input tests.
EXPLANATION:
If a value is specified for the globalterm keyword, the value is applied to the test
section if this test section does not yet have any tester termination. Otherwise, the
globalterm is ignored unless the developer keyword forcehterm=yes is specified.
USER RESPONSE:
INFO (TGR-103): Unconditionally override globalterm to global term value

{0,1,z,x} for the tests under resimulation
EXPLANATION:
If the keyword globalterm and developer keyword forcehterm=yes are both
specified, the globalterm value is unconditionally applied to the tests under
resimulation.
USER RESPONSE:
ERROR (TGR-111): Invalid specification of testrange keyword - trange_parm. It must be

of the following forms:
testrange=testgroup, testgroup, ...

testgroup=odometer:odometer
odometer=blank, stored pattern type, signature-based type (for example, 1.1.1.3 or

1.1.1.2.5 for stored pattern type and 1.1.1.3(1.1) or 1.1.1.5(5.256) for signature-based type)
testnumber=test sequence number in the vector file
Specify analyze_vectors help=testrange to obtain extended help for this keyword.

EXPLANATION:
The specified values for the testrange keyword are invalid. Adhere to the following
guidelines:
testrange=testgroup,testgroup,...
where testgroup is one of the following:
odometer to process a single piece of test data
odometer: - to process test data beginning with odometer and ending at
the end of the test data
:odometer - to process from the beginning of the test data to the end of the
odometertest data
odometer:odometer - to process beginning with odometer test data to
the end of the odometer test data
odometer=stored pattern type (for example, 1.1.1.3) or signature-based type (for
example, 1.1.1.3(1.1))
testnumber - specify a test sequence number in the vector file
USER RESPONSE:
Specify analyze_vectors help=testrange to obtain extended help for this
keyword.
WARNING (TGR-112): The specified testrange starts inside of

sequences_have_memory. Since the restorestate keyword has been specified, the,
testrange will be used. The program assumes the user knows how to align the testrange
with the save state; the program does not make this check. The program also assumes the
user is responsible for setting a testrange inside of sequences_have_memory.
EXPLANATION:

Normally a testrange is not allow to start within a sequences_have_memory range.

Otherwise, a simulator would have to start simulation without having the build up memory
in the latches and RAMS.
With a restorestate=yes specified for General Purpose Simulation, the assumption
is made that the user knows how to align the range and the save state. The system has
no way to make this check.
USER RESPONSE:
Accept the liability. There is no check.
WARNING (TGR-113): The specified testrange starts inside of

sequences_have_memory. This is not allowed, sequences_have_memory will be
preserved. Either specify a testrange that includes memory or save the states and then
rerun with the restorestates keyword.
EXPLANATION:
Normally a testrange is not allowed to start within sequences_have_memory range.
Otherwise, a simulator would have to start simulation without having the build up memory
in the latches and RAMS. This is not allowed. The sequences_have_memory will be
preserved.
USER RESPONSE:
If you are using General Purpose Simulation and have done a savestate, a
restorestate is required, in which case the testrange will be used.
INFO (TGR-135): The pattern file (TBDbin) is empty. No patterns have been saved for this
experiment.
EXPLANATION:
The pattern file (TBDbin) is empty. No patterns have been saved for this experiment.
USER RESPONSE:
WARNING (TGR-144): The design has non-zero pipeline depth. The input experiment was
not manipulated. The simulation continues, but the test data might be inaccurate. Run
insert_vector_pipeline_sequence to manipuate the input experiment and then rerun
the simulation.
EXPLANATION:
Patterns are not manipulated for Scan Control Pipelines.

USER RESPONSE:
Manipulate the input experiment by running insert_vector_pipeline_sequence
and then resimulate the input experiment.
ERROR (TGR-145): Cannot append to experiment experiment name because it

contains Scan Control Pipeline patterns that have already been manipulated. Specify a
different input experiment name and commit the experiment or remove append=yes and
rerun
EXPLANATION:
Pattern audit information indicates the input experiment has already had its patterns
manipulated for Scan Control Pipelines. Encounter Test is unable to append to this
experiment under these conditions.
USER RESPONSE:
Perform one of the following actions to resolve this condition:
Specify a different input experiment name to create an additional experiment
Run commit_tests to commit the experiment and continue your
methodology,
Specify append=no (or remove append=yes) to overwrite the current
experiment and patterns.
INFO (TGR-200): Parameter settings for this run:

EXPLANATION:
This messag lists limited keywords that are applicable to the resimulation run. This
information is produced in verbose mode.
USER RESPONSE:
ERROR (TGR-302): Program was unable to restart from a CheckPoint record. Contact
EXPLANATION:
The program was trying to obtainp information from a checkpoint record, and failed in the
process.
USER RESPONSE:

INFO (TGR-303): No Check Point is to be taken for the run. Set the checkpoint keyword
to a non-zero value to allow checkpoints
EXPLANATION:
The checkpoint was specifed as zero indicating that no checkpoint is to be taken.
USER RESPONSE:
If checkpoint deta is desired, specify a non-zero value for the checkpoint keyword;
othersie, no response is required.
INFO (TGR-304): A Check Point will be taken every elapsed time minutes.
EXPLANATION:
A checkpoint value was specified or it defaulted to 60 minutes.
USER RESPONSE:
INFO (TGR-305): The Check Point ID checkpoint_ID will be ignored since

restart=no is specified.
EXPLANATION:
A checkpoint record was found, however the program was requested to start anew as a
result of the restart=no keyword specification.
USER RESPONSE:
INFO (TGR-306): The run will start from the Check Point ID checkpoint_ID.
EXPLANATION:
The run will start at the checkpoint record and proceed.
USER RESPONSE:
ERROR (TGR-307): Program was unable to take a successful Check Point. Contact
EXPLANATION:
A system action failed while attempting to take a checkpoint.

USER RESPONSE:
INFO (TGR-308): The run will start from the Check Point ID<checkpoint_ID > but will
stop at the end of this test procedure since restart=end is specified.
EXPLANATION:
A checkpoint record was found. However, program was asked to bring the run to an
orderly halt, and clear out the checkpoint data.
USER RESPONSE:
ERROR (TGR-309): The keyword keyword has different values between the check pointed
and the restarted runs. Specify the same keyword value as the checkpointed run and rerun.
EXPLANATION:
A critical keyword value was found to be different in this run from the checkpointed run.
USER RESPONSE:
Specify the same keyword value as the checkpointed run and rerun.
ERROR (TGR-310): Cannot run the Parallel Process due to initialzation errors. Stopping all
Slave processes. Respond to previous error messages in the run.
EXPLANATION:
Conditions require that the parallel processing (master) cleans up slave processes and
gracefully end.
USER RESPONSE:
Review and resolve other error messages in this run and then rerun.
ERROR (TGR-311): Parallel processing run requires hosts or numslaves keyword. Provide
a list of hosts or set numslaves or llmachines with numslaves if LSF or Load Leveler is
desired.
EXPLANATION:
parallelprocess=yes requires either hosts, llmachines, or numslaves where
llmachines requires numslaves to be specified. hosts and numslaves are used to
determine how many slave processing to spawn. If the user is giving the target machines,

use host keyword. If the user is using Distributed Resource Management tools such as
LSF or Load Leveler, specify numslaves or llmachines with numslaves keyword.
USER RESPONSE:
Provide a list of hosts or set numlsaves or llmachines with numslaves if LSF or
Load Leveler is desired.
ERROR (TGR-340): Parallel processing with gmonly=yes is not allowed. Parallel

processing only applies to fault simulation at this time. Remove the gmonly=yes keyword
specification or run a uni-process resimulation.
EXPLANATION:
The parallel effort under the present algorithm only applies to the fault simulation effort.
It is a waste of time and machine resources to be running gmonly under parallel
processing.
USER RESPONSE:
Rerun either with removal of the gmonly=yes keyword specification or use a uni-
process resimulation.
ERROR (TGR-341): Running delaysim under parallel processing is disallowed. Delay

simulation is a good machine only simulation. Parallel processing only applies to fault
simulation at this time. Run normal simulation of using delaysim.
EXPLANATION:
Delay simulation is a good machine only simulation.There are no benefits from running
under a parallel process.
USER RESPONSE:
Run a normal uni-process simulation run if using delaysim.
ERROR (TGR-342): Running WRP/LBIST pattern simulation under parallel processing is

disallowed. The interface is not available to resimulate WRP/LBIST patterns in parallel
processing. Run uni-process simulation.
EXPLANATION:
There is no support to re-simulate WRP/LBIST patterns in parallel processing.
USER RESPONSE:
Run a uni-process resimulation by removing the keywords hosts, llmachine or
numslaves.


36
THT - Hierarchical Core Test System
Messages
THT-001 through THT-599 on page 1199

THT-600 through THT-999 on page 1205
THT-001 through THT-599

INFO (THT-030): Loading the core to chip map correspondence file filename.
EXPLANATION:
The description file containing all pin mapping for this run is being loaded.
USER RESPONSE:
WARNING (THT-032): [Severe] The core to chip map correspondence file filename
EXPLANATION:
The file containing core to chip mapping (coreToChipMap.<testmode>) should
reside in the tbdata directory. This file could not be opened.
USER RESPONSE:
Either the file does not exist in the directory or the permissions do not allow this file to be
read. Check the filename and permissions.
WARNING (THT-034): [Severe] The core to chip map correspondence file filename is
empty.
EXPLANATION:

THT - Hierarchical Core Test System Messages
The file containing core to chip mapping (coreToChipMap.<testmode>) exists but

the file does not contain any data.
USER RESPONSE:
Check the core to chip mapping file for mapping data.
WARNING (THT-036): [Severe] The core to chip map correspondence file filename
contains no usable data.
EXPLANATION:
The file containing core to chip mapping (coreToChipMap.<testmode>) exists but
the file contains no usable data.
USER RESPONSE:
Check the core to chip mapping file for the correct format and data.
WARNING (THT-051): [Severe] The core pattern migration data file filename was not
found.
EXPLANATION:
The coremigrationpath keyword combined with the cell name for the core formed a
fully qualified path name to a file which does not exist.
USER RESPONSE:
Ensure the coremigrationpath entered is correct and that the directory containing $
the test data for this core cell name exists.
INFO (THT-060): Processing core pattern migration data file filename.

EXPLANATION:
This informational message provides the name of the pattern file to be migrated.
USER RESPONSE:
WARNING (THT-080): [Severe]The core input pin pinname does not have a
correspondence pin needed for the sequence_type sequences.
EXPLANATION:
to the core.

USER RESPONSE:
Ensure the core input pin is listed in the core to chip mapping
(coreToChipMap.<testmode>) file.
WARNING (THT-082): [Severe] The core output pin pinname does not have a
correspondence pin needed for the sequence_type sequences.
EXPLANATION:
USER RESPONSE:
Ensure the core output pin is listed in the core to chip mapping
WARNING (THT-086): [Severe] The MISR output pin pinname does not have a
correspondence pin.
EXPLANATION:
USER RESPONSE:
Ensure the core output pin is listed in the core to chip mapping
WARNING (THT-090): [Severe] A suitable operation was not found for event event This
EXPLANATION:
USER RESPONSE:
Ensure that all pins exercised in this event are in the core to chip mapping
WARNING (THT-116): [Severe] The event type eventtype at event eventodom is not
supported in the core's test data.
EXPLANATION:
Core Test supports several event types but this is not one of them.

USER RESPONSE:
WARNING (THT-119): [Severe] Due to severe messages issued during the run, stimulus
or measure data may be missing from the output patterns. Verify the tests by performing
Verilog simulation.
EXPLANATION:
If severe messages are issued during the run, the output patterns may not contain all
stimulus and measure data. Therefore, the tests may not work at the tester. Verify that
the tests will work by performing Verilog simulation.
USER RESPONSE:
Correct any severe messages issued prior to this message and rerun
migrate_core_tests.
WARNING (THT-132): [Severe] One or more measures on MISR output pins were
encountered in event event. These pins will be ignored.
EXPLANATION:
A Measure_PO event contained one or more MISR output pins to be measured. MISR
output pins are only measured during a Composite_MISR_Signature event.
USER RESPONSE:
Currently the measuring of MISR output pins in the core's test data is not supported.
WARNING (THT-150): [Severe] Latch correspondence in the core modeinit sequence for
EXPLANATION:
USER RESPONSE:
Choose the PIPO correspondence type in the coreToChipMap file for all exercised pins
in the core's modeinit sequence.
WARNING (THT-152): [Severe] Latch correspondence in a scanop sequence for event

EXPLANATION:

scan chain at the same time the core scan chain was being loaded. This would most
USER RESPONSE:
Choose the PIPO correspondence type in the coreToChipMap file for all exercised pins
in the core's scanop sequences.
WARNING (THT-154): [Severe] Latch correspondence for event type eventtype is not
supported.
EXPLANATION:
Core pins that are pulsed, scanned in, or scanned out must not have latch
corrupt core data.
USER RESPONSE:
Choose the PIPO correspondence type in the coreToChipMap file for all pins that will
be pulsed or used as scan in or scan out pins.
WARNING (THT-160): [Severe] The test patterns being processed contain MISR Observe
Select (MOS) states for the core. In order to process these states, a chip description file
containing the chip's MOS states must be provided.
EXPLANATION:
If the core's test patterns contain MOS states, the chip must also be configured for MOS
states. The name of a description file containing the chip's MOS states must be provided
to migrate_core_tests.
USER RESPONSE:
Create a chip description file with the chip's MOS states and provide the name to the $
migrate_core_tests program using the chipdescfile=filename keyword.
INFO (THT-166): The time stamp for core experiment experiment_name is earlier than
the latest time stamp for committed migrated experiments. Therefore, this experiment will not
be processed.
EXPLANATION:
If the time stamp for a core experiment is earlier than the latest time stamp for committed
experiments, it will not be processed.
USER RESPONSE:

If not processing this experiment is correct, no action is necessary. Otherwise, a new

core experiment will have to be created and re-run through migrate_core_tests.
WARNING (THT-224): [Severe] Pin pin_name in the MOS_Pin_List statement of the chip
description file file_name was not found. The run terminates.
EXPLANATION:
The MOS_Pin_List statement contains chip pin names required to select core instances.
The pin called out in the message was not found on the chip.
USER RESPONSE:
Ensure the chip pin name in the chip description file is correctly spelled and exists on the
chip.
WARNING (THT-226): [Severe] The core name core_name in the MOS_Pin_States

statement of chip description file file_name was not found in the 'coreToChipMap' file.
EXPLANATION:
The coreToChipMap file contains correspondence for each active core. If a core name
in the chip description file is not found in the coreToChipMap file, the core cannot be
processed.
USER RESPONSE:
Ensure the core name used in the MOS_Pin_States statement of the chip description file
is correctly spelled and the core is an active core.
INFO (THT-430): Message number THT- message_number was printed

message_limit times out of a total of message_total.
EXPLANATION:
This message contains the number of times a message was printed out of a total number
USER RESPONSE:
ERROR (THT-506): [Internal] The Hierarchical Test Description API appears to be in an

infinite loop and will terminate memory allocations.
EXPLANATION:
USER RESPONSE:

Contact Customer Services.
THT-600 through THT-999

ERROR (THT-600): [Internal] The THT function, function_name, was called with node
node_id but this node does not yet have a value associated with it. Processing terminates.
EXPLANATION:
USER RESPONSE:
ERROR (THT-610): [Internal] The THT function, function_name, was called with
invalid node node_id.
EXPLANATION:
USER RESPONSE:
ERROR (THT-620): [Internal] The THT function, function_name, was called with
invalid node node_id.
EXPLANATION:
USER RESPONSE:
ERROR (THT-630): [Internal] The core block pin_name in the coreToChipMap file was
not found.
EXPLANATION:
USER RESPONSE:

ERROR (THT-632): [Internal] The core block index pin_index in the chip model was not
found.
EXPLANATION:
USER RESPONSE:
ERROR (THT-634): [Internal] The core pin pin_index in the coreToChipMap file was not
found.
EXPLANATION:
USER RESPONSE:
ERROR (THT-636): [Internal] The correspondence pin pin_name in the coreToChipMap

file was not found.
EXPLANATION:
USER RESPONSE:
Contact customer support (see Contacting Customer Service on page 23)
WARNING (THT-638): [Severe] Both the core pin pin corepinname and it's
correspondence pin pin corrpinname are designated as bidirectional pins. This
configuration is not supported at this time. The run terminates.
EXPLANATION:
to the core.
USER RESPONSE:
Ensure the core input pin is listed in the core to chip mapping



37
THM - Hierarchical Model Messages
THM-002 through THM-430 on page 1209

THM-002 through THM-430

WARNING (THM-002): Non-Memory Block cell-name passed to Memory method
method-name.
EXPLANATION:
Encounter Test has determined that the named cell is a RAM or ROM primitive, but there
are features about this primitive which Encounter Test does not expect. Therefore,
Encounter Test will not process this cell correctly.
USER RESPONSE:
Check for other messages that explain the full effect of this condition. Check the specified
cell to ensure that it matches the Encounter Test requirements for RAM or ROM cells. If
neither of the above checks resolves the problem, contact customer support (see
WARNING (THM-003): Non-Memory Pin pin-name passed to Memory method method-

name.
EXPLANATION:
Encounter Test has determined that the named pin is a pin on a RAM or ROM primitive,
but there are features about this pin which Encounter Test does not expect. Therefore,
Encounter Test will not process this pin correctly.
USER RESPONSE:

Check for other messages that explain the full effect of this condition. Check the specified
pin and block to ensure that it matches the Encounter Test requirements for RAM or ROM
cells. If neither of the above checks resolves the problem, contact customer support (see
WARNING (THM-004): Port number port on block-name is out of range 0..max-port-

number.
EXPLANATION:
The specified block is a RAM or ROM primitive which contains more ports than
Encounter Test allows.
USER RESPONSE:
Redesign the cell containing the RAM or ROM primitive so that no RAM or ROM primitive
has more ports than the maximum allowed by Encounter Test.
WARNING (THM-005): Address bit bit-number on block-name is out of range

0..maximum-address-bit.
EXPLANATION:
The specified block is a RAM or ROM primitive which contains more address bits than
Encounter Test allows.
USER RESPONSE:
Redesign the cell which contains the RAM or ROM primitive so that no one RAM or ROM
primitive contains more than the Encounter Test maximum number of address bits.
WARNING (THM-006): Data bit bit-number on block-name is out of range

0..maximum-data-bit.
EXPLANATION:
The specified block is a RAM or ROM primitive which is defined to have more data bits
than Encounter Test allows.
USER RESPONSE:
Redesign the cell which contains the specified RAM or ROM primitive so that no single
RAM or ROM primitive contains more data bits than the maximum allowed by Encounter
Test.
WARNING (THM-007): Pin name pin has unknown type.

EXPLANATION:

The specified block is a RAM or ROM primitive. Each pin connected to the RAM or ROM
primitive must be associated with a specific pin type in order for Encounter Test to
correctly model the RAM or ROM. The specified pin was not associated with a valid pin
type.
Note: The association of a pin type with a pin occurs during the Build Model process,
and is accomplished differently, depending on the model source input type. If the input
source is VIM, a PTYPE attribute is required. If the input source is not VIM, the pin name
is used to determine the pin type.
USER RESPONSE:
Correct the design source so that a valid pin type is associated with the specified pin.
WARNING (THM-010): Unable to open file Segment file-name - verify existence of file.
EXPLANATION:
Encounter Test attempted to open the specified file, but received a bad return code from
the operating system.
USER RESPONSE:
Check surrounding messages for more details. Check the specified file to make sure it
exists and contains valid data.
WARNING (THM-011): Error opening file file-name.

EXPLANATION:
Encounter Test attempted to open the specified file, but received a bad return code from
the operating system.
USER RESPONSE:
Check surrounding messages for more details. Check the specified file to make sure it
exists and contains valid data.
WARNING (THM-012): File file-name is not a compatible logic model file.

EXPLANATION:
Encounter Test attempted to read the specified file, assuming that the file was a
Encounter Test hierarchical model file. However, the data in the file does not conform to
the Encounter Test hierarchical model file format.
USER RESPONSE:

Check the surrounding messages for more details. Check the specified file to see if it has
been corrupted. If so, recreate the specified file.
WARNING (THM-013): Requested cell cell-name cannot be found.

EXPLANATION:
A Encounter Test application requested information about the specified cell, but the
specified cell did not appear in the Encounter Test hierarchical model.
USER RESPONSE:
Check the surrounding messages for details.
WARNING (THM-014): search-type(search-request) search failed for current-

index at depth search-depth.
EXPLANATION:
A Encounter Test application is attempting to find a hierarchical net, pin, or block from a
net, pin, or block index. The search failed.
USER RESPONSE:
WARNING (THM-015): Error opening file fileName. Password authorization failed.

EXPLANATION:
Encounter Test attempted to open the password protected hierModel file, but
authorization failed.
USER RESPONSE:
WARNING (THM-020): [Severe] file-name activeNodeMap file is missing.

EXPLANATION:
Encounter Test creates an activeNodeMap file when a test mode is defined. The
activeNodeMap file defines which pins and nets are active in the mode. An application
attempted to open the activeNodeMap file, but the expected file does not exist. In this
case, the application will treat every pin and net as active.
USER RESPONSE:
Recreate the activeNodeMap file by rerunning Test Mode Define.

WARNING (THM-021): [Severe] Cant access activeNodeMap data from file file-name
- all logic identified as active.
EXPLANATION:
Encounter Test creates an activeNodeMap file when a test mode is defined. The
activeNodeMap file defines which pins and nets are active in the mode. An application
attempted to read the activeNodeMap file, but the expected file does is empty. In this
case, the application will treat every pin and net as active.
USER RESPONSE:
Recreate the activeNodeMap file by rerunning Test Mode Define.
ERROR (THM-201): Unable to open the hierarchical model.

EXPLANATION:
The hierarchical model for the specified WORKDIR cannot be read.
USER RESPONSE:
Check the value of WORKDIR. If they are correct, check that the hierModel and
hierAttributes file exist in the working directory, and can be read. If not, rebuild the model.
ERROR (THM-203): Unable to open the transistor model.

EXPLANATION:
The transistor model for the specified WORKDIR cannot be read.
USER RESPONSE:
Check the values of WORKDIR. If they are correct, check that the transModel and
transAttributes file exist in the working directory, and can be read. If not, rebuild them
model.
INFO (THM-204): Propagated instance instance_attr_name attributes.

EXPLANATION:
THMpropagate found cell level attributes, and propagated the specified number of those
attribute values to instances of those cells.
USER RESPONSE:
No response required, informational message only.
ERROR (THM-400): [Internal] THMbitPosition method invoked on pin-name which is

neither an address nor data pin.

EXPLANATION:
Program Error.. this method should not have been called.
USER RESPONSE:
ERROR (THM-401): [Internal] Multiple LoadBlockFromName invocations between

TermModlIntf.
EXPLANATION:
Program error.. routine invoked incorrectly.
USER RESPONSE:
ERROR (THM-402): [Internal] count Model Interface objects were not freed.
EXPLANATION:
Program error. Logic model objects were obtained, but not freed. Processing continues
and is correct, but memory usage may be higher than necessary.
USER RESPONSE:
WARNING (THM-403): Model predates timestamp support (modelTime of 0 generated) -

Model should be rebuilt.
EXPLANATION:
The Encounter Test hierarchical model is very old.
USER RESPONSE:
It is strongly recommended that the hierarchical model be rebuilt.
INFO (THM-404): Hierarchical model edit storage collection started. Model size: size
bytes.
EXPLANATION:
Hierarchical model build is collecting storage that is no longer needed.
USER RESPONSE:

INFO (THM-405): Hierarchical model edit storage collection completed. Model size: size
bytes.
EXPLANATION:
Hierarchical model build is finished collecting storage that is no longer needed.
USER RESPONSE:
INFO (THM-406): Hierarchical model access test program starting.

EXPLANATION:
Hierarchical model access test program has started.
USER RESPONSE:
INFO (THM-407): Hierarchical model access test program completed.

EXPLANATION:
Hierarchical model access program has completed.
USER RESPONSE:
WARNING (THM-411): error_string

EXPLANATION:
An error was found during semantic checking of the edits just made.
USER RESPONSE:
Correct the error by re-editing the design or undo the edit.
WARNING (THM-412): Hierarchical model edit not applied, reason: reason

EXPLANATION:
The requested hierarchical model edit was not applied for the reason specified.
USER RESPONSE:
Verify whether or not the resulting hierModel is correct. If necessary, rebuild the model,
or correct the batch edit file and reapply the edits.

WARNING (THM-413): error_string

EXPLANATION:
An error was found during semantic checking of the edits just made.
USER RESPONSE:
If the action taken by the model edit program is correct, no action is necessary.
Otherwise, edit the design to correct the action taken by model edit.
WARNING (THM-414): object1 name name representing index index1 is ambiguous.

object2 index index2 also has this name. Index index will be returned when requested
by name.
EXPLANATION:
The specified name represents more than one object of the same type (block, pin or net)
in the Encounter Test hierModel. Since periods (.) may represent levels of Encounter Test
hierarchy and may also be part of an instance, cell, pin or net name, it is possible that the
same name may represent more than one object. Eg, pin name A.B.C may represent pin
C on instance A.B, or it may represent pin B.C on instance A.
USER RESPONSE:
It is highly recommended that the names be changed to make them unambiguous and
rebuild the model, or the wrong pin, block or net may be used by Encounter Test
applications.
WARNING (THM-415): Invalid constraint block name constraint block name

encountered while attempting to remove constraint from cell cell name.
EXPLANATION:
The constraint block name specified on the Remove Constraint statement in the Model
Edit file or in the GUI could not be found in the model.
USER RESPONSE:
Correct the constraint block name and run Model Edit again.
WARNING (THM-416): Invalid short block name short block name encountered while
attempting to remove constraint instance constraint instance name.
EXPLANATION:
The short block name (portion of the full constraint block name) specified on the Remove
Constraint statement in the Model Edit file or in the GUI could not be found in the model.

USER RESPONSE:
WARNING (THM-417): Invalid short block name short block name encountered while
attempting to remove constraint constraint instance name from cell cell name.
EXPLANATION:
The short block name (portion of the full constraint block name) specified on the Remove
Constraint statement in the Model Edit file or in the GUI could not be found in the model.
USER RESPONSE:
WARNING (THM-418): Invalid constraint block|edit cell name block

name|cell name specified on Remove Constraint statement in Model Edit file.
EXPLANATION:
The block name specified on a Remove Constraint statement in the Model Edit file does
not exist in the model.
USER RESPONSE:
WARNING (THM-419): Errors encountered while attempting to remove a constraint. See

previous messages. The constraint was not removed.
EXPLANATION:
Errors occurred while processing Remove Constraint statement(s) in the Model Edit file
or in the GUI. Previous messages should indicate the specifics of the problem. The
constraint was not removed.
USER RESPONSE:
Correct the problems identified in the previous messages and run Model Edit again.
INFO (THM-430): Time sensitive encrypted cloak PASSWORD = password. It will expire in
number days.
EXPLANATION:
The time sensitive encrypted cloak password is being provided by program
prepare_cloak_password.

This is to be used as the value when exporting environment variable

TBCLOAKPW_cellname to uncloak the cell, where cellname is the name of the cell
that has the original password (attribute TB_cloak_password) for which this time
sensitive encrypted password is being generated. The password passed in to
prepare_cloak_password must be the value of the TB_cloak_password attribute
for the cell.
This password will be valid for the number of days shown in the message. It will expire
at midnight Greenwich Mean Time (GMT) "number" days from the beginning of the
current day.
USER RESPONSE:

WARNING (THM-431): Unable to fileAction fileName
Reason: systemExplanation
Macro List file not created.
EXPLANATION:
The macroList file was not created due to the referenced reason. The macroList file
contains a list of all macro blocks in block instance name format. This file is read by the
GUI to fill in the Macros to Include Macros to Exclude list for Verify Core Isolation.
USER RESPONSE:
Correct the identified problem and rebuild the model to enable Verify Core Isolation to
more effectively run.
WARNING (THM-500): Error in Backtracing for boundary Scan External: block blockid
RAM or ROM found!
EXPLANATION:
A RAM or ROM was found in tracing back from a primary output to find its associated
boundary scan latch. This deviates from boundary scan design guidelines and will
degrade testability for this test mode as well as interconnect test generation on the higher
level package.
USER RESPONSE:

Ensure the external boundary scan chain test configuration controls are specified, using
TI test function pin attributes, to direct the primary output backtrace to its associated
boundary scan latch rather than into the system logic.
WARNING (THM-501): Non-boundary scan latch latch-name was found in forward

tracing from PI PI-pin-name. object is not included in the boundary model.
EXPLANATION:
This primary input forward trace found system logic which was not scannable in the
boundary scan external mode. The identified non-boundary scan latch will be replaced
by a source of x for test generation and fault simulation, and will degrade testability for
this test mode as well as interconnect test generation on the higher level package.
USER RESPONSE:
Ensure the external boundary scan chain test configuration controls are specified, by the
TI test function pin attribute, to direct the primary input forward trace to its associated
boundary scan latch.
WARNING (THM-502): Latch blockid2, which is non-scanable in the boundary scan external
test mode, gates the system clock path to boundary scan receiver latch blockid1. This
condition will cause faults into this receiver latch to be untestable in this test mode.
EXPLANATION:
The identified receiver latch was associated with a primary input, but backtracing from its
clock input to include all the logic necessary to ensure controllability from the primary
input to this latch found a non-boundary scan latch. This non-boundary scan latch will be
replaced
this test mode as well as the ability to do a complete interconnect test on the higher level
package.
USER RESPONSE:
Ensure that the external boundary scan chain test configuration controls are specified,
by the TI test function pin attribute, to direct the primary input forward trace to its
associated boundary scan latch. Further, ensure that clock paths to this boundary scan
latch are not gated by any latch that is non-scannable in this test mode.
WARNING (THM-503): Non-boundary scan latch blockid was found in backtracing from
Primary Output pinid. blockid is not included in the boundary model.
EXPLANATION:

This primary output backtrace found system logic which was not scannable in the
USER RESPONSE:
Ensure the external boundary scan chain test configuration controls (TI test function pin
attribute) are specified to direct the primary output backtrace to its associated boundary
scan latch.
WARNING (THM-504): No boundary scan latches were found forward tracing from PI
pinid.
EXPLANATION:
A boundary scan latch is defined as one which is scannable in the boundary scan
external test mode. No scannable latch was found in tracing forward from this primary
input. This will degrade testability for this test mode as well as interconnect test
generation on the higher level package.
USER RESPONSE:
attribute) are specified to direct the primary input forward trace to its associated
WARNING (THM-505): No boundary scan latches or PIs were found back tracing from PO
PO name.
EXPLANATION:
external test mode. No scannable latch was found in tracing backward from this primary
output. This will degrade testability for this test mode as well as interconnect test
USER RESPONSE:
attribute) are specified to direct the primary output backward trace to its associated
WARNING (THM-506): Primary Input Pin pinid is unused.

EXPLANATION:
No net is connected to this primary input pin.

USER RESPONSE:
Verify that the logic is correct.
WARNING (THM-507): Latch latch_Name is not at 1/0 thus not considered a bscan
latch.
EXPLANATION:
The referenced latch was not assigned a value from the simulation and therefore is not
considered to be a a boundary latch.
USER RESPONSE:
No response required, unless the latch is expected to be a boundary latch. In that case,
analyze the design to determine and resolve why it the latch does not function like a
boundary latch and rerun if necessary.
INFO (THM-508): Primary Input Pin pinid connects to n boundary scan latches.
EXPLANATION:
This message tells how many boundary scan external scannable latches were traced
forward to from the indicated PI.
USER RESPONSE:
To minimize the amount of boundary scan external logic any system latches found in this
PI forward trace should be placed in scan paths that are not active in the boundary scan
external mode. This will prevent their inclusion in the external logic.
INFO (THM-509): Forward trace on PI PI_Name included number boundary scan latches.
These latches did not meet the 0/1 criteria for boundary scan latches.
EXPLANATION:
The specified number of latches were topologically connected to the referenced PI, but
the simulation did not apply 0/1 to these latches, therefore they are not considered
boundary latches.
USER RESPONSE:
If this condition is unexpected, analyze the individual latches listed in other THM
messages to determine why the 0/1 values are blocked and rerun ff necessary.
WARNING (THM-510): Forward trace on PI pinid included n boundary scan latches. This
PI was not picked up in the backtrace on the latches.
EXPLANATION:

The number of boundary scan external scannable latches that were found in tracing
forward from this PI is displayed. In backtracing from these latches, with TI values
enforced, this same PI was not found.
USER RESPONSE:
Make certain that there is no primary input with the TI attribute that is blocking the path
from this primary input to its associated boundary scan latch.
WARNING (THM-511): PO, po name, backtraced into Latch Block blockid. This latch
was used as a boundary scan latch for PO po name.
EXPLANATION:
The indicated latch is used as a boundary scan latch to the data input of a three-state
driver that feeds more than one primary output. It will not be possible to independently
control these primary output nets, thus limiting the ability to perform a complete
interconnect test on the next higher level package.
USER RESPONSE:
Make certain that this multiple usage of the same boundary scan data latch is as
intended, and that there is not a design error.
INFO (THM-512): PO, po name, backtraced into Latch Block blockid. This latch was
used as a boundary scan latch for PO po name.
EXPLANATION:
The indicated latch is used as a boundary scan latch to the enable input of a three-state
driver that feeds more than one primary output.
USER RESPONSE:
Make certain that this multiple usage of the same boundary scan enable latch is as
WARNING (THM-513): RAM/ROM block blockid2 gates the system clock path to
boundary scan receiver latch blockid1. This condition will cause faults into this receiver
latch to be untestable in this test mode.
EXPLANATION:
The identified receiver latch was associated with a primary input, but backtracing from it
to include all the logic necessary to ensure controllability from the primary input to this
latch found a RAM or ROM block. This block will be replaced by a source of x for test
generation and fault simulation, and will degrade testability for this test mode as well as
the ability to do a complete interconnect test on the higher level package.

USER RESPONSE:
latch are not gated by any RAM or ROM.
WARNING (THM-514): RAM or ROM block blockid1 was found in backtracing from
Primary Output blockid2. blockid1 is not included in the boundary model.
EXPLANATION:
boundary scan external mode. The identified RAM/ROM block will be replaced by a
source of x for test generation and fault simulation, and will degrade testability for this test
mode as well as the ability to do a complete interconnect test on the higher level
package.
USER RESPONSE:
scan latch.
WARNING (THM-515): Latch blockid1, which is non-scanable in the boundary scan

external test mode, gates the data path to boundary scan receiver latch blockid2. This
EXPLANATION:
data input to include all the logic necessary to ensure controllability from the primary
replaced by a source of x for test generation and fault simulation, and will degrade
testability for this test mode as well as the ability to do a complete interconnect test on
the higher level package.
USER RESPONSE:
associated boundary scan latch. Further, ensure that data paths to this boundary scan
WARNING (THM-516): RAM/ROM block blockid1 gates the data path to boundary scan
receiver latch blockid2. This condition will cause faults into this receiver latch to be
untestable in this test mode.

EXPLANATION:
input to this latch found a RAM or ROM block. This block will be replaced by a source of
x for test generation and fault simulation, and will degrade testability for this test mode as
well as the ability to perform a complete interconnect test on the higher level package.
USER RESPONSE:
boundary scan latch. Further, ensure that data paths to this boundary scan latch are not
gated by any RAM or ROM.
WARNING (THM-517): PO pinid data path has n boundary scan latches and m non-
boundary scan latches.
EXPLANATION:
The backtrace along the data path of the TSD associated with this primary output
encountered more latches than just a single scannable boundary scan latch. This is a
deviation from rigorous boundary scan design practices which can have adverse test
generation consequences. If non-boundary scan latches are encountered then test
generation done using this mode will be degraded since non-boundary scan latches are
by definition non-scannable. If more than one boundary scan latch is encountered there
may be adverse impacts on test generation time and test data volume, although
coverage likely will not suffer.
USER RESPONSE:
Modify your boundary scan design so that only one boundary scan latch and no non-
boundary scan latch is associated with this primary outputs data backtrace.
WARNING (THM-518): PO pinid enable path has n boundary scan latches and m non-
EXPLANATION:
The backtrace along the enable path of the TSD associated with this primary output

USER RESPONSE:
boundary scan latch is associated with this primary outputs enable backtrace.
WARNING (THM-520): Error reading data from file file_name, data is string
EXPLANATION:
Ths program was unable to read the data in the referenced file.
USER RESPONSE:
Modify the data in the file to be readable and rerun.
WARNING (THM-521): Error reading data from file file_name. String string is not a
valid object name
EXPLANATION:
Ths identified string in the message is assumed to be a valid object name.
USER RESPONSE:
Correct the object name in the file and rerun.
WARNING (THM-522): Latch latch_Name from the latch file is not scannable. The
backtrace will be attempted.
EXPLANATION:
The referenced latch is not scannable.
USER RESPONSE:
Analyze and correct the cause(s) for the following conditions and rerun:
The reason the latch is not scannable
The reason the latch is selected for backtrace
WARNING (THM-523): There are blocks active in this test mode that have the CLOAK
attribute.
EXPLANATION:
The program has detected active blocks that are cloaked, therefore their content cannot
be displayed.
USER RESPONSE:

WARNING (THM-524): Block block_Name is contained in block block_Name, cell name

cell_Name. Block block_Name has a CLOAK attribute.
EXPLANATION:
The referenced block is cloaked and therefore its content cannot be displayed.
USER RESPONSE:

INFO (THM-806): Starting to build NodeIsActive data.
EXPLANATION:
The program has begun the active node building process.
USER RESPONSE:
INFO (THM-813): Finished building NodeIsActive data.

EXPLANATION:
The program has completed the active node building process.
USER RESPONSE:
INFO (THM-814): Testmode contains percent active% active logic, percent

inactive (non-constraint)% inactive logic and percent contraints%
constraint logic.
EXPLANATION:
This message identifies the percent of active logic in the Encounter Test Model for the
current test mode. Logic is active if it appears that it may be observable (might affect the
value seen at a measurable point) in the current test mode.
Constraint logic, logic added by Encounter Test during model import when
CONSTRAINT properties are present, is "virtual" logic that can never be observed. The
inactive logic is "real" (non-constraint) logic that cannot be observed, because the logic

feeds only "blackbox" or dangling logic, is blocked from observability by test mode
constrained signals (test-inhibited or test-constrained primary inputs or latches), the logic
feeds only to non-tester-contacted pins or a combination of these reasons. These three
percentages should always add up to 100%.
USER RESPONSE:
INFO (THM-815): count out of total nets active for percent active%, percent
inactive% inactive. Constraints comprise percent constraints% of the total
number of nets.
EXPLANATION:
This message identifies the number of active nets in the Logic Model. A net is active if
(and only if) it can affect a measure in the current test mode. The non-active logic can be
caused by constraints or by "real" logic that, for some reason, cant be observed. The
percentage of the total number of nets that were created as a result of processing
constraints is provided.
USER RESPONSE:
ERROR (THM-817): [Internal] Block Tally count

EXPLANATION:
This message gives the count of the number of blocks that were obtained by the
application, but were not released when the application closed the Logic Model.
USER RESPONSE:
ERROR (THM-818): [Internal] Pin Tally count

EXPLANATION:
This message gives the count of the number of pins that were obtained by the
USER RESPONSE:
ERROR (THM-819): [Internal] Net Tally count

EXPLANATION:
This message gives the count of the number of nets that were obtained by the
USER RESPONSE:
ERROR (THM-820): [Internal] Name Tally count

EXPLANATION:
This message gives the count of the number of names that were obtained by the
USER RESPONSE:
ERROR (THM-821): [Internal] Attr Tally count

EXPLANATION:
This message gives the count of the number of attributes that were obtained by the
USER RESPONSE:
ERROR (THM-822): [Internal] PlcMk Tally count

EXPLANATION:
This message gives the count of the number of place-markers that were obtained by the
USER RESPONSE:
INFO (THM-830): Processing Primary Output Pin: pinid Test Function Flags: test
function attributes
EXPLANATION:
A backtrace is being conducted from this primary output, which has the stated test
function attribute, if any. The messages which follow this one will tell what boundary scan
latches are associated with this primary output.

USER RESPONSE:
INFO (THM-831): backtrace on Enable Pin of blockid

EXPLANATION:
The preceding THM-830 message identified the primary output that was being
backtraced. This backtrace has gone through the enable pin of the indicated three-state
driver and has found the listed latches along that path.
USER RESPONSE:
INFO (THM-832): backtrace on Data Pin of blockid

EXPLANATION:
The preceding THM-830 message identified the primary output that was being
backtraced. This backtrace has gone through the data pin of the indicated three-state
driver and has found the listed latches along that path.
USER RESPONSE:
INFO (THM-833): Processing ScanOut Primary Output: pinid

EXPLANATION:
The backtrace from this scan out pin found the indicated numbers of pins, nets and
USER RESPONSE:
If these numbers are not as expected then change the logic and/or boundary scan
configuration controls (TI test function pin attribute) so that the correct logic is associated
with this scan-out PO.
INFO (THM-834): Processing Latch: blockid Logic added: # pins = m, # nets = nets
EXPLANATION:
The identified latch is the first one found in backtracing from the scan-out primary output
identified in the previous THM-833 message. The indicated number of pins and number
of nets were found in backtracing from this latch along the scan path to the scan-in pin.
USER RESPONSE:

Verify that this is the last latch in the external boundary scan scan path and that the pin
and net counts are as expected. If not then change the logic and/or boundary scan
configuration controls (TI test function pin attribute) so that the correct logic is found for
the scan path.
INFO (THM-836): Logic added: # pins = m, # nets = n, # scan Latches = p

EXPLANATION:
The backtrace from this primary output pin found the specified numbers of pins, nets and
boundary scan latches. The number of pins and number of nets are expressed as deltas
over those already found in previous primary output backtraces.
USER RESPONSE:
If the numbers of pins, nets or latches associated with this primary output backtrace are
excessive then a problem with the boundary scan structure is indicated. Change the logic
and/or boundary scan configuration controls (TI test function pin attribute) so that the
correct boundary scan logic is found for this primary output.
INFO (THM-837): Processing Primary Input Pin: pinid Test Function Flags: test
function attributes
EXPLANATION:
A forward trace is being conducted from this primary input, which has the stated test
function attribute, if any. The messages which follow this one will tell what boundary scan
latches are associated with this primary input.
USER RESPONSE:
INFO (THM-838): Associated Latch: blockid Logic added: # pins = m, # nets = n

EXPLANATION:
The forward trace from this primary input pin found the specified numbers of pins and
nets before finding the indicated boundary scan latch. The number of pins and number
of nets are expressed as deltas over those already found in previous primary input
traces.
USER RESPONSE:
If the number of pins or number of nets associated with this primary input forward trace
is excessive then a problem with the boundary scan structure is indicated. Change the
logic and/or boundary scan configuration controls (TI test function pin attribute) so that
the correct boundary scan logic is found for this primary input.

INFO (THM-840): There were number message number messages for this PO or PI.
EXPLANATION:
This message will give a count of the number of times the program encountered the
condition reported for the referenced message number when processing the primary
input or primary output (see the previous THM-830, THM-833 or THM-837). The printed
message for the referenced message number is limited by the build_testmode
printlimit command line option. Refer to "build_testmode for more information. The
printlimit option defaults to one. When it is not overridden, messages are printed only
once per primary input or primary output and then this THM-840 summary message is
issued. Refer to "build_testmode in the Encounter Test: Reference: Commands for
detail.
USER RESPONSE:
INFO (THM-841): backtrace on block, pin or net name

EXPLANATION:
This message will give the name of a block, pin, or net that will be backtraced and
included in the activeNodeMap. This block, pin, or net was specified in the ponets file
during invocation of build_testmode.
USER RESPONSE:
INFO (THM-842): Logic added: # pins = number, # nets = number

EXPLANATION:
This message will specify the number of pins and nets that will be added to the
activeNodeMap. A previous message names the primary input or primary output that
was traced out to find this logic.
USER RESPONSE:
INFO (THM-843): Processing Netlist file file_Name.

EXPLANATION:
Processing of the referenced netlist file has begun.
USER RESPONSE:

INFO (THM-844): Error opening Netlist file file_Name.

EXPLANATION:
The program encountered an error when attempting to open the referenced netlist file.
USER RESPONSE:
INFO (THM-845): No boundary scan latches were found forward tracing from PI
PI_pin_Name. This PI does not feed any internal logic.
EXPLANATION:
The program notes that the indicated Primary Input does not feed boundary scan
latches, and therefore does not feed any boundary scan internal logic.
USER RESPONSE:
INFO (THM-846): Processing Chopper: chopper_Name

Logic added: # pins = number_of_pins, # nets = number_of_nets.
EXPLANATION:
The program has begun to process the referenced clock chopper.
USER RESPONSE:
INFO (THM-847): Build NodeIsActive Summary of WARNING and ERROR messages:

EXPLANATION:
This message prints a summary of the error and warning messages issued for this
process.
USER RESPONSE:
WARNING (THM-850): Unknown Command/Object commandOrObject on line number

lineNumber of partition file partitionFile.
EXPLANATION:

The specified command or object was unknown to the partition file parser. All commands
must be uppercase (e.g. INCLUDE, STOP, BACKTRACE). If its a block, pin or net object,
then the object prefix was unknown (e.g. Block.f.l). The unknown command or object is
causes partition file processing to immediately terminate.
USER RESPONSE:
Correct the above named partition file to use valid command and object names.
WARNING (THM-851): The End of Partition File partitionFile was reached with an
unclosed block comment ("/*" with no ending "*/"). The block comment was opened on line
number commentStart.
EXPLANATION:
A Block Comment was opened but was never closed before the end of file. All commands
from the beginning of the opening of the comment to the end of file are treated as
comment text and are ignored.
USER RESPONSE:
Add the required "*/" where the block comment was intended to end.
WARNING (THM-852): Invalid object commandOrObject used on an INCLUDE or

REMOVE command on line number lineNumber of partition file partitionFile.
EXPLANATION:
The specified object was invalid on the given command. The INCLUDE and REMOVE
commands do not support the Pin.f.l or Net.f.l object types. The invalid object is causes
partition file processing to immediately terminate.
USER RESPONSE:
Correct the above named partition file to use valid command and object names.
INFO (THM-853): Unable to uncompress file fileName.

EXPLANATION:
USER RESPONSE:

INFO (THM-854): Unable to compress file fileName.

EXPLANATION:
the specified file.
USER RESPONSE:
page 23).
ERROR (THM-999): An unexpected condition occurred in the Encounter Test model code.
information: An error occurred on line line_number of source file file_name:
variable_text
EXPLANATION:
USER RESPONSE:

38
TID - Electronic Chip ID Test Generation
Messages
TID-001 through TID-300 on page 1235
TID-001 through TID-300

INFO (TID-001): Initializing ECID Test Sequence Generation.
EXPLANATION:
Indicates invocation of ECID Test Sequence Generation Utility.
USER RESPONSE:
For informational use only. To eliminate this message, invoke ECID utility with the -q
(quiet mode) option.
INFO (TID-002): ECID Test Sequence Generation Initialization successfully completed.

EXPLANATION:
Indicates successful initialization of ECID Test Sequence Generation Utility.
USER RESPONSE:
INFO (TID-010): ECID Test Sequence Generation has identified numFuses fuses.
EXPLANATION:
Displays the number of fuses identified via the ECID_BIT attribute.
USER RESPONSE:

TID - Electronic Chip ID Test Generation Messages
INFO (TID-020): ECID Fuse to Latch Correlation Successfully Completed.

EXPLANATION:
Indicates invocation of ECID Test Sequence Generation Utility.
USER RESPONSE:
INFO (TID-030): A valid ECID Test Sequence has previously been generated. No attempt
will be made to recreate the test sequence.
EXPLANATION:
An ECID test sequence has been previously generated for this test mode.
USER RESPONSE:
(quiet mode) option. To force regeneration of the test section, the existing experiment
must be removed.
INFO (TID-050): ECID Test Sequence Generation successfully completed.

EXPLANATION:
Indicates that an ECID test sequence was successfully derived.
USER RESPONSE:
INFO (TID-060): ECID Path Sensitization successfully completed.

EXPLANATION:
Indicates that all paths between ECID fuses and correlating latches have been sensitized
simultaneously.
USER RESPONSE:

INFO (TID-099): ECID Test Sequence Generation ended.

EXPLANATION:
Indicates completion of ECID Utility.
USER RESPONSE:
WARNING (TID-100): ECID Test Sequence Generation unable to initialize.

EXPLANATION:
ECID Test Sequence Generation received a bad return code from one of the utility
programs. This is most likely due to a programming error.
USER RESPONSE:
WARNING (TID-101): Error initializing model for ECID Test Sequence Generation.
EXPLANATION:
The ECID Test Sequence Generation utility received a bad return code during its
initialization phase from a model access subroutine. This is probably due to a program
error.
USER RESPONSE:
WARNING (TID-102): Error initializing the pattern generator for ECID Test Sequence
Generation.
EXPLANATION:
initialization phase from a pattern generation initialization subroutine. This is probably
due to a program error.
USER RESPONSE:
WARNING (TID-103): Error initializing test data access methods for ECID Test Sequence
Generation.

EXPLANATION:
initialization phase from a test data access subroutine.
This is probably due to a program error.
USER RESPONSE:
WARNING (TID-104): ECID Test Sequence Generation unable to sensitize all fuse/latch
paths simultaneously.
EXPLANATION:
In order to generate the ECID test sequence which will scan out the ECID fuse
information, all fuse to latch paths must be sensitized simultaneously. This error is most
likely caused by conflicting requirements to propagate all of the fuse values to their
corresponding latches simultaneously.
USER RESPONSE:
Examine the model source to identify the source of conflict. When determined, modify
the model source to allow for simultaneous propagation of fuse values, import the new
source and rerun the ECID utility.
WARNING (TID-200): [Severe] ECID Test Sequence Generation unable to identify fuses.
EXPLANATION:
The ECID Test Sequence Generation utility was unable to locate fuses from the model
source, thereby preventing fuse/latch correlation and subsequent test sequence
generation.
USER RESPONSE:
Ensure that the model source is correct. Fuses must be identified in the model by the
attribute TB_ECID_BIT. If fuses are present but not attributed, modify the model source
and import the design again. If there are no fuses associated with this design, then the
ECID utility should not be invoked.
WARNING (TID-201): [Severe] ECID Test Sequence Generation unable to correlate fuse
fuseID to a scan latch.
EXPLANATION:

The ECID Test Sequence Generation utility attempts to correlate all fuse sources to
corresponding scan latches. For the fuse source specified, no corresponding scan latch
was identified.
USER RESPONSE:
Examine the model source and verify that the specified fuse source feeds at least one
scan latch. If not, modify the model source to correct the problem, import the new model
and rerun the ECID Utility.
WARNING (TID-202): [Severe] ECID fuse fuseID and fuse fuseID both correlate to
observable latch latchnode.
EXPLANATION:
The ECID Test Sequence Generation utility attempt to correlate all fuse sources to
appropriate observable latches failed because two fuses correlated to the same
observable latch. It is required that each fuse correlate to a unique observable latch.
USER RESPONSE:
Examine the model source and verify that ECID requirements are satisfied. If not, modify
the model source to correct the problem, import the new model and rerun ECID Test
Sequence Generation.
WARNING (TID-203): [Severe] ECID fuse fuseID and fuse fuseID do not correlate to
the same observable scan chain.
EXPLANATION:
appropriate observable latches failed because two fuses identified did not correlated to
observable latches within the same scan chain. It is required that each fuse correlate to
the same observable scan chain.
USER RESPONSE:
ascending contiguous positions within the same observable scan chain.
EXPLANATION:
appropriate observable latches failed because two fuses identified did not correlated to

ascending contiguous positions within the same observable scan chain. It is required that
each fuse correlate to contiguous positions within the same observable scan chain in
ascending order as defined by the ECID_BIT attribute.
USER RESPONSE:
the same type of observable laches within the observable scan chain.
EXPLANATION:
appropriate observable latches failed because the two fuses identified did not correlated
to the same type of measure latches within the same observable scan chain.
USER RESPONSE:
WARNING (TID-220): [Severe] ECID Fuse to Latch Correlation was unsuccessful.

EXPLANATION:
Severe error(s) occurred during ECID Fuse to Latch Correlation.
USER RESPONSE:
Refer to previously issued messages to determine cause of failure. To eliminate this
message, invoke ECID utility with the -q (quiet mode) option.
WARNING (TID-250): [Severe] ECID Test Sequence Generation was unsuccessful.

EXPLANATION:
Severe error(s) occurred during ECID Test Sequence Generation.
USER RESPONSE:
Refer to previously issued messages to determine cause of failure. To eliminate this
message, invoke ECID utility with the -q (quiet mode) option.
WARNING (TID-251): [Severe] ECID unable to generate test sequence due to violation of
fuse/latch correlation.

EXPLANATION:
The ECID Test Sequence Generation utility was unable to generate a test sequence
which would capture the fuse source data in the appropriate scan chain for observation.
USER RESPONSE:
Examine the error messages issued during the fuse/latch correlation phase and take
appropriate action to resolve those conditions. If no error messages were issued then a
programming error has occurred and customer support (see Contacting Customer
Service on page 23) should be contacted.
WARNING (TID-300): [Severe] ECID Fuse fuseName does not correlate to required
observable latch latchName.
EXPLANATION:
ECID rules require that all ECID fuses correlate to observable latches which are within
the same scan chain. Furthermore, the latches must be contiguous within the scan chain
and the fuses must correlate such that they will be scanned out in ascending order as
defined by the value of the TB_ECID_BIT attribute. ECID test sequence generation has
determined that, for the given correlation attempt, the specified fuse does not correlate
to the required latch to satisfy these conditions.
USER RESPONSE:
Examine the model source to determine whether this specified fuse does not feed the
correct measure latch. If not, modify the source and re-import the model.


39
TIE - Import EVCD Messages
TIE-001 through TIE-999 on page 1243
TIE-001 through TIE-999

ERROR (TIE-001): Error: importfile filename could not be opened.
EXPLANATION:
The specified importfile could not be opened and caused the process to terminate.
USER RESPONSE:
Ensure that the importfile file name was correctly specified correctly. If it was spelled
correctly, check that the file exists and that read access permission to the file exists.
Correct any misspellings or file permissions and rerun.
ERROR (TIE-002): Error - cannot lock object object.

EXPLANATION:
The indicated object could not be locked and caused the process to terminate. This
object is an experiment, testmode, or model.
USER RESPONSE:
Verify the indicated object exists and is registered correctly in the globalData file. Also
verify the object is correctly spelled. If needed, create the object or correct any
misspellings, and rerun.
ERROR (TIE-003): Failed while trying to register the experimental TBDbin file on the
globalData file.
EXPLANATION:
The attempt to register the output experimental TBDbin file on the globalData file failed
and caused abnormal termination.

A preceding error message describes the error condition.

USER RESPONSE:
ERROR (TIE-004): Failure attempting dependency creation: experiment -> testmode.

EXPLANATION:
This experiment is dependent on the test mode. The program attempted to register this
dependency in the globalData file, but failed, causing the process to terminate. A
preceding message from the globalData file utility describes the error condition.
USER RESPONSE:
ERROR (TIE-005): The testMode test mode is not registered on the globalData file.
EXPLANATION:
When a test mode is created successfully by Build Test Mode, it is registered on the
globalData file. The program detected that the testmode was not registered, causing the
process to terminate.
USER RESPONSE:
Verify the TESTMODE environment variable or input parameter was specified correctly.
Verify whether Build Test Mode successfully completed. Rerun Build Test Mode if
needed, then rerun Read Vectors and correctly specify TESTMODE.
ERROR (TIE-006): Error received from utility or method.

EXPLANATION:
The indicated utility or method failed and caused the process to terminate. A preceding
message describes the error condition.
USER RESPONSE:
ERROR (TIE-007): NULL pointer returned from TBDinit.

EXPLANATION:
Initialization of the TBD data repository failed and caused the process to terminate. A
preceding message describes the error condition.

USER RESPONSE:
ERROR (TIE-008): fileName not a file.

EXPLANATION:
The specified file name for importfile is not a file and caused the process to terminate.
USER RESPONSE:
Verify an existing file has been specified. Correct any errors and rerun.
ERROR (TIE-009): No inputfile was specified.

EXPLANATION:
An input source was not specified and caused the process to terminate. An input source
file is a required input.
USER RESPONSE:
Rerun specifying the pattern source.
ERROR (TIE-010): Unsupported logic value logicValue occurred in: fileName line:
lineNum.
EXPLANATION:
This is a program error.
USER RESPONSE:
ERROR (TIE-011): TIEimport failed attempting to add an objectType to the test vectors.
EXPLANATION:
The EVCD import process failed while attempting to add the specified test vectors object
and caused the process to terminate.
USER RESPONSE:
ERROR (TIE-012): Space allocation failed. The import program can not allocate space for
name table.
EXPLANATION:

Sufficient space was not available to build the tables required by The EVCD import
process.
USER RESPONSE:
ERROR (TIE-400): fileName

EXPLANATION:
The Input EVCD file contained a syntax error and caused the process to terminate.
USER RESPONSE:
View the indicated line in the EVCD file, correct the error, and rerun.
ERROR (TIE-401): A scope type of scopeType was specified in the input EVCD. This is an
unsupported scope.
EXPLANATION:
The input EVCD file contained an unsupported scope type and caused the process to
terminate. module is the only supported scope type
USER RESPONSE:
The only supported scope in EVCD is module. Create a legal EVCD file and retry.
ERROR (TIE-402): A variable type of variableType was specified in the input EVCD.
This is an unsupported variable.
EXPLANATION:
The input EVCD file contained an unsupported variable type. and caused the process to
terminate. port is the only supported variable type
USER RESPONSE:
The only supported variable type in EVCD is port. Create a legal EVCD file.
WARNING (TIE-403): A port value of value was specified in the input EVCD. This is an
unsupported value.
EXPLANATION:
The input EVCD file contained an unsupported port value in the variable section however
processing continues. This port will be set to x.
USER RESPONSE:

Determine why there is a unsupported value within the EVCD. Correct the problem and
rerun EVCD import.
ERROR (TIE-404): port name was specified in the input EVCD. read_vectors failed while
attempting to find a hierModel index corresponding to this port.
EXPLANATION:
The input EVCD file contained an unrecognized port name, however processing
continues.
USER RESPONSE:
Determine the cause for the unsupported port name within the EVCD. Following are
some suggestions:
Copy and paste port name from message into the schematic viewer. Does the name
exist? Is this a port on the top level.
Have you produced a correct EVCD? The recommended NC system task is:
dumports(<test_bench_module.CHIP_instance>,"your_evcd_output_file",,2);
where: "2" tells NCsim to output the IEEE language standard format EVCD.
Correct the problem and rerun read_vectors.
WARNING (TIE-405): port value was specified in the input EVCD. This port is not a
primary Input or output. Values on this port will be dropped.
EXPLANATION:
Current EVCD support only allows importation of values found on primary inputs and
outputs. All other values are dropped however processing continues.
USER RESPONSE:
WARNING (TIE-406): TestSequence NNN completes with TI value not at its stability value.
EXPLANATION:
The specified test period specified caused the test sequence to end without all test
inhibits at stability. Processing continues.
USER RESPONSE:
Verify the correct test period value is specified.

WARNING (TIE-407): TestSequence NNN completes with Clock value not at its stability
(off) value.
EXPLANATION:
The Specified test period caused the test sequence to end without all clocks at stability/
off value. Processing continues.
USER RESPONSE:
Verify the correct test period value is specified.
WARNING (TIE-408): A direction value of value was found for name. This pin is not
defined as a type. This evcd entry will be dropped.
EXPLANATION:
The program was instructed to stim a pin that is not defined as an input pin or was
instructed to measure a pin which is not defined as a output pin. The data is dropped
USER RESPONSE:
Verify the Encounter Test model was built correctly. If not, rebuild the model before
attempting to re-import the EVCD data.
WARNING (TIE-409): An identifier of identifier was found on line line_number of

the input EVCD. This identifier was not defined within the input EVCD file. This error is most
likely the result of a syntax problem. Correct any syntax problems found and rerun
read_vectors.
EXPLANATION:
The input EVCD file contained an unrecognized and undefined identifier. Processing
continues.
USER RESPONSE:
Determine why there is a unsupported port name within the EVCD. Correct the problem
and rerun read_vectors.
INFO (TIE-800): Starting read_vectors.

EXPLANATION:
This informational message indicates the import EVCD process for has started.
USER RESPONSE:

INFO (TIE-801): Importing file: fileName.

EXPLANATION:
This informational message indicates the name of the file which is being imported.
USER RESPONSE:
INFO (TIE-803): The object object is already in use try again later.
EXPLANATION:
The indicated object could not be locked, therefore processing was terminated.
USER RESPONSE:
Rerun when the object is not in use.
INFO (TIE-804): TIEimport failed. Refer to preceding error messages.

EXPLANATION:
This informational message indicates that EVCD import processing unsuccessfully
completed.
USER RESPONSE:
Refer to the preceding error messages to determine the cause for the application failure.
INFO (TIE-805): Output filename: filename.

EXPLANATION:
This informational message indicates the name of the output file. Processing continues.
USER RESPONSE:
INFO (TIE-806): TIEimport (read_vectors language=evcd) completed syntax

checking of file filename. Syntax errors string found.
EXPLANATION:
The keyword value syntaxonly=yes was specified. Syntax checking of the input file
has completed.
USER RESPONSE:

If no syntax errors were detected, remove syntaxonly=yes from the command string
and rerun. If syntax errors were detected, correct errors and rerun. Continue until all
syntax errors have been detected and corrected. When no additional syntax errors are
detected, remove syntaxonly=yes from the command line and rerun to read the file.
INFO (TIE-807): TIEimport (read_vectors language=evcd) sucessfully completed

importing file filename.
EXPLANATION:
The program has successfully completed the import of the referenced file
USER RESPONSE:
ERROR (TIE-999): Internal Program Error occurred in file: fileName line: lineNumber
errorString
EXPLANATION:
This is a program error.
USER RESPONSE:

40
TIM - Import Test Pattern Data Messages
TIM-001 through TIM-050 on page 1251

TIM-001 through TIM-050

ERROR (TIM-001): Syntax error: Non-integer character found for node index in line
number. Edit the TBDpatt file by correcting the node index or fix the file syntax and then
rerun read_vectors.
EXPLANATION:
The node index must be a valid integer. Either the node index wasincorrectly specified
and contains a character which is not a digit or there are other errors in the file (for
example, a missing semicolon between events) causing the second event to be
incorrectly interpreted as a node index. Processing terminates.
USER RESPONSE:
Edit the input TBDpatt file to correct the node index or fix the file syntax, and then rerun.
ERROR (TIM-002): Error: read_vectors failed in TIMwriteBinaryFile while trying to

write the test vectors to the output file.
EXPLANATION:
An error occurred when read_vectors tried to write the data to a binary (TBDbin) file.
A preceding message explains the error condition. Processing terminates.
USER RESPONSE:

Check the previous message and correct the described error condition and then rerun.
If no previous message is produced, contact customer support (see Contacting
ERROR (TIM-003): Loading of vector correspondence file for test mode testmode failed.
Reason = reason.
EXPLANATION:
The vector correspondence file needed to import a TBDpatt file which is in vector format
could not be loaded due to thr reason described in the message. Processing terminates.
USER RESPONSE:
Correct the error condition and rerun write_vector_correspondence.
ERROR (TIM-004): Error: read_vectors failed setting experiment name = experiment

in TIMset Experiment.
EXPLANATION:
read_vectors was processing an experiment name and was unable to set it in the test
vectors. A preceding error message describes the error condition. Processing
terminates.
USER RESPONSE:
Correct the error condition described in the previous error message and rerun. If no
previous message is produced, contact customer support (see Contacting Customer
ERROR (TIM-006): Error: importfile filename could not be opened. Ensure that the
importfile filename is correctly specified and rerun.
EXPLANATION:
The importfile could not be opened.
USER RESPONSE:
Ensure that the importfile filename was correctly specified. If it was correctly spelled,
verify the file exists and that you have read access to it. Correct any misspellings or file
permissions and rerun.
ERROR (TIM-008): Error - application cannot lock object object.

EXPLANATION:

Ccould not lock the indicated object. This object is either an experiment, testmode, or
model. Processing terminates.
USER RESPONSE:
Check that the indicated object exists and is registered correctly in the globalData file.
Also check that it is spelled correctly. Create the object if needed or correct any
misspellings, and rerun.
ERROR (TIM-009): read_vectors failed while trying to register the experimental TBDbin
file on the globalData file. Correct the error condition reported in previous messages and
rerun.
EXPLANATION:
read_vectors faild in its attempt to register the output experimental TBDbin file on the
globalData file. A preceding error message describes the error condition. Processing
terminates.
USER RESPONSE:
Correct the error condition described in the preceding message, and rerun. Contact
ERROR (TIM-010): read_vectors - Failure attempting dependency creation: experiment

-> testmode. A preceding message from the globalData file utility describes the error
condition. Correct the error condition and rerun.
EXPLANATION:
The experiment is dependent on the test mode. The read_vectors command failed
in its attempt to register this dependency in the globalData file,. A preceding message
from the globalData file utility describes the error condition. Processing terminates.
USER RESPONSE:
Correct the error condition described in the preceding message and rerun. Contact
ERROR (TIM-011): The application testmode test mode is not registered on the
globalData file. Ensure that the test mode was successfully created and that the parameter
was correctly specified and then rerun.
EXPLANATION:
When a test mode is successfully created by build_testmode, it is registered on the
globalData file. read_vectors or read_sequence_definition checked the

test mode registration and found that the test mode was not registered. Processing
terminates.
USER RESPONSE:
Ensure that the TESTMODE environment variable or input parameter is correctly
specified. Ensure that build_testmode successfully completed. Rerun
build_testmode if needed, then rerun read_vectors and specify TESTMODE
correctly. Contact customer support (see Contacting Customer Service on page 23) if
problems persist.
ERROR (TIM-012): application - Error received from utility or method.

utility or method failed attempting to load test mode test mode name. A preceding
message should describe the error condition. Correct error(s) and rerun.
EXPLANATION:
The indicated utility or method failed while attempting to load the named test mode. If
the test mode that we are attempting to load was found within a Begin_Test_Mode
event, Going_To_Mode or In_Test_Mode, object it must exist before it can be loaded.
If the failure occurs on the test mode that we are attempting to build, a preceding
message should describe the error condition.
USER RESPONSE:
If the test mode named within the Begin_Test_Mode event, Going_To_Mode or
In_Test_Mode object does not exist, you must build the test mode before preceding. If
the named test mode is not required, remove it from the input file before attempting to
rerun import.
If the error occurs for the test mode we are attempting to build, correct the error condition
described in the preceding message and rerun.
Contact customer support (see Contacting Customer Service on page 23) if problems
persist.
ERROR (TIM-014): application - NULL pointer returned from TBDinit. Correct error
condition(s) described in previous messages and rerun.
EXPLANATION:
Initialization of the TBD data repository failed. A preceding message describes the error
condition. Processing terminates.
USER RESPONSE:

ERROR (TIM-020): read_vectors - Error: invalid test procedure type = type in line
number. Correct the test procedure type and rerun.
EXPLANATION:
An invalid test procedure type was encountered in the input TBDpatt file on the line
indicated. Processing terminates.
USER RESPONSE:
Correct the test procedure type and rerun.
ERROR (TIM-022): read_vectors - Error: invalid test sequence type = type in line
number. Correct the test sequence type and rerun.
EXPLANATION:
An invalid test sequence type was encountered in the input TBDpatt file on the line
indicated. Processing terminates.
USER RESPONSE:
Correct the test sequence type and rerun.
ERROR (TIM-028): application - could not determine a valid object from name name
on line number. Either the name does not exist within the model or the name was used in
conjunction with the wrong event type.
EXPLANATION:
The specified line in the TBDpatt file being read contains a name that either does not
exist within the model or the name was used in conjunction with the wrong event type.
For example,, a latch name was used within a Stim_PI event.
USER RESPONSE:
Check the spelling of the name on the line identified in the message. If the data being
read was created for a different version of the model, it is possible the net or block does
not exist within this version and must be removed from the input TBDpatt file. If the name
is a valid name for this model, ensure that the event type is correct for this object (for
example, Scan_Load for latches, Stim_PI for primary inputs). If the event type is
incorrect, correct the event type.
Correct the spelling, or remove the name or correct the event type and rerun.

ERROR (TIM-029): read_vectors - Error: Could not determine node name for vector
position position, vector type of type. Check your vector correspondence file (TBDvect).
EXPLANATION:
The indicated position in the vector could not be translated to a node. Processing
terminates.
USER RESPONSE:
Ensure the vector correspondence file was created successfully for this mode. Also,
ensure the vector correspondence file has not been incorrectly edited.
ERROR (TIM-030): application - Error: Vector is too long in line number.

EXPLANATION:
The vector on or near the indicated line is too long. Processing terminates.
USER RESPONSE:
Edit your importfile and shorten the vector.
ERROR (TIM-033): read_sequence_definition - Error: read_vectors failed in

TIMwriteSeqFile while trying to write the TBDseq file. Correct errors found in previous
messages and rerun.
EXPLANATION:
read_sequence_definition failed while attempting to write the TBDseq file. A
preceding message describes the error condition. Processing terminates.
USER RESPONSE:
ERROR (TIM-034): read_sequence_definition - Error: read_vectors failed setting

sequence definition name = name. Correct the error condition described in the preceding
message and rerun.
EXPLANATION:
read_sequence_definition failed while attempting to set the sequence definition
name for the indicated sequence. A preceding message describes the error condition.
USER RESPONSE:

ERROR (TIM-036): Error: read_sequence_definition failed to determine sequence

definition number from the sequence definition name name, in the apply event, line number.
Check the sequence definition name and ensure that the sequence definition file (TBDseq)
contains this sequence.
EXPLANATION:
read_sequence_definition must translate the sequence definition name in the
Apply event to a number that corresponds to its order in the TBDseq file. Therefore, the
sequence definition being applied must either be in the TBDseq file or, if importing a
TBDseqPatt file, must be in the TBDseqPatt file prior to the Apply event. Processing
terminates.
USER RESPONSE:
Ensure that the sequence definition exists, and that the Apply event has the sequence
definition name correctly spelled. Remove the Apply event if the sequence definition
does not exist. Fix the Apply event and rerun.
ERROR (TIM-038): read_sequence_definition - Error: Format mode must be node,

not vector. The sequence definition file being imported by Build Test Mode
(build_testmode) must have format mode = node Correct mode format and rerun.
EXPLANATION:
Vector format requires a TBDvect file which cannot be created prior to running
build_testmode. Therefore, the sequence definition file imported by
build_testmode cannot be in vector format. Processing terminates.
USER RESPONSE:
Change the sequence definition file used in build_testmode to node format and
rerun.
ERROR (TIM-039): application - Error: Test mode mode_name specified in the

Begin_Test_Mode event, line number, is not a valid test mode. Ensure that the test mode
name is correctly spelled and has been created.
EXPLANATION:
The Begin_Test_Mode event cannot specify a test mode which does not exist.
USER RESPONSE:

If the test mode was misspelled, correct the spelling and rerun. If the test mode has not
yet been built, run build_testmode for the test mode and then rerun.
ERROR (TIM-040): application - Error: Diagnostics with invalid event type, line
number, in filename. Diagnostics must be with an Expect event.
EXPLANATION:
Diagnostics can only follow an Expect event. Processing terminates.
USER RESPONSE:
Delete the diagnostics or move them so that they immediately follow an Expect event
and rerun.
ERROR (TIM-041): read_vectors - Error: TBDpatt file is in vector format, and was
created from a previous level of Encounter Test, but TBDvectorfile was not specified.
Rerun via command line and specify TBDvectorfile.
EXPLANATION:
If you are importing a TBDpatt file that contains event types from a previous level of
Encounter Test (for example, Stim_L1 and Measure_L1 events), then you must have
the vector correspondence file from that level. The file name of the vector
correspondence file must be specified as the TBDvectorfile keyword, which is a
command line only option. Processing terminates.
USER RESPONSE:
Determine the file name of the vector correspondence file that was used when the
TBDpatt file was created. Specify the TBDvectorfile keyword and rerun via command
line. If you do not have this vector correspondence file, then you can change your
TBDpatt file to node format and rerun.
ERROR (TIM-042): read_vectors - Error: Test_Section is missing the required

attribute attribute, near line number. Specify this attribute and rerun read_vectors.
EXPLANATION:
The attribute indicated in the error message was not specified. This attribute must be
specified before attempting to rerun read_vectors. Processing terminates.
USER RESPONSE:
Edit the importfile to add the missing attribute and rerun. For a complete list of
read_vectors options specify read_vectors -h. See read_vectors in the
Encounter Test: Reference: Commands for more information.

ERROR (TIM-043): read_vectors - Error: Signature event has both iteration and
fast_forward attributes specified near line number. Both attributes cannot be specified
on the same Signature event. Remove one of the attributes and rerun.
EXPLANATION:
The attributes indicated in the error message were both specified. It is invalid to specify
both for the same Signature event. Processing terminates.
USER RESPONSE:
Edit the importfile to remove one of the attributes and rerun. For a complete list of
read_vectors options specify "read_vectors -h". See read_vectors in the
Encounter Test: Reference: Commands for more information.
ERROR (TIM-044): read_vectors - Error: termination_domination specified as

unknown, near line number, when tester_termination is 0 or 1. When
tester_termination is specified as 0 or 1, a termination_domination of tester or
product must also be specified. Set a termination_domination and rerun
EXPLANATION:
When tester_termination is specified as 0 or 1, then either of the followng must occur:
termination_domination of tester or product must be specified
termination_domination may be defaulted to the TDR value
USER RESPONSE:
Edit the importfile to either remove the termination_domination or specify it as
0 or 1. Refer to the Encounter Test: Reference: Test Pattern Formats for more
information.
ERROR (TIM-045): application - Error: Node node specified near line number was
not the correct type of node for the event type which it is in. Either remove the node or replace
it with a node of the expected type
EXPLANATION:
The indicated node is invalid because it was not the correct type of node. For example,
if the event type is Scan_Load, then node must be an RSL node.
USER RESPONSE:

Edit the importfile and either remove the node or replace it with a node of the
expected type. Refer to the Encounter Test: Reference: Test Pattern Formats for
more information.
ERROR (TIM-046): Space allocation failed. Attempt to allocate number bytes failed.
EXPLANATION:
USER RESPONSE:
Rerun the application when more space is available.
ERROR (TIM-047): fast_forward attribute is incorrectly specified. Specify a valid

attribute value and rerun. If the attribute is on an LBIST test section, the valid values are
fast_forward_sequences or fast_forward_pins. If the attribute is on a channel scan
event, the valid values are fast_forward or fast_forward_save. Otherwise, only
fast_forward is valid.
EXPLANATION:
The fast_forward attribute is incorrectly specified. If the attribute is on an LBIST test
section, the valid values are fast_forward_sequences or fast_forward_pins. If
the attribute is on a channel scan event, the valid values are fast_forward or
fast_forward_save. Otherwise, only fast_forward is valid.
USER RESPONSE:
Edit the importfile to correct the attribute and rerun.
ERROR (TIM-048): Event event encountered in input vectors, line number, when defining
a new test mode. The named event can not be imported while building a new testmode.
Remove this event and re-run.
EXPLANATION:
When defining a test mode, the input test vector file may not contain any Scan_Load or
Scan_Unload events for the test mode being built. Since the test mode has not yet been
defined, the controllable scan chains and observable scan chains are not yet known.
Therefore, they cannot be used until after the test mode is defined. Processing
terminates.
USER RESPONSE:
Edit the importfile to remove the referenced event and rerun.

ERROR (TIM-049): application - Error: application could not determine

appropriate nodeID from name = name. Correct the name and rerun.
EXPLANATION:
An incorrect name was encountered in the input TBDpatt file on the indicated line. The
name may be a valid name, but it was not appropriate in this context. For example, using
a latch block name in a Stim_PI event would result in this error. Processing terminates.
USER RESPONSE:
Check the spelling of the name and check that the name is appropriate. Correct the
spelling or change to the correct name and rerun.
ERROR (TIM-050): Could not determine hierModel pin for observe point node node
specified near line number. Observe points must be on hierModel pins. Remove the node or
replace it with a node correlating to a hierModel pin and rerun
EXPLANATION:
The indicated node is invalid because it could not be correlated to a hierModel pin.
Observe points must be on hierModel pins.
USER RESPONSE:
Edit the importfile and either remove the node or replace it with a node correlating
to a pin. Refer to the Encounter Test: Reference: Test Pattern Formats for more
information.

ERROR (TIM-051): Could not determine Psuedo PI entry from name name in line number.
Correct the spelling or remove the name and then rerun.
EXPLANATION:
An incorrect name was encountered in the input TBDpatt file on the indicated line and
caused processing to terminate.
USER RESPONSE:
Check the spelling of the name. If the data being imported was for a different version of
the part, it is possible the psuedo PI does not exist in this version and may have to be
removed from the input TBDpatt file. Correct the spelling or remove the name, and rerun.
ERROR (TIM-052): read_vectors can not process structure-neutral test vectors. This is
not an accepted input test vector format.

EXPLANATION:
This experiments pattern data is in structure neutral format. This is not an accepted
pattern format. Processing terminates.
USER RESPONSE:
Correct the pattern format problem and rerun.
ERROR (TIM-053): read_vectors cannot process a Skewed_Scan_Load event for this

part. Replace the Skewed_Scan_Load events with Scan_Load events and rerun.
EXPLANATION:
The design does not support skewed loads. Only Scan_Loads may be imported for this
design.
USER RESPONSE:
Replace the Skewed_Scan_Load events with Scan_Load events and rerun.
ERROR (TIM-054): read_vectors cannot process a Skewed_Scan_Unload event for

this part. Replace the Skewed_Scan_Unload events with Scan_Unload events and rerun.
EXPLANATION:
The part does not support skewed unloads. Only Scan_Loads may be imported for this
design.
USER RESPONSE:
Replace the Skewed_Scan_Unload events with Scan_Unload events and rerun.
ERROR (TIM-055): Illegal usage of the Apply event. Apply events can only be used within
Sequence Definitions which have a sequence type of SCANOP or SCANSECT,
CNANNELMASKLOAD and MISRMASKLOAD.
EXPLANATION:
read_sequence_definition found an Apply event in an illegal location. Apply
events are only legal within sequence definitions of type SCANOP, SCANSECT,
CNANNELMASKLOAD and MISRMASKLOAD. Run terminates.
USER RESPONSE:
Correct the usage of the Apply even and rerun.

WARNING (TIM-056): Node node specified near line number was not defined as a clock
in the mode we are processing. Only clocks can be included in Pulse or Stim_Clock events.
Ensure that only clocks are referenced in Pulse and Stim_Clock events before rerunning.
EXPLANATION:
The indicated node was not flagged as a clock in this testmode. Use of a non-clock in a
clock event will cause a pattern audit to be set. Message is only written the first time the
node is used as a clock. Processing continues.
USER RESPONSE:
To correct this problem, perform one of the following:
Edit the importfile and either remove the node or replace it with a node defined
as a clock.
Rebuild your testmode and flag this node as a clock. If it is necessary to
continue processing without correcting this error, contact your manufacturing
site and ensure that they accept your test vectors. Refer to "TBDpatt and
TBDseqPatt Format" in the Encounter Test: Reference: Test Pattern
Formats for more information.
ERROR (TIM-057): Setup Sequence was not imported because it contains a measure
event. Remove all measure events from the Setup Sequence and rerun.
EXPLANATION:
Setup sequences are intended only for initializing the design in preparation for a series
of tests. A Setup sequence does not test anything by itself. Encounter Test software is
not designed to handle a test sequence disguised as a Setup sequence, so to avoid
unpredictable results or a possible crash in subsequent processing, this sequence is not
imported.
USER RESPONSE:
If this is a Setup sequence, edit the sequence definition and remove all measure events.
If it was a test sequence, edit the test sequence changing its type. Then rerun
ERROR (TIM-058): Event event was encountered in input test vectors, line number. No
Scan_Load, Scan_Unload or Channel_Scan events can be imported to this
mode.Remove this event and rerun.
EXPLANATION:

The mode was defined with no Representative Stim Latches (RSL) or Representative
Measure Latches (RML)The input pattern file may not contain any Scan_Load,
Scan_Unload, or Channel_Scan events. Processing terminates.
USER RESPONSE:
ERROR (TIM-059): application: filename not a file. Correct the importfile

specification and rerun.
EXPLANATION:
The specified importfile name is not a file. Processing terminates.
USER RESPONSE:
Correct the importfile specification and rerun.
ERROR (TIM-060): read_sequence_definition: Go_To_Mode and/or

In_Test_Mode objects are not allowed in the modeinit Sequence Definition. Correct the
modeinit Sequence_Definition and rerun.
EXPLANATION:
The mode initialization sequence includes Go_To_Mode and/or In_Test_Mode
application objects, this is not allowed. Processing terminates.
USER RESPONSE:
Correct the mode initialization sequence definition and rerun Build Test Mode.
WARNING (TIM-061): [Severe] Node node specified near line number is not controllable
in the mode_name test mode, so is not valid in the Scan_Load event.
EXPLANATION:
Each node specified in the indicated event must be a controllable latch. Either a non-latch
node was specified, or the latch is not in a controllable scan chain.
USER RESPONSE:
Ensure the correct node was specified. It must be a latch and it must be controllable.
One method to check this is to view the block in Encounter Tests View Schematic
window. Before displaying the Schematic Window, select the relevant test mode (which
appears in the TIM-061 message). Ensure Function: Flop/Latch Scan Data is
included under Items to Display in the Information Window Display Options (select

Options-Information Window in the Test: Schematic window). Highlight the block and
look in the Information Window for PSL after Flop/Latch Scan Data: Latch is..
If the latch is not a PSL (primary stim latch), review the circuit design and test function
information for this test mode to determine why the latch is not controllable.
Rerun after resolving any design or test function problems.
ERROR (TIM-062): Test mode modeName specified in the Begin_Test_Mode event is not
the parent test mode. The parent testmode is modeName. Correct the Begin_Test_Mode
event and then rerun read_vectors.
EXPLANATION:
The "Begin_Test_Mode" event must specify the parent test mode. the
"Begin_Test_Mode event found in the input test vectors contains the wrong test mode
name. Processing terminates.
USER RESPONSE:
Correct the "Begin_Test_Mode" event by inserting the correct test mode Name and
rerun.
WARNING (TIM-063): [Severe] Lineholds for Sequence Definition name conflict with
existing linehold information for this testmode. Refer to previous TLH messages, correct
linehold conflicts and then rerun.
EXPLANATION:
Linehold information found for the named Sequence Definition conflicts with the linehold
information for this testmode.
USER RESPONSE:
Refer to previous TLH messages in your job log. Rerun read_sequence_definition
to reimport the sequence definition after correcting any conflicting lineholds.
WARNING (TIM-064): [Severe] Multiple uncorrelated Primary Input ports were pulsed in
sequence identifier. Simulation of this event will be done with the clocks overlapped,
but may produce incorrect results if there are races in the design.
EXPLANATION:
Test vectors have been imported that contain an event that pulses more than one clock
at the same time. Encounter Test does not do any timing verification to ensure that the
clock pulses will actually overlap in the logic. Encounter Test will simulate the logic with
the clocks on simultaneously, but it may produce incorrect results if the clocks do not
overlap.

USER RESPONSE:
Use either or both of the following approaches:
If the clocks are not required to be simultaneously on, the input patterns can be
modified to serialize the clock pulses.
If the clocks are required to be overlapped to produce the correct results, verify
the timing of the common logic to ensure the clocks are overlapped so that the
simulators predicted results will match the actual hardware.
ERROR (TIM-065): Value specified for the BIST_flush attribute is not supported. Only
values of 1 and 0 supported. Correct the specified value and rerun.
EXPLANATION:
Only values of 1 and 0 are supported for the BIST_flush attribute. A value other than
1 or 0 was found. Program terminates.
USER RESPONSE:
Correct the specified value and rerun read_vectors.
ERROR (TIM-066): A pattern loop was found in setup sequence sequencename. Setup
sequences cannot be properly simulated if they contain pattern loops. Edit the setup
sequence definition by unraveling the loop and then rerun.
EXPLANATION:
Syntactically and in principle, it is acceptable to have pattern loops within setup
sequences. However, due to their special nature, setup sequences cannot be properly
simulated if they contain pattern loops.
USER RESPONSE:
Edit the setup sequence definition by unraveling the loop. That is, remove the
begin_loop and end_loop patterns and replicate the patterns inside by the number
of times you want them to be repeated. Then reimport the sequence definition.
ERROR (TIM-067): A mix of manipulated and unmanipulated test vectors were found in the
input file. Manipulated and unmanipulated test vectors cannot read into a single uncommitted
tests file.
EXPLANATION:
Test vectors created for a part number with utilizes pipeline scan must be run through the
insert_vector_pipeline_sequence program. The test vectors must be
manipulated before being applied at the tester. Multiple Tests were found within the input

file. One or more indicated that the test vecotrs had been manipulated, while one or
more indicated that they have not been manipulated. Encounter Test does not support
both manipulated and unmanipulated tests within the same test vector file.
USER RESPONSE:
Separate the manipulated and unmanipulated test vectors into separate files. Import the
manipulated and unmanipulated test vectors into separate Uncommitted vector files.
WARNING (TIM-068): [Severe] Block blockName was reduced from the model. The
block was reduced to the base of the fanout. Results may not match the results received when
processing the unreduced model.
EXPLANATION:
The Block is one leg of a fanout, and there is a buffer behind it that gets reduced back to
the root of the fanout. If this is true, forcing or releasing the reduced block ends up
affecting the entire fanout, not just the leg. Therefore, the result is not the same as it
would be in the unreduced model.
USER RESPONSE:
Build the unreduced model if necessary before you continue processing.
ERROR (TIM-069): Non Apply event was found within a SCANOP, SCANSECT,
CHANNELMASKLOAD, or MISRMASKLOAD Sequence Definition. Only Apply events are
allowed within these sequence types.
EXPLANATION:
A non Apply event was detected while importing a Sequence Definition of type SCANOP,
SCANSECT, CHANNELMASKLOAD or MISRMASKLOAD. Only Apply events are allowed
within these Sequence Definitions types. Run terminates.
USER RESPONSE:
ERROR (TIM-070): application: No input file was specified.

EXPLANATION:
No input source was specified. You must specify an inputfile or STDIN. Processing
terminates.
USER RESPONSE:
Re-run specifying the pattern source.

ERROR (TIM-071): read_vectors: Experiment filename is registered on the

globalData file. To overwrite an existing experiment you must specify overwrite=yes.
EXPLANATION:
An experiment name was specified which is registered on the globalData file. An
experiment name was specified which is registered on the globalData file.
overwrite=yes must be specified if you wish to overwrite the existing experiment.
USER RESPONSE:
Rerun specifying overwrite=yes if your wish is to overwrite the experiment. To create
a new experiment, change the name to one which is not registered on the globalData file.
ERROR (TIM-072): A logic value of NNN was found for a clock pulse. Legal pulse values are
+ or -. Correctly specify clock pulse values and rerun.
EXPLANATION:
The correct logic values for pulse events are + and -.
USER RESPONSE:
Modify all pulse events to correctly specify + and - for all clock values and rerun.
ERROR (TIM-073): Error in insert_vector_pipeline_sequence. The modeinit

sequence was not successfully updated.
EXPLANATION:
The program attempted to update the mode initialization sequence however an abnormal
exit occurred, producing either a core dump or other terminating error.
USER RESPONSE:
Review the lob for any messages that might help solve the problem. Refer to Pipelined
Control Signals in the Encounter Test: Guide 2: Testmodes and Initialization
Sequences in the Encounter Test: Guide 2: Testmodes for related information.
If the condition persists, contact customer support (see Contacting Customer Service
on page 23).
ERROR (TIM-074): read_sequence_definition failed attempting to open the name.

EXPLANATION:
read_sequence_definition failed to open the referenced TBDseq.
USER RESPONSE:

Verify the name and permissions, then rerun.
ERROR (TIM-075): Event event was encountered in input test vectors, line number. No
stream events of this type can be imported to this mode. Remove this event and rerun.
EXPLANATION:
The Mode was defined with no scanin or scanout pins. The input pattern file may not
contain any Compressed_Input_Stream or Compressed_Output_Stream events.
USER RESPONSE:
ERROR (TIM-076): [Input] Vector formatted events are not accepted during
build_testmode. Change any events using the vector format to use the name format and
restart the build_testmode process.
EXPLANATION:
When building test modes use name=value format rather then a vector to specify input
values. A vector formatted event was detected in the input pattern file.
USER RESPONSE:
Replace the vector formatted events with name formatted events and rerun
build_testmode.
ERROR (TIM-077): [Input] application - Error received from TLMloadModel

attempting to load the model for workdir.name.
EXPLANATION:
The specified application received an error condition attempting to load the the model.
The indicated utility or method failed. A preceding message describes the error
condition.
USER RESPONSE:
Correct the error condition described in the preceding message(s) and rerun. Contact
customer support (see Contacting Customer Service on page 23) if the problem
persists.
ERROR (TIM-078): [Input] application - Error received from TLMlsetMode

attempting to set test mode testmode. Refer to previous messages, correct the problem
and rerun.

EXPLANATION:
The specified application received an error condition attempting to set the named test
mode. The indicated utility or method failed. A preceding message describes the error
condition.
USER RESPONSE:
Correct the error condition described in the preceding message(s) and rerun. Contact
customer support (see Contacting Customer Service on page 23) if the problem
persists.
ERROR (TIM-079): Test mode modeName found in a objectType object does not exist.
The test mode must be build before the test mode can be used. Create modeName before
rerunning.
EXPLANATION:
While processing input test vectors or sequences a Going_To_Mode or
In_Test_Mode object specifies a test mode that does not exist for this part. Processing
terminates.
USER RESPONSE:
If the wrong test mode name was specified, correct the name specification and rerun. If
the test mode name is correct and the test mode is required then build the test mode
before rerunning this process. If no test mode specification is required then remove the
object from your input data and rerun.
ERROR (TIM-080): [Input] Experiment name keyword name does not match the
experiment name name found within the input test vectors. If your process requires that these
names match, correct the naming difference and rerun read_vectors. If it is not necessary
that your names match remove the consistentnames keyword from your command line
EXPLANATION:
Command line experiment name keyword does not match the experiment name found
in the input test vectors. This is only a problem if your process requires them to be the
same.
USER RESPONSE:
If matching names are required correct the naming problem before rerunning
read_vectors. If matching names are not necessary remove the consistentnames
keyword from the command line and rerun read_vectors.

ERROR (TIM-081): [Input] application found one or more syntax errors in file
filename. Correct the reported syntax errors and rerun.
EXPLANATION:
Detected syntax errors caused the import process to fail.
USER RESPONSE:
Correct syntax errors and rerun.
ERROR (TIM-082): [Input] The mode initialization Test_Sequence odometer has

Start_Osc events that do not agree with the oscillator programming specified on
Start_Osc events in a previous mode initialization Test_Sequence within the same
Test_Section. Oscillator frequencies cannot be changed in the middle of a
Test_Section. This experiment will not be imported.
EXPLANATION:
Oscillators require special constructs in WGL, STIL, and Verilog, and those constructs
cannot be dynamically changed. Importing of these vectors would cause errors in the
downstream command write_vectors.
USER RESPONSE:
Determine how a Test_Section was created that contains initialization Test_Sequences
which are not identical. Since this does not happen with Encounter Tests
create_*_tests commands, it must have happened through some editing of the
vector data. Edit the file again and put the Tester_Loops in separate Test_Sections
by inserting the following:
] Test_Section;
[Test_Section;
between the end of the preceding Tester_Loop and the begining of the Tester_Loop
that contains the mode initialization Test_Sequence identified in the message. Rerun
read_vectors performing the edit.
ERROR (TIM-083): [Input] The Start_Osc event odometer is not allowed because a
previous Start_Osc event in this Test_Sequence is specified on the same pin pinname.
One of these Start_Osc events must be removed before rerunning.
EXPLANATION:
An oscillator cannot be reprogrammed in the middle of a sequence. Only one
Start_Osc event is allowed per pin or per correlated pin group.
USER RESPONSE:

Remove one of the Start_Osc events and rerun read_vectors.
ERROR (TIM-084): [Input] The Start_Osc event odometer is not allowed because a
previous Start_Osc event in this Sequence_Definition is specified on the same pin
pinname. One of these Start_Osc events must be removed before rerunning.
EXPLANATION:
An oscillator cannot be reprogrammed in the middle of the mode initialization
Sequence_Definition. Only one Start_Osc event is allowed per pin or per
correlated pin group.
USER RESPONSE:
Remove one of the Start_Osc events and rerun read_vectors.
ERROR (TIM-085): [Input] Sequence_Definition sequencename contains one or more

Start_Osc events. Start_Osc events are supported by Encounter Test only within the
modeinit Sequence_Definition. This Sequence_Definition will not be imported.
Remove any Start_Osc events from the Sequence_Definition before attempting to
import the Sequence_Definition.
EXPLANATION:
The referenced Sequence_Definition does not have a type of mode initialization.
Only mode initialization Sequence_Definitions may contain Start_Osc events.
USER RESPONSE:
Remove one of the Start_Osc events from the Sequence_Definition and rerun
read_vectors.
ERROR (TIM-086): More than 1024 pattern loops were found within a single
Test_Sequence. Current read_vectors support for pattern loops within a single
Test_Sequence is limited to 1024, read_vectors terminates. If support for greater than
1024 pattern loops is required, contact Cadence Customer Support.
EXPLANATION:
A single Test_Sequence was found containing greater then 1024 pattern loops.
Current support is limited to 1024 patterns loops. read_vectors terminates.
USER RESPONSE:
If the problem is caused by an error within the input test_vectors, correct the error
and rerun read_vectors. If the input test vectors are correct, contact Cadence
Customer Support (see Contacting Customer Service on page 23).

ERROR (TIM-087): Sequence_Definition name was not found. name was specified in an
apply event. Sequence_Definitions referenced in Apply events must have been previously
defined. They must exist in the TBDseq file or precede all Sequence_Definitions which
reference it in the TBDseqPatt file. Rerun read_sequence_definition after ensuring all
Sequence_Definitions specified within Apply events are defined before being referenced.
EXPLANATION:
Sequence_Definitions must be defined before they can be specified in an Apply event. If
they were not previous imported, they must appear in the TBDseqPatt file being imported
before they can used in an Apply event.
USER RESPONSE:
Ensure all required Sequence_Definitions are defined before they are used. Rerun
read_sequences.
ERROR (TIM-088): A mix of Apply events and other event types was found within a single
pattern. Encounter Test does not support mixing Apply and non-Apply event types within the
same pattern. Processing terminates.
EXPLANATION:
Encounter Test does not support mixing Apply events and other event types in the same
pattern.
USER RESPONSE:
ERROR (TIM-089): Test mode modeName was specified in the Begin_Test_Mode event.
No parent test mode was defined. Correct your modeinit Test_Sequence and rerun
read_vectors.
EXPLANATION:
The Begin_Test_Mode is only specified if a parent test mode was defined. No parent
test mode exists. Processing terminates.
USER RESPONSE:
Correct the modeinit Test_Sequence and rerun.
ERROR (TIM-090): Sequence_Definition name which contains a Begin_Test_Mode

event was referenced by one or more Apply events. Use of Begin_Test_Mode events
outside of the modeinit sequence is not supported by Encounter Test. This sequence cannot
be inserted. Rerun after removing all Apply events which reference the name
Sequence_Definition.

EXPLANATION:
Begin_Test_Mode events can only occur as the first event within a modeinit
Sequence_Definition. As a result this sequence can not appear in an apply event.
USER RESPONSE:
Rerun after ensuring all apply events referencing the modeinit sequence are removed.
ERROR (TIM-092): read_vectors can not import a TBDpatt file containing stim_register or
measure_register objects.
EXPLANATION:
read_vectors does not support importing objects of this type.
USER RESPONSE:
validate this TBDpatt file requires these objects for the flow being achieved. A suggestion
is to print the patt file using expandscan=yes to load values straight to the PIs instead
of through the registers.
WARNING (TIM-513): Multiple events occurred on pinName pinname within a pattern of

odometer Sequence Definition. Insure that the manufacturing site processing you test
vectors supports processing static patterns which contain multiple events on a single pin. If
not rerun read_vectors to reimport the test vectors after correcting the problem.
EXPLANATION:
Multiple stims and/or pulses occurred within one pattern. Processing continues. An Audit
is set in the Test Pattern Audits.
USER RESPONSE:
Insure that the manufacturing site processing you test vectors supports processing static
patterns which contain multiple events on a single pin. If not rerun read_vectors to
reimport the test vectors after correcting the problem.

ERROR (TIM-402): application: filename
EXPLANATION:
The input TBDpatt file contained a syntax error. Processing terminates.
USER RESPONSE:

Review the TBDpatt file at the indicated line, fix the error and rerun.
WARNING (TIM-403): TBDread (read_vectors) - Obsolete unsupported event,

Stim_L1_L3, encountered in line number. It will be converted to Scan_Load event. This
may cause resimulation results to be different than expected.
EXPLANATION:
the input TBDpatt file contained a Stim_L1_L3 event which is no longer supported. The
event is converted to a Scan_Load event with no L3 stim. This may cause resimulation
results to be different than expected. Processing continues.
USER RESPONSE:
Use the output TBDbin file or add a P-clock pulse to the TBDpatt file and rerun.
WARNING (TIM-404): Obsolete unsupported event, Stim_L1_L3_Extra_A_Clock,

encountered in line number. It will be converted to a Skewed_Load event. This may cause
resimulation results to be different than expected.
EXPLANATION:
The input TBDpatt file contained a Stim_L1_L3_Extra_A_Clock event which is no
longer supported. The event is converted to a Skewed_Load event with no L3 stim. This
may cause resimulation results to be different than expected. Processing continues.
USER RESPONSE:
Use the output TBDbin file or add a P-clock pulse to the TBDpatt file and rerun.
WARNING (TIM-405): read_vectors - Scan_Load has value specified in vector position

position which is for Skewed_Scan_Load, events only, on line number. Thi extra value
will be ignored.
EXPLANATION:
The vector correspondence indicates that the indicated position in the vector is for a
skewed stim latch (SSL). It is ignored for a normal Scan_Load. Processing continues.
USER RESPONSE:
Check the input data to ensure that the Scan_Load contains the stims that you want and
are in the correct vector order. Change your input data if desired and rerun.
WARNING (TIM-407): read_sequence_definition - Non-replaceable Sequence

definition name, sequence type type already exists in the sequence definition (TBDseq) file.
The sequence definition name you are attempting to import will be discarded.
EXPLANATION:

The importfile contained a sequence definition which already exists in the sequence
definition (TBDseq) file. This sequence is a non-replaceable sequence. The sequence
you are trying to import will be discarded. Processing continues.
USER RESPONSE:
If the sequence definition which was already in the TBDseq file is satisfactory, then no
action is needed.
If you really want the imported sequence definition to replace the existing sequence
definition, delete the TBDseq file and import your own sequence definitions.
Export (report_sequences) the sequence definitions
Edit the resulting TBDseqPatt file to replace the indicated sequence definition
with your own version.
Rerun read_read_sequence_definition.
This should only be done with extreme caution since changing your sequence definitions
may invalidate your tests.
WARNING (TIM-408): read_vectors - termination_domination near line number

is ignored. If tester_termination is specified as none, then tester_termination is
not applicable and is ignored.
EXPLANATION:
If tester_termination is specified as none, then termination_domination is
not applicable and is ignored. Processing continues.
USER RESPONSE:
No response required. Refer to the Encounter Test: Refere nce: Test Pattern
WARNING (TIM-409): read_vectors - termination_domination near line number

does not match the domination specified in the TDR. The termination_domination from
the importfile will be used.
EXPLANATION:
The termination_domination value in the input file is not the same as the
domination specified in the TDR. The value from the input file is used. Processing
continues.
USER RESPONSE:

WARNING (TIM-410): read_vectors - tester_termination near line number does

not match the termination specified in the TDR. The tester_termination from the
importfile will be used.
EXPLANATION:
The tester_termination value in the input file is not the same as the termination
specified in the TDR. The value from the input file is used.
USER RESPONSE:
WARNING (TIM-411): read_vectors - Error: Invalid value, value, specified near line
number. Only 0 and 1 are valid ignore values. The invalid value will be ignored.
EXPLANATION:
The indicated value is invalid for an ignore value. Only 0 or 1 are accepted. Processing
continues and the invalid value is ignored.
USER RESPONSE:
Review the importfile to ensure that the ignored value is not needed. If it is needed,
edit the importfile, correct the invalid value, and rerun.
Refer to the Encounter Test: Refere nce: Test Pattern Formats for more information.
WARNING (TIM-412): application - Correlated PI value at bit position position

conflicts with its representative PI. The values will be left as specified.
EXPLANATION:
A set of PIs which are correlated were specified with conflicting values. The values will
be left as specified for this set. This should be carefully reviewed to ensure that this is
really intended. Normally, correlated PIs should have values which do NOT conflict with
the correlation; however there are rare instances when you may need them to be at other
values. Processing continues and the set of correlated PIs will be left as is.
USER RESPONSE:

Review this carefully to ensure that this is not a mistake, but is really intended. If this was
not intended, then edit the importfile, correct the invalid value, and rerun. Refer to
the Encounter Test: Refere nce: Test Pattern Formats for more information.
WARNING (TIM-413): application - Correlated PI value on node node conflicts with

its representative PI. The values will be left as specified.
EXPLANATION:
A set of PIs which are correlated were specified with conflicting values. The values will
be left as specified for this set. This should be carefully reviewed to ensure that this is
really intended. Normally correlated PIs should have values which do NOT conflict with
the correlation; however there are rare instances when you may need them to be at other
values. Processing continues and the set of correlated PIs will be left as is.
USER RESPONSE:
Review this carefully to ensure that this is not a mistake, but is really intended. If this was
not intended, then edit the importfile, correct the invalid value, and rerun. Refer to
the Encounter Test: Refere nce: Test Pattern Formats for more information.
ERROR (TIM-414): The number of begin_loop patterns does not match the number of
end_loop patterns in TYPE NAME. Correct this mismatch between begin_loop and
end_loop patterns and reimport your test vectors.
EXPLANATION:
Every loop must have a begin and an end. read_vectors or
read_sequence_definition detected a mismatch between the number of
begin_loop and end_loop patterns.
USER RESPONSE:
Correct this mismatch and reimport your test vectors.
ERROR (TIM-415): application found an eventName event which contains an invalid

oscillator. pinname is not identified as an oTI or OSC test function pin in the currently
processed testmode.
EXPLANATION:
Any pin found in a Start_Osc, Stop_Osc or Wait_Osc event must be identified as an
oTI or OSC in the current testmode.
USER RESPONSE:

If the wrong pin was specified in the input data, correct the data and rerun. If the pin is
required to be used as an oscillator rebuild the testmode specifying this pin as an oTI or
OSC and then rerun the import step.
WARNING (TIM-416): Oscillator pinname was found to have a pulsespercycle count

not supported by the TDR. The Start_Osc event is in sequence identifier. Correct
the pulsespercycle count and reimport the test vectors.
EXPLANATION:
The application checked the cycle count against the TDR
Oscillator_Cycles_Per_Tester parameter and did not find a matching cycle
count.
USER RESPONSE:
Review the input test vectors and correct the pulsespercycle parameter. Reimport
the test vectors.
WARNING (TIM-418): A Wait_Osc event was detected without a preceding Start_Osc

event in sequence identifier. Review the input pattern test pattern data adding
Start_Osc and Wait_Osc events where necessary. Rerun after correcting the data.
EXPLANATION:
A Start_Osc event is missing from the data. One will be assumed and processing will
continue. Previous pattern data may be missing required Wait_Osc events.
USER RESPONSE:
Review the input pattern test pattern data adding Start_Osc and Wait_Osc events
where necessary. Refrun after correcting the data.
WARNING (TIM-419): A Wait_Osc event was detected in a pattern with other conflicting
events in sequence identifier.
EXPLANATION:
Patterns with a Wait_Osc event cannot also contain Start_Osc or latch events.
USER RESPONSE:
Remove the Wait_Osc events from the affected patterns. Rerun read_vectors.
WARNING (TIM-420): Oscillator pinname was found with a pulsespercycle count

greater than zero. The pulsespercycle count for an asynchronous oscillator should be

zero. The Start_Osc event can be found in sequence identifier. Correct the
pulsespercycle parameter and reimport the test vectors.
EXPLANATION:
The oscillator count for all asynchronous oscillators should be zero. Processing
continues.
USER RESPONSE:
Review the input TBD data and correct the pulsespercycle parameter. Reimport the
test vectors.
WARNING (TIM-421): Asynchronous oscillator pinname was found on a Start_Osc

event in sequence identifier. The TDR does not support asynchronous oscillators.
Review and correct the input test vectors and then reimport the test vectors.
EXPLANATION:
The TDR does not support asynchronous oscillators. Processing continues.
USER RESPONSE:
Review and correct the input test vectors and then reimport the test vectors.
WARNING (TIM-422): Oscillator pinname was found with a pulsespercycle count of

zero. The pulsespercycle count for synchronous oscillator should not be zero. The
Start_Osc event can be found in sequence identifier. Review the input test vectors,
correct the pulsespercycle parameter, and then reimport the test vectors.
EXPLANATION:
The oscillator count for all synchronous oscillators should not be zero. An allowable
pulsespercycle count can be found in the TDR.
USER RESPONSE:
Review the input test vectors and correct the pulsespercycle parameter. Reimport
the test vectors.
WARNING (TIM-423): Sequence definition name sequence type type already exists in the
sequence definition (TBDseq) file, it will be replaced with sequence definition name which
has a sequence definition type of type.
EXPLANATION:

This is a warning that you have replaced an existing sequence definition with another
sequence definition which has the same name but a different type. Processing continues.
USER RESPONSE:
An existing sequence definition was removed from the TBDseq file. If this sequence
definition is required, rerun read_sequence_definition and reimport the sequence
definition with a new name.
WARNING (TIM-424): Sequence definition name, sequence type number is a non-

replaceable sequence definition. A sequence definition with this name already exists in the
sequence (TBDseq) file. The sequence definition you are attempting to import will be
discarded.
EXPLANATION:
Each sequence definition must have a unique name. Processing continues.
USER RESPONSE:
If no sequence definition of this non-replaceable type exists in the sequence definition
file, change the name and rerun read_sequence_definition to reimport the
WARNING (TIM-425): Multiple Sequence Definitions with a type of nonscanflush exist in

the sequence definition (TBDseq) file. Only the first nonscanflush sequence in the TBDseq
file will be utilized by Encounter Test applications. If your intent was to replace your
nonscanflush sequence, change its name to match that of the first nonscanflush in the
sequence defintion (TBDseq) file and then reimport the new sequence.
EXPLANATION:
Multiple sequence definitions with a type of nonscanflush have been imported. Each
of the sequences has a unique name, but only the first of these nonscanflush sequences
will be utilitized by Encounter Test.
USER RESPONSE:
If your intent was to replace your nonscanflush sequence, change its name to match that
of the first nonscanflush in the sequence defintion (TBDseq) file and then rerun
read_sequence_definition to replace the first sequence.
WARNING (TIM-426): A Lineholds object is attached to Sequence Definition name which

has a sequence type of type. Encounter Test only utilizes linehold information found on
Sequence Definitions with a sequence type setup or test. This Lineholds data will be
imported but it will not be checked for accuracy or utilized by the Encounter Test system.
EXPLANATION:

During Encounter Test processing only Lineholds information specified on Sequence

Definitions of type test is utilized. Lineholds data found on Sequence Definitions with a
type other then test is ignored during processing.
USER RESPONSE:
If your intent was for the Sequence Definition to have a type of test, change the
sequence setup or test and then reimport the sequence definition.
WARNING (TIM-427): A Lineholds object is attached to Sequence Definition name. This

Linehold data will be imported but it cannot be checked for accuracy by
read_sequence_definition. To check this linehold information with
read_sequence_definition, reimport this sequence after build_testmode has
completed.
EXPLANATION:
Information required to check the linehold data is not available to
read_sequence_definition during build_testmode.
USER RESPONSE:
To check this linehold information with read_sequence_definition, reimport this
sequence after build_testmode has completed. If not checked for accuracy, problems
could occur during subsequent Encounter Test processing.
WARNING (TIM-429): A linehold specified on pin pinName is overridden by sequence

Definition sequenceName. Ensure the Sequence_Definition is correct. If it is incorrect, edit
the Sequence_Definition and rerun read_sequence_definition.
EXPLANATION:
A linehold was specified on the referenced pin name, but the sequence definition
specifies a pulse or stim (to the opposite state) on this pin.
USER RESPONSE:
Ensure the sequence definition is correct. If it is not correct, edit the sequence and rerun
WARNING (TIM-430): Sequence Definition sequenceName conflicts with the specified

linehold on pseudo PI pinName. Ensure the Sequence_Definition is correct. If it is not
correct, edit the Sequence_Definition and rerun read_sequence_definition.
EXPLANATION:
A linehold was specified on ppi name, but the sequence definition specifies a pulse or
stim (to the opposite state) on this pseudo primary input.

USER RESPONSE:
Ensure the sequence definition is correct. If it is not correct, edit the sequence definition
and rerun read_sequence_definition.
WARNING (TIM-431): Sequence Definition sequenceName conflicts with the TI attribute

specified on pinName. Ensure the Sequence_Definition is correct. If the
Sequence_Definition is incorrect, edit the Sequence_Definition and rerun
read_sequence_definition. If the Sequence_Definition is correct, change the test
function pin attribute by editing the testmode defintion and rebuild the testmode.
EXPLANATION:
The pin, pinName, was specified to be held constant by a TI attribute. These attributes
are not intended to be overridden. Verify Test Structures (TSV) uses these values in
determining whether the logic conforms with the design guidelines which support the
generation of valid test data.
sequenceName specifies a pulse or stim (to the opposite state) on this pin, invalidating
the TSV assumptions. Encounter Test cannot guarantee valid test data if this state is
overridden.
USER RESPONSE:
Ensure the Sequence Definiton is correct. If not, edit the sequence definiton and rerun
read_sequence_definition to import the updated sequence definition. If the
sequence is correct, change the test function pin attribute by editing the testmode
definition and rebuilding the testmode.
WARNING (TIM-432): Sequence Definition sequenceName conflicts with the TC attribute

specified on pinName. Ensure the Sequence_Defintiion is correct. If the
Sequence_Definition is incorrect, edit the Sequence_Definition and rerun
read_sequence_definition. If the Sequence_Definition is correct, change the test
function pin attribute by editing the testmode defintion and rebuild the testmode.
EXPLANATION:
The pin, pinName, was specified to be held constant by a TC attribute. These attributes
are not intended to be overridden. TSV uses these values in determining whether the
logic conforms with the design guidelines which support the generation of valid test data.
sequenceName specifies a pulse or stim (to the opposite state) on this pin, invalidating
the TSV assumptions. Encounter Test cannot guarantee that its test data will be valid if
this state is overridden.
USER RESPONSE:

Ensure the Sequence_Defintiion is correct. If the Sequence_Definition is incorrect, edit

the Sequence_Definition and rerun read_sequence_definition. If the
Sequence_Definition is correct, change the test function pin attribute by editing the
testmode defintion and rebuild the testmode.
WARNING (TIM-433): Clock stim found on a pin that is not identified as a clock. Found in
sequence identifier. Edit your input patterns placing all non-clock PI stims within
Stim_PI events and reimport the test vectors.
EXPLANATION:
A non-clock Primary Input was stimmed within a Stim_Clock event. Stim data for non-
clock PIs should be found in Stim_PI events.
USER RESPONSE:
Edit your input patterns placing all non-clock PI stims within StimPi events. Rerun
read_vectors or read_sequence_definition to reimport your test vectors.
WARNING (TIM-434): BIST_flush attribute was found outside a modeinit sequence type
name. This attribute will be ignored. Ensure the sequence type is correct. If the sequence
type is correct, then remove the BIST_flush attribute from this event. If necessary, set the
Sequence_Definition type to modeinit or init if importing test vectors and then rerun.
EXPLANATION:
The BIST_flush attribute is significant only in the context of a mode initialization
sequence. It is used to direct Encounter Test to automatically derive the initial states of
the channel latches when setting up (initializing) an LBIST test mode. This attribute was
found on a event in a sequence that is not a modeinit sequence.
USER RESPONSE:
Ensure the sequence was properly identified. If necessary, change the sequence type to
modeinit if importing a sequence definition or init if importing Encounter Test pattern
data. If the sequence type is correct, then remove the BIST_flush attribute from this
event. Rerun after making any of these modifications.
WARNING (TIM-436): BIST_flush was specified, but is not supported at this time. It will
be ignored.
EXPLANATION:
Support for the BIST_flush option has been suspended due to technical problems.
Encounter Test results are not reliable when this option is used, therefore is disabled for
this release.
USER RESPONSE:

If the initial value of the channel latches is critical for your BIST methodology, then you
must specify the values individually in the Scan_Load event of the mode initialization
sequence instead of relying on the BIST_flush option. If it was not imperative for you
to use the BIST_flush option, then this message can safely be ignored.
WARNING (TIM-437): A eventType event was specified with a vector number

characters long. The correct vector length is number. All unspecified values will be set to the
default value. If no default value was specified, x will be used as the default.
EXPLANATION:
When processing the supplied vector, there was not a value specified for all of the bit
positions. Unspecified bit positions will be set to the default value specified by the user.
If no default value was specified for the event, x will be used as the default.
USER RESPONSE:
If a value other then x or the default is required. specify the correct values in the vectors
WARNING (TIM-438): A eventType event was specified with a vector number

characters long. The correct vector length is number. All extra values will be dropped. If the
resulting event values were not what you require, correct the input test vectors and rerun
read_vectors.
EXPLANATION:
The number of values specified in the input vectors were greater than required. All extra
values were dropped.
USER RESPONSE:
If the resulting event values were not what you require, correct the input test vectors and
rerun read_vectors.
WARNING (TIM-439): Block Name specified on line position of the input file is not found
in a controllable scan chain. The latch and its value will be ignored.
EXPLANATION:
The vector correspondence indicates that the indicated position in the vector is for a
skewed stim latch (SSL). It is ignored for a normal Scan_Load. Processing continues.
USER RESPONSE:
Review the input data to ensure that the Scan_Load contains the desired stims and are
in the correct vector order. Correct and rerun if necessary.

WARNING (TIM-440): The test mode specified indicates that scan control pipeline support
is required. Tests must begin with a Scan_Load event, contain a Channel_Scan event or
end with a Scan_Unload event. One or more tests exist where this is not the case. Correct
the input test vectors by adding the required events and rerun.
EXPLANATION:
Pipeline scan chain tests must start with a Scan_Load event, contain a Channel_Scan
event or finish with a Scan_Unload event. Tests that do not meet this requirement are
invalid.
USER RESPONSE:
Correct the input patterns by making sure that all tests begin with a Scan_Load event
and contain a Channel_Scan event or end with a Scan_Unload event. Rerun after
correcting the input test patterns.
ERROR (TIM-443): Unable to include file with empty file name at file_line.
EXPLANATION:
An include was specified with an blank specification of the file to include. Nothing will be
included.
USER RESPONSE:
Check the includes in the STIL data to ensure that they are correct.
WARNING (TIM-500): Multiple events occurred on pinname within pattern

patternNumber. Ensure that the manufacturing site processing your test vectors supports
processing static patterns which contain multiple events on a single pin. If not, correct the
problem and rerun read_vectors.
EXPLANATION:
USER RESPONSE:
Ensure that the manufacturing site processing your test vectors supports processing
static patterns which contain multiple events on a single pin. If not, correct the problem


WARNING (TIM-501): An init type sequence was processed, but it is not the same as the
modeinit sequence that was used to build the test mode. This sequence is being replaced by
the modeinit sequence in TBDseq.modeName.
EXPLANATION:
A primary purpose of the mode initialization sequence is to place the design into the
stability state for the test mode. There are many internal tables and much Encounter Test
processing that depend upon this state. Therefore, it is forbidden to alter the initial state
after the mode is built. The exception to this is that line-hold fixed value latches, PRPGs
and MISRs may be initialized differently, as long as their initialization is done by way of a
Scan_Load event, appropriately placed, in the modeinit sequence so that Encounter
Test can recognize it. The current message means that there is a difference between the
modeinit sequence as defined in the TBDseq file and the init sequence that was being
processed, and this difference is not confined to the values in fixed-value latches, PRPGs
and MISRs (actually, all non-TI and non-TC latches) as represented by the Scan_Load.
The init sequence is replaced by the modeinit sequence from the TBDseq file, and the
Scan_Load values from the input init sequence are used.
USER RESPONSE:
No response required; processing continues.
WARNING (TIM-502): No Start_Osc event was found in sequence identifier

before encountering a Stop_Osc event for the oscillator. Review the input test vectors and
insert Start_Osc events where necessary and then rerun read_vectors.
EXPLANATION:
The input test vectors contain a Stop_Osc event for an oscillator which was not
previously started. Processing continues.
USER RESPONSE:
Review the input test vectors, insert Start_Osc events where necessary and then rerun
read_vectors.
WARNING (TIM-503): The Test_Sequence being processed has a mix of patterns, some
with Wait_Osc events and others without Wait_Osc events. If Wait_Osc events are
required, update the test vectors by adding them where required. If they are not required,
remove them from the test vectors. Rerun read_vectors after editing the input file.
EXPLANATION:

A Test Sequence which contains no Start_Osc or Stop_Osc events must either have
Wait_Osc events in all patterns or no Wait_Osc events. A mix has been detected.
USER RESPONSE:
Review the input test vectors. If Wait_Osc events are necessary, add them where
required. If no Wait_Osc events are needed in the Test Sequence, remove the
unnecessary Wait_Osc events. After making the required changes, rerun
read_vectors.
WARNING (TIM-504): [Severe] The event at line lineNumber of the file fileName
refers to an OPCG or PLLregister (registerName) which is not recognized for the target
test mode. The specified register value is ignored and could lead to incorrect PLL or OPCG
programming. This error should be corrected before continuing.
EXPLANATION:
The register name found within the Load_OPCG_Controls event did not match an
existing OPCG register.
USER RESPONSE:
Correct the Load_OPCG_Controls event and rerun.
attempts to assign a values (ValueString) to an OPCG or PLL register
(registerName), but the number of specified values is greater than the register length. The
extra register values will be ignored and could lead to incorrect PLL or OPCG programming.
This error should be corrected before continuing.
EXPLANATION:
The program detected more values for the OPCG register than bit positions within the
OPCG register.
USER RESPONSE:
Correct the Load_OPCG_Controls event and rerun.
WARNING (TIM-506): [Severe] Load_OPCG_Controls in lineNumber file sequence

fileName refers to an OPCG or PLLregister name (registerName), but at least one of
the bits in this register is not located within a scan chain of the parent test mode (modeName).
The specified value(s) will be ignored and could lead to incorrect PLL or OPCG programming.
This error should be corrected before continuing.
EXPLANATION:

One or more of the latches in this OPCG register can not be loaded using the scan chains
of the parent test mode.
USER RESPONSE:
Correct the OPCG registers and rebuild the test mode build.
WARNING (TIM-507): [Severe] The event at line lineNumber of the file fileName is
not allowed. This event is only allowed within a modeinit sequence preceding a Scan_Load
event or within a setup sequence definition. This event is ignored. The error should be
corrected before continuing.
EXPLANATION:
Load_OPCG_Controls events should only be found in sequences with a type of
modeinit or setup. The event was found in a non -upported location.
USER RESPONSE:
Correct the input file errors and rerun.
refers to an OPCG or PLL register (registerName), but a problem was discovered with the
definition of this register when the test mode was defined. The specified register values are
ignored and could lead to incorrect PLL or OPCG programming. This error should be
corrected before continuing.
EXPLANATION:
The Load_OPCG_Controls event contained values for a register that had problems
when the test mode was defined.
USER RESPONSE:
This message is more than likely triggered by problems reported via analysis messages
TSV-132 or TSV-133. Please use these TSV messages as a starting point for analysis.
Correct problems with your OPCG or PLL registers and restart processing for this test
mode.
WARNING TIM-509): [Severe] The event at line lineNumber of the file fileName
attempts to assign values (value) to an OPCG or PLL register (registerName), but the
number of speciried values is less then the register length. The unspecified high order bits
will be set to zero and could lead to incorrect PLL or OPCG programming. This error should
be corrected before continuing.
EXPLANATION:

The program detected fewer values for the OPCG register than bits positions within
within the OPCG register. A value of zero will be used for unspecified bit positions
USER RESPONSE:
Correct the Load_OPCG_Controlsl event and rerun.
WARNING (TIM-510): Pattern pattern_number which is a timed test pattern does not
end with a capture event. If the test was manually written and was intended to end with a
capture event, edit the Test_Sequence to correct this error by specifying the attribute
timed_type=capture for the last event and then rerun.
EXPLANATION:
A complete timed pattern normally ends with a capture event. The final event within the
identified timed pattern in the message is not classified as a capture event.
USER RESPONSE:
If the test was manually written and was intended to end with a capture event, edit the
test sequence definition to correct this error by specifying the attribute
timed_type=capture for the last event in the timed test pattern and then rerun
read_vectors or read_sequence_definition as appropriate.
WARNING TIM-511): The Load_OPCG_Controls event was not found in the correct
modeinit sequence location. The Load_OPCG_Controls event should be located in the first
pattern of the modeinit Sequence_Definition between the Begin_Test_Mode event and the
Scan_Load event. The OPCG registers are not loaded. Correct the modeinit
Sequence_Definition and rerun
EXPLANATION:
The Load_OPCG_Controls event should be located in the first pattern of the modeinit
sequence between the Begin_Test_Mode event and the Scan_Load event. The
Scan_Load was not updated with the latch values from the Load_OPCG_Controls
event because the Load_OPCG_Controls event was not found in the correct location.
USER RESPONSE:
Insert the Load_OPCG_Controls event between the Begin_Test_Mode event and
the Scan_Load event and then rerun the program.
WARNING (TIM-512): Sequence Definition sequence_number contains one or more

timed test patterns which do not end with a capture event.If the Sequence_Definition timed
patterns were intended to end with a capture, correct this error by specifying the attribute
timed_type=capture on the last event in the timed test pattern and then rerun.
EXPLANATION:

A complete timed pattern normally ends with a capture event. The final event within the
timed pattern is not a capture event.
USER RESPONSE:
If the Sequence Definition timed patterns are intended to end with a capture event, edit
the test sequence definition by specifying the attribute timed_type=capture for the
last event in the timed test pattern and then rerun.
WARNING (TIM-513): Multiple events occurred on pinName pinname within a pattern of

odometer Sequence Definition. Ensure that the manufacturing site processing your test
vectors supports processing patterns which contain multiple events on a single pin. If not,
correct the pattern and rerun read_sequence_definition.
EXPLANATION:
Multiple stims and/or pulses occurred within one pattern. Processing continues and a
test pattern audit is set.
USER RESPONSE:
Ensure that the manufacturing site processing your test vectors supports processing
static patterns which contain multiple events on a single pin. If not, correct the problem
WARNING (TIM-514): read_vectors found an empty eventType event in

Test_Sequence odometer. Encounter Test does not add clocks to empty eventType
events. The Test_Sequence is kept as is, but it will most likely not work as intended and
should be corrected. Add the required clocks to the event or remove the event from your test
vectors and then rerun.
EXPLANATION:
An empty clock event was encountered while importing the identified Test_Sequence.
Clocks will not be added to the event. The Test_Sequence is kept as is, but it will most
likely not work as intended and should be corrected. Processing continues.
USER RESPONSE:
Add the required clocks to the event or remove the event from your test vectors and then
rerun read_vectors.
WARNING (TIM-515): read_sequence_definition found an empty eventType event

in Sequence_Definition sequenceName. Encounter Test does not add clocks to empty
eventType events. The Sequence_Definition is kept as is, but it will most likely not
work as intended and should be corrected. Add the required clocks to the event or remove
the event from your Sequence_Definition and then rerun.

EXPLANATION:
An empty clock event was encountered while importing the identified
Sequence_Definition. The Sequence_Definition is kept as is, but it will most
likely not work as intended and should be corrected. Processing continues.
USER RESPONSE:
Add the required clocks to the event or remove the event from your
Sequence_Definition and then rerun read_sequence_definition.
WARNING (TIM-516): [Severe] Checking of the modeinit sequence was disabled. A Test
Section was found lacking an init Test Sequence.
EXPLANATION:
copyinitseq=no disables checking of the modeinit Test_Sequence. A Test Section
was found lacking an init sequence
RESPONSE:
Processing continues. If you want a modeinit Test_Sequence either add one to the
input test vector file.
ERROR (TIM-517): Load_OPCG_Controls event found when no OPCG exists.

Load_OPCG_Controls event(s) must be removed before you continue.
EXPLANATION:
No OPCG status record exists and a Load_OPCG_Controls event has been
encountered. Without OPCG status information read_vectors can not continue.
USER RESPONSE:
Remove all Load_OPCG_Controls events before restarting your process.
WARNING (TIM-518): Multiple events occurred on pinName pinnamewithin the Sequence

odometer. Ensure that the manufacturing site processing you test vectors supports
processing static patterns which contain multiple events on a single pin. If not rerun
read_vectors to reimport the test vectors after correcting the problem.
EXPLANATION:
USER RESPONSE:

Insure that the manufacturing site processing you test vectors supports processing static
patterns which contain multiple events on a single pin. If not rerun read_vectors to
reimport the test vectors after correcting the problem.
INFO (TIM-800): Starting application.

EXPLANATION:
Informational message indicating that processing has started. Processing continues.
USER RESPONSE:
INFO (TIM-801): application importing file: filename.

EXPLANATION:
Informational message indicating the name of the file which is being imported.
USER RESPONSE:
INFO (TIM-804): application: The object object is already in use. Try again later.
EXPLANATION:
The indicated object could not be locked so read_vectors could not continue.
USER RESPONSE:
Rerun when the object is not in use.
INFO (TIM-805): application successfully completed importing file filename.

EXPLANATION:
Informational message indicating that processing completed successfully.
USER RESPONSE:
INFO (TIM-806): application failed. Refer to preceding error messages.

EXPLANATION:

Informational message indicating that processing completed unsuccessfully. Processing

terminates.
USER RESPONSE:
Refer to the preceding error messages to determine what caused the application to fail.
assistance if problems persist.
INFO (TIM-807): application output file will be filename.

EXPLANATION:
Informational message indicating the name of the output file. Processing continues.
USER RESPONSE:
INFO (TIM-808): Sequence Definition sequencename already exists in the TBDseq file.
The existing sequence will be replaced.
EXPLANATION:
A Sequence Definition existed in the TBDseq file with the same name as one specified
for import. The existing sequence Definition was replaced with the new sequence
Definition. Processing continues.
USER RESPONSE:
INFO (TIM-809): The input contains pseudo primary input events, but there are no pseudo
primary inputs in test mode modename. All pseudo primary input events will be ignored.
EXPLANATION:
This message indicates that the pattern source file contains one or more of the following
events: Stim_PPI, Stim_PPI_Clock, Pulse_PPI. This test mode has no pseudo
primary inputs (PPIs) defined, so these events are meaningless in this test mode.
USER RESPONSE:
Ensure the correct test mode and correct pattern source file are selected. If you intended
to import patterns from a test mode containing pseudo primary inputs into the test mode
without pseudo primary inputs, then no response is necessary.

INFO (TIM-810): A duplicate Start_Osc Event has been processed in sequence

identifier.
EXPLANATION:
A Start_Osc event has been processed which overlays a preceding Start_Osc
without an intervening Stop_Osc. Processing continues, but the initial Start_Osc data
has been overwritten.
USER RESPONSE:
Ensure that the data reflects your intent. If not, correct and reimport the patterns.
INFO (TIM-811): Sequence Definition name is an empty sequence. An empty

Sequence_Definition contains no vector data. Ensure that the Sequence_Definition reflects
your intent. If not, correct and rerun read_sequence_definition.
EXPLANATION:
The named sequence definition is empty. An empty sequence definition contains no
pattern data.
USER RESPONSE:
Ensure that the Sequence_Definition reflects your intent. If not, correct and rerun
INFO (TIM-812): value is not a supported default value for eventType. A default value
of value will be used. Compressed_Input_Stream and
Skewed_Compressed_Input_Stream event types do not support default values of
scan_0 and scan_1. The default values of 1 and 0 have been substituted.
EXPLANATION:
Compressed_Input_Stream and Skewed_Compressed_Input_Stream event
types do not support default values of scan_0 and scan_1. The default values of 1 and
0 have been substituted. Processing continues.
USER RESPONSE:
INFO (TIM-813): application completed syntax checking of file filename. Syntax

errors string found. If no syntax errors were found remove syntaxonly=yes from the
command line and rerun. If syntax errors were found, corrent them and rerun.
EXPLANATION:

The keyword option syntaxonly=yes was specified on the command line. Syntax
check of the input file is completed and processing ends.
USER RESPONSE:
Correct the identified syntax errors and rerun. Continue until all syntax errors have been
found and resolved and then remove syntaxonly=yes from the command line and
rerun to import the file.
ERROR (TIM-814): A repeat count of count was specified for Repeat event odometer.
Repeat counts larger then 4,294,967,295 are not supported by Encounter Test. If a repeat
count of greater than 4,294,962,295 is required, use multiple loops or nested loops to achieve
the desired result and then rerun read_vectors.
EXPLANATION:
Repeat counts larger then 4,294,962,295 are not supported.
USER RESPONSE:
If a repeat count of greater than 4,294,962,295 is required, use multiple loops or nested
loops to achieve the desired result and then rerun read_vectors.
ERROR (TIM-815): A Compact_Scan_Load event was found within the modeinit

Sequence_Definition. Compact_Scan_Load events are not supported for use in
Sequence_Definitions with a type of modeinit. Replace the Compact_Scan_Load
event with a Scan_Load event and rerun build_testmode.
EXPLANATION:
Compact_Scan_Load events are not supported for use in Sequence_Definitions
with a type of modeinit.
USER RESPONSE:
Replace the Compact_Scan_Load event with a Scan_Load event and rerun
build_testmode.
WARNING (TIM-816): The keyword value maxpatternloops=count was specified for

read_vectors. Pattern loops greater then 4294967295 are not supported by Encounter
Test. The value for maxpatternloops will be set to 4294967295
EXPLANATION:
Pattern loop counts greater then 4,294,967,295 are not supported by Encounter Test.
Any pattern loops containing a repeat count greater then 4,294,967,295 will be broken
into multiple pattern loops.

USER RESPONSE:
If a repeat count of greater then 4,294,967,295 is required, use multiple loops or nested
loops to achieve the desired result, and then rerun read_vectors.
WARNING (TIM-817): A repeat count of count was specified for a Repeat event in
Sequence Definition sequencename. The read_vectors command will break this
pattern loop into multiple loops based on the maxpatternloops setting of
patternloops.
EXPLANATION:
The Repeat count specified within the indicated Sequence Definition is greater then the
value specified for the maxpatternloops keyword. The read_vectors command will
automatically break the indicated loop into multiple loops such that the
maxpatternloops value is not exceeded by any loop. This is purely a structural
translation which should be value in the general case.
USER RESPONSE:
If this translation is unacceptable, modify the input patterns and/or the
maxpatternloops count and then rerun read_vectors.
ERROR (TIM-818): default_value=random was specified on one or more

eventename events. default_value=random is only supported for event types
Compact_Scan_Load and Compressed_Input_Stream. Either remove
default_value=random from the event or change the event type being specified.
EXPLANATION:
A default value of random is only supported for Compact_Scan_Load and
Compressed_Input_Stream events types . This attribute was specified on another
event type.
USER RESPONSE:
Either change the event type or the default_value specification and then rerun.
ERROR (TIM-999): [Internal] Internal Program Error occurred in file:fileName line:

lineNumber. errorString. Contact Cadence Support for assistance.
EXPLANATION:
USER RESPONSE:

assistance.

41
TIS - Import STIL Messages
TIS-001 through TIS-052 on page 1299

TIS-001 through TIS-052

ERROR (TIS-001): The STIL parser discovered a parse_error processing token token
on line line_number of file file.
EXPLANATION:
Syntax errors have been detected while parsing the STIL data and have terminated the
command.
USER RESPONSE:
Correct the syntax errors and rerun the command.
ERROR (TIS-002): Unable to Process STIL Version: VersionStr. Processing ends.

EXPLANATION:
The STIL Version level is not compatible with the currently supported version. The
currently supported version is 1.0.
USER RESPONSE:
Rebuild the STIL data file using the supported version and then rerun the command.
ERROR (TIS-003): Unable to the determine STIL Version. Processing ends.

EXPLANATION:

The application could not find the STIL version information at the top of the STIL file. This
disables verification of the the syntax of the input data and terminates the program.
USER RESPONSE:
Ensure that the STIL file being read is in the correct format. If so, ensure that a valid
Version statement exists in that file to identify the STIL version of the data. Resolve
problems and then rerun.
ERROR (TIS-004): Unable to open the STIL file. Processing ends

EXPLANATION:
The command was unable to open the file specified with the importfile keyword and
then terminated.
USER RESPONSE:
Ensure the file specified with the importfile keyword exists and is readable, and then
rerun.
ERROR (TIS-005): [Internal] Unable to handle the number of nested file includes.
EXPLANATION:
The Encounter Test STIL parser keeps track of the included file context while it is parsing
by using an included file stack. The depth of the included file context required to parse
this STIL data exceeds the capacity of the context stack. The STIL parser will terminate.
USER RESPONSE:
Contact customer support (see Contacting Customer Service on page 23). To work
around the problem, reduce the depth of included files in the STIL data and rerun the
command.
ERROR (TIS-006): [Internal] Attempted to end more include files than were started.
Processing ends.
EXPLANATION:
A program error has occurred and has caused an abnormal termination.
USER RESPONSE:
ERROR (TIS-007): [Internal] Invalid signal signal with waveform character \\0 in
waveform table wave_form_table in timing domain timing_domain.

EXPLANATION:
A null wave form character was passed into the utility which translates wave form
characters into actions. A null action will be returned, and processing will continue, but
the results are suspect.
USER RESPONSE:
ERROR (TIS-008): The STIL data does not contain a timing domain. Processing ends.
EXPLANATION:
There is no timing domain in the input STIL data. At least one Timing block is required in
STIL data.
USER RESPONSE:
Ensure that at least one timing domain exists in the input STIL data and then rerun.
ERROR (TIS-009): [Internal] Exceeded maximum token length

(maximum_token_length) at file_line.
EXPLANATION:
A token appears in STIL which is larger than the maximum token size supported by
Encounter Test as specified in the message. Encounter Test will truncate the token to the
specified length.
USER RESPONSE:
Check the input STIL to determine if such an extraordinarily long token is required. If so,
contact customer support (see Contacting Customer Service on page 23) to increase
the current maximum.
ERROR (TIS-010): Unable to load Encounter Test correlation data. Processing ends.
EXPLANATION:
The model utility was unable to load the correlation data causing an abnormal
termination.
USER RESPONSE:
Check for previous TLM messages. Resolve the problems identified in those messages
and rerun.

ERROR (TIS-011): Scan macro symbol symbol from scan macro definition at
file_line does not appear as a signal or signal group. Processing ends.
EXPLANATION:
A symbol appeared within the shift block of a scan macro, but that symbol is not defined
in the rest of the STIL data. Specifically, the symbol is not defined in either the signal
definitions nor the signal group block. Since the scan macro will not be successful, the
conversion terminates.
USER RESPONSE:
Ensure that the signal referenced in the scan macro is defined as either a signal or a
signal group and then rerun.
ERROR (TIS-012): [Internal] Unable to add a new event to test pattern

sequence_odometer. Processing ends
EXPLANATION:
A new event is required to accommodate the specified action, but it is not known what
kind of event is required to accomplish that action. The event will be ignored.
USER RESPONSE:
ERROR (TIS-013): Unable to add a new event to test pattern pattern_odometer.

EXPLANATION:
The TBD method to add a new event to the specified pattern resulted in an error.
USER RESPONSE:
Check for previous TBD messages for more information. Resolve the problems identified
in those messages and rerun.
ERROR (TIS-014): Unable to add a new test pattern to test sequence

sequence_odometer. Processing ends.
EXPLANATION:
The test pattern data method to add a new pattern to the specified sequence resulted in
an error.
USER RESPONSE:

ERROR (TIS-015): Unable to add a new test sequence to test procedure

procedure_odometer. Processing ends.
EXPLANATION:
The test pattern data method to add a new sequence to the specified procedure resulted
in an error.
USER RESPONSE:
ERROR (TIS-016): Unable to add a new test procedure to tester loop

tester_loop_odometer. Processing ends.
EXPLANATION:
The test pattern data method to add a new procedure to the specified loop resulted in an
error.
USER RESPONSE:
ERROR (TIS-017): Unable to add a new tester loop to test section

test_section_odometer. Processing ends.
EXPLANATION:
The test pattern data method to add a new loop to the specified section resulted in an
error.
USER RESPONSE:
ERROR (TIS-018): [Internal] Unable to add a test section type attribute to test section
test_section_odometer.
EXPLANATION:
The TBD method to add a test section type to the specified section resulted in an error.
USER RESPONSE:
Check for previous TBD messages for more information.

ERROR (TIS-019): [Internal] Unable to set termination domination attribute on test section
EXPLANATION:
The TBD method to set termination domination on the specified section resulted in an
error.
USER RESPONSE:
ERROR (TIS-020): [Internal] Unable to set termination on test section

EXPLANATION:
The TBD method to set termination on the specified section resulted in an error.
USER RESPONSE:
ERROR (TIS-021): Unable to add a new test section to experiment

experiment_odometer. Processing ends.
EXPLANATION:
The test pattern data method to add a new section to the specified experiment resulted
in an error.
USER RESPONSE:
ERROR (TIS-022): Unable to save registration information. Processing ends.

EXPLANATION:
The global data methods successfully updated the information on registration of this
experiment, but could not save the information to disk.
USER RESPONSE:
Check for previous TFW messages. Resolve the problems identified in those messages
and rerun.
ERROR (TIS-023): Unable to register a dependency of experiment experiment_name

on testmode testmode. Processing ends.

EXPLANATION:
Registration of the specified experiment requires creating a dependency on the specified
test mode, but the global data routines to create that dependency returned an error.
USER RESPONSE:
and rerun.
ERROR (TIS-024): Unable to register experiment experiment_name. Processing ends.

EXPLANATION:
The global data routines to register the specified experiment returned an error.
USER RESPONSE:
and rerun.
ERROR (TIS-025): Unable to set experiment name experiment_name in new

experiment.
EXPLANATION:
The TBD methods to add the specified experiment name to the experiment were
unsuccessful.
USER RESPONSE:
Check for previous TBD messages.
ERROR (TIS-026): [Internal] Unable to add an experiment hierarchy to the uncommitted

Vectors file.
EXPLANATION:
The TBD methods to add an experiment name to the uncommitted Vectors file were
unsuccessful.
USER RESPONSE:
ERROR (TIS-027): Unable to open the experimental TBDbin file for writing.
EXPLANATION:

The methods to create the experimental TBDbin file and open it for writing were
unsuccessful.
USER RESPONSE:
Check for previous TBD messages, resolve problems, and then rerun.
ERROR (TIS-028): [Internal] Unable to create the in-core version of the output Vectors file.
EXPLANATION:
The TBD methods to open the Vectors repository were unsuccessful.
USER RESPONSE:
ERROR (TIS-029): Experiment experiment_name already exists and the replace

keyword is set to no.
EXPLANATION:
experiment name specified on the EXPERIMENT keyword already exists, and the
replace keyword value was specified or defaulted to no.
USER RESPONSE:
Either remove the previous experiment, or specify a different experiment name in the
EXPERIMENT parameter, or use the keyword replace=yes.
ERROR (TIS-030): [Internal] Unable to load test mode scan information.

EXPLANATION:
Attempted to load latch table information, but TLMloadMethod returned an error return
code.
USER RESPONSE:
Check for previous TLM messages.
ERROR (TIS-031): The vector statement at file_line referenced a wave form character
of wave_form_character outside of a shift block.
EXPLANATION:
The wave form character % only makes sense in STIL inside of a shift block. However, a
reference to the % character occurs outside a shift block.
USER RESPONSE:

Correct the input STIL data.
ERROR (TIS-033): Goto label of label specified at file_line was not found.
EXPLANATION:
The specified goto statement references a label which does not exist in the STIL data.
USER RESPONSE:
WARNING (TIS-034): [Severe] Unable to find pattern block with id pattern_block_id.

EXPLANATION:
A reference to an internal pattern block id could not be found in the parsed STIL
database.
USER RESPONSE:
ERROR (TIS-035): [Internal] Unsupported pattern entry type of pattern_entry_type

found at file_line.
EXPLANATION:
A pattern entry which is not currently supported was found on the specified file/line. This
construct will be ignored.
USER RESPONSE:
ERROR (TIS-036): [Internal] Slot tables already allocated on call to TISprocessWFTs.

EXPLANATION:
TISprocessWFTs should only be called once without an intervening TISfreeSlotTables.
USER RESPONSE:
ERROR (TIS-037): The output assign file: fileName already exists and replace keyword
is set to no.
EXPLANATION:
The assign file name specified on the assignfile keyword already exists. The replace

value was specified or defaulted to no that prevents replacing the existing files.
USER RESPONSE:
Perform one of the following actions:
Remove the previous file.
Specify a different file name in the assignfile parameter
Specify replace=yes.
ERROR (TIS-038): The output seqdef file: fileName already exists and replace keyword
is set to no.
EXPLANATION:
The seqpatt file name specified on the seqdef keyword already exists. The replace
value was specified or defaulted to no that prevents replacing the existing files.
USER RESPONSE:
Perform one of the following actions:
Remove the previous file.
Specify a different file name in the seqdef parameter
Specify replace=yes.
ERROR (TIS-039): The output directory: out_directory cannot be created.

EXPLANATION:
The program detected that the reference output directory does not exist and
unsuccessfully attempted to create it.
USER RESPONSE:
Check permissions and system space values, then retry.
ERROR (TIS-040): Problem writing file fileName. System reason is sysReason.

EXPLANATION:
An attempt to write the file failed.
USER RESPONSE:
Refer to the system reason for reason for the failure. Correct and rerun.

ERROR (TIS-041): Problem closing file fileName. System reason is sysReason.

EXPLANATION:
An attempt to close the file failed.
USER RESPONSE:
Refer to the system reason for reason for the failure. Correct and rerun.
ERROR (TIS-042): The name of the assign file to write the test mode definition is not
specified.
EXPLANATION:
The assignfile keyword was not specified to set the assign file name, to write the test
mode definition
USER RESPONSE:
Rerun the application, specifying a value for assignfile.
ERROR (TIS-043): Writing the TBD Sequence Pattern file failed.

EXPLANATION:
An attempt to write the Sequence Pattern file failed.
USER RESPONSE:
Refer to previous messages for error details. Correct and rerun.
ERROR (TIS-044): Writing the Assign file failed.

EXPLANATION:
An attempt to write the assignfile failed.
USER RESPONSE:
Refer to previous messages for error details. Correct and rerun.
ERROR (TIS-045): Unable to set the pattern context for a generic test sequence as there
are multiple pattern exec blocks.
EXPLANATION:
The application is attempting to determine the correct context for a generic test
sequence. Since the context depends on the attributes in a STIL pattern exec block, and

there are more than one pattern exec block in the input STIL data, the application could
not determine the pattern exec block that specified the correct context
USER RESPONSE:
Correct the input STIL data and rerun the application.
ERROR (TIS-046): Application applName cannot be run because the input STIL file:
fileName contains the user-defined keyword SignalNameForm set to a value of
something other than Pin.
EXPLANATION:
The STIL file contains a user-defined keyword that prohibits the application from running
because it requires an Encounter Test model. The application has not loaded the
USER RESPONSE:
Remove the user-defined keyword in the STIL file or change it to the value of Pin, then
rerun.
ERROR (TIS-047): Unable to Process STIL extension: extension_name. Currently

extensions Design, TRC and CTL are supported. Rebuild the STIL data file at a extension
level compatible with the program.
EXPLANATION:
The referenced STIL extension is not currently supported.
USER RESPONSE:
Rebuild the STIL data file at a compatible extension level. Currently supported
extensions are Design, TRC and CTL.
ERROR (TIS-048): The STIL macro_or_procedure macro_or_procedure_name

in macro_or_procedure_domain macro_or_procedure_domain_name
contains a SHIFT block, but it is impossible to determine the time in the cycle at which the
scan load and/or scan unload occur. Therefore, the scan protocols associated with this
macro_or_procedure cannot be automatically created.
EXPLANATION:
It was impossible to determine from the waveform table the waveforms that would be
applied to the scan in or scan out pins referenced in the SHIFT block of the specified
macro or procedure. Therefore, the program was unable to determine the relative timing
of scan in stimulus versus clock pulse versus scan out measures. Since this basic scan
protocol information cannot be derived from the STIL data, the referenced macro or

procedure cannot be used to create test mode scan protocol information in the form of
custom scan sequences. In this situation, scan sequences will be automatically created
by Encounter Test.
USER RESPONSE:
Check the scan sequences created automatically, or from other scan macros or
procedures after the test mode is built. If these scan sequences implement the desired
scan protocol, no further action is required. If not, ensure that the symbols referenced by
the vector statements in the SHIFT block of this macro or procedure have associated
stim or measure waveform characters defined in the waveform table used by this macro.
WARNING (TIS-049): Macro or Procedure macro_name in domain macro_domain

contains a shift block with a shift length is zero. The shiftlength will be set to one. During
build_testmode the shift length will be computed and the repeat count of the scan
Sequence_Definition will be reset to the correct length. This macro or procedure is defined
at file_line.
EXPLANATION:
The shift length was not specified in the macro or procedure that contains the shift block.
The repeat count of the scan Sequence_Definition will be set to one. During
build_testmode the repeat count will be set to the length of the longest control or
observe register.
USER RESPONSE:
If a length is longer than the length of the longest control or observe register is required
update the input STIL data to include the required length and re-import the STIL data.
ERROR (TIS-050): The sequence definition file seqdef filename for testmode
testmode does not have a mode initialization sequence.
EXPLANATION:
The TBDseqPatt file of the specified testmode does not have a mode initialization
sequence.
USER RESPONSE:
Check for errors from build_testmode, and rebuild the test mode to ensure that a
mode initialization sequence has been created for that test mode, and then rerun
read_vectors.
WARNING (TIS-051): [Severe] The STIL file does not have a proper Timing Table defined,
reason.
EXPLANATION:

No wave definitions were found in the Timing Table in the provided STIL file.
USER RESPONSE:
Validate timing data exists. If no data is meant to exist remove stiltimings=yes from
the command invocation.
WARNING (TIS-052): [Severe] The TIStimingData.testmode file was not be created.

EXPLANATION:
An previous problem was found that is preventing ET from creating the TIStimingData
file.
USER RESPONSE:
Check previous messages and correct any issues.

WARNING (TIS-400): Unrecognized time format: time_expr.
EXPLANATION:
The specified time format appeared in the STIL data, but was not recognizable as a valid
time format. A value of 0 will be used in place of the specified value.
USER RESPONSE:
Check for further messages which may better identify the source of the problem, Then,
fix the problem in the input STIL data.
WARNING (TIS-401): Invalid time units for period for timing domain timing_domain,
wave form table inherited_wave_form_table_name at file_line.
EXPLANATION:
The specified time expression for the period was not recognizable as a valid STIL time
format. A period of 0 will be used in place of the specified value.
USER RESPONSE:
No response is required, since the period value is not used in converting the STIL data
to a Encounter Test format. However, other tools may require a valid period, so it is
recommended that the value be fixed.
WARNING (TIS-402): [Severe] Unable to find inherited wave form

inherited_wave_form_table_name referenced at file_line.

EXPLANATION:
A reference to an inherited wave form table appears at the file and line number specified
in the message, but the specified wave form table could not be found. The reference to
this table will be ignored.
USER RESPONSE:
Fix the input STIL data to ensure that each wave form table referenced exists in the data.
WARNING (TIS-403): No wave form characters were defined for the wave at file_line
in wave form table wave_form_table in timing domain timing_domain.
EXPLANATION:
A wave definition appeared in the specified wave form table, but no wave form characters
are associated with that wave.
USER RESPONSE:
If the wave should be used, fix the input STIL data to ensure that valid wave form
characters are associated with the specified wave definition.
WARNING (TIS-404): No sigref_expr defined for the wave at file_line in wave form
table wave_form_table in timing domain timing_domain.
EXPLANATION:
A wave definition appeared in the specified wave form table, but no sigref_expr is
associated with that wave.
USER RESPONSE:
If the wave should be used, fix the input STIL data to ensure that a valid sigref_expr is
associated with the specified wave definition.
WARNING (TIS-405): [Severe] Unable to find wave definition for sigref_expr

sigref_expr and wave form character wave_form_character in wave form table
wave_form_table in timing domain timing_domain.
EXPLANATION:
A reference was found to the specified wave form character associated with the specified
sigref_expr, but the specified combination does not appear in the associated wave
form table. The wave form character will be treated as a no-op for the purposes of
translation.
USER RESPONSE:

Fix the input STIL data to ensure that each sigref_expr and wave form character
combination is specified in the referenced wave form table.
WARNING (TIS-406): Attempting to define a pulse for sigref_expr clock_sigref_expr

in timing domain timing_domain wave form table wave_form_table defined at
file_line. Conflicts with stim to event_action_character for sigref_expr
conflicting_sigref_expr at time time. Encounter Test will not support
simultaneous stims and pulses
EXPLANATION:
The Encounter Test STIL translator attempts to infer pulses from waves which contain
either stim up, stim down, stim up; or stim down, stim up stim down, all in the same tester
cycle. Such a wave form has been identified, and will be treated as a pulse, but,
according to the STIL wave form table, another pin can be stimmed at the same time the
pulse is occurring. Such simultaneous actions cannot be represented in Encounter Test
pattern data. Processing will continue, but it is assumed that the pulse will not occur at
the same time as the stim.
USER RESPONSE:
This message can be ignored if both the pulse and the stim are never invoked in the
same vector. If the pulse and the vector are not required to occur simultaneously, the
message can also be ignored. However, if the pulse and the stim must happen
simultaneously for the correct results to occur, the pattern will not simulate correctly in
the Encounter Test pattern data.
WARNING (TIS-407): Wave Form Table wave_form_table in timing domain

timing_domain at file_line contains an event within a potential clock pulse at time
time. Clocks will be stimmed.
EXPLANATION:
The Encounter Test STIL translator attempts to infer pulses from waves which contain
either stim up, stim down, stim up; or stim down, stim up stim down, all in the same tester
cycle. Such a wave form has been identified, but cannot be treated as a pulse because,
according to the STIL wave form table, another pin can be stimmed when the pulse is
occurring. A pulse will not be created. Instead, the clock in question will be stimmed on
and off to allow intervening events within the pulse.
USER RESPONSE:
No response is required, but the Encounter Test pattern data will not be simulated as
efficiently as it would otherwise. Check the specified wave form table to ensure that
overlapping pulses and stims are required. If not, edit the input STIL data to remove this
condition.

WARNING (TIS-408): [Severe] Unable to find wave form table wave_form_table for
timing domain timing_domain referenced from file_line.
EXPLANATION:
A wave form table was referenced in the STIL pattern data, but the specified wave form
table does not appear in the STIL data. All subsequent pattern entries will be ignored
until a new wave form table reference appears.
USER RESPONSE:
Ensure that the specified wave form table appears in the input STIL data.
WARNING (TIS-409): [Severe] Unable to find signal signal with wave form character
wave_form_character in wave form table wave_form_table in timing domain
timing_domain.
EXPLANATION:
A vector or condition statement in the STIL patterns referenced the specified signal and
wave form character, but the signal and wave form character did not appear in the
specified wave form table. This event will be treated as a no-op.
USER RESPONSE:
Ensure that the specified signal and wave form character appears in the specified wave
form table in the input STIL data.
WARNING (TIS-410): Signal signal identified as a scan in pin in the scan structures block
at file_line has a direction of pin_direction
EXPLANATION:
The input STIL data indicates that the specified pin is a scan in the scan structures block,
but the signals block indicates that the pin is not an input pin. This will not affect
translation to Encounter Test patterns, but represents a conflict within the STIL data.
USER RESPONSE:
No response is required, but it is recommended that this problem gets fixed in the STIL
data.
WARNING (TIS-411): [Severe] Wave Form Table not specified in pattern data.
EXPLANATION:
Vector data occurred in the STIL pattern data before a wave form table was specified. In
this case, Encounter Test attempts to find the first valid wave form table.

USER RESPONSE:
Ensure that a wave form table has been specified before any Vectors data in the input
STIL patterns. Check the subsequent Encounter Test messages to determine which
wave form table Encounter Test will use by default.
WARNING (TIS-412): Signal signal identified as a scan in pin in the scan structures block
at file_line does not appear in the signals block.
EXPLANATION:
The input STIL data indicates that the specified signal is a scan in the scan structures
block, but the signal does not appear in the signals block. This will not affect translation
to Encounter Test patterns, but represents a conflict within the STIL data.
USER RESPONSE:
data.
WARNING (TIS-413): [Severe] No wave form tables exist for timing domain
timing_domain.
EXPLANATION:
The specified timing domain contains no wave form tables.
USER RESPONSE:
Ensure that the specified timing domain contains at least one wave form table in the input
STIL data.
WARNING (TIS-414): [Severe] Using wave form table wave_form_table1 from timing
domain timing_domain.
EXPLANATION:
Vector data occurred in the STIL pattern data before a wave form table was specified.
This message indicates the default wave form table that Encounter Test will use.
USER RESPONSE:
Ensure that a wave form table is specified in the pattern data before any Vectors data
occurs.
WARNING (TIS-415): Scan chain length from scan attribute in signal block,
signal_block_scan_length, does not match scan chain length from the scan
structures block at file_line2: scan_structures_scan_length.

EXPLANATION:
The scan length was specified in both the signal block and the scan structures block, but
the scan length did not agree. Encounter Test will use the scan length specified in the
scan structures block.
USER RESPONSE:
data.
WARNING (TIS-416): Signal signal identified as a scan out pin in the scan structures
block at file_line has a direction of pin_direction.
EXPLANATION:
The input STIL data indicates that the specified pin is a scan out in the scan structures
block, but the signals block indicates that the pin is not an output pin. This will not affect
translation to Encounter Test patterns, but represents a conflict within the STIL data.
USER RESPONSE:
data.
WARNING (TIS-417): Signal signal identified as a scan out pin in the scan structures
block at file_line does not appear in the signals block.
EXPLANATION:
The input STIL data indicates that the specified signal is a scan out in the scan structures
block, but the signal does not appear in the signals block. This will not affect translation
to Encounter Test patterns, but represents a conflict within the STIL data.
USER RESPONSE:
data.
WARNING (TIS-418): [Severe] Unable to determine scan load timing for macro macro in
macro domain macro_domain.
EXPLANATION:
During preprocessing of scan macros, it was impossible to determine when a scan load
occurs within the test cycle. Encounter Test will assume the scan load occurs at time 0.
USER RESPONSE:

Ensure that the input STIL contains references to the specified macro with scan vectors
that point to a valid wave form table from which the scan load timings can be derived.
WARNING (TIS-419): [Severe] Unable to determine scan unload timing for macro macro
in macro domain macro_domain.
EXPLANATION:
During preprocessing of scan macros, it was impossible to determine when a scan
unload occurs within the test cycle. Encounter Test will assume the scan unload occurs
at time 0.
USER RESPONSE:
Ensure that the input STIL contains references to the specified macro with scan vectors
that point to a valid wave form table from which the scan unload timings can be derived.
WARNING (TIS-420): [Severe] Unable to determine which wave form table should be used
when processing macro macro defined at file_line.
EXPLANATION:
It was impossible to determine which wave form table was in effect when the specified
macro was invoked. Encounter Test will choose a default wave form table.
USER RESPONSE:
Ensure that a wave form table has been specified before the specified macro is used.
WARNING (TIS-421): [Severe] Scan load occurs in multiple time slots (slot_1 and
slot_2) within a cycle. Encounter Test will only honor one.
EXPLANATION:
While preprocessing references to the specified scan macro or procedure, a scan load
occurs at more than one time during a test cycle.
Encounter Test can only support scan loads which all occur at the same time in the tester
cycle. Encounter Test will assume all scan loads occur in the first time slot for this scan
macro or procedure.
USER RESPONSE:
Check the scan wave form characters specified in the usages of the specified scan
macro or procedure, and ensure these wave form characters cause the scan load to
occur at only a single time during the test cycle.
WARNING (TIS-422): [Severe] Scan unload occurs in multiple time slots (slot_1 and
slot_2) within a cycle. Encounter Test will only honor one.

EXPLANATION:
While preprocessing references to the specified scan macro or procedure, a scan unload
occurs at more than one time during a test cycle. Encounter Test can only support scan
unloads which all occur at the same time in the tester cycle. Encounter Test will assume
all scan unloads occur in the first time slot for this scan macro or procedure.
USER RESPONSE:
Check the scan wave form characters specified in the usages of the specified scan
macro or procedure, and ensure these wave form characters cause the scan unload to
occur at only a single time during the test cycle.
WARNING (TIS-423): [Severe] Too many levels of included file nesting. Only 16 levels
supported.
EXPLANATION:
The STIL file pointed to by the importfile parameter contains an include which points to
a lower level file, which, in turn also contains an include, and so on, until the number of
levels of included file exceeds the capacity of the Encounter Test STIL importer.
USER RESPONSE:
Either reduce the number of levels of included files, or contact customer support (see
Contacting Customer Service on page 23) to increase the levels of supported include
files.
WARNING (TIS-424): [Severe] Unable to open file filename.

EXPLANATION:
Encounter Test was unable to open the specified file, which is either the file specified by
the importfile keyword, or one of the files included by that file. The contents of the
specified file will not be parsed.
USER RESPONSE:
Check the file to see if it is present and readable.
WARNING (TIS-425): [Severe] Unable to include file with empty file name at file_line.
EXPLANATION:
An include was specified with an blank specification of the file to include. Nothing will be
included.
USER RESPONSE:

WARNING (TIS-426): [Severe] No active time slots found in current wave form table at
file_line.
EXPLANATION:
Either a wave form table was not specified, or the wave form table that was specified had
no valid actions specified. In either case, the pattern data at the specified file and line
number will not be processed.
USER RESPONSE:
Ensure that a wave form table has been specified (check previous messages), and
ensure that the wave form table has legal actions at valid times.
WARNING (TIS-427): Wave form table wave_form_table in timing domain

timing_domain does not define an action for sigref_expr sigref_expr position
position.
EXPLANATION:
Attempted to get an action for the specified sigref_expr and position, but the specified
wave form table does not define that position. A null action will be returned.
USER RESPONSE:
Determine why such a position is being requested in the STIL data for the specified
sigref_expr, and change the STIL data either to not reference that position, or define
that position in the wave form table.
WARNING (TIS-428): Unable to find signal signal in the Encounter Test model.
EXPLANATION:
The specified signal was specified as an input or output pin in the STIL data, but the pin
does not appear in the associated Encounter Test model. Values for this pin will be
ignored.
USER RESPONSE:
Determine why the pin either appears in the STIL data and should not, or does not
appear in the Encounter Test model, and should. Fix either the Encounter Test model or
the STIL data.
WARNING (TIS-429): [Severe] Unable to determine scan direction for scan signal
signal.
EXPLANATION:

The specified symbol appears as a scan signal in a shift block of a macro definition, but
did not appear in the scan structure block. It is unclear if this pin should be a scan-in pin
or a scan-out pin.
USER RESPONSE:
Correct either the shift macro definition or the scan structures block in the input STIL so
that each scan signal is identified as either a scan-in or a scan-out.
WARNING (TIS-430): [Severe] Unable to find a stim register in the Encounter Test model
for scan-in signal signal.
EXPLANATION:
A scan-in pin associated with a scan macro in the STIL data does not map to a scan-in
pin in the Encounter Test model. The controllable register associated with this scan in pin
will not appear in the Encounter Test patterns.
USER RESPONSE:
Determine why the scan-in pin is incorrect either in the Encounter Test model or in the
STIL data. Correct either the Encounter Test model or the STIL data.
WARNING (TIS-431): [Severe] Unable to find a measure register in the Encounter Test
model for scan-out signal signal.
EXPLANATION:
A scan-out pin associated with a scan macro in the STIL data does not map to a scan-
out pin in the Encounter Test model. The measure register associated with this scan out
pin will not appear in the Encounter Test patterns.
USER RESPONSE:
Determine why the scan-out pin is incorrect either in the Encounter Test model or in the
STIL data. Correct either the Encounter Test model or the STIL data.
WARNING (TIS-432): [Severe] Unable to map stim bit stim_bit of scan chain with scan
in scan_in_pin to a Encounter Test scan latch from scan macro reference at
file_line.
EXPLANATION:
The STIL data requested a stim of the specified bit in the specified controllable scan
chain, but Encounter Test does not know how to access that bit in the scan chain. The
specified stim will not occur, and invalid results are possible.
USER RESPONSE:

Determine why the specified bit is uncontrollable in Encounter Test and either remove
that stim from the STIL data, or change the Encounter Test model to make that bit
controllable.
WARNING (TIS-433): [Severe] Unable to map measure bit measure_bit of scan chain
with scan out scan_out_pin to a Encounter Test scan latch from scan macro reference at
file_line.
EXPLANATION:
The STIL data requested a measure of the specified bit in the specified measurable scan
specified measure will not occur, and invalid results are possible.
USER RESPONSE:
Determine why the specified bit is immeasurable in Encounter Test and either remove
that measure from the STIL data, or change the Encounter Test model to make that bit
measurable.
WARNING (TIS-434): [Severe] Invalid time units for wave form at file_line.
EXPLANATION:
The specified time expression for the period was not recognizable as a valid STIL time
format. A time of 0 will be used in place of the correct value.
USER RESPONSE:
Determine the problem with the time format and correct the input STIL data. Since the
default time value of 0 will be used for this action, the resulting Encounter Test patterns
will most probably be incorrect.
WARNING (TIS-435): [Severe] Unable to set event type of event_type for event
event_odometer.
EXPLANATION:
Attempted to set an event type for this event, but got an error return code from the TBD
set event type method. This event will be ignored.
USER RESPONSE:
WARNING (TIS-436): Condition statement will be ignored in scan macro reference from
file_line.
EXPLANATION:

A condition statement was encountered in a reference to a scan macro. The STIL

standard allows for such a construct, but it does not make sense. The values in the
condition statement will be ignored.
USER RESPONSE:
If the values in the condition statement are important, it should be changed to a STIL
vector statement. Otherwise, this message can be ignored.
WARNING (TIS-437): [Severe] Reference to undefined macro macro_name in macro

domain macro_domain from file_line will be ignored.
EXPLANATION:
The specified macro reference refers to a macro which has not been defined in the STIL
data. The macro reference will be ignored.
USER RESPONSE:
Modify the input STIL data to either remove the reference to the undefined macro, or
define the macro.
WARNING (TIS-438): Conflicting termination values discovered. Global termination is

turned off.
EXPLANATION:
At least two different signals were terminated to different values per the input STIL data.
Since Encounter Test only supports termination of all pins to the same value, it is
impossible to represent this conflicting termination information in the Encounter Test
patterns. Therefore, the Encounter Test patterns will be treated as if no termination were
present.
USER RESPONSE:
No response is required. Turning off termination may cause pessimistic results and lower
fault coverage, but should still work correctly. If termination is important, analyze the input
STIL data to determine and resolve the termination conflict.
WARNING (TIS-439): [Severe] More symbols than wave form characters from wave form
at file_line.
EXPLANATION:
A wave form exists where the number of wave form characters specified is larger than
the number of signals to which those characters should be assigned. The result is that
only those wave form characters which correspond to valid symbols will be assigned. The
rest of the wave form characters will be ignored.

USER RESPONSE:
WARNING (TIS-440): [Severe] Invalid hex digit digit at position position in string
string.
EXPLANATION:
Attempting to convert hex to a bit string while processing wave form characters, but one
of the hex digits is not valid (e.g. 0-9, A-F). The converter will treat this as a hex 0.
USER RESPONSE:
WARNING (TIS-441): [Severe] Too many levels of included file nesting. Only 16 levels
supported.
EXPLANATION:
The STIL file pointed to by the importfile parameter contains an include which points to
a lower level file, which in turn also contains an include, and so on, until the number of
levels of included file exceeds the capacity of the Encounter Test STIL importer.
USER RESPONSE:
Either reduce the number of levels of included files, or contact customer support to
increase the levels of include files supported.
WARNING (TIS-442): [Severe] Unable to open file fileName.

EXPLANATION:
Encounter Test was unable to open the specified file, which is either the file specified by
the importfile keyword, or one of the files included by that file. The contents of the
specified file will not be parsed.
USER RESPONSE:
Ensure that the file is present and readable.
WARNING (TIS-443): [Severe] Unabl8e to include file with empty file name at
file_line.
EXPLANATION:
An include was specified with a blank specification of the file. Nothing will be included.
USER RESPONSE:

WARNING (TIS-444): [Severe] Unable to determine scan unload timing for procedure
procedure in procedure domain procedure_domain.
EXPLANATION:
During preprocessing of scan procedures, it was impossible to determine when a scan
unload occurs within the test cycle. Encounter Test will assume the scan unload occurs
at time 0.
USER RESPONSE:
Ensure that the input STIL contains references to the specified procedure with scan
vectors that point to a valid wave form table from which the scan unload timings can be
derived.
WARNING (TIS-445): [Severe] Unable to determine which wave form table should be used
when processing procedure procedure defined at file_line.
EXPLANATION:
It was impossible to determine which wave form table was in effect when the specified
procedure was invoked. Encounter Test will choose a default wave form table.
USER RESPONSE:
Ensure that a wave form table has been specified before the specified procedure is used.
WARNING (TIS-446): [Severe] Reference to undefined procedure procedure_name in

procedure domain procedure_domain from file_line will be ignored.
EXPLANATION:
The specified procedure reference refers to a procedure which has not been defined in
the STIL data. The procedure reference will be ignored.
USER RESPONSE:
Modify the input STIL data to either remove the reference to the undefined procedure, or
define the procedure.
WARNING (TIS-447): Condition statement will be ignored in scan procedure reference from
file_line.
EXPLANATION:

A condition statement was encountered in a reference to a scan procedure. The STIL

standard allows for such a construct, but it does not make sense. The values in the
condition statement will be ignored.
USER RESPONSE:
If the values in the condition statement are important, it should be changed to a STIL
vector statement. Otherwise, this message can be ignored.
WARNING (TIS-448): [Severe] Unable to map measure bit measure_bit of scan chain
with scan out scan_out_pin to a Encounter Test scan latch from scan procedure
reference at file_line.
EXPLANATION:
The STIL data requested a measure of the specified bit in the specified measurable scan
specified measure will not occur, and invalid results are possible.
USER RESPONSE:
Determine why the specified bit is immeasurable in Encounter Test and either remove
that measure from the STIL data, or change the Encounter Test model to make that bit
measurable.
WARNING (TIS-449): [Severe] Unable to map stim bit stim_bit of scan chain with scan
in scan_in_pin to a Encounter Test scan latch from scan procedure reference at
file_line.
EXPLANATION:
The STIL data requested a stim of the specified bit in the specified controllable scan
specified stim will not occur, and invalid results are possible.
USER RESPONSE:
Determine why the specified bit is uncontrollable in Encounter Test and either remove
that stim from the STIL data, or change the Encounter Test model to make that bit
controllable.
WARNING (TIS-450): [Severe] Unrecognized character character (hex_value) at

file_line_number.
EXPLANATION:
While parsing the STIL, a character was encountered that was not recognized by the
STIL parser. This character will be ignored.

USER RESPONSE:
Check to ensure that ignoring this character will not affect processing. If the character is
in error, edit the STIL file and remove the character. Otherwise, contact customer support
(see Contacting Customer Service on page 23) to add the character to the list of valid
characters in a STIL file.

WARNING (TIS-451): [Severe] The vector statement at file_line_number
referenced symbol symbol_name which is not a primary input pin.
EXPLANATION:
A vector statement references a symbol that must be pulsed or stimmed, but that signal
is not a primary input pin. The stim or pulse will be ignored.
USER RESPONSE:
Check signal names and signal group names to ensure that every symbol name or
symbol group name which is stimmed or pulsed in this vector statement correlates to a
valid primary input pin.
WARNING (TIS-452): [Severe] The vector statement at file_line_number

referenced symbol symbol_name which is not a primary output pin.
EXPLANATION:
A vector statement references a symbol that must be measured, but that signal is not a
primary output pin. The measure will be ignored.
USER RESPONSE:
Check signal names and signal group names to ensure that every symbol name or
symbol group name which is measured in this vector statement correlates to a valid
primary output pin.
WARNING (TIS-453): KeyedData keyword ignored outside of pattern context on line

line_number of file file.
EXPLANATION:
The KeyedData keyword is only respected by the STIL parser when it appears inside a
pattern block. This instance of the KeyedData keyword appeared outside a pattern block,
and therefore will be ignored.
USER RESPONSE:

If this instance of the KeyedData keyword was present in order to pass information to the
test patterns, move the KeyedData block inside a pattern block. If not, this message can
be ignored.
WARNING (TIS-454): Unsupported KeyedData level token of level_token found at

file_line_number.
EXPLANATION:
The STIL parser only recognizes the following (case-sensitive) level tokens for the
KeyedData keyword:
Experiment
Section
Loop
Procedure
Sequence
Pattern
This usage of KeyedData will be ignored.
USER RESPONSE:
Check the token name to ensure that it matches one of the supported level tokens. Be
sure to check that the case exactly matches the supported level tokens.
WARNING (TIS-455): Ignoring the first offset bits of data specified for scan chain with
scan in scan_in_pin in scan macro reference at file_line.
EXPLANATION:
The STIL data requested more stims than bits for the specified scan chain. Encounter
Test will treat the extra stims as normalized scan-padded data. Since this is scan-in data,
the extra bits will be ignored from the beginning of the data.
USER RESPONSE:
Ensure that the data being ignored is non-critical, normalizing data. If the intention was
not to over-specify data for the given scan chain, adjust the data so that it matches the
desired data for the scan chain.
WARNING (TIS-456): [Severe] The value(s) specified for symbol symbol will be ignored.
EXPLANATION:

Any and all values specified for the referenced symbol will be ignored. This is most likely
because the referenced symbol could not be found in the Encounter Test model.
USER RESPONSE:
Check for a corresponding TIS-428 message and correct it.
WARNING (TIS-457): Unable to map the events at time time of vector referenced at
file_line to a single Encounter Test event.
EXPLANATION:
Encounter Test must use more than one Encounter Test Event to represent the
information described in the STIL at the referenced file & line, for the specified time within
the tester cycle. Because of this, the events will not be represented simultaneously, and
simulation errors may occur.
USER RESPONSE:
Check to ensure these events should indeed be executed simultaneously. If the order of
the events written out by Encounter Test is not as intended, modify the times in the
waveform table to represent the order of their desired execution.
WARNING (TIS-458): Unable to map STIL stim N to an equivalent value in Encounter Test.
Changing stim N to stim new_value for signal signal_name at line file_line.
EXPLANATION:
The stim N could have occurred either in the current vectors statement or in the preceding
condition statement. The STIL stim N construct indicates that the tester is driving a non-
Z value on this pin, but does not yet know whether the value is 0 or 1. Encounter Test
does not currently support this condition.The STIL reader does the following:
Arbitrarily chooses a 0 or 1 as the value to which this pin should be stimulated.
Tries to pick a stability value
If no stability value can be found, the STIL reader tries to choose the previous
non-Z value to which this pin has been stimulated.
If neither of the above cases apply, the STIL reader arbitrarily stimulates the pin
to 0. As an unknown value is arbitrarily replaced with a known value, the
simulation of the resulting patterns may be slightly more optimistic than the
original patterns, and in some rare cases, may even cause incorrect simulation.
USER RESPONSE:
It is recommended to remove all stim N constructs from the waveform table. If that is not
possible, check to see if the value chosen by the program is reasonable. If so, no action

is required. Otherwise, change this specific stim N value to the correct up or down (U or
D) action, and then rerun.
WARNING (TIS-459): Vector did not contain enough wave form characters to satisfy all
signals in symbol symbol at file_line.
EXPLANATION:
A vector statement in the STIL data specifies a list of wave form characters to be applied
to the signals referenced by the symbol group identified in the message, but there are
more signals in the symbol group than there are wave form characters. The STIL parser
will apply wave form characters only to those signals in the symbol group for which wave
form characters exist.
USER RESPONSE:
Update the specified line in the STIL data to ensure that the length of the wave form
character string matches the number of signals referenced by the symbol group.
WARNING (TIS-460): Unable to determine scan direction for scan pin symbol. Assuming
scan-in.
EXPLANATION:
The pin in the message appears inside the shift block of a scan procedure or macro, and
contains the scan substitution character # in the shift block, but this pin did not have a
ScanIn or ScanOut attribute, and the pin direction is InOut. In this case, the translator is
unable to determine if this is a scan-in or scan-out pin. The translator has arbitrarily
chosen to treat this as a scan-in pin.
USER RESPONSE:
Add ScanIn or ScanOut attributes to the input STIL and rerun.
WARNING (TIS-461): Ignoring unsupported KeyedData syntax found at file_line.

EXPLANATION:
The syntax for the KeyedData statement on the specified file/line is not supported. The
statement will be ignored.
USER RESPONSE:
Correct the statement to have a valid key=data format and rerun.
WARNING (TIS-462): STIL Design version design_version is not officially supported.

EXPLANATION:

The STIL data contains design version information that does not match the design
versions officially supported by this software. The results may be correct and complete,
but there may be constructs in this STIL data which are not correctly supported.
USER RESPONSE:
If possible, recreate the STIL data using a better accepted design version (e.g. Design
1.0), and import the accepted version of the data. If that is not possible, double check the
results to make sure they are correct and complete.
WARNING (TIS-463): Unexpected event eventName from file fileLine was ignored
while analyzing scan protocols.
EXPLANATION:
Only certain types of events, such as stims or pulses, are expected within scan macros
or procedures. In this case, an unexpected event was discovered in the STIL input data.
It will not affect the creation of the scan protocol.
USER RESPONSE:
Verify that the specified event is not required to enable the scan protocol. If it is required,
edit the sequence file produced by this program before running Build Test Mode.
WARNING (TIS-464): [Severe] Multiple scan protocols were detected. Using the protocols
from macro/procedure macroProcedureName1 defined in file fileLine1, and ignoring
the protocols from macro/procedure macroProcedureName2 defined in file fileLine2.
EXPLANATION:
Encounter Test supports a single scan protocol per test mode. Two scan macros were
found which implement different scan protocols. Encounter Test has arbitrarily chosen
one of the scan protocols, and used that one to define the test mode.
USER RESPONSE:
If the correct scan protocol for the desired test mode has been chosen, no response is
required. Otherwise, edit the STIL file to remove the scan macro with the incorrect scan
protocol, and rerun.
WARNING (TIS-465): [Severe] Scan Protocol Checking error detected.

MacroDomain: scanMacroDomain Macro: scanMacroName File: fileName, Symbol:
symbolName
EXPLANATION:
Encounter Test has chosen a scan macro to represent the scan protocol. When checking
all other scan macros in the STIL file, Encounter Test discovered a scan macro which

stims the specified symbol to a different value than the value already specified as a part
of the scan protocol.
USER RESPONSE:
If a stim of the specified symbol is not required for the scan protocol, no response is
required. If the stim is required, modify the scan macro chosen to represent the scan
protocol, and add a stim of the symbol to the required value to that macro.
WARNING (TIS-466): [Severe] Scan Protocol Checking error detected. Pulse polarity
mismatch.
symbolName
EXPLANATION:
pulses the specified symbol to a different value than the value already specified as a part
of the scan protocol.
USER RESPONSE:
If a pulse of the specified symbol is not required for the scan protocol, no response is
required. If the pulse is required, modify the scan macro chosen to represent the scan
protocol by changing the pulse to the correct polarity.
WARNING (TIS-467): [Severe] Scan Protocol Checking error detected.

symbolName
EXPLANATION:
failed to pulse the specified symbol, although the symbol was pulsed as a part of the scan
protocol.
USER RESPONSE:
If a pulse of the specified symbol is required for the scan protocol, no response is
required. If the pulse is not required, modify the scan macro chosen to represent the scan
protocol by removing the pulse.
WARNING (TIS-468): [Severe] Scan Protocol Checking error detected. No pulses exist.
symbolName

EXPLANATION:
failed to pulse any symbols, although the specified symbol was pulsed as a part of the
scan protocol.
USER RESPONSE:
If a pulse of the specified symbol is required for the scan protocol, no response is
required. If the pulse is not required, modify the scan macro chosen to represent the scan
protocol by removing the pulse.
WARNING (TIS-469): [Severe] Scan Protocol Checking error detected. Measure bit
mismatch.
symbolName
EXPLANATION:
specified that the symbol in question was measured at a different value than that
specified as the scan protocol.
USER RESPONSE:
If a measure of the specified symbol is not required for the scan protocol, no response is
required. If the measure is required, modify the scan macro chosen to represent the
correct value.
WARNING (TIS-470): [Severe] Scan Protocol Checking error detected. Events %s and %s
mismatch.
MacroDomain: eventName1 Macro: eventName2 File: fileName
EXPLANATION:
implements a different set of events than the events in the scan protocol.
USER RESPONSE:
If the order of events is correct in the original scan protocol, no response is required. If
the order of events is correct in the macro to represent the correct value.
WARNING (TIS-471): [Severe] Scan Protocol Checking error detected. Event not found.
MacroDomain: eventName1 Macro: eventName2 File: fileName

EXPLANATION:
implements a different set of events than the events in the scan protocol.
USER RESPONSE:
If the order of events is correct in the original scan protocol, no response is required. If
the order of events is correct in the macro to represent the correct value.
WARNING (TIS-472): A Mode Initialization Sequence could not be built. Input Macro name
not specified.
EXPLANATION:
While building the Sequence Definition file (TBDseqPatt), the input macro name was not
specified. The macro name is required in order to determine the mode init sequence.
USER RESPONSE:
If a mode init macro is not specified, Encounter Test creates a default mode initialization
sequence. If the default mode initialization sequence is sufficient, no response is
required. Otherwise, rerun the application with the mode init macro name specified.
WARNING (TIS-473): [Severe] A Mode Initialization Sequence could not be built. Input
Macro name macroName not found.
EXPLANATION:
While building the Sequence Definition file (TBDseqPatt), the input macro name was not
found in the input STIL. A valid macro name is required in order to determine the mode
init sequence
USER RESPONSE:
Re-run the application with a valid macro name specified.
Macro name macroName in Macro domain macroDomainName is a scan macro.
EXPLANATION:
While building the Sequence Definition file (TBDseqPatt), the input macro name was
found in the input STIL but it is a scan macro. The macro name should be a non-scan
macro in order to build the mode init sequence
USER RESPONSE:

Re-run the application with a non-scan macro name specified.
WARNING (TIS-475): [Severe] The Mode Initialization Sequence could not be created
from Macro name macroName Macro Domain Name macroDomainNames because the
Macro name and Macro Domain exist more than once in the STIL file.
EXPLANATION:
The macro name was found to exist in more than one macro domain. The names must
differ in order to distinguish which one to use when creating the mode initialization
sequence.
USER RESPONSE:
Ensure the STIL macro names and macro domain names are unique.
WARNING (TIS-476): In fileName:
The resulting vector statement assigns more than one waveform character to the symbol
symbol.The second waveform character newWaveformChar will be ignored while the first
waveform character encountered, retainedWaveformChar, will be retained.
EXPLANATION:
Only the first waveform character is assigned to a given symbol within a vector
statement. Any subsequent waveform character(s) applied to the same symbol within the
vector statement will be ignored.
USER RESPONSE:
If this causes a problem, consider issuing a new vector statement in the STIL to change
the waveform character of a given symbol.
WARNING (TIS-477): In filename, the resulting vector statements assign more than one
waveform character to the symbol symbol. Waveform character newWaveformChar will
be ignored while the first waveform character encountered, retainedWaveformChar, will
be retained.
EXPLANATION:
During evaluation of the STIL timing construct within the waveform table, the construct
was found to be difficult to convert internally. A conversion down to the Atto level was
successful and most likely is acceptable.
USER RESPONSE:
If the result is unacceptable, consider issuing a new vector statement in the STIL to
change the waveform character of a given symbol.

WARNING (TIS-478): [Severe] In fileInfo, clock clockName was not at the stability
value when pulsed.
EXPLANATION:
A pulse value was applied that did not match the previous pulse value.
USER RESPONSE:
Verify pulse values in the STIL file
WARNING (TIS-479): [Severe] Pin pinName is defined as an pinDirection pin but a

stimOrMeasure event was applied.
fileInfo
The stimOrMeasure event was ignored.
EXPLANATION:
An event was invalid for the given pin and its direction.
USER RESPONSE:
Verify the pin, its direction and the stim/measure events associated with it within the STIL
file
WARNING (TIS-480): [Severe] Pin pinName is defined in the STIL file as an

pinDirection pin but it is not defined as such in the Encounter Test model.
EXPLANATION:
The pins direction defined in the STIL file does not match pin direction in the model.
USER RESPONSE:
Determine why the pins direction is different between the STIL data and the Encounter
Test model. Fix either the Encounter Test model or the STIL data.
WARNING (TIS-481): Scan structures block scanStructureName could not be found.

The resulting TBD will not contain Scan Data Objects (Scan Cells).
EXPLANATION:
While attempting to derive Scan Cell information from the Scan Structures block, the
specified ScanStructures block could not be found.
USER RESPONSE:
If a scan structure name was specified, verify it was correctly typed on the command line
or in the STIL. If a scan structure name was not specified as indicated by the name
#global#, verify that a non-named scanStructures block was specified in the STIL.

WARNING (TIS-482): Ignoring eventType of Symbol=symbol slot=slot

action=action in Scan Sequence Definition.
file_line
EXPLANATION:
Either a stim or a measure of an input or output pin that was not identified as a scan-in
or scan-out pin was discovered inside the shift block of a scan macro or procedure.
Typically, all non-scan stims and measures are expected to occur either before or after
the shift block.
USER RESPONSE:
Verify that the specified stim or measure should not really occur before or after the shift
block. If the stim or measure must occur inside the shift block, the resulting scan
sequence must be manually edited before building a test mode. Refer to STIL Pattern
File in the Encounter Test: Guide 1: Models for related information.
WARNING (TIS-483): [Severe] The number of STIL scan cycles (scanCycleCount) is

less than the Encounter Test scan length (scanLength).
Reference : file_line
EXPLANATION:
There is a difference between the scan length as determined by the Encounter Test
model and the number of scan cycles defined in the STIL input.
USER RESPONSE:
Determine why there is a difference between the STIL data and the Encounter Test
model. Correct either the Encounter Test model or the STIL data.
WARNING (TIS-484): [Severe] The number of STIL scan cycles (scanCycleCount) is

greater than the Encounter Test scan length (scanLength).
Reference : file_line
EXPLANATION:
There is a difference between the scan length as determined by the Encounter Test
model and the number of scan cycles defined in the STIL input.
USER RESPONSE:
Determine why there is a difference between the STIL data and the Encounter Test
model. Correct either the Encounter Test model or the STIL data.
MacroDomain name macroDomainName not found.

EXPLANATION:
The input macro domain name was not found in the input STIL while building the
Sequence Definition file (TBDseqPatt). The macro domain name is required to determine
the modeinit sequence.
USER RESPONSE:
Rerun the application, specifying a valid macro domain name.
WARNING (TIS-486): The net signal name netSignalName has a STIL specified
direction of signalDirFromSTIL while the Encounter Test Model indicates that the net
direction is signalDirFromModel. The net signal will be ignored.
EXPLANATION:
While resolving the defined input signal names in the STIL file to a pin, the program
determined a mismatch between the anticipated signal directions in the STIL file and the
USER RESPONSE:
Possible causes are:
The STIL specified signal direction is incorrect.
The Encounter Test model pin direction is incorrect.
The signal net name is incorrect.
Resolve the applicable condition and rerun.
WARNING (TIS-487): The net signal name netSignalName with a specified direction of
signalDirFromSTIL pin in the STIL could not be found in the Encounter Test Model. The
net signal will be ignored.
EXPLANATION:
While resolving the defined input signal net names in the STIL to a pin, the program
determined that no pin exists in the Encounter Test model that fits the nets description.
USER RESPONSE:
The STIL specified signal or signal direction is incorrect.
An incorrect Encounter Test model is specified.
The Encounter Test model pin direction is incorrect.


WARNING (TIS-488): The net signal name netSignalName with a specified direction of
signalDirFromSTIL pin in the STIL could not be found within the top level of the
Encounter Test Model. The net signal will be ignored.
EXPLANATION:
While resolving the input signal net names defined in the STIL to a pin, the program
determined that no pin exists in the Encounter Test model that fits the net description,
specifically at the top level of the model.
USER RESPONSE:
The STIL specified signal or signal direction is incorrect.
An incorrect Encounter Test model is been specified.
WARNING (TIS-489): A vector specified that a hex base should be associated with signal
signalName, but a hex base was not specified for that signal.
Reference: file_line
EXPLANATION:
The vector item at the specified reference file and line number requested hexadecimal to
wfcs translation using a hex base specified in a signal or signalGroup block for the
specified signal. However, no hex base was specified in the signal or signalGroup block
for that name. The vector item will be ignored.
USER RESPONSE:
Either add a base specification in the signal or signalGroups block or do not include a
hex (\\h) specification in the vector data.
WARNING (TIS-490): A vector specified that a decimal base should be associated with
signal signalName, but a decimal base was not specified for that signal.
Reference: file_line
EXPLANATION:

The vector item at the specified reference file and line number requested decimal to wfcs
translation using a decimal base specified in a signal or signalGroup block for the
specified signal. However, no decimal base was specified in the signal or signalGroup
block for that name. The vector item will be ignored.
USER RESPONSE:
Either add a base specification in the signal or signalGroups block or do not include a
decimal (\\d) specification in the vector data.
WARNING (TIS-491): [Severe] Unbalanced quoted string ; stringVar at : file_line.

EXPLANATION:
The input STIL file has string data that appears to have been started but the closing
quotes was not found.
USER RESPONSE:
Fix the suspect quoted string and rerun the application.
WARNING (TIS-492): No scan test sequences found.

EXPLANATION:
No scan test sequences were found in the STIL input.
USER RESPONSE:
This may or may not be a problem. If at least one scan test sequence was expected, a
problem may exist in the STIL, particularly with the load or unload pattern data.
WARNING (TIS-493): [Severe] Signal signal in wave form table wave_form_table

in timing domain timing_domain, may be invalid.
EXPLANATION:
The specified signal does not appear to have a direction associated with it.
USER RESPONSE:
Ensure that the signal name is properly defined in the signals construct. Correct either
the signal name in either the signals construct or in the specified waveform table.
WARNING (TIS-494): It is recommended that you run simulate_vectors rather than

read_vectors when processing compression networks for Diagnostics.
EXPLANATION:

Simulate_vectors will create Diagnostic Measure Latch information required for

diagnostics. Also, the results from simulate_vectors can provide adequate
miscompare information for analysis.
USER RESPONSE:
Run simulate_vectors in the future when processing compression networks for
Diagnostics.
WARNING (TIS-495): [Severe] Symbol symbol_name referenced in the vector statement

at vector_statement_file_and_line has not been previously defined in either a
signal block or a signalGroup block. All vector assignments to this symbol will be ignored.
EXPLANATION:
A vector statement at the indicated file and line referenced the symbol specified in the
message, but this symbol has not previously been defined in either a signal block or
signalGroup block that is valid in this context. This is a STIL semantic error and must be
corrected. All assignments to this symbol will be ignored. All results may be incorrect.
USER RESPONSE:
Perform either of the following and then rerun:
Add a definition for the referenced symbol to either the signal block or the
signalGroup block in the STIL data.
Change the referenced symbol to a valid signal or signalGroup name in the
input STIL data.
WARNING (TIS-496): Test Inhibit pins cannot be identified because the input STIL data
contans no test patterns and no testmode initialization information.
EXPLANATION:
The build_testmode command is trying to infer which pins should be test inhibited
from the input STIL file. To do this, the command must either have a valid set of patterns,
or have information about the testmode initialization, as specified by the initmacro
keyword. The input STIL file has neither a valid set of patterns or testmode initialization
information. Therefore, no test inhibit pins will be identified in the resulting assign file
produced by this command. The test mode will still be built, but if test inhibit information
is required, the testmode will not be correct.
USER RESPONSE:
Ignore this message if no test inhibit pins are required for this testmode.

If test inhibit pins are required, then either use the initmacro keyword to point to valid
testmode initialization information, or modify the input STIL file to contain valid test
patterns and/or valid testmode initialization information and then rerun.
WARNING (TIS-497): [Severe] The timing expression contained a division in which the
denominator value of the division is zero or negative at file_line. The timing expression
will result in a zero value.
EXPLANATION:
A division in the timing expression at the referenced line of the STIL input data has a zero
in the denominator. This expression will be evaluated to a zero value and processing will
continue. The waveforms that rely on this timing expression are likely to be incorrect.
USER RESPONSE:
Define a non-zero value for the denominator in the timing expression at the referenced
file and line number and rerun.
WARNING (TIS-498): [Severe] The PatternExec block at file_line_number uses

a different category than previous PatternExec blocks. Multiple category specifications are
not supported using a single STIL file. The original category category will be used.
EXPLANATION:
The use of multiple category blocks is supported by the STIL specification, but Encounter
Test only supports a single category.
This message indicates that a second category is explicitly specified by a category
statement in a PatternExec block or implicitly specified by the lack of a category
statement (in which case , Encounter Test treats the category as #global#).
The category in the referenced PatternExec block is different than the category either
implicitly or explicitly identified in previous PatternExec blocks. Encounter Test will
ignore this category selection.
USER RESPONSE:
Use the same category domain in all the PatternExec blocks and rerun.
WARNING (TIS-499): [Severe] The first vectors of the STIL data do not match the mode
initialization sequence for testmode testmode . A mode initialization sequence has been
inserted before events derived from STIL.
EXPLANATION:
The first vectors of the STIL data were compared against the test mode initialization
sequence that was created when the specified test mode was built, and the STIL data

does not match the test mode initialization sequence. Encounter Test is inserting its own
testmode initialization sequence to ensure that the circuit is in the state associated with
this test mode before processing any events derived from the STIL data.
The following are possible causes for this message.
The test mode is incorrectly specified .
The test mode is correct and the STIL mode initialization is functionally
equivalent to the Encounter Test mode initialization sequence for this test mode,
but the two do not exactly match.
The STIL data assumes that the test mode initialization sequence has been
applied already and that the circuit is already in the correct state.
USER RESPONSE:
If the test mode was incorrectly specified, specify the correct testmode and rerun
read_vectors.
If the STIL data contains a test mode initialization sequence that does not exactly match,
and the test mode initialization can be executed twice with no side effects, no action is
required.
If the test mode is correct, and the STIL data assumes that test mode initialization has
already occurred, no action is required.
Otherwise, either rebuild the test mode to contain the correct test mode initialization or
edit the STIL input data so that the first few vectors match the test mode initialization
sequence, and then rerun read_vectors.
WARNING (TIS-500): [Severe] The timing data being parsed is of an unknown type:
timingDomainType
EXPLANATION:
The STIL timings parser only handles four types of data: default, test, scan, and init. It is
designed this way to properly assign the correct write_vectors keywords. Data
contained in these unknown types are not processed.
USER RESPONSE:
Rename if possible the timings data in the STIL file. The timing type needs to contain
these values as a substring.
WARNING (TIS-501): [Severe] The timing data being parsed for the pin pinname, is
larger than the period for the WaveFormTable waveFormTable. The run will continue to
create the timing data file but the timings are suspect.

EXPLANATION:
The STIL timings parser has encountered an event time that is larger than the period for
these waveforms. The TIStimingData file will still be created, but write vectors will
probably fail unless the data is corrected.
USER RESPONSE:
Validate the timing data provided in the import file is the correct data and rerun. Either
adjust the period to encompass the event timing or adjust the event timing to fit within the
period

INFO (TIS-801): Primary STIL (1450.0) version stil_version_number.
EXPLANATION:
Describes the currently parsed STIL version.
USER RESPONSE:
INFO (TIS-802): program name has completed.

EXPLANATION:
The import program has completed processing.
USER RESPONSE:
INFO (TIS-804): program name started.

EXPLANATION:
The import program has been invoked.
USER RESPONSE:
INFO (TIS-805): STIL parsing ended with a return code of parse_rc.

EXPLANATION:

The process of parsing the STIL data completed, resulting in a return code specified in
the message.
USER RESPONSE:
INFO (TIS-806): Returning from included file to file: file line: line number.
EXPLANATION:
An end-of-file has been encountered in an included STIL file. This message indicates a
return to the point after the original include.
USER RESPONSE:
INFO (TIS-807): Including file: file.

EXPLANATION:
The STIL parser encountered an include, and is starting to read the included file
specified in the message.
USER RESPONSE:
INFO (TIS-808): Processing Pattern Exec block: pattern_exec_block_name using

timing domain timing_domain.
EXPLANATION:
Starting to write the patterns contained in the specified pattern exec block out to a
Encounter Test experiment.
USER RESPONSE:
INFO (TIS-809): A Mode Initialization Sequence was not created.

EXPLANATION:
The STIL to Mode define conversion program was unable to generate a mode
initialization sequence within the sequence (TBDseqPatt) file.
USER RESPONSE:

Refer to a previous message that may accompany this message that describes why the
Mode Initialization Sequence was not created.
INFO (TIS-810): The Mode Initialization Sequence was created from macro name
macroName macro domain name macroDomainName.
EXPLANATION:
The macro name was detected in more than one macro domain. The first macro domain
that contained the macro name was used in determining the mode initialization
sequence.
USER RESPONSE:
No response required if the intent was to use the selected macro domain. However, if the
intent was to select a different macro domain, specify the desired domain should be
specified using the macrodomainname keyword, and then rerun.
INFO (TIS-811): The sequences to define the scan protocol will be generating using
macro name: macroName
macro domain name: macroDomainName
EXPLANATION:
The scan protocol information was derived from the specified macro and macro domain.
USER RESPONSE:
No response required if the intent was to use the selected macro info. However, if the
intent was to select different macro information, specify the scan in/out macro before the
selected macro in the STIL file and then rerun.
INFO (TIS-812): The scan protocol information will be derived from

Procedure name: procName
Procedure Domain Name: procDomainName
EXPLANATION:
The scan protocol information was derived from the specified procedure and procedure
domain.
USER RESPONSE:
No response required if the intent was to use the selected procedure info. However, if the
intent was to select different procedure information, the scan in/out procedure must be
specified before the selected procedure in the STIL file.
INFO (TIS-815): Found numberOfScanTestSequences scan test sequences.

EXPLANATION:
The stated number of scan test sequences were found in the STIL input.
USER RESPONSE:
INFO (TIS-816): Extended STIL data: Extension: extension_name, Extension Number:

extension_number, Extension Version: extension_version.
EXPLANATION:
The message describes the STIL extension information currently being parsed.
USER RESPONSE:
INFO (TIS-817): No Scan Information found for scan bits scan bit to number of scan
cycles for symbol symbol in Macro/Procedure Reference at Macro Reference.
These bits will be stimmed to X and not measured.
EXPLANATION:
The scan information for these scan bits is not stored.
USER RESPONSE:
INFO (TIS-818): Ignored number_ignored scan in pins identified in the scan structures
block scan_domain_name at file_line.
EXPLANATION:
The input STIL data indicates that pins are scan-in in the scan structures block, but the
signals block indicates that the pin is not an input pin, or does not appear in the signals
block. Typically, this is because these pins are pseudo pins, and can be ignored.
USER RESPONSE:
No response required. More detail is available for each ignored pin by rerunning using
parameter TISdebug=1.
INFO (TIS-819): Returning from included file to file: file line: line number.
EXPLANATION:

An end-of-file has been encountered in an included STIL file. This message indicates a
return to the point after the original include.
USER RESPONSE:
INFO (TIS-820): Including file: file

EXPLANATION:
The STIL parser encountered an include, and is starting to read the included file
specified in the message.
USER RESPONSE:
INFO (TIS-821): Include files are not support by read_vectors. Include file file is
ignored. Processing continues.
EXPLANATION:
The use of Include "filename" is only supported for read_sequence_definition.
read_vectors will not process the specified file.
USER RESPONSE:
No response required. Processing continues.
INFO (TIS-822): STIL timings are being imported to file: stiltimings File Name
EXPLANATION:
Stil Timings have been requested.
USER RESPONSE:
INFO (TIS-823): STIL timings were found of type: stiltimings type

EXPLANATION:
Stil Timings have been found in the input stil file and they are defined as this type.
USER RESPONSE:
INFO (TIS-999): Debug_Text.

EXPLANATION:
General debug message
USER RESPONSE:


42
TJA - Write BSDL Messages
TJA-103 through TJA-653 on page 1351
TJA-103 through TJA-653

INFO (TJA-103): Using mode delay simulation
EXPLANATION:
The delay mode being used by the simulator for this application
USER RESPONSE:
WARNING (TJA-201): [Severe] Unable to identify Test Access Port: test access
port
EXPLANATION:
One of the required test access ports for IEEE 1149.1 could not be identified from the
test function pins defined in the current test mode.
The output BSDL will contain only the PORT statement.
USER RESPONSE:
Define the missing TAP using the Test Mode Define functions.
WARNING (TJA-205): expected 01 to be the Least Significant Bits of the Instruction

Register after CaptureIR but got sim val
EXPLANATION:
The IEEE 1149.1 standard states that the two least significant bits of the Instruction
register must be 01 after entering the Capture-IR state.
USER RESPONSE:

This may be a design problem. Run Boundary Scan Verification to analyze your design,
then rerun write_bsdl.
ERROR (TJA-206): Cannot determine size of Instruction Register

EXPLANATION:
The size of the register is determined by shifting logic 1/0 into TDI in the ShiftIR state and
counting how may pulses of TCK it takes to see the 0/1 appear on TDO.
USER RESPONSE:
This may be a design problem. Run Boundary Scan Verification to analyze your design,
then rerun write_bsdl.
ERROR (TJA-207): Cannot determine size of Boundary Scan Register

EXPLANATION:
The size of the register is determined by Test Structure Identification as part of building
the test mode with the EXTEST instruction loaded and the chip in the Shift_DR state. Only
one register should be identified and this should be the boundary scan chain.
USER RESPONSE:
Contact customer support to resolve building a test mode which identifies the Boundary
Scan Register bits during Test Mode Define.
WARNING (TJA-209): [Severe] BSDL Output File file_1 is not writeable

EXPLANATION:
The specified output file name where the BSDL would be written does not give write
permission to you.
USER RESPONSE:
Establish write permission or specify a different file name
WARNING (TJA-210): [Severe] BSDL Output File file currently exists but replace was
not specified.
EXPLANATION:
The specified output file where the BSDL should be written already exists but the replace
option was not specified. The BSDL will NOT be written to this file.
USER RESPONSE:
Specify a different file name or use the replace option.

WARNING (TJA-224): [Severe] Input BSDL file: file name cannot be opened.
EXPLANATION:
The bsdlinput parameter was specified on the command line, but this file was not found
or not readable
USER RESPONSE:
Make sure the specified file is correct.
WARNING (TJA-230): Output BSDL file is not complete because of previous errors.
EXPLANATION:
The output BSDL file was written with only minimal data in it because some problem
during the program prevented more information being generated.
USER RESPONSE:
Do not use the BSDL file for any production Test Generation.
WARNING (TJA-301): Boundary Scan Cell cell, cellname, is determined to be an

Internal cell with no correlation to any chip I/O pin.
EXPLANATION:
The cell position in the Boundary Scan Register could not be determined to have any cell
function other than internal. Some aspect of the IEEE 1149.1 Standard may be incorrect
which caused this result.
USER RESPONSE:
If the intent of the design was to have this Boundary Cell be internal, then no action is
needed. Otherwise, modify the BSDL file to reflect the correct cell function and port
correlation and verify the behavior using Encounter Test.
Refer to IEEE 1149.1 Boundary Scan Verification and "Performing IEEE 1149.1
Boundary Scan Verification" in the Encounter Test: Guide 3: Test Structures for
WARNING (TJA-302): Boundary Scan Cell cell, cellname, was determined to have
a combination of cell functions, cfunc1 and cfunc2 which is not allowed by the IEEE
1149.1 Boundary Scan Standard.
EXPLANATION:
The cell position in the Boundary Scan Register was determined to have two different
logical functions where the combination is forbidden by the IEEE 1149.1 Standard.

USER RESPONSE:
This may be a design problem. Modify the BSDL file to reflect the correct cell function
and port correlation and verify the behavior using IEEE 1149.1 Boundary Scan
Verification to analyze your design.
WARNING (TJA-303): Logical Chip Pin pname does not have any correlation to any
Boundary Scan Cell, yet it is not defined as a Test Function pin.
EXPLANATION:
No cell position in the Boundary Scan Register was determined to either capture or drive
the logic value of the chip pin.
USER RESPONSE:
If this is a system data pin, then the IEEE 1149.1 Standard requires that it should be
tested using the Boundary Scan Register. If this finding differs from the intent of the
design, then use IEEE 1149.1 Boundary Scan Verification to analyze your design.
WARNING (TJA-304): Logical Chip Pin pname is defined as a Test Function pin and its
value is captured into Boundary Scan Cell pname.
EXPLANATION:
The TAP and compliance enable pins should not be captured into nor driven from the
Boundary Scan Register.
USER RESPONSE:
If this is a design problem, then it must be fixed. If this finding differs from the intent of
the design, then use IEEE 1149.1 Boundary Scan Verification to analyze it.
WARNING (TJA-305): Boundary Scan Cell cell, cellname, is a control cell which has
conflicting disable values for the outputs that it controls.

EXPLANATION:
The logical value which this cell must contain to enable or disable the ports that it controls
must be consistent for all the ports.
USER RESPONSE:
This may be a design problem. Verify the behavior using IEEE 1149.1 Boundary Scan
Verification.
WARNING (TJA-306): Boundary Scan Cell cell1, cell1name, has a disable value of
val which is different than other cells controlled by cell cell2, cell2name.
EXPLANATION:
The cell position in the Boundary Scan Register was determined to have disable value
which differs from other cell controlled by the same cell.
USER RESPONSE:
This may be a design problem. Verify the behavior using IEEE 1149.1 Boundary Scan
Verification.
WARNING (TJA-307): Boundary Scan Cell cell, cellname, maps to the following
output pins.
EXPLANATION:
The cell position in the Boundary Scan Register was determined to drive more than one
chip pin.
USER RESPONSE:
This may be a design problem. Modify the BSDL file to reflect the correct cell function
and port correlation and verify the behavior using IEEE 1149.1 Boundary Scan
Verification to analyze your design.

WARNING (TJA-308): Boundary Scan Cell cell, cellname, was designated Internal
because reason.
EXPLANATION:
The cell position in the Boundary Scan Register could not be determined to have any cell
function other than internal. Some aspect of the IEEE 1149.1 Standard may be incorrect
which caused this result.
USER RESPONSE:
If the intent of the design was to have this Boundary Cell be internal, then no action is
needed. Otherwise, modify the BSDL file to reflect the correct cell function and port
correlation and verify the behavior using IEEE 1149.1 Boundary Scan Verification.
WARNING (TJA-310): A BOUNDARY_REGISTER statement can not be produced without an

opcode for the EXTEST instruction.
EXPLANATION:
If write_bsdl has been invoked without a BSDL file, no BOUNDARY_REGISTER
statement will be produced since there is no known instruction opcode for EXTEST. This
information should be conveyed via an input BSDL file as are other instructions/opcodes.
USER RESPONSE:
Input a BSDL file with the appropriate EXTEST opcode.
WARNING (TJA-401): Could not produce PHYSICAL_PIN_MAP for attr because one or
more physical pin names were missing or incorrect.
EXPLANATION:
Not every port has a correct physical pin specification for this attribute.
USER RESPONSE:
Ensure that all pins have a proper physical pin specification.
WARNING (TJA-402): Physical pin name pin for logical port port in
PHYSICAL_PIN_MAP attr is syntactically incorrect.
EXPLANATION:
The specified physical pin specification is not correct

USER RESPONSE:
Ensure that the pin has a proper physical pin specification
WARNING (TJA-403): No physical pin name was found for logical port port in
PHYSICAL_PIN_MAP attr.
EXPLANATION:
Every logical port must have a physical pin specified
USER RESPONSE:
Ensure that the port has a proper physical pin specification
WARNING (TJA-404): Could not produce PHYSICAL_PIN_MAP for attr because no

physical pin names were provided.
EXPLANATION:
No port had a physical pin specification for this attribute.
USER RESPONSE:
Ensure that the attribute name provided has proper physical pin specifications.
WARNING (TJA-405): Physical pin name pin for logical port port in
PHYSICAL_PIN_MAP attr is repeated more than once.
EXPLANATION:
The specified physical pin was given more than once.
USER RESPONSE:
Ensure that each pin name is used no more than once per physical pin map.
WARNING (TJA-415): [Severe] Syntax error in attribute name name

EXPLANATION:
The specified attribute name is not in the correct syntax for this application. Each name
must start with an alpha character only and contain alpha, numeric or underscores.
When folded to upper case, each name specified must be unique.
USER RESPONSE:
Specify the attribute correctly.
WARNING (TJA-416): [Severe] Attribute name name not unique

EXPLANATION:
The specified attribute name was not unique for this application. Each name must start
with an alpha character only and contain alpha, numeric or underscores. When folded to
upper case, each name specified must be unique.
USER RESPONSE:
Specify the attribute correctly.
WARNING (TJA-500): [Severe] Unable to obtain license for BSDL Generation

EXPLANATION:
The License Server refused permission to run BSDL Generation
USER RESPONSE:
Contact your Encounter Test system administrator
WARNING (TJA-501): [Severe] Unable to load the hierModel for circuit.

EXPLANATION:
A required file is not found
USER RESPONSE:
Ensure that the Encounter Test model is correctly specified. Refer to "write_bsdl in the
Encounter Test: Reference: Commands for command line syntax information.
WARNING (TJA-502): [Severe] Unable to load the flatModel for design

EXPLANATION:
A required file is not found.
USER RESPONSE:
Ensure that the Encounter Test model is correctly specified
WARNING (TJA-503): [Severe] Unable to establish use of the test mode mode name
EXPLANATION:
A required file is not found or is in use
USER RESPONSE:

Ensure that the Encounter Test model and Test Mode is correctly specified. Refer to
"write_bsdl in the Encounter Test: Reference: Commands for command line syntax
information.
ERROR (TJA-605): BSDL generation can not continue due to reason.

EXPLANATION:
A terminating error has occurred. The run terminates.
USER RESPONSE:
Examine the log and the stderr log for a preceding message which may offer additional
information relating to why the run terminated. If such a message exists, refer to the
corresponding explanation/response. Otherwise, note the reason given in this message
and contact customer support if necessary (see Contacting Customer Service on
page 23).
INFO (TJA-606): Testmode for Boundary Register Determination created successfully.

EXPLANATION:
A testmode was built
USER RESPONSE:
WARNING (TJA-607): [Severe] Could not create Testmode for Boundary Register
Determination.
EXPLANATION:
The testmode which identifies the boundary register as the scan chain for test generation
was created successfully.
USER RESPONSE:
See previous TTM messages in the log output for an explanation.
INFO (TJA-608): Testmode modename for Boundary Register Determination was saved
EXPLANATION:
The testmode which identifies the boundary register as the scan chain for test generation
was not removed.
USER RESPONSE:

WARNING (TJA-609): [Severe] The Input BSDL file contained errors which may prevent
the copy of some statement to the output BSDL file
EXPLANATION:
No semantically incorrect statements are copied from the input to the output
USER RESPONSE:
Fix the BSDL input
WARNING (TJA-651): [Severe] No Encounter Test model specified (WORKDIR=)

EXPLANATION:
There was no path provided which contains the Encounter Test model files
USER RESPONSE:
Refer to the Encounter Test: Guide 1: Models for information on building a model.
WARNING (TJA-652): [Severe] No Test Mode specified (TESTMODE=)

EXPLANATION:
There was no required Test Mode name provided with TESTMODE=.
USER RESPONSE:
Ensure that a Test Mode is correctly specified. Refer to the Encounter Test: Guide 1:
Models for information on building a test mode.
ERROR (TJA-653): Can not create BSDL using the test mode test mode name since
the test mode was defined with an instruction: instruction name | instruction
opcode and a TAP_TG_STATE: tap_tg_state name.
EXPLANATION:
write_bsdl has determined that the selected test mode is inappropriate for producing
a BSDL file. This may be due to one or more of the following:
The test mode is defined with a scan type which is not 1149.1. write_bsdl may only
be invoked on an 1149.1 test mode which defines no INSTRUCTION and
TAP_TG_STATE.
USER RESPONSE:
Make necessary adjustments to the mode test mode definition file and rerun test mode
define. Alternatively, select a test mode which meets the criteria for running
write_bsdl.

ERROR (TJA-999): [Internal] An unexpected condition occurred in the Encounter(R) Test

write_bsdl code. Contact Cadence Customer Support to report this error and give them
the following information: An error occurred on line line_number of source file
file_name: variable_text
EXPLANATION:
USER RESPONSE:


43
TJB - Parse BSDL Messages
TJB-100 through TJB-250 on page 1363

TJB-100 through TJB-250

INFO (TJB-100): Encounter Test IEEE 1149.1 BSDL Parser started: time-date
EXPLANATION:
The BSDL Parser function has started. TJB-
USER RESPONSE:
INFO (TJB-101): Encounter Test IEEE 1149.1 BSDL Parser ended: time-date
EXPLANATION:
The BSDL Parser function has completed.
USER RESPONSE:
WARNING (TJB-102): [Severe] Input BSDL file: BSDL_filename is empty. This parser
requires at least an entity/generic statement and an end statement in the BSDL file.
EXPLANATION:
An empty BSDL file was encountered. The BSDL parser requires a BSDL file containing
at least an entity/generic statement and an end statement in the BSDL file.
USER RESPONSE:

Ensure the BSDL file is correct and rerun.
WARNING (TJB-103): [Severe] Input BSDL file: BSDL_filename is unreadable. Check

the permission bits for this file.
EXPLANATION:
The BSDL file could not be read due to the file permission data set for that file.
USER RESPONSE:
Ensure that the BSDL file permission bits allow read access. Change the permission bits
on the BSDL file and rerun.
WARNING (TJB-104): [Severe] Input BSDL file: BSDL_filename cannot be opened.

Ensure the file exists within the path specified. error information
EXPLANATION:
The BSDL file could not be read due to error information specified.
USER RESPONSE:
Ensure the file exists within the path specified and validate the BSDL file name. Correct
the problem and rerun.
WARNING (TJB-105): [Severe] The BSDL does not appear to be applicable for the model.
The BSDL file: BSDL_filename contains an entity name of: entity name which cannot
be found as a cell name in the model.
Model information:
WORKDIR = project name
The BSDL entity name must exist as a cell name within the model.
EXPLANATION:
The BSDL file and the logic model do not correlate to each other. The entity name
specified in the BSDL does not exist as a cell name in the logic model.
USER RESPONSE:
Ensure that you have the correct BSDL file and the correct logic model specified. Also
be sure that the entity name in the BSDL file is correct. Correct the problem and rerun.
INFO (TJB-106): An output BSDL file will not be printed.

EXPLANATION:

BSDL output will not be printed.

USER RESPONSE:
WARNING (TJB-107): [Severe] No BSDL input file to process, one needs to be specified.
EXPLANATION:
At least one BSDL input file is required as input.
USER RESPONSE:
Specify a valid BSDL file as input and rerun.
WARNING (TJB-108): [Severe] A model related problem has occurred. An attempt to load
a block in the model failed.
Model information:
EXPLANATION:
Internal code has failed while loading the logic model.
USER RESPONSE:
assistance.
WARNING (TJB-109): [Severe] A model related problem has occurred. An attempt to load
the model from disk failed.
Model information:
EXPLANATION:
Internal code has failed while loading the logic model.
USER RESPONSE:
assistance.
WARNING (TJB-110): debug or semantic output file: BSDL_outputfilename

cannot be opened. A default name of default_outputfilename will be used.

EXPLANATION:
The output file name could not be opened, a default file name will be generated.
USER RESPONSE:
No response required unless the output name does not suffice. If the output name does
not suffice, ensure the specified output file name is valid and permission bits allow
writing. Correct the problem and rerun.
WARNING (TJB-111): Default debug or semantic output file: filename cannot be

opened. debug or semantic output data will be written to the log file.
EXPLANATION:
The default debug or semantic output file could not be used. Output will go to
stdout.
USER RESPONSE:
No response required unless the stdout file does not suffice. If the stdout file does not
suffice, check to ensure that the default output file name is valid and permission bits allow
writing.
WARNING (TJB-112): [Severe] Initialization of the internal structures has failed.

EXPLANATION:
An internal application error has occurred.
USER RESPONSE:
assistance.
WARNING (TJB-113): [Severe] The model does not contain any usage blocks.
Model information:
EXPLANATION:
The logic model loaded does not contain any blocks other than the Prototype (Block 0)
block.
USER RESPONSE:
Ensure that the selected logic is correct. Check the source from which the model was
built and ensure completeness.

Correct the problem and rerun.
WARNING (TJB-116): The compliance enable pattern for test function pin name specifies
a compliance value of X (dont care condition). A test function of -TI|+TI will be used for pin
name.
EXPLANATION:
The BSDL file specifies a compliance value of X for the specified pin. A test function of -
TI or +TI as specified in the message will be used for further processing.
USER RESPONSE:
WARNING (TJB-117): [Severe] The BSDL test function value for pin name is in conflict
with the mode test function value. BSDL test function = test function. Mode test
function = test function.
EXPLANATION:
The BSDL file specifies a test function value for a pin with is in conflict with the test
function value specified for this pin in the test mode.
USER RESPONSE:
Change the BSDL test function value for the pin or rebuild the test mode with the correct
test function value. See IEEE 1149.1 Boundary Scan Controls in the Encounter Test:
Guide 2: Testmodes for additional information.
WARNING (TJB-118): [Severe] The mode test function for pin name is not defined as a
test function in the BSDL. Mode test function = test function.
EXPLANATION:
The specified pin is a test function pin in the mode but not in the BSDL.
USER RESPONSE:
Add this pin to the BSDL compliance enable pin list or TAP port pin list as appropriate.
Alternatively, remove this pin from the test mode. See "IEEE 1149.1 Boundary Scan
Controls" in the Encounter Test: Guide 2: Testmodes for additional information.
WARNING (TJB-119): [Severe] The BSDL test function for pin name is not defined in
the mode.
BSDL test function = -TI|+TI.
EXPLANATION:

The specified pin is defined as a test function pin in the BSDL but it is not defined as a
test function pin in the testmode.
USER RESPONSE:
Rebuild the mode with the current BSDL or assign the pin the correct test function value
during mode build time. See "IEEE 1149.1 Boundary Scan Controls" in the Encounter
Test: Guide 2: Testmodes for additional information.
WARNING (TJB-120): The mode test function for pin name is not defined as a test function
in the BSDL. The mode test function is = test function. The mode test function is
defined for a Pseudo Primary Input (PPI). A Pseudo Primary Input can not have a test
function assignment in the BSDL. Assigning a Test Function to an internal node may not work
in the hardware.
EXPLANATION:
The specified pin is a Pseudo Primary Input Pin (PPI) which has the specified test
function assignment defined for the mode. A PPI test function pin assignment can not be
correlated to a test function pin assignment in the BSDL. The IEEE 1149.1 standard
limits test function pin assignments to primary input pins.
USER RESPONSE:
Instead of using design cut points and their corresponding Pseudo Primary Inputs, define
a compliance pattern that will disable the logic that has to be hidden from Encounter Test
applications. Then rebuild the test mode and rerun this application. See "Test Function
Pins for an 1149.1 Mode" in the Encounter Test: Guide 2: Testmodes for additional
information.
In rare cases, PPI test function pin assignments are necessary to enable the software
logic model to accurately reflect how the hardware will behave on power-up. From an
1149.1 compliance perspective, if the PPI logic state(s) can not be achieved by a simple
power-on of the device, then the device would be considered non-compliant. For
example, if a sequence of hardware events is required to achieve the defined PPI state,
then the device is considered non-compliant.
severity (TJB-201): [severity] A scan port type attribute statement is not

defined.
EXPLANATION:
The identified TAP_SCAN attribute statement is not defined and is required. Refer to
IEEE Standard 1149.1b-1994: B.8.9.
USER RESPONSE:

Define the required TAP_SCAN attribute statement. See "Test Function Pins for an
1149.1 Mode" in the Encounter Test: Guide 2:Testmodes for additional information.
severity (TJB-202): [severity] More than one scan port type attribute is
defined.
EXPLANATION:
Only one TAP_SCAN attribute of the indicated type may be defined.
USER RESPONSE:
Remove the scan port type attribute statement which is redundant or erroneous. See
"Test Function Pins for an 1149.1 Mode" in the Encounter Test: Guide 2:Testmodes
for additional information.
severity (TJB-203): [severity] The INSTRUCTION_LENGTH attribute has a value

less than 2. The instruction register must be at least two bits in length.
EXPLANATION:
The INSTRUCTION_LENGTH attribute has a length value of less than two. Refer to
IEEE Standard 1149.1b-1994: B.8.11.3 (a).
USER RESPONSE:
Correct the length value to be greater than two and rerun. The INSTRUCTION_LENGTH
attribute defines the length of the instruction register in bits. See "BSDL File" in the
Encounter Test: Guide 2:Testmodes.
severity (TJB-204): [severity] The INSTRUCTION_CAPTURE value is of length

actual length while the expected length is length.
EXPLANATION:
The length of the INSTRUCTION_CAPTURE value exceeds the instruction length
specified in the INSTRUCTION_LENGTH attribute. Refer to IEEE Standard 1149.1b-
1994: B.8.11.3 (g).
USER RESPONSE:
Determine the correct length of the instruction register and ensure that both the
INSTRUCTION_CAPTURE and INSTRUCTION_LENGTH have consistent lengths. See
"BSDL File" in the Encounter Test: Guide 2:Testmodes.
severity (TJB-205): [severity] The minimum length of the

INSTRUCTION_CAPTURE bit string is 2.
EXPLANATION:

The length of the INSTRUCTION_CAPTURE value must be at least 2 bits.

USER RESPONSE:
Correct the bit string length and rerun. See ""BSDL File" in the Encounter Test: Guide
2:Testmodes.
severity (TJB-207): [severity] No constant PIN_MAP_STRING statements are

defined.
EXPLANATION:
No constant PIN_MAP_STRING statement is defined in the BSDL. The information
recorded in the PIN_MAP_STRING statement is required for normal processing at the
tester hardware. If this information is not explicitly defined in the BSDL, then it will be
necessary to provided separately along with the BSDL file. Refer to IEEE Standard
1149.1b-1994: B.8.7.1.
USER RESPONSE:
Add a constant PIN_MAP_STRING statement to the BSDL. See "BSDL File" in the
severity (TJB-208): [severity] The minimum length for an

INSTRUCTION_OPCODE bit string is 2.
EXPLANATION:
The minimum length of an INSTRUCTION_OPCODE bit string is two bits. Refer to IEEE
Standard 1149.1b-1994: B.8.11.3.
USER RESPONSE:
Ensure that the INSTRUCTION_OPCODE bit strings are at least two bits. See "BSDL
File" in the Encounter Test: Guide 2:Testmodes.
severity (TJB-209): [severity] Bit string bit string is of length actual-

length while the expected length is length.
EXPLANATION:
The length of the bit string data must match the length specified in the
INSTRUCTION_LENGTH statement. Refer to IEEE Standard 1149.1b-1994: B.8.11.3
(b).
USER RESPONSE:
Correct the data in error to ensure a match of lengths. See "BSDL File" in the Encounter
Test: Guide 2:Testmodes.

severity (TJB-210): [severity] The statement name statement is considered

out of order since one or more statements which follow it should appear before it.
EXPLANATION:
The statements in a BSDL description must appear in the required order. The identified
statement is considered out of order since one or more statements which follow it should
appear before it. The required ordering of statements is defined by the IEEE Standard
1149.1b-1994 in rule B.8.1.1.
USER RESPONSE:
Review each occurrence of TJB-210 and make adjustments to the BSDL per rule
B.8.1.1. Rerun the BSDL parse to ensure the adjusted statement ordering is correct and
that there are no other errors with regard to statement ordering.
severity (TJB-211): [severity] An EXTEST instruction whose opcode value is all

zeros must be defined.
EXPLANATION:
An EXTEST instruction with an opcode value of all zeros must be defined for 1149.1
compliance. Refer to IEEE Standard 1149.1b-1994: B.8.11.3 (d).
USER RESPONSE:
Add the EXTEST instruction opcode value of all zeros to the INSTRUCTION_OPCODE
statement assuming it is implemented in the hardware. See "BSDL File" in the
severity (TJB-212): [severity] The EXTEST instruction is not defined in the

INSTRUCTION_OPCODE statement.
EXPLANATION:
The EXTEST instruction is a required for 1149.1 compliance, however, no EXTEST
instruction is defined in the INSTRUCTION_OPCODE statement.
Refer to IEEE Standard 1149.1-2001: B.8.11.3 (d).
USER RESPONSE:
Assuming it is implemented in the hardware, add the EXTEST instruction to the
severity (TJB-213): [severity] An EXTEST instruction whose opcode value is all

ones must be defined.
EXPLANATION:

An BYPASS instruction with an opcode value of all ones must be defined for 1149.1
compliance. Refer to IEEE Standard 1149.1b-1994:
B.8.11.3 (c).
USER RESPONSE:
Add the BYPASS instruction opcode value of all ones to the INSTRUCTION_OPCODE
statement assuming it is implemented in the hardware. See "IEEE 1149.1 Boundary
Scan Verification Results File" in the Encounter Test: Guide 3: Test Structures and
"BSDL File" in the Encounter Test: Guide 2:Testmodes.
severity (TJB-214): [severity] The SAMPLE instruction is not defined in the

EXPLANATION:
The SAMPLE instruction is a required for 1149.1 compliance, however, no SAMPLE
instruction is defined in the INSTRUCTION_OPCODE statement. Refer to IEEE
Standard 1149.1b-1994: B.8.11.3 (e).
USER RESPONSE:
Add the SAMPLE instruction to the INSTRUCTION_OPCODE statement assuming it is
implemented in the hardware. See ""BSDL File" in the Encounter Test: Guide
2:Testmodes.
severity (TJB-215): [severity] The PRELOAD instruction is not defined in the

EXPLANATION:
The PRELOAD instruction is a required for 1149.1-2001 compliance, however, no
PRELOAD instruction is defined in the INSTRUCTION_OPCODE statement.
Refer to IEEE Standard 1149.1-2001: B.8.11.3 (g).
USER RESPONSE:
Assuming it is implemented in the hardware, add the PRELOAD instruction to the
severity (TJB-216): [severity] No logical port statement is defined.

EXPLANATION:
A port statement which defines the logical ports of the chip is not defined in the BSDL.
This is a required statement. Refer to IEEE Standard 1149.1b-1994: B.8.3.

USER RESPONSE:
Add a logical port statement to the BSDL. See "BSDL File" in the Encounter Test:
Guide 2:Testmodes.
severity (TJB-217): [severity] The PRELOAD opcode (opcode) is not an opcode

defined for the SAMPLE instruction.
EXPLANATION:
The PRELOAD instruction and the SAMPLE instruction are required to have the same
opcodes when using COMPONENT CONFORMANCE STD_1149_1_1990 or
STD_1149_1_1993.
Refer to IEEE Standard 1149.1-2001: B.8.11.3 (h.2).
USER RESPONSE:
Ensure the PRELOAD instruction and the SAMPLE instruction have the same opcodes
defined.
severity (TJB-218): [severity] BSDL port name: port name referenced in the
BSDL statement type is not valid since it is not defined in the port statement.
EXPLANATION:
The BSDL port name in this statement should be defined in the logical port statement.
Refer to IEEE Standard 1149.1b-1994: B.8.7.3 (f) and B.8.10.3 (d.1).
USER RESPONSE:
Define the BSDL port name in the logical port statement. See "BSDL File" in the
severity (TJB-219): [severity] The port statement defines port: port name as a
vectored port and the BSDL statement type references it as bit.
EXPLANATION:
The port was determined to be a vectored port as defined in the logical port statement
yet it is not defined in this statement as a vectored port. Refer to IEEE Standard 1149.1b-
1994.
USER RESPONSE:
Validate the port name and ensure the use of indexes when defining and referencing
vectored ports. See "BSDL File" in the Encounter Test: Guide 2:Testmodes.

severity (TJB-220): [severity] The BSDL statement defines port: port name as a
vectored port and the port statement defines it as bit.
EXPLANATION:
The port was determined to be a NON-vectored port as defined in the logical port
statement yet it appears to be a vectored port within this statement. Refer to IEEE
Standard 1149.1b-1994: B.8.14.2 (f).
USER RESPONSE:
Validate the port name and ensure the use of indexes when defining and referring to
vectored ports. Do not index NON-vectored ports. See "BSDL File" in the Encounter
severity (TJB-221): [severity] In the BSDL statement type, for port: port
name, the index index number is outside the range specified in the logical port statement.
EXPLANATION:
The vectored ports index must be within the range specified in the logical port statement.
Refer to IEEE Standard 1149.1b-1994:
B.8.13.3 (f), B.8.14.2 (g), B.8.8.3 (f), B.8.9.3 (d).
USER RESPONSE:
Ensure the range specified is valid. Ensure the index specified is valid. See "BSDL File"
in the Encounter Test: Guide 2:Testmodes.
severity (TJB-223): [severity] BOUNDARY_REGISTER cell number cell

number is defined with a control cell of cell number, yet BOUNDARY_REGISTER cell
number cell number is not defined as a control cell.
EXPLANATION:
A boundary register cell was defined as being controlled by a another boundary register
cell which in turn was not defined as a control cell. Refer to IEEE Standard 1149.1b-
1994: B.8.14.2 (m).
USER RESPONSE:
The reference to the control cell may be wrong or the cell referenced as the control cell
needs to be defined as a control cell.
severity (TJB-224): [severity] Boundary-Scan Register Cell number cell

number is not in the BOUNDARY_REGISTER statement. However it is referenced as being a
control cell.

EXPLANATION:
A reference was made to a boundary-scan chain cell that does not exist. Refer to IEEE
Standard 1149.1b-1994: B.8.14.2 (m).
USER RESPONSE:
Ensure that the definition of control cell and references to control cells are correct in the
Boundary-Scan Register Description. See "BSDL File" in the Encounter Test: Guide
2:Testmodes.
severity (TJB-225): [severity] The length of the boundary register as defined by

the BOUNDARY_REGISTER statement is boundary register length and does not
equal the length of boundary length length defined by the BOUNDARY_LENGTH
statement.
EXPLANATION:
Either the length specified in the BOUNDARY_LENGTH statement is wrong or the
number of cells and/or cell numbering defined in the BOUNDARY_REGISTER statement
is wrong. There may be additional messages clarifying inconsistencies between the
BOUNDARY_LENGTH statement and the BOUNDARY_REGISTER statement. Refer to
IEEE Standard 1149.1b-1994: B.8.14.2 (b).
USER RESPONSE:
Boundary register cell numbers must be defined such that they are within the range of
zero to N-1, where N is the value of the length specified in the BOUNDARY_LENGTH
statement. Correct the length specified in the BOUNDARY_LENGTH statement or the
cell definitions in the BOUNDARY_REGISTER statement. See "Boundary Scan
Modeling" in the Encounter Test: Guide 2:Testmodes and ""BSDL File" in the
severity (TJB-226): [severity] Only one BSDL statement type statement is

expected. The first one is accepted, the others are ignored.
EXPLANATION:
Only one statement of this is expected in a BSDL file.
USER RESPONSE:
Eliminate duplicate BSDL statement (s).
severity (TJB-227): [severity] The PHYSICAL_PIN_MAP string value of value

does not have a constant PIN_MAP_STRING defined.
EXPLANATION:

A constant PIN_MAP_STRING statement is not defined in the BSDL.

USER RESPONSE:
Define one or more constant PIN_MAP_STRING statements. One such statement must
have the name defined in the PHYSICAL_PIN_MAP statement. See ""BSDL File" in the
severity (TJB-228): [severity] An array size mismatch between the logical port
statement and the CONSTANT pin mapping statement exists for BSDL port: port name
The logical port statement indicates a size of size, while the size specified in CONSTANT
pin mapping port is size.
EXPLANATION:
There is a mismatch between the vector size of a port. In the logical port statement it is
depicted as one size and in the CONSTANT pin mapping statement it is depicted as
another size. Refer to IEEE Standard 1149.1b-1994: B.8.7.3 (c), B.8.7.3 (d).
USER RESPONSE:
Ensure that there is a direct correlation for vectored port names between the logical port
statement and the CONSTANT pin map statement. See "BSDL File" in the Encounter
severity (TJB-229): [severity] BSDL port: port name is in the logical port
statement, but it is not defined in the constant PIN_MAP_STRING statement.
EXPLANATION:
A BSDL port is not in the constant PIN_MAP_STRING yet it is in the logical port
statement.
USER RESPONSE:
Include the port in the constant PIN_MAP_STRING statement. See "BSDL File" in the
severity (TJB-230): [severity] The INSTRUCTION_CAPTURE value value does

not end in 01.
EXPLANATION:
The last two bits in the INSTRUCTION_CAPTURE value should end in 01. Refer to IEEE
Standard 1149.1b-1994: B.8.11.3 (g.2).
USER RESPONSE:

Check the validity of the INSTRUCTION_CAPTURE value and correct it. See "BSDL
File" in the Encounter Test: Guide 2:Testmodes.
severity (TJB-231): [severity] The first Boundary-Scan Register Cell number is not
cell number 0, it is cell number cell number. Cell number 0 is expected to be the first
Boundary-Scan Register cell.
EXPLANATION:
The first cell in a Boundary-Scan Register chain should be cell number 0.
USER RESPONSE:
Re-write the Boundary-Scan Register chain so that it starts with cell number 0.
severity (TJB-232): [severity] Port: portname is defined in the model but not
defined in the BSDL Test_Port_Alias or port statements.
EXPLANATION:
The identified port is defined in the logic model but not the BSDL. This is an indication of
an incomplete or inappropriate BSDL file (e.g The wrong BSDL file for the circuit).
In this context, a BSDL port is an input, output, or bidirectional pin.
Read BSDL is attempting to correlate each logic model port (pin) to a port in the BSDL
Test_Port_Alias and or port statements.
A BSDL Test_Port_Alias provides a mapping of logic model port names to BSDL port
names, particularly when the logic model port name would result in invalid BSDL syntax.
USER RESPONSE:
The Read BSDL tool can be used to automatically generate BSDL for the circuit.
The generated BSDL will contain a logical port statement which corresponds to the
loaded logic model. The generated BSDL will also contain a Test_Port_Alias statement
if the logic model port names are not BSDL legal port names. The generated BSDL can
then be updated from the original BSDL to carry forward BSDL information not
automatically generated. Alternatively, the logical port statement and optional
Test_Port_Alias statements in the generated BSDL can be carried back to the original
BSDL. The updated/corrected BSDL file should be parsed to ensure the discrepancies
between the BSDL port statement and the logic model have been resolved.
severity (TJB-233): [severity] The BSDL port: port name does not exist as a
primary input or primary output pin in the model.
EXPLANATION:

The identified BSDL port was not found as a primary input pin or primary output pin in
the logic model. In this context, a BSDL port is equivalent to a primary input or primary
output. BSDL parser is attempting to correlate each BSDL port to a primary input or
output pin in the logic model.
USER RESPONSE:
The Read BSDL tool can be used to automatically generate BSDL for the circuit. The
generated BSDL will contain a logical port statement which corresponds to the logic
model. The generated BSDL can then be updated from the original BSDL to carry
forward BSDL information not automatically generated. Alternatively, the logical port
statement in the generated BSDL can be carried back to the original BSDL. In the latter
case, the BSDL should also be reviewed for additional port name references to ensure
they too are correct.
See "Creating BSDL" in the Encounter Test: Guide 2:Testmodes for additional
information.
severity (TJB-234): [severity] The IDCODE or USERCODE Register value:

value has a length of length, where a length of length is expected.
EXPLANATION:
The length of the IDCODE or USERCODE Register should be 32 bits.
USER RESPONSE:
Correct the length of the Register to be 32 bits long.
severity (TJB-235): [severity] A 1 is expected as the last bit in the IDCODE

Register. Value is: value.
EXPLANATION:
The last bit (right-most) of the IDCODE Register should be a 1. Refer to IEEE Standard
1149.1b-1994: B.8.12.3 (a).
USER RESPONSE:
Change the last (right-most) of the IDCODE Register to be a 1.
severity (TJB-236): [severity] The port direction of BSDL port port name, is
inconsistent with the port direction defined in the model.
EXPLANATION:
The BSDL ports direction is not consistent with the ports direction in the model.
USER RESPONSE:

Either the BSDLs port direction is wrong or the logic models port direction is wrong.
Analyze to determine which is wrong, correct it and rerun.
severity (TJB-237): [severity] A USERCODE_REGISTER is defined without the

definition of the IDCODE and/or USERCODE instructions.
EXPLANATION:
Definition of a USERCODE_REGISTER requires that both an IDCODE and
USERCODE instruction be defined. Refer to IEEE Standard 1149.1b-1994: B.8.12.3 (c).
USER RESPONSE:
Add/remove the appropriate information to/from the BSDL. See "BSDL File" in the
severity (TJB-238): [severity] No INSTRUCTION_LENGTH statement is defined.

EXPLANATION:
An INSTRUCTION_LENGTH statement which defines the length of the instruction
register is not defined in the BSDL. This is a required statement. Refer to IEEE Standard
1149.1b-1994: B.8.11.
USER RESPONSE:
Add an INSTRUCTION_LENGTH statement to the BSDL.
See ""BSDL File" in the Encounter Test: Guide 2:Testmodes.
severity (TJB-239): [severity] No INSTRUCTION_OPCODE statement is defined.

EXPLANATION:
An INSTRUCTION_OPCODE statement which defines the instruction opcode values is
not defined in the BSDL. This is a required statement. Refer to IEEE Standard 1149.1b-
1994: B.8.11.
USER RESPONSE:
Add an INSTRUCTION_OPCODE statement to the BSDL.
See "BSDL File" in the Encounter Test: Guide 2:Testmodes.
severity (TJB-241): [severity] COMPLIANCE_PATTERNS port: port name is

defined in the statement type statement.
EXPLANATION:

COMPLIANCE_PATTERNS port is defined in the identified statement which is in

violation of the standard. Refer to IEEE Standard 1149.1b-1994: B.8.10.3 (g).
USER RESPONSE:
Remove the identified COMPLIANCE_PATTERNS port from the identified statement.
severity (TJB-243): [severity] The COMPLIANCE_PATTERNS attribute is defined

with number ports, yet the compliance pattern length is length.
EXPLANATION:
The number of ports in the Compliance Pattern attribute should equal the number of
patterns in the Compliance Pattern attribute. Refer to IEEE Standard 1149.1b-1994:
B.8.10.3 (a).
USER RESPONSE:
Ensure that the number of ports equals the number of patterns.
severity (TJB-244): [severity] Compliance Enable port name compliance

enable port name does not appear in the Compliance Pattern port list.
EXPLANATION:
The Compliance Enable port name should appear in the Compliance Pattern port list.
USER RESPONSE:
Ensure that all Compliance Enable port names appear in the Compliance Pattern port
list.
severity (TJB-245): [severity] The COMPLIANCE_PATTERN port name: name

appears more than once in the COMPLIANCE_PATTERN port list.
EXPLANATION:
Duplicate Compliance Pattern port names exist in the Compliance Pattern port list. Refer
to IEEE Standard 1149.1b-1994: B.8.10.3 (b).
USER RESPONSE:
Eliminate the duplicate compliance pattern port names.
severity (TJB-246): [severity] Compliance Pattern port name: compliance

pattern port name also appears as a TAPtype port name.

EXPLANATION:
A TAP port should not be used as a Compliance Pattern port. Refer to IEEE Standard
1149.1b-1994: B.8.10.3 (c).
USER RESPONSE:
Ensure correct port names in both the TAP attributes and the Compliance Pattern port
names.
See "Test Function Pins for an 1149.1 Mode" in the Encounter Test: Guide
2:Testmodes.
severity (TJB-247): [severity] BSDL port: portname

in the statement type should be specified as type modetype, yet in the port statement
it is defined as type modetype.
EXPLANATION:
The BSDL port direction/type specified in this statement is inconsistent with the direction/
type defined in the logical port statement. Refer to IEEE Standard 1149.1b-1994:
B.8.10.3 (d.2). B.8.9.3 (a.1), B.8.9.3 (a.2).
USER RESPONSE:
Correct either the statements port direction or the logical port description statements
direction/type.
severity (TJB-248): [severity] BSDL port name: port name is defined in the
logical port statement but does not appear in the BOUNDARY_REGISTER statement.
EXPLANATION:
All data ports defined in the logical port statement are expected to be in the
BOUNDARY_REGISTER statement. Refer to IEEE Standard 1149.1b-1994: B.8.14.2
(q).
USER RESPONSE:
Ensure that all data ports represented in the logical port are identical to those in the
BOUNDARY_REGISTER statement (description).
severity (TJB-249): [severity] BSDL port name: port name appears in the
logical port statement more than once.
EXPLANATION:
The same BSDL port name appears more than once in the logical port description
statement. Only one is expected. Refer to IEEE Standard 1149.1b-1994: B.8.3.3 (b).

USER RESPONSE:
Ensure there are no duplicate BSDL port names in the logical port description statement.
severity (TJB-250): [severity] The PORT_GROUPING port name: grouped

port name appears in the logical port statement as type linkage.
EXPLANATION:
A Grouped Port port name should not appear in the logical port description statement as
type linkage. Refer to IEEE Standard 1149.1b-1994: B.8.8.3 (a).
USER RESPONSE:
Validate the use of the port name in both the Grouped Port statement and the logical port
statement.

severity (TJB-251): [severity] The TAP port name: TAP port name appears in
more than one of the TAP attribute statements.
EXPLANATION:
The TAP port name exists in more than one of the TAP attribute statements specified in
the BSDL. Refer to IEEE Standard 1149.1b-1994: B.8.9.3 (c).
USER RESPONSE:
Ensure that the port names used in each of the TAP attribute statements are unique
(used only once).
severity (TJB-252): [severity] Boundary-Scan Cell number cell number in the

Boundary-Scan Register Description has an invalid merge combination. One of the merged
cells does not have an INPUT function.
EXPLANATION:
Cell function merges for this cell should include a function of INPUT for one of the cells
to be merged. Refer to IEEE Standard 1149.1b-1994: B.8.14.2 (d.1).
USER RESPONSE:
Validate cell functions defined in the merged entries and correct the error(s).


Boundary-Scan Register Description has an invalid merge combination. Cell function merges
of INPUT and function type are illegal.
EXPLANATION:
Cell function merges of INPUT and certain function types are illegal in the Boundary-
Scan Register Description. Refer to IEEE Standard 1149.1b-1994: B.8.14.2 (d.1).
USER RESPONSE:
Validate the cell functions defined in the merged entries and correct the error(s).

Boundary-Scan Register Description has a port name of *(asterisk) and a function of
function. This combination is illegal.
EXPLANATION:
The combination of this function and port name of * (asterisk) is illegal. Refer to IEEE
Standard 1149.1b-1994: B.8.14.2 (h).
USER RESPONSE:
Validate both the function and port name for this entry.

Boundary-Scan Register Description does not have any disable data associated with it.
EXPLANATION:
Disable data should appear for this Boundary-Scan Cell number in the Boundary-Scan
Register Description. Refer to IEEE Standard 1149.1b-1994: B.8.14.2 (j).
USER RESPONSE:
Validate the need for Disable data and append it within the Boundary-Scan Register
Description.
See "Boundary Scan Modeling" in the Encounter Test: Guide 2:Testmodes.
severity (TJB-256): [severity] The differential type representative port:

representative port name in the PORT_GROUPING statement is not in the
BOUNDARY_REGISTER statement.
EXPLANATION:

The representative port in the Port Grouping statement is in the Boundary-Scan Register
Description. Refer to IEEE Standard 1149.1b-1994: B.8.8.3 (c).
USER RESPONSE:
If this is a severe message, validate the use of this port in the Port Grouping statement
and the Boundary-Scan Register Description.
See "Boundary Scan Modeling" in the Encounter Test: Guide
2:TestmodesEncounter Test: Guide 2:Testmodes.
severity (TJB-257): [severity] The differential type associated port:

port name in the PORT_GROUPING statement is in the BOUNDARY_REGISTER
statement.
EXPLANATION:
The associated port in the Port Grouping statement is in the Boundary-Scan Register
Description. Refer to IEEE Standard 1149.1b-1994: B.8.8.3 (d).
USER RESPONSE:
If this is a severe message, validate the use of this port in the Port Grouping statement
and the Boundary-Scan Register Description.
See "Boundary Scan Modeling" in the Encounter Test: Guide 2:Testmodes.
severity (TJB-258): [severity] The BSDL statement port: port name is in

the BOUNDARY_REGISTER statement.
EXPLANATION:
The BSDL port is in both the Boundary-Scan Register Description and in the BSDL
statement. Refer to IEEE Standard 1149.1b-1994:
B.8.10.3 (e), B.8.9.3 (b).
USER RESPONSE:
If this is a severe message, validate the use of this port name and eliminate it from either
the BSDL statement or the Boundary-Scan Register Description.
severity (TJB-259): [severity] There is no extension parameter string associated

with count BSDL Extension statement(s) named Test_TAP_LATCH.
EXPLANATION:
The BSDL Extension statement has no extension data associated with it.
USER RESPONSE:

Validate and append extension data if necessary.

See "BSDL Extension - Port Alias" in the Encounter Test: Guide 2:Testmodes.
severity (TJB-260): [severity] There is more than one pattern specified in the
COMPLIANCE_PATTERNS attribute. Only the first pattern will be used in defining the 1149.1
test mode.
EXPLANATION:
Only one pattern should be specified in the Compliance Pattern attribute. Therefore the
first one (by default) is used.
USER RESPONSE:
If the default is acceptable, no action is required. Otherwise, validate the Compliance
Patterns specified.
See "Test Function Pins for an 1149.1 Mode" in the Encounter Test: Guide
2:Testmodes.
severity (TJB-261): [severity] In the TAP LATCH BSDL Extension statement, the
cell name cell name is not in the model.
EXPLANATION:
TAP LATCH BSDL port (cell) names should exist in the logic model for proper correlation.
USER RESPONSE:
Ensure that the proper port names were specified in the TAP LATCH BSDL Extension
statement and that the correct logic model is being used.

number is defined as a control cell, yet no other cell references it as a control cell.
EXPLANATION:
Semantic Check B.8.14.2 (l) requires that if a cell is defined as a CONTROL or
CONTROLR cell, then some other cell must refer to that cell as its controlling cell. Refer
to IEEE Standard 1149.1b-1994: B.8.14.2 (l).
USER RESPONSE:
Ensure that the identified cell is a control cell and identify the cell(s) it controls. A
boundary scan control cell must control at least one cell.
severity (TJB-263): [severity] In the package name PIN_MAP_STRING, the

port name port name appears more than once.

EXPLANATION:
Physical port names must be unique in the PIN_MAP_STRING attribute.
USER RESPONSE:
Ensure that physical port names in the PIN_MAP_STRING attribute are unique.
severity (TJB-264): [severity] In the package name PIN_MAP_STRING, the

physical port number port number appears more than once.
EXPLANATION:
Physical port numbers must be unique in the PIN_MAP_STRING attribute. Refer to IEEE
Standard 1149.1b-1994: B.8.7.3 (a).
USER RESPONSE:
Ensure that physical port numbers in the PIN_MAP_STRING attribute are unique.
severity (TJB-265): [severity] The Boundary-Scan Register Description port:

boundary scan chain port name has a pin type of IN specified in the logical port
statement yet it does not have a function of either INPUT, CLOCK or OBSERVE_ONLY.
EXPLANATION:
A Boundary-Scan Register Description port with a pin type of IN (in the logical port
statement) should have a function of either INPUT, CLOCK or OBSERVE_ONLY in the
Boundary-Scan Register Description. Refer to IEEE Standard 1149.1b-1994: B.8.14.2
(s.1).
USER RESPONSE:
Validate the ports pin type and the ports function type.

boundary scan chain port name has a pin type of OUT specified in the logical port
statement yet it does not have a function of either OUTPUT2 or OUTPUT3.
EXPLANATION:
A Boundary-Scan Register Description port with a pin type of OUT (in the logical port
statement) should have a function of either OUTPUT2 or OUTPUT3 in the Boundary-
Scan Register Description. Refer to IEEE Standard 1149.1b-1994: B.8.14.2 (s.2).
USER RESPONSE:


boundary scan chain port name has a pin type of BUFFER specified in the logical port
statement yet it does not have a function of OUTPUT2.
EXPLANATION:
A Boundary-Scan Register Description port with a pin type of BUFFER (in the logical port
statement) should have a function type of OUTPUT2 in the Boundary-Scan Register
Description. Refer to IEEE Standard 1149.1b-1994: B.8.14.2 (s.3).
USER RESPONSE:
severity (TJB-268): [severity] The port: port name is defined with a pin type of
buffer and is defined in BOUNDARY_REGISTER cell boundary register cell
number with a disable spec. Ports defined with type buffer can not have a disable spec
defined in the BOUNDARY_REGISTER.
EXPLANATION:
Semantic Check B.8.14.2 (s.2) port defined in the BOUNDARY_REGISTER which has a
pin type of buffer can be defined with boundary register cell function of OUTPUT2 only
and can not have a disable spec. Refer to IEEE Standard 1149.1b-1994: B.8.14.2 (s.3.2).
USER RESPONSE:
A two state driver which can be driven to an inactive state (e.g. weak1), should be defined
with a pin type of out in port statement and have a disable spec defined the
BOUNDARY_REGISTER statement. A two state driver which can not be driven to an
inactive state from a control cell, should be defined with a pin type of buffer in port
statement and not have a disable spec defined in the BOUNDARY_REGISTER
statement.

boundary scan chain port name has a pin type of INOUT specified in the logical
port statement yet it does not have a function of either BIDIR,OUTPUT2, OUTPUT3, INPUT
or OBSERVE_ONLY.
EXPLANATION:
A Boundary-Scan Register Description port of type INOUT in the logical port statement
should have a function of either BIDIR,OUTPUT2, OUTPUT3, INPUT or
OBSERVE_ONLY. Refer to IEEE Standard 1149.1b-1994: B.8.14.2 (s.4).
USER RESPONSE:
Correct either the type or the function for this port.


boundary scan chain port name is of type OUT in the logical port statement and it
has more than one Boundary Register cell entry with the function OUTPUT2 or OUTPUT3
specified.
EXPLANATION:
A Boundary-Scan Register Description port of type OUT can only have one Boundary
Register cell entry with the function of OUTPUT2 or OUTPUT3. Refer to IEEE Standard
1149.1b-1994: B.8.14.2 (s.2.2).
USER RESPONSE:
Eliminate the duplicate cell entries with function of OUTPUT2 or OUTPUT3 for this port.

boundary scan chain port name is of type BUFFER in the logical port statement
and it has more than one Boundary Register cell entry with the function OUTPUT2 specified.
EXPLANATION:
A Boundary-Scan Register Description port of type BUFFER in the logical port statement
can only have one Boundary Register cell entry with the function of OUTPUT2. Refer to
IEEE Standard 1149.1b-1994: B.8.14.2 (s.3.3).
USER RESPONSE:
Eliminate the duplicate cell entries with function of OUTPUT2 for this port.

boundary scan chain port name is of type INOUT in the logical port statement and
has function of BIDIR in the Boundary-Scan Register Description, only ONE Boundary
Register cell entry for this port name can appear as a Boundary Register cell entry with the
function BIDIR, OUTPUT2 or OUTPUT3. More than one cell entry was detected.
EXPLANATION:
and a function of BIDIR in the Boundary-Scan Register should only have one Boundary
Register cell entry with the function BIDIR, OUTPUT2 or OUTPUT3. Refer to IEEE
Standard 1149.1b-1994: B.8.14.2 (s.4.2).
USER RESPONSE:
Eliminate duplicate cell entries for this port with a function of BIDIR, OUTPUT2 or
OUTPUT3.


boundary scan chain port name is of type INOUT in the logical port statement and
has function of OUTPUT2 or OUTPUT3 in the Boundary-Scan Register Description, only
ONE Boundary Register cell entry for this port name can appear as a Boundary Register cell
entry with the function OUTPUT2 or OUTPUT3. More than one cell entry was detected.
EXPLANATION:
and a function of OUTPUT2 or OUTPUT3 in the Boundary-Scan should only have one
Boundary Register cell entry with the function OUTPUT2 or OUTPUT3. Refer to IEEE
Standard 1149.1b-1994: B.8.14.2 (s.4.3).
USER RESPONSE:
Eliminate duplicate cell entries for this port with a function of OUTPUT2 or OUTPUT3.
severity (TJB-274): [severity] Since the port: port name in logical port
statement is defined as inout in the port statement and is defined as having a cell function
of OUTPUT2 or OUTPUT3 in the BOUNDARY_REGISTER statement, this port requires an
additional boundary register cell whose cell function is either INPUT or OBSERVE_ONLY.
EXPLANATION:
The logical port statement defines the port as type INOUT while the
BOUNDARY_REGISTER description statement defines the cell associated with this port
as either OUTPUT2 or OUTPUT3. If the I/O buffer for the port can and should be
exercised bidirectionally in the 1149.1 design state, then the boundary register
implementation should include a input capable cell for the identified port and the BSDL
should refer to the ports input cell. If the I/O buffer for the port should be configured as
unidirectional output in the 1149.1 state, then the boundary register implementation and
the BSDL is fine as defined. Refer to IEEE Standard 1149.1b-1994: B.8.14.2 (s.4.4).
USER RESPONSE:
Review the IEEE 1149.1 boundary register cell requirements for bidirectional pins.
Determine how the pin should be exercised in the 1149.1 design state and ensure that
the boundary register implementation and BSDL specification support the intended use
of the pin.

BOUNDARY_REGISTER statement has a function name of function name and does not
have a port value of asterisk (*).
EXPLANATION:

A Boundary-Scan Cell number with the specified function should have a port value of *
(asterisk). Refer to IEEE Standard 1149.1b-1994: B.8.14.2 (h).
USER RESPONSE:
Validate the Boundary-Scan Cell number and its port value.

number is defined with a cell function of cell function name and also contains a
disable specification.
EXPLANATION:
The BOUNDARY_REGISTER cell number with the specified function can not have
disable data defined for it. Refer to IEEE Standard 1149.1b-1994: B.8.14.2 (i).
USER RESPONSE:
Validate the BOUNDARY_REGISTER cell function to determine whether it is
appropriate.
severity (TJB-277): [severity] BSDL port: port name is defined as type linkage
and is defined in BOUNDARY_REGISTER cell number cell number.
EXPLANATION:
The identified port is defined as type linkage in the logical port statement and is
referenced as port in the BOUNDARY_REGISTER statement. Linkage ports can not be
members of the boundary register. Refer to IEEE Standard 1149.1b-1994: B.8.14.2 (p.1),
B.8.14.2 (p.2).
USER RESPONSE:
Validate the type of the identified port and adjust the BOUNDARY_REGISTER cell
description as appropriate.
severity (TJB-278): [severity] BSDL port: port name is defined in the

BOUNDARY_REGISTER statement and not defined in the port statement.
EXPLANATION:
The identified port is defined in the BOUNDARY_REGISTER statement and not in the
logical port statement. Refer to IEEE Standard 1149.1b-1994: B.8.14.2 (o).
USER RESPONSE:
Correct the identified port name in the BOUNDARY_REGISTER statement and or add
the identified port to the logical port statement.

severity (TJB-279): [severity] BSDL port: portname is defined as inout and has
no control cell defined in the BOUNDARY_REGISTER statement.
EXPLANATION:
The identified port is defined as inout in the logical port statement and has an OUTPUT2
or OUTPUT3 cell in the BOUNDARY_REGISTER statement but has no control cell
defined in the BOUNDARY_REGISTER statement.
USER RESPONSE:
A bidirectional pin must have an associated control cell if the pin is not bidir, then change
the port type in the logical port statement to either buffer or out.
severity (TJB-280): [severity] A Hierlevel BSDL file is expected. Of the list of BSDL
files inputted into this program, a BSDL file containing an entity name of entity name must
appear. Insert the BSDL into your list of BSDL and rerun.
EXPLANATION:
One hierlevel BSDL file is expected. The entity name in the hierlevel BSDL file must
match that of the hiermodels top block (block 0) cell name. The hierlevel BSDL file
should correlate to the ports/pins on the top block.
USER RESPONSE:
Insert the hierlevel BSDL file and rerun.
severity (TJB-281): [severity] Only one Hierlevel BSDL file is expected, however,
more than one BSDL file contains an entity name of: entity name indicating that it is a
hierlevel BSDL file.
EXPLANATION:
Only one BSDL file containing the hierlevel BSDL entity name should appear amongst
the input BSDL files specified.
The hierlevel BSDL file should correlate to the ports/pins on the top block in the logic
model.
USER RESPONSE:
Remove the unnecessary BSDL files from your list of BSDL files and rerun.
severity (TJB-282): [severity] There are no BSDL files to consider for this run.
Check the input BSDL file(s) for validity.
EXPLANATION:

No BSDL input files processed.

USER RESPONSE:
Ensure that all BSDL paths and BSDL names are correct.
severity (TJB-283): [severity] Total number of BSDL files processed: count

EXPLANATION:
Total number of BSDL files processed for this run.
USER RESPONSE:
severity (TJB-284): [severity] There are fewer than two BSDL files for this
application.
EXPLANATION:
Less than 2 BSDL files were processed for this run.
USER RESPONSE:
This may or may not be desirable. Ensure that the all BSDL files required for this run were
specified as input.
severity (TJB-285): [severity] No standard use statement is defined.

EXPLANATION:
At least one standard package file must be specified via the use statement in the BSDL.
One such file is the STD_1149_1_1994 package file. Example use statement syntax is:
use STD_1149_1_1994.all; Your installation should have the IEEE 1149.1 standard
package file shipped with the installation package. Refer to IEEE Standard 1149.1b-
1994: B.8.4.
USER RESPONSE:
Add a use statement to the BSDL file which refers to one of the IEEE 1149.1 standard
package files. If the BSDL needs to refer to additional user defined package files, then
their use statements must appear after any use statements referencing IEEE 1149.1
standard use statements.
severity (TJB-286): [severity] No COMPONENT_CONFORMANCE statement is

defined, or is defined with a non-compliant conformance string value. Component is assumed
to conform to STD_1149_1_1993.

EXPLANATION:
A BSDL file is required to contain a COMPONENT_CONFORMANCE attribute statement
which identifies the edition of the standard to which the circuitry of the component
conforms. Further, the string value defined by the COMPONENT_CONFORMANCE attribute
must be STD_1149_1_1993 or STD_1149_1_2001. Refer to IEEE Standard 1149.1b-
1994: B.8.6.
USER RESPONSE:
Add a COMPONENT_CONFORMANCE statement to the BSDL to the BSDL file which
identifies the edition of the standard to which the circuitry of the component conforms.
Example syntax is: attribute COMPONENT_CONFORMANCE of <entity name>: entity is
"STD_1149_1_1993";
severity (TJB-287): [severity] No INSTRUCTION_CAPTURE statement is

defined.
EXPLANATION:
An INSTRUCTION_CAPTURE statement which defines the instruction register capture
value is not defined in the BSDL. This is a required statement. Refer to IEEE Standard
1149.1b-1994: B.8.11.
USER RESPONSE:
Add an INSTRUCTION_CAPTURE statement to the BSDL. See "BSDL File" in the
severity (TJB-288): [severity] No BOUNDARY_LENGTH statement is defined.

EXPLANATION:
A BOUNDARY_LENGTH statement which defines the length of the boundary register is
not defined in the BSDL. This is a required statement. Refer to IEEE Standard 1149.1b-
1994: B.8.14.2.
USER RESPONSE:
Add a BOUNDARY_LENGTH statement to the BSDL. See "Boundary Scan Modeling"in
the Encounter Test: Guide 2:Testmodes.
severity (TJB-289): [severity] No BOUNDARY_REGISTER statement is defined.

EXPLANATION:

A BOUNDARY_REGISTER statement which defines the functional make-up of the

boundary register is not defined in the BSDL. This is a required statement. Refer to IEEE
Standard 1149.1b-1994: B.8.14.2.
USER RESPONSE:
Add a BOUNDARY_REGISTER statement to the BSDL. See "Boundary Scan Modeling"
in the Encounter Test: Guide 2:Testmodes and "BSDL File" in the Encounter Test:
Guide 2:Testmodes.
severity (TJB-290): Since the port: port name is defined as inout in the port statement
and is defined as having a cell function of INPUT or OBSERVE_ONLY in the
BOUNDARY_REGISTER statement, this port requires an additional boundary register cell
whose cell function is either OUTPUT2 or OUTPUT3.
EXPLANATION:
The logical port statement defines the port as type INOUT while the
BOUNDARY_REGISTER description statement defines the cell associated with this port
as either INPUT or OBSERVE_ONLY. If the I/O buffer for the port can and should be
exercised bidirectionally in the 1149.1 design state, then the boundary register
implementation should include a output capable cell for the identified port and the BSDL
should refer to the ports output cell. If the I/O buffer for the port should be configured as
unidirectional input in the 1149.1 state, then the boundary register implementation and
the BSDL is fine as defined. Refer to IEEE Standard 1149.1b-1994: B.8.14.2 (s.4.5).
USER RESPONSE:
Review the IEEE 1149.1 boundary register cell requirements for bidirectional pins.
Determine how the pin should be exercised in the 1149.1 design state and ensure that
the boundary register implementation and BSDL specification support the intended use
of the pin.
INFO (TJB-298): Summary of semantic check severities for this BSDL:

Informationals: count
Warnings : count
Severe Errors : count
EXPLANATION:
Summary of semantic check severities.
USER RESPONSE:
INFO (TJB-299): The highest severity from this run is: severity.

EXPLANATION:
Highest severity from the run.
USER RESPONSE:
severity (TJB-300): [severity] The public instruction instruction name does

not have an associated test data register defined.
EXPLANATION:
Semantic Check B.8.13.3 (b) requires that all non-standard public instructions defined in
the INSTRUCTION_OPCODE statement $ must have an associated test data register
defined in the REGISTER_ACCESS statement. Refer to IEEE Standard 1149.1b-1994:
B.8.13.3 (b).
USER RESPONSE:
Define the associated test data register for the public instruction identified.

severity (TJB-301): [severity] The REGISTER_ACCESS description for test data
register register name has an invalid register length.
EXPLANATION:
Semantic Check B.8.13.3 (c) requires the length of each publicly accessible design-
specific test data register has to be specified and has to be greater than 0; if the register
is specified more than once in the REGISTER_ACCESS, then the first appearance has
to define the length, and subsequent appearances may either not define it again or define
it identically. Refer to IEEE Standard 1149.1b-1994: B.8.13.3 (c).
USER RESPONSE:
Correct the test data register access length to meet the above guidelines for the register
identified.

register register name has a data register capture value of capture val for
instruction, instruction name, which does not contain the same number of bits as the
defined register length of length.
EXPLANATION:

Semantic Check B.8.13.3 (f) requires the CAPTURES pattern value for an instruction
specified in the REGISTER_ACCESS statement has to contain the same number of bits
as the length its associated data register. Refer to IEEE Standard 1149.1b-1994:
B.8.13.3 (f).
USER RESPONSE:
Correct the length of the data register capture value for the instruction and data register
identified. The data register capture value must contain exactly the same number of bits
as the defined length of the test data register to which it applies. The CAPTURES item
of the REGISTER_ACCESS is optional. An X is an acceptable capture value.
severity (TJB-303): [severity] The instruction name instruction is defined

as a private, however it is not a user defined instruction.
EXPLANATION:
Semantic Check B.8.11.3 (h) requires that only user defined instructions can be defined
as private instructions. The identified instruction is a standard instruction. Refer to IEEE
Standard 1149.1b-1994: B.8.11.3 (h).
USER RESPONSE:
Only define non-standard user defined instructions as private.
severity (TJB-304): [severity] The RUNBIST_EXECUTION statement defines the

length of the EXPECT_DATA as expect data length. However, the length of the expect
data differs from the length of the data register (register name) accessed by the
RUNBIST instruction as defined in the REGISTER_ACCESS statement. The
length_type defines the length of the register accessed by the RUNBIST instruction as
register length.
EXPLANATION:
Semantic Check B.8.15.3 (a) requires that the number of bits in the EXPECT_DATA
defined in the RUNBIST_EXECUTION statement match the number of bits defined as
the length of the register accessed by the RUNBIST instruction as defined in the
REGISTER_ACCESS statement. Refer to IEEE Standard 1149.1b-1994: B.8.15.3 (a).
USER RESPONSE:
Ensure the RUNBIST expect data contains the same number of bits as the length of the
test data register accessed by the RUNBIST instruction.
severity (TJB-305): [severity] The RUNBIST_EXECUTION statement is specified

in the BSDL, but an instruction name of RUNBIST is not found in the

EXPLANATION:
Semantic Check B.8.15.3 (c) requires that if a RUNBIST_EXECUTION statement is
defined in the BSDL description, the RUNBIST has to be the name of some instruction
in the INSTRUCTION_OPCODE statement. Refer to IEEE Standard 1149.1b-1994.
Refer to IEEE Standard 1149.1b-1994: B.8.15.3 (c).
USER RESPONSE:
Either specify RUNBIST as instruction name in the INSTRUCTION_OPCODE statement
or remove the RUNBIST_EXECUTION statement from the BSDL.
severity (TJB-306): [severity] The length of the boundary register specified in the
BOUNDARY_LENGTH statement is not greater than zero.
EXPLANATION:
Semantic Check B.8.14.2 (a) requires the value of the integer (length) in the
BOUNDARY_LENGTH statement has to be greater than zero. Refer to IEEE Standard
1149.1b-1994: B.8.14.2 (a).
USER RESPONSE:
Specific a valid length (greater than 0) in the BOUNDARY_LENGTH statement.
severity (TJB-307): [severity] The BOUNDARY_REGISTER statement has a cell

number specified of cell number which is greater than N-1, where N is boundary length
number (the value of the length specified in the BOUNDARY_LENGTH statement).
EXPLANATION:
Semantic Check B.8.14.2 (b) states that every cell number of the
BOUNDARY_REGISTER statement must have a value in the range of zero to N-1, where
N is the value of the length specified in the BOUNDARY_LENGTH statement. Refer to
IEEE Standard 1149.1b-1994: B.8.14.2 (b).
USER RESPONSE:
Specify a cell number that is within the range of zero to N-1, where N is the value of the
length specified in the BOUNDARY_LENGTH statement.
severity (TJB-308): [severity] The BOUNDARY_REGISTER statement does not

contain a cell number of cell number. Every integer with a value between zero and N-1
(where N is the value of the length specified in the BOUNDARY_LENGTH statement) has to
appear as a cell number in some cell entry of the BOUNDARY_REGISTER statement.
EXPLANATION:

Semantic Check B.8.14.2 (c) requires that every integer with a value between zero and
N-1 (where N is the value of the length specified in the BOUNDARY_LENGTH
statement) has to appear as a cell number in some cell entry of the
BOUNDARY_REGISTER statement. Refer to IEEE Standard 1149.1b-1994: B.8.14.2
(c).
USER RESPONSE:
Define a BOUNDARY_REGISTER cell entry for the missing cell number or adjust the
length specified in the BOUNDARY_LENGTH statement.
severity (TJB-309): [severity] The instruction name instruction defined in

the REGISTER_ACCESS statement is not defined as an instruction name in the
EXPLANATION:
Semantic Check B.8.13.3 (d) requires that every instruction name defined in the
REGISTER_ACCESS statement must also be defined as an instruction name in the
INSTRUCTION_OPCODE statement. Refer to IEEE Standard 1149.1b-1994: B.8.13.3
(d).
USER RESPONSE:
Ensure that the instruction names defined in both the REGISTER_ACCESS and the
INSTRUCTION_OPCODE statement are correct and complete.
severity (TJB-310): [severity] The instruction name instruction defined in

the INSTRUCTION_PRIVATE statement is not defined as an instruction name in the
EXPLANATION:
Semantic Check B.8.11.3 (i) requires that every instruction name defined in the
INSTRUCTION_PRIVATE statement must also be defined as an instruction name in the
(i).
USER RESPONSE:
Ensure that the instruction names defined in both the INSTRUCTION_PRIVATE and the
INSTRUCTION_OPCODE statement are correct and complete.
severity (TJB-311): [severity] An IDCODE instruction is defined in the

INSTRUCTION_OPCODE statement but no IDCODE_REGISTER is defined.
EXPLANATION:

If the design implements a DEVICE_ID register (IDCODE register), then the

INSTRUCTION_OPCODE statement should define the IDCODE instruction. Refer to
IEEE Standard 1149.1b-1994: B.8.12.3 (b.2).
USER RESPONSE:
If the design has an 1149.1 DEVICE_ID register (IDCODE register), then add an
IDCODE_REGISTER statement to the BSDL. If the design does not have an 1149.1
DEVICE_ID register (IDCODE register), then remove the IDCODE instruction from the
INSTRUCTION_OPCODE statement. See "BSDL File" in the Encounter Test: Guide
2:Testmodes.
severity (TJB-312): [severity] An IDCODE_REGISTER is defined without an

IDCODE instruction.
EXPLANATION:
Semantic Check B.8.12.3 (b) requires that if a IDCODE_REGISTER statement is
defined, then IDCODE must be one of the instructions defined in the
(b).
USER RESPONSE:
If the design has an 1149.1 DEVICE_ID register (IDCODE register), then add an
IDCODE instruction to the INSTRUCTION_OPCODE statement. If the design does not
have an 1149.1 DEVICE_ID register (IDCODE register), then remove the
IDCODE_REGISTER statement from the BSDL.
severity (TJB-313): [severity] BOUNDARY_REGISTER cell #cell number is

defined as an OUTPUT2 with a control cell of bad control cell number. A two-state
driver which has an inactive state must control itself.
EXPLANATION:
The BOUNDARY_REGISTER statement has an OUTPUT2 cell defined which is
controlled by cell other than the OUTPUT2 cell. Semantic Check B.8.14.2 (k) requires
that any OUTPUT2 cell which has a control cell specified must control itself and therefore
have a control cell value which is the same as the cell value OUTPUT2. Refer to IEEE
Standard 1149.1b-1994: B.8.14.2 (k).
USER RESPONSE:
If the two-state driver has an inactive state and is self controlling, then change the control
cell value to the same cell value as the OUTPUT2. If the two-state driver has no inactive
state (other than via the HIGHZ instruction), then remove the disable able specification

from the OUTPUT2 cell definition; This includes the control cell, disable value and
disable result.

defined with a disable value of disable value which is not the same as the safe value of
its control cell. Control cell cell number has a safe value of safe value.
EXPLANATION:
The BOUNDARY_REGISTER statement has an OUTPUT3 or BIDIR cell whose driver is
controlled by another cell, however, the disable value defined for the OUTPUT3/BIDIR
cell is not the same as the safe value defined for the control cell. Semantic Check
B.8.14.2 (n) and B.8.14.1.4 requires that the safe value of a control cell must be the same
as the disable value defined for each of the cells (drivers) it controls. Refer to IEEE
Standard 1149.1b-1994: B.8.14.2 (n).
USER RESPONSE:
Ensure that a safe value of a control cell is the same as the disable value for each of the
drivers it controls. A disable value is defined for each output cell whose driver is
controlled by the control cell.

defined with a safe value of "X". The safe value for a control cell must be either 0 or 1.
EXPLANATION:
The BOUNDARY_REGISTER statement has a control cell defined with a safe value of
X. The safe value for a control cell must be either zero or one. Refer to IEEE Standard
1149.1b-1994: B.8.14.1.4.
USER RESPONSE:
Change the safe value of the identified control cell to either zero or one as appropriate.
severity (TJB-316): [severity] BSDL port: port name has an invalid bit_vector
definition. The bit_vector range must have a value of integer_1 (number) less than or equal
to integer_2 (number).
EXPLANATION:
A bit_vector used in a logical port description statement must have the value of integer_1
less than or equal to integer_2. Refer to IEEE Standard 1149.1b-1994: B.8.3.3(a).
USER RESPONSE:
Change the value of integer_1 so that it is less than or equal to integer_2.

severity (TJB-317): [severity] The constant pin mapping name (name) is not
unique.
EXPLANATION:
Semantic Check B.8.7.3(e) requires that each pin mapping name should be unique
within the list of pin mappings. Refer to IEEE Standard 1149.1b-1994: B.8.7.3(e).
USER RESPONSE:
Rename the non-unique pin mapping name to the one that is not already in the list of pin
mappings.
severity (TJB-318): [severity] The instruction opcode (opcode) is shared by the

instruction instruction and the instruction instruction, yet the lengths of the TDRs
accessed by these instructions differ. The instruction instruction accesses TDR TDR
name whose length is TDR length. The instruction instruction accesses TDR TDR
name whose length is TDR length.
EXPLANATION:
Semantic Check B.8.11.3(i) allows the same opcode provided the TDR lengths are
equivalent. Refer to IEEE Standard 1149.1-2001: B.8.11.3(i).
USER RESPONSE:
Ensure the TDRs accessed by this opcode have equivalent lengths.
severity (TJB-319): [severity] Two ports (port name) and (port name)
referenced in the statement statement do not have the same pin type.
EXPLANATION:
Semantic Check B.8.8.3(e) requires that the representative port and the associated or
correlated port referenced in a DIFFERENTIAL_VOLTAGE or
DIFFERENTIAL_CURRENT statement have the same pin type. The pin type for a port
is defined in the logical port statement. Refer to IEEE Standard 1149.1b-1994:
B.8.8.3(e).
USER RESPONSE:
Need to have same pin type for representative and associated ports within the same twin
group.
severity (TJB-320): [severity] The package file cell name: package file
cell name is defined in package files: package file name and package file
name.

EXPLANATION:
Semantic Check B.8.5.3 requires that VHDL package file identifiers must be unique.
Refer to IEEE Standard 1149.1b-1994: B.10.1.3(b).
USER RESPONSE:
Change the package file cell name so that it is a unique name when compared against
all package file cell names used by the BSDL.
severity (TJB-321): [severity] The TAP port: port name is defined as differential
since it appears in a statement statement either as representative port or an associated
port.
EXPLANATION:
Semantic Check B.8.9.3(e) requires that no TAP port can appear as a representative port
or an associated port in a twin group. Refer to IEEE Standard 1149.1b-1994: B.8.9.3(e).
USER RESPONSE:
TAP port name should be changed so that it is not one of the names in a twin group.
severity (TJB-322): [severity] BOUNDARY_REGISTER cell (cell number) is

a merged cell which is defined with different cell types (cell type (name) and cell
type (name)).
EXPLANATION:
Semantic Check B.8.14.2(d.2) requires that all the merged cells should have same name
for cell type. Refer to IEEE Standard 1149.1b-1994: B.8.14.2(d.2).
USER RESPONSE:
The cell type name for the two merged cells should be checked again and shall have the
same name.
severity (TJB-323): [severity] BOUNDARY_REGISTER cell (cell number) is

a merged cell but does not the same safe value for all of its cell functions.
EXPLANATION:
Semantic Check B.8.14.2(d.3) requires that all merged cells should have same safe
value unless one of the safe values is X. Refer to IEEE Standard 1149.1b-1994:
B.8.14.2(d.3).
USER RESPONSE:

Safe value for the two merged cells should be checked again and need be changed so
that it is same for both the cells.
severity (TJB-324): [severity] BOUNDARY_REGISTER cell number (cell

number) references cell type name (cell type name) which is not defined in any of the
VHDL packages referenced by this BSDL.
EXPLANATION:
Semantic Check B.8.14.2(e) requires that each boundary cell should be described in
either the standard VHDL package or a user-supplied VHDL package. Refer to IEEE
Standard 1149.1b-1994: B.8.14.2(e).
USER RESPONSE:
Boundary cell name need to be defined in the package file.
severity (TJB-325): [severity] The package file: package file name contains
more than one definition of cell name: cell type name.
EXPLANATION:
Semantic Check B.10.1.3(b) requires that each cell name in a package file must be
unique. Refer to IEEE Standard 1149.1b-1994: B.10.1.3(b). Additionally, B.8.5.3 requires
that VHDL package file identifiers must be unique.
USER RESPONSE:
Change the package file cell name so that it is a unique name.
severity (TJB-326): [severity] INSTRUCTION_OPCODE (bit string

(opcode)) of instruction (instruction name) and INSTRUCTION_OPCODE (bit
string (opcode)) of instruction (instruction name) are defined ambiguously.
EXPLANATION:
Semantic Check B.8.11.3.f requires that opcodes should not be ambiguous i.e.,
duplicates or with Xs that are decodable as two or more duplicate instructions.
Refer to IEEE Standard 1149.1b-1994: B.8.11.3.f.
USER RESPONSE:
Change either of those opcode so that it eliminates any ambiguity.
severity (TJB-327): [severity] Test_Image_Unwired defines port (port name)

as an image unwired port but the port is defined in the (logica | physical) port
statement.

EXPLANATION:
The Test_IMAGE_Unwired BSDL extension - Image Unwired requires that an image
unwired port cannot appear in a PHYSICAL_PIN_MAP or in the Logical port statement
as type in, out or inout but could certainly appear in the logical port statement as type
linkage.
USER RESPONSE:
Change needs to be made so that Test_Image_Unwired port does not appear as a port
under PHYSICAl_PIN_MAP statement or under Logical port statement as a non-linkage
type. See "BSDL Extension for Identifying Image Unwired Ports" in the Encounter Test:
Guide 2:Testmodes for related information.
severity (TJB-328): [severity] BOUNDARY_REGISTER cell cell number is

defined as a cell function with a control cell of cell number (or a cell
function which controls itself) but its disable result is not equivalent to the weak logic value
of its disable value.
EXPLANATION:
Semantic Checks B.8.14.4(k & l) requires OUTPUT2 and BIDIR cells that control
themselves to have WEAK0/1 or PULL0/1 values when the disable value is 0 or 1. Refer
to IEEE Standard 1149.1-2001: B.8.14.4(k & l).
USER RESPONSE:
Ensure OUTPUT2 and BIDIR cells have WEAK0/1 or PULL0/1 values when the disable
value is 0 or 1.
severity (TJB-330): [severity] BOUNDARY_REGISTER cell cell_number is

defined with a non-compliant disable value of disable_value.
EXPLANATION:
Semantic Check B.8.14.3.7 specifies the allowable disable values for a boundary cell.
Refer to IEEE Standard 1149.1-2001: B.8.14.3.7.
USER RESPONSE:
Change the disable value for the referenced boundary cell to a compliant value.

register register_name has a duplicate instruction name instruction_name in test
data register register_name.
EXPLANATION:

Semantic Check B.8.13.3 (e) requires that any instruction name shall appear in only one
instruction capture list within the register string. Refer to IEEE Standard 1149.1-2001:
B.8.13.3 (e).
USER RESPONSE:
Remove the duplicate instruction name from the Register Access attribute and rerun.
WARNING (TJB-338): [Severe] Cell number cellnum with the port name portname
and function type function, has the same port name and function type as cell number
cellnum in the BOUDARY_REGISTER statement.
EXPLANATION:
In the BSDL's BOUNDARY_REGISTER statement, no two cell numbers with this
function type can have the same port name.
USER RESPONSE:
Correct the duplicate port name in the BSDL and re-run verify_11491_boundary.
WARNING (TJB-340): [Severe] The EXTEST_PULSE and EXTEST_TRAIN instructions

are used with the IEEE Std 1149.6-2003 standard. Specify the
AIO_COMPONENT_CONFORMANCE entity of STD_1149_6_2003 to use these instruction
names.
EXPLANATION:
The IEEE standard for advanced digital networks defines two new instructions,
EXTEST_PULSE and EXTEST_TRAIN. These instructions are to be used with the
AIO_COMPONENT_CONFORMANCE entity of STD_1149_6_2003.
USER RESPONSE:
Add the AIO_COMPONENT_CONFORMANCE entity of STD_1149_6_2003 to the BSDL file
and then rerun.
WARNING (TJB-341): [Severe] If the AIO_Pin_Behavior attribute is specified, the

EXTEST_PULSE and EXTEST_TRAIN structions must also be specified in the
INSTRUCTION_OPCODE attribute.
EXPLANATION:
The IEEE Std 1149.6-2003 standard requires the EXTEST_PULSE and EXTEST_TRAIN
instructions be defined when using the AIO_Pin_Behavior attribute.
USER RESPONSE:
Add the EXTEST_PULSE and EXTEST_TRAIN instructions to the BSDL and then rerun.

WARNING (TJB-342): [Severe] Standard use statement

- use STD_1149_6_2003:all; - must be in the BSDL when using EXTEST_PULSE and
EXTEST_TRAIN instructions.
EXPLANATION:
instructions be defined when - use STD_1149_6_2003:all; - is present in the
BSDL.
USER RESPONSE:
WARNING (TJB-343): [Severe] Standard use statement

- use STD_1149_6_2003:all; - must be in the BSDL when using EXTEST_PULSE and
EXPLANATION:
instructions be defined when - use STD_1149_6_2003:all; - is present in the
BSDL.
USER RESPONSE:
WARNING (TJB-344): [Severe] The AIO port name port_name must be defined in the
BOUNDARY_REGISTER statemen.
EXPLANATION:
The BOUNDARY_REGISTER statement must contain all AIO port names,
USER RESPONSE:
Add the port name to the BOUNDARY_REGISTER statement and then rerun.
WARNING (TJB-345): [Severe] When using AIO attributes, an

AIO_COMPONENT_CONFORMANCE entity of STD_1149_6_2003 must be included in the
BSDL.
EXPLANATION:
An AIO_COMPONENT_CONFORMANCE entity of STD_1149_6_2003 must be in the BSDL
when using AIO attributes AIO_EXTEST_Pulse_Execution,
AIO_EXTEST_Train_Execution, AIO_Pin_Behavior, or EXTEST_PULSE and

USER RESPONSE:
and then rerun.
WARNING (TJB-346): [Severe] Invalid AIO_COMPONENT_CONFORMANCE entity. The only

allowable AIO_COMPONENT_CONFORMANCE entity is STD_1149_6_2003.
EXPLANATION:
The only entity defined for AIO_COMPONENT_CONFORMANCE is STD_1149_6_2003.
USER RESPONSE:
and then rerun.
WARNING (TJB-347): The EXTEST_PULSE and EXTEST_TRAIN instructions are used

with the IEEE Std 1149.6-2003 standard. This standard requires that these instructions be
included in the REGISTER_ACCESS statement and be associated with the BOUNDARY
register.
EXPLANATION:
The IEEE standard for advanced digital networks defines two new instructions,
EXTEST_PULSE and EXTEST_TRAIN. These instructions are to be included in the
REGISTER_ACCESS statement and be associated with the BOUNDARY register.
USER RESPONSE:
Add the line BOUNDARY (EXTEST_PULSE, EXTEST_TRAIN);" to the
REGISTER_ACCESS statement and then rerun.
severity (TJB-350): severity Port port_name referenced in the

DIFFERENTIAL_VOLTAGE | DIFFERENTIAL_CURRENT statement does not have the
pin_attribute pin attribute in the model.
EXPLANATION:
The representative port or associated port referenced in the DIFFERENTIAL_VOLTAGE
or DIFFERENTIAL_CURRENT statement does not have the representative or correlated
model pin attribute.
USER RESPONSE:
Add the representative and correlated ports to the assign or modedef file using the
CORRELATE statement and rebuild the test mode.

severity (TJB-351):severity Representative port port_name and associated port

port name referenced in the DIFFERENTIAL_VOLTAGE | DIFFERENTIAL_CURRENT
statement are not correlated to each other in the model.
EXPLANATION:
The representative port and the associated port referenced in the
DIFFERENTIAL_VOLTAGE or DIFFERENTIAL_CURRENT statement are not referenced
in the model as being correlated to each other. The associated port must be correlated
to the representative port in the model.
USER RESPONSE:
Add the representative and associated ports to the assign or modedef file using the
CORRELATE statement and rebuild the test mode.
INFO (TJB-400): Partial BSDL encountered.

EXPLANATION:
Incomplete BSDL was detected. Not all the BSDL statements exist within the BSDL file
specified.
USER RESPONSE:
This may or may not be desirable. Ensure that the BSDL has enough of the information
required for your purposes. See "BSDL File" in the Encounter Test: Guide
2:Testmodes.
INFO (TJB-402): The BSDL does not have a PORT statement -- No defaults were made..
EXPLANATION:
The BSDL does not have a port statement specified.
USER RESPONSE:
Ensure that there were no ports required to be specified for the BSDL.
INFO (TJB-403): The BSDL does not have any USE include statements -- No defaults were
made..
EXPLANATION:
The BSDL does not have any USE include statements.
USER RESPONSE:
Ensure that there were no includes required for the BSDL specified.

WARNING (TJB-500): [Severe] Unable to open BSDL output file with a name of: file
name The BSDL file cannot be written.
EXPLANATION:
The output BSDL file cannot be written to.
USER RESPONSE:
Check permissions and path names.
WARNING (TJB-501): [Severe] The BSDL chip name exceeds print limitations of column
number.
EXPLANATION:
The BSDL chip name is too long.
USER RESPONSE:
Start the statement as far left as possible and retry. Contact customer support (see
Contacting Customer Service on page 23) for assistance if you are unable to resolve
this problem.
WARNING (TJB-502): [Severe] In printing the BSDL statement type statement, data:
data value in the field type field exceeds the print capacity.
EXPLANATION:
The field size is too big to print.
USER RESPONSE:
Reduce the field size if possible and rerun.
WARNING (TJB-600): [Severe] Memory Allocation problem. Not enough memory

available to continue. Malloc on internal variable variable name for size of size FAILED.
EXPLANATION:
The application has asked for more memory and the machine you are running on does
not have it available.
USER RESPONSE:
If possible, try running on a larger machine (one with more memory). If you are convinced
that the application is demanding too much memory, contact customer support (see

WARNING (TJB-601): [Severe] Memory Allocation problem. Not enough memory

available to continue. Realloc on internal variable: variable name for size of size FAILED.
EXPLANATION:
The application has asked for more memory and the machine you are running on does
not have it available.
USER RESPONSE:
If possible, try running on a larger machine (one with more memory). If you are convinced
that the application is demanding too much memory, contact customer support (see
ERROR (TJB-650): [Internal] Unexpected program error. Unknown application type. It is

not recognized by Mode Define.
EXPLANATION:
An internal programming error has occurred.
USER RESPONSE:
assistance.
INFO (TJB-700): Start BSDL Parse on file: filename.

EXPLANATION:
BSDL Parse has started.
USER RESPONSE:
INFO (TJB-701): Completed BSDL Parse on file: BSDL_filename.

EXPLANATION:
BSDL Parse has completed.
USER RESPONSE:
INFO (TJB-703): Internal structures were loaded success type

EXPLANATION:

Structures containing data from the BSDL has been loaded either successfully or
unsuccessfully.
USER RESPONSE:
If an unsuccessful load occurred, contact customer support (see Contacting Customer
Service on page 23) for assistance.
ERROR (TJB-704): BSDL parse can not continue due to reason.

EXPLANATION:
USER RESPONSE:
and contact customer support (see Contacting Customer Service on page 23) if
necessary.
WARNING (TJB-800): [Severe] Error in Package File: package file name at or near
line #line number, error type.
EXPLANATION:
An error was detected in the package file at or near the line indicated.
USER RESPONSE:
Fix the error and rerun.
WARNING (TJB-802): As a result of a syntax error, lines line number to line number
in this BSDL file are ignored.
EXPLANATION:
A syntax error has caused certain BSDL lines to be ignored. Data for these ignored
statements will NOT be considered during processing.
USER RESPONSE:
Fix the syntax error and rerun.
WARNING (TJB-803): Unable to find or open Package File: package file name.
EXPLANATION:
The Package File could not be found or opened.

USER RESPONSE:
Check the package file name and package path specified by the environment variable or
command line parameter BSDLPKGPATH.
WARNING (TJB-804): [Severe] Parse problem occurred with BSDL file:

BSDL_filename The limitation of number characters in a quoted string has been
exceeded. (Check for a missing quote mark.)
EXPLANATION:
A character string within the BSDL file exceeded the predefined limited length allowed.
USER RESPONSE:
Ensure the quotation marks are accurate for the character strings specified in the BSDL
file. A missing quote may cause this problem.
WARNING (TJB-805): [Severe] Parse problem occurred with Package file: package
file name. The limitation of number lines in a Package file has been exceeded. (Shorten
or break it up into two files.)
EXPLANATION:
There is a limited number of lines a package file may contain. The package file exceeds
the limitation.
USER RESPONSE:
Shorten or break the package file up to reduce file sizes and rerun.
WARNING (TJB-806): [Severe] Syntax error detected at or near line #line number
exists. optional extra information
EXPLANATION:
A syntax error in the BSDL was detected.
USER RESPONSE:
Resolve the syntax error and rerun.
INFO (TJB-807): Severe processing errors has terminated processing of BSDL file:
BSDL_filename.
EXPLANATION:
Severe processing errors have caused this parse to fail.
USER RESPONSE:

Resolve the processing errors and rerun.
INFO (TJB-808): Begin parse of package file: package file name.

EXPLANATION:
The BSDL parser has started to parse a package file.
USER RESPONSE:
INFO (TJB-809): End parse of package file: package file name.

EXPLANATION:
The BSDL parser has completed parsing a package file.
USER RESPONSE:
ERROR (TJB-850): String string value is longer than the standard size of 128000.
EXPLANATION:
The BSDL File has a string longer than the maximum length of 128000 allowed by the
tool.
USER RESPONSE:
Break up the string by using continuation characters at the end.
WARNING (TJB-900): [Severe] Error: An Illegal character of character octal

value at or near line line number exists.
EXPLANATION:
The BSDL file contains an illegal or unrecognizable character that the BSDL parser
cannot handle.
USER RESPONSE:
Correct the Illegal character in the BSDL file and rerun.


44
TJC - IEEE 1149.1 Boundary Scan
Verification Messages
TJC-102 through TJC-200 on page 1415

TFK-100 through TFK-101 on page 1458
TJC-102 through TJC-200

ERROR (TJC-102): Boundary Scan Verification (BSV) received an error when processing
the BSDL file and is terminating. See previous TJB messages for more information.
EXPLANATION:
The Boundary Scan Verification tool received severe errors when processing the BSDL
file and is unable to continue. This could be due to not finding the BSDL file or severe
errors in the file itself. The exact cause for this error should be available in the previous
TJB messages.
USER RESPONSE:
Take corrective action based on the previous TJB messages and rerun the Boundary
Scan Verification tool.
INFO (TJC-110): Verification processing may have completed prematurely based on

reaching the maximum number of miscomparing checks (maxnummisc=number).
EXPLANATION:
The Boundary Scan Verification tool uses a Stop On Nth Miscompare mechanism to limit
both CPU time and the size of generated files. Boundary Scan Verification has

TJC - IEEE 1149.1 Boundary Scan Verification Messages
encountered N checks which have generated miscompares (checks which did not
yielded the expected results). Boundary Scan Verification stops the verification after
detecting N miscomparing (failing) checks based on the value of specified for the
maxnummisc option.
USER RESPONSE:
To continue processing beyond the Nth miscompare, raise the value maxnummisc to the
desired level. Specifying a value of zero for maxnummisc allows Boundary Scan
Verification to all apply checks before terminating.
WARNING (TJC-111): Mapping verification will not be performed for pin: pin name since
the pin is not normally a target pin for mapping verification.
EXPLANATION:
The identified pin defined in the facility mapping target can not be selected for mapping
verification since it is not a pin which would normally go through mapping verification. A
pin is a candidate for mapping verification if it is defined in the boundary register with
input or output capability.
USER RESPONSE:
Remove the pin from the mappingtarget facility.
INFO (TJC-112): Boundary Scan Verification has determined that the BSDL for the design
has no TRST specified and no BSDL extension for "TAP_LATCH" specified. All non-fixed
value latches are set to an arbitrary known state.
EXPLANATION:
Boundary Scan Verification requires the ability to initialize the state of the latches of the
TAP Finite State Machine. For circuits without a TRST pin, this can be accomplished via
the Encounter Test BSDL extension "TAP_LATCH". The Encounter Test BSDL
TAP_LATCH statement is used to identify those latches which comprise the TAP Finite
State Machine. The BSDL file specified for this invocation of BSV does not contain a
TRST port statement nor a TAP_LATCH statement, therefore BSV will set all non-fixed
value latches to an arbitrary known state to initialize the TAP to some known state and
allow an 1149.1 synchronous reset to be performed.
USER RESPONSE:
There is a possibility that the results of the verification are invalid since the results are
based on assuming known states for latches other than the TAP latches.
ERROR (TJC-113): Unrecognized facility name

EXPLANATION:

The provided facility name is incorrect. In order to proceed with the debug option on user-
provided IO pins, a valid facility name is required.
USER RESPONSE:
Specify a valid facility name.
ERROR (TJC-114): Execution terminates as the file name provided was incorrect.
EXPLANATION:
An invalid file name was specified.
USER RESPONSE:
Specify a valid file name.
INFO (TJC-116): IEEE 1149.1 BSV generated files - file size (bytes) file name:
EXPLANATION:
This message reports file names and their sizes (in bytes) of files generated by BSV. This
will normally include the name and file size of the BSV results file. The BSV results file
contains the details of the verification patterns and verification results. The message also
reports the name and file sizes of Vectors files created by BSV.
USER RESPONSE:
ERROR (TJC-117): Verification can not be performed due to terminating error conditions.
EXPLANATION:
Boundary Scan Verification is not able to run based on terminating ERROR or
WARNING [Severe] level errors.
USER RESPONSE:
Review response for preceding ERROR and or severe WARNING [Severe] level
messages.
WARNING (TJC-118): The BSDL file defines test function pins not found in the test mode.
EXPLANATION:
The input BSDL file to Boundary Scan Verification contains one or more test function pins
(eg. COMPLIANCE_ENABLE pins) which are not defined in the test mode. Boundary

Scan Verification continues processing using the test function pins defined in the BSDL
file.
USER RESPONSE:
BSV is reporting an inconsistency in the Test Function Pins defined in the BSDL versus
those defined in the test mode on which it is running. BSV will perform the verification
using the Test Function Pins defined in the BSDL. This is a valid verification of 1149.1.
This message is intended to alert you that differences do exist in Test Function Pin
definitions. Refer to "Test Function Pins for an 1149.1 Mode" in the Encounter Test:
Guide 2:Testmodes for related information.
WARNING (TJC-119): Verification of all public | private instructions was requested yet no
public|private instructions are defined in the BSDL.
EXPLANATION:
Verification of public instructions requires that one or more public instructions be defined
in the BSDL. Public instructions are defined to be any instruction which is a non-standard
instruction and a non-private instruction. Verification of private instructions requires that
one or more private instructions be defined in the BSDL.
Private instructions are defined to those defined via the INSTRUCTION_PRIVATE
statement in the BSDL. Verification of a public or private instruction requires that an
instruction opcode be defined for the instruction via the INSTRUCTION_OPCODE
statement in the BSDL. It also requires that each public or private instruction to be
verified must appear in the REGISTER_ACCESS statement. In the case of a private
instruction, a temporary modification needs to be made to the BSDL such that the private
instruction appears in the REGISTER_ACCESS statement. Refer to IEEE Standard
1149.1b-1994.
USER RESPONSE:
Ensure that the BSDL contains the necessary instruction definitions in the
INSTRUCTION_OPCODE and REGISTER_ACCESS statements. Verification of private
instructions also requires that the instruction be defined as private via the
INSTRUCTION_PRIVATE statement and that the instruction appear in the
REGISTER_ACCESS statement (as a temporary change for verification purposes only).
WARNING (TJC-120): Verification of the instruction name instruction was requested yet the
instruction name instruction is not defined in the BSDL.
EXPLANATION:
Verification of the identified instruction requires that the identified instruction name and
instruction opcode be defined via INSTRUCTION_OPCODE statement in the BSDL.
BSV uses the instruction name for verification of a particular instruction.

USER RESPONSE:
Ensure that the BSDL contains the necessary instruction definition in the
INSTRUCTION_OPCODE statement. If the instruction is a user-defined instruction, the
instruction must also be included in the REGISTER_ACCESS statement.
If you have BSV to verify all instructions (verify=all), and the identified instruction is
intentionally not defined in the BSDL (e.g. its not supported), then no action is required.
WARNING (TJC-121): [Severe] Verification of the instruction name instruction was

requested yet the instruction name instruction is not associated with any test data register as
defined in the BSDL. Verification will not be performed for the instruction name instruction.
EXPLANATION:
Verification of the identified instruction requires that the identified instruction name be
associated with a test data register in the BSDL via the REGISTER_ACCESS statement.
USER RESPONSE:
Ensure that the identified instruction is associated with a test data register via the
REGISTER_ACCESS statement in the BSDL.
WARNING (TJC-122): [Severe] Verification of the instruction_name instruction was

requested yet the instruction_name instruction requires a BSDL boundary register
definition whose length is greater than zero.
EXPLANATION:
Verification of the instruction_name instruction requires that a
BOUNDARY_REGISTER definition is defined in the BSDL with a length greater than
zero.
Verification of instruction_name is not performed.
USER RESPONSE:
Ensure that the boundary register is defined with a length greater than zero in the BSDL
via the BOUNDARY_LENGTH statement.
ERROR (TJC-123): Verification of one or more instructions was requested yet the
instruction register length is not defined in the BSDL.
EXPLANATION:
Verification of any instruction requires that length of the instruction register be defined
via INSTRUCTION_LENGTH statement in the BSDL.
USER RESPONSE:

Ensure that the BSDL contains the INSTRUCTION_LENGTH statement and that its
value is at least two.
ERROR (TJC-124): An experimental TBD was requested and no experiment was specified.
EXPLANATION:
A request was made to have 1149.1 BSV write its verification sequences to an
uncommitted Vectors via the writepatterns=yes option. However, no uncommitted
name was provided via the EXPERIMENT environment variable and or command line
option.
USER RESPONSE:
If an uncommitted TBD is desired, then EXPERIMENT and writepatterns=yes must
be specified. If no experiment is desired then writepatterns=no should be specified.
WARNING (TJC-125): [Severe] verification_type verification was requested but

can not be performed given the specified testmode.
EXPLANATION:
The requested verification can not be performed based on the type of test mode
specified. Verification of all supported instructions is possible by using a test mode which
does not specify any INSTRUCTION and or TAP_TG_STATE. BSV will automatically
create a test mode appropriate for boundary register IO mapping verification. If the
specified testmode is defined with a specific INSTRUCTION and or TAP_TG_STATE
then verification using such a test mode is limited to that instruction and TAP state. For
example, if the test mode is defined as having an instruction of EXTEST and a
TAP_TG_STATE of CAPTURE_DR and UPDATE_DR, then IOMAPPING is the only
verification possible.
USER RESPONSE:
Define and select a mode appropriate for the verification to be performed.
WARNING (TJC-126): Verification of the EXTEST instruction is incomplete without also

completing type verification.
EXPLANATION:
The requested verification can not be performed based on the type of test mode
specified. Verification of all supported instructions is possible by using a test mode which
does not specify any INSTRUCTION and or TAP_TG_STATE. BSV will automatically
create a test mode appropriate for I/O mapping verification. If the specified testmode is
defined with a specific INSTRUCTION and or TAP_TG_STATE then verification using
such a test mode is limited to that instruction and TAP state. For example, if the test mode

is defined as having an instruction of EXTEST and a TAP_TG_STATE of CAPTURE_DR

and UPDATE_DR, then IOMAPPING is the only verification possible.
USER RESPONSE:
Define and select a mode appropriate for the verification to be performed.
INFO (TJC-127): Begin definition of test mode name test mode.

EXPLANATION:
BSV is building the identified test mode for verification and or analysis purposes, or
because a user request was made to create the test mode.
USER RESPONSE:
INFO (TJC-128): Definition of the test mode name test mode completed.
EXPLANATION:
BSV has completed building the identified test mode. option.
USER RESPONSE:
WARNING (TJC-129): [Severe] check name verification was requested but can not be
performed since the test mode test mode name could not be created for performing these
checks.
EXPLANATION:
The requested verification can not be performed because the identified test mode was
not successfully created. Under normal circumstances, this error should not occur.
However, fails could occur due file locks, write permissions, or file system space
constraints etc.
USER RESPONSE:
Review the Encounter Test log and standard error output to determine why the test mode
build process failed.
INFO (TJC-130): BSVs test mode definition process for the test mode name test mode was
unsuccessful and as such no scan latches have been identified for the register name
register. As a result, BSV will not produce latch expect values for scans on the register
name register.

EXPLANATION:
BSV will produce expect values on scan latches for an 1149.1 scan chain when that
register is being verified. However, the ability to produce scan latch expects is dependent
on a successful test mode definition process in which the register is defined with
appropriate stim and measure register characteristics.
USER RESPONSE:
Determine if the identified test mode was created. If so, review the register definition for
the identified test mode. A completed stim and measure register is required consisting of
the same stim/measure latches for each bit position. The register length must be equal
to that which is defined in the BSDL being used for verification.
INFO (TJC-131): All checks included in the verification group name group have
been completed via previous checks completed on this invocation of BSV. The need to run
the checks in the verification group name has been satisfied.
EXPLANATION:
BSV has determined that previously completed checks has removed the need to redo
these checks again in the identified verification group. For example, all of the checks
which are performed in the TAP FSM group are also performed in other verification
groups (e.g. bypass, reset). If all of the checks in the TAP FSM group have been
completed by other groups, then there is no need to reverify these same checks in the
TAP FSM group. The determination is based on completion only, not whether the checks
passed or failed.
USER RESPONSE:
No action is required.
WARNING (TJC-132): [Severe] A bit value of X appearing in opcode (bit string

(opcode) of instruction (instruction name) is ambiguous and will not be verified.
EXPLANATION:
Semantic Check B.8.11.3.f requires that opcodes containing X should not be ambiguous
i.e., decodable as two or more different instructions. Refer to IEEE Standard 1149.1b-
1994: B.8.11.3.f. Refer to previous TJB error messages (TJB326) which indicates other
instruction(s) and the opcode(s) with which this opcode is ambiguous.
USER RESPONSE:
Change the opcode to eliminate any ambiguity.

WARNING (TJC-133): Verification of the private instruction name instruction was requested
yet the instruction name instruction is not associated with any test data register as
defined in the BSDL. Verification will not be performed for the instruction name instruction.
EXPLANATION:
Verification of the identified instruction requires that the identified instruction name be
associated with a test data register in the BSDL via the REGISTER_ACCESS statement.
Note that private instructions need not be included in the REGISTER_ACCESS
statement unless verification in desired. Once verification is complete, private
instructions should be removed from the REGISTER_ACCESS statement.
USER RESPONSE:
This message may be ignored if there is no requirement to verify the private instruction.
Otherwise, ensure that the identified instruction is associated with a test data register via
the REGISTER_ACCESS statement in the BSDL.
WARNING (TJC-134): The private instruction group name group was not verified.
EXPLANATION:
The identified verification group was not included in the verification. This is indicates an
incomplete verification was performed.
USER RESPONSE:
If you are intentionally making an incomplete verification run (something other than
verify=all), no response is required. However, if you are making a complete
verification run (verify=all), then review the BSV logfile to determine why the
identified verification group was not verified. Verification of private instructions is
optional.
WARNING (TJC-135): Verification of the private instruction name instruction was

requested yet the register accessed by the instruction name instruction is defined with no
length or a length of zero in the REGISTER_ACCESS statement. Verification will not be
performed for the instruction name instruction.
EXPLANATION:
Verification of the identified instruction requires that the instruction is associated with a
data register in the REGISTER_ACCESS statement and that the length defined for the
register in the REGISTER_ACCESS statement is greater than zero. Lengths of the
standard registers, BYPASS, DEVICE_ID and BOUNDARY are per the standard or are
supplied via other BSDL constructs.
USER RESPONSE:

If you are attempting to verify a private instruction, ensure it is associated with a test data
register via the REGISTER_ACCESS statement and that the register length is greater
than zero. An instruction accessing the BOUNDARY_REGISTER relies on the
BOUNDARY_LENGTH which must also be greater than zero.
If you are not attempting to verify a private instruction, then remove it from the
REGISTER_ACCESS statement.
WARNING (TJC-136): [Severe] Verification of the instruction name instruction was

requested yet the register accessed by the instruction name instruction is defined with no
length or a length of zero in the REGISTER_ACCESS statement. Verification will not be
performed for the instruction name instruction.
EXPLANATION:
Verification of the identified instruction requires that the instruction is associated with a
data register in the REGISTER_ACCESS statement and that the length defined for the
register in the REGISTER_ACCESS statement is greater than zero. Lengths of the
standard registers, BYPASS, DEVICE_ID and BOUNDARY are per the standard or are
supplied via other BSDL constructs.
USER RESPONSE:
Ensure that a user defined instruction is associated with a test data register via the
REGISTER_ACCESS statement and that the register length is greater than zero. An
instruction accessing the BOUNDARY_REGISTER relies on the BOUNDARY_LENGTH
which must also be greater than zero.
INFO (TJC-137): BSVs full verification suite could not be used to verify the user instruction:
instruction name, since the size of the register name register is number which
exceeds the maxsimreglength specification of number.
EXPLANATION:
The size of the register used in the verification of the identified instruction is greater than
the identified maximum allowed. maxsimreglength is an expert user option which
controls whether BSV will use its normal verification suite for verification of an instruction.
If the bit length of register accessed by an instruction exceeds maxsimreglength, then
BSV will only perform structural checking of the register unless scanonlysim has been
enabled, in which case, the verification will also include limited simulation.
USER RESPONSE:
maxsimreglength is normally used to limit the CPU time required for verification of
instructions which access large registers. BSVs full verification suite will be applied to

the identified instruction if maxsimreglength is specified with a value which is greater

than the register length accessed by the identified instruction.
Alternatively, scanonlysim can be specified which will limit the CPU time required for
verification of an instruction by only performing one simulation based check for an
instruction which accesses a register which exceeds maxsimreglength. When an
instructions register length exceeds maxsimreglength, a test mode is automatically
created to allow structural checking of the register.
WARNING (TJC-138): [Severe] BSVs full verification suite could not be used to verify the:
instruction name, instruction since the size of the register name register is number
which exceeds the maxsimreglength specification of: number.
EXPLANATION:
The size of the register used in the verification of the identified instruction is greater than
the identified maximum allowed. maxsimreglength is an expert user option which
controls whether BSV will use its normal verification suite for verification of an instruction.
If the bit length of register accessed by an instruction exceeds maxsimreglength, then
BSV will only perform structural checking of the register unless scanonlysim has been
enabled, in which case, the verification will also include limited simulation.
USER RESPONSE:
maxsimreglength is normally used to limit the CPU time required for verification of
instructions which access large registers. BSVs full verification suite will be applied to
the identified instruction if maxsimreglength is specified with a value which is greater
than the register length accessed by the identified instruction.
Alternatively, scanonlysim can be specified which will limit the CPU time required for
verification of an instruction by only performing one simulation based check for an
instruction which accesses a register which exceeds maxsimreglength. When an
instructions register length exceeds maxsimreglength, a test mode is automatically
created to allow structural checking of the register. Instructions which are defined by the
IEEE Std are expected to be verified via BSV normal verification suite. Ensure that
maxsimreglength is sufficient for instructions defined by the IEEE Std.
WARNING (TJC-139): The test mode name test mode could not be created. The test
mode name test mode was needed for error (message) analysis or was requested per the
regidentification option.
EXPLANATION:
The identified test mode was not successfully created. Under normal circumstances, this
error should not occur. However, fails could occur due file locks, write permissions, or file
system space constraints etc. BSV attempted to create the test mode either because

regidentification=yes or regidentification=fail and BSV detected

compliance failure for the instruction identified in the test mode name. In this case, failure
to create the test mode does not affect the completeness of BSVs checking. It does
however, affect the completeness of BSVs message analysis processing.
USER RESPONSE:
Review the Encounter Test log and standard error output to determine why the test mode
build process failed.
INFO (TJC-140): Verification will be performed using zero delay simulation.

EXPLANATION:
BSV will use zero delay when simulating verification patterns.
USER RESPONSE:
No action is required if zero delay simulation is intended. Otherwise, request unit delay
simulation by either removing delaymode from the command line (unit delay is the
default) or specifying delaymode=unit.
WARNING (TJC-141): The BSDL defines more than one COMPLIANCE_PATTERN for this
entity. Only one such pattern is verified by this invocation of BSV, namely the
COMPLIANCE_PATTERN used to define the test mode in which BSV is running.
EXPLANATION:
Each BSDL COMPLIANCE_PATTERN represents at least one different set of pin:value
pairs which are defined to enable 1149.1 compliance. Each such pattern is to have an
equivalent effect on the logic with regard to enabling compliance. This message indicates
that only once such pattern can be verified by BSV in a particular test mode. If additional,
compliance patterns are to be verified, then one test mode must be defined for each such
pattern. Presently, TestMode define uses the first compliance pattern to defined the test
mode.
USER RESPONSE:
Define one test mode for each compliance pattern. Provide TestMode define with a
BSDL file with an appropriate COMPLIANCE_PATTERNS statement for the test mode.
The target BSDL file should list the target compliance pattern first in the
COMPLIANCE_PATTERNS statement and then supplied to TestMode define.
For additional information, refer to "Test Function Pins for an 1149.1 Mode" in the
Encounter Test: Guide 2:Testmodes and Creating an 1149.1 Test Mode for Boundary
Scan Verification in the Encounter Test: Guide 3: Test Structures.
INFO (TJC-142): name verification started.

EXPLANATION:
Self explanatory. This message is used for normal log file application output.
USER RESPONSE:
INFO (TJC-143): verification_name verification completed

(#expects=expects,#miscompares=miscompares)
EXPLANATION:
The message indicates BSV has completed one check or one group of checks. The
number of expects is the number of verification patterns which had known expect states.
The number of miscompares is number of actual states which differed from known expect
states.
USER RESPONSE:
WARNING (TJC-144): Verification of the private instruction name instruction was

requested yet the instruction name instruction has no opcodes defined in the
INSTRUCTION_OPCODE statement. Verification will not be performed for the instruction
name instruction.
EXPLANATION:
Verification of the identified instruction requires that the instruction have one or more
opcodes defined in the INSTRUCTION_OPCODE statement.
USER RESPONSE:
Add the identified instruction to the BSDL INSTRUCTION_OPCODE statement.
WARNING (TJC-146): Register identification has been suppressed

(regidentification=no) and will adversely affect the completeness of BSVs error (GUI
message) analysis.
EXPLANATION:
Specifying regidentification=no prevents BSV from creating test modes which are
used to produce analysis data when failures are detected during verification processing.
If BSV detects no compliance errors, then there is no adverse impact. However, if
compliance errors are detected, then message analysis will be adversely affected since
the resulting View Schematic display will not be as robust as it would otherwise be (for
example, it would contain less logic or diminish focus on the location of the error).

USER RESPONSE:
BSV should be run with regidentification=fail (default) when it detects
compliance errors.
INFO (TJC-147): Structural checks started for the register name register accessed by
the instruction name instruction.
EXPLANATION:
Starting structural checks to determine if TB_<inst>_<tap_state> mode has register
identification errors.
INFO (TJC-148): No errors found during structural checks for the Register Name register
accessed by the Instruction Name instruction.
EXPLANATION:
Structural checks to determine if TB_<inst>_<tap_state> mode has register identification
errors completed with no errors.
INFO (TJC-149): Structural checks completed for the register name register accessed
by the instruction name instruction.
EXPLANATION:
Starting structural checks to determine if TB_<inst>_<tap_state> mode has register
identification errors.
WARNING (TJC-150): The group name group was not verified.

EXPLANATION:
The identified verification group was not included in the verification. This is indicates an
incomplete verification was performed.
USER RESPONSE:
If you are intentionally making an incomplete verification run (something other than
verify=all), then no response is required. However, if you are making complete
verification run (verify=all), then review the BSV logfile to determine why the
identified verification group was not verified.
INFO (TJC-151): Boundary Scan Verification passed.

EXPLANATION:
This message indicates that there were no violations of any of the IEEE 1149.1 rules
checked by BSV.

USER RESPONSE:
WARNING (TJC-152): Boundary Scan Verification failed.

EXPLANATION:
This message indicates that 1149.1 BSV was either unsuccessful in processing the
design or that there were one or more IEEE 1149.1 rule violations checked by BSV. One
or more WARNING [Severe] or higher level severity messages will result in a failing
1149.1 BSV.
USER RESPONSE:
Refer to previous WARNING [Severe] or higher severity level messages in the BSV log.
WARNING (TJC-160): One or more HIGHZ values have been detected on output pins
where a Weak0 or Weak1 value was expected. A miscompare will not be issued.
EXPLANATION:
A Weak0 or Weak1 value is obtained by placing the output driver in the HIGHZ state and
having the tester provide a zero or one termination value. Depending on the output
circuitry involved, verify_11491_boundary does not always include tester
termination in the calculation of the output value. Therefore in these situations a HIGHZ
value will be equivalent to a Weak0 or Weak1 value.
USER RESPONSE:
INFO (TJC-200): text

EXPLANATION:
USER RESPONSE:

INFO (TJC-201): BSV Simulation Results Summary
EXPLANATION:

USER RESPONSE:
INFO (TJC-202): number_Expects number_Miscompares group name

EXPLANATION:
USER RESPONSE:

EXPLANATION:
USER RESPONSE:
INFO (TJC-204): number_Expects number_Miscompares group name

EXPLANATION:
USER RESPONSE:

EXPLANATION:
USER RESPONSE:
WARNING (TJC-206): [Severe] Unexpected result detected in capture and scan of the
instruction register. Miscompare detected in:
odometer|blank APN APN number and test mode test mode name
EXPLANATION:

BSV has detected a miscompare in the scan out of the instruction register. The identified
APN performs a serial unload of the instruction register immediately after performing a
CaptureIR. The unload resulted in a miscompare in one or more bits of the expected
CaptureIR state at TDO. BSV uses the definition of the BSDL
INSTRUCTION_CAPTURE state to determined the expected CaptureIR state.
USER RESPONSE:
Use the BSV results file to review the details of the check including the verification
patterns, the expected and actual results. Refer to "IEEE 1149.1 Boundary Scan
Verification Results File" in the Encounter Test: Guide 3: Test Structures for related
information.
WARNING (TJC-207): [Severe] Unexpected result detected in consecutive scans of the

instruction register. Miscompare detected in:
EXPLANATION:
BSV has detected a miscompare in the scan out of the instruction register. The identified
APN performs two back to back serial loads/unloads of the instruction register. The
unload resulted in a TDO miscompare in one or more bits of the expected unload state.
The first load is used to load a known state into the instruction register. The second load/
unload of the instruction register contains TDO expects which were determined by the
first (preceding) load of the instruction register.
USER RESPONSE:
information.
register name register the instruction name instruction. Miscompare detected in:
following UpdateIR of intstruction opcode|for odometer|blank
APN APN number and test mode test mode name
EXPLANATION:
BSV has detected a miscompare in the scan out of the identified register when the
identified instruction was active. This message normally indicates that a miscompare has
occurred on the expected register capture state. BSV uses the BSDL BSDL to determine
the expected capture states.
USER RESPONSE:

information.
WARNING (TJC-210): [Severe] Unexpected result detected in synchronous (clocked)

reset of the TAP controller. A capture and scan of the BYPASS | DEVICE_ID register failed to
produce the expected result. Miscompare detected in:
EXPLANATION:
BSV has detected a miscompare in the scan out of the BYPASS or DEVICE_ID register
following a synchronous (clocked) reset of the TAP controller. This message normally
indicates that a miscompare has occurred on the expected register capture state. If the
BSDL defines an IDCODE instruction then IDCODE_REGISTER defines the expected
DEVICE_ID register capture state. If the BSDL does not define an IDCODE instruction,
then the a bit value of one is defined as the expected BYPASS register capture state.
USER RESPONSE:
information.
WARNING (TJC-211): [Severe] Unexpected result detected in asynchronous reset of the

TAP controller. A capture and scan of the BYPASS|DEVICE_ID register failed to produce
the expected result. Miscompare detected in:
EXPLANATION:
BSV has detected a miscompare in the scan out of the BYPASS or DEVICE_ID register
following an asynchronous reset of the TAP controller. This message normally indicates
that a miscompare has occurred on the expected register capture state. If the BSDL
defines an IDCODE instruction then IDCODE_REGISTER defines the expected
DEVICE_ID register capture state. If the BSDL does not define an IDCODE instruction,
then the a bit value of one is defined as the expected BYPASS register capture state.
USER RESPONSE:
information.

WARNING (TJC-212): [Severe] Unexpected result detected in scan of the register name
register following UpdateIR of instruction opcode <opcode value> for | for the instruction
name instruction. Miscompare detected in:
EXPLANATION:
BSV has detected a miscompare in the scan out of the identified register when the
identified instruction was active. This message indicates that a miscompare has
occurred on a scan out of the five bit shift signature (10011) used by BSV when verifying
the scan operation of a register.
USER RESPONSE:
information.
WARNING (TJC-213): [Severe] Unexpected result detected in consecutive scans of the

register name register when accessed by instruction opcode <opcode value> for | for the
instruction name instruction. Miscompare detected in:
EXPLANATION:
BSV has detected a miscompare in the scan out of the identified register. The identified
APN performs two back to back serial loads/unloads of the identified register. The unload
resulted in a TDO miscompare in one or more bits of the expected unload state. The first
load is used to load a known state into the identified register. The second load/unload of
the identified register contains TDO expects which were determined by the first
(preceding) load of the identified register.
USER RESPONSE:
information.
register name register following UpdateDR when accessed by instruction opcode <opcode
value> for | for the instruction name instruction. Miscompare detected in:
EXPLANATION:

BSV has detected a miscompare in the scan out of the identified data register. BSV first
preconditions the identified register was to a known/safe state, traverses through
UpdateDR, and then unloads the identified register. The TDO miscompare occurred on
the serial unload of the identified register. The TDO miscompare may be the bits of the
expected CaptureDR state and or in the five bit shift signature (10011). A miscompare in
the five bit shift signature may be reported via an additional message for this APN.
USER RESPONSE:
information.
WARNING (TJC-215): [Severe] Unexpected result detected in scan of instruction register.

Miscompare detected in:
EXPLANATION:
BSV has detected a miscompare in the scan out of the instruction register. An APN
(check) issuing this message has performed a serial load/unload of the five bit shift
signature on the instruction register. A miscompare has occurred at TDO on one or more
of the five bits. BSV uses the INSTRUCTION_LENGTH attribute in the BSDL to
determine the expected length of the instruction register.
USER RESPONSE:
information.
WARNING (TJC-216): [Severe] Unexpected result detected in capture and scan of

instruction register when ShiftIR not immediately preceded by CaptureIR. Miscompare
detected in:
EXPLANATION:
BSV has detected a miscompare in the scan out of the instruction register. An APN
(check) issuing this message has performed a CaptureIR but did not
immediately unload the instruction register. Instead, the APN traverses from the
CaptureIR state through the following states Exit1IR : PauseIR : Exit2IR : ShiftIR state.
Once in ShiftIR, a complete unload is performed on the instruction register wherein the
CaptureIR state is expected. The instruction register is loaded/unloaded with the five bit
shift signature as well and may also result in miscompares.

USER RESPONSE:
information.
WARNING (TJC-217): [Severe] TDO was not in an inactive state when the TAP controller
was not in the ShiftIR or ShiftDR state. Miscompare detected in:
EXPLANATION:
BSV has detected a miscompare at the TDO output pin. TDO is expected to be in an
inactive state (HighZ) when the TAP controller is not in the ShiftIR or ShiftDR state.
USER RESPONSE:
information.
WARNING (TJC-218): [Severe] Unexpected result detected in capture and scan of register
name register when ShiftDR not immediately preceded by CaptureDR. Miscompare detected
in:
EXPLANATION:
BSV has detected a miscompare in the scan out of the identified data register. An APN
(check) issuing this message has performed a CaptureDR but did not immediately
unload the data register. Instead, the APN traverses from the CaptureDR state through
the following states: Exit1DR : PauseDR : Exit2DR : ShiftDR state. Once in ShiftDR, a
complete unload is performed on the identified data register wherein the CaptureDR
state is expected. The data register is loaded/unloaded with the five bit shift signature as
well and may also result in miscompares. For user defined registers, BSV uses the
CAPTURES attribute of the REGISTER_ACCESS statement to determine the expected
CaptureDR state. Boundary register capture behavior is verified during IOMapping
verification.
USER RESPONSE:
information.

WARNING (TJC-289): [Severe] Register identification failed to completely identify the

register name register accessed by the instruction name instruction.
Register back | forward trace was incomplete. Register register name trace identified
number bits. The last bit identified is bsdl cell# and latch block name | unknown.
EXPLANATION:
BSV has determined that the register identification process failed to completely identify
the identified register when accessed by the identified instruction. In general, a register
is identified by putting the design in the ShiftDR state and performing a logic trace from
the scan out pin (TDO), to the scan in pin (TDI), and conversely tracing from the scan in
pin to the scan out pin.
In this instance, the logic tracing process failed to complete either the forward or back
trace process. This is an indication of a broken register. A broken register can mean
either a disconnect in the logic, or a fully connected scan path which is not fully
sensitizable in the ShiftDR state. The message identifies the number of bit positions
which were successfully identified in either the trace forward or trace back direction. Note
also that a forward trace of the register will proceed no further than the back trace.
USER RESPONSE:
Review the BSV log file to determine the name of the generated test mode (for example,
TB_<instruction>_<tap state>) to which this message applies. If you are using the GUI,
open the test mode generated by BSV and then run Report Test Structures -
Controllable/Observable scan chain Information. This will produce a register description
which will show the register latches identified by Encounter Test. You can also open the
schematic viewer for the generated test mode and put the design in the Scan (ShiftDR)
state to analyze the register scan path. Resolve/investigate an incomplete back trace
before an incomplete forward trace since the success of the forward trace is based on
the success of the back trace.
WARNING (TJC-293): [Severe] The register name register accessed by the

instruction name instruction has odd inversion. The cell: hier cell name,
corresponding to BSDL cell number:
number, is the first inverting cell nearest TDO.
EXPLANATION:
BSV has determined that the identified register when accessed by the identified
instruction has odd inversion. The message indicates the first inverting cell nearest to
TDO. There may be other inverting cells in the register. Refer to IEEE 1149.1 Rule
8.2.1(b) which states that data applied at TDI must appear at TDO without inversion.
USER RESPONSE:

Review the BSV log file to determine the name of the generated test mode (e.g.
Controllable/Observable scan chain Information. This will produce a register description
which will show the register latches identified by Encounter Test and where inversions
exist. You can also open the schematic viewer for the generated test mode and put the
circiut in the Scan (ShiftDR) state to analyze the register scan path.
WARNING (TJC-295): [Severe] The register name register has one or more scan bit
positions which become corrupt as a result of exercising the scan protocol. The number
register has number bit positions which are corrupted via the scan entry or scan
preconditioning | scan section exit, scan exit or load suffix portion of the scan protocol.
EXPLANATION:
BSV has determined that the are one or more scan bit position in the identified register
which become corrupt scanning process. The number of scan corrupt bits identified the
number of representative stim latches (RSLs) or representative measure latches (RMLs)
which are corrupted by the scanning process. Bit positions which are corrupted by scan
preconditioning lose their observability (RMLs). Bit positions which are corrupted by the
load suffix lose there stimability. A scan corrupt latch is a register latch which fails to
retain its stim or measure state at some point in the scanning process.
USER RESPONSE:
Review the BSV log file to determine the name of the generated test mode (e.g.
Controllable/Observable scan chain Information and request that floating latches be
included. This will produce a register description which will show the register latches and
corruptible latches identified by Encounter Test. You can also open the schematic viewer
for the generated test mode and put the design in the Scan (ShiftDR) state to analyze
the register scan path.
WARNING (TJC-297): [Severe] The instruction register has one or more scan bit positions
which become corrupt as a result of exercising the scan protocol. The instruction register has
number bit positions which are corrupted via the scan entry or scan
preconditioning | scan section exit, scan exit or load suffix
portion of the scan protocol.
EXPLANATION:
BSV has determined that the are one or more scan bit position is the instruction register
which become corrupt scanning process. The number of scan corrupt bits identified the
number of representative stim latches (RSLs) or representative measure latches (RMLs)
which are corrupted by the scanning process. Bit positions which are corrupted by scan

preconditioning lose their observability (RMLs). Bit positions which are corrupted by the
load suffix lose there stimability. A scan corrupt latch is a register latch which fails to
retain its stim or measure state at some point in the scanning process.
USER RESPONSE:
WARNING (TJC-300): Unexpected result detected when verifying mapping between BSDL
cell# number, latch block: block name and input pin: pin name, I/O cell: cell name.
Input pin state is: value, expected latch state is: value, actual latch state is: value.
EXPLANATION:
Verification of the mapping (correspondence) between the identified cell/latch and pin
has failed. The BOUNDARY_REGISTER description in the BSV input BSDL file defines
the mapping of I/Os and boundary cells. BSV has determined that a pin does not map to
the cell as defined by the BSDL or there is a problem with the I/O to boundary latch
mapping.
Compare the Encounter Test-generated BSDL file to the original BSDL and resolve
discrepancies.
USER RESPONSE:
One possible reason for this message is a BSDL file which does not reflect logic model
with respect to the boundary register and I/Os. Another possible reason is that the input
pin maps to the proper boundary register cell, but the I/O to boundary latch
correspondence could not be established or is established but the correspondence does
not comply with the Std (e.g. odd inversion in the correspondence path).
Use the Encounter Test write_bsdl tool to produce a BSDL file which derives the
BOUNDARY_REGISTER definition (I/O mapping) from the logic model. See "Creating
BSDL" in the Encounter Test: Guide 2:Testmodes for additional information.
Refer to "1149.1 BSV Verification Procedures (APNs)" in the Encounter Test: Guide 3:
Test Structures for a description of referenced APN.

WARNING (TJC-301): [Severe] Unexpected result detected when verifying mapping of
input pin: pin name, I/O cell: cell name BSDL cell# number, latch block: value has
an expected state of: value and an actual state of: value.
Miscompare detected in: odometer | blank APN APN name and test mode test
mode name.

EXPLANATION:
Verification has detected a problem while verifying the mapping (correspondence) for the
identified pin. The BOUNDARY_REGISTER description in the BSV input BSDL file
defines the mapping of I/Os and boundary cells. BSV has determined that the identified
cell/latch has unexpectedly changed state while verifying the mapping for the identified
pin.
USER RESPONSE:
with respect to the boundary register and I/Os. This message indicates that there is
correspondence from an I/O to a boundary latch which is not reflected in the BSV input
BSDL.
BOUNDARY_REGISTER definition (I/O mapping) from the logic model. See ""Creating
discrepancies.
WARNING (TJC-302): [Severe] Unexpected result detected when verifying mapping

between BSDL cell# number, latch block: name and output pin: pin name, I/O cell: cell
name.
Expected pin state is: value, actual pin state is: value.
odometer|blank APN APN name and test mode test mode name.
EXPLANATION:
Verification of the mapping (correspondence) between the identified cell/latch and pin
has failed. The BOUNDARY_REGISTER description in the BSV input BSDL file defines
the mapping of I/Os and boundary cells. BSV has determined that a pin does not map to
the cell as defined by the BSDL or there a problem with the I/O to boundary latch
mapping.
USER RESPONSE:
with respect to the boundary register and I/Os. Another possible reason is that the
boundary register cell maps to the proper I/O, but the boundary latch to I/O
not comply with the Std (e.g. odd inversion in the correspondence path). Another

possible reason for this messages is: if the output driver has an enable/disable capability,
it may be that the driver was not enabled either because the BSDL file is in error for this
I/O or there is a logic problem.
discrepancies.
WARNING (TJC-303): [Severe] Unexpected result detected when verifying mapping of

output pin: pin name, I/O cell: cell name Output pin: pin name has an expected state
of: logic value and an actual state of: logic value.
EXPLANATION:
Verification has detected a problem while verifying the mapping (correspondence) for the
identified pin. The BOUNDARY_REGISTER description in the BSV input BSDL file
defines the mapping of I/Os and boundary cells. BSV has determined that the second
pin identified has unexpectedly changed state while verifying the mapping for the first pin
identified.
USER RESPONSE:
with respect to the boundary register and I/Os. This message indicates that there is
correspondence from an a boundary latch to an I/O which is not reflected in the BSV
input BSDL.
discrepancies.
WARNING (TJC-304): [Severe] Unexpected result detected in the state of system output
pin: pin name, I/O cell: cell name when verifying all pins controlled by a shared enable

are driven to their active|inactive state.

Shared enable (control cell) is BSDL cell number: number, latch block: name.
Expected pin state is: value, actual pin state is: value.
Data cell is BSDL cell number: number, latch block: name.
EXPLANATION:
Verification of the mapping (correspondence) between the identified control cell/latch
and the output pins it controls has failed. The BOUNDARY_REGISTER description in the
BSV input BSDL file defines the mapping of I/Os and boundary cells. This message may
appear when BSV is verifying the functionality of a shared control (enable) cell. BSV has
determined that a data cell and or its control cell does not map to the a pin as defined by
the BSDL or there a problem with the boundary latch to I/O mapping.
USER RESPONSE:
with respect to the boundary register and I/Os. Another possible reason is that the
boundary register cell maps to the proper I/O, but the boundary latch to I/O
not comply with the Std (e.g. odd inversion in the correspondence path). Another
possible reason for this messages is: if the output driver has an enable/disable capability,
it may be that the driver was not enabled either because the BSDL file is in error for this
I/O or there is a logic problem.
discrepancies.
INFO (TJC-305): Miscompare detected in: odometer | blank APN APN name and
test mode test mode name.
EXPLANATION:
This message is the continuation of a message.
USER RESPONSE:

WARNING (TJC-306): [Severe] There must be exactly one scan input register (TDI) and
one scan output register (TDO). The number of scan input registers is number. The number
of scan output registers is number.
EXPLANATION:
BSV has determined that the test mode on which it was invoked has an inappropriate
number of scan input and or scan output registers. The test mode on which BSV is
invoked must define exactly one scan input register (TDI) and one scan output register
TDO.
USER RESPONSE:
Review the test mode definition log and test mode define file to ensure that only one TDI
register and only one TDO register is defined. Additionally, view the model statistics
information to review the register information reported for this test mode.
WARNING (TJC-307): [Severe] The lengths of the control (stim) and observe (measure)
registers must be the same. The length of the control register is number. The length of the
observe register is number.
EXPLANATION:
BSV has determined that the test mode on which it was invoked selects a register for
scan which has a different number of control and observe latches. The latches which
comprise the register are identified during the test mode definition process.
USER RESPONSE:
View the model statistics information to review the registers identified by test mode define
for this test mode.
WARNING (TJC-308): [Severe] The length of the register name register defined by the
BSDL|Standard is not the same length as the register selected for scan by the
instruction name instruction. The number defines the length of the register name
register as number bits. The register identification process determined that the length of the
register accessed by the instruction name instruction is number bits.
EXPLANATION:
BSV has determined that there is a discrepancy in the register length defined by the
BSDL/Standard and the topologically identified register length for the register selected
by the identified instruction. If this message is issued for the boundary register, it will
prevent BSV from verifying boundary register - I/O correspondence (IOmapping checks),
otherwise compliance checking is not affected.
USER RESPONSE:

One possible reason for this message is a BSDL file which does not reflect the logic
model.
BOUNDARY_REGISTER definition from the logic model.
discrepancies.
information.
WARNING (TJC-309): [Severe] No BSDL BOUNDARY_REGISTER is defined or the

BSDL BOUNDARY_LENGTH defined is defined as zero. A non-zero length
BOUNDARY_REGISTER definition is required for verifying any instruction which selects the
BOUNDARY_REGISTER.
EXPLANATION:
BSV has determined that the BSDL has no BOUNDARY_REGISTER statement defined
or is defined with BOUNDARY_LENGTH of zero. EXTEST, SAMPLE/PRELOAD and
IOmapping verification all require a non zero length boundary register definition. There
may be other instructions which can not be verified if they require the boundary register
for verification (e.g. CLAMP), or select the boundary register.
USER RESPONSE:
Review/Determine how the BSDL was produced. If using a test synthesis tool, determine
if it should have produced a BSDL boundary register information.
Alternatively, use the Encounter Test write_bsdl tool to produce a BSDL file which
derives the BOUNDARY_REGISTER definition from the logic model. See "Creating
pin: pin name, I/O cell: cell name when verifying that all system output pins are driven
to PRELOAD|active state when|while the EXTEST|CLAMP|RUNBIST
instruction becomes|is active. Expected pin state is: logic state actual pin state is:
logic state.
Miscompare detected in: odometer|blank
EXPLANATION:
BSV has detected a miscompare at the identified system output pin. An APN (check)
issuing this message expected that the identified pin was driven to a preloaded/active
state for the identified instruction. An APN issuing this message will have produced a
sequence which preconditioned the boundary register output cell associated with the

identified pin. The preconditioning of the boundary register cell occurs via the PRELOAD
instruction or via the EXTEST instruction. The preconditioning of the boundary register
output cell determines the expected state of the output pin.
USER RESPONSE:
information.
Possible reasons for this message are:
A BSDL file which does not reflect logic model with respect to the boundary
register and I/Os.
The boundary register cell maps to the proper I/O but the correspondence does
If the output driver has an enable/disable capability, it may be that the driver was
not enabled either because the BSDL file is in error for this I/O or there is a logic
problem.
Use the Encounter Test write_bsdl tool to produce a BSDL file which
derives the BOUNDARY_REGISTER definition (I/O mapping) from the logic
model. See "Creating BSDL" in the Encounter Test: Guide 2:Testmodes for
Compare the Encounter Test-generated BSDL file to the original BSDL and
resolve discrepancies.
pin: pin name, I/O cell: cell name when verifying that all system output pins retain their
previous/preload state while the instruction name instruction is active. Expected pin state is:
logic state, actual pin state is: logic state. Miscompare detected in:
EXPLANATION:
issuing this message expected that the identified pin did not deviate from its previous/
preload state for the identified instruction. This message indicates that the identified pin
did not stay at its previous/preload state over TAP FSM state transitions as expected. An
APN issuing this message will have produced a sequence which preconditioned the
boundary register output cell associated with the identified pin. The preconditioning of
the boundary register cell occurs via the PRELOAD instruction or via the EXTEST

instruction. The preconditioning of the boundary register output cell determines the
expected state of the output pin.
USER RESPONSE:
information.
with respect to the boundary register and I/Os or the BSDL does reflect the model
implementation but there is a logic problem.
If the BSDL is suspect, use the Encounter Test write_bsdl tool to produce a BSDL
file which derives the BOUNDARY_REGISTER definition (I/O mapping) from the logic
model. Review the logic implementation to determine why a particular or set of I/Os may
not be holding their state as required. See "Creating BSDL" in the Encounter Test:
Guide 2:Testmodes for additional information.
WARNING (TJC-312): [Severe] Unexpected result detected in the scan of the register
name register. Miscompare occurred on scan out of five bit shift signature when the
instruction name instruction is active. Miscompare detected in: odometer | blank
APN APN name and test mode test mode name
EXPLANATION:
BSV has detected a miscompare in the scan out of the identified register. The
miscompare has occurred on the scan out of one or more of the bits in the five bit shift
signature (10011) used by BSV to verify proper shift behavior (e.g. appropriate length,
lack of inversion). An BSV APN (check) producing this message over-shifts the register
by five bits. An APN may also produce another message which provides additional
information about other miscompares in other miscompare for the identified register. This
message may be issued by may BSV APNs (checks).
USER RESPONSE:
information.
WARNING (TJC-313): [Severe] Unexpected result detected in the scan of the register
name register. Miscompare occurred on scan out of five bit shift signature. Miscompare
detected in:

EXPLANATION:
BSV has detected a miscompare in the scan out of the identified register. The
miscompare has occurred on the scan out of one or more of the bits in the five bit shift
signature (10011) used by BSV to verify proper shift behavior (e.g. appropriate length,
lack of inversion). An BSV APN (check) producing this message over-shifts the register
by five bits. An APN may also produce another message which provides additional
information about other miscompares in other miscompare for the identified register. This
message may be issued by may BSV APNs (checks).
USER RESPONSE:
information.
WARNING (TJC-314): APN APN name and test mode test mode name
EXPLANATION:
This is the continuation of message 310. BSV has detected a miscompare at the
identified system output pin. An APN (check) issuing this message expected that the
identified pin was driven to a preloaded/active state for the identified instruction. An APN
issuing this message will have produced a sequence which preconditioned the boundary
register output cell associated with the identified pin. The preconditioning of the
boundary register cell occurs via the PRELOAD instruction or via the EXTEST
instruction. The preconditioning of the boundary register output cell determines the
expected state of the output pin.
USER RESPONSE:
information.
Possible reasons for this message:
A BSDL file which does not reflect logic model with respect to the boundary
register and I/Os.
The boundary register cell maps to the proper I/O but the correspondence does

If the output driver has an enable/disable capability, it may be that the driver was
not enabled either because the BSDL file is in error for this I/O or there is a logic
problem.
Use the Encounter Test write_bsdl tool to produce a BSDL file which
derives the BOUNDARY_REGISTER definition (I/O mapping) from the logic
model. See "Creating BSDL" in the Encounter Test: Guide 2:Testmodes for
Compare the Encounter Test-generated BSDL file to the original BSDL and
resolve discrepancies.
WARNING (TJC-315): Miscompare detected in: odometer | blank APN APN name
and test mode test mode name.
EXPLANATION:
Continuation of various messages
USER RESPONSE:
registers must be a non-zero value. The length of the control register is number. The length
of the observe register is number.
EXPLANATION:
scan which has a zero length control or observe length. The latches which comprise the
register are identified during the test mode definition process.
USER RESPONSE:
View the circuit statistics information to review the registers identified by test mode define
for this test mode.
WARNING (TJC-320): [Severe] Unexpected boundary register capture value detected

when verifying that the state of all system input pins are captured into the boundary register
when the instruction name instruction is active. The state of input pin: pin name, I/
O cell: cell name was not observed in BSDL cell number: cell number period or
latch block. Input pin state is: logic state, expected latch state is: logic state,
actual latch state is: logic state.
EXPLANATION:

BSV has detected a miscompare at the identified system input pin. An APN (check)
issuing this message expected that the state of identified pin was captured into the
identified boundary register cell while the boundary register is accessed by the identified
instruction. An APN issuing this message will have preconditioned the identified pin to a
known state which is expected to be observed in its boundary register cell(s). The
content of the boundary register cell is examined by via a serial unload of the boundary
register.
USER RESPONSE:
information.
model. See "Creating BSDL" in the Encounter Test: Guide 2:Testmodes for additional
information.
WARNING (TJC-321): [Severe] Unexpected boundary register capture value detected

when verifying that the state of bidirectional system input pins are captured into the boundary
register when the instruction name instruction is active and the I/O driver is active. The
expected state of input pin: pin name, I/O cell: cell name, was not observed in BSDL
cell number: cell number, latch block: block name. The expected latch state is: logic
state, actual latch state is: logic state.
EXPLANATION:
BSV has detected a miscompare at the identified system bidirectional pin. An APN
(check) issuing this message expected that the state of the driver sourcing the pin was
captured into the identified boundary register cell while the boundary register is
accessed by the identified instruction. An APN issuing this message will have enabled
the drive to drive an active (known) state which is expected to be observed in its
boundary register cell(s).
USER RESPONSE:
Verification Results File" in the Encounter Test: Guide 3: Test Structures for

model. See "Creating BSDL" in the Encounter Test: Guide 2:Testmodes for additional
information.
pin: pin name, I/O cell: cell name when verifying that all system output pins with an
inactive state are driven to their inactive state when the instruction name
instruction becomes|is active. Expected pin state is: logic value actual pin
state is: logic value.
Miscompare detected in: odometer|blank APN APN name and test mode test
mode name.
EXPLANATION:
issuing this message expected that the identified pin was driven to its inactive state for
the identified instruction was active or became active. An APN issuing this message will
have produced a sequence which preconditioned the boundary register output cell
associated with the identified pin. This includes both the data cell and the enable cell. All
output pins are preconditioned to an active (known) state. The APN (check) then loads
the boundary register a second time to set all drivers to their inactive state. The pins
which are participating in this check are expected to switch to their inactive state on the
falling edge of the TCK clock pulse which triggers entry into the UpdateDR state. The
BOUNDARY_REGISTER description in the BSV input BSDL file defines system output
pins capable of driving an inactive state (any output capable pin with a disable spec).
USER RESPONSE:
file which derives the BOUNDARY_REGISTER definition from the logic model.

information.
pin: pin name, I/O cell: cell name when verifying that all system output pins are driven
to the HIGHZ state when the instruction name instruction becomes active. Actual pin
state is: logic value. Miscompare detected in: odometer | blank APN APN name
and test mode test mode name.
EXPLANATION:
issuing this message expected that the identified pin was to be driven to the HIGHZ state
when the identified instruction became active. The APN expects that all pins will be
driven to the HIGHZ state on the falling edge of the TCK clock pulse which triggers entry
into the UpdateIR state. Support for the HIGHZ instruction requires that all system output
pins be capable of being driven to the HIGHZ state.
The same behaviour is expected for a RUNBIST instruction with a
RUNBIST_EXECUTION statement which defines that all system output pins will be
driven to the HIGHZ state.
USER RESPONSE:
pin: pin name, I/O cell: cell name when verifying that all system output pins remain in the
HIGHZ state while the instruction name instruction is active. Actual pin state is: logic
value. Miscompare detected in:
odometer | blank APN APN name and test mode test mode name.
EXPLANATION:
issuing this message expected that the identified pin was to remain in the HIGHZ state
while the identified instruction became active. The APN issuing this message first
attempted to set all system output pins to the HIGHZ state and then expected they would
remain in the HIGHZ state while traversing through various TAP states. A separate
message is issued if the pin did not switch to the HIGHZ state as expected. Support for
the HIGHZ instruction requires that all system output pins be capable of being driven to

the HIGHZ state. The same behaviour is expected for a RUNBIST instruction with a
RUNBIST_EXECUTION statement which defines that all system output pins will be
driven to the HIGHZ state.
USER RESPONSE:
WARNING (TJC-336): [Severe] There must be exactly one scan input register (TDI) and
one scan output register (TDO) when building test mode number. The number of scan input
registers is number. The number of scan output registers is number.
EXPLANATION:
BSV has determined that the test mode on which it was invoked has an inapropriate
number of scan input and or scan output registers. The test mode on which BSV is
invoked must define exactly one scan input register (TDI) and one scan output register
(TDO).
USER RESPONSE:
Review the test mode definition log and test mode define file to ensure that only one input
register and one output register is defined. Additionally, view the circuit statistics
information to review the register information reported for this test mode.
registers must be a non-zero value for test mode number. The length of the control register
is number. The length of the observe register is number.
EXPLANATION:
scan which has a zero length control or observe length. $ The latches which comprise
the register are identified during the test mode definition process.
USER RESPONSE:
View the circuit statistics information to review the registers identified by test mode define
for this test mode.
WARNING (TJC-350): [Severe] No boundary register parallel (update) latch identified for
control cell: hier cell name, at BSDL bit position number.
EXPLANATION:

The BSDL defines the identified boundary register scan bit position as a CONTROL(R)
cell, however register identification failed to identify a parallel update latch for the cell.
This may result in failing boundary register I/O mapping checks when an I/O pin which
uses the identified bit position fails to behave as expected.
USER RESPONSE:
Use the BSDL BOUNDARY_REGISTER definition to determine which I/Os are
controlled by the identified CONTROL(R) cell. Determine if any I/O pin is called out in
additional error messages. Use the schematic view to review the logic associated with
both the data and control paths for the failing I/O. If no other messages point back to the
identified CONTROL(R) cell, determine if the cell should be a identified as a
CONTROL(R) cell. There may be additional BSDL parse related messages for the
identified cell as well.
WARNING (TJC-351): [Severe] No boundary register parallel (update) latch identified for
scan/capture cell: hier cell name, at BSDL bit position number.
EXPLANATION:
The BSDL defines the identified boundary register scan bit position as a OUTPUT2,
OUTPUT3, or BIDIR cell, however register identification failed to identify a parallel
update latch for the cell. This may result in failing boundary register checks when an I/O
pin which uses the identified bit position fails to behave as expected.
USER RESPONSE:
Determine if the I/O associated with the identified BSDL bit position is called out in
additional error messages. Use the schematic view to review the logic associated with
both the data and control paths for the failing I/O. If no other messages point back to the
identified cell and bit position, determine if the cell should be a identified as a OUTPUT2,
OUTPUT3, or BIDIR cell. There may be additional BSDL parse related messages for the
identified cell as well.

WARNING (TJC-500): [Severe] Not authorized to write to the file: results file.
EXPLANATION:
The file permissions of the file prohibit BSV from writing the identified file
USER RESPONSE:
Modify the file access permissions to provide write access.

WARNING (TJC-501): [Severe] Unable to open the file: file name.

EXPLANATION:
The identified file could not be opened.
USER RESPONSE:
Ensure that the path and file name is correct and that the file exists with appropriate file
access permission.
ERROR (TJC-510): [Internal] Unexpected error detected during verification.

EXPLANATION:
USER RESPONSE:
WARNING (TJC-511): WORKDIR was not specified and is a required parameter.

EXPLANATION:
WORKDIR is a required parameter which specifies the top-level directory structure
where your imported model and the results of Encounter Test applications reside.
USER RESPONSE:
Specify WORKDIR on the command line or as an exported variable.
WARNING (TJC-513): [Severe] TESTMODE was not specified and is a required

parameter.
EXPLANATION:
TESTMODE is a required parameter which specifies the name of a predefined test
mode.
USER RESPONSE:
Specify TESTMODE on the command line or as an exported variable. Specify the name
of the 1149.1 test mode which was defined at the test mode define step for the model
being processed.
ERROR (TJC-514): Unable to obtain read | write lock for the object name.
Processing Terminates.
EXPLANATION:

The application was unable to obtain a read/write lock on the named object.
USER RESPONSE:
Ensure that the specified file exists with file permissions that allow you read access.
ERROR (TJC-515): Unable to obtain read lock for the test mode name. Processing
Terminates.
EXPLANATION:
The application was unable to obtain a read lock on the test mode.
USER RESPONSE:
Ensure that TESTMODE is set correctly for the design being processed. Ensure that the
model-related files exist with file permissions that allow you read access.
ERROR (TJC-516): Unable to obtain license for IEEE 1149.1 Boundary Scan Verification.
EXPLANATION:
IEEE 1149.1 Boundary Scan Verification requires a license; however, a license for the
1149.1 BSV was not was not obtained.
USER RESPONSE:
Obtain a license for the IEEE 1149.1 Boundary Scan Verification application . It also is
possible a license may exist but may be in use by another process.
ERROR (TJC-517): [Internal] Unexpected error on request|free of flatModel context.

EXPLANATION:
USER RESPONSE:
ERROR (TJC-518): Unable to load the hierModel for the circuit.

EXPLANATION:
The Encounter Test model could not be properly loaded into storage. There may be
something wrong with the Encounter Test model files.
USER RESPONSE:
Re-import the design to create new Encounter Test model files.

ERROR (TJC-519): Unable to set mode using TESTMODE = name.

EXPLANATION:
The specified testmode could not be properly loaded into storage. There may be
something wrong with the test mode files.
USER RESPONSE:
Recreate the test mode to create new test mode files.
ERROR (TJC-520): [Internal] Unexpected error on unload of flat model.

EXPLANATION:
USER RESPONSE:
ERROR (TJC-522): [Internal] Unexpected error detected in creating HierPortMap.

EXPLANATION:
USER RESPONSE:
ERROR (TJC-523): [Internal] Unexpected error detected in creating simulation interface.

EXPLANATION:
USER RESPONSE:
ERROR (TJC-524): BSV cannot perform verification using the test mode test mode
name since the test mode limits BSV to verifying a portion of the total 1149.1 logic
implementation. The test mode was defined with instruction: instruction name |
instruction opcode and TAP_TG_STATE: tap_tg_state name.
EXPLANATION:
Boundary Scan Verification has determined that the selected test mode is inappropriate
for running BSV. This may be due to one or more of the following:

The test mode is defined with a scan type which is not 1149.1.
The test mode is defined with an unsupported 1149.1 INSTRUCTION and or
TAP_TG_STATE.
.BSV may only be invoked on a test mode which defines no INSTRUCTION and
TAP_TG_STATE.
USER RESPONSE:
Make necessary adjustments to the mode test mode definition file and rerun test mode
define. Alternatively, select a test mode which meets the criteria for running 1149.1 BSV.
Refer to Creating an 1149.1 Test Mode for Boundary Scan Verification in the
Encounter Test: Guide 3: Test Structures for additional information.
ERROR (TJC-525): [Internal] Unexpected application error detected in - errorText.

EXPLANATION:
USER RESPONSE:
ERROR (TJC-526): A BSDL file is required for Boundary Scan Verification. A BSDL input
file was not specified or could not be opened.
EXPLANATION:
Boundary Scan Verification requires a BSDL input file however, a BSDL input file was not
specified or could not be opened.
USER RESPONSE:
Ensure that a BSDL input file is specified and that the BSDL file exists in the directory
specified.
WARNING (TJC-527): An oscillation occurred during verification of group in test test

(ATSN:number) vector vector on net net. Results may not be valid beyond this test. (net
set to X)
EXPLANATION:
An oscillation occurred during simulation which required the simulator to set some nodes
to X. Further simulation could give invalid results.
USER RESPONSE:
Remove the oscillation from the design.

ERROR (TJC-529): Verification cannot continue due to reason.

EXPLANATION:
USER RESPONSE:
necessary.
ERROR (TJC-530): Unable to register object name in the globalData file.

EXPLANATION:
BSV was not able to register the named object to the circuits globalData file. A
terminating error has occurred.
USER RESPONSE:
necessary.
ERROR (TJC-531): Unable to save the globalData file following updates for experiment.
EXPLANATION:
BSV was unable to save updates it made to the circuits globalData file in support of the
identified object. A terminating error has occurred.
USER RESPONSE:
information relating to why the run terminated. If such a message exists,
refer to the corresponding explanation/response. Otherwise, note the reason given in this
message and contact customer support (see Contacting Customer Service on
page 23) if necessary.

TFK-100 through TFK-101

ERROR (TFK-100): Message File Incompatible. File written in version incompatible with
version trying to read it.
EXPLANATION:
TFK Message File versions are not backward compatible. New version can read old
version, but not vice-versa.
USER RESPONSE:
There is version incompatibility for the TFK message file produced by Encounter Test
RPCT/IEEE 1149.1 Boundary Scan Verification. Refer to the explanation and process
accordingly.
INFO (TFK-101): Message File not created. No messages available for Analysis.
EXPLANATION:
Messages supporting interactive analysis are not available in this test mode.
USER RESPONSE:
ERROR (TJC-999): [Internal] An unexpected condition occurred in the Encounter(R) Test

verify_11491_boundary code. Contact Cadence Customer Support to report this error
and give them the following information:
An error occurred on line line_number of source file file_name:
variable_text
EXPLANATION:
USER RESPONSE:
direct call to the customer support line (see Contacting Customer Service on page 23),
and provide the complete text of the message. This will allow the programmer to find and
fix the problem more quickly.

45
TLD - Signature-Based Test Messages
TLD-001 through TLD-999 on page 1459
TLD-001 through TLD-999

WARNING (TLD-001): [Severe] Test Structure Verification Mode Compatibility Checks
failed. The resulting Stored Pattern test data may be invalid.
EXPLANATION:
The validity of converted test data can only be assured when the source and target (child
and parent) test modes are compatible as determined by the TSV Mode Compatibility
Checks. Since these checks failed in this instance, the converted test data may be
invalid.
USER RESPONSE:
Refer to the messages resulting from the TSV Mode Compatibility Checks and take
appropriate corrective action if desired. Otherwise, this message can be ignored at risk.
WARNING (TLD-002): [Severe] Test Structure Verification Mode Compatibility Checks

were not run. The resulting Stored Pattern test data may be invalid.
EXPLANATION:
The validity of converted test data can only be assured when the source and target (child
and parent) test modes are compatible as determined by the TSV Mode Compatibility
Checks. Since these checks were not run in this instance, the converted test data may
be invalid.
USER RESPONSE:
Run TSV Mode Compatibility Checks and take appropriate corrective action if desired.
Otherwise, this message can be ignored at risk.
ERROR (TLD-003): Unable to open output uncommitted pattern file file_name. Run
ends.

EXPLANATION:
The indicated file could not be opened as required. The run terminates.
USER RESPONSE:
file system and that file permissions are set correctly and rerun. If problems persist,
INFO (TLD-004): Successfully wrote the output Vectors file.

EXPLANATION:
Informational message informing that the output Vectors file was successfully generated.
USER RESPONSE:
WARNING (TLD-005): [Severe] Failed writing the output Vectors file.

EXPLANATION:
The output Vectors file failed to be written. No output test data will result.
USER RESPONSE:
Ensure there is sufficient space in the file system and that file permissions are set
correctly and rerun. If problems persist, contact customer support (see Contacting
ERROR (TLD-006): Unable to open input uncommitted pattern file fileName. Run ends.
EXPLANATION:
The indicated file could not be opened as required. The run terminates.
USER RESPONSE:
Ensure that the part parameters specified are correct, that file permissions are set
correctly and rerun. If problems persist, contact customer support (see Contacting
ERROR (TLD-007): Invalid scan section number in scanop sequence. Run ends.
EXPLANATION:
TBDscanSectionNumber(scanopID) returned the scan section number that is > 1. The
Scan_Entry_Sequence and Scan_Exit_Sequence is given scan section number of 0.

The Scan_Section_Sequence has scan section number of 1. If there are multiple scan
section protocols in child testmode, scan section may be greater than 1. It is assumed
that there will only be one scan section in child testmode.
USER RESPONSE:
Determine whether there are multiple Scan_Section_Sequences in scanop sequence in
the child testmode.
If there are, contact customer support (see Contacting Customer Service on page 23)
for code update.
WARNING (TLD-110): Stim_PPI event is ignored during convert to stored pattern process.
There are no PPIs defined in parent mode.
EXPLANATION:
The Stim_PPI in the child modes conversion (copied) to stored pattern causes
undesireable cores. Stored patterns are written in the parent mode. When the parent
mode does not have the same PPI/cutpoints as the child mode, the converted stored
pattern produces wrong results.
USER RESPONSE:
Ensure a corresponding Stim_PI event exists for a Stim_PPI event so that the data is
properly initialized.
WARNING (TLD-111): [Severe] child mode PPI name PPI in child mode does not
exist in the parent mode Cannot stim this PPI during convert to stored pattern process.
Converted patterns are suspect.
EXPLANATION:
Stored patterns are written in the parent mode and when that parent mode does not have
the same PPI/cutpoints as the child mode, the converted stored pattern produces wrong
results. PPIs in child modes Stim_PPI event are translated to parent modes Stim_PPI
event during conversion to stored pattern. There are PPIs defined in the child mode that
are not defined in the parent mode. Encounter Test tries to map it as much possible, but
the extra PPIs in the child mode may cause data to be uninitialized in the parent mode
and may result in incorrect stored pattern vectors.
USER RESPONSE:
Ensure a corresponding Stim_PI event exists for a Stim_PPI event so that the data is
properly initialized.
INFO (TLD-705): Test Range Groups:

EXPLANATION:
Informational message indicating print of test range groups is to follow.
USER RESPONSE:
ERROR (TLD-999): [Internal] The following internal program error occurred on line
line_number of file "file_name":
variable_text
EXPLANATION:
The program has encountered an unexpected condition which requires investigation by
the software provider.
USER RESPONSE:
Contact customer support (see Contacting Customer Service on page 23), providing
the text from this message.

46
TJM - IEEE 1149.1 Boundary Scan Chain
Test Mode Define Messages
TJM-100 through TJM-105 on page 1463
TJM-100 through TJM-105

INFO (TJM-100): IEEE 1149.1 BSDL parser process started: date time
EXPLANATION:
None.
USER RESPONSE:
INFO (TJM-101): IEEE 1149.1 BSDL parser process ended: date time
EXPLANATION:
None
USER RESPONSE:
INFO (TJM-102): Processing errors have occurred. Refer to prior messages for details.
EXPLANATION:
None.
USER RESPONSE:
ERROR (TJM-103): [Internal] Problem occurred while writing to the globalData file.

TJM - IEEE 1149.1 Boundary Scan Chain Test Mode Define Messages
EXPLANATION:
None
USER RESPONSE:
WARNING (TJM-104): [Severe] A test mode name was not specified or was specified but
is incorrect.
EXPLANATION:
A test mode name is required. The TESTMODE parameter/environment variable was not
specified or was specified, but is incorrect.
USER RESPONSE:
Verify that a valid TESTMODE specification has been made.
INFO (TJM-105): TJMmode <flags> where: <flags>

-h : specify this option to print this help
TJMmode is not a user application. TJMmode is an executable used by testmode define.
TJMmode serves as a interface between the BSDL parser (TJB) and test mode define
(TTM).
EXPLANATION:
None
USER RESPONSE:

47
TLH - Linehold Messages
TLH-001 through TLH-050 on page 1465

TLH-051 through TLH-999 on page 1482
TLH-001 through TLH-050

WARNING (TLH-001): [Severe] No linehold file specified. No lineholds parsed.
EXPLANATION:
The application requested linehold support but there was no linehold file specified.
USER RESPONSE:
Ensure that you specified a filename on the LINEHOLD= parameter. If your input looks
correct, contact customer support (see Contacting Customer Service on page 23) for
assistance.
WARNING (TLH-002): [Severe] Linehold file filename does not exist. No lineholds
parsed.
EXPLANATION:
The linehold file specified with the LINEHOLD parameter did not exist. The name entered
is shown in the message.
USER RESPONSE:
Determine the name of the linehold file and restart the application with
LINEHOLD=correct name. Or remove the LINEHOLD parameter and run the application
without lineholds.
WARNING (TLH-003): [Severe] Failed to open linehold file filename. No lineholds

parsed.
EXPLANATION:

The linehold file you specified exists but the application program was unable to open it.
Generally this means the logon-id that started the application does not have permission
to read the file.
USER RESPONSE:
Ensure you specified the correct linehold file name (the input name is given in
the message).
Ensure you have read authority for the file.
NFS: Use ls -l filename to list the file permissions for owner, group, user
(you must have at least r (read) permission). Use groups to find out what
group you are in. Use chmod, chgrp, or chown to change the file permissions,
groups, or ownership.
AFS: Use fs listacl to list the directorys access list (you must have at least
rl (read and lookup) permission. Use pts to find out the membership of a
group. Use fs setacl to change the directorys access list.
WARNING (TLH-004): [Severe] Unrecognized statement on line line_number:

statement.
EXPLANATION:
The statement on the indicated line of the linehold file is not recognized.
USER RESPONSE:
Edit the linehold file and change the indicated line to contain valid linehold syntax. Refer
to Linehold File in the Automatic Test Pattern Generation User Guide for additional
information.
WARNING (TLH-005): [Severe] Unable to resolve Pin|Net|Block|PPI name in

statement statement_number, line line_number.
EXPLANATION:
The name specified in the indicated statement and line is not recognized as valid for this
model.
USER RESPONSE:
Ensure that the LINEHOLD file is correct for this model.
Ensure that the name specified is the correct name for the object. This must be
the proper name--either long or short form is acceptable.

Ensure that the indication of PIN, BLOCK, NET, or PPI is accurate for the
specified name. If you did not specify PIN, BLOCK, NET, or PPI, it defaults to
PIN.
WARNING (TLH-006): [Severe] Statement_name value of value on line

line_number is invalid. Recognized values are values.
EXPLANATION:
The indicated line number of the linehold file has a HOLD or a DEFAULT command with
a value that is not recognized by Encounter Test.
USER RESPONSE:
Edit the linehold file and change the value on the indicated line number. In general, valid
values for the HOLD statement are 0, 1, Z, X, W, L, and H, and valid values for the
DEFAULT statement are 0, 1, Z, L, and H.
INFO (TLH-007): Statement_name value of value was specified for a correlated

Pin|Net|Block|PPI name at line line_number. It has been translated to a
Statement_name on Representative Pin|Net|Block|PPI name to a value of
value.
EXPLANATION:
A non-representative member of a correlated group was used in a Hold or Default
statement. A Hold or Default on this member implies a corresponding Hold or Default on
all other member(s) of the correlated group. By convention, the Hold or Default is
translated to the representative member, with all non-representative member(s) implicitly
receiving values in accordance with their relation to the representative.
USER RESPONSE:
This message may point to an error if a line-hold conflict is detected with any of the
correlated pins, resulting in the appearance of message TLH-020.
WARNING (TLH-008): [Severe] Pin|PPI name on line line_number is a

test_function and cannot be held or defaulted out of stability.
EXPLANATION:
You may not use a linehold to change/remove an existing Test Inhibit (TI) or Test
Constraint (TC) specification since that would change the definition of the test mode (that
is, the active logic in the test mode would be different).
USER RESPONSE:
If you did not intend to change a TI or TC value:

Ensure the object (Pin, Net, Block, or PPI) and name you specified on the
indicated line is accurate. If not, correct the indicated line in the linehold file and
rerun this application.
Ensure you specified the correct test mode name. If not, correct the test mode
specification (TESTMODE= on the command line; Select Existing Test Mode
from the graphical interface) and rerun.
If you did intend to change a TI or TC value:
If you were doing an append to an existing experiment, commit the existing
uncommitted data.
Copy the existing test mode definition file and add/change the assignment
statement for this TI or TC. Do not change the TDR or COMET information.
Run Define Test Mode to build the new test mode.
Run TSV to analyze the effect of changing/removing the TI or TC (optional)
Run the application on the new mode.
Since the two test modes will be in the same COMET, the faults already marked
tested in the original test mode will not be processed again in this test mode.
WARNING (TLH-009): [Severe] Pin|Net|Block|PPI name on line line_number

cannot be held to value because it is not a three-state element.
EXPLANATION:
Only three-state Pins, Nets, Blocks, or PPIs can be set to high impedance (Z).
USER RESPONSE:
Edit the indicated line number in the linehold file and change the value or the name.
Rerun the application to have the new linehold included.
INFO (TLH-010): Pin|PPI name on line line_number is a test function Pin|PPI held
out of stability.
EXPLANATION:
The linehold on the indicated line number is opposite of the stability value.
USER RESPONSE:
This pin/PPI has a stability value. Lineholding it may significatnly affect test coverage.
Also note that this linehold may not be honored during the scan operation or other times
when the stability value is required for proper test data.


is a test function Pin|PPI held out of stability.
EXPLANATION:
The latch you have applied a linehold to on the indicated line is not controllable in this
test mode. Therefore, the linehold cannot be applied.
USER RESPONSE:
Ensure your specification on the indicated line of the linehold file is accurate. If
not, correct the indicated line in the linehold file and rerun this application.
If you expect the latch to be controllable in this test mode, use TSV to analyze
latch/flip-flop scan characteristics. Correct the problems found with TSV
analysis, rebuild the test mode and rerun this application.

is a fixed value latch and cannot be defaulted.
EXPLANATION:
A Linehold fixed value latch is by definition, held to a fixed value (logic 0 or 1). While you
may hold it to a value opposite its flagged value, you may not specify a default on it to
either value. A default implies the value may be changed, and it is not possible to change
the value on a fixed value latch because it is not controllable in the test mode in which
its value is fixed.
USER RESPONSE:
Ensure that you specified the correct name for the latch on the indicated line in
the linehold file.
If you did not expect the latch to be an LH fixed value latch, review your test
mode definition information.
If you intended to hold the latch instead of default it, correct the statement on
the indicated line in the linehold file.

is a test_function fixed value latch and cannot be held to value.
EXPLANATION:

The value of a Test Inhibit or Test Constraint fixed value latch is, by definition, fixed. You
cannot hold it to a different value.
USER RESPONSE:
Ensure that you specified the correct name for the latch on the indicated line in
the linehold file.
If you did not expect the latch to be TI or TC fixed value latch, review your test

corresponds to a Clock Chopper|RAM or ROM|Tied Pin, Net, Block, or
PPI|Invalid Pin, Net, Block, or PPI and cannot be held.
EXPLANATION:
The Pin, Net, Block, or PPI on the indicated line in the linehold file corresponds to the
indicated type of model element. Clock Choppers (CHOP blocks), RAMs, ROMs and
Tied logic cannot be lineheld.
If the message indicates the Pin, Net, Block, or PPI is invalid, it means the name you
specified corresponds to a Pin, Net, Block, or PPI that is not in the test mode.
USER RESPONSE:
Ensure that the name you specified on the indicated line is correct. If not,
correct the indicated line in the linehold file and rerun this test generation
experiment.
WARNING (TLH-015): [Severe] Syntax error on line line_number - comment delimiter

detected within a comment. Linehold parsing ends.
EXPLANATION:
The indicated line number has a syntax error.
USER RESPONSE:
Correct the indicated line in the linehold file and rerun the application.
WARNING (TLH-016): [Severe] Syntax error on line line_number - comment

terminator detected outside comment. Linehold parsing ends.
EXPLANATION:

The indicated line number has a syntax error.

USER RESPONSE:
Correct the indicated line in the linehold file and rerun the application.
WARNING (TLH-017): [Severe] No Pin|Net|Block|PPI name was found in the

statement on line line_number.
EXPLANATION:
The indicated line in the linehold file had a HOLD, DEFAULT, or RELEASE statement
without a name.
USER RESPONSE:
Edit the linehold file and include a name in the statement on the indicated line.
WARNING (TLH-018): [Severe] No value was specified for the Statement_name

EXPLANATION:
The HOLD or DEFAULT statement is used to hold a specific net to a specific value. No
value was specified in the statement on the indicated line.
USER RESPONSE:
Edit the linehold file and include the value you want the Pin, Net, Block, or PPI held to.
WARNING (TLH-019): [Severe] Block name on line line_number has multiple outputs
and thus cannot be held.
EXPLANATION:
The HOLD statement is used to linehold a specific point to a specific value. When you
linehold a block to a value, it is equivalent to holding the output of the block to that value.
However, when the block has multiple outputs, the definition of holding the block to a
value is ambiguous. Therefore, the linehold cannot be processed.
USER RESPONSE:
Edit the linehold file and change the name specification on the indicated line so it points
to the specific output Pin (or Net) that you want held to the specified value.
WARNING (TLH-020): Pin|Net|Block|PPI name on line line_number was

previously specified. The statement on line winning_line_number is used.
EXPLANATION:

You either have a duplicate name specified in the linehold file or have specified a Pin or
PPI which was already being held due to a linehold (LH) test function flag. The value on
winning_line_number is used.
USER RESPONSE:
If the value in the statement on the winning_line_number is desired, no action is required.
Otherwise, edit the linehold file and correct the appropriate statement(s) and rerun the
application.
WARNING (TLH-021): [Severe] Default value of value is invalid in the statement on line
line_number.
EXPLANATION:
The value you are attempting to use on a DEFAULT statement is invalid. Valid values for
the DEFAULT statement are 0, 1, Z, L, and H.
USER RESPONSE:
Specify a valid value or remove the statement.
Refer to "Special Rules for the HOLD and DEFAULT statements" in the Automatic Test
Pattern Generation User Guide for additional information.
WARNING (TLH-022): [Severe] Pin|PPI name on line line_number is a clock and

cannot be held to value (the ON value).
EXPLANATION:
Clocks cannot be lineheld ON.
USER RESPONSE:
Edit the linehold file and remove the linehold or change the value -- you can linehold the
clock OFF.
WARNING (TLH-023): [Severe] Pin|PPI name on line line number cannot be

released because it is not flagged as a Linehold (LH).
EXPLANATION:
The Pin, Net, Block, or PPI specified in the RELEASE statement did not have a Linehold
(LH) specified in the design source (or test mode file). Therefore, there is nothing to
release.
USER RESPONSE:

If the name is in error, edit the linehold file to change the name to the correct Pin, Net,
Block. or PPI. If you think the name is correct, ensure that you specified the correct object
type -- the default is PIN. Correct the linehold file and rerun the application.
INFO (TLH-024): Pin|PPI name on line line_number is a test function Pin|PPI

held to stability.
EXPLANATION:
The indicated Pin, Net, Block, or PPI will be held to the stability value throughout the
application.
USER RESPONSE:
INFO (TLH-025): Pin|Net|Block|PPI name on line line_number is a fixed value

latch held to the flagged value.
EXPLANATION:
The indicated fixed value latch is held to the flagged ("+" = logic 1, "-" = logic 0) value.
USER RESPONSE:
INFO (TLH-026): Parsing linehold file linehold_file_name. Extracting

statement_types.
EXPLANATION:
Indicates the name of the file that contains the linehold information. Only information
contained in the referenced statements will be extracted for use in subsequent
processing.
USER RESPONSE:
WARNING (TLH-027): [Severe] The specified latch values cannot be loaded through a
scan operation.
EXPLANATION:
It is a requirement that a scan operation can be used to set all the latch values in your
linehold file. There is something in your latch linehold specification that would require
more than a simple scan operation to set up the values.

USER RESPONSE:
Evaluate the linehold values you specified on the latches and make changes so that all
the latches can be set using a scan operation. If this can not be done, you may need
manual patterns rather than simply a set of lineholds.
INFO (TLH-028): The following lineholds are currently in effect:

EXPLANATION:
Following this message is a list of the lineholds in effect for the run. The list is determined
from your Hold/Release specifications and the test function pins and PPIs defined for this
test mode and may consist of:
Holds on LH (Linehold) flagged pins and PPIs (not having been Released)
Holds on LH (Linehold) flagged fixed value latches
Default Values on OI (Output Inhibit) flagged pins and PPIs to the inhibiting
value
Default Values on CI (Clock Isolation) flagged pins and PPIs to the non-stability
value
Default Values on +/-SE (Scan Enable) pins and PPIs to the non-stability value
Holds and Default Values derived from statements specified in the user linehold
file
USER RESPONSE:
No response is required if the linehold list is consistent with your expectations.
Otherwise, you should stop the run and alter the linehold inputs to ensure the linehold
set matches expectations prior to rerunning the application.
INFO (TLH-029): There are currently no lineholds in effect.

EXPLANATION:
There are no lineholds in effect (either you did not specify any, or you used RELEASE to
release the only ones that were specified.
USER RESPONSE:
No response required, this is simply a confirmation message.

WARNING (TLH-030): [Severe] Severe error condition(s) were detected during linehold
processing. The linehold set is unacceptable.
EXPLANATION:
This is a summary message to indicate the highest severity of the linehold processing
messages.
USER RESPONSE:
Review the individual messages. Make corrections to the linehold file and rerun the
application.
WARNING (TLH-031): [Severe] Justification of held internal Pin(s), Net(s), and/or Block(s)
aborted prior to finding a solution.
EXPLANATION:
When you specify lineholds on internal Pins, Nets, or Blocks (that is, not Primary Inputs
or Pseudo Primary Inputs), the values are converted to values on controllable points (i.e.,
primary inputs and/or scannable latches). This conversion is done with the test
generation justification process, which in this instance, aborted prior to finding a solution.
USER RESPONSE:
The lineholds you specified cannot be achieved. Change the lineholds and rerun the
application.
detected unresolvable conflict(s).
EXPLANATION:
generation justification process. The internal values could not be justified without
conflicts (that is, they cannot all occur simultaneously).
USER RESPONSE:
Analyze the linehold values you specified to determine which values are really required.
Change the linehold file and rerun the application.
requires a value from array output|non-scan latch Pin|Net|Block name.
EXPLANATION:

generation justification process. In order to justify your internal lineholds, an array (RAM
or ROM) output or non-scannable latch is required at value. Since arrays and non-scan
latches cannot be lineheld to a value, your internal lineholds cannot be processed.
USER RESPONSE:
Analyze the lineholds you specified on internal Pins, Nets, and Blocks to determine
whether you can select a different set of lineholds that does not require an array or non-
scan latch at value. Change the linehold file and rerun the application.
requires clock Pin|PPI name held to value (the ON value).
EXPLANATION:
generation justification process. In order to justify your internal lineholds, the indicated
clock had to be stimmed to the ON value. Clocks may not be lineheld ON.
USER RESPONSE:
Analyze your linehold values to determine whether you can select a different set of
lineholds that does not require a clock to be lineheld ON. Change the linehold file and
rerun the application.
INFO (TLH-035): All statements were parsed successfully.

EXPLANATION:
The linehold file you specified has been processed successfully.
USER RESPONSE:
INFO (TLH-036): Attempting to justify Held|Defaulted internal Pin(s), Net(s), and/or

Block(s).
EXPLANATION:

generation justification process. The justification process is starting. You will see
additional messages to indicate whether it has been successful.
USER RESPONSE:
INFO (TLH-037): All Held|Defaulted internal Pin(s), Net(s), and/or Block(s) were
justified successfully.
EXPLANATION:
generation justification process. The justification process has completed successfully, so
your internal lineholds are acceptable.
USER RESPONSE:
INFO (TLH-038): Statement_name on latch Pin|Net|Block|PPI name to a value of

value has been translated to a value of value on Representative Stim Latch
Pin|Net|Block|PPI name.
EXPLANATION:
For ease of processing, the linehold value you specified on the indicated latch has been
converted to the equivalent value on a related latch (Representative Stim Latch). You do
not need to be concerned about this, but this message lets you know how your input is
processed.
USER RESPONSE:
INFO (TLH-039): Pin|PPI name has been successfully released by way of the Release
EXPLANATION:
The specified Pin or PPI has been released.
USER RESPONSE:

WARNING (TLH-040): Pin|PPI name in the Release statement on line line_number

was not previously held. The Release statement is ignored.
EXPLANATION:
The specified Pin or PPI was not being held, therefore is already released.
USER RESPONSE:
Ensure the correct Pin or PPI was specified. If incorrect, correct the specification and
rerun. Otherwise, disregard this message understanding that the Pin or PPI identified, is
not being held.
WARNING (TLH-041): [Severe] Linehold value of value is not valid for

Pin|Net|Block|PPI name on line line_number.
EXPLANATION:
The value you are attempting to use in the indicated statement is not valid for the
associated object (block, pin, net, or PPI). The following table shows the valid values for
each node function.
Linehold Value
---------------------------------
Node Function | 0 1 Z X W L H | Applicable notes
----------------------------------------------------------------------
PI | * * * * | 1 - 4
LATCH | * * | 3, 5
TSD | * * * | 6
NTSD | * * * | 6
DOTT | * * * | 6
PO | * * * | 6
BUF | * * * | 6
NBUF | * * * | 6
XOR | * * * | 6
XNOR | * * * | 6
OR | * * * | 6
NOR | * * * | 6
AND | * * * | 6
NAND | * * * | 6
NFET | * * * | 6
PFET | * * * | 6
RESISTOR | * * * * | 6
RAM | | 7
ROM | | 7
CHOPT | | 7
NCHOPT | | 7
CHOPL | | 7
NCHOPL | | 7
TIUP | | 7
TIDN | | 7
TIX | | 7
TIH | | 7
TIOSC | | 7
Notes:

------
1. A non-contacted PI may be lineheld only to X or Z.
2. A contacted PI may be lineheld to Z only if three-state.
3. A test inhibit or test constraint PI or FVL may not be lineheld opposite the
test function value.
4. A clock PI may not be lineheld opposite stability.
5. A latch may be lineheld only if scannable or fixed value.
6. An internal (non-controllable) node must be able to attain the value through
justification.
7. Arrays, clock choppers, and ties may not be lineheld.
USER RESPONSE:
Specify a valid value for this statement or remove the statement.
WARNING (TLH-042): [Severe] Pin name on line line_number cannot be held to

value in test mode testmode_name because it is not contacted by the tester.
EXPLANATION:
The linehold on the indicated line number is not valid because the associated pin is not
contacted by a tester pin, thereby rendering the pin non-controllable in this test mode.
USER RESPONSE:
Ensure your specification on the indicated line of the linehold file is accurate. If
not, correct the indicated line in the linehold file and rerun this application.
name specification (TESTMODE= on the command line or Select Existing Test
Mode from the graphical interface) and rerun.
If you expect the specified pin to be controllable in this test mode and are unable
to determine the reason why it is not, contact customer support (see
ERROR (TLH-043): [Internal] test_function_name Pin name is not contacted by

the tester in test mode testmode_name.
EXPLANATION:
The indicated pin is a test function flagged pin (Output Inhibit or Linehold), which is
erroneously not assigned to a tester pin by Encounter Test and thus cannot be lineheld.
This is an indication of a Encounter Test program error.
USER RESPONSE:
assistance.

INFO (TLH-044): Pin|Net|Block|PPI name on line line_number is a Linehold

fixed value latch held opposite to the flagged value.
EXPLANATION:
The indicated Linehold (LH) fixed value latch is held to a value opposite the initial value
determined from the mode initialization sequence.
USER RESPONSE:
INFO (TLH-045): The following correlated latch lineholds have been added on behalf of
line_number.
EXPLANATION:
Following this message is a list of the lineholds which were added due to their correlation
to a Linehold (LH) fixed value latch contained on the indicated line. The mode
initialization sequence assumes a non-skewed scan operation, thus by implication the list
of lineholds following this message are included in the linehold set.
USER RESPONSE:
INFO (TLH-046): statement_type value of value was specified for cut point
Pin|Net|Block|PPI name at line line_number. It has been translated to a
statement_type on Pseudo Primary Input PPI name to a value of value.
EXPLANATION:
A cut point associated with the indicated Pseudo Primary Input (PPI) was specified in a
Hold statement. A Hold on this cut point implies a corresponding Hold on all other cut
point(s) associated with the PPI. By convention, the Hold on the cut point is translated to
the associated PPI, with all associated cut point(s) implicitly receiving values in
accordance with their relation to the PPI.
USER RESPONSE:
This message may point to an error if a linehold conflict is detected with any of the
associated cut points, resulting in the appearance of message TLH-020.

is a Pseudo Primary Input (PPI) and cannot be defaulted.
EXPLANATION:

A Pseudo Primary Input (PPI) may not be defaulted to a value. Since the value(s) on all
cut point(s) associated with a PPI are supplied by
a user-supplied sequence, a definite value (if any) must exist. Note that holding of PPIs
is permitted.
USER RESPONSE:
Ensure that you specified the correct name for the default statement on the
indicated line in the linehold file.
If you intended to hold the PPI instead of default it, correct the statement on the
indicated line in the linehold file.

is ambiguous.
EXPLANATION:
The name specified on the indicated line number is ambiguous (not instance-specific) for
this model.
USER RESPONSE:
Modify the indicated name so it identifies a specific instance of an object in the model.
WARNING (TLH-049): [Severe] Linehold linehold_entity = linehold_value

in test sequence sequence_name1, conflicts with a linehold in test sequence(s)
sequence_name2.
EXPLANATION:
In order for lineholds from multiple user sequences to be successfully combined into a
single set, no linehold conflicts can exist (that is, two or more different values specified
for the same node). In this case, the identified linehold was specified at conflicting values
in the identified user sequences.
USER RESPONSE:
If the linehold is incorrect in one of the sequences, correct the Define_Sequence
statement in the imported source, and re-import the sequence. Otherwise, rerun the
application, not specifying one of the identified sequences in order to resolve the conflict.
WARNING (TLH-050): [Severe] Invalid linehold linehold_entity =

linehold_value in test sequence sequence_name - is not controllable or a fixed value
linehold latch in test mode testmode_name.
EXPLANATION:

Each linehold specified in a Define_Sequence user Linehold object, must either be

directly controllable in the associated test mode (i.e., not an internal node), or be a fixed
value linehold (LH) latch in that test mode. The linehold identified in this message does
not meet these requirements.
USER RESPONSE:
Correct the identified linehold by modifying the Define_Sequence source statement, then
re-import the sequence and rerun the failing application.
TLH-051 through TLH-999

WARNING (TLH-051): User sequence name sequence_name was not found in the
TBDseq file for test mode testmode_name.
EXPLANATION:
The identified sequence was not found in the TBDseq file for the test mode. The name
is ignored.
USER RESPONSE:
If the name was incorrectly specified at application runtime, correct the name and rerun.
Otherwise, ensure the test mode name was correctly specified.
WARNING (TLH-052): Linehold linehold_entity = linehold_value in test

sequence sequence_name overrides a linehold from either the test mode definition or a
user linehold file.
EXPLANATION:
The identified linehold conflicts with a linehold specified via an alternate source (i.e., user
linehold file, test mode definition, or logic model source). The value specified in the
identified user sequence will be used.
USER RESPONSE:
If the linehold from the identified user sequence is acceptable, no action is required.
Otherwise, rerun omitting the identified user sequence.
INFO (TLH-053): Extracting statement_type from user sequences.

EXPLANATION:
Indicates linehold information of the indicated type is being extracted from user
sequences.

USER RESPONSE:
INFO (TLH-054): Extracted lineholds successfully from user sequences:

sequence_names.
EXPLANATION:
Indicates linehold information was successfully extracted from the identified user
sequences.
USER RESPONSE:
WARNING (TLH-055): [Severe] Pin|PPI name on line line_number is a GO Signal

and cannot be held or defaulted out of stability.
EXPLANATION:
You may not specify a linehold on a GO Signal (Primary Input or Pseudo Primary Input),
if the specified value differs from the stability value for the GO Signal. Setting of GO signals
to non-stability values is controlled strictly by On-Product Clock Generation
USER RESPONSE:
Perform the following if you did not intend to linehold a GO Signal away from stability:
Ensure the specified object (Pin, Net, Block, or PPI) and name on the indicated line
is accurate. If not, correct the indicated line in the linehold file and rerun this
application.
Ensure you specified test mode name. is correct If not, correct the test mode
specification (TESTMODE= on the command line; Window-Analysis Content or the
application form on the GUI) and rerun.
WARNING (TLH-056): [Severe] Pin|Net|Block on line line_number is an OPCG

control register latch and cannot be held.
EXPLANATION:
You may not specify a hold on an On-Product Clock Generation (OPCG) control register
latch. The loading of OPCG control register latches is strictly controlled by the
Load_OPCG_Controls event contained in a setup sequence.
USER RESPONSE:

Ensure the correct name is specified for the latch on the indicated line in the linehold
file.
If you did not expect the latch to be an OPCG control register latch, review your test
WARNING (TLH-057): [Severe] Pin|PPI on line line_number is identified as an

oscillator, but this pin does not have a +/-OSC test function attribute. Remove this linehold
statment or add the OSC test function to the pin and rebuild the testmode.
EXPLANATION:
A pin must have the +/-OSC test function attribute to be connected to a continuously
running oscillator. The OSCILLATE statement in the linehold file is meaningless when
applied to a pin that is not an oscillator.
USER RESPONSE:
Ensure the correct pin was specified. If not, edit the linehold file and rerun. If this is the
correct pin, rebuild the testmode after editing the mode definition file or the netlist to
include the +/-OSC test function attribute on this pin.
WARNING (TLH-058): An OSCILLATE statment for Pin|PPI on line line_number

specifies a pulsespercycle count of pulsespercycle but this value is not supported
by the Tester Description Rule (TDR). The override is accepted, but the tests may not work.
Ensure this value can be supported, or change the linehold file and rerun.
EXPLANATION:
The TDR is intended to give the limitations of the test system where the vectors will be
applied. The TDR that was specified when the testmode was built indicates that this
pulsespercycle ratio of oscillator cycles per tester cycle is not supported.
USER RESPONSE:
Ensure the test system can accommodate the pulsespercycle ratio specifed in the
override. If it can, then ignore this warning message. Consider obtaining a more accurate
TDR for building testmodes in the future. If the test system cannot accommodate the
specifed pulsespercycle, edit the linehold file to specify an acceptable value, and
rerun.
WARNING (TLH-059): An OSCILLATE statment for correlated Pin|PPI on line

line_number. has been translated to representative rep_name.
EXPLANATION:
A non-representative member of a correlated group was used in an OSCILALTE
statement. By convention, all control pins are specified by reference to the representative

member, with all non-representative members implicitly receiving values in accordance

with their relation to the representative.
USER RESPONSE:
Ensure the correct pin was specified. Avoid this message in the future by using the
representative pin.
INFO (TLH-060): The following oscillation overrides are currently in effect:

EXPLANATION:
Following this message is a list of the oscillation overrides from the specified linehold file
in effect for the run. The list is determined from the OSCILLATE statements in that file.
USER RESPONSE:
No response is required if the list is consistent with your expectations. Otherwise, stop
the run and alter the OSCILLATE statements in the linehold file to ensure the oscillation
overrides match expectations prior to rerunning the application.
WARNING (TLH-061): [Severe] Pin name on line line_number has an invalid (not
greater than 0) value for UP.
EXPLANATION:
The UP value for an OSCILLATE statement must be greater than 0.
USER RESPONSE:
Ensure that the specification on the indicated line of the linehold file is accurate and rerun
if necessary.
ERROR (TLH-062): Scan Register lineholds cannot be solved for scan cycle cycle which
has count flops lineheld.
EXPLANATION:
For a testmode with XOR decompression, any scan register lineholds must be solvable
solvable back to the SI pins so they can be put into the Compressed Input Stream event.
USER RESPONSE:
Check your scan register lineholds for this scan cycle. If too many flops are required at
value, they may not all be solvable.
INFO (TLH-063): Extracting node_type from user sequence sequence_name.

EXPLANATION:

Update the lineholds with the stim nodes and values found in the input
Sequence_Definition passed in.
USER RESPONSE:
INFO (TLH-064): node_type node_name was not added to the linehold data for reason
reason.
EXPLANATION:
Update the lineholds with the stim node and value found in the stim events of the input
Sequence_Definition was not possible.
USER RESPONSE:
ERROR (TLH-065): Scan Register lineholds cannot be solved as a collection.

EXPLANATION :
For a testmode with Sequential decompression, any scan register lineholds must be
solvable back to the SI pins so they can be put into the Compressed Input Stream event.
USER RESPONSE:
Check your scan register lineholds. If too many flops are required at value, they may not
all be solvable.
ERROR (TLH-999): [Internal] An unexpected condition occurred in the Encounter Test

linehold processing code. Contact Cadence Customer Support to report this error and give
them the following information:
An error occurred on line line_number of source file file_name variable_text:

EXPLANATION:
This error indicates a program error. Communicate the information produced in the
message text to Cadence Customer Support.
USER RESPONSE:
using your normal process; sourcelink, email, or directly call to the customer support line,
more quickly fix the problem.



48
TLM - Logic Model Messages
TLM-001 through TLM-050 on page 1489

TLM-001 through TLM-050

ERROR (TLM-001): Required parameter WORKDIR was not specified. Encounter Test
Circuit Import Flat Model Build exits.
EXPLANATION:
WORKDIR is a required parameter to identify the design to process.
USER RESPONSE:
Specify WORKDIR and rerun. Refer to "build_model" in the Encounter Test:
Reference: Commands for additional information.
ERROR (TLM-003): Unable to resolve input design hierModel file. Encounter

Test Circuit Import Flat Model Build exits.
EXPLANATION:
Encounter Test has failed to resolve the input design hierModel filename using
WORKDIR. See previous TFW message(s).
USER RESPONSE:
Correct problem identified by TFW message(s) or contact customer support (see
ERROR (TLM-004): Unable to obtain read lock access of input design hierModel
file. Encounter Test Circuit Import Flat Model Build exits.

EXPLANATION:
Encounter Test has failed to obtain read lock access of input design hierModel. See
previous TFW message(s). This could occur if another user or process has obtained
write locks against the design, such as would occur during commit of test data or
removing the design.
USER RESPONSE:
ERROR (TLM-005): Unable to open input design hierModel file. Encounter Test
EXPLANATION:
Encounter Test has failed to memory map the input design hierModel file. See previous
TSU message(s).
USER RESPONSE:
Correct problem identified by TSU message(s) or contact customer support (see
ERROR (TLM-006): Top level cell cellname has no contents. Encounter Test Circuit
Import Flat Model Build exits.
EXPLANATION:
Top level cell description in hierModel does not define any ports and/or any internal nets
to create the flatModel.
USER RESPONSE:
Check previous messages from Encounter Test Circuit Import during creation of the
hierModel. The normal cause for this error is the creation of a hierModel containing only
an interface (DEF) and no content descriptions. Verify the Search Order(s) specified and
the cell name used as input to Circuit Import are correct.
ERROR (TLM-007): Unable to allocate table workspace for n bytes. Encounter Test
EXPLANATION:
Encounter Test has failed to allocate table for the specified number of bytes. See
previous TFW message(s). The most likely cause is insufficient swap space.
USER RESPONSE:

Ensure there is sufficient swap space available on the system being used and/or user
profile allows for the allocation of storage required.
ERROR (TLM-008): Unable to re-allocate table (number of table entries)

workspace for n bytes for net netname of cell cellname. Encounter Test Circuit Import Flat
Model Build exits.
EXPLANATION:
Encounter Test has failed to re-allocate table to new size. See previous TFW
message(s).
USER RESPONSE:
ERROR (TLM-009): Unable to obtain write lock access for output flatModel file.
Encounter Test Circuit Import Flat Model Build exits.
EXPLANATION:
Encounter Test has failed to obtain write lock access to create the output flatModel. See
USER RESPONSE:
INFO (TLM-010): This function is supported for Encounter Test development use only. To
obtain information about the Encounter Test model, use report_model_statistics or
report_test_structures.
EXPLANATION:
This function dumps out some programmer debug information about the Encounter Test
model. The user-readable equivalent of this information can be obtained from
report_model_statistics (View Circuit Statistics).
USER RESPONSE:
Use report_model_statistics (View Circuit Statistics) to obtain information about
the model.

ERROR (TLM-012): Unable to allocate required workspace for n megabytes. Encounter

EXPLANATION:
Encounter Test has failed to allocate workspace. See previous TFW message(s).
Encounter Test Circuit Import Flat Model Build analyzes the hierModel and estimates the
amount of storage required to create the flatModel. This amount is currently not
available.
USER RESPONSE:
ERROR (TLM-013): [Internal] PROGRAM ERROR: workspace overflow processing cell

cellname in routine name. TLMSEGSIZE=initial allocation size. As a
temporary workaround, rerun build_flatmodel specifying TLMSEGSIZE=increment
of allocation size on the command line, incrementing TLMSEGSIZE by 25% until
build_flatmodel is successful. Contact customer support so this design may be
analyzed. Build Model Build exits.
EXPLANATION:
A workspace table overflow has occurred. Pre-allocation algorithm not sufficient for this
design. This design must be analyzed to modify allocation algorithm.
USER RESPONSE:
Run build_flatmodel specifying TLMSEGSIZE as a temporary workaround to get a
successful model build. TLMSEGSIZE can be exported as an environment variable or
specified on the build_flatmodel command line.
WARNING (TLM-014): Unable to allocate estimated workspace of n megabytes. Encounter

Test Circuit Import will try to continue with a smaller amount of storage.
EXPLANATION:
Encounter Test has failed to allocate the amount of workspace estimated to build the
flatModel. See previous TFW message(s). Encounter Test Circuit Import Flat Model
Build analyzes the hierModel and estimates the amount of storage required to create the
flatModel. This amount is currently not available. Encounter Test Circuit Import will
reduce the estimate by 20% and again.
If the amount of storage finally allocated is too low, Circuit Import Flat Model Build will
either recognize the overflow and terminate, or it may core.

USER RESPONSE:
If Encounter Test Circuit Import completes successfully, no action is required. Otherwise,
ensure there is sufficient swap space available on the system being used and/or user
profile allows for the allocation of storage required. If the design is in excess of 5M gates,
a 64 bit system may be required.
INFO (TLM-015): Not enough memory available for normal flatModel creation. Processing
continues. A temporary flatModel file will be used to save memory.
EXPLANATION:
Encounter Test was unable to get enough memory to build the flatModel file in-core. It
will attempt to continue in a memory conservation mode where it writes information
normally kept in memory out to disk. Be aware that a large amount of DASD will be
required for this to work. However, the temporary flatModel will be deleted before the final
flatModel file is written.
USER RESPONSE:
No response required. This message is purely informational. If there is still not enough
memory or DASD to build the model, additional (terminating level) messages will be
issued.
ERROR (TLM-016): Model access code and model file levels are incompatible. Model files
built with newer level of code than is currently being run. Rebuild Model files or run level of
code that was used to build model files.
EXPLANATION:
The flat model being loaded was created with a newer level of code than is currently
being run. The file is not backward compatible.
USER RESPONSE:
Re-run Encounter Test Model Import or run the level of Encounter Test used to create the
Encounter Test Model.
ERROR (TLM-017): Unable to open | decrypt protected hierModel. Password

authorization failed. Build Model exits.
EXPLANATION:
Build Flat Model was unable to open or decrypt a password protected hierModel file due
to password authorization failures.
USER RESPONSE:

If running build_model, this should not be occurring and customer support should be
contacted (see Contacting Customer Service on page 23).
If running build_flatmodel, a valid authorization password must be specified.
INFO (TLM-018): Controllable registers exist that are loaded internally (from a PRPG with
or without a spreader network), but the test mode data for test mode test mode name is
at a level that is older than the current level of Encounter Test being run and Test Structure
Verification was not performed.
Either run verify_test_structures in the old release or rebuild the test mode in this new
release. This ensures correct migration of the older releases test structure information for use
with this new release.
Any release prior to 3.1.4 qualifies as an old release.

EXPLANATION:
One or more controllable registers have been defined as being loaded via PRPG (that is,
LBIST) but the test mode data does not contain information regarding load configuration
and observe points because it was built in an older release. Information from an older
release is automatically migrated to the current release as long as Test Structure
Verification was performed in the old release of the software.
USER RESPONSE:
Either verify the test structures using the older release (pre-ET3.1.4) of the software or
rebuild this test mode using the current release to ensure that the test structure
information is being correctly migrated.
ERROR (TLM-019): Unable to process flatModel name. Model was created in a prior
version using the reducemodel keyword. The reducemodel keyword is obsolete for this
version. Rebuild the logic model in current version or process the design with version 6.2 or
older.
EXPLANATION:
The reducemodel keyword is obsolete in version 7.2.
USER RESPONSE:
Reprocess the design starting with build_model using the current version of
Encounter Test or process the design with version 6.2 or older.
ERROR (TLM-020): Unable to delete flatModel filename before writing new flatModel.
error number n from EDAMfdel: explanation of error number value. Encounter

EXPLANATION:
Encounter Test was unable to delete previous flatModel file. See previous EDAM
message(s).
USER RESPONSE:
Correct problem identified by EDAM messages(s) and error number value or contact
ERROR (TLM-021): Unable to allocate flatModel filename. Error number n from

EDAMfopn: explanation of error number value. Build Model exits.
EXPLANATION:
Encounter Test was unable to allocate flatModel file. See previous EDAM message(s).
USER RESPONSE:
Correct problem identified by EDAM messages(s) and error number value or contact
ERROR (TLM-022): Unable to open EDAM SA storage area number for writing
flatModel. Error number n from EDAMsopn: explanation of error number value.
Encounter Test Circuit Import Flat Model Build exits.
EXPLANATION:
Encounter Test was unable to open storage area for writing flatModel file.
USER RESPONSE:
Correct problem identified by EDAM message(s) and error number value or contact
Storage area number is debug data that may be needed for analysis of problem by
customer support.
ERROR (TLM-023): Unable to write table name to flatModel. Error number n from
EDAMsput: explanation of error number value. Encounter Test Circuit Import
Flat Model Build exits.
EXPLANATION:
Encounter Test failed to write table to flatModel file.
USER RESPONSE:

ERROR (TLM-024): Unable to close flatModel. Error number n from EDAMfcls:

explanation of error number value. Encounter Test Circuit Import Flat Model
Build exits.
EXPLANATION:
EDAM error trying to close flatModel file.
USER RESPONSE:
Correct problem identified by EDAM messages and error number value or contact
INFO (TLM-025): Unable to terminate EDAM utility. Error number number from EDAMterm:
explanation of error number value. Encounter Test Circuit Import Flat Model
Build continues.
EXPLANATION:
Error occurred when trying to terminate use of EDAM utility.
USER RESPONSE:
Unless a symptomatic error occurs, Encounter Test Circuit Flat Model Build will complete
successfully.
ERROR (TLM-026): Unable to successfully load flatModel | hierModel |

modeInfo | TSItsvInterfaceFile | pipelineInfo file.
additional information about what caused the error
Model access terminating.

EXPLANATION:
Customer Support.
USER RESPONSE:
Verify the file exists.
Check file permissions and ensure the machine being used has enough memory. If the
file exists and machine has enough memory perform the following:
If the hierModel/flatModel is missing or tables could not be loaded from the file,
rebuild the model using build_model.

If only the flatModel has a problem and not the hierModel, build_flatmodel
can be run instead of build_model.
If the modeInfo or TSItsvInterfaceFile or pipelineInfo file is missing or
tables could not be loaded from the file, rebuild the test mode using
build_testmode.
Otherwise, contact customer support (see Contacting Customer Service on page 23)
for assistance.
ERROR (TLM-027): Unable to successfully load flatModel | hierModel |

modeInfo | TSItsvInterfaceFile | pipelineInfo file.
Errno/return code error code | return code returned from program name.
Model access terminating.

EXPLANATION:
Customer Support.
USER RESPONSE:
Verify the file exists.
Check file permissions and ensure the machine being used has enough memory. If the
file exists and machine has enough memory perform the following:
If the hierModel/flatModel is missing or tables could not be loaded from the file,
rebuild the model using build_model.
If only the flatModel has a problem and not the hierModel, build_flatmodel
can be run instead of build_model.
If the modeInfo or TSItsvInterfaceFile or pipelineInfo file is missing or
tables could not be loaded from the file, rebuild the test mode using
build_testmode.
Otherwise, contact customer support (see Contacting Customer Service on page 23)
for assistance.
ERROR (TLM-028): Insufficient storage to allocate table name table. Failed trying to
allocate number of bytes bytes. Model access terminating.
EXPLANATION:

A model access routine was unable to load the table shown in the message. The calling
application will determine if this is a terminating condition. The information regarding the
table and number of bytes being allocated is mainly for use by Customer Support.
USER RESPONSE:
Ensure the machine being used has enough memory to run this design. If sufficient
memory is available, contact customer support (see Contacting Customer Service on
WARNING (TLM-029): [Severe] Unable to open netvoltagefile filename. Errno is

errno. Check perror message printed to stderr. Build Flat Model continues and uses
the default set of netnames to identify sources of Power (vdd, and so on) and Ground (gnd,
and so on).
EXPLANATION:
Build Flat Model was not able to open the referenced net voltage file. The run continues
and uses the default set of net names for identifying sources of Power (vdd, and so on)
and Ground (gnd, and so on).
USER RESPONSE:
Verify the contents of the netvoltagefile and rerun. Refer to Sourceless Nets in the
WARNING (TLM-030): [Severe] No nets identified processing netvoltagefile

filename. Build Flat Model continues and uses the default set of netnames to identify
sources of Power (vdd, and so on) and Ground (gnd, and so on).
EXPLANATION:
Build Flat Model processing of the net voltage file produced no results.The run continues
and uses the default set of net names for identifying sources of Power (vdd, and so on)
and Ground (gnd, and so on).
USER RESPONSE:
Verify the contents of the netvoltagefile and rerun. Refer to Sourceless Nets in the
WARNING (TLM-031): [Severe] Syntax error on line linenumber in netvoltagefile

filename. Last token: last_token_found. Build Flat Model ignores this data and
continues syntax checking looking for the next valid token.
optional additional info

EXPLANATION:

Build Flat Model has found invalid syntax on the identified line. Check
last_token_found to help identify the error. Parsing of netvoltagefile
continues.
USER RESPONSE:
Ensure this error is corrected. Verify the contents of the netvoltagefile and rerun.
Refer to Sourceless Nets in the Encounter Test: Guide 1: Models for additional
information.
INFO (TLM-032): Parsing voltagefile filename. Duplicate specification of ground |

power net netname ignored. Parsing continues.
EXPLANATION:
Build Flat Model has found multiple specifications of the same power or ground net.
Parsing of netvoltagefile ignores this data and continues.
USER RESPONSE:
Remove duplicate specification(s) to eliminate this message.
WARNING (TLM-033): [Severe] Parsing define_ground_nets |

define_power_nets for netvoltagefile filename, line lineumber. Net
netname was previously specified in a define_power_nets |
define_ground_nets statement. Net cannot be both a source of power and ground. This
specification is discarded. Parsing continues.
EXPLANATION:
Build Flat Model has found the same net specified as both a source of power and ground.
Parsing of netvoltagefile ignores this specification of the net.
USER RESPONSE:
Determine whether the default action is acceptable or correct data and rerun.
WARNING (TLM-034): [Severe] Net netname, by default, is recognized as a source of

power | ground. Netvoltage file filename has attempted to define this net as a source
of ground | power. Net cannot be both a source of power and ground. Net is processed
as a source of power | ground only.
EXPLANATION:
The specified netvoltage file has defined overrides for either power or ground, but not
both. The identified net name is considered an attempt to define the net as both a source
of power and ground. This is not allowed. the net is processed using its system default
behavior.

USER RESPONSE:
Determine whether the default action is acceptable or correct data and rerun.
ERROR (TLM-035): PROGRAM LIMITATION: net netname of cell cellname, when

flattened, has more than 65535 sinks. Encounter Test Circuit Import.
Flat Model Build exits. Contact customer support (see Contacting Customer Service on
page 23).
EXPLANATION:
Fanout of net is too large to be processed.
USER RESPONSE:
Have design analyzed by customer support and/or modify design by breaking net into
multiple logical nets with buffer(s).

flattened, has more than supported number of sources and PIs. Encounter Test Circuit
Import Flat Model Build exits. Contact customer support (see Contacting Customer Service
on page 23).
EXPLANATION:
Too many sources and PIs are being dotted together.
USER RESPONSE:

flattened, has more than supported number of transistor sinks. Encounter Test Circuit Import
Flat Model Build exits. Contact customer support (see Contacting Customer Service on
page 23).
EXPLANATION:
Too many transistor sinks being fed by a single three-state primitive.
USER RESPONSE:

ERROR (TLM-038): Error encountered processing comment beginning on line

line_number in netvoltage file filename. End-of-file reached before end of comment
syntax '*/'. Processing terminates.
EXPLANATION:
While parsing the netvoltage file, build_model encountered the begin comment syntax
'/*', but end-of-file was encountered before the end of comment syntax '*/'. This is a
terminating condition.
USER RESPONSE:
Correct the file and rerun Build Model.
ERROR (TLM-050): PROGRAM LIMITATION: contents for cell cellname exceeds model
hierarchy limitation of n levels. Encounter Test Circuit Import Flat Model Build terminates.
Each TLM-051 message that follows represents the next higher cell walking back up the
hierarchy that produced this message. Contact customer support (see Contacting Customer
EXPLANATION:
There are too many hierarchy levels defined for this design. The cellname printed is the
lowest level cell in the hierarchy whose contents exceeded the number of levels
supported by Encounter Test. A corresponding set of TLM-051 messages will be printed
identifying each cell walking back up the hierarchy to the top level cell.
USER RESPONSE:
Have design analyzed by customer support and/or modify design by flattening/removing
levels of hierarchy.

INFO (TLM-051): Cell cellname.
EXPLANATION:
Each TLM-051 message represents the next higher cell walking back up the cell
hierarchy just processed that produced the TLM-050 message.
USER RESPONSE:
This message is provided as debug data.

ERROR (TLM-060): Required parameter WORKDIR was not specified. Encounter Test Edit
ROM Contents terminates.
EXPLANATION:
USER RESPONSE:
Specify WORKDIR and rerun. Refer to "build_model" in the Encounter Test:
ERROR (TLM-062): Required parameter ROMPATH was not specified. Encounter Test Edit
ROM Contents terminates.
EXPLANATION:
ROMPATH is a required parameter to identify the path for accessing ROM personality
(contents) data.
USER RESPONSE:
Specify ROMPATH and rerun. Refer to "build_model" in the Encounter Test:
ERROR (TLM-063): Unable to resolve flatModel file. Encounter Test Edit ROM
Contents terminates.
EXPLANATION:
Encounter Test has failed to resolve the input design flatModel filename using
USER RESPONSE:
ERROR (TLM-064): Unable to obtain write lock access for flatModel file. Encounter
Test Edit ROM Contents terminates.
EXPLANATION:
Encounter Test has failed to obtain write lock access to update the flatModel. See
USER RESPONSE:


ERROR (TLM-065): Unable to access input design hierModel,

hierAttributes or flatModel. See previous message(s). Encounter Test Edit ROM
Contents terminates.
EXPLANATION:
Encounter Test has failed to access either the hierModel, hierAttributes, or flatModel. See
previous message(s).
USER RESPONSE:
Correct problem identified by message(s) or contact customer support (see Contacting
ERROR (TLM-066): Unable to malloc space required. ROM updates have not
occurred. Encounter Test Edit ROM Contents terminates.
EXPLANATION:
Encounter Test is unable to malloc the space required for processing. ROM updates have
not occurred.
USER RESPONSE:
assistance.
ERROR (TLM-067): Unable to write ROM Contents input ROM Contents file to
input design flatModel file. Reason for failure. ROM updates, if any,
have been discarded. Encounter Test Edit ROM Contents terminates.
EXPLANATION:
Encounter Test has failed to write data to the design flatModel. ROM updates have not
occurred.
USER RESPONSE:
assistance.
ERROR (TLM-068): Unable to close input design flatModel file. ROM updates
have not occurred. Reason for failure. Encounter Test Edit ROM Contents
terminates.
EXPLANATION:

Encounter Test has failed to close the input design flatModel. ROM updates have not
occurred.
USER RESPONSE:
assistance.
ERROR (TLM-070): [Internal] TLMlevelize must be called prior to Failing Method.

EXPLANATION:
A Encounter Test application has attempted to access the flatModel levelized design
prior to execution of the levelization.
USER RESPONSE:
assistance.
WARNING (TLM-100): [Severe] Invalid dotting function (DFN) attribute value specified
for pin pinname of cell cellname. Property is ignored.
EXPLANATION:
Invalid DFN attribute encountered. Since dotting function (DFN) attribute was specified
for the pin, it is assumed to be required for the pin. Property is ignored to allow creation
of the flatModel.
USER RESPONSE:
Respecify attribute with valid value (AND, OR, T) and rerun. THIS ERROR SHOULD BE
CORRECTED BEFORE CONTINUING.
WARNING (TLM-101): [Severe] Invalid dotting function (DFN) attribute value specified
for pin pinname on block blockname of cell cellname. Property is ignored.
EXPLANATION:
Invalid DFN attribute encountered. Since dotting function (DFN) attribute was specified
for the pin, it is assumed to be required for the pin. Property is ignored to allow creation
of the flatModel.
USER RESPONSE:
Respecify attribute with valid value (AND, OR, T) and rerun. THIS ERROR SHOULD BE

WARNING (TLM-102): Invalid dotting function (DFN) attribute value specified for pin
pinname on three-state block blockname of cell cellname.
Property is ignored. DFN of T is used instead.
EXPLANATION:
Invalid DFN attribute specified for a three-state primitive. Specified DFN attribute is
ignored, T is default dotting function for all three-state primitives.
USER RESPONSE:
Remove DFN attribute to remove this message from subsequent Circuit Imports.
Encounter Test only supports a dotting function of T for three-state primitives.
WARNING (TLM-105): Multi-source net netname of cell cellname has no dotting

function(DFN) properties specified. Input parameter defaultDFN=value is used to model the
net.
EXPLANATION:
Dotted net encountered, but no DFN properties were specified to tell Encounter Test how
to logically model the physical dot.
USER RESPONSE:
If defaultDFN value used is not the proper logical function to model the dotted net, add a
DFN attribute to a primitive output pin or cell output pin somewhere in the hierarchy for
the net in question. Adding a DFN attribute will remove this message during subsequent
Circuit Imports. THIS ERROR MAY NEED TO BE CORRECTED BEFORE
CONTINUING.
WARNING (TLM-106): Multi-source net netname of cell cellname has a resolved

dotting function (DFN) of NO indicating dotting is not allowed. A three-state dot is used to
model the net.
EXPLANATION:
Dotted net encountered, but at least one primitive output pin or cell output pin has a DFN
attribute of NO. This indicates the pin should not be in a dotted net. A three-state dot is
used to model the net to allow creation of the flatModel.
USER RESPONSE:
Verify correct usage of all cells throughout the hierarchy for the net identified. Either DFN
attribute has been incorrectly specified, or design usage is incorrect. THIS ERROR
SHOULD BE CORRECTED BEFORE CONTINUING.

WARNING (TLM-107): Multi-source net netname of cell cellname has conflicting dotting
function (DFN) properties specified. A three-state dot is used to model the net.
EXPLANATION:
Dotted net encountered, but incompatible DFN values seen between primitive output
pins and/or cell output pins. A three-state dot is used to allow creation of the flatModel.
USER RESPONSE:
WARNING (TLM-108): Bidi primary output net netname of cell cellname has no dotting
function (DFN) properties specified. Input parameter defaultDFN=dfn value is used to
model the net.
EXPLANATION:
Bidi primary output nets are modeled with a dot to represent the dotting of the bidi pin
with the internal sources in the net when the bidi pin acts as an input. Neither a primitive
output pin or cell output pin had a DFN attribute specified. Input parameter defaultDFN
value is used to model the dot.
USER RESPONSE:
If defaultDFN value is not the proper logical function to model the net, add a DFN attribute
to a primitive output pin or cell output pin somewhere in the hierarchy for the net in
question. Adding a DFN attribute will remove this message during subsequent Circuit
Imports. THIS ERROR SHOULD BE CORRECTED BEFORE CONTINUING.
WARNING (TLM-109): Bidi primary output net netname of cell cellname has a resolved
dotting function (DFN) of NO indicating dotting is not allowed. DFN of T is used to model net.
EXPLANATION:
with the internal sources in the net when the bidi pin acts as an input. At least one
primitive output pin or cell output pin has a DFN attribute of NO. This indicates the pin
should not be in a dotted net. A three-state dot is used to model the net to allow creation
of the flatModel.
USER RESPONSE:

WARNING (TLM-110): Bidi primary output net netname of cell cellname has conflicting
dotting function (DFN) properties specified. DFN of T is used to model net.
EXPLANATION:
with the internal sources in the net when the bidi pin acts as an input. Incompatible DFN
values seen between primitive output pins and/or cell output pins. A three-state dot is
used to model the net to allow creation of the flatModel.
USER RESPONSE:
WARNING (TLM-113): [Severe] Invalid TIE attribute value specified for pin pinname of
cell cellname. Property is ignored.
EXPLANATION:
Invalid TIE attribute encountered. Since TIE attribute was specified for the pin, it is
assumed to be required for the pin. Property is ignored to allow creation of the flatModel.
USER RESPONSE:
Respecify attribute with valid value(0, 1, X) and rerun. THIS ERROR SHOULD BE
WARNING (TLM-114): [Severe] Invalid TIE attribute value specified for pin pinname on
block blockname of cell cellname. Property is ignored.
EXPLANATION:
Invalid TIE attribute encountered. Since TIE attribute was specified for the pin, it is
USER RESPONSE:
Respecify attribute with valid value(0, 1, X) and rerun. THIS ERROR SHOULD BE
WARNING (TLM-115): Conflicting TIE properties between pin pinname on block

blockname of cell cellname1 and Interface (DEF) pin of cell cellname2. TIEX
generated to drive pin.
EXPLANATION:

Input usage pin does not have a parent net connected to it. Therefore, pin must be tied
off. Checking of TIE properties has revealed a conflict between usage pin and interface
(DEF) pin. Because of the conflicting TIE properties, the pin is tied to X.
USER RESPONSE:
Correct conflict so pin will be tied to appropriate value. THIS ERROR SHOULD BE
WARNING (TLM-116): Conflicting TIE properties between pin pinname on block

blockname of cell cellname and a TIE attribute that has propagated up through the
hierarchy. TIEX generated to drive pin.
EXPLANATION:
Input usage pin does not have a parent net connected to it. Therefore, pin must be tied
off. Checking of TIE properties has revealed a conflict. Because of the conflicting TIE
properties, the pin is tied to X.
USER RESPONSE:
Correct conflict so pin will be tied to appropriate value. THIS ERROR SHOULD BE
WARNING (TLM-117): TIDN|TIUP|TIEX is generated for sourceless net netname of

cell cellname based on input keyword defaultTIE=default TIE value.
EXPLANATION:
The net is sourceless and therefore must be tied to a logic value. build_model did not
find any TIE properties for this net, did not match the net name to either the default set
(gnd,vdd,...) or to a net name from an input netvoltagefile, to know which logic
value the net should be tied to. Input parameter defaultTIE is used to model the net.
USER RESPONSE:
If this default action is not desired, refer to Sourceless Nets in the Encounter Test:
Guide 1: Models to determine how to correct this situation.
THIS ERROR MAY NEED TO BE CORRECTED BEFORE CONTINUING.
WARNING (TLM-118): Conflicting TIE properties were found for sourceless net netname
of cell cellname. TIEX generated to drive net.
EXPLANATION:

Net is sourceless and therefore needs to be tied to a logic value. Conflicting TIE
properties were found when checking primitive input pins and cell input pins along the
net throughout the hierarchy.
USER RESPONSE:
Specify a TIE attribute on a primitive input pin, cell input pin, or usage pin in the net if a
TIEX is not desired. THIS ERROR SHOULD BE CORRECTED BEFORE CONTINUING.
WARNING (TLM-119): Pin pinname on block blockname of cell cellname has no net
and no TIE properties were found. TIE{0,1,X} generated to drive pin based on input
parameter defaultTIE=default TIE value.
EXPLANATION:
No net exists to drive pin.
USER RESPONSE:
If a different logic value is desired to drive pin, specify a TIE attribute and rerun. THIS
ERROR SHOULD BE CORRECTED BEFORE CONTINUING.
INFO (TLM-120): Primary Output Pin pinname of cell cellname has internal net
netname which is sourceless. A TIUP, TIDN, or TIEX will be generated if parent net(s)
throughout the hierarchy are also sourceless.
EXPLANATION:
There are no internal sources driving this PO net of the cell. Since creation of the
flatModel is from the bottom up, generation of a TIE block to drive the net is deferred until
processing any, and all, parent nets.
USER RESPONSE:
If analysis shows that this pin of the cell does not contribute to its parent net, no action
is required. If a TIUP, TIDN, or TIEX is required to drive this PO pin of the cell, add the
respective primitive in the design source for this cell. THIS CONDITION MAY NEED TO
BE CORRECTED BEFORE CONTINUING.
INFO (TLM-121): Primary Output Pin pinname of cell cellname has no internal net and
is therefore sourceless. A TIUP, TIDN, or TIEX will be generated if parent net(s) throughout
the hierarchy are also sourceless.
EXPLANATION:
There are no internal sources driving this PO of the cell. Since creation of the flatModel
is from the bottom up, generation of a TIE block to drive the net is deferred until
processing any, and all, parent nets.

USER RESPONSE:
If analysis shows that this pin of the cell does not contribute to its parent net, no action
is required. If a TIUP, TIDN, or TIEX is required to drive this PO pin of the cell, add the
respective primitive in the design source for this cell. THIS CONDITION MAY NEED TO
BE CORRECTED BEFORE CONTINUING.
INFO (TLM-122): number NFETs/PFETs have both their source and drain connected to the
same net. They have been removed from the flat model.
EXPLANATION:
NFETs/PFETs where both the source and drain are connected to the same net do not
affect the logical function of the design. In order to produce a correct model, they are
being removed from the model so they will not appear as a source on the net.
USER RESPONSE:
No action is required unless you want to override this function and keep the transistors
in your logic model. However, doing so may create unwanted X sources and three-state
DOT blocks. In order to override this function, export TLMKEEPTRANSISTORS=v
(where v is any value) and rerun Encounter Test Circuit Import.
INFO (TLM-123): number NFETs/PFETs have both their source and drain tied to gnd/vdd.
They have been removed from the flat model.
EXPLANATION:
NFETs/PFETs where both the source and drain are tied to the disable value of the FET
do not affect the logical function of the design. In order to produce a correct model, they
are being removed from the model so they will not appear as a source on the net.
USER RESPONSE:
No action is required unless you want to override this function and keep the transistors
in your logic model. However, doing so may create unwanted X sources and three-state
DOT blocks. In order to override this function, export TLMKEEPTRANSISTORS=v
(where v is any value) and rerun Encounter Test Circuit Import.
WARNING (TLM-124): Invalid product termination (TERM) attribute value specified for pin
pinname of cell cellname. Property is ignored.
EXPLANATION:
Invalid TERM attribute encountered. Since a TERM attribute was specified for the pin, it
is assumed to be required for the pin. Property is ignored to allow creation of the
flatModel.

USER RESPONSE:
Respecify attribute with valid value(0,1) and rerun. THIS ERROR SHOULD BE
WARNING (TLM-125): Invalid product termination (TERM) attribute value specified for pin
pinname on block blockname of cell cellname. Property is ignored.
EXPLANATION:
Invalid TERM attribute encountered. Since a TERM attribute was specified for the pin, it
is assumed to be required for the pin. Property is ignored to allow creation of the
flatModel.
USER RESPONSE:
WARNING (TLM-128): Invalid tester termination (TTERM) attribute value specified for pin
pinname of cell cellname. Property is ignored.
EXPLANATION:
Invalid TTERM attribute encountered. Since a TTERM attribute was specified for the pin,
it is assumed to be required for the pin.
Property is ignored to allow creation of the flatModel.
USER RESPONSE:
WARNING (TLM-129): Invalid tester termination (TTERM) attribute value specified for pin
pinname on block blockname of cell cellname. Property is ignored.
EXPLANATION:
Invalid TTERM attribute encountered. Since a TTERM attribute was specified for the pin,
it is assumed to be required for the pin. Property is ignored to allow creation of the
flatModel.
USER RESPONSE:

WARNING (TLM-132): Conflicting product termination (TERM term value) and tester
termination (TTERM tterm value) properties specified for three-state block
blockname of cell cellname. TTERM attribute is ignored. TERM attribute is used.
EXPLANATION:
A three-state primitive may not have different product termination (TERM) and tester
termination (TTERM) attribute values.
USER RESPONSE:
If three-state tester termination (TTERM) attribute is required for block, remove TERM
attribute.
Important
WARNING (TLM-134): Net netname of cell cellname has conflicting product termination
(TERM) properties specified. TERM=X is used.
EXPLANATION:
A three-state net has at least one primitive input/output pin, usage input/output pin, or
cell input/output pin with a TERM attribute value of 1 and at least one with a TERM
attribute value of 0.
USER RESPONSE:
If three-state termination (TERM) attribute is required for net, either remove conflicting
value(s) or verify correct usage of all cells throughout the hierarchy for the net. THIS
ERROR SHOULD BE CORRECTED BEFORE CONTINUING.
WARNING (TLM-135): Net netname of cell cellname has conflicting tester termination
(TTERM) properties specified. TTERM=X is used.
EXPLANATION:
A three-state net has at least one primitive input/output pin, usage input/output pin, or
cell input/output pin with a TTERM attribute value of 1 and at least one with a TTERM
attribute value of 0.
USER RESPONSE:
If three-state tester termination (TTERM) attribute is required for net, either remove
conflicting value(s) or verify correct usage of all cells throughout the hierarchy for the net.

WARNING (TLM-136): Net netname of cell cellname has conflicting product termination
(TERM term value) and tester termination (TTERM tterm value) properties specified.
TTERM attribute is ignored. TERM attribute is used.
EXPLANATION:
A three-state net may not have different product termination (TERM) and tester
termination (TTERM) attribute values.
USER RESPONSE:
If three-state tester termination (TTERM) attribute is required for net, remove TERM
attribute from all primitive input/output pin(s), usage input/output pin(s), and cell input/
output pins(s) throughout the hierarchy for the net. Verify correct usage of all cells
throughout the hierarchy for the net. THIS ERROR SHOULD BE CORRECTED
BEFORE CONTINUING.
WARNING (TLM-139): PI net netname of cellname has an internal source. Verify cell
pin directions have been defined correctly.
EXPLANATION:
A net connected to cell input pin is also connected to an internal block output pin.
USER RESPONSE:
Verify correct cell contents were found from the proper Search Order during Build Model
and/or cell pin directions have been defined correctly and then rerun if necessary.
WARNING (TLM-140): Cell cellname has and/or inout output pins with no internal net.
TIEX generated for pin pinname and all similar pins.
EXPLANATION:
The referenced pin defined on interface (DEF) has no internal net connected (driving) to
it. This pin, and all others with no internal net, are assumed to be an "X" generator.
USER RESPONSE:
If the cell is to be modeled as a blackbox set of X generators, no action is required.
Otherwise, verify correct cell contents were found from the proper Search Order during
Build Model and/or cell contents have been correctly defined.
INFO (TLM-141): No net connected to pin pinname on block blockname of cell

cellname.
EXPLANATION:
Pin defined on block interface has no net connected to it in cell content description.

USER RESPONSE:
and/or cell contents have been correctly defined.
INFO (TLM-142): n primitive blocks with no output pins were discarded from the flatModel.
EXPLANATION:
A primitive block must have an output pin defined.
USER RESPONSE:
Verify correct cell contents for all primitive functions have been defined correctly. Contact
customer support (see Contacting Customer Service on page 23) for assistance, if
necessary.
WARNING (TLM-143): At least one PO of multi-PO net netname of cell cellname has
pin direction inout. Pin pinname is selected for modeling as inout, all other PO pins on the
net are modeled as output only. Pin pinname must be used for test function pin assignments
and within sequence definition files for proper processing during build_testmode.
EXPLANATION:
Only one pin in a multi-PO net is modeled as both an input and output. The referenced
pin name is the pin that must be used for specification of test function flags or when
creating user-defined sequence definitions for build_testmode.
USER RESPONSE:
Verify the correct cell contents were found from the proper Search Order during Build
Model and/or cell contents have been correctly defined. Rerun if necessary.
WARNING (TLM-144): Pin pinname of multi-PO net netname of cell cellname is

modeled as output only. Pin pinname must not be used for test function pin assignments or
within sequence definition files for proper processing during build_testmode.
EXPLANATION:
Only one pin in a multi-PO net is modeled as both an input and output. The referenced
pin name is the pin that cannot be used for specification of test function flags or when
creating user-defined sequence definitions for build_testmode.
USER RESPONSE:
Verify the correct cell contents were found from the proper Search Order during Build
Model and/or cell contents have been correctly defined. Rerun if necessary.

WARNING (TLM-145): Net netname of cell cellname has multiple sources and no sinks.
Verify cell pin directions have been correctly defined.
EXPLANATION:
A Net connected to cell input pin is also connected to an internal block output pin.
USER RESPONSE:
and/or cell pin directions have been correctly defined.
WARNING (TLM-146): Net netname of cell cellname has multiple sinks and no sources.
Verify cell pin directions have been correctly defined.
EXPLANATION:
A net connected to a cell output pin is not being driven by any internal block output pin.
USER RESPONSE:
Verify correct cell contents were found from the proper Search Order during Build Model,
and that cell pin directions and cell contents have been correctly defined.
INFO (TLM-147): Net netname is a PI and PO net of cell cellname.

EXPLANATION:
Net connected to both a cell input and cell output pin.
USER RESPONSE:
Verify correct cell contents were found from the proper Search Order during Build
Model,and that cell pin directions and cell contents have been correctly defined.
INFO (TLM-148): Net netname is a multi-PI net of cell cellname.

EXPLANATION:
Net connected to multiple cell input pins.
USER RESPONSE:
Verify correct cell contents were found from the proper Search Order during Build
Model,and that cell pin directions and cell contents have been correctly defined.
INFO (TLM-149): Net netname is a multi-PO net of cell cellname.

EXPLANATION:

Net connected to multiple cell output pins.

USER RESPONSE:
and that cell pin directions have been defined correctly, and cell contents are defined
correctly.
INFO (TLM-150): Net netname of cell cellname and n other net(s) have been processed
together as one logical net.
The other net(s) are: netname(s).
EXPLANATION:
Within the specified cell, each of the nets specified in the message is connected to one
or more pins on the same usage block. Inside the usage block, these pins are connected
to the same net.
The external nets connected to these pins are being shorted together.
This situation implies that all these nets are electrically common and are to be processed
together as a single net in the flat model.
USER RESPONSE:
Verify that correct cell contents were found from the proper Search Order during Circuit
Import and that cell contents and I/Os are defined correctly. If the usage block is a wire-
through cell (a single wire connecting a single input pin and output pin with no sources
or sinks on any logical elements in the cell), this is expected and is not a problem.
Otherwise, attaching multiple cell input and/or output pins on the same cell net is being
done. This is not considered normal, but is allowed and is being brought to the users
attention for possible analysis.
Use the following routine to analyze the situation:
From the View Schematic window, select View, then select Net to view the net
identified in the message
Press the custom (right) mouse button to select Show Sources and Sinks.
This will show you the pins on the cells that feed or are fed by the net. Trace
down the hierarchy using your left mouse button to select the name of the net
on the inside of the cell that is connected to the pin; and then using the custom
mouse button to select Descend Hierarchy (or by using your middle mouse
button on the net name).
When you find the condition described in the message, determine if the cell
contents are what you expected:

If you expected this condition, continue with Encounter Test processing, nothing
else is required.
If you did not expect this condition, check the messages from Import a New
Circuit to determine where the cell was found.
If it picked up the wrong version of the cell, check the Search Order to determine
why the wrong cell was found.
Refer to the following for details:
Performing Import New Circuit in the Encounter Test: Guide 1: Models.
"Actions on the Encounter Test View Schematic Window" in the Encounter Test:
Reference: GUI.
"Net Actions" in the Encounter Test: Reference: GUI.

INFO (TLM-152): Unable to uncompress file fileName.
EXPLANATION:
USER RESPONSE:
INFO (TLM-153): Unable to compress file fileName.

EXPLANATION:
the specified file.
USER RESPONSE:
page 23).

WARNING (TLM-154): Net netname of cell cellname is connected to a net that acts as
an implied source (ground or vdd). A tie block is created and dotted with other source(s) on
the net to detect potential 3-state contention.
EXPLANATION:
The option to create implied sources for ground or vdd nets was specified during Circuit
Import. The net specified is connected to a ground or vdd net. A tie block is created to
represent ground or vdd and is dotted with the existing source(s) of the net so that a
potential three-state contention can be detected if the logic value on the source of the net
differs from the implied tie value.
USER RESPONSE:
If this net was not intended to be an implied source of ground or vdd, either remove the
option to create implied sources during Circuit Import, or rename the net.
If the net was intended to be an implied source of ground or vdd, no action is necessary,
although test coverage may be degraded due to 3-state contention.
INFO (TLM-155): PI PI name of cell cellName feeds a DOTT | FET (3-state) block but
also feeds other 2-state blocks. The PI will be flagged as a 2-state PI but this model may be
incorrect.
EXPLANATION:
The PI referenced in the message feeds either a DOTT or an FET (transistor) which are
considered 3-state blocks. The PI also fans out to other 2-state blocks. This creates
uncertainty about whether the PI is 2-state or 3-state. It will be flagged as 2-state and
simulation on this model will treat it as such.
USER RESPONSE:
Determine whether flagging this PI as 2-state is acceptable. If not, change the design so
that the PI feeds only 2-state logic or only 3-state logic (not a mix of 2-state and 3-state
logic) and rebuild the model.
ERROR (TLM-160): [Internal] Invalid pin pinname on ROM block blockname of cell
cellname. ROMs should not have data inputs defined.
EXPLANATION:
ROM primitive block should not have any data inputs defined. This error can only occur
as a result of a program error. Encounter Test Circuit Import Hierarchical Model Build
resolves definition of all primitives.
USER RESPONSE:

ERROR (TLM-161): [Internal] Invalid pin pinname on ROM block blockname of cell
cellname. ROMs should not have a write_clock input.
EXPLANATION:
ROM primitive block should not have a write_clock input defined. This error can only
occur as a result of a program error. Encounter Test Circuit Import Hierarchical Model
Build resolves definition of all primitives.
USER RESPONSE:
WARNING (TLM-162): Invalid definition for ROM block blockname of cell cellname.
CONTENTS attribute not specified to identify the ROM personality file. Contents of ROM
assumed to be X.
EXPLANATION:
CONTENTS attribute should be specified for all ROM primitives to identify the ROM
personality file.
USER RESPONSE:
Add CONTENTS attribute to ROM primitive specification and rerun. THIS ERROR
WARNING (TLM-163): Error processing ROM personality CONTENTS file filename.

Invalid data value char for address location, data bit position. X is used.
EXPLANATION:
Invalid data value specified in CONTENTS file ignored. Logic X used instead.
USER RESPONSE:
Respecify a valid value(0,1,X) in CONTENTS file for specified address, data bit and
rerun.
Important

Contents of ROM assumed to be X.
EXPLANATION:

Error occurred when trying to read CONTENTS file.

USER RESPONSE:
Check existence/permissions of CONTENTS file and ROMPATH environment variable
for finding CONTENTS file. Ensure CONTENTS_FORMAT=2 attribute is specified if
ROM CONTENTS file conforms to the Verilog style syntax.
Important

input value on line n is ignored.
EXPLANATION:
Invalid data specified in ROM CONTENTS file is ignored.
USER RESPONSE:
Respecify CONTENTS data and rerun.
Important
WARNING (TLM-166): Error processing ROM personality CONTENTS file filename. Not
enough input data. ROM CONTENTS padded with X.
EXPLANATION:
Not enough data specified for size of ROM. Unspecified addresses assumed X.
USER RESPONSE:
Important
WARNING (TLM-167): Error processing ROM personality CONTENTS file filename. Too
much input data. Data ignored beginning with value on line n.
EXPLANATION:

CONTENTS file specified more data than is appropriate for the size of this ROM
primitive. Extra data ignored.
USER RESPONSE:
Important
WARNING (TLM-168): Suspect data found processing ROM personality CONTENTS file
filename. The first 1, 2, or 3 bits of hex char on line n is (are) not zero. Normal
processing of ROMs whose width(w) is not a multiple of 4 ignores these bits. Bits to be
ignored should be zero. Ensure CONTENTS are correct.
EXPLANATION:
ROM has a width that is not a multiple of 4. After converting the first hex char for each
address to binary, the first 1, 2, or 3 bits are ignored (depending on the remainder when
the width is divided by 4). The data being ignored is not zero. Having this data non-zero
may or may not be an error in the specification of the ROM CONTENTS file. Ensure the
CONTENTS file is correct.
USER RESPONSE:
Respecify CONTENTS data and rerun, if necessary.
WARNING (TLM-169): Unable to open EDAM SA storage area number for accessing
ROM Contents. Error number n from EDAMsopn: explanation of error number
value.
Contents of ROM assumed to be X.
EXPLANATION:
Encounter Test was unable to open storage area for accessing ROM Contents data.
USER RESPONSE:
Customer Support.
WARNING (TLM-170): Unable to map EDAM SA storage area number for accessing
ROM Contents. Error number n from EDAMmap: explanation of error number
value. Contents of ROM assumed to be X.

EXPLANATION:
Encounter Test was unable to map storage area for accessing ROM Contents data.
USER RESPONSE:
Customer Support.
WARNING (TLM-171): Model access unable to load OPCG stats. No statistics_name

record for test mode testmode_name.
EXPLANATION:
The program was unable to load the indicate OPCG statistcs record for the indicated test
mode. It was determined that the statistics should have existed and model access of the
OPCG stats has failed. The calling application will determine if this is a terminating
condition.
USER RESPONSE:
Rebuild the test mode or contact customer support (see Contacting Customer Service
on page 23) for assistance if the problem persists.
ERROR (TLM-175): [Internal] Invalid port definition of RAM/ROM block blockname of

cell cellname. read_enable pin pinname found but no address inputs defined.
EXPLANATION:
ROM primitive block should have address inputs defined. This error can only occur as a
result of a program error. Encounter Test Circuit Import Hierarchical Model Build resolves
definition of all primitives.
USER RESPONSE:
WARNING (TLM-184): [Severe] Invalid CORRELATE attribute value specified for pin
pinname of cell cellname. First character of value must be either a +/1 or -/0 indicating
whether the correlated pin is in phase(+/1) or out of phase(-/0) with its representative pin.
Property is ignored.
EXPLANATION:
Invalid CORRELATE attribute encountered. First character of value is incorrect. First
character of value is required to indicate the relationship between the correlated pin

(having the CORRELATE attribute) and its representative pin (pinname specified as
value of CORRELATE attribute). If the two pins are to be treated identically, specify +/1
to indicate the correlated pin is in phase with its representative. If the correlated pin is to
be treated opposite its representative, specify -/0 to indicate the correlated pin is "out of
phase with its representative. Since CORRELATE attribute was specified for the pin, it is
USER RESPONSE:
Respecify CORRELATE attribute and rerun.
Important
WARNING (TLM-185): [Severe] Invalid CORRELATE attribute pinname1 specified for

pin pinname2 of cell cellname. Pin pinname1 is not defined for cell OR the two pins do
not have the same pin direction. Property is ignored.
EXPLANATION:
Invalid CORRELATE attribute encountered. pinname1 does not identify a pin on the
cell boundary or the pin directions of pinname1 and pinname2 do not match. Since
USER RESPONSE:
Respecify CORRELATE attribute and rerun.
Important
WARNING (TLM-186): [Severe] Conflicting CORRELATE attribute pinname1 specified

for pin pinname2 of cell cellname. Pin pinname1 also has a CORRELATE attribute
specified. CORRELATE attribute for pin pinname2 is ignored.
EXPLANATION:
Invalid CORRELATE attribute encountered. CORRELATE attribute for pinname2
identifies pinname1 as its primary pin to be correlated to, but pinname1 also has a
CORRELATE attribute indicating it is to be correlated to yet another pin. Since
USER RESPONSE:

Provide customer support (see Contacting Customer Service on page 23) with design
hierModel/hierAttributes files and log file.
WARNING (TLM-186): [Severe] Conflicting CORRELATE attribute pinname1 specified

for pin pinname2 of cell cellname. Pin pinname1 also has a CORRELATE attribute
specified. CORRELATE attribute for pin pinname2 is ignored.
EXPLANATION:
Invalid CORRELATE attribute encountered. CORRELATE attribute for pinname2
identifies pinname1 as its primary pin to be correlated to, but pinname1 also has a
CORRELATE attribute indicating it is to be correlated to yet another pin. Since
USER RESPONSE:
ERROR (TLM-187): Internal Program Error: Unable to find Primary PI | PO for correlated
entry entry number, node ID node ID. Contact Customer Support.
EXPLANATION:
An internal program error has occurred. An invalid PI/PO has been passed to model
routine TLMpiEntryGetRPIfromCPI or TLMpoEntryGetRPOfromCPO. This will
require a code fix in the calling application.
USER RESPONSE:
Contact customer support (see Contacting Customer Service on page 23) with design
INFO (TLM-190): PFLT/TFLT attribute for block_function instance block_name of

cell cell_name is IGNORED. PFLT/TFLT overrides are not supported for
block_function instances.
EXPLANATION:
The PFLT attribute for specifying which static pin faults are to be created on the pins of
a block, and/or the TFLT attribute for specifying which dynamic pin faults are to be
created on the pins of a block, were specified on a block for which these attributes are
not supported. The most likely reason is that the block is one which normally has pattern
faults created for it instead of pin faults.
USER RESPONSE:

If you intended to remove pin faults from these blocks, it is possible that the fault model
was built with the wrong options specified. The build_faultmodel command creates
pin faults on certain "pattern fault" blocks if the default autopatternfaults=no option
to replace automatically generated pattern faults with pin faults is in effect. If this is the
case, rebuild the fault model with the autopatternfaults=yes option.
Otherwise, perform either of the following actions:
Remove the PFLT/TFLT attribute from the design source and rebuild the model
(or use the edit_model command to remove them).
Ignore the message and continue.
Refer to the following in the Encounter Test: Reference: Commands for additional
information:
build_faultmodel
edit_model
INFO (TLM-191): DFLT/RFLT attribute for block_function instance block name of

cell cell name is IGNORED. DFLT/RFLT overrides not supported forblock_function
instances.
EXPLANATION:
The DFLT attribute for removing parametric driver faults on the pins of a block and/or the
RFLT attribute for removing parametric receiver faults on the pins of a block was/were
specified on a block for which these attributes are not supported. The most likely reason
is that the block is one which normally does not have parametric driver/receiver faults.
USER RESPONSE:
Either remove the DFLT/RFLT attribute from the design source and rebuild the model (or
use model edit to remove them) or ignore the message and continue on.
Refer to following for more information:
Pin Fault Specification Using Verilog in the Encounter Test: Guide 4:
Faults.
"Summary of Attributes" in the Encounter Test: Guide 1: Models.
INFO (TLM-192): FAULTS=NO attribute for block function instance block name of
cell cell name is IGNORED. FAULTS=NO override not supported for block function
instances.
EXPLANATION:

The FAULTS=NO attribute for removing static/dynamic faults from a block was specified
on a block for which this attribute is not supported. The most likely reason is that the block
is one which normally does not have static/dynamic faults.
USER RESPONSE:
Either remove the FAULTS=NO attribute from the design source and rebuild the model (or
use model edit to remove them) or ignore the messages and continue on.
INFO (TLM-193): Invalid attribute name value of attribute value specified for
input pin pin name on block block name in view view name. Value is ignored.
EXPLANATION:
The PFLT, TFLT, DFLT, or RFLT attribute value specified is not a supported value. The
attribute will be ignored.
USER RESPONSE:
Refer to "Summary of Attributes" in the Encounter Test: Guide 1: Models for a list of
supported attributes and their valid values. Correct the attribute in the design source or
remove it and rebuild the model (or use model edit to do this), or ignore this message
and continue on if this is not considered a problem.
Additional information is available in Pin Fault Syntax in the Encounter Test: Guide
4: Faults.

ERROR (TLM-201): Required parameter WORKDIR was not specified. Report program
terminates.
EXPLANATION:
USER RESPONSE:
Specify WORKDIR and rerun.
ERROR (TLM-202): Required parameter ENTITY was not specified. Report program
terminates.
EXPLANATION:
ENTITY is a required parameter to identify the design to process.

USER RESPONSE:
Specify ENTITY and rerun.
WARNING (TLM-203): Options requiring TESTMODE will not be processed. Required

parameter TESTMODE was not specified.
EXPLANATION:
TESTMODE is a required parameter for options t, s, l, v, o, w, x and k.
USER RESPONSE:
Specify TESTMODE and rerun.
ERROR (TLM-204): No options were specified to process.

EXPLANATION:
No options were specified.
USER RESPONSE:
Specify one or more options and rerun.
ERROR (TLM-205): Unable to resolve input design flatModel file. Report

program terminates.
EXPLANATION:
Report program has failed to resolve the input design flatModel filename using
USER RESPONSE:
ERROR (TLM-206): Unable to access input design flatModel file. Report

program terminates.
EXPLANATION:
Report program has failed to access the input design flatModel. See previous
message(s).
USER RESPONSE:

WARNING (TLM-207): Unable to access test mode modename. Options requiring

TESTMODE will not be processed.
EXPLANATION:
Encounter Test has failed to access the input TESTMODE. See previous message(s).
USER RESPONSE:
WARNING (TLM-208): Unable to access latch data for test mode modename. Latch options
requested will not be processed.
EXPLANATION:
Encounter Test has failed to access the input TESTMODE latch data. See previous
message(s).
USER RESPONSE:
WARNING (TLM-209): Unable to access three-state dot data for test mode modename.
Keeper devices will not be processed.
EXPLANATION:
Encounter Test has failed to access the input TESTMODE keeper device data. See
previous message(s).
USER RESPONSE:
INFO (TLM-210): Dependent pin pinName in the CORRELATE modedef statement is

defined as a representative pin in the model. All dependent pins correlated in the model to
this representative pin will be correlated to the representative pin specified in the
CORRELATE modedef statement.
EXPLANATION:
A CORRELATE statement in the test mode definition file specified that some pin, call it
PinA, is correlated to some other pin, PinB. A CORRELATE attribute in the model source
has some other pin(s) correlated to PinA. All these pins, including PinA, will now be
correlated to PinB, and PinA will no longer be considered a representative pin.

USER RESPONSE:
Make sure that you wanted the entire group of pins correlated together. If not, use
additional CORRELATE and/or UNCORRELATE statements to define the correlation you
need, and rebuild the test mode.
Refer to "CORRELATE" and BuildTest Mode in the Encounter Test: Guide 2:
INFO (TLM-211): Conflict with the attribute defined correlation polarity and modedef polarity
was detected for dependent pin corrPinName and representative pin repPinName.
Polarity as defined in the modedef will be used.
EXPLANATION:
The relative polarity of two correlated pins has been respecified by a CORRELATE
statement in the test mode definition file.
USER RESPONSE:
Make sure the relative polarity as specified in the mode definition file is correct.
INFO (TLM-212): The dependent pin corrPinName in the CORRELATE modedef

statement is defined as a dependent pin (to a different representative pin) through the
correlate attribute. The correlation is changed to the modedef definition.
EXPLANATION:
PinA, is correlated to some other pin, PinB. A CORRELATE attribute in the model source
has PinA correlated to some other pin, PinC. The mode definition file takes precedence;
for this test mode, the correlation of the named pin will be as defined in the mode
definition file.
USER RESPONSE:
No action is required if this correlation is the desired outcome.
If this is not the desired outcome, correct the pin correlation specified in the mode
definition file and rebuild the test mode.
Refer to "CORRELATE" in the Encounter Test: Guide 1: Models for additional
information.
WARNING (TLM-213): [Severe] The representative pin repPinName in the CORRELATE

modedef statement has previously been defined as a dependent pin.
The statement will be IGNORED.

EXPLANATION:
PinA, is correlated to some other pin, PinB. A CORRELATE attribute in the model source,
or in a previous mode definition CORRELATE statement has PinB correlated to some
other pin, PinC.
Your intent is not clear. To understand why Encounter Test might be confused, refer to
the RESPONSE section, below. Encounter Test will not process this CORRELATE
statement.
USER RESPONSE:
If you intended both PinA and PinB to be correlated to PinC, change this CORRELATE
statement to correlate PinA directly with PinC, and rebuild the test mode.
If you intended PinA to be correlated to PinB, but not to PinC, add a UNCORRELATE
PinB statement to the mode definition file, and rebuild the test mode.
Refer to "CORRELATE" and Build Test Mode in the Encounter Test: Guide 2:
ERROR (TLM-214): [Internal] PROGRAM ERROR: Internal problem occurred while

processing the Pin correlation data.
correlateIssue
Contact customer support so this design may be analyzed.

EXPLANATION:
The internal correlation structures contain unexpected data. The correlation is suspect
at best.
USER RESPONSE:
Contact customer support (see Contacting Customer Service on page 23) so this
design may be analyzed..
WARNING (TLM-220): LMovrds: file parsing error occurred on line line

number for message message number while parsing TEImsgOverrides file. Override
ignored
EXPLANATION:
The parsing error described in the message (most likely a syntax error) occurred on the
line shown for the message ID shown, in the message overrides file. Processing
continues and this override is ignored. The only way for this to occur is if the

TEImsgOverrides file that was originally created by build_model has been

manually edited.
USER RESPONSE:
Correct the error in the message overrides file (TEImsgOverrides) and rerun if
necessary.
INFO (TLM-221): Unable to successfully use shared memory for file filename. Data type
is datatype. Length of the data is length. Processing continues without using shared
memory for this data. Application execution is unaffected.
EXPLANATION:
This situation does not affect application execution. However, if this execution is one of
many within a script flow, subsequent application initializations will not be speeded up
due to the data not being saved in shared memory. Also, if there are concurrent
application executions on the same machine, there will be no sharing of this data. This
message is issued when the program failed to use Shared Memory for loading the design
related information. There can be many reasons for this situation to happen. Following
are the most possible sources of failure:
The machine does not have enough Shared Memory space to load the design data
identified.
The machine is not configured with the correct Shared Memory limits.
USER RESPONSE:
This message will be preceded by other messages which identify the reason for failure.
Contact your system administrator to increase the amount of Shared Memory available
for application use. It is recommended that Shared Memory be set to one-half of the real
memory size on the machine.
WARNING (TLM-222): Invalid MSGID specification msgid on line lineNumber while

parsing TEImsgOverrides2 file. TSV message elimination is not supported for the
TEImsgOverrides2 file. CSV is converted to TSV and message suppression is done for
this MSGID. Processing continues.
EXPLANATION:
The MSGID value is the syntax for TSV message elimination. Message elimination is not
supported within a TEImsgOverrides2 file. MSGID is converted to TSV and message
suppression is done for this MSGID. Processing continues.
USER RESPONSE:

If necessary, change MSGID specification of CSV to TSV for the line number identified
in the TEImsgOverrides2 file.
WARNING (TLM-223): Instance | Net hierarchicalname specified on line

lineNumber in TEImsgOverrides2 file for MSGID msgid does not exist. Override is
EXPLANATION:
A TEImsgOverrides2 file was found in the tbdata (or ENTITY) directory. The instance
or net name specified does not exist in the design. Messages cannot be suppressed for
this specification. Processing continues and this override is ignored.
USER RESPONSE:
Verify the name of the instance or net. If the name is valid, ensure the syntax properly
identifies the name as a NET (for a net name) or INSTANCE (for an instance name).
Correct the error in the TEImsgOverrides2 file as necessary.
WARNING (TLM-224): Parsing error occurred on line lineNumber for MSGID

msgid while parsing TEImsgOverrides2 file. Processing for current MSGID msgid
stops. Skipping to the next MSGID.
EXPLANATION:
The parsing error described in the message (most likely a syntax error) occurred on the
line shown for the message ID shown while parsing the TEImsgOverrides2 file. Due
to the simplistic nature of the parser used for the TEImsgOverrides2 file, processing
must skip to the next MSGID specified.
USER RESPONSE:
Correct the error in the TEImsgOverrides2 file as necessary.
INFO (TLM-500): Net Voltage File Data:

EXPLANATION:
A print of the power and ground nets defined by the Alternate Voltage file.
USER RESPONSE:
No response necessary.
ERROR (TLM-993): Unable to migrate testmode data. Data within modeInfo file was
created before year 2004.
EXPLANATION:

The modeInfo file was created prior to year 2004. Data cannot be migrated to latest
format for processing in current release of Encounter Test.
USER RESPONSE:
Provide customer support (see Contacting Customer Service on page 23) with tbdata
directory and log file.
ERROR (TLM-994): [Internal] PROGRAM ERROR: Unable to convert

CORRELATE=pinname1 for pin pinname2 of cell cellname. CORRELATE attribute
ignored. Contact customer support (see Contacting Customer Service on page 23) if
correlation required (TLMnodeID nodeID).
EXPLANATION:
A program error has occurred. Unable to match pinname1 to its respective PI/PO.
Debug data has been printed to help customer support in analysis.
USER RESPONSE:
Provide customer support with design hierModel/hierAttributes files and log file.
ERROR (TLM-995): [Internal] PROGRAM ERROR: Unable to compress index/cell view

index/cellname. Encounter Test Flat Model Build exits. Contact customer support (see
Contacting Customer Service on page 23). Debug data - TLMnodeID nodeID/
primitive function - Relative hierModel object index hierModel index.
EXPLANATION:
A program error has occurred. Internal table data has been over-written. Debug data has
been printed to help customer support in analysis.
USER RESPONSE:
ERROR (TLM-996): [Internal] PROGRAM ERROR: Unable to compress index/cell view

index/cellname. Encounter Test Flat Model Build exits. Contact customer support (see
Contacting Customer Service on page 23). Debug data - searching for hierPin hierModel
index TLMnodeID nodeID.
EXPLANATION:
A program error has occurred. Internal table data has been corrupted. Debug data has
USER RESPONSE:

INFO (TLM-998): debug data

EXPLANATION:
This message is strictly debug data for customer support analysis.
USER RESPONSE:
ERROR (TLM-999): [Internal] PROGRAM ERROR: "debug data"

EXPLANATION:
A program error has occurred. Internal table data has been corrupted. Debug data has
USER RESPONSE:

49
TLP - Low Power Messages
TLP-100 through TLP-700 on page 1535
TLP-100 through TLP-700

ERROR (TLP-100): Common Power Format: error message text
EXPLANATION:
This message reports error messages related to the Conformal linters parsing of the
Common Power Format (CPF) file. Refer to the Conformal documentation if help is
required on the linter message ID referred to in this error message.
USER RESPONSE:
Fix error(s) in the CPF file and rerun the command.
WARNING (TLP-101): Common Power Format: error message text

EXPLANATION:
This message reports error messages related to the Common Power Format (CPF)
syntax and semantic accuracy. Some examples are pins or instances specified in the
CPF not present in the Encounter Test model.
USER RESPONSE:
Check the CPF file and/or netlist, fix the detected error(s) and rerun if necessary.
ERROR (TLP-102): Unable to obtain license_name License.

EXPLANATION:
This command requires the indicated license to run. In this case, the license could not
be obtained at the time of invocation. The run cannot proceed without the required
license.
USER RESPONSE:

Ensure the specified license is available and rerun.
ERROR (TLP-103): error_message_text

EXPLANATION:
This message flags errors encountered while parsing the Common Power Format
information. Some examples are - linter errors in the CPF, mismatches with set_design,
and so on. The message text provides a detailed description of the error scenario.
USER RESPONSE:
Fix the error(s) reported by the message and rerun the command.
ERROR (TLP-104): Unable to locate CPF information in the Encounter Test database.
Ensure that the prepare_cpf_data command has been previously executed to populate
the Encounter Test database.
EXPLANATION:
CPF information must be available in the Encounter Test database from a previously
successful prepare_cpf_data command.
USER RESPONSE:
Rerun the prepare_cpf_data command to populate the Encounter Test Database
with the CPF information.
ERROR (TLP-105): Unable to read lock file filename.

EXPLANATION:
The command requires a read lock on the referenced file to ensure that the file contents
do not change while this command is running. This error message is produced because
a read lock on this file cannot be obtained.
USER RESPONSE:
Ensure that the file is available. If the problem persists, ensure no other application has
a write lock on this file. Rerun when the file is available.
ERROR (TLP-106): Value, value, specified for the keyword keyword is not valid.
EXPLANATION:
An unsupported value has been specified for the keyword.
USER RESPONSE:

Specify a supported value for the keyword. Refer to the appropriate command
documentation to determine the allowed values for this keyword.
ERROR (TLP-107): The input CPF file is hierarchical. See line line_number, file
filename. Encounter Test does not support reading in hierarchical CPF files. Run this file
through the CPF integrator and read in the integrated CPF file instead of this hierarchical file.
EXPLANATION:
Encounter Test does not support reading in hierarchical CPF files. One example of a
hierarchical CPF is set_instance -design <xxx> -domain_mapping {{a b}}..
USER RESPONSE:
Process hierarchical CPF files through the CPF integrator to generate a flattened CPF
that can be read in by Encounter Test.
ERROR (TLP-108): Unable to load the Encounter Test model. Ensure that the correct
WORKDIR has been specified, the build_model command has been run previously, and that
this command has read/write access to files in the WORKDIR/tbdata directory.
EXPLANATION:
The build_model command must have been run prior to running this command. If
build_model has already been run, then ensure the correct WORKDIR has been
specified and that this command has read/write access to the files in the WORKDIR/
tbdata directory.
USER RESPONSE:
Ensure the preceding scenarios in the message explanation are not preventing this
command from loading the model. If problems persist, contact customer support refer to
ERROR (TLP-109): In the set_macro_model command, macroname macroname is

invalid as it does not exist in the design.
EXPLANATION:
The macro name specified with the set_macro_model command must exist in the
design.
USER RESPONSE:
Ensure the macro name is correctly specified or that the macro is added to the design.
Rerun build_model if the netlist is edited to add the macro and then rerun this
command.

ERROR (TLP-110): Encounter Test currently does not support wildcards in the instance
name instname specified on the set_instance command. Provide a fully qualified
instance name and rerun this command.
EXPLANATION:
Wildcards are not supported in the instance name provided to the set_instance
command.
USER RESPONSE:
Expand the wildcards in the instance name and rerun the command.
ERROR (TLP-111): Power Sequence name could not be found in the Encounter Test
database. Ensure that its sequence definition has been loaded into Encounter Test.
EXPLANATION:
The specified power sequence could not be located in the Encounter Test database. The
sequence may be read into Encounter Test via the read_sequence_definition
command, via build_testmode, or via the sequencefile option of this command.
USER RESPONSE:
Ensure the sequence has been read into Encounter Test and rerun the command.
ERROR (TLP-112): Retention test generation will terminate as there are no SRPGs active
in this power mode.
EXPLANATION:
Test generation will terminate if there are no SRPGs to target for retention tests.
USER RESPONSE:
Ensure there are SRPGs active in this power mode and rerun the command, or perform
test generation in a different power mode.
ERROR (TLP-113): Errors were encountered while running cmdname to process the fault
subset. The command run was cmdtext.
EXPLANATION:
The specified command was run as part of the steps to build a fault subset consisting of
just the faults on SRPGs.
USER RESPONSE:
Fix the errors by running the specified command standalone, and then rerun this
command.

ERROR (TLP-114): Unable to find the logfile for the cmdname invocation. The logfile should
be at file.
EXPLANATION:
An error may have occurred during the specified command that prevented logfile
generation.
USER RESPONSE:
Fix the reported errors and then rerun this command.
ERROR (TLP-115): This design has number scan sections. Multiple scan sections are not
supported by this command.
EXPLANATION:
Retention test generation does not support more than one scan section. If this message
appears, then number should be greater than 1. Retention test processing will terminate.
USER RESPONSE:
Ensure the scan sequences were properly defined. If more then one scan section
actually exists, the scan protocol must be redesigned for retention test generation.
ERROR (TLP-116): This is a compression test mode. Retention test generation is not
supported for compression test modes.
EXPLANATION:
Retention test generation does not support compression test modes.
USER RESPONSE:
Run this command only for non-compression test modes.
ERROR (TLP-117): There are zero regType Registers in this test mode. Retention test
generation requires a non-zero number of stimmable and measurable registers.
EXPLANATION:
Retention test generation requires a non-zero number of stimmable and measurable
registers.
USER RESPONSE:
Run this command only for test modes that have both stimmable and measurable
registers.

ERROR (TLP-118): Retention test generation will terminate as this test mode is not a power
mode.
EXPLANATION:
Retention test generation for SRPGs requires the test mode to be a power mode since
this form of test generation requires Common Power Format (CPF) information.
USER RESPONSE:
When performing test generation for SRPGs, run this command only for test modes that
are power modes, or rebuild this test mode to be a power mode.
ERROR (TLP-119): Retention test cannot be generated for any of the scan chains in this
design.
EXPLANATION:
There are several reasons that retention test cannot be generated. If one of these applies
to any scan chain, that scan chain is ignored for purposes of generating the retention
tests. This message means that for each scan chain, one of the following applies:
The scan chain register is not both controllable and observable.
The scan data input is not a contacted primary input.
The scan data output is not a primary output.
USER RESPONSE:
Ensure you are running in the correct test mode. The test mode must have one or more
scan chains that meet all the conditions listed in the explanation of this message.
ERROR (TLP-120): Errors encountered during generation of retention test patterns.

EXPLANATION:
There were errors during retention test generation.
USER RESPONSE:
Refer to previous messages for error information, resolve errors, and then rerun.
ERROR (TLP-121): A CPF Name Mapping file was used when running the
prepare_cpf_data command, but the name mapping information cannot be located in the
Encounter Test database. Rerun prepare_cpf_data to populate this information in the
Encounter Test database.
EXPLANATION:

When the prepare_cpf_data command is run, the Encounter Test database is

updated to reflect the information generated by this command. However, if you modify
the tbdata directory, some of this information may be corrupted.
USER RESPONSE:
Rerun prepare_cpf_data to update the Encounter Test database.
WARNING (TLP-300): Common Power Format linter WARNING message_text

EXPLANATION:
This message reports warning messages related to the Conformal linters parsing of the
Common Power Format (CPF) file. Refer to Conformal documentation if help is required
on the linter message ID referred to in this message.
USER RESPONSE:
No response is required if the warning is expected. Otherwise, fix the Warning(s) in CPF
file and rerun the command.
WARNING (TLP-301): message_text

EXPLANATION:
This message flags warnings encountered while processing the Common Power Format
information. One example is the inability obtain a hier block from the Encounter Test
model that matches a CPF object.
USER RESPONSE:
Review the warning message, fix any issues and rerun if necessary.
WARNING (TLP-302): Testmode testmodename is not a Power Mode. All Power

Component instances in the design will be assumed to be powered on in this testmode.
EXPLANATION:
Since the specified testmode is not a power mode, it is not possible to determine which
power component instances in the design are powered on. Hence, all power component
instances in the design are assumed to be powered on and will be reported.
USER RESPONSE:
If the testmode is associated with a power mode, rebuild the testmode before running this
command.

WARNING (TLP-303): The prepare_cpf_data command issued warning messages

while processing the CPF information. Some of these warnings may negatively impact the
CPF-based processing done by this command.
EXPLANATION:
The prepare_cpf_data command issued Warning messages while parsing the CPF
information and correlating it against the Encounter Test model. Incorrect data may result
depending upon the CPF data that is being accessed by the current command.
USER RESPONSE:
Review the warning messages generated by prepare_cpf_data and fix issues
relevant to the current command. Rerun prepare_cpf_data before rerunning this
command.
WARNING (TLP-304): Power Sequence sequencename does not have any patterns. This
power sequence will not be used for test generation.
EXPLANATION:
During test generation, patterns within the user-specified power sequence are copied
into the generated test sequence. Since the user-specified power sequence does not
have any patterns, this power sequence will be ignored during test generation.
USER RESPONSE:
Fix the power sequence and rerun the command.
WARNING (TLP-305): Power Sequence sequencename does not have the sequence
definition attribute of test. This sequence will not be used for test generation.
EXPLANATION:
The power sequence definition must have the sequence definition attribute of test.
Other sequence definition attributes like modeinit, scan, and so on,, are not supported.
The specified sequence will be ignored during test generation.
USER RESPONSE:
If this sequence is to be used for test generation, change the sequence definition
attribute to test and rerun the command.
WARNING (TLP-306): SRPG blockname with hierblock index hierIndex is on the scan
path but does not have any measure points within it. This SRPGs retention capabilities
cannot be tested by scan. This may affect the test coverage.
EXPLANATION:

The Test Structure Identification process did not identify any measure points within this
SRPG instance. One reason for this could be a lockup flop present after the scan flop
within this SRPG. The lockup flop then becomes the RML for this scan bit. There must
be a stimmable and observable scan bit within the SRPG for the SRPG retention
capability to be tested.
USER RESPONSE:
No response required. The intent of this message is to indicate that there may be a loss
in test coverage.
WARNING (TLP-307): SRPG blockname with hierblock index hierIndex is not on the
scan path and hence its retention capabilities cannot be tested by scan. This may affect the
test coverage.
EXPLANATION:
SRPGs that are not on the scan path cannot currently be tested for retention defects. The
specified SRPG will not be targeted during test generation.
USER RESPONSE:
If this SRPG is intentionally excluded from the scan chains, then no response is required.
Otherwise, rerun scan synthesis to add this SRPG to the scan chains.
WARNING (TLP-308): Since Power domain domain_name is OFF in Power Mode

mode_name, Encounter Test will treat this domain to be OFF when building the testmode.
But since this domain has been defined in the CPF as an external controlled shutoff, it will
likely stay powered ON at the tester, and the shutoff condition will not be verified by Encounter
Test. The shutoff condition must be set to the correct state, otherwise the generated tests may
fail during simulation.
EXPLANATION:
Encounter Test will not perform specific shutoff condition checks for externally controlled
domains during test mode build since these domains can remain powered ON at the
automatic test equipment. If a power mode specifies such external controlled domains to
be OFF in that power mode, then these domains will be treated as OFF in that power
mode. At the tester, these domains may stay powered ON since their power rails may not
take into account this shutoff condition since the power gating is off the chip. This warning
is intended to highlight the possibility of such mismatches.
USER RESPONSE:
If the described condition is not the design intent, consider not generating test patterns
under such power modes.

WARNING (TLP-340): There were num_seq test sequences where the percentage of scan
flops that can switch could not be brought below the maxcaptureswitching limit of
user_limit. This number is percentage% of the total (includes ineffective/rejected)
sequences.
EXPLANATION:
The message indicates the number of tests where the capture switching activity cannot
be guaranteed to be below the user-specified limit.
USER RESPONSE:
Consider either of the following and then rerun if necessary:
Specify a lower compaction effort.
Insert more fine grain clock gating logic.
WARNING (TLP-341): There were numseq test sequences where the percentage of scan
flops that can switch could not be brought below the maxcaptureswitching limit of
userlimit%. This number is percentage% of the totalnumseq sequences
generated in this run.
EXPLANATION:
The message indicates the number of tests where the capture switching activity cannot
be guaranteed to be below the user-specified limit.
USER RESPONSE:
Consider either of the following and then rerun if necessary:
Specify a lower compaction effort.
Insert more fine grain clock gating logic.
WARNING (TLP-342): For num clock(s), the specified maxcaptureswitching value of

maxcapswitch may not be achieved due to inadequate clock gating.
EXPLANATION:
For clock trees that directly control a lot of scan flops instead of using clock gating logic,
sufficient number of flops cannot be gated off to reach the user specified
maxcaptureswitching limit.

USER RESPONSE:
Analyze the switching activity of the generated patterns (using write_toggle_gram
command) to verify if the actual switching is within acceptable limits. If not, rerun ATPG
using lower compaction effort or insert additional clock gating logic into the design.
WARNING (TLP-343): Out of the totalnum clock gates identified, there were num clock
gates for which problems were encountered when trying to control them during test
generation. numcontrollable clock gates will be utilized during test generation to reduce
capture switching activity.
EXPLANATION:
This message could be generated due to the following reasons:
The testmode constraints make it impossible for the clock to be gated off at this clock
gate.
The clock gating logic is controlled by a latch whose data may be tied to a static
value, but the latch may not be a flush latch. If the latch were a fixed value latch, this
logic would not even have been identified as a clock gate. Either way, this clock gate
cannot be controlled by the test generator to gate the clock off and reduce capture
switching.
The logic controlling the functional enable of the clock gate comes from TIEX (or
TIUP/TIDN) blocks or unmodeled (black-box) logic, making it impossible in this
testmode for the clock to be gated off at this clock gate.
USER RESPONSE:
Rerun test generation specifying reportclockgateinfo=all. This keyword lists all
the identified clock gates along with YES/NO information on whether the clock gate can
be utilized during test generation to reduce capture switching activity. Open the
Encounter Test Schematic in the Test Constraint and Clocks Off state to analyze the
clock gates and determine why the logic controlling the clock gate cannot be set to gate
the clock off.
ERROR (TLP-344): The specified maxcaptureswitching value of maxcapswitch cannot

be achieved due to inadequate clock gating on clock pinname. uncpercent of flops are
not controlled by clock gates, and a margin of margin is required for effective ATPG. Raise
the maxcaptureswitching limit, add additional clock gating to the design or linehold the
clock during ATPG.
EXPLANATION:
In order to effectively generate patterns, enough flops have to be gated off using clock
gating logic, a sufficient number of flops cannot be gated off to reach the user specified

maxcaptureswitching limit. If more than 1/2 of the ungated flops switch during capture,
there will not be enough ungated flops for ATPG to use when generating tests.
USER RESPONSE:
Raise the maxcaptureswitching limit, add additional clock gating to the design or
linehold the clock during ATPG. If a clockconstraints file is used, remove the clock from
the clockconstraints file.
ERROR (TLP-345): The specified maxcaptureswitching value of maxcapswitch cannot

be achieved during the phase pulse for testsequence=seqname due to inadequate clock
gating. uncpercent of flops are not controlled by clock gates, and a margin of margin is
required for effective ATPG. Raise the maxcaptureswitching limit, add additional clock
gating to the design or remove the clocks from the testsequence.
EXPLANATION:
In order to effectively generate patterns, enough flops have to be gated off using clock
gating logic, a sufficient number of flops cannot be gated off to reach the user specified
maxcaptureswitching limit. If more than 1/2 of the ungated flops switch during
capture, there will not be enough ungated flops for ATPG to use in pattern generation.
USER RESPONSE:
Raise the maxcaptureswitching limit, add additional clock gating to the design or remove
the clock(s) from the testsequence.
WARNING (TLP-346): The specified maxcaptureswitching value of maxcapswitch

may not be achieved due to inadequate clock gating on clock pinname. uncpercent of
flops are not controlled by clock gates, and a margin of margin is required for effective
ATPG.
EXPLANATION:
The run continues, but in order to effectively generate patterns, enough flops have to be
gated off using clock gating logic, a sufficient number of flops cannot be gated off to
reach the user specified maxcaptureswitching limit. If more than 1/2 of the ungated
flops switch during capture, there may not be enough ungated flops for ATPG to use
when generating tests.
USER RESPONSE:
linehold the clock during ATPG. If a clockconstraints file is used, remove the clock
from the clockconstraints file.

WARNING (TLP-347): The specified maxcaptureswitching value of maxcapswitch

may not be achieved during the seqname pulse for testsequence=uncpercent due to
inadequate clock gating. phase of flops are not controlled by clock gates, and a margin of
margin is required for effective ATPG.
EXPLANATION:
The run continues, but in order to effectively generate patterns, enough flops have to be
gated off using clock gating logic, a sufficient number of flops cannot be gated off to
reach the user specified maxcaptureswitching limit. If more than 1/2 of the ungated
flops switch during capture, there may not be enough ungated flops for ATPG to use in
pattern generation.
USER RESPONSE:
remove the clock(s) from the testsequence.
ERROR (TLP-501): [Internal] An unexpected condition occurred in the Encounter Test

code. Contact customer support to report this error and provide the following information:
error_info.
EXPLANATION:
information provided in the message is not intended to be meaningful to you; but it will
USER RESPONSE:
Contact the customer support team using your normal process; SourceLink, E-mail, or
customer support.
INFO (TLP-600): Processing Common Power Format (CPF) file filename.

EXPLANATION:
The specified CPF file has been provided to the command and the contents will be
verified for syntax and semantic accuracy.
USER RESPONSE:

INFO (TLP-601): The CPF information has been saved in the Encounter Test database.
EXPLANATION:
The specified CPF file has been read in and the relevant information has been stored in
the Encounter Test database that downstream Encounter Test commands can use.
USER RESPONSE:
INFO (TLP-602): Reading CPF information from the Encounter Test database.
EXPLANATION:
This message indicates that the command is accessing CPF information from the
Encounter Test database.The database must have been populated earlier by running the
prepare_cpf_data command.
USER RESPONSE:
INFO (TLP-603): Getting Power Component instances active in Power Mode powermode.
EXPLANATION:
The command uses the specified type of power components to look for all instances in
the design that match the power component type and that are active in the power mode
USER RESPONSE:
INFO (TLP-604): Found numinstances active instances of Power Component type(s)

powercomponents in Power Mode powermode.
EXPLANATION:
The command uses the specified type of power components to reort the number of
instances in the design that match the power component type and that are active in the
power mode.
USER RESPONSE:
INFO (TLP-605): Getting Power Component instances in the design.

EXPLANATION:
The command is obtaining the power component instances in the design.
USER RESPONSE:
INFO (TLP-606): Found numinstances instances of Power Component type(s)

powercomponents in the design.
EXPLANATION:
The command uses the specified type of power components to report then number of
instances in the design that match the power component type.
USER RESPONSE:
INFO (TLP-607): For Power Component type powercomponents, there are no cells
defined in the CPF file.
EXPLANATION:
The Common Power Format (CPF) file does not contain any cell definitions for the
specified power component type. Some examples of CPF commands for defining cells
are define_state_retention_cell and define_isolation_cell. Refer to the
Encounter Test: Flowsfor a comprehensive list of CPF-related commands.
USER RESPONSE:
No response is required if this is the intent. Otherwise, assess whether the CPF file must
be enhanced to define the power component cells and rerun if necessary.
INFO (TLP-608): A fault subset will be created containing just the faults on Power
Components of type SRPG. This fault subset is created by running report_faults
powercomponent=srpg and prepare_fault_subset.
EXPLANATION:
A fault subset will be created. This is the same fault subset that would be created by
sequentially running the report_faults and prepare_fault_subset commands.
USER RESPONSE:

INFO (TLP-609): The Testmode Statistics below are based on a fault subset
containing only the active faults on SRPGs, and not all the faults active in testmode
modename.
EXPLANATION:
The Testmode Statistics section of the log normally reports fault statistics on ALL
the faults active in the testmode. The statistics below are for a subset of the faults active
in the testmode.
USER RESPONSE:
INFO (TLP-610): There is number Power Sequence name(s) specified to this command.
EXPLANATION:
The message states the number of user-specified number of power sequences.
USER RESPONSE:
INFO (TLP-611): Power Sequence sequencename has number pattern(s).

EXPLANATION:
The message states the identified number of patterns in the user-specified power
sequence.
USER RESPONSE:
INFO (TLP-612): There are number scan chains that are both controllable and observable.
EXPLANATION:
The message states the identified number of controllable and observable chains in the
current testmode.
USER RESPONSE:
INFO (TLP-613): The length of the longest scan chain is number bits.
EXPLANATION:

The message states the length of the longest scan chain.

USER RESPONSE:
INFO (TLP-614): SRPG blockname with hierblock index hierIndex has a measure
latch in it, but does not have a corresponding stim latch. The program will skip this measure-
only latch.
EXPLANATION:
The specified latch is present with the SRPG cell, but is a measure-only latch. A latch
must be capable of both stim and measure to properly test the retention capability of the
SRPG. The specified latch will be ignored and the command will look for other latches
inside the SRPG.
USER RESPONSE:
INFO (TLP-615): The logfile for cmdname command is file.

EXPLANATION:
The message identifies the location of the log file produced by the specified command.
USER RESPONSE:
INFO (TLP-616): Since measureallflops=yes is specified, all scan flops active in this
test mode will be measured in the Scan_Unload event.
EXPLANATION:
Since the measureallflops=yes keyword is specified, this command will not be using
any Common Power Format (CPF) information, and all the scan flops active in this test
mode will be expected to retain their state after the power sequence is applied.
USER RESPONSE:
INFO (TLP-617): Total of number retention tests have been generated.

EXPLANATION:
This messages states the number of generated retention tests.

USER RESPONSE:
INFO (TLP-640): Number of clock gates identified in this testmode is number.

EXPLANATION:
This messages states the number of identified clock gates for the current testmode.
USER RESPONSE:
INFO (TLP-641): Number of clock trees identified in this testmode is number. Only the clock
trees controlling scan flops are reported.
EXPLANATION:
This messages states the number of iclock trees controlling scan flops for the current
testmode.
USER RESPONSE:
INFO (TLP-642): There is number clock(s) for which the specified

maxcaptureswitching value of maxcapswitch% cannot be achieved due to
inadequate clock gating.
EXPLANATION:
For clock trees that directly control many scan flops instead of using clock gating logic, a
sufficient number of flops cannot be gated off to reach the user-specified
USER RESPONSE:
INFO (TLP-643): Percentage of flops gated in this testmode is number%.

EXPLANATION:
This message indicates the extent of clock gating in the current testmode.
USER RESPONSE:

INFO (TLP-644): Average number of flops controlled per clock gate in this testmode is
number.
EXPLANATION:
This message indicates the granularity of clock gating available in this testmode.
USER RESPONSE:
INFO (TLP-645): Since a value of 100 has been specified for the maxcaptureswitching
keyword, no effort will be made to utilize clock gates to reduce capture switching.
EXPLANATION:
A maxcaptureswitching value of 100 indicates that the capture switching activity of
upto 100% is allowed. Therefore, no clock gates need to be turned off to reduce the
switching activity.
USER RESPONSE:
No response required if this is the desired value for the maxcaptureswitching
keyword.
INFO (TLP-646): There are a total of num scan flops that can switch in this testmode.
EXPLANATION:
This message reports the number of flops that are part of the scan chains. This number
is testmode specific, and identifies the number of RMLs present in the testmode.
USER RESPONSE:
INFO (TLP-647): For maxcaptureswitching of perc, the maximum number of scan flops that
can be allowed to switch is numflops.
EXPLANATION:
This messages reports the maximum number of RMLs that can be allowed to toggle in
a single clock pulse event to achieve the specified maxcaptureswitching value.
USER RESPONSE:
INFO (TLP-648): Unable to identify any clock gates in this testmode.

EXPLANATION:
This message could be generated due to the following reasons:
There may not be any clock gating logic that is present in the design.
There may be clock gating logic present in the design, but it may not be a part of the
active logic in this testmode.
The test signal override to the clock gating logic may be a +/-TI signal. This will
cause the clock gating logic to be forced ON for the entire duration of the test and
cannot be turned OFF by ATPG. Such clock gates cannot be identified by this
command.
The style of clock gating logic may be unsupported by the command. Refer to the
Encounter Test: Flows for a list of supported clock gating styles.
USER RESPONSE:
No response required if there are no clock gates present in the design or active in this
testmode.
INFO (TLP-649): There are no scan flops in this testmode that could possibly toggle during
the capture cycles. No effort will be made to identify and utilize clock gates to reduce capture
switching.
EXPLANATION:
This testmode does not contain any scan flops that could toggle during the capture cycle.
Therefore, capture switching analysis will not be performed.
USER RESPONSE:
No response required if this testmode is not supposed to contain any scan flops.
INFO (TLP-650): The following lineholds are being applied to avoid the use of apparent clock
gate overrides during ATPG. If this is not desired, specify holdcgoverrides=no:
EXPLANATION:
The latches/PIs identified appear to be clock gate overrides. Using them during ATPG
could make it impossible to achieve the desired maxcaptureswitching.
USER RESPONSE:
If lineholding the override latches/PIs is correct, no action is required. Otherwise, specify
holdcgoverrides=no and rerun ATPG using your own lineholds as necessary.

INFO (TLP-652): The following PIs/flops appear to be clock gate overrides. It may be
necessary to linehold one or more of them in order to achieve the desired capture switching:
EXPLANATION:
The PIs/flops identified appear to be clock gate overrides. Using them during ATPG
could make it impossible to achieve the desired maxcaptureswitching.
USER RESPONSE:
If ATPG is able to generate patterns, no action is required. If the requested capture
switching cannot be achieved, it may be necessary to linehold one or more if these flops/
PIs.
INFO (TLP-700): Common Power Format linter INFO message_text.

EXPLANATION:
This message reports any infornational messages related to the Conformal linters
parsing of the Common Power Format (CPF) file. Refer to the Conformal documentation
if help is required on the linter message ID referred to in this message.
USER RESPONSE:


50
TLS - Logic Model Smart Scan Messages
TLS-001 - TLS-050 on page 1557
TLS-001 - TLS-050
ERROR (TLS-001): [Internal] Internal Program Error occurred in file:'fileName'
line:linenumber. msgString
EXPLANATION:
Program Error.
USER RESPONSE:
ERROR (TLS-002): Failed to open file for reading :string. Check the access permissions
and path for this file.
EXPLANATION:
The application failed to open the specified file for reading. Check that the access
permissions are set correctly and the user has read permissions in the specified
directory.
USER RESPONSE:
Check the access permissions or specify a valid existing file.
ERROR (TLS-003): The smartscan description file name is not specified.
EXPLANATION:
The application failed to get the filename for the smartscan description file. Use keyword
smartscanfile to specify this file or set the enviornment variable TLS_smartscanfile with
a valid smartscan description file name .
USER RESPONSE:

Provide a valid existing smartscan description file.
INFO (TLS-004): Successfully opened file string for reading.

EXPLANATION:
The application has opened the specified file for reading.
USER RESPONSE:
ERROR (TLS-005): Unexpected statement string at file string line number .

EXPLANATION:
Unexpected statement at the specified line. Check for syntax errors in previous lines.
USER RESPONSE:
ERROR (TLS-006): [Syntax error]keyword string missing string. File string line
number.
EXPLANATION:
Syntax error at the specified line. Check the Encounter Test documentation for the
correct syntax.
USER RESPONSE:
ERROR (TLS-007): [Syntax error]: End of file reached, statement not yet complete. File
string line number.
EXPLANATION:
correct syntax.
USER RESPONSE:
ERROR (TLS-008): [Syntax error ]: string . File string line number .

EXPLANATION:

correct syntax.
USER RESPONSE:
ERROR (TLS-009): [Syntax error)]: missing keyword string . File string line
string.
EXPLANATION:
correct syntax.
USER RESPONSE:
ERROR (TLS-010): [Syntax error] missing string . File string line number .
EXPLANATION:
correct syntax.
USER RESPONSE:
ERROR (TLS-011): [Syntax error] Unexpected token string expected string. File
string line number.
EXPLANATION:
Unexpected statement at the specified line. Check for syntax errors in previous lines.
USER RESPONSE:
ERROR (TLS-012): Pin name string is not found in the design. File string line number.
EXPLANATION:
The specified pin name is not present in the Encounter Test database. Check if the
specified name is correct. If this is a pseudo pin, check if the editfile keyword is specified
with build_model and the correct editfile is provided.
USER RESPONSE:

Correct the error and rerun the command.
ERROR (TLS-013): Instance name string is not found in the design. File string line
number.
EXPLANATION:
The specified instance name is not present in the Encounter Test database. Check if the
specified name is correct.
USER RESPONSE:
ERROR (TLS-014): Pin string is already assigned to a smartscan register flop. File
string line number.
EXPLANATION:
The specified pin name is already assigned to a serializer or deserializer flop. The same
primary input/output pin cann't be assigned again to a smartscan register flop. The
smartscan register flop act as primary input/output for the rest of the design. There can't
be two or more flops for the same primary input/output pin.
USER RESPONSE:
Specify the correct primary pin name that maps to this flop and rerun the command.
ERROR (TLS-015): Duplicate entry for Instance name string . File string line number.
EXPLANATION:
The specified instance name is already specified in the smartscan description file. The
same instance name can't be assigned twice.
USER RESPONSE:
Correct the instance name for the smartscan register flop and rerun the command.
ERROR (TLS-016): Unexpected end of file reached, expecting '*/' . File string line
number.
EXPLANATION:
The block comment terminating character '*/' is not found in the file after the comment
the block comment begin character '/*'. These block comments characters must always
be specified in pairs.

USER RESPONSE:
Correct the syntax and rerun the command.
WARNING (TLS-017): [Severe] No path found from instance string bit_index=number

to primary pin string. Check if the names and bit_index value are specified correctly in the
smartscan description file.
EXPLANATION:
No path is found from the instance name to the specified pin name. Either the instance
name or the pin name are not correct or the bit_index value specified is incorrect. In case
all of them are correct check if the smartscan structures are correctly inserted.
USER RESPONSE:
WARNING (TLS-018): The command string is not a user executable. Use the help all
command to obtain a list of valid commands.
EXPLANATION:
The specified command is not provided as a user executable command and not
intentded for general use.
This is meant for internal validation and debug purpose.
USER RESPONSE:
Use the help all command to obtain a list of valid commands.
ERROR (TLS-019): Bit_Index=number for flop string specified in smartscan description file
is greater than the size of this register=number .
EXPLANATION:
The bit_index specifies the position of flop in the smart scan register and can't be greater
than the size of this register
USER RESPONSE:
Correct the bit_index and rerun the command.
ERROR (TLS-020): Invalid value for bit_index=number for flop string in smart scan
description file.
EXPLANATION:

The bit_index specifies the position of flop in the smart scan register. This should be a
positive value greater than zero and less than the size of this smartscan register.
USER RESPONSE:
Correct the bit_index and rerun the command.
ERROR (TLS-021): Duplicate value for bit_index=number for flop string in smart scan
description file.
EXPLANATION:
The bit_index specifies the position of flop in the smart scan register. This should be a
positive value greater than zero and less than the size of this smartscan register. The
same bit_index value should not be assigned to multiple flops of one smartscan register.
USER RESPONSE:
Correct the bit_index and re-run the command.
WARNING (TLS-022): [Severe] The specified sequence name string could not be
loaded. Check if the name is correct.
EXPLANATION:
The sequence with the name specified could not be loaded from the sequence definition
file. Make sure the sequence name specified is correct and the
read_sequence_definition command has been run for the specified sequence
definition file containing this sequence.
USER RESPONSE:
Correct the name and rerun the command.
INFO (TLS-023): Found path from instance string bit_index=number to pin string.
EXPLANATION:
As part of structural checks tracing is done to verify a path exists for the flops and the
pins specified in smart scan description file. This message indicates a path was found
between the specified instances or pins.
USER RESPONSE:
INFO (TLS-024): Exceeded the maximum number of nodes for tracing the path from string
to string

EXPLANATION:
pins specified in smart scan description file. This message indicates the instance/pin
name specified could not be reached and number of nodes traversed has exceeded the
maximum number of nodes expected to be traversed to reach the specified node.
USER RESPONSE:
WARNING (TLS-025): [Severe] No path found from instance string bit_index=number

to instance string bit_index=number. Check if the names and bit_index values are
specified correctly in the smartscan description file.
EXPLANATION:
No path is found between the specified instance names. Either the instance names are
not correct or the bit_index values specified may be incorrect. In case all of them are
correct check if the smartscan structures are correctly inserted.
USER RESPONSE:
INFO (TLS-026): Found path from instance string bit_index=number to instance

string bit_index=number.
EXPLANATION:
pins specified in smart scan description file. This message indicates a path was found
between the specified instances or pins.
USER RESPONSE:
WARNING (TLS-027): [Severe] The pin string is at value string for block string,
after simulating a pulse at the top level clock pin.
EXPLANATION:
The specified pin represents a control signal, which must be set for the serializer to act
as shift register. This pin is expected to be at logic one after simulating a pulse at the top
level pin
USER RESPONSE:

Check the pinassign file and the path from the top level clock pin to the input clock pin of
the specified block. The clock path should not be gated and a direct path should exist to
the input clock pin. Also check if the connections are done properly and the
smartscan_modeinit sequence in the sequence defination file sets the signals
correctly.
WARNING (TLS-028): [Severe] The input clock pin string for block string does not
get the clock pulse when simulating a pulse at the top level clock pin.
EXPLANATION:
The specified block is smartscan controller block and it expects to get the clock pulse
when the top level clock pin is pulsed. In case the clock path is gated and a direct path
does not exists to the input clock pin this warning is reported.
USER RESPONSE:
Clear the clock path to correct this error and rerun the command.
WARNING (TLS-029): [Severe] The pin string in the smartscan description file is
specified as string and has SMARTSCAN_PSEUDO_PIN attribute set.
EXPLANATION:
The SSI/SSO pins are the real pins contacted by the tester during test. The
SMARTSCAN_PSEUDO_PIN attribute indicates the pin is a pseudo pin created by
editmodel interface and will be removed by the write_vectors command. The pseudo
pins can't be a SSI/SSO pin.
USER RESPONSE:
Correct this error and rerun the command.
WARNING (TLS-030): [Severe] The primary pin string specified for deserializer flop
bit_index=number name=string are not equivalent. These two do not seem to feed the
same set of compression channels. Expected=string
EXPLANATION:
The smartscan description file specifies the deserializer/serializer flop instance, along
with the equivalent PSI/PSO pin names. The application verifies if both of these will feed
or get data from the same set of compression channels. This error indicates the data at
deserializer flop can't be loaded into the compression channels fed by the specified
parallel scan_in pin. The expected pin name is the name for the correct pin.
USER RESPONSE:

Check if the correct pin name is specified with correct flop instance and rerun the
command.
INFO (TLS-031): Verified equivalence for pin string with deserializer flop
bit_index=number name string .
EXPLANATION:
with the equivalent PSI/PSO pin names. Verification is done using structural tracing to
verify if both of these will feed into or get data from the same set of compression
channels. This message indicates the pin names are valid and equivalent.
USER RESPONSE:
WARNING (TLS-032): [Severe] The primary pin string specified for deserializer flop
bit_index=number name=string are not equivalent. The specified flop is connected to
CME pin internally whereas the specified primary pin is not connected to the same CME pin.
Expected=string
EXPLANATION:
with the equivalent PSI/PSO pin names. The application verifies if both of these are
equivalent, i.e. the specified flop will get the same data during serial interface as the
specified primary pin during parallel interface. This error indicates the data at deserializer
flop will be loaded into the CME pin internally and the specified primary pin is not
connected to the same internal CME pin. The expected pin name is the name for the
correct pin.
USER RESPONSE:
Check if the correct pin name is specified with correct flop instance and re-run the
command.
INFO (TLS-033): Verified equivalence for CME pin string with deserializer flop
bit_index=number name string.
EXPLANATION:
with the equivalent PSI/PSO pin names. The application verifies if both of these are
equivalent, i.e. the specified flop will get the same data during serial interface as the
specified primary pin during parallel interface. This message indicates the data at
deserializer flop will be loaded into the CME pin internally and the specified primary pin

is also connected to the same internal CME pin. This means the pin names are valid and
equivalent.
USER RESPONSE:
WARNING (TLS-034): [Severe] The primary pin string specified for serializer flop
bit_index=number name=string are not equivalent. These two do not seem to get data
from the same set of compression channels. Expected=string
EXPLANATION:
with the equivalent PSI/PSO pin names. The application verifies if both of these will feed
or get data from the same set of compression channels.
This error indicates, the data for the compression channels feeding into the specified
scan_out pin, cannot be unloaded from the specified serializer flop. The expected pin
name is the name for the correct pin.
USER RESPONSE:
Check if the correct pin name is specified with correct flop instance and re-run the
command.
INFO (TLS-035): Verified equivalence for pin string with serializer flop
bit_index=number name string .
EXPLANATION:
with the equivalent PSI/PSO pin names. Verification is done using structural tracing to
verify if both of these will feed into or get data from the same set of compression
channels. This message indicates the pin names are valid and equivalent.
USER RESPONSE:
ERROR (TLS-036): Syntax error: missing string. File string line number.
EXPLANATION:
correct syntax.
USER RESPONSE:

ERROR (TLS-037): Syntax error: missing keyword string. File string line number
number.
EXPLANATION:
correct syntax.
USER RESPONSE:
ERROR (TLS-038): Syntax error: string. File string line number number.
EXPLANATION:
correct syntax.
USER RESPONSE:
ERROR (TLS-039): Syntax error: Unrecognised token string. File string line number
number.
EXPLANATION:
correct syntax.
USER RESPONSE:
Correct the syntax errors and re-run the command.
ERROR (TLS-040): Pin name string is not found in the design. File string line
number.
EXPLANATION:
The specified pin name is not present in the Encounter Test database. Check if the
specified name is correct.
If this is a pseudo pin, check if the editfile keyword is specified with build_model
and the correct editfile is provided.
USER RESPONSE:

ERROR (TLS-041): The source pin string do not have test function flag set. File string
line number.
EXPLANATION:
The specified source pin do not have test function flag set. This flag should be one
among the following: SI, SO, CME.
USER RESPONSE:
ERROR (TLS-042): The source pin string is not SI, SO, CME. File string line
number.
EXPLANATION:
The specified source pin should be one among the following: SI, SO, CME.
USER RESPONSE:
ERROR (TLS-043): The correspondence pin string has attribute

MULTISCAN_PSEUDO_PIN set on it via the editfile. File string line number.
EXPLANATION:
The specified correspondence pin has attribute MULTISCAN_PSEUDO_PIN set on it via
the editfile. The correspondence pin must not have this attribute set on it.
USER RESPONSE:
ERROR (TLS-044): The end of file reached but end of section description is not found. File
string line number.
EXPLANATION:
The end of section description is not found.
USER RESPONSE:
WARNING (TLS-045): Pin string is already assigned to a smartscan register flop. File
string line number .

EXPLANATION:
The specified pin name is already assigned to a serializer or deserializer flop. The same
primary input/output pin should not be assigned again to a smartscan register flop.
However when CME pin fans out to multiple smartscan bits this warning can be ignored.
USER RESPONSE:
Ignore if same CME pin is fanning out to multiple smartscan bits, else specify the correct
primary pin name that maps to this flop and rerun the command.
WARNING (TLS-046): [Severe] The pin string in the smartscan description file is
specified as string, and the pin is also marked as CME pin. The CME pin is not supported
for SERIAL_SCAN_IN pin.
EXPLANATION:
The SERIAL_SCAN_IN(SSI) pins cannot be a CME pin. This is not supported and may
results in miscompares.
USER RESPONSE:
Correct this issue by specifying a non-CME pin as SSI pin and rerun the command.
WARNING (TLS-047): [Severe] Unable to run some of the checks for verifing the
equivalence of PSI/CME/PSO pins with the smartscan register flops. Make sure the mapping
specified in smartscan description file is correct.
EXPLANATION:
The check for verifying equivalence of PSO/PSI pins with the specified serializer/
deserializer flops are present in TLS. These checks prints messages TLS-030, TLS-032,
and TLS-034 severe warnings if it fails. However for these verifications, there is some
structural tracing that is done, which depends upon the internal structure of compression
macro. If the compression macro is not as expected, these checks can not be executed.
These checks are technically challenging and the current solution assumes a specific
structure inside the compression macro. If the compression macro is flattenned, it will not
be able to find these structures, and application will not be able to execute these checks,
since they can't be executed.
USER RESPONSE:
The compression macro should be same as inserted by RC, else these checks can't be
done by the application. Make sure the specified smartscan description file is correct.
WARNING (TLS-048): [Severe] Specified Block not found. Block name string is not
available in ET Model.

EXPLANATION:
The specified block name is not found in ET model.
USER RESPONSE:
Correct the name and rerun the application.
WARNING (TLS-049): [Severe] No pins found containing the specified name=string on

block string. Some of the verification checks cannot be done.
EXPLANATION:
The pin with name containing the specified name is not present on the block specified.
These names are needed to run verification checks for verifying equivalence of serializer/
desrializer nodes with the specified PSI/PSO pins. In the absence of these pins the
specified checks could not be run.
USER RESPONSE:
Correct the names and rerun the application.
ERROR (TLS-050): Invalid value number specified with keyword string . File string
line number.
EXPLANATION:
Syntax error at the specified line. The value specified is not a valid value for the keyword
mentioned.
USER RESPONSE:
Specify a valid value and rerun the command.

51
TMD - Manufacturing Release Data
Messages
TMD-001 through TMD-100 on page 1571
TMD-001 through TMD-100

WARNING (TMD-001): [Severe] Required Parameter parameter_name was not
provided. Add parameter to the command line and rerun.
EXPLANATION:
The build_manufacturing interface command requires the indicated parameter
value before it can proceed.
USER RESPONSE:
Provide this parameter name and value and rerun. Refer to
"build_manufacturing_interface" in the Encounter Test: Reference: Commands for
WARNING (TMD-002): [Severe] Name TMD_name of Encounter Test Manufacturing Data

is greater than 50 characters.
EXPLANATION:
At some point in the release process there is a limit of 50 characters for the length of the
TMD name. The program has noted that the referenced TMD name is longer than 50
characters.
USER RESPONSE:
Reduce the size of some field or fields in the referenced name.
WARNING (TMD-003): [Severe] Failed to open the LUF for reasons:

system_error_message

TMD - Manufacturing Release Data Messages
EXPLANATION:
The LUF generation program has requested that the LUF file be opened for writing. The
open was unsuccessful and the system has returned an error number. The error number
is used to extract the system error message and is delivered here as the reason for the
failure.
USER RESPONSE:
Correct the system errors. If the problems persist after correcting the system errors,
WARNING (TMD-004): [Severe] Failed to open the hierModel.

EXPLANATION:
The LUF generation program has asked that the hierModel be opened and has received
a return signal that says that the model is unavailable or nonexistent.
USER RESPONSE:
Ensure your command string is correctly specified and rerun. If running from the GUI,
then contact customer support (see Contacting Customer Service on page 23).
WARNING (TMD-005): [Severe] Aborting TMD generation - No LUF produced.

EXPLANATION:
The build_manufacturing_interface command received the signal that the
process was unsuccessful upon return from the LUF generation process. Therefore, the
run is being terminated without generating the TMD file. Additional messages are
produced that indicate the nature of the problem.
USER RESPONSE:
Review prior messages, resolve the indicated problems and then rerun. Contact
WARNING (TMD-006): [Severe] Failed to produce TMD file. Ref: System message for tar
and compress.
EXPLANATION:
To produce the TMD file, the program makes up a long system command consisting of a
tar command followed by a list of files to be placed in the tar file and then a pipe to
compress. This command is turned over to the operating system to be executed. There
is no return clue as to how well the operation performed, so a check for the existence of

the expected file is executed. If it is not found, it is assumed that the command failed, and
it is hoped that the system delivered some information.
USER RESPONSE:
If no helpful system information was produced, contact customer support (see
ERROR (TMD-007): Vectors files for mode modename is back-level. The TMD file is not
built.
EXPLANATION:
The program is checking to see that the Vectors are at 0401 or higher.
USER RESPONSE:
Build the Vectors at level 0401 or higher.
ERROR (TMD-008): Unrecognized keywords in the parameter list.

EXPLANATION:
A check of the keywords in the list provided to the program had a keyword that was
unexpected.
USER RESPONSE:
Remove the offending keyword
INFO (TMD-009): Both a tar file and a pax file have been called for. A tar is used.
EXPLANATION:
The -t flag is for a tar file. The -p flag is for a pax file. Both were given. The default is a
tar file, therefore a tar file will be used.
USER RESPONSE:
If pax is required, omit the -t flag and rerun.
INFO (TMD-010): parameter_name is defaulted to parameter_value.

EXPLANATION:
A value was not specified for the referenced parameter name. The default value is used.
USER RESPONSE:

If the default is not desired, specify the desired value for the referenced parameter and
rerun.
WARNING (TMD-011): [Severe] No test vectors exist for mode modename.

EXPLANATION:
There are no test vectors for this mode.
USER RESPONSE:
Verify whether test vectors are expected for the test mode. If test vectors are expected,
create them and then rerun build_manufacturing interface .
WARNING (TMD-012): [Severe] The checksum of this model was marked ERROR,
therefore, the UNLEV has been set to zero.
EXPLANATION:
This model was built from a VIM netlist. There was a CHECKSUM recorded at the top
level. When the Encounter Test model was built, the calculated CHECKSUM of the VIM did
not match the recorded CHECKSUM and therefore it was marked CHECKSUM=ERROR.
This indicates that the VIM was edited after it was created, which may mean there is a
mismatch between the Physical Design Model and the model used by Encounter Test.
There was a severe error message delivered at the time it was built.
Processing is allowed to continue for debug purposes.
USER RESPONSE:
Ensure no mismatch exists between the physical Design Model and the model used by
Encounter Test, resolve mismatches if they exist and then rerun.
INFO (TMD-020): Test Modes on testmodelist found valid.

EXPLANATION:
The program has validated the testmodelist specification..
USER RESPONSE:
ERROR (TMD-025): Test Modes on testmodelist not found.

EXPLANATION:
The program is unable to find the test modes specified by the testmodelist
specification..

USER RESPONSE:
Ensure the correct test modes are specified and rerun.
ERROR (TMD-026): Test modes not found - an incorrect spelling is assumed.

EXPLANATION:
Listed testmodes were requested on the TMD, but the testmodes were not found.
USER RESPONSE:
Correct the specification and rerun.
ERROR (TMD-030): The Parent mode parent_mode_name was not included with the
Child mode child_mode_name. Specify the parent mode with the testmodelist
keyword and rerun build_manufacturing_interface.
EXPLANATION:
If the Child mode is included in the testmodelist, then is it expected that the Parent
mode will also be included.
USER RESPONSE:
Include the parent mode in the testmodelist specification and rerun.
WARNING (TMD-031): [Severe] The comet comet_name is only partially included in the
testmodelist. Specify all testmodes included within the comet for the testmodelist
keyword and rerun build_manufacturing_interface.
EXPLANATION:
If any of the testmodes of the comet are included in the testmodelist, then all of
them must be included.
USER RESPONSE:
Specify all testmodes that comprise the comet for the testmodelist keyword and
rerun.
WARNING (TMD-032): No faultModel found - no fault data will be included on the TMD.
EXPLANATION:
A faultModel is expected In most cases, but not all cases.
USER REPSONSE:

If a faultModel is required, create one and then rerun

build_manufacturing_interface; otherwise, no response is required.
INFO (TMD-033): TestMode testmode not included was processed with Assumed
Scan - it is not included in the TMD.
EXPLANATION:
Currently, Assumed Scan modes are not transmitted.
USER RESPONSE:
No response is required if it is acceptable that the mode is exluded,; otherwise, reprocess
the mode without Assumed Scan and then rerun
build_manufacturing_interface.
WARNING (TMD-034): [Severe] TestMode testmode not included was processed

with Assumed Scan. It was also on the testmodelist to be transmitted, but it cannot be
included in the TMD.
EXPLANATION:
Currently, Assumed Scan modes are not transmitted.
USER RESPONSE:
No response is required if it is acceptable that the mode is exluded,; otherwise, reprocess
the mode without Assumed Scan and then rerun
ERROR (TMD-035): Error parsing arguments

EXPLANATION:
There was an error parsing the argument list.
USER RESPONSE:
Check for previous TFW error messages. Correct the arguments, and rerun. See
"extract_manufacturing_interface_files" in the Encounter Test: Reference:
Commands.
ERROR (TMD-036): TMD file TMD_file_name is neither compressed nor gzipped.

EXPLANATION:
The specified TMD file did not have a suffix of either .gz or .Z, so the
extract_manufacturing_interface_files process does not know how to read
the file.

USER RESPONSE:
Check to make sure that the TMD file is in fact a TMD file generated by Encounter Test.
ERROR (TMD-037): Unable to use working directory: Part_directory

EXPLANATION:
The working directory name is not one that either previously exists or can be created.
USER RESPONSE:
Check the values for WORKDIR to determine why the working directory is not available
to extract_manufacturing_interface_files.
ERROR (TMD-038): Unable to open TMD TMD_file_name

EXPLANATION:
The system was unable to uncompress and unpack the TMD file.
USER RESPONSE:
Check to make sure the TMD file is correct and complete.
INFO (TMD-039): Reading global data file to determine dependencies

EXPLANATION:
Progress message
USER RESPONSE:
INFO (TMD-040): Requested test modes: list_of_requested_test_modes

EXPLANATION:
Information only
USER RESPONSE:
INFO (TMD-041): Registered test modes: list_of_registered_test_modes

EXPLANATION:
Information only

USER RESPONSE:
WARNING (TMD-042): Requested test mode test_mode was not available in the TMD
and cannot be unloaded.
EXPLANATION:
The specified test mode was not found in the TMD.
USER RESPONSE:
Recreate the TMD If the test mode is required.
INFO (TMD-043): extract_manufacturing_interface_files complete

EXPLANATION:
TMD extract completed
USER RESPONSE:
WARNING (TMD-044): File fileName was not in the TMD.

EXPLANATION:
The specified file was registered as a dependency on a file that was extracted from the
TMD, but the file does not appear in the TMD itself.
USER RESPONSE:
In almost every case, no response is required. Most often, this occurs when the specified
file is derived from other files that can be extracted from the TMD, or which are not
required for Encounter Test processing.
INFO (TMD-045): Extracting fileName

EXPLANATION:
The specified file is required and exists on the TMD. The
extract_manufacturing_interface_files process is starting to read this file
from the TMD
USER RESPONSE:

ERROR (TMD-046): Unable to uncompress file fileName from TMD TMD Name to
Target Directory
EXPLANATION:
An error occurred trying to read the specified file from the specified TMD.
USER RESPONSE:
Try to determine why the file could not be extracted from the TMD.
ERROR (TMD-047): Unable to invoke the space management script Space Script
EXPLANATION:
An error occurred executing the specified space management script.
USER RESPONSE:
If the space management script is the Encounter Test default script (TFWpermSpace),
contact contact customer support (see Contacting Customer Service on page 23).
Otherwise, contact the individual who locally modified the space management script.
ERROR (TMD-048): System Error occurred in file:fileName line:NNN.

System error message: msgString
EXPLANATION:
A return code of -1 was returned from the system call and caused termination.
USER RESPONSE:
Review the system error and correct the problem. Rerun
build_maufacturing_interface to build the TMD.
WARNING (TMD-049): [Severe] Filename name is greater then 8Gb. pax does not handle
file sizes greater then 8Gb. The file will not be included on the TMD.
EXPLANATION:
The pax utility does not currently support files greater then 8Gb. The referenced file is
excluded from the TMD.
USER RESPONSE:
Use gzip to compress the referenced file and then rerun

WARNING (TMD-050): [Severe] Filename name is greater then 8GB. Not all versions of
tar handle filesizes greater then 8GB. The file will not be included on the TMD. If you need
to include this file on the TMD you must ensured that GNU tar version 1.14 or later has been
installed in your environment. Add posix=yes to your
build_manufacturing_interface command line and rerun.
EXPLANATION:
build_manufacturing_interface support for 8GB and larger files requires that
posix=yes be added to your build_manufacturing_interface command line.
posix=yes was not found on the build_manufacturing_interface command
line.
USER RESPONSE:
Only GNU tar versions 1.14 and later support file sizes greater then 8GB. If GNU tar
version 1.14 or later has been installed in your environment add posix=yes to your
build_manufacturing_interface command line and rerun. If GNU tar version
1.14 or higher is has been installed add posix=yes to
build_manufacturing_interface commandline and rerun.
ERROR (TMD-051): System Error occurred while attempting to build your TMD. On your
command line you specified posix=yes. Not all versions of tar support the posix format.
This is the likely cause of the system call failure. If none of your input files are greater than
8GB, remove the posix keyword from your command line and rerun. If support for greater
then 8GB files is needed you must ensure that you have GNU tar 1.14 or later installed in your
environment before rerunning.
EXPLANATION:
posix=yes was found the build_manufacturing_interface command line. Only
GNU tar versions 1.14 and later support the posix format. If GNU tar version 1.14 or later
is not installed in your environment the system call to tar and gzip your data will fail.
USER RESPONSE:
From your system prompt enter tar --version. If GNU tar version 1.14 or later has not
been installed, and support for 8GB or greater files is needed, ensure that GNU tar 1.14
or later is installed before rerunning. If you don't need 8GB file support remove
posix=yes from your build_manufacturing_interface command line and rerun.
INFO (TMD-052): Including VCHAIN data for testmode testmode.

EXPLANATION:

vchain data was requested for this testmode. scanDiagBoundInfo and

scanDiagPatternList files are registered for this testmode and will be written to the
TMD.
USER RESPONSE:
None required.
WARNING (TMD-053): VCHAIN data is registered for testmode testmode but one or both
of the data files appears to have been removed.
EXPLANATION:
vchain data files scanDiagBoundInfo and scanDiagPatternList files are
registered for this testmode. One or both are missing.
USER RESPONSE:
If files are required recreate these files and rerun
WARNING (TMD-054): This part contains cores and coremigrationpath has not been
specified. The LUF file being created will not contain the LUF content from the cores.
EXPLANATION:
Passing the coremigrationpath keyword into
build_manufacturing_interface allows the concatination of the core level LUF
files at the chip level.
USER RESPONSE:
Correct the missing keyword and re-run build_manufacturing_interface.
WARNING (TMD-055): The Core corename has not been run through the core migration
process and does not exist in the coremigrationpath specified.
EXPLANATION:
build_manufacturing_interface was not able to locate a core directory for one of
the cores on this chip.
USER RESPONSE:
Validate this core has been properly migrated to the chip level and re-run

WARNING (TMD-056): The Core corename does not contain a LUF file in the
keywordoption specified.
EXPLANATION:
build_manufacturing_interface was not able to locate a LUF file within the core
migration directory.
USER RESPONSE:
build_manufacturing_interface needs to be executed on the Core, execute for
the Core and then re-run build_manufacturing_interface for the Chip.
WARNING (TMD-057): [Severe] The symbolicly linked file, filename, does not exist at
the linked path.
EXPLANATION:
build_manufacturing_interface attempted to copy the symbolicly linked file from the core
migration directory but the path to the file has been changed.
USER RESPONSE:
update the linkage to the files in the core migration tbdata directory that was created by
prepare_core_migration_diagnostics
INFO (TMD-100): Parameters:

EXPLANATION:
The currently invoked parameters/values are listed.
USER RESPONSE:

52
TMI - Verify Macro Isolation Messages
TMI-001 through TMI-050 on page 1583

TMI-001 through TMI-050

WARNING (TMI-001): [Severe] The verify_macro_isolation function,
function_Name, could not find file file_Name.
EXPLANATION:
verify_macro_isolation attempted to open the file listed but the file does not exist.
USER RESPONSE:
Ensure the file exists and rerun verify_macro_isolation.

function_Name, could not write data to the file, file_Name.
EXPLANATION:
verify_macro_isolation attempted to write to the file listed but was unsuccessful.
USER RESPONSE:

Determine the reason (check things such as permission bits and file space, and ensure
the file name spelling is correct), and rerun verify_macro_isolation.

function_Name, could not read data from the file, file_Name.
EXPLANATION:
verify_macro_isolation attempted to read from the file listed but was
unsuccessful.
USER RESPONSE:
Ensure that the file exists and that the permission bits are set correctly, and rerun
verify_macro_isolation.

function_Name, could not close the file, file_Name.
EXPLANATION:
verify_macro_isolation was unable to close the file listed.
USER RESPONSE:
Ensure that the file exists and that the permission bits are set correctly, and rerun
WARNING (TMI-005): [Severe] The file, file_Name, has a file ID of file_ID1 in the file
header. The file ID should be file_ID2 in order to run this version of
verify_macro_isolation. Rerun verify_macro_isolation with append=no.
EXPLANATION:
verify_macro_isolation was unable to verify the file header for the filename listed.
The file was created with an old level of verify_macro_isolation and cannot be
processed by the current level.
USER RESPONSE:
Rerun with the current level of verify_macro_isolation.
WARNING (TMI-006): [Severe] An invalid block name block_name was received for
macro block index block_index. Protected macro blocks cannot be processed by
EXPLANATION:

verify_macro_isolation is unable to process macro blocks that have the

PROTECT module attribute.
USER RESPONSE:
Do not run verify_macro_isolation on parts that contain protected macro blocks.
INFO (TMI-007): Attribute attribute_Name on block block_Name is invalid.

EXPLANATION:
The value specified for the attribute is invalid. If the attribute name is MACRO, this block
will not be considered an embedded macro. If any other attributes are specified for this
block, the attribute value will be ignored by verify_macro_isolation
USER RESPONSE:
Correct the attribute value in the design source, and reprocess the part beginning with
the IMPORT step.
INFO (TMI-008): There are no macros for this test mode.

EXPLANATION:
verify_macro_isolation did not find any block with the MACRO attribute with a
value of YES or TDM. It will not process any embedded macros for this test mode.
USER RESPONSE:
If no macros are to be processed, no further actions are required. If there are macros to
be processed, put macro attributes on them and reprocess the circuit.
INFO (TMI-009): MACRO attribute specified, but no MACRO_MIC_NAME for block

block_Name. A default operation containing all pins on the block will be created.
EXPLANATION:
When the MACRO attribute has a value of YES or TDM and the MACRO_MIC_NAME is
not present, verify_macro_isolation attempts to find isolation for a default
operation containing all macro input and output pins.
USER RESPONSE:
If the default operation is desired, no further actions are required. If specific operations
are required and a MIC (Macro Isolation Control) file exists describing the operations,
add the MACRO_MIC_NAME attribute for the block to the part design source.
INFO (TMI-010): Processing MIC file file_Name.

EXPLANATION:
This indicates that verify_macro_isolation is beginning to process the specified
MIC.
USER RESPONSE:
WARNING (TMI-011): [Severe] Unexpected End of File while processing MIC file.
EXPLANATION:
An EOF was detected before processing of a MIC statement or keyword was completed.
USER RESPONSE:
Correct the MIC file for errors such as a missing comma, semicolon, or misspelled
keyword. The specific message can be selected from the Verify Core Isolation Specific
Message List. An editor, specified by environment variable TB_EDITOR, is invoked and
starts an edit session for the incorrect MIC.
Refer to "Macro Isolation Control (MIC) File Reference" in the Encounter Test: Guide
3: Test Structures for additional information.
WARNING (TMI-012): [Severe] MIC syntax error at line line_number.

EXPLANATION:
A syntax error was encountered while processing the MIC file at the line number listed in
the message. Processing terminates.
USER RESPONSE:
The specific message can be selected from the Verify Core Isolation Specific Message
List. An editor, specified by environment variable TB_EDITOR, is invoked and starts an
edit session for the incorrect MIC. Correct the MIC file for errors such as a missing
comma, semicolon, or misspelled keyword.
WARNING (TMI-013): [Severe] MIC lines line_number to line_number have been

discarded due to syntax error.
EXPLANATION:

A syntax error from a previous line has caused the lines in the range listed of the MIC file
to be invalid. Processing continues with the next valid MIC statement.
USER RESPONSE:
edit session for the incorrect MIC. Refer to message TMI-012 for the line number that has
the syntax error. Correct the MIC file and rerun verify_macro_isolation. Refer to
"Macro Isolation Control (MIC) File Reference" in the Encounter Test: Guide 3: Test
Structures for additional information.
WARNING (TMI-014):[Severe] Range specification range1:range2 at line line_number

is incorrect. The lengths of the two ranges are not equal.
EXPLANATION:
When a range of pins or nets is specified in an INNER_NETS, OPERATION, or a
PINGROUP statement, the range bound specifications must be equal. For example,
XYZ000:XYZ10 is invalid (first range bound specification is 6 characters, the second is 5
characters). This pin (or net) range is not processed. Processing continues.
USER RESPONSE:
Find the invalid range bound specification using the line number given and have it
corrected by the MIC file developer. The specific message can be selected from the
Verify Core Isolation Specific Message List. An editor, specified by environment variable
TB_EDITOR, is invoked and starts an edit session for the incorrect MIC. Refer to "Macro
Isolation Control (MIC) File Reference" in the Encounter Test: Guide 3: Test
WARNING (TMI-015): [Severe] Range specification

range_boundary1:range_boundary2 at line line_number is incorrect. The
numeric range exceeds 10,000.
EXPLANATION:
When a range of pins or nets is specified in an INNER_NETS, OPERATION, or a
PINGROUP statement, the range is limited to 10,000 pins or nets. This pin (or net) range
is not processed. Processing continues.
USER RESPONSE:
Find the invalid range specification using the line number given and have it corrected by
the MIC file developer. The specific message can be selected from the Verify Core
Isolation Specific Message List. An editor, specified by environment variable

WARNING (TMI-016): [Severe] Range specification

range_boundary1:range_boundary2 at line Line Number is incorrect. The range
specifications are not matching character types.
EXPLANATION:
When a range of pins or nets is specified in an INNER_NETS or PINGROUP statement,
the range specifications must have matching character types. For example,
AB1X0:AB119 is invalid because X and 1 are not matching character types (alpha vs.
numeric). This pin (or net) range is not processed. Processing continues.
USER RESPONSE:
Find the invalid range specification using the line number given and have it corrected by
the MIC file developer. The specific message can be selected from the Verify Core
Isolation Specific Message List. An editor, specified by environment variable
WARNING (TMI-018): [Severe] The MIC file, file_NameA, dated dateA, is different
from the MIC file, file_NameB, dated dateB.
EXPLANATION:
The existing isolation created from a previous invocation of
verify_macro_isolation using the first MIC file listed is different from the isolation
created from the second MIC file. This is caused by a difference in the MIC files used for
each run.
USER RESPONSE:
Verify the MICPATH is correct. If you wish to rerun using a new MIC file, specify the
append=no option or deselect the Append to existing uncommitted option on the Macro
Structure Verification window. Refer to "Macro Isolation Control (MIC) File Reference" in
the Encounter Test: Guide 3: Test Structures for additional information.
WARNING (TMI-019): [Severe] Attempt to register MacroIsolationbin file file_Name on

EXPLANATION:
The MacroIsolationbin file could not be registered on the globalData file for this test
mode.

USER RESPONSE:
WARNING (TMI-020): [Severe] Attempt to save MacroIsolationbin file file_Name in the

globalData file failed.
EXPLANATION:
The MacroIsolationbin file statistics could not be saved in the globalData file for this test
mode.
USER RESPONSE:
Determine why the file statistics could not be saved.
WARNING (TMI-023): [Severe] MACRO_CORR_n attribute is specified incorrectly on pin

pin_Name.
EXPLANATION:
The MACRO_CORR_n attribute must be specified as follows:
MACRO_CORR_n=MIC=micname,ALGORITHM=algname,PIN=pinname.
Where:
n is an integer
micname is the Macro Isolation Control (MIC) file which this attribute applies to
algname is the Algorithm within the identified MIC file which this attribute
applies to
pinname is the simple name of the macro pin to which this attribute applies
The attribute was not specified correctly. This pin will not become a required
correspondence point. Processing continues.
USER RESPONSE:
Correct the specification of the attribute and rerun verify_macro_isolation.
The specific message can be selected from the Specific Message List. The pin is
displayed with the TI/TIE state applied.
WARNING (TMI-024): [Severe] MACRO_CORR_n attribute is specified on pin

pin_Name. This pin does not met the controllability or observability requirements of the
macro pin as specified by the keyword=value pairs of the attribute.

EXPLANATION:
This pin (identified in the message) will not be used as a correspondence point for the
macro pin as specified by the keyword=value pairs of the attribute. The pin cannot be
used because of one of the following conditions:
The designated macro pin is an input pin and the attribute is specified on a latch
which is not controllable.
The designated macro pin is an output pin and the attribute is specified on a
latch which is not observable.
The attribute is specified on a product pin which is not contacted by the tester.
The attribute is ignored and processing continues.
USER RESPONSE:
If the attribute was automatically inserted by Cadence Test Synthesis, contact
If this attribute was manually coded remove it.
The specific message can be selected from the Specific Message List. The pin is
displayed with the TI/TIE state applied. |*
INFO (TMI-025): Number of macros to be processed during this run: number_macros.

EXPLANATION:
This message specifies the number of macros to be processed for this
verify_macro_isolation run.
USER RESPONSE:
WARNING (TMI-026): [Severe] verify_macro_isolation was run previously with a

different setting of the command line option runforsignoff. Rerun
verify_macro_isolation with append=no or change the command line option of
runforsignoff to match the prior run.
EXPLANATION:
verify_macro_isolation cannot append results when the command line option
runforsignoff is changed in a subsequent run. verify_macro_isolation has
detected an attempt to append the results of a run which was performed with one setting
of runforsignoff to this run which has a different setting.

USER RESPONSE:
Rerun with append=no or change runforsignoff to match the prior run.
WARNING (TMI-030): [Severe] Inner net name net_Name is tied to the wrong value
value1. The MIC requires a value of value2. No isolation data will be generated for
operation operation_Name.
EXPLANATION:
This inner net is not valid since it connects to a TIE block which does not have the same
value that is required on the inner net as specified in the MIC. No isolation is generated
for this operation. Processing continues.
USER RESPONSE:
Either the MIC was coded incorrectly or the logic design within the macro is not in sync
with the MIC. Verify the MIC and/or the macro logic design before attempting to solve this
operation. The specific message can be selected from the Verify Core Isolation Specific
Message List. The invalid net is displayed with the TI/TIE state applied. Refer to "Macro
WARNING (TMI-031): [Severe] Inner net name net_Name is a non-sourced (tied) net. No
isolation data will be generated for operation operation_Name.
EXPLANATION:
This inner net is not valid since it does not trace back to a controllable or observable
latch, or a product pin. No isolation is generated for this operation. Processing continues.
USER RESPONSE:
operation. The specific message can be selected from Verify Core Isolation Specific
WARNING (TMI-032): [Severe] Inner net name net_Name is a multi-sourced (dotted) net.
No isolation data will be generated for operation operation_Name.
EXPLANATION:
This inner net is not valid since it traces back to more than one source pin. This may
cause verify_macro_isolation to choose the wrong correspondence point. No
isolation is generated for this operation. Processing continues.

USER RESPONSE:
WARNING (TMI-033): [Severe] No source found for inner net name net_Name. No
isolation data will be generated for operation operation_Name.
EXPLANATION:
A source pin for the inner net could not be located. No isolation is generated for this
operation. Processing continues.
USER RESPONSE:
operation. If the logic design is suspected of being incorrect, the specific
message can be selected from the Verify Core Isolation Specific Message List. The
invalid net is displayed with the TI/TIE state applied. Trace back on the net to determine
why is has no source. Refer to "Macro Isolation Control (MIC) File Reference" in the
WARNING (TMI-035): [Severe] Unable to find the macro block name, block_Name. No
processing will be done on this block.
EXPLANATION:
The macro block listed in the message was specified in the macro=option as a macro
block to be processed by verify_macro_isolation. This block either does not exist
in the model or the block is not identified as a macro. Processing continues.
USER RESPONSE:
Determine why the macro block does not exist in this model. You may have mis-spelled
or mis-typed the block name, or are using the wrong model.
If the block exists in the model, it must have a MACRO attribute of YES or TDM to indicate
that the hierarchical block represents an embedded macro or core.
If the macro block has a specified MACRO_TYPE, the specified type must be found in
the MIC file specified for the macro. Correct the block name or the block macro properties
in the input source, recreate the logic model, and rerun verify_macro_isolation.

INFO (TMI-036): Macro block blockName will not be processed. It does not meet the MIC
criteria for processing.
EXPLANATION:
The macro block listed in the message was specified in the macro= option or the
excludemacro= option of the verify_macro_isolation command line. The
properties for this block do not meet the criteria specified in the MIC for processing.
USER RESPONSE:
Check the specification of the macro for spelling or typing errors. If the block exists in the
model, it must have a MACRO attribute of YES or TDM to indicate that the hierarchical block
represents an embedded macro or core. If the macro block has a specified
MACRO_TYPE, the specified type must be found in the MIC file specified for the macro.
Correct the block name or the block macro properties in the input source, recreate the
logic model, and rerun verify_macro_isolation.
INFO (TMI-037): The file, file_Name, is not registered in globalData and therefore cannot
be accessed. It will be created during this verify_macro_isolation run.
EXPLANATION:
The specified file is not registered. The file will be created during this run and
verify_macro_isolation processing continues. This may occur if the
verify_macro_isolation append option was set to yes but the MacroIsolation does
not exist.
USER RESPONSE:
ERROR (TMI-038): [Internal] The modal filename for the file file_Name could not be
constructed.
EXPLANATION:
The file name could not be determined.t
USER RESPONSE:
WARNING (TMI-039): [Severe] The file, file_Name, is not writeable, therefore the
results of this verify_macro_isolation run cannot be saved.
EXPLANATION:

The permission bits for the file are not set to "write".
USER RESPONSE:
The file owner must have the appropriate permission bits set to make the file writeable.
WARNING (TMI-040): [Severe] The file, file_Name, is not readable, therefore the results
of this verify_macro_isolation run cannot be saved.
EXPLANATION:
The permission bits for the file are not set to "read".
USER RESPONSE:
The file owner must have the appropriate permission bits set to make the file readable.
ERROR (TMI-041): [Internal] The master filename for the file file_Name could not be
constructed.
EXPLANATION:
The file name could not be determined.t
USER RESPONSE:
WARNING (TMI-042): [Severe] The directory, directory_Name, is not writeable,

therefore the results of this verify_macro_isolation run cannot be saved.
EXPLANATION:
The permission bits for the directory are not set to "write".
USER RESPONSE:
The directory owner must have the appropriate permission bits set to make the file
writeable.
WARNING (TMI-043): [Severe] The directory, directory_Name, is not readable,

therefore the results of this verify_macro_isolation run cannot be saved.
EXPLANATION:
The permission bits for the directory are not set to "read".
USER RESPONSE:

readable.
ERROR (TMI-044): [Internal] The directory could not be constructed using

PROJECT=project, ENTITY=entity.
EXPLANATION:
The directory name could not be determined.t
USER RESPONSE:
WARNING (TMI-045): Stable pin pin_Name is not a macro input pin, but was specified as
a STABLE pin in the MIC. The pin will not be considered a stable pin.
EXPLANATION:
The MIC STABLE statement describes the "stable" or "quiescent" state for a macro. Each
specified pin must be a macro input pin. The pin is ignored. Processing continues.
USER RESPONSE:
Ensure the MIC STABLE statement specifies only macro input pins. The specific
message can be selected from the Verify Core Isolation Specific Message List. The
invalid pin is displayed with the TI/TIE state applied.
WARNING (TMI-047): [Severe] Attempt to register a dependency of experiment|file

against the mode|experiment on the globalData file failed.
EXPLANATION:
The reason for the failure cannot be determined by verify_macro_isolation.
USER RESPONSE:
corrective action.
WARNING (TMI-050): STATIC MACRO, DYNAMIC MACRO, or DYNAMIC TIMED MACRO

test type is not defined for mode test_mode.
One of these test types must be defined if MTG is to be run on this experiment.
EXPLANATION:

The mode definition file used to define the test mode does not specify STATIC MACRO,
DYNAMIC MACRO, or DYNAMIC TIMED MACRO in the TEST_TYPE statement. This is
required if macro test patterns are to be generated by the MTG application using the
isolation data from this verify_macro_isolation run.
USER RESPONSE:
Verify the Mode Definition path and filename for the mode is correct and that the
appropriate test type is defined in the Mode Definition file TEST_TYPE statement.

WARNING (TMI-051): [Severe] Test mode test_mode is IEEE 1149.1, which is not
processed by verify_macro_isolation.
EXPLANATION:
verify_macro_isolation does not process an IEEE 1149.1 test mode. Processing
terminates.
USER RESPONSE:
Do not attempt to run verify_macro_isolation for IEEE 1149.1 test modes.
WARNING (TMI-052): [Severe] Test mode test_mode is Scan to MISR, which is not
processed by verify_macro_isolation.
EXPLANATION:
verify_macro_isolation does not process a Scan to MISR test mode. Processing
terminates.
USER RESPONSE:
Do not attempt to run verify_macro_isolation for Scan to MISR test modes.
WARNING (TMI-053): [Severe] Test mode test_mode contains internal clock domains.
This test mode cannot be processed by verify_macro_isolation.
EXPLANATION:
verify_macro_isolation does not process test modes which have internal clock
domains. Processing terminates.
USER RESPONSE:
Do not run verify_macro_isolation for test modes with internal clock domains.

WARNING (TMI-054): [Severe] Pin/Net pin_name on macro block_name in algorithm

alg_name, operation oper_name has no source or sink. This operation will not be solved.
EXPLANATION:
The pin or inner-net does not have a source or sink identified in the model.
USER RESPONSE:
Change the model to connect the pin/net.
WARNING (TMI-055): [Severe] Command line parameter macrotype must be specified

when performing test data macro for macros (cores) and the MIC file contains two algorithms.
EXPLANATION:
When a test data macro type test mode (test_types td_macro in the mode definition file)
is processed by verify_macro_isolation and two algorithms are present in the
Macro Isolation Control (MIC) file the desired test (algorithm) must be specified by the
macrotype keyword of the command line. The current test mode had a test type of
td_macro specified and there were two algorithms in the MIC but the macrotype keyword
was not specified on the command line. Processing continues.
USER RESPONSE:
Specify the appropriate macrotype on the command line and rerun.
WARNING (TMI-056): Pin/Net pin_name does not exist on macro block_name in

Algorithm alg_name, Operation oper_name.
EXPLANATION:
The pin or inner-net in the MIC does not exist on the macro for this Algorithm and
Operation.
USER RESPONSE:
Check the pin/net name in the MIC for spelling. If you do not wish to see this type of
warning, turn the option off.
WARNING (TMI-057): [Severe] Required Pin/Net pin_name does not exist on macro
block_name in Algorithm alg_name, Operation oper_name.
EXPLANATION:
The required pin or inner-net in the MIC does not exist on the macro for this Algorithm
and Operation.
USER RESPONSE:

Check the pin/net name in the MIC for spelling. If you do not wish to see this type of
warning, turn the option off.
WARNING (TMI-060): [Severe] The Stable net name, net_Name, on block block_Name
is a multi-sourced (dotted) net. The Stable net will not be used.
EXPLANATION:
The Stable net is not valid since it traces back to more than one source pin. This may
cause verify_macro_isolation to choose the wrong correspondence point. The
Stable net is ignored. Processing continues.
USER RESPONSE:
Verify the MIC and/or the logic design. If the Stable net in the MIC is correct, the specific
message can be selected from the.
The net is displayed with the TI/TIE state applied. Trace back on the net to determine why
it has more than one source.
Change the design so that the net traces back to only one source. If the Stable net is
incorrect, correct the MIC and rerun verify_macro_isolation.
WARNING (TMI-061): [Severe] The Stable net name, net_name, on block block_Name
is a non-sourced (tied) net. The Stable net will not be used.
EXPLANATION:
The Stable net is not valid since it does not trace back to a controllable or observable
latch, or product pin. The Stable net is ignored. Processing continues.
USER RESPONSE:
Verify the MIC and/or the logic design. If the Stable net is correct, the specific message
can be selected from Verify Core Isolation Specific Message List. The net is displayed
with the TI/TIE state applied. Trace back on the net to determine why it is tied. Change
the design so that the net traces back to a controllable or observable pin. If the Stable
net is incorrect, correct the MIC and rerun verify_macro_isolation. Refer to
WARNING (TMI-062): [Severe] The Stable net name, net_Name, on block block_Name
has no source pin. The Stable net will not be used.
EXPLANATION:

The Stable net is not valid since it does not trace back to a controllable or observable
latch, or product pin. The Stable net is ignored. Processing continues.
USER RESPONSE:
Verify the MIC and/or the logic design. If the Stable net is correct, the specific message
can be selected from the verify_macro_isolation Specific Message List. The net
is displayed with the TI/TIE state applied. Trace back on the net to determine why it has
no source pin.
Change the design so that the net traces back to a controllable or observable pin. If the
Stable net is incorrect, correct the MIC and rerun verify_macro_isolation. Refer
to "Macro Isolation Control (MIC) File Reference" in the Encounter Test: Guide 3: Test
WARNING (TMI-068): [Severe] Macro macro_name does not meet the MIN_PINS
requirement for ALGORITHM alg_name, OPERATION oper_name, PINGROUP
pin_group_name.
EXPLANATION:
The specified macro is required to have certain pins designated for correspondence
based on the pin names in MIN_PINS keyword in the MIC file. This macro does not meet
these requirements. Processing continues.
USER RESPONSE:
Ensure that at least one set of pins designated in the MIN_PINS keyword for the pin
group provided exists on the macro. Also ensure that the required pins have not been
dropped during MIC processing. Change the design or MIC so at least one set of pins
from the MIN_PINS keyword exists and rerun verify_macro_isolation.
WARNING (TMI-080): More than one MIC Definition Statement found in file.
EXPLANATION:
Multiple MIC_DEF statements were specified in the MIC. The MIC_DEF statement is an
optional statement that identifies date and time information. Processing continues.
USER RESPONSE:
edit session for the incorrect MIC. Correct the MIC file. It should contain only one
MIC_DEF statement. Refer to "Macro Isolation Control (MIC) File Reference" in the

WARNING (TMI-081): More than one Macro Definition Statement found in the User Control
file.
EXPLANATION:
Multiple MUCDEF statements were specified in the User Control (UC) file. The MUCDEF
statement is an optional statement that identifies date and time information. Processing
continues.
USER RESPONSE:
edit session for the incorrect UC file. Correct the UC file. It should contain only one
MUCDEF statement. Refer to "User Control File" in the Encounter Test: Guide 3: Test
INFO (TMI-082): Processing Macro User Control (UC) file file_Name.

EXPLANATION:
verify_macro_isolation is processing the specified User Control file. Processing
continues.
USER RESPONSE:
WARNING (TMI-083): [Severe] An ALGORITHM statement was used before a MACRO

statement.
EXPLANATION:
The ALGORITHM statement is a list of algorithm names that apply to a particular macro.
Therefore, a MACRO statement must be specified before the ALGORITHM statement.
The ALGORITHM and all other control statements that follow (until a MACRO statement
is encountered) are not processed. Processing continues.
USER RESPONSE:
edit session for the incorrect UC file. Add a MACRO statement so that it precedes the
ALGORITHM statement, or check for a MACRO statement syntax error if one does
precede the ALGORITHM statement.

WARNING (TMI-084): [Severe] An OPERATION statement was used before an

ALGORITHM statement.
EXPLANATION:
The OPERATION statement is a list of operation names that apply to a particular
algorithm. Therefore, an ALGORITHM statement must be specified before the
OPERATION statement. The OPERATION and all other control statements that follow
(until an ALGORITHM statement is encountered) are not processed. Processing
continues.
USER RESPONSE:
edit session for the incorrect UC file. Add an ALGORITHM statement so that it precedes
the OPERATION statement, or check for an ALGORITHM statement syntax error if one
does precede the OPERATION statement.
WARNING (TMI-085): [Severe] A CORRESPONDENCE statement was used before a

MACRO statement.
EXPLANATION:
The CORRESPONDENCE statement is a list of macro pins and the desired
correspondence point for a particular macro. Therefore, a MACRO statement must be
specified before the CORRESPONDENCE statement. The CORRESPONDENCE
statement is not processed. Processing continues.
USER RESPONSE:
edit session for the incorrect UC file. Add a MACRO statement so that it precedes the
CORRESPONDENCE statement, or check for a MACRO statement syntax error if one
does precede the CORRESPONDENCE statement.
Refer to "CORRESPONDENCE Statement" in the Encounter Test: Guide 3: Test
WARNING (TMI-086): [Severe] Unexpected End of File while processing Macro UC file.
EXPLANATION:

An EOF was detected before processing of a UC statement or keyword was completed.

UC file processing terminates. verify_macro_isolation processing continues.
Unexpected results may occur as the UC file was not completely processed.
USER RESPONSE:
edit session for the incorrect UC file. Correct the UC file.
WARNING (TMI-087): [Severe] Macro UC file syntax error at line line_number.

EXPLANATION:
A syntax error was encountered while processing the UC file at the line number listed in
the message. verify_macro_isolation processing continues. Unexpected results
may occur as the UC file was not completely processed due to syntax error(s).
USER RESPONSE:
edit session for the incorrect UC file. Correct the UC file. Refer to
"verify_macro_isolation User Control Files" in the Encounter Test: Guide 3:
Test Structures for additional information.
WARNING (TMI-088): [Severe] Macro UC lines line_number1 to line_number2

have been discarded due to syntax error.
EXPLANATION:
A syntax error from a previous line has caused the lines in the range listed to be invalid.
Processing continues with the next valid statement in the UC file.
verify_macro_isolation processing continues. Unexpected results may occur as
the UC file was not completely processed due to syntax error(s).
USER RESPONSE:
edit session for the incorrect UC file. Correct the UC file. Refer to "verify_macro_isolation
User Control Files" in the Encounter Test: Guide 3: Test Structures for additional
information.


WARNING (TMI-101): ALGORITHM statement has no name specified in the NAME
keyword. This statement is discarded.
EXPLANATION:
The ALGORITHM statement identifies the macro test algorithm file required to test this
macro. The MIC contains an ALGORITHM statement that has no name. A name must
be specified for each ALGORITHM statement. Processing continues.
USER RESPONSE:
edit session for the incorrect MIC file. Correct the ALGORITHM statement in the MIC file.
Refer to "Macro Isolation Control (MIC) File Reference" in the Encounter Test: Guide 3:
WARNING (TMI-102): ALGORITHM statement Algorithm_Statement_Name has no

operation(s) specified in the OPERATIONS keyword.
EXPLANATION:
The OPERATIONS keyword identifies the operations used by this algorithm. The MIC
contains an ALGORITHM statement that has no operations specified. At least one
operation must be specified in an ALGORITHM statement. Processing continues.
USER RESPONSE:
edit session for the incorrect MIC file. Correct the ALGORITHM statement named in the
message. Refer to "Macro Isolation Control (MIC) File Reference" in the Encounter
Test: Guide 3: Test Structures for additional information.
WARNING (TMI-103): ALGORITHM statement Algorithm_Statement_Name has

duplicate operation names specified in the OPERATIONS keyword. The duplicate operation,
operationName, is ignored.
EXPLANATION:
An ALGORITHM statement has the same operation name specified two or more times
in the OPERATIONS keyword. The first occurrence is processed and the duplicate is
USER RESPONSE:

edit session for the incorrect MIC file. Remove or rename the duplicate operation(s) in
the ALGORITHM statement. Refer to "Macro Isolation Control (MIC) File Reference" in
WARNING (TMI-104): INNER_NETS statement has no name specified in the NAME

EXPLANATION:
The INNER_NETS statement identifies (by virtual net name) nets inside the macro that
are required for an operation.
Operations reference these pins via the name specified in the NO_DISTURB or
PINGROUPS keywords. A name must be specified for each INNER_NETS statement so
that it can be referenced by an operation. Processing continues.
USER RESPONSE:
edit session for the incorrect MIC file. Correct the INNER_NETS statement in the MIC
file. Refer to "Macro Isolation Control (MIC) File Reference" in the Encounter Test:
Guide 3: Test Structures for additional information.
WARNING (TMI-105): INNER_NETS statement Inner_Net_Statement_Name has no

net(s) specified.
EXPLANATION:
The MIC contains an INNER_NETS statement that has no nets specified. At least one
net must be specified in an INNER_NETS statement. Processing continues.
USER RESPONSE:
edit session for the incorrect MIC file. Correct the INNER_NETS statement named in the
WARNING (TMI-106): INNER_NETS statement Inner_Net_Statement_Name has

duplicate net names specified. The duplicate net, net_Name, is ignored.
EXPLANATION:

An INNER_NETS statement has the same net name specified two or more times in the
NETS keyword. The first occurrence is processed and the duplicate is ignored.
USER RESPONSE:
List. An editor, specified
by environment variable TB_EDITOR, is invoked and starts an edit session for the
incorrect MIC file. Remove or rename the
duplicate net(s) in the INNER_NETS statement. Refer to "Macro Isolation Control (MIC)
File Reference" in the Encounter Test: Guide 3: Test Structures for additional
information.
WARNING (TMI-107): PINGROUP statement has no name specified in the NAME keyword.
This statement is discarded.
EXPLANATION:
The PINGROUP statement identifies a group of pins that may be used for an operation.
Operations reference these pins via the name specified in the PINGROUPS keyword. A
name must be specified for each PINGROUP statement so that it can be referenced by
an operation. Processing continues.
USER RESPONSE:
edit session for the incorrect MIC file. Correct the PINGROUP statement in the MIC file.
WARNING (TMI-108): PINGROUP statement Pin_Group_Statement_Name has no

pin(s) specified in the PINS keyword.
EXPLANATION:
The MIC contains a PINGROUP statement that has no pins specified. At least one pin
must be specified in a PINGROUP statement. Processing continues.
USER RESPONSE:
edit session for the incorrect MIC file. Correct the PINGROUP statement named in the

WARNING (TMI-109): PINGROUP statement Pin Group Statement_Name has duplicate

pin names specified in the PINS keyword. The duplicate pin, pin_Name, is ignored.
EXPLANATION:
A PINGROUP statement has the same pin name specified two or more times in the PINS
keyword. The first occurrence is processed and the duplicate is ignored. Processing
continues.
USER RESPONSE:
edit session for the incorrect MIC file. Remove or rename the duplicate pin(s) in the
PINGROUP statement. Refer to "Macro Isolation Control (MIC) File Reference" in the
WARNING (TMI-110): OPERATION statement has no name specified in the NAME

EXPLANATION:
The OPERATION statement identifies the name of an operation used by test algorithms.
The algorithms reference these operations via the name specified in the OPERATIONS
keyword. A name must be specified for each OPERATION statement so that it can be
referenced by an algorithm. Processing continues.
USER RESPONSE:
edit session for the incorrect MIC file. Correct the OPERATION statement in the MIC file.
WARNING (TMI-111): OPERATION statement Operation_Statement_Name has

duplicate pin group names specified in the PINGROUPS keyword. The duplicate pin group,
Pin_Group_Name, is ignored.
EXPLANATION:
An OPERATION statement has the same pin group name specified two or more times in
the PINGROUPS keyword. The first occurrence is processed and the duplicate is

USER RESPONSE:
edit session for the incorrect MIC file. Remove or rename the duplicate pingroup(s) in the
OPERATION statement. Refer to "Macro Isolation Control (MIC) File Reference" in the

duplicate inner net names specified in the NO_DISTURB keyword. The duplicate inner net,
Inner_Net_Name, is ignored.
EXPLANATION:
An OPERATION statement has the same inner net name specified two or more times in
the NO_DISTURB keyword. The first occurrence is processed and the duplicate is
USER RESPONSE:
edit session for the incorrect MIC file. Remove or rename the duplicate inner net(s) in the
WARNING (TMI-113): OPERATION statement Operation_Statement_Name has the

same name, Pin_Group_Name, specified in both the NO_DISTURB keyword and the
PINGROUPS keyword. The PINGROUPS entry is ignored.
EXPLANATION:
An OPERATION statement has the same name specified for both a NO_DISTURB and
a PINGROUP entry. These names should be unique since they represent two different
groups of pins. Processing continues.
USER RESPONSE:
edit session for the incorrect MIC file. Remove or rename the PINGROUP entry in the
WARNING (TMI-114): OPERATION statement Operation_Statement_Name has no

pins specified in the PINS keyword.

EXPLANATION:
The PINS keyword identifies macro pins required for an operation. At least one pin must
be specified for this keyword. Processing continues.
USER RESPONSE:
edit session for the incorrect MIC file. Correct the OPERATION statement named in the

duplicate pins specified in the PINS keyword. The duplicate pin, pin_Name, is ignored.
EXPLANATION:
An OPERATION statement has the same pin name specified two or more times in the
PINS keyword. The first occurrence is processed and the duplicate is ignored.
USER RESPONSE:
edit session for the incorrect MIC file. Remove or rename the duplicate pin(s) in the
WARNING (TMI-116): [Severe] This MIC file has no ALGORITHM statements. There must
be at least one ALGORITHM statement in the MIC.
EXPLANATION:
The ALGORITHM statement identifies the name of a macro test algorithm file required
to test a macro. There must be at least one ALGORITHM statement in a MIC file.
USER RESPONSE:
edit session for the incorrect MIC file. Correct the MIC file and rerun. Refer to "Macro

WARNING (TMI-117): ALGORITHM statement Algorithm_Statement_Name is the

same name as a previous ALGORITHM statement. This algorithm statement is ignored.
EXPLANATION:
If the MIC file contains multiple ALGORITHM statements, the names specified in the
NAME= keywords must be unique. Processing continues.
USER RESPONSE:
edit session for the incorrect MIC file. If the MIC requires multiple ALGORITHM
statements, rename the statements so that each algorithm statement has a unique
name. Refer to "Macro Isolation Control (MIC) File Reference" in the Encounter Test:
WARNING (TMI-118): ALGORITHM statement Algorithm_Statement_Name has an

operation specified which has no corresponding OPERATION statement in the MIC. The
operation name is operation_Name.
EXPLANATION:
The algorithm statement has an operation specified in the OPERATIONS keyword but
this operation does not exist in this MIC. There must be a matching OPERATION
statement for every operation listed in the algorithm statement(s). Processing continues.
USER RESPONSE:
edit session for the incorrect MIC file. Ensure the MIC has a valid operation statement for
every operation used by the algorithm statement(s). Refer to "Macro Isolation Control
(MIC) File Reference" in the Encounter Test: Guide 3: Test Structures for additional
information.
WARNING (TMI-119): INNER_NETS statement Inner_Nets_Statement_Name is the

same name as a previous INNER_NETS statement. This inner nets statement is ignored.
EXPLANATION:
If the MIC file contains multiple INNER_NETS statements, the names specified in the
NAME= keywords must be unique for each statement. Processing continues.
USER RESPONSE:
The specific message can be selected from the "Verify Core Isolation Specific Message
List". An editor, specified by environment variable TB_EDITOR, is invoked and starts an

edit session for the incorrect MIC file. Rename the INNER_NETS statement(s) so that
each inner net statement has a unique name. Also ensure that any operation statement
using this inner nets statement has the correct name in the NO_DISTURB or
PINGROUPS keyword. Refer to "Macro Isolation Control (MIC) File Reference" in the
INFO (TMI-120): INNER_NETS statement Inner_Nets_Statement_Name has been

specified which is not used in any OPERATION statement in the MIC.
EXPLANATION:
This inner nets statement name is not specified in any operation statement
NO_DISTURB or PINGROUPS keywords. Processing continues.
USER RESPONSE:
edit session for the incorrect MIC file. If the inner nets are not required for any operation,
remove this INNER_NETS statement from the MIC. If the inner nets are required for an
operation, ensure that the name specified in operation NO_DISTURB or PINGROUPS
keywords matches the INNER_NETS statement name. Refer to "Macro Isolation Control
information.
WARNING (TMI-121): PINGROUP statement Pin_Group_Statement_Name is the

same name as a previous PINGROUP statement. This pin group statement is ignored.
EXPLANATION:
If the MIC file contains multiple PINGROUP statements, the names specified in the
NAME= keyword for each statement must be unique. Processing continues.
USER RESPONSE:
edit session for the incorrect MIC file. Rename the PINGROUP statement(s) so that each
pin group statement has a unique name. Also ensure that any operation statement using
this pin group statement has the correct name in the PINGROUPS keyword. Refer to
INFO (TMI-122): PINGROUP statement Pin_Group_Statement_Name has been

specified which is not used in any OPERATION statement.
EXPLANATION:

This pin group statement name is not specified in any operation statement PINGROUPS
keyword. Processing continues.
USER RESPONSE:
edit session for the incorrect MIC file. If this pin group is not required for any operation,
remove this PINGROUP statement from the MIC. If this pin group is required for an
operation, ensure that the name specified in the operation PINGROUPS keyword
matches the PINGROUP statement name. Refer to "Macro Isolation Control (MIC) File
Reference" in the Encounter Test: Guide 3: Test Structures for additional
information.
WARNING (TMI-123): OPERATION statement Operation_Statement_Name is the

same name as a previous OPERATION statement. This operation statement is ignored.
EXPLANATION:
If the MIC file contains multiple OPERATION statements, the names specified in the
NAME keywords must be unique for each statement. Processing continues.
USER RESPONSE:
edit session for the incorrect MIC file. Rename the OPERATION statement(s) so that
each operation statement has a unique name. Also ensure that any algorithm statement
using this operation statement has the correct name in the OPERATIONS keyword.
INFO (TMI-124): OPERATION statement Operation_Statement_Name has been

specified which is not used in an ALGORITHM statement.
EXPLANATION:
This operation statement name is not specified in any algorithm statement
OPERATIONS keyword. Processing continues.
USER RESPONSE:
edit session for the incorrect MIC file. If this operation is not required for any algorithm,
remove this OPERATION statement from the MIC. If this operation is required for an
algorithm, ensure that the name specified in the algorithm OPERATIONS keyword

matches the OPERATION statement name. Refer to "Macro Isolation Control (MIC) File
Reference" in the Encounter Test: Guide 3: Test Structures for additional
information.
WARNING (TMI-125): [Severe] OPERATION statement

Operation_Statement_Name references a pin group, Pin_Group_Name, which has
no corresponding PINGROUP or INNER_NETS statement in the MIC.
EXPLANATION:
The operation requires pins (via the PINGROUPS keyword) but neither a PINGROUP
nor an INNER_NETS statement exists on the MIC which matches the name listed in the
operation statement PINGROUPS keyword. Processing terminates for this operation.
USER RESPONSE:
edit session for the incorrect MIC file. Correct the MIC so that the operation statement
PINGROUPS keyword references a PINGROUP or INNER_NETS statement that exists
in the MIC file and rerun verify_macro_isolation. Refer to "Macro Isolation Control
information.
WARNING (TMI-126): [Severe] PINGROUP statement

Pin_Group_Statement_Name, which contains a MIN_PINS keyword, has the same
name as a previous PINGROUP statement. This PINGROUP statement with MIN_PINS
keyword is ignored.
EXPLANATION:
If the MIC file contains multiple PINGROUP statements, the names specified in the
NAME= keyword for each statement must be unique. This particular PINGROUP
statement contains the MIN_PINS keyword which will be deleted. Processing continues.
USER RESPONSE:
Select the specific message from the Verify Core Isolation Specific Message List. An
editor, specified by environment variable TB_EDITOR, is invoked and starts an edit
session for the incorrect MIC file. Rename the PINGROUP statement(s) so that each
PINGROUP statement has a unique name. Also ensure that any operation statement
using this PINGROUP statement has the correct name in the PINGROUPS keyword.
WARNING (TMI-127): [Severe] OPERATION operation_Name has no pins or nets

specified via the PINGROUPS or NO_DISTURB keywords.

EXPLANATION:
This operation has no pins or nets. This problem could be caused by one of the following:
The operation statement has no inner nets or pin groups specified.
The INNER_NETS or PINGROUP statements used by this operation are
invalid.
If this operation does not use inner nets and pin groups, it must have pins specified via
the PINS keyword. Processing terminates for this operation.
USER RESPONSE:
edit session for the incorrect MIC file. If the operation uses inner nets and/or pin groups,
ensure the inner net and pin group statements are valid. (Messages TMI-105 and TMI-
108 indicate invalid inner net and pin group statements). Correct the inner net and/or pin
groups statement(s) and rerun verify_macro_isolation.
If the operation does not use inner nets and pin groups, no pins were specified (message
TMI-114 indicates this). Correct the OPERATION statement and rerun
verify_macro_isolation. Refer to "Macro Isolation Control (MIC) File Reference"
in the Encounter Test: Guide 3: Test Structures for additional information.
WARNING (TMI-128): [Severe] The pin name pin_Name appears used in more than one
PINGROUP used by OPERATION Operation_Statement_Name. This pin is ignored.
EXPLANATION:
A pin name appears in more than one PINGROUP used by this operation. Processing
continues.
USER RESPONSE:
edit session for the incorrect MIC file. Identify two or more PINGROUPS used by this
operation that specify the pin. Correct the MIC and rerun. Refer to "Macro Isolation
Control (MIC) File Reference" in the Encounter Test: Guide 3: Test Structures for
WARNING (TMI-129): MIC error. Innernet, net_Name, in Innernet Inner_Net_Name. A

net with a required value cannot be shared. The SHARE specification is ignored.
EXPLANATION:

The SHARE=yes option is used to allow macro innernets to share a common

correspondence point. If the net is required to be at a value (the value being a 0 or 1),
the share option has no meaning since the value is obtained via preconditioning and is
therefore not a net which requires correspondence. The SHARE=yes option is ignored.
USER RESPONSE:
Verify the net is correctly coded in the INNER_NETS statement. If it is correctly coded to
require a 0 or 1 value, remove the SHARE option. (Leaving SHARE in does not affect the
isolation solution, but removing it will make this message go away.)
WARNING (TMI-130): [Severe] The net name net_Name appears in more than one
INNER_NETS statement used by operation Operation_Statement_Name. This net is
ignored.
EXPLANATION:
The same net name has been specified on different INNER_NETS statements used by
the operation. The duplicate net is ignored. Processing continues.
USER RESPONSE:
edit session for the incorrect MIC file. Verify the operation is using the correct
INNER_NETS and that each INNER_NETS statement has the correct net names
specified. If the same nets are required for each INNER_NETS statement, ignore this
WARNING (TMI-131): INNER_NETS statement Inner_Nets_Statement_Name has

duplicate prefix names specified. The duplicate prefix, prefix_Name, is ignored.
EXPLANATION:
The same prefix name has been specified on different INNER_NETS statements used
by the operation. The duplicate prefix is ignored. Processing continues.
USER RESPONSE:
edit session for the incorrect MIC file. Verify the operation is using the correct
INNER_NETS and that each INNER_NETS statement has the correct prefix names

specified. If the same prefixes are required for each INNER_NETS statement, ignore this
WARNING (TMI-132): [Severe] The PINGROUP statement with name

Pin_Group_Name has the MIN_PINS pin name pin_name specified which does not exist
in the pin group. This may cause the MIN_PINS check to fail.
EXPLANATION:
The pin names specified in the MIN_PINS keyword section must also be specified in the
PINS keyword section of the PINGROUP statement. Processing continues.
USER RESPONSE:
Check for misspelling of any pin names in the PINGROUP statement. Add the MIN_PINS
pin name to the PIN keyword section or remove it from the MIN_PINS keyword section.
Rerun verify_macro_isolation.
WARNING (TMI-133): [Severe] A MIN_PINS syntax error occurred at line line_Number.

The keyword is discarded.
EXPLANATION:
A syntax error was encountered while processing the MIN_PINS keyword in the MIC file
at the line number listed in the message. Processing continues.
USER RESPONSE:
session for the incorrect MIC. Check the MIC file for errors such as a misplaced or
missing comma, semicolon, or misspelled pin name. Refer to "Macro Isolation Control
information.
WARNING (TMI-134): Test function specified is invalid for test mode that uses scan type =
none. OPERATION (or PINGROUP) statement name = Operation (or Pin Group) Statement
Name, PIN name = Pin Name.
EXPLANATION:
The TEST_FUNCTION keyword indicates the type of PI correspondence that is required
for a macro input pin. The only test function type that is valid for scan type=NONE is
SYSTEM_CLOCK. The TEST_FUNCTION specification is ignored. Processing
continues.
USER RESPONSE:

edit session for the incorrect MIC file. Verify the correct test mode was used. If the test
mode with scan type = NONE is correct, remove the TEST_FUNCTION specification
from the pin or change it to SYSTEM_CLOCK. Refer to "Macro Isolation Control (MIC)
File Reference" in the Encounter Test: Guide 3: Test Structures for additional
information.
WARNING (TMI-135): ALGORITHM statement Algorithm_Statement_Name has

duplicate test function names specified in the TEST_FUNCTION keyword. The duplicate test
function, Test_Function_Name, is ignored.
EXPLANATION:
An ALGORITHM statement has the test function name specified two or more times in the
TEST_FUNCTION keyword. The first occurrence is processed and the duplicate is
USER RESPONSE:
edit session for the incorrect MIC file. Remove or rename the duplicate test function(s) in
the ALGORITHM statement Refer to "Macro Isolation Control (MIC) File Reference" in

MPR name specified. This algorithm cannot be processed when running MTG.
EXPLANATION:
The MIC contains an ALGORITHM statement that does not have the MPR_NAME
keyword specified. The MPR_NAME keyword specifies the name Macro Pattern Rule
(MPR) that contains a description of the test algorithm used by MTG to generate macro
test patterns. Processing continues.
USER RESPONSE:
edit session for the incorrect MIC file. If test patterns are to be created for this algorithm
using the MTG function, the MPR name must be identified in the MPR_NAME keyword.
If you are not creating macro test patterns, this message can be ignored. (You can
prevent message from printing by coding MPR_NAME=none in the ALGORITHM
statement.) Refer to "Macro Isolation Control (MIC) File Reference" in the Encounter

WARNING (TMI-137): STABLE statement has a duplicate pin name. The duplicate pin,
pin_Name, is ignored.
EXPLANATION:
The MIC STABLE statement has the same pin specified two or more times in the PINS
keyword. The first occurrence is processed and the duplicate is ignored. Processing
continues.
USER RESPONSE:
edit session for the incorrect MIC file. Remove the duplicate pin(s) in the STABLE
statement. Refer to "Macro Isolation Control (MIC) File Reference" in the Encounter

group attribute(s) specified in the GROUP_ATTRIBUTES keyword.
EXPLANATION:
The MIC contains an ALGORITHM statement that does not have the required
GROUP_ATTRIBUTES keyword specified.
The GROUP_ATTRIBUTES keyword identifies the macro attributes to be used for
determining the grouping of an algorithm used by two or more macros. This
ALGORITHM statement is ignored. Processing continues.
USER RESPONSE:
edit session for the incorrect MIC file. Ensure a GROUP_ATTRIBUTES keyword is
specified for all algorithm statements in the MIC. If macro attributes are not used for
grouping criteria, specify GROUP_ATTRIBUTES=none. Refer to "Macro Isolation Control
information.
WARNING (TMI-141): The Stable Net name, net_Name, does not appear in any
INNER_NETS statement. The Stable Net is discarded.
EXPLANATION:
Each stable net named in the MIC STABLE statement must also exist in an
INNER_NETS statement.
USER RESPONSE:

edit session for the incorrect MIC file. Ensure that all stable nets named in the STABLE
statement exist in an INNER_NETS statement that has net_type=input specified.
WARNING (TMI-142): STABLE statement has a duplicate net name. The duplicate net,
net_Name, is ignored.
EXPLANATION:
Duplicate net names are not allowed in a STABLE statement. Processing continues.
USER RESPONSE:
edit session for the incorrect MIC file. Correct the duplicate net name condition and rerun
WARNING (TMI-143): MIC error, Pin pin_Name in pingroup Pin_Group_Name. A pin

with a required value cannot be shared. The SHARE specification is ignored.
EXPLANATION:
The SHARE=yes option is used to allow macro pins to share a common correspondence
point. If the pin is required to be at a value (the value being a 0 or 1), the share option
has no meaning since the value is obtained via preconditioning and is therefore not a pin
which requires correspondence. The SHARE=yes option is ignored. Processing
continues.
USER RESPONSE:
edit session for the incorrect MIC file. Verify the pin is correctly coded in the PINGROUP
statement. If it is correctly coded to require a 0 or 1 value, remove the SHARE option.
(Leaving SHARE in does not affect the isolation solution, but removing it will make this
message go away.) Refer to "Macro Isolation Control (MIC) File Reference" in the
INFO (TMI-144): MIC error, PINGROUP statement Pin_Group_Statement_Name.

Dpo, pre_dpo, or post_dpo values are invalid for pingroups with
corresp_type=Corresp_Type. The pingroup must have corresp_type=pipo. These values
are ignored.

EXPLANATION:
Dynamic pattern ordering of pins is supported only for macro pins which correspond to
primary input or output pins. Therefore the PINGROUP statement must have
CORRESP_TYPE=pipo specified.
USER RESPONSE:
edit session for the incorrect MIC file. Correct the PINGROUP statement and rerun
INFO (TMI-145): Operation operation_Name, pin pin_Name has no dpo value.

EXPLANATION:
This pingroup is used for an operation which has timing=repetitive specified but no
dpo value has been specified for the pin. Each pin requiring correspondence must have
a dpo value.
USER RESPONSE:
INFO (TMI-146): Operation operation_Name is specified to be timed in a repetitive

manner but pin pin_Name has a PRE_DPO/POST_DPO value specified.
EXPLANATION:
This pingroup is used for an operation which has timing=repetitive specified but a
pre_dpo or post_dpo value has been specified for the pin. These keywords are valid
only for timing=non_repetitive operations.
USER RESPONSE:

INFO (TMI-147): Operation operation name is specified to be timed in a non-repetitive

manner but pin pin_Name has neither a PRE_DPO, POST_DPO, nor DPO value specified.
EXPLANATION:
This pingroup is used for an operation which has timing=non_repetitive specified
but no dpo, pre_dpo, or post_dpo value has been specified for the pin. Each pin
requiring correspondence must have one of these event ordering keywords specified.
USER RESPONSE:
INFO (TMI-148): A PRE_DPO or POST_DPO value was specified on the same pin that has
a DPO value specified. Operation operation_Name, pin pin_Name.
EXPLANATION:
Only one event ordering keyword (dpo, pre_dpo, or post_dpo) is allowed for a pin.
USER RESPONSE:
INFO (TMI-149): A DPO or POST_DPO value was specified on the same pin that has a
PRE_DPO value specified. Operation operation_Name, pin pin_Name.
EXPLANATION:
Only one event ordering keyword (dpo, pre_dpo, or post_dpo) is allowed for a pin.
USER RESPONSE:

WARNING (TMI-150): MIC error. Operation operation_Name must have at least two
pins with unique Dynamic Pattern Order (DPO) values specified.
EXPLANATION:
For an operation to be timed, there must be two events generated in the dynamic test
pattern. This is accomplished with the unique dpos specified on 2 or more
correspondence pins.
USER RESPONSE:
The specific message can be selected from the "Verify Core Isolation Specific Message
List". An editor, specified by environment variable TB_EDITOR, is invoked and starts an

WARNING (TMI-151): User Control MACRO statement, macro name macro_Name was
not found. The statement is discarded.
EXPLANATION:
The macro named in the message does not exist in the model. Processing continues.
USER RESPONSE:
edit session for the incorrect UC file. Correct the MACRO statement in the UC file. Refer
to "verify_macro_isolation User Control Files" in the Encounter Test: Guide 3: Test
WARNING (TMI-152): User Control ALGORITHM statement, macro name macro_Name,

algorithm name algorithm_Name was not found. The statement is discarded.
EXPLANATION:
The MIC file specified in the macros MACRO_MIC_NAME attribute does not have an
algorithm statement which matches the algorithm named in the message. Processing
continues.
USER RESPONSE:

edit session for the incorrect UC file. Correct the ALGORITHM statement in the UC file.
3: Test Structures and verify_macro_isolation User Control Files" in the
WARNING (TMI-153): User Control OPERATION statement, macro name macro_Name,

algorithm name algorithm_Name, operation name operation_Name was not found.
The statement is discarded.
EXPLANATION:
The MIC file specified in the macros MACRO_MIC_NAME attribute does not have the
operation named in the message that matches any operation name specified for the
algorithm named in the message. Processing continues.
USER RESPONSE:
edit session for the incorrect UC file. Correct the OPERATION statement in the UC file.
3: Test Structures and verify_macro_isolation User Control Files" in the
WARNING (TMI-154): User Control CORRESPONDENCE statement, macro pin name

pin_Name has no entity specified. The statement is discarded.
EXPLANATION:
No correspondence point (either a primary I/O or a latch) was specified for the macro pin
named in the message. Processing continues.
USER RESPONSE:
edit session for the incorrect UC file. Correct the CORRESPONDENCE statement in the
UC file. Refer to "Macro Isolation Control (MIC) File Reference" in the Encounter Test:
Guide 3: Test Structures and verify_macro_isolation User Control Files" in the
WARNING (TMI-155): User Control CORRESPONDENCE statement, duplicate macro pin

name pin_Name specified. The duplicate macro pin name is discarded.
EXPLANATION:

The same macro pin was listed more than once in the correspondence statement.
USER RESPONSE:
WARNING (TMI-157): User Control CORRESPONDENCE statement, invalid macro pin

name pin_Name specified for macro macro_Name. The statement is discarded.
EXPLANATION:
The macro pin does not exist on the macro named in the message. Processing
continues.
USER RESPONSE:
WARNING (TMI-159): User Control CORRESPONDENCE statement, invalid workdir

specified for macro pin pin_Name. The statement is discarded.
EXPLANATION:
The pin entity (desired correspondence point) specified for the macro pin named in the
message does not exist in the model. Processing continues.
USER RESPONSE:
UC file. Refer to "Macro Isolation Control (MIC) File Reference" in the Encounter
Test: Guide 3: Test Structures and verify_macro_isolation User
Control Files" in the Encounter Test: Guide 3: Test Structures for additional
information.

WARNING (TMI-160): User Control CORRESPONDENCE statement, invalid pin function

for entity entity, macro pin pin_Name specified. Entity function must be a PI, PO, or latch.
The statement is discarded.
EXPLANATION:
The entity (desired correspondence point) specified for the macro pin named in the
message is not a primary I/O or a latch. Processing continues.
USER RESPONSE:

for entity entity, macro pin pin_Name specified. Entity cannot be a latch if latch names
are present. The statement is discarded.
EXPLANATION:
The entity (desired correspondence point) specified for the macro pin named in the
message specifies latches in the correspondence path. When this is the case, the entity
must be primary input or output pin. Processing continues.
USER RESPONSE:
Correct the CORRESPONDENCE statement in the UC file. Refer to "Macro Isolation
Control (MIC) File Reference" in the Encounter Test: Guide 3: Test Structures and
WARNING (TMI-162): User Control CORRESPONDENCE statement, invalid block name

block_Name specified for macro pin pin_Name. The statement is discarded.
EXPLANATION:
The block entity specified for the macro pin named in the message does not exist in the
model. Processing continues.
USER RESPONSE:

Guide 3: Test Structures and "verify_macro_isolation User Control Files" in
WARNING (TMI-163): User Control CORRESPONDENCE statement, invalid number of

latches for entity entity, macro pin pin_Name specified. A maximum of 4 latches are
allowed for double latch design. The statement is discarded.
EXPLANATION:
The primary I/O pin entity for the macro pin named in the message has more than four
latches specified in the desired through latch correspondence path. Processing
continues.
USER RESPONSE:
UC file. If necessary, change the logic surrounding the array to conform with the
restriction. Refer to "Macro Isolation Control (MIC) File Reference" in the Encounter
Test: Guide 3: Test Structures and "verify_macro_isolation User Control
Files" in the Encounter Test: Guide 3: Test Structures for additional information.
WARNING (TMI-164): User Control CORRESPONDENCE statement, invalid latch name

entity specified for macro pin pin_Name. The statement is discarded.
EXPLANATION:
The primary I/O pin entity for the macro pin named in the message has latches specified
for a through latch correspondence path, but the latch name does not exist in the model.
USER RESPONSE:
Guide 3: Test Structures and "verify_macro_isolation User Control Files" in the

for entity entity, macro pin pin_Name specified. Entity must be a latch. The statement is
discarded
EXPLANATION:

The primary I/O pin entity for the macro pin named in the message has latch names
specified for a through latch correspondence path, but the entity is not a latch output pin.
USER RESPONSE:
Correct the CORRESPONDENCE statement in the UC file. Refer to "Macro Isolation
Control (MIC) File Reference" in the Encounter Test: Guide 3: Test Structures and
Test Structures additional information.
WARNING (TMI-166): User Control HOLD statement, invalid pin function for entity entity.
Must be a PI, latch, or common IO. The statement is discarded.
EXPLANATION:
The specified entity in the HOLD statement is not a primary input or latch. Processing
continues.
USER RESPONSE:
Correct the HOLD statement in the UC file.
WARNING (TMI-167): User Control statement statement, has duplicate name name.
The duplicate name is ignored.
EXPLANATION:
The User Control statement listed in the message has the same name specified two or
more times. Processing continues.
USER RESPONSE:
edit session for the incorrect UC file. Correct the statement in the UC file. Refer to "Macro
Structures and "verify_macro_isolation User Control Files" in the Encounter
WARNING (TMI-170): [Severe] User Control GROUP statement, algorithm name

Group_Name has no macros specified. The statement is discarded.
EXPLANATION:
The GROUP statement specifies an algorithm name, but no macros are listed that are
desired to be grouped together for this verify_macro_isolation run. Processing
continues.

USER RESPONSE:
edit session for the incorrect UC file. Correct the GROUP statement in the UC file. Refer
to "Macro Isolation Control (MIC) File Reference" in the Encounter Test: Guide 3: Test
Structures and "verify_macro_isolation User Control Files" in the Encounter
WARNING (TMI-172): [Severe] User Control GROUP statement has macro name
macro_Name specified for algorithm name algorithm_Name, but the macro does not
exist. The statement is discarded.
EXPLANATION:
The macro named in the message does not exist in the model. Processing continues.
USER RESPONSE:
edit session for the incorrect UC file. Correct the GROUP statement in the UC file. Refer
to "Macro Isolation Control (MIC) File Reference" and "verify_macro_isolation
User Control Files" in the Encounter Test: Guide 3: Test Structures for additional
information.
WARNING (TMI-174): [Severe] User Control GROUP statement has macro name
macro_Name specified for algorithm name algorithm_Name, but the MIC did not specify
this algorithm for the macro. The statement is discarded.
EXPLANATION:
The MIC file specified in the macros MACRO_MIC_NAME attribute does not have an
algorithm statement which matches the algorithm named in the message. Processing
continues.
USER RESPONSE:
Determine if the ALGORITHM statement is missing from the MIC for this macro or if the
UC file GROUP statement has an invalid algorithm name specified. If the UC file is
incorrect, the specific message can be selected from the Verify Core Isolation Specific
Message List. An editor, specified by environment variable TB_EDITOR, is invoked and
starts an edit session for the incorrect UC file. Correct the invalid GROUP statement. If
the MIC is incorrect, add the missing ALGORITHM for the macro. Refer to "Macro
Isolation Control (MIC) File Reference" and "verify_macro_isolation User Control
Files" in the Encounter Test: Guide 3: Test Structures for additional information.

WARNING (TMI-175): [Severe] User Control GROUP statement for algorithm

algorithm_Name is not permitted by the MIC ALGORITHM statement for grouping. Either
the MIC must be changed to allow grouping, or do not attempt to group for this algorithm. The
GROUP statement is discarded.
EXPLANATION:
The algorithm statement named in the message is coded in the MIC with keyword
GROUP=no specified. This means that macros using this algorithm will not be grouped.
Including this algorithm in a User Control GROUP statement is invalid. Processing
continues.
USER RESPONSE:
If the UC file GROUP statement has an incorrect algorithm name, select the specific
message from the Verify Core Isolation Specific Message List. An editor, specified by
environment variable TB_EDITOR, is invoked and starts an edit session for the incorrect
UC file. Correct the invalid GROUP statement. Correct the MIC ALGORITHM statement
if it is incorrect. Refer to "Macro Isolation Control (MIC) File Reference"
verify_macro_isolation User Control Files" in the Encounter Test: Guide 3:
WARNING (TMI-176): [Severe] Macro named macro_Name specified in User Control

GROUP statement used MIC MIC_NameA, but should use MIC MIC_NameB to be grouped
with the macros in this GROUP statement. All macros in a GROUP statement must use the
same MIC. The statement is discarded.
EXPLANATION:
The macro named in the message has a different MIC specified in the macro's
MACRO_MIC_NAME attribute than the other macros listed in the User Control file
GROUP statement. All macros in a group must the same MIC. Processing continues.
USER RESPONSE:
Determine if the GROUP statement has an incorrect macro specified or if the
MACRO_MIC_NAME is incorrectly specified for the macro in the design source.
WARNING (TMI-177): [Severe] Not all macros are in User Control GROUP statement for
algorithm algorithm, but the multigroup field from the MIC for at least one operation was
set to SEVERE. Either add all macros that use this algorithm to the group statement, or
change the MULTIGROUP severity for the algorithms operations in the MIC. The statement
is discarded.
EXPLANATION:

The MULTIGROUP keyword, being set to SEVERE, indicates that an operation must
have a grouped isolation solution for ALL macros. The User Control GROUP statement
conflicts with this since it does not include all macros using the same MIC. Processing
continues.
USER RESPONSE:
Determine if the GROUP statement should include all macros using the same MIC or if
the MIC OPERATION statement with MULTIGROUP=S coded should be set to W
(warning) or I (informational).
WARNING (TMI-178): Not all macros are in User Control GROUP statement for algorithm
algorithm_Name, and the multigroup field from the MIC for at least one operation was set
to WARNING.
EXPLANATION:
The MULTIGROUP keyword, being set to WARNING, indicates that it is desirable for the
operation to have a grouped isolation solution for ALL macros. The User Control GROUP
statement conflicts with this since it does not include all macros using the same MIC.
USER RESPONSE:
Determine if the GROUP statement should include all macros using the same MIC or if
the MIC OPERATION statement has an incorrect MULTIGROUP option coded. Refer to
"Macro Isolation Control (MIC) File Reference" and "verify_macro_isolation User
Control Files" in the Encounter Test: Guide 3: Test Structures for additional
information.
WARNING (TMI-199): Group attribute Attribute_Name in Algorithm statement

Algorithm_Statement_Name does not exist for macro Macro_Name. This algorithm
will not be grouped.
EXPLANATION:
The attribute does not exist in the definition block for the macro. This macro will not be
grouped with other macros which use the same algorithm. Processing continues.
USER RESPONSE:
Determine if the attribute is missing from the macro DEF block or if it is incorrect in the
MIC file Algorithm statement. Refer to "Macro Isolation Control (MIC) File Reference" in
INFO (TMI-200): Verifying operation operation_Name, macro Macro|Group_Name.

EXPLANATION:

This message indicates the operation that verify_macro_isolation will process

next. Any messages that follow this message and precede the next TMI-200 message
pertain to this operation. Processing continues.
USER RESPONSE:

ERROR (TMI-201): [Internal] Unable to initialize Pattern Generation Utilities - Run fails.
EXPLANATION:
The program failed while using the Pattern Generation utility.
USER RESPONSE:
ERROR (TMI-202): [Internal] Unable to reset the Pattern Generation Utilities - Run fails.
EXPLANATION:
USER RESPONSE:
ERROR (TMI-203): [Internal] Program error encountered while using Reverse Implication
Pattern Generation Utility.
EXPLANATION:
USER RESPONSE:
ERROR (TMI-204): [Internal] Program error encountered while using Forward Propagation
Pattern Generation Utility.
EXPLANATION:
USER RESPONSE:

ERROR (TMI-205): [Internal] Program error encountered while using the Pattern
Generation Utility.
EXPLANATION:
USER RESPONSE:
ERROR (TMI-206): [Internal] Program error encountered while using the Pattern
Generation Trace Utilities.
EXPLANATION:
USER RESPONSE:
WARNING (TMI-207): [Severe] For operation operation_Name, pin pin_Name of

macro macro_Name has no possible correspondence point targets. This operation fails.
EXPLANATION:
verify_macro_isolation was unable to isolate the pin in the operation. Processing
continues with the next operation.
USER RESPONSE:
List. The pin is displayed with the TIE/TI state and the appropriate must values for the
operation. Examine preceding processing messages for indications of the cause of the
failure. Assuming the design is valid, it may be necessary to provide a Linehold file and/
or forcing isolation via MACRO_CORE_n pin properties for
verify_macro_isolation to successfully solve the operation. Refer to "Properties
for Embedded Macro Test Generation" in the Encounter Test: Guide 3: Test
Structures and Linehold File in the Automatic Test Pattern Generation User
INFO (TMI-209): Operation operation_Name for macro Macro|Group_Name has no

pins associated with it.
EXPLANATION:

Processing continues with the next operation.

USER RESPONSE:
List. The macro is displayed with the TI/TIE state applied. If this operation is supposed
to have pins, determine why it doesnt. Check for preceding processing messages that
may have indicated a problem with this operation.
WARNING (TMI-212): [Severe] Operation operation_Name of algorithm

algorithm_Name for macro Macro|Group_Name failed. No solution was found.
(Elapsed_Time elapsed, CPU_Time cpu)
EXPLANATION:
verify_macro_isolation was unable to find a solution for all of the pins requested
by the operation. Processing continues with the next operation.
USER RESPONSE:
List. The macro is displayed with the TI/TIE state applied. Determine possible causes for
operation failure by examining preceding processing messages.
verify_macro_isolation controls such as a Linehold file or forces may be
necessary to solve the operation. Refer to Linehold File in the Automatic Test Pattern

algorithm_Name for macro Macro|Group_Name was not resolved. Increase the effort
parameter and rerun this operation.
EXPLANATION:
The effort parameter controls how hard verify_macro_isolation works to solve the
operation. The effort parameter specified (or defaulted) when this run was invoked did
not allow verify_macro_isolation to provide a solution.
USER RESPONSE:
Increase the effort parameter and try this operation again. If the maximum effort has
already been tried, verify_macro_isolation cannot solve the operation without
some user controls (lineholds and/or forces) added, or a design modification of the part.
INFO (TMI-215): Operation operation_Name for macro Macro|Group_Name was

verified. (Elapsed_Time elapsed, CPU_Time cpu)
EXPLANATION:

This message indicates the operation that verify_macro_isolation just completed

processing was successful (has valid isolation). The elapsed and cpu time used to
process this operation is provided. Processing continues.
USER RESPONSE:
WARNING (TMI-217): [Severe] CPU time expired.

EXPLANATION:
The maximum CPU time specified or defaulted for this run has been reached. Isolation
data generated through the last completed operation is saved. Processing terminates.
USER RESPONSE:
Increase the CPU option parameter and rerun verify_macro_isolation.
WARNING (TMI-218): [Severe] Elapsed time expired.

EXPLANATION:
The maximum elapsed time specified or defaulted for this run has been reached.
Isolation data generated through the last completed operation is saved. Processing
terminates.
USER RESPONSE:
Increase the Elapsed option parameter and rerun verify_macro_isolation.
WARNING (TMI-219): [Severe] For operation operation_Name, the required value on

pin pin_Name is not 0, 1, X, or Z.
EXPLANATION:
A required value must be 0, 1, X, or Z. If the value was neither of these, the value set for
this pin is X. Processing continues.
USER RESPONSE:
If the value is incorrect, the specific message can be selected from the Verify Core
Isolation Specific Message List. An editor specified by the TB_EDITOR environment
variable is invoked and starts an edit session for the incorrect MIC file. Correct the value
for this pin in the MIC file. Normally, a required value would be 0 or 1.
WARNING (TMI-224): A solution for operation operation_Name for macro

Macro|Group Name was found, but uses latches that are non-controllable. Continuing to
search for a valid solution.

EXPLANATION:
Non-controllable latches used in a solution are invalid since they cannot be loaded via a
normal scan-in sequence and the required values cannot be guaranteed to be correct.
This solution is rejected.
USER RESPONSE:
No response is necessary if a valid solution has been found. If no solution is found,
contact customer support (see Contacting Customer Service on page 23) with the
following information:
The test methodology you are utilizing.
A brief explanation concerning the verify_macro_isolation scenario in
which you failed.
WARNING (TMI-225): A solution for operation Operation Name for macro Macro|Group
Name cannot be verified. If verification is required, the search for a valid solution continues.
EXPLANATION:
verify_macro_isolation found a solution (preconditioning) for a set of
correspondence points for the operation but the verify_macro_isolation checking
function determined that the preconditioning is invalid. If additional sets of
correspondence points exist, verify_macro_isolation will attempt to find a valid
solution. Otherwise the operation will fail to be solved and severe error message TMI-212
will be printed.
If verification=ignore is specified on the command line, the solution is accepted
without verification and message TMI-299 will be printed.
This error should not occur since a solution must always successfully pass verification.
When this error does occur there are three possible causes:
The test generation function created an invalid solution.
The verify function incorrectly failed a valid solution.
There are races in the precondition logic which causes the solution to fail
verification.
USER RESPONSE:
Customer support (see Contacting Customer Service on page 23) should be contacted
if this error occurs, even if verify_macro_isolation eventually found a valid solution
that did pass verification. Please be prepared to provide the following information:


which you failed.
If a verified solution cannot be found and you wish to continue processing the isolation
data through MTG, verify_macro_isolation can be rerun using verification options
"ignore" or "none".
WARNING (TMI-227): A solution for operation Operation Name for macro Macro|Group
Name was found but rejected by TPG internally. The search for a valid solution continues.
EXPLANATION:
The TPG function found a solution (preconditioning) for a set of correspondence points
for the operation but TPG determined that the preconditioning is invalid. If additional sets
of correspondence points exist verify_macro_isolation will continue to look for a
valid solution. Otherwise, the operation will fail to be solved and severe error message
TMI-212 will be printed.
This is an error that should not occur because a solution generated by TPG should
always be valid. A solution which is not valid indicates there is a problem with the test
generator. It is necessary that customer support (see Contacting Customer Service on
page 23) be contacted so that this test generation problem can be corrected.
USER RESPONSE:
Customer support (see Contacting Customer Service on page 23) should be contacted
if this error occurs, even if verify_macro_isolation eventually found a valid
solution. Please be prepared to provide the following information:
which you failed.
WARNING (TMI-228): [Severe] Innernet net_Name is fed directly by a non-observable

latch. Since this net cannot be observed, operation operation_Name fails.
EXPLANATION:
This inner net is not valid since it is not observable. No isolation is generated for this
USER RESPONSE:

Message List. The innernet and the non-observable latch that feeds it are displayed with
the TI/TIE state applied.
WARNING (TMI-233): [Severe] Operation operation_Name for macro

Macro|Group_Name was not resolved. A solution was found, but was invalid because of
pulse polarity problems. Ensure that the flags on the clock pins are correct. If they are not,
correct them and rerun.
EXPLANATION:
The required stability value is based on the pulse polarity specified for the macro pin in
the MIC and path inversion level from the correspondence point to the macro pin. When
a primary input corresponds to a pulsed macro pin in multiple operations the stability (off)
value for the primary input cannot change (i.e. the stability (off) value for the must be the
same in all operations using that primary input for correspondence).
verify_macro_isolation has detected a change in the required stability value
between operations.
The Tester Description Rule (TDR) indicates that verify_macro_isolation is to
consider this to be a severe error.
USER RESPONSE:
Identify the operations for which the designated primary input corresponds to a macro
pulsed pin. Check that the macro pins in each operation are specified with the correct
pulse polarity in the MIC. If they are not, correct the pulse polarity and rerun. If the
polarities are correct, the logic must be changed such that the stability (off) value is
consistent in all operations using this primary input. The specific message can be
selected from the Verify Core Isolation Specific Message List. The macro is displayed
with the TI/TIE state applied.
WARNING (TMI-234): [Severe] Innernet pin_Name is fed directly by a non-controllable

latch. Since this net cannot be stimmed, operation operation_Name fails.
EXPLANATION:
This inner net is not valid since it is not controllable. No isolation is generated for this
USER RESPONSE:
operation. The specific message can be selected from Verify Core Isolation Specific
Message List. The innernet and the non-controllable latch that feeds it are displayed with
the TI/TIE state applied.

WARNING (TMI-235): [Severe] Group Single Latch Load was specified for algorithm
algorithm_Name. The MIC indicates that no latch is allowed to be used at different
precondition values for operations in this algorithm. Print isolation to determine actual latches
in conflict.
EXPLANATION:
The latch value conflicts cause additional SRL loads for macro tests resulting in a higher
test cost.
USER RESPONSE:
If the additional latch loading is not acceptable, determine the cause.
verify_macro_isolation user controls (lineholds and/or correspondence
statements) can be used to find isolation to reduce latch loading. The specific message
can be selected from the Verify Core Isolation Specific Message List. The first latch
which required reloading is displayed with the TIE/TI state.
WARNING (TMI-237): [Severe] Pin pin_Name of macro macro_Name is at value due to

a TIE block or a TI PI therefore this pin cannot be used for correspondence and operation
operation_Name fails.
EXPLANATION:
The pin indicated in the message is an input pin to a macro and requires correspondence
(as indicated by the MIC). The pin is controlled to a value by either a TIE block of a TI
primary input. therefore verify_macro_isolation cannot isolate this pin to a valid
correspondence point. The operation fails for this macro. Processing continues.
USER RESPONSE:
Either modify the design such that the pin corresponds to a valid correspondence point
or modify the PINGROUP or INNER_NETS statement for the operation to designate the
appropriate value for the input pin.
WARNING (TMI-238): [Severe] For operation operation_Name, pin pin_Name1 and

pinName2 have only one possible correspondence point, pinName3. Since these pins are
not allowed to share correspondence, the operation fails.
EXPLANATION:
The pins indicated in the message have only one possible correspondence point and
these pins are not allowed to share that correspondence point. The pins are not allowed
to share the indicated correspondence point either because there is a difference in
inversion between the pins and the correspondence point or because the MIC pingroup
statements for the pins do not allow the sharing of correspondence points.
The operation fails for this macro. Processing continues.

USER RESPONSE:
Modify the design such that each pin has a unique correspondence point or modify the
appropriate pin groups in the MIC file to allow correspondence point sharing.
WARNING (TMI-239): [Severe] For operation operation_Name, a conflict was detected

in the request list therefore the operation fails.
EXPLANATION:
The values required by the operations pingroup statements are in conflict. That is, it is
impossible for the test generation utility to simultaneously establish all of the design
values required by the operation.
The operation fails for this macro. Processing continues.
USER RESPONSE:
Either modify the design such each pin required at value can be stimulated to that value
(without disturbing any other pins value) or correct the MIC file.
WARNING (TMI-240): [Severe] For operation operation_name, a conflict was detected

in the implication of the request list therefore the operation fails.
EXPLANATION:
The values required by the operations pingroup statements are in conflict. That is, it is
impossible to simultaneously establish all of the design values required by the operation.
Either the reverse implication or the forward propagation of the required values caused
a conflict. The operation fails for this macro. Processing continues.
USER RESPONSE:
Either modify the design such each pin required at value can be stimulated to that value
(without disturbing any other pins value) or correct the MIC file. The macro or macros
(set of pins if innernets are in use) comprising the failing group is/are displayed. The pins
which are under test, that is those pins which appear in a PINGROUP statement for the
operation are highlighted (the default is red).
The design state consists of the set of required stimulus which could successfully be
established. The "pop-up" window indicates the subsequent request which could not be
satisfied due to the values already in the circuit.

Macro|Group_Name was not resolved. A solution was found, but was invalid because pin
pin_Name is used as a clock but will be required to be at different stability values during
product testing.

EXPLANATION:
The required stability value is based on the pulse polarity specified for the macro pin in
the MIC and path inversion level from the correspondence point to the macro pin. When
a primary input corresponds to a pulsed macro pin in multiple operations the stability (off)
value for the primary input cannot change (i.e. the stability (off) value must be the same
in all operations using that primary input for correspondence).
verify_macro_isolation has detected a change in the required stability value
between operations. The Tester Description Rule (TDR) indicates that
verify_macro_isolation is to consider this to be a severe error.
USER RESPONSE:
Identify the operations for which the designated primary input corresponds to a macro
pulsed pin. Check that the macro pins in each operation are specified with the correct
pulse polarity in the MIC. If they are not, correct the pulse polarity and rerun. If the
polarities are correct, the logic must be changed such that the stability (off) value is
consistent in all operations using this primary input. The specific message can be
selected from the Verify Core Isolation Specific Message List. The macro is displayed
with the TI/TIE state applied.

Macro|Group_Name was not resolved. A solution was found, but was invalid because pin
pin_Name is used as a clock but there are no more tester pins available which can be
defined as a clock pin.
EXPLANATION:
The CLOCK_PINS option of the TEST_PINS statement in the Tester Description Rule
(TDR) specifies how many tester pins can deliver pulses to the product. This operation
required a non-clock PI to be used for pulsing a macro pin but there are no more tester
pins available which can be used as a clock (pulsed) pin.
USER RESPONSE:
Identify the operation for which the designated primary input corresponds to a macro
pulsed pin. Check that the macro pin is correctly specified as a pulsed pin. If it is not,
correct and rerun. If the pin is correctly specified as being pulsed, check the TDR
CLOCK_PINS value. Also check that the correct TDR name was specified in the mode
definition file. If the tester pulsed pin limit is reached, then the logic must be changed
such that the pin isolates to a PI flagged as a clock or to another PI which is already being
used as a clock. The specific message can be selected from the Verify Core Isolation
Specific Message List. The macro is displayed with the TI/TIE state applied.

WARNING (TMI-244): [Severe] In operation operation_Name, a required value or

correspondence for pin pin_Name of macro macro_Name cannot be established because
there is no logic feeding this pin, therefore the operation fails.
EXPLANATION:
A required value or correspondence is required on a macro pin that is not fed by any
logic. The operation fails for this macro. Processing continues.
USER RESPONSE:
Either modify the design such that there is logic feeding the pin or modify the MIC file.
The macro is displayed and the failing pin is highlighted (the default is red).
INFO (TMI-245): Operation operation_Name for macro Macro|Group_Name,

algorithm algorithm_Name has been solved | verified.
EXPLANATION:
This indicates that verify_macro_isolation has solved this operation in a previous
algorithm. The isolation data from that solution will be reused.
USER RESPONSE:

algorithm_Name for macro Macro_Name failed.
EXPLANATION:
An attempt to solve this operation in a previous algorithm failed.
USER RESPONSE:
Determine possible causes for the original operation failure of the previous algorithm.
WARNING (TMI-247): [Severe] In operation operation_Name, the value required for

pin pin_name of macro macro_Name conflicts with value established by the TI/TIE state,
therefore the operation fails.
EXPLANATION:
The value required for the pin by the operation is in conflict with a TI/TIE state. That is,
simulation of the TI/TIE state produces a value at the pin which is in conflict with the value
specified in the MIC file. The operation fails for this macro. Processing continues.
USER RESPONSE:

Either modify the design such that the pin is not forced to the wrong value by the TI/TIE
state or modify the MIC file. The macro is displayed and the failing pin is highlighted (the
default is red). The design is set to the TI/TIE state.
WARNING (TMI-248): [Severe] In operation operation_Name, the value required for

pin pin_Name of macro macro_Name conflicts with value established by the Macro User
Control file statements, therefore the operation fails.
EXPLANATION:
The value required for the pin by the operation is in conflict with the linehold state. That
is, simulation of the Macro User Control file statements produces a value at the pin which
is in conflict with the value specified in the MIC file. The operation fails for this macro.
USER RESPONSE:
Modify the Macro User Control file so that the pin is not forced to the wrong value. The
macro is displayed and the failing pin is highlighted (the default is red). The design is set
to the state establshed by the Macro User Control file statements.
WARNING (TMI-249): [Severe] For control operation operation_Name, pin pin_Name

of macro macro_Name is not at the required value when the preconditioning is applied.
EXPLANATION:
The pin identified in the message was not controlled to the value specified in the
appropriate control operation pingroup statement of the MIC file by the application of the
TI/TIE state (referred to as the modeinit preconditioning). Any pin assigned a value in the
control operation must achieve that value by modeinit preconditioning. Processing
continues.
USER RESPONSE:
If the MIC is correct, modify the logic such that the pin is controlled, by a TI flagged
primary input or a TIE net to the appropriate value and rerun. If the pin need not be
controlled to the value, remove the pin from the control operation pingroup statement and
rerun.
ERROR (TMI-250): [Internal] Macro macro_Name was not found in the macro tables.
This should have been checked by User Control checking.
EXPLANATION:
The program filed while using the macro table.
USER RESPONSE:


ERROR (TMI-251): [Internal] Algorithm operation_Name was not found in the macro
tables. This should have been checked by User Control checking.
EXPLANATION:
USER RESPONSE:
ERROR (TMI-252): [Internal] Operation operation_Name was not found in the macro
tables. This should have been checked by User Control checking.
EXPLANATION:
USER RESPONSE:
WARNING (TMI-270): [Severe] Invalid linehold specified in the User Control file. Linehold
was specified as an entity which it is not, that is. a block that is not a block, and so on. Name
entity_Name.
EXPLANATION:
The program failed while using the User Control file.
USER RESPONSE:
WARNING (TMI-271): Pin pin_name for operation operation_Name had a

MACRO_CORR_n attribute specified on it, and was also forced to a correspondence point via
the User Control file. The user control will override.
EXPLANATION:
The identified pin has a MACRO_CORR_n model attribute specified in the design source
and the same pin has a CORRESPONDENCE statement coded in the user control file.
verify_macro_isolation will honor the user control file specification and ignore the
model attribute.

USER RESPONSE:
If you wish to have the model attribute applied remove the CORRESPONDENCE statement
for this pin and rerun verify_macro_isolation.
WARNING (TMI-280): [Severe] Group single latch load was specified for algorithm
algorithm_name but preconditioning pin pin_name was assigned different values in
operation oper_name and operation oper_name for macro macro_name in group
group_number.
EXPLANATION:
test cost.
USER RESPONSE:
If the additional latch loading is unacceptable, verify_macro_isolation user
controls (lineholds and or correspondence statements) can be used to find isolation to
reduce latch loading. Refer to "verify_macro_isolation User Control Files" in the
WARNING (TMI-282): [Severe] Group single latch load was specified for algorithm
algorithm_name but preconditioning pin pin_name of operation oper_name is used
as a correspondence pin for macro pin pin_name in operation oper_name in group
group_number.
EXPLANATION:
test cost.
USER RESPONSE:
If the additional latch loading is unacceptable, verify_macro_isolation user
controls (lineholds and or correspondence statements) can be used to find isolation to
reduce latch loading. Refer to "verify_macro_isolation User Control Files" in the
WARNING (TMI-286): A linehold on source pin pin_name for macro macro_name,

algorithm algorithm_name, and operation oper_name has conflicting values.
EXPLANATION:
Linehold conflicts are caused by specifying two different values on the same net using
the User Control file.
USER RESPONSE:

Check the User Control file for the same linehold at the Macro level, Algorithm level, and
Operation level to ensure the value does not change between levels.
WARNING (TMI-288): A linehold on source pin pin_name for Group group_number,

operation oper_name has conflicting values.
EXPLANATION:
Linehold conflicts are caused by specifying two different values on the same net using
the User Control file.
USER RESPONSE:
Check the User Control file for the same linehold at the Macro level, Algorithm level, and
Operation level and ensure the value does not change between levels.
WARNING (TMI-299): [Severe] Solved operations have not been verified.

EXPLANATION:
verify_macro_isolation was executed with "verification=none" command
line option. This generates an isolation file containing unverified solutions for operations
which have been solved. This message is generated so that severe exit code (4) is set
in the verify_macro_isolation audit statistics.
The "verification=none" command line option gives the user the option to continue
processing if desired in cases where an operation is solved but cannot be verified (a TMI-
225 message is issued for such an operation). This option should NOT be used for
normal verify_macro_isolation processing.
USER RESPONSE:
If operation solutions need to be verified, rerun with verification=required.
ERROR (TMI-320): [Internal] TLH invalid value for default linehold..

EXPLANATION:
An illegal linehold value is specified.
USER RESPONSE:
Correct the linehold value and rerun.
WARNING (TMI-322): [Severe] Macro macro_Name cannot be processed because the

MIC data has not been read in. Ensure the MIC data can be read (check MIC path, file name,
etc.) and rerun with append=no specified.
EXPLANATION:

The program was unable to detect the MIC.

USER RESPONSE:
Correct the MIC path and rerun.
WARNING (TMI-351): MIC error. ASSOCIATED_PINGROUP statement has no name. The

statement is ignored..
EXPLANATION:
An ASSOCIATED_PINGROUP statement with no name specified was was detected in the
MIC file. Processing continues with the next valid MIC statement.
USER RESPONSE:
session for the incorrect MIC. Find the ASSOCIATED_PINGROUP statement and correct
it by specifying a name. Rerun verify_core_isloation.
WARNING (TMI-352): MIC error. ASSOCIATED_PINGROUP statement

Associated_Pingroup_Name has a duplicate entry Pingroup_Name specified in
the PINGROUPS keyword.
EXPLANATION:
The identified ASSOCIATED_PINGROUP statement has the same name specified more
than once for the PINGROUPS keyword. The duplicate name is ignored.
USER RESPONSE:
it by removing the duplicate name(s). Rerun verify_core_isloation.
WARNING (TMI-353): MIC error. ALGORTHM statement Algorithm_Name has a

duplicate entry Associated_Pingroup_Name specified in the
ASSOCIATED_PINGROUPS keyword.
EXPLANATION:

The identified ALGORITHM statement has the same name specified more than once for
the ASSOCIATED_PINGROUPS keyword. The duplicate name is ignored.
USER RESPONSE:
it by removing the duplicate name(s). Rerun verify_core_isloation.
WARNING (TMI-354): MIC error. PINGROUP statement Pingroup_Name, pin pin_Name

has CORR_ID specified. This is only valid if MACRO_SOURCE or MACRO_DEPENDENT is
specified for CORRESP_TYPE. The CORE_ID is ignored..
EXPLANATION:
The identified PINGROUP statement has a CORE_ID= keyword specified for a pin which
has a correspondence type other than MACRO_SOURCE or MACRO_DEPENDENT.
USER RESPONSE:
session for the incorrect MIC. Find the PINGROUP statement and correct it by removing
the CORE_ID from the identified pin. Rerun verify_core_isloation.
WARNING (TMI-355): [Severe] MIC error. ALGORITHM statement Algorithm Name

has ASSOCIATED_PINGROUPS "Associated_pingroups Name" specified but there
is no corresponding ASSOCIATED_PINGROUP statement.
EXPLANATION:
The ASSOCIATED_PINGROUP statement lists the pingroups necessary to connect two
macros together. This statement must exist for each entry listed in the algorithm
statement ASSOCIATED_PINGROUPS keyword.
USER RESPONSE:
Correct the MIC and rerun.

WARNING (TMI-356): [Severe] MIC error. ALGORITHM statement Algorithm Name.

ASSOCIATED_PINGROUPS keyword has "Associated_pingroups Name" specified
but no corresponding entry is specified in the MACRO_TYPE keyword.
EXPLANATION:
Each entry specified in the ASSOCIATED_PINGROUPS keyword of the ALGORITHM
statement is required to be listed in the MACRO_TYPES keyword. This is necessary to
connect the correct macros together using the pingroups listed in the
ASSOCIATED_PINGROUPS keyword.
USER RESPONSE:
WARNING (TMI-357): [Severe] MIC error. PINGROUP statement Pingroup Name.

There is no ASSOCIATED_PINGROUP statement with this PINGROUP name specified.
EXPLANATION:
The PINGROUP statement has a CORRESP_TYPE of MACRO_SOURCE or
MACRO_DEPENDENT. When this is the case, this pingroup name must be specified in
at least one ASSOCIATED_PINGROUP statement.
USER RESPONSE:
WARNING (TMI-358): [Severe] MIC error. Pin Pin Name in macro_dependent

PINGROUP Pingroup Name has no corresponding macro_source pin specified for
operation Operation Name.
EXPLANATION:
Each pin coded in a pingroup with corresp_type=macro_dependent is required to
have a source pin coded in another pingroup with corresp_type=macro_source.
This correlation is made with matching corr_id keywords.
USER RESPONSE:

Associated_Pingroup_Name already exists. This statement is ignored.
EXPLANATION:
The ASSOCIATED_PINGROUP statement is duplicated in the MIC file.

USER RESPONSE:
session for the incorrect MIC. Correct the MIC by removing the redundant statement. and
rerun.

Associated_Pingroup_Name. There is no ALGORITHM with
Associated_Pingroup_Name specified in the ASSOCIATED_PINGROUPS keyword.
This statement is ignored.
EXPLANATION:
The ASSOCIATED_PINGROUP statement was specified but the MIC contains no
ALGORITHM specified with a matching name in the ASSOCIATED_PINGROUPS keyword.
USER RESPONSE:
rerun.
WARNING (TMI-361): MIC error. PINGROUP Pingroup_Name has

corresp_type=Coresp_Type but pin pin_Name does not have CORR_ID specified.
The pin is ignored.
EXPLANATION:
The PINGROUP statement was specified with a corresp_type however no CORR_ID
was specified.
USER RESPONSE:
rerun.

WARNING (TMI-379): The keyword ANCHOR=YES in algorithm Algorithm Name cannot be

used with the keyword GROUP=NO or GROUP=TOPOLOGY.
EXPLANATION:
The keyword ANCHOR=YES is only valid with the keyword GROUP=YES. The
combination used in the MIC is not allowed.
USER RESPONSE:
Select from one of the following four allowable combinations:
For no grouping: ANCHOR=NO and GROUP=NO
For normal grouping: ANCHOR=NO and GROUP=YES
For topological grouping: ANCHOR=NO and GROUP=TOPOLOGY
For anchored grouping: ANCHOR=YES and GROUP=YES
Make the appropriate change to the MIC file and rerun. See "ALGORITHM Statement"
INFO (TMI-380): Checking macro groups.

EXPLANATION:
This indicates that verify_macro_isolation is putting the macros into groups
where necessary.
USER RESPONSE:
WARNING (TMI-381): [Severe] The anchored group in MIC MIC_Name, algorithm

Algorithm_Name, and operation Operation_Name does not contain any non-anchored
macros.
EXPLANATION:
An anchor group must consist of both anchored and non-anchored macros. The
anchored macros must contain MACRO_DEPENDENT pins and the non-anchored
macros must contain MACRO_SOURCE pins.
USER RESPONSE:

WARNING (TMI-382): [Severe] The anchored group in MIC MIC Name, algorithm
Algorithm Name, and operation Operation Name does not contain any anchored
macros.
EXPLANATION:
An anchor group must consist of both anchored and non-anchored macros. The
anchored macros must contain MACRO_DEPENDENT pins and the non-anchored
macros must contain MACRO_SOURCE pins.
USER RESPONSE:
WARNING (TMI-384): [Severe] No source macro was found for the anchor macro Macro
Name in the group consisting of algorithm Algorithm Name and operation Operation Name.
EXPLANATION:
An anchor group consists of both anchored and non-anchored (source) macros. There
must be a connection between the MACRO_SOURCE pins on each source macro and
the MACRO_DEPENDENT pins on at least one anchor macro.
USER RESPONSE:
INFO (TMI-385): None of the required macro types in MIC MIC Name, algorithm
Algorithm Name, operation Operation Name, were found in the group. All operations
in this group were discarded.
EXPLANATION:
This message is printed if the MACRO_TYPE_REQUIRED statement in the MIC for an
ALGORITHM is specified and none of the required macro types are found within the group
of macros for this operation.
USER RESPONSE:
No action is necessary if it is determined that none of the required macro types are
present in this particular group of macros. Otherwise, correct the part or the MIC and
rerun.
WARNING (TMI-386): [Severe] The MACRO_DEPENDENT pins on dependent macro

Macro Name do not trace back to the MACRO_SOURCE pins on any source macro in any
topology group in MIC MIC Name.
EXPLANATION:

There must be a connection between the MACRO_DEPENDENT pins on a dependent

macro and the MACRO_SOURCE pins on at least one source macro when using topology
grouping.
USER RESPONSE:
Correct the MIC if there is an error in the MACRO_DEPENDENT or MACRO_SOURCE
pingroup names. Correct the circuitry if a path does not exist between the
MACRO_DEPENDENT and MACRO_SOURCE pins.
WARNING (TMI-390): [Severe] The MACRO_SOURCE pin Pin Name on macro Macro
Name in the group consisting of algorithm Algorithm Name and operation Operation Name is
tied to a MACRO_SOURCE pin on macro Macro Name.
EXPLANATION:
MACRO_SOURCE pins on one macro must not connect to MACRO_SOURCE pins on
a different macro.
USER RESPONSE:
WARNING (TMI-391): [Severe] The MACRO_DEPENDENT pin Pin Name on anchor

macro Macro Name in the group consisting of algorithm Algorithm Name and operation
Operation Name traced back to source macro Macro Name but one or more pins on this
anchor macro have already traced back to source macro Macro Name.
EXPLANATION:
The MACRO_DEPENDENT pins on an anchor macro must all trace back to
MACRO_SOURCE pins on a single source (non-anchored) macro.
USER RESPONSE:
WARNING (TMI-392): [Severe] The MACRO_DEPENDENT pin Pin Name on macro

Macro Name in the group consisting of algorithm Algorithm Name and operation Operation
Name does not trace back to a MACRO_SOURCE pin.
EXPLANATION:
Each MACRO_DEPENDENT pin on an anchor macro must trace back to a
MACRO_SOURCE pin on a source (non-anchored) macro.
USER RESPONSE:


ERROR (TMI-420): [Internal] Programming error: error
EXPLANATION:
A programming error has occurred.
USER RESPONSE:
WARNING (TMI-501): Preconditioning pin pin_Name is a latch output. This is invalid since
the operation specifies PI only preconditioning.
EXPLANATION:
The isolation solution is invalid, message TMI-225 will be printed.
USER RESPONSE:
See message TMI-225 explanation and response.
WARNING (TMI-502): Invalid preconditioning source, pin pin_Name. A preconditioning pin

must be a Primary Input, Common Input/Output, or a Latch output.
EXPLANATION:
USER RESPONSE:
WARNING (TMI-504): Preconditioning pin pin_Name is a TI pin which is not set to its
stability value.
EXPLANATION:
USER RESPONSE:
WARNING (TMI-505): Preconditioning pin pin_Name is a fixed value latch which is being
held at the wrong value.
EXPLANATION:


USER RESPONSE:
WARNING (TMI-507): Preconditioning causes a disruption in output correspondence path

from macro pin pin_Name1 to correspondence point pin pin_Name2. Value at
correspondence point is Sim_Value1/Sim_Value2. The value should be X/X.
EXPLANATION:
USER RESPONSE:
WARNING (TMI-516): Macro pin pin_Name1, index Pin_Index1, is a clock control that
corresponds to pin Pin_Mame2 which is not flagged as a Clock PI.
EXPLANATION:
The macro pin is specified as a pulsed pin but the correspondence PI is not identified as
a clock. This can cause serious problems in manufacturing with setting up the proper
clock timing templates. Moreover, this condition may result in correspondence path
checking errors. Processing continues.
USER RESPONSE:
To correct this condition identify the pin in question as a clock pin, using model attributes,
BSDL or the test mode ASSIGN statement. If this is not possible, contact your
manufacturing site to give them advance warning of this condition. This will help prevent
deviations from any RTAT (rapid turnaround time) agreement.
WARNING (TMI-518): Correspondence/Preconditioning conflict. Correspondence pin

pin_Name is also used for preconditioning in this operation.
EXPLANATION:
USER RESPONSE:
WARNING (TMI-522): Preconditioning pin pin_Name1 disturbed while testing the

correspondence path for macro pin pin_Name2. Pin_Index2.

EXPLANATION:
USER RESPONSE:
WARNING (TMI-529): Required value of Value is not achieved for Macro pin pin_Name,
index Pin_Index2.
EXPLANATION:
USER RESPONSE:
WARNING (TMI-530): Correspondence path error between Macro pin pin_Name1, index
Pin_Index1, and correspondence point pin Pin_Name2.
EXPLANATION:
USER RESPONSE:
WARNING (TMI-531): For operation operation_name, the latch correspondence pin

pin_name for pin pin_name of macro macro_name may be disturbed as the clock(s) to
the latch are not controlled off.
EXPLANATION:
The Pingroup statement for the macro pin indicated that the pin requires
correspondence to either a primary input or to a latch which will retain its value
throughout the operation. The solution found used a latch which was shown to be
corruptible.
The isolation solution is invalid; message TMI-225 will be printed
USER RESPONSE:
WARNING (TMI-538): Macro pins pin_Name1 and pin_Name2 share correspondence

point pin pin_Name3. This is allowed by the MIC as the SHARE keyword was specified for

both pins, but a pulsed pin cannot share a correspondence net with a non-pulsed pin and vice
versa.
EXPLANATION:
USER RESPONSE:
WARNING (TMI-539): Pulsed macro pins pin_Name1 and pin_Name2 share

correspondence point pin pin_Name3 but the correct pulse polarities cannot be obtained for
both macro pins.
EXPLANATION:
USER RESPONSE:
WARNING (TMI-540): Preconditioning pin pin_Name is a OI pin which is not set to its
stability value.
EXPLANATION:
USER RESPONSE:
WARNING (TMI-541): Macro pins pin_Name1 and pin_Name2 share correspondence

point pin_Name3 but the same state cannot be obtained for both macro pins.
EXPLANATION:
USER RESPONSE:
WARNING (TMI-542): [Severe] Timed operation pin_Name cannot be verified. Macro pin
operation_Name has no event order specified.
EXPLANATION:

This pin is used for an operation which has timing=repetitive specified but no dpo
value has been specified for the pin. No test patterns will be generated by MTG for this
operation.
USER RESPONSE:
Correct the MIC and rerun verify_macroisolation. Refer to "Macro Isolation
operation_Name has a invalid event order specified.
EXPLANATION:
This pin is used for a dynamic timed (repetitive) operation but a a pre_dpo or post_dpo
value has been specified for the pin.
These keywords are valid only for non_repetitive timed operations. No test patterns
will be generated by MTG for this operation.
USER RESPONSE:
Correct the MIC and rerun verify_macro_isolation. Refer to "Macro Isolation
operation Name has no event order specified.
EXPLANATION:
This pin is used for a dynamic timed (non_repetitive) operation but no dpo, pre_dpo, or
post_dpo value has been specified for the pin. Each pin requiring correspondence must
have an event ordering keyword specified. No test patterns will be generated by MTG for
this operation.
USER RESPONSE:
WARNING (TMI-545): [Severe] Dynamic test operation operation_Name does not

have at least two correspondence pins with unique event ordering.
EXPLANATION:

For an operation to be timed, there must be at least two events generated in a dynamic
test pattern. This is accomplished with unique dpo values specified on 2 or more
correspondence pins. No test patterns will be generated by MTG for this operation.
USER RESPONSE:
WARNING (TMI-600): Error occured while generating MIPD file.

EXPLANATION:
Internal error occured while generating MIPD file.
USER RESPONSE:
Contact Customer Service.
INFO (TMI-800): Block names for filename have been saved.

EXPLANATION:
Block names have been saved in the referenced file.
USER RESPONSE:


53
TMT - Create MacroTests Messages
TMT-001 through TMT-050 on page 1659

TMT-001 through TMT-050

WARNING (TMT-001): [Severe] The create_macro_tests function, function, could
not find file filename.
EXPLANATION:
create_macro_tests attempted to open the file listed but the file does not exist.
USER RESPONSE:
Determine the reason (wrong workdir, testmode, path, etc.), correct and rerun.

not write data to file filename.
EXPLANATION:
create_macro_tests attempted to write data to the listed file but could not.
USER RESPONSE:

not read data from file filename.
EXPLANATION:

USER RESPONSE:

not close file filename.
EXPLANATION:
USER RESPONSE:

not verify the file header in file filename.
EXPLANATION:
MacroIsolationbin file may have been created with an old version of Verify Core
Isolation.
USER RESPONSE:
INFO (TMT-010): Loading MPR file filename.

EXPLANATION:
This indicates that create_macro_tests is beginning to load the specified MPR.
USER RESPONSE:
WARNING (TMT-011): [Severe] The isolation data indicates that Verify Core Isolation was
run in the sign-off mode (the verify_macro_isolation command line keyword
runforsignoff=yes was specified). create_macro_tests will generate patterns but an
audit is set as required by the manufacturing site. create_macro_tests processing
continues.
EXPLANATION:

The isolation data produced by Verify Core Isolation when the

verify_macro_isolation command line option runforsignoff=yes is specified
may not contain all the algorithms which are executed by the MPR. Since the
manufacturing site will regenerate the isolation data including all the required algorithms,
this message is intended to notify you that an audit has been set.
USER RESPONSE:
If it is your intent to generate macro test patterns, rerun Verify Core Isolation with
runforsignoff=no and then rerun create_macro_tests. If the manufacturing site
will be generating the macro test patterns, ignore this message.
WARNING (TMT-037): [Severe] The file, filename, is not registered in globalData and
therefore cannot be accessed.
EXPLANATION:
The MacroIsolationbin Verify Core Isolation output file was not registered.
USER RESPONSE:
ERROR (TMT-038): [Internal] The modal filename for the file filename could not be
constructed.
EXPLANATION:
A program error prevented the application from creating the required name for this file in
the context of the testmode.
USER RESPONSE:
WARNING (TMT-039): [Severe] The file, filename, is not writeable, therefore the results
of this create_macro_tests run cannot be saved.
EXPLANATION:
The permission bits for this file are not set to "write".
USER RESPONSE:
WARNING (TMT-040): [Severe] The file, filename, is not readable, therefore the results
of this create_macro_tests run cannot be saved.

EXPLANATION:
The permission bits for this file are not set to "read".
USER RESPONSE:
ERROR (TMT-041): [Internal] The master filename for the file filename could not be
constructed.
EXPLANATION:
A program error prevented the application from creating the required name for this file in
the context of the the committed (master) data.
USER RESPONSE:
WARNING (TMT-042): [Severe] The directory, directoryname, is not writeable,

therefore the results of this create_macro_tests run cannot be saved.
EXPLANATION:
USER RESPONSE:
writable.
WARNING (TMT-043): [Severe] The directory, directoryname, is not readable,

therefore the results of this create_macro_tests run cannot be saved.
EXPLANATION:
USER RESPONSE:
readable.
ERROR (TMT-044): [Internal] The directory name could not be constructed using
PROJECT = projectname, PARTID = partid.
EXPLANATION:

The program could not create the directory name with the internal variables formed from
the specified WORKDIR (and optionally ENTITY.
The PROJECT should be the same as the WORKDIR and the PARTID should either be
tbdata or the ENTITY specification.
USER RESPONSE:
prepared to communicate the specified WORKDIR and ENTITY used for the input
command string and the PROJECT and PARTID referenced in the message.
ERROR (TMT-045): [Internal] A non-zero return code was returned from Encounter Test
(TBD) function function. MTG (create_macro_tests) processing terminates.
EXPLANATION:
A program function called by the application failed. The application is unable to continue
without the result of this function.
USER RESPONSE:
WARNING (TMT-046): [Severe] No isolation data exists in the MacroIsolationbin file.

EXPLANATION:
The Verify Core Isolation run failed before any isolation data could be generated.
USER RESPONSE:
Create valid isolation data before rerunning create_macro_tests.
WARNING (TMT-050): [Severe] A test type of STATIC MACRO, DYNAMIC MACRO, or

DYNAMIC TIMED MACRO was not specified for testmode modename.
create_macro_tests processing terminates.
EXPLANATION:
The testmode must have a test type of STATIC MACRO, DYNAMIC MACRO, or
DYNAMIC TIMED MACRO defined. Processing terminates. The type of macro test
desired must be specified in the modedef file for the specified test mode.
create_macro_tests needs this information to determine the format of the test
patterns that it generates.
USER RESPONSE:

Verify the Mode Definition path and filename for the testmode is correct. If the Mode
Definition path is correct, check that the appropriate test type is defined in the Mode
Definition file. Add the macro test type to the mode definition file and rerun the mode build
and Verify Core Isolation applications before rerunning create_macro_tests.

WARNING (TMT-051): [Severe] Test mode modename is IEEE 1149.1, which is not
processed by create_macro_tests.
EXPLANATION:
create_macro_tests does not process an IEEE 1149.1 test mode. Processing
terminates.
USER RESPONSE:
Do not attempt to run create_macro_tests for IEEE 1149.1 test modes. Select a non-
IEEE 1149.1 testmode. Ensure that the testmode has the appropriate test type defined
(static or dynamic macro) in the Mode Definition File.
INFO (TMT-052):The command line keyword testvectorformat=option is ignored

because the specified option is invalid.
EXPLANATION:
The specified option for the testvectorformat keyword is invalid. The application will
ignore the specification and continue with the default based on the test mode definition.
USER RESPONSE:
If the default value is unacceptable, rerun create_macro_mpr_tests with a valid
testvectorformat specification. The valid values can be found in
create_macro_mpr_tests in the Encounter Test: Reference: Commands or by using
-h, -H, help, or help=testvectorformat on the create_macro_mpr_tests
command line.
WARNING (TMT-100): Isolation data for group groupnum does not exist. Run
report_groups_for_core_tests to obtain the valid groups created by Verify Core
Isolation.
EXPLANATION:
The group number specified in the selectgroup option does not exist in the
MacroIsolationBin file. If this is the only group specified, processing terminates.
Otherwise, processing will continue for the other valid groups.

USER RESPONSE:
Verify which groups were successfully created by Verify Core Isolation for the specified
inexperiment by running report_groups_for_core_tests, which prints a list of
groups that can be processed by create_macro_tests or
create_macro_mpr_tests. Refer to report_groups_for_core_tests in the
WARNING (TMT-101): [Severe] A thru-latch correspondence point for operation

opername has a latch type which is not a BML or RML. Correspondence point index =
hierindex.
EXPLANATION:
A thru-latch solution supports only the B_SHIFT_CLOCK Measure Latch or
Representative Measure Latch types. Pattern generation for this group fails.
USER RESPONSE:
If this part requires a thru-latch solution, analysis is required to determine why the
isolation uses invalid latch types. If a latch solution is acceptable, create a new Verify
Core Isolation experiment using an isolation solution generated with the
corresptype=pipolatch option specified, and rerun create_macro_mpr_tests
or create_macro_tests.
WARNING (TMT-102): Isolation data for operation opername was not verified. No test
patterns will be created for algorithms that use this operation.
EXPLANATION:
An operation read from the MacroIsolationBin file was flagged as "not verified". Any test
algorithm in the MPR which uses this operation will cause test pattern generation to fail
for that group. Processing continues.
USER RESPONSE:
No action is necessary if the MPR does not use this operation in any of the test
algorithms. Otherwise, determine why the isolation was not verified in Verify Core
Isolation, create a new Verify Core Isolation experiment with required operations isolated
successfully, and rerun create_macro_tests.
WARNING (TMT-103): [Severe] The single latch load requirement for group groupnum
failed. It was requested in the MIC ALGORITHM GROUP_LATCH_LOAD keyword. Patterns
are not generated for this group.
EXPLANATION:

Verify Core Isolation found conflict(s) in latch preconditioning for operations used by the
algorithm for this group. Possible problems are:
Non-conflicting preconditioning exists, but Verify Core Isolation chose a
different solution.
The macro was embedded incorrectly.
The MIC requirement for single latch load is incorrect.
USER RESPONSE:
Print the isolation using the Verify Core Isolation print isolation option to determine latch
precondition conflicts. If a valid solutions exists, Verify Core Isolation user controls
(lineholds or correspondence) can be specified to guide Verify Core Isolation. Contact
the MIC developer if the GROUP_LATCH_LOAD specification is incorrect or the
embedding logic design is invalid.
WARNING (TMT-104): Group groupnum is not a valid group number. Processing

continues.
EXPLANATION:
Isolation data for this group number does not exist.
USER RESPONSE:
Correct the group number in the selectgroup option. To print a list of valid group numbers,
run create_macro_tests with the printgroups option. The group numbers listed are
the valid group numbers which can be used with the selectgroup option.
WARNING (TMT-105):[Severe] No group(s) to process.

EXPLANATION:
None of the groups listed in the selectgroup option exist in the isolation data. Processing
terminates.
USER RESPONSE:
numbers, run create_macro_tests with the printgroups option. The group numbers
listed are the valid group numbers which can be used with the selectgroup option.
WARNING (TMT-150): No macro test patterns generated from MPR mprname, algorithm
algorithm_name.
EXPLANATION:

The MPR either did not execute any operations or the operation(s) executed did not
require any test patterns to be generated. (The small number of patterns, if any, shown
in the pattern count in the experiment statistics, were generated by the test initialization
sequence.) Processing continues.
USER RESPONSE:
If macro test patterns were expected, determine why no
create_macro_testsExecuteOperation functions are being called. Likely causes
would be incorrectly coded conditional statements, incorrect loop control, or simply
missing execute operation statements. In cases where operation(s) are being called,
determine the validity of the test algorithm and the isolation data.
ERROR (TMT-201): [Internal] Program error. No group data exists.

EXPLANATION:
A program error occurred and no group data can be found.
USER RESPONSE:
WARNING (TMT-202): [Severe] Isolation data does not exist for operation opername in
MPR mprname. Test generation for group groupnum fails. Processing continues.
EXPLANATION:
An create_macro_testsExecutionOperation function in the MPR references an
operation name which does not exist in the isolation.
USER RESPONSE:
Verify the valid operation names. Correct the create_macro_testsExecuteOperation
statement in the MPR, recompile the MPR, and rerun create_macro_tests.
WARNING (TMT-204): [Severe] Pin (or net) name in pingroup pgname has an assignment
specified in the MPR but is defined as pulse in the MIC.
EXPLANATION:
An create_macro_testsAssignValue or create_macro_testsAssignString
function in the MPR includes a pin or net which was defined in the MIC as "pulsed".
Patterns for this group will not be created. Processing continues with the next group.
USER RESPONSE:
Determine the origin of the error (MIC or MPR), recreate isolation (if it was a MIC error)
and rerun create_macro_mpr_tests.

WARNING (TMT-205): Operation opername has an invalid loopcount of loopcount

specified in the MPR. This operation is processed with loopcount set to 1.
EXPLANATION:
The create_macro_testsExecuteOperation in the MPR was called with an invalid
loopcount parameter. The loopcount is set to 1. Processing continues.
USER RESPONSE:
Correct the create_macro_tests ExecuteOperation statement in the MPR and
recompile.
ERROR (TMT-207): [Internal] Program error. Isolation data does not exist for subgroup
subgroupnum.
Group = groupnum, Operation = opernum.
EXPLANATION:
A program error occurred and no isolation data can be found for the subgroup identified
in the message.
USER RESPONSE:
ERROR (TMT-208): [Internal] MIC name micname is not found in the macro tables MIC
info cltn.
EXPLANATION:
The referenced MIC name is not in the internal program tables and therefore the program
cannot find the data for this MIC.
USER RESPONSE:
ERROR (TMT-209): [Internal] Operation opername is not found in the macro tables MIC
info cltn. MIC name = micname.
EXPLANATION:
The referenced operation name is not in the internal program tables and therefore the
program cannot find the data for this operation.
USER RESPONSE:

ERROR (TMT-210): [Internal] Pin group pgname for operation opername is not found in
the macro tables MIC info cltn. MIC name = micname.
EXPLANATION:
The referenced pin group name is not in the internal program tables and therefore the
program cannot find the data for this pin group.
USER RESPONSE:
ERROR (TMT-211): [Internal] Pingroup pgname required for operation opername is

found in the macro tables MIC info cltn but there are no pins (or nets). MIC name = micname.
EXPLANATION:
The required pin group information is not in the internal program tables and therefore the
program cannot find the data for this pin group.
USER RESPONSE:
WARNING (TMT-212): [Severe] Assigning test data for pingroup pgname, operation
opername, failed because macro index index is invalid.
EXPLANATION:
The macro index used by the MPR create_macro_testsAssignStringMacro or
create_macro_testsAssignValueMacro function is invalid because there is no
matching index found in the macro group for the operations test sequence. Processing
for this group is terminated. create_macro_tests processing continues.
USER RESPONSE:
Verify the MPR macro assignment function is using the correct macro handle. If it is,
WARNING (TMT-213): [Severe] The default value (stimval) for controllable scan chain
stimregid from pin group pgname conflicts with the default value previously specified.
EXPLANATION:
The pin group has latch correspondence in which a latch resides in a controllable scan
chain that has a default value specified from a previous
create_macro_testsAssignLatch function. However, this pin group is either trying to
set up a different default value or is not setting up a default value at all (ie. is not using
the create_macro_testsAssignLatch function). If a default value is specified for a

controllable scan chain via create_macro_testsAssignLatch, all pin groups which

contain latches in the same controllable scan chain must have the same default value
specified.
USER RESPONSE:
Correct the MPR, ensuring the correct default value for the controllable scan chain is the
same for each create_macro_testsAssignLatch function and rerun
create_macro_tests.
WARNING (TMT-250): [Severe] Test pattern generation for operation opername in group
groupnum failed.
EXPLANATION:
Test patterns for an operation could not be generated. Processing continues.
USER RESPONSE:
Check previous messages for the specific error condition that caused this operation to
fail.
WARNING (TMT-301): A stim/measure value was not assigned to pin/net name for
operation opername.
EXPLANATION:
A stim or measure value for the pin or net was not assigned by either an
create_macro_testsAssignValue or create_macro_testsAssignString function
in the MPR. A value of "X" is assumed for this pin/net. Processing continues.
USER RESPONSE:
If this test requires a valid value (0 or 1) for the pin/net, correct and recompile the MPR,
rerun create_macro_mpr_tests.
WARNING (TMT-302): A stimlatch event occurred while processing group number

groupnum.
EXPLANATION:
An create_macro_testsNotifyEvent function in the MPR causes this message to
print whenever a stim latch event occurs. Processing continues.
USER RESPONSE:
None.

WARNING (TMT-303): [Severe] A stimlatch event occurred while processing group number
groupnum. Patterns are not written for this group.
EXPLANATION:
The MPR has an create_macro_testsNotifyEvent function placed in the test
algorithm to stop processing if a stim latch event occurs.
USER RESPONSE:
Ensure that the notification of this event is called for. If this event is significant, analysis
needs to be done to determine what caused the event and how to prevent it.
WARNING (TMT-304): [Severe] A positive/negative pulse cannot be generated for

macro pin pinname. The initial value for the pin was not set or was set to an incorrect value.
This operation fails. Processing continues.
EXPLANATION:
A pulse cannot be applied because the correspondence pin has not been stimmed to the
correct stability value. Since the correspondence pin is a PI which is not a clock, the
stability value must be established before the pulse is applied.
USER RESPONSE:
Verify that the MIC has REQUIRE_STAB=yes specified for this operation, as this will
cause generation of the correct PI stim value before the pulse is applied. If this is not the
case, correct the MIC and rerun Verify Core Isolation, create_macro_tests.
WARNING (TMT-305): While processing algorithm algorithm_name, operation

operation_name, the program could not combine the preconditioning pattern containing
the Stim_PI event with the macro clock pattern containing the Pulse event because a new
pattern was generated between the two patterns. Processing continues.
EXPLANATION:
In order to combine the pre-conditioning pattern containing the Stim_PI event and the
Macro Clock pattern containing the Pulse event, no other patterns can be generated
between these two patterns.
USER RESPONSE:
Most likely, the MIC will need to be modified. Look at the TBDpatt file and find the extra
pattern(s) that was generated between the Stim_PI event and the Pulse event. The type

of event and the pins involved should tell you where in the MIC to look and what pins need
to be modified.
WARNING (TMT-306): No preconditioning Stim_PI event was generated for algorithm

algorithm_name, operation opername but the MPR requested that the preconditioning
Stim_PI event and the macro clock Pulse event be combined into the same pattern. The
macro clock Pulse will be placed in a separate pattern. Processing continues.
EXPLANATION:
In order to combine the preconditioning Stim_PI event and the macro clock Pulse event
into the same pattern, a Stim_PI event must be followed by a Pulse event with no
additional events in between.
USER RESPONSE:
Determine why a preconditioning Stim_PI event was not generated for this Algorithm/
Operation.

WARNING (TMT-400): Invalid string length specified for pingroup pgname in MPR
mprname. Processing continues.
EXPLANATION:
The length of the string of values (specified for the pingroup in an
create_macro_testsAssignString function call in the MPR) does not match the
number of pins in the pingroup. The pingroup is defined in a PINGROUP or INNERNETS
statement in the MIC for the macros in the group.
USER RESPONSE:
This is not normally a problem unless the pins without a value exist on a macro, in which
case message TMT-301 is issued. If it is a problem, check the appropriate MPR
create_macro_testsAssignString function call and MIC PINGROUP or INNERNETS
statement to determine the error. The MIC and MPR names for the group can be found
in the create_macro_tests output group summary. If the MIC and MPR were written
by a technology supplier, contact the supplier.
WARNING (TMT-401): Pingroup name pgname specified in MPR mprname does not exist
in the MIC. This pingroup assignment is ignored.
EXPLANATION:

The pingroup name specified in an create_macro_testsAssignString or

create_macro_testsAssignValue function call in the MPR does not exist in the MIC.
If the pins in the pingroup are used in a subsequent operation, they will not have a value
assigned.
USER RESPONSE:
If required assignments are missing (there will be TMT-301 messages if this is the case),
check the appropriate MPR create_macro_testsAssignString or
create_macro_testsAssignValue function call and MIC PINGROUP or INNERNETS
statements to determine the error. The MIC and MPR names for the group can be found
in the create_macro_tests output group summary. The groups algorithm name is
found in the MPR output statistics. If the MIC and MPR were written by a technology
supplier, contact the supplier.
WARNING (TMT-402): Invalid value specified for pingroup pgname in MPR mprname.
Only 1 or 0 is allowed. The value is set to x. Processing continues.
EXPLANATION:
An create_macro_testsAssignString function call (for the pin group) in the MPR
currently being processed must have only 1s or 0s in the assignment string. Each pin
corresponding to an invalid value is assigned an "x" value.
USER RESPONSE:
If required assignments are missing (there will be TMT-301 messages if this is the case),
check the create_macro_testsAssignString function calls for the pingroup in the
MPR, correct the assignment string and recompile the MPR.
WARNING (TMT-403): Invalid TBD level tbdlevelname was specified for key data in
MPR mprname. Only testerloop or testprocedure is allowed. Processing continues.
EXPLANATION:
An create_macro_testsPutTbd function call in the MPR currently being processed
has an incorrect parameter for the TBD level that the key data is associated with.
USER RESPONSE:
Check the create_macro_testsPutTbd function calls for the invalid TBD level, correct
the TBD level and recompile the MPR.
WARNING (TMT-404): [Severe] Invalid macro handle was specified in MPR mprname,
while processing group number groupnum. Processing continues.
EXPLANATION:

The macro handle input parameter to an MPR function call was invalid. The error is in
one of the function calls (create_macro_testsGetMacroCellName,
create_macro_testsGetMacroAttributeData,
create_macro_testsGetRomWordData). Determine the cause of the invalid macro
handle and recompile the MPR.
USER RESPONSE:
Determine the cause of the invalid macro handle and recompile the MPR.
WARNING (TMT-405): [Severe] Macro handle data for group number groupnum is
corrupted. An error in the code for MPR mprname caused the problem. Processing
continues.
EXPLANATION:
The macro handle data obtained in the MPR when the
create_macro_testsGetMacroHandles function was invoked has been damaged
while the MPR was being processed by create_macro_tests. The data was probably
overwritten by code in the MPR.
USER RESPONSE:
Determine the MPR code error and recompile the MPR.
WARNING (TMT-406): Invalid event type type specified for an

create_macro_testsNotifyEvent function call in MPR mprname. Processing continues.
EXPLANATION:
The create_macro_testsNotifyEvent function supports only notification of the
"STIMLATCH" event.
USER RESPONSE:
Check the event parameter for the create_macro_testsNotifyEvent function calls in
the MPR. Correct the parameter and recompile the MPR.
WARNING (TMT-407): Invalid severity type severity specified for an

EXPLANATION:
The create_macro_testsNotifyEvent function supports only the WARNING [Severe]
severity code.
USER RESPONSE:

Check the severity parameter for the create_macro_testsNotifyEvent function calls

in the MPR. Correct the parameter and recompile the MPR.
WARNING (TMT-408): Invalid status type type specified for an

EXPLANATION:
The create_macro_testsNotifyEvent function accepts only "ON" and "OFF" for the
status parameter.
USER RESPONSE:
Check the status parameter for the create_macro_testsNotifyEvent function calls in
the MPR. Correct the parameter and recompile the MPR.
WARNING (TMT-409): The ROM romname has no contents data. All ROM data bits
returned by the create_macro_testsGetRomWordData function are X. Processing
continues.
EXPLANATION:
The ROM personality CONTENTS file for the macros being processed could not be
found. Possible errors:
The ROM CONTENTS file path was incorrectly specified when running the
Encounter Test IMPORT application.
The CONTENTS attribute for the ROM that specifies the ROM CONTENTS file
is missing or incorrect.
USER RESPONSE:
Check the IMPORT ROM CONTENTS file path and the ROM CONTENTS file attribute.
Correct any errors, rerun IMPORT and reprocess the design.
WARNING (TMT-410): [Severe] A ROM was not found for macro macroname, but ROM
data was requested by the MPR. Test generation for group groupnum fails.
EXPLANATION:
A ROM primitive could not be found inside the macro. The macro cell definition may not
have included the ROM. Possible errors are missing rules or a cell in the macro that
should have contained the ROM has no contents.
USER RESPONSE:

Correct the macro cell definition and reprocess the design.
WARNING (TMT-411): Data for macro attribute attributename was requested by the
MPR but no data exists for the attribute. Processing continues.
EXPLANATION:
No data exists for the macro attribute listed in the message. In this case, a NULL pointer
is returned by the create_macro_testsGetMacroAttributeData function. This may
cause problems (such as an unexplained termination of the create_macro_tests
run) on some platforms if the NULL pointer is used for an argument in C Library functions.
USER RESPONSE:
If this is causing a problem with create_macro_tests, determine if you should have
a condition where no attribute data exists. In cases where this is possible, the return
value should be checked by the MPR and processed accordingly.
WARNING (TMT-412): Invalid status type type specified for

create_macro_testsMeasureCurrent function call in MPR mprname. Processing
continues.
EXPLANATION:
The create_macro_testsMeasureCurrent function accepts only "YES" and "NO" for
the status parameter.
USER RESPONSE:
Check the status parameter for the create_macro_testsMeasureCurrent function
calls in the MPR. Correct the parameter and recompile the MPR.
WARNING (TMT-413): Invalid controllable scan chain default value specified in

create_macro_testsAssignLatch function for pin group opername, MPR groupnum.
Supported values are 0/1/X/SCAN_0/SCAN_1. controllable scan chain default value is set to
X. Processing continues.
EXPLANATION:
The controllable scan chain default value specified in the
create_macro_testsAssignLatch function supports only a value of "0", "X", "1",
"SCAN_0", or "SCAN_1". (Although "X" is a valid value, it has no affect since the default
is X.)
USER RESPONSE:
Correct the MPR and rerun create_macro_tests.

WARNING (TMT-414): Invalid status type type specified for

create_macro_testsCombinePrecPatterns function call in MPR mpr_name. Processing
continues.
EXPLANATION:
The create_macro_testsCombinePrecPatterns function accepts only "ON" and
"OFF" for the status parameter.
USER RESPONSE:
Check the status parameter for the create_macro_testsCombinePrecPatterns
function calls in the MPR. Correct the parameter and recompile the MPR.
ERROR (TMT-420): [Internal] Unable to get macro block information from macro block
handle index macro_handle.
EXPLANATION:
USER RESPONSE:
ERROR (TMT-421): [Internal] Unable to find pin name pin_name on macro block handle
macro_handle.
EXPLANATION:
This is most likely an MPR program error.
USER RESPONSE:
ERROR (TMT-422): [Internal] Unable to find the source macro block for pin name
pin_name on macro block handle macro_handle.
EXPLANATION:
USER RESPONSE:
WARNING (TMT-423): Invalid message severity severity in MPR message number

message_number. Valid severity values are I, W, S, P, and E.

EXPLANATION:
This is an MPR program error.
USER RESPONSE:
WARNING (TMT-450): [Severe] Unable to initialize the simulator. Refer to preceding

simulator messages.
EXPLANATION:
The MPR requested state information on a pin which required that the simulator be
initialized but the simulator initialization was unsuccessful.
USER RESPONSE:
Use the preceding simulator messages to analyze the problem.
WARNING (TMT-500): [Severe] Cannot find algorithm algorithm_name in MPR

mprname.
EXPLANATION:
The algorithm for the macro group currently being processed by create_macro_tests
cannot be found in the MPR residing in the directory specified in the
create_macro_tests MPRPATH parameter. Possible errors are:
The MPR was incorrectly specified in the MIC ALGORITHM statement
MPR_NAME keyword.
An incorrect level of the MPR was found in the directory specified in the
create_macro_tests MPRPATH parameter.
Test patterns for this macro group will not be generated.
USER RESPONSE:
Correct the MIC, MPR or MPRPATH parameter. Recompile the MPR if it was incorrect.
WARNING (TMT-501): [Severe] Cannot load API library libname. Internal error:
codenum Check LIBPATH.
EXPLANATION:

The API library "TMTApi.o" does not exist in the library path specified by LIBPATH. Test
patterns for this group will not be generated.
USER RESPONSE:
Ensure the API library exists in the LIBPATH.
WARNING (TMT-502): [Severe] Cannot load MPR mprname, library libname. Internal
error: codenum
EXPLANATION:
create_macro_tests is attempting to load the MPR that contains the algorithm for
this macro group. If the Internal error listed is Exec format error the most likely cause is
that the identified MPR was compiled on a different platform than the one on which the
job was running. Obtain the MPR compiled on the platform that you wish to run on. The
other likely cause is that the MPR was not found in the MPR library path.
Test patterns for this group will not be generated.
USER RESPONSE:
Correct the create_macro_tests MPRPATH parameter and rerun.
WARNING (TMT-503): [Severe] Cannot bind MPR library libname to API library. Internal
error: codenum
EXPLANATION:
create_macro_tests had difficulty processing the MPR.
USER RESPONSE:
If the internal error code is 12, run the job on a machine with more memory. If the error
code is 22, contact customer support (see Contacting Customer Service on page 23).
ERROR (TMT-504): [Internal] Failure detected in obtaining list of object file names. Check
internal buffer size. Internal error: codenum
EXPLANATION:
USER RESPONSE:
ERROR (TMT-505): [Internal] Invalid magic number in file header for filename.
EXPLANATION:


USER RESPONSE:
ERROR (TMT-506): [Internal] The auxiliary file header is not available in filename.
EXPLANATION:
USER RESPONSE:
ERROR (TMT-507): [Internal] Invalid magic number in auxiliary file header of filename.
EXPLANATION:
USER RESPONSE:
WARNING (TMT-508): [Severe] Cannot find MPR mprname, library libname. Check
MPRPATH.
EXPLANATION:
create_macro_tests is attempting to load the MPR that contains the algorithm for
this macro group. The MPR was not found in the library path. Test patterns for this group
will not be generated.
USER RESPONSE:
Correct the create_macro_tests MPRPATH parameter.
WARNING (TMT-509): [Severe] MPR mprname exited. Cannot recover.

EXPLANATION:
An exit function occurred while the algorithm in the MPR was executing. Test patterns for
this group will not be generated.
USER RESPONSE:
If the exit function call is in the MPR and is not desired remove it. If the exit is not in the
MPR, contact customer support (see Contacting Customer Service on page 23).

ERROR (TMT-520): [Internal] Error building generic message number

message_number.
EXPLANATION:
USER RESPONSE:
Contact customer support (see Contacting Customer Service on page 23) and
communicate the message number.
ERROR (TMT-521): [Internal] Message number message_number has an incorrect

number of arguments.
EXPLANATION:
USER RESPONSE:
Contact customer support (see Contacting Customer Service on page 23) and
communicate the message number.


54
TND - Good Machine Delay Simulation
Messages
TND-001 through TND-600 on page 1683

TND-001 through TND-600

INFO (TND-001): Start DynaSim simulator version (Version) The flat model is | is
not reduced. Time: simulation wall clock start time
EXPLANATION:
This message is intended to provide only information and does not denote an error
condition. The Version: field provides a unique code level identifier that can be used
when communicating with customer support personnel. The simulation start time field
provides the time at which DynaSim started processing. This can be used in conjunction
with other time stamped messages produced by the simulator to gauge simulator
progress vs. elapsed time.
USER RESPONSE:
WARNING (TND-401): [Severe] number of active clock nets Primary Input

clocks were active during Stim or Pulse event odometer. Simulation will be done with
the clocks overlapped. There may be incorrect results if there are races in the design.
EXPLANATION:

TND - Good Machine Delay Simulation Messages
USER RESPONSE:
Use one of the following approaches:
INFO (TND-415): Starting simulation of the test section at TBD location TBD loc. The test
section type is tsect type. The tester termination is tester term. The dom term
termination will dominate. Treatment of X for miscompares
EXPLANATION:
condition. The message indicates that simulation of a test section is about to begin, and
denotes the attributes of the test section. The treatment of X for measure compares field
indicates how measure values of X in the input pattern data will be treated with respect
to performing compares between these measure values and the measure values found
by DynaSim. Incoming logic X values will either be ignored - no compare attempted at
these measure points - or utilized - the X is compared against DynaSims measure value.
Whether X values are ignored or used depends on the setting of the "Ignore Measures
at X" control option.
USER RESPONSE:
None.
INFO (TND-420): Starting simulation of the pattern group at TBD location TBD loc.
EXPLANATION:
condition. The message indicates that simulation of a group of patterns is about to begin.
The pattern group field denotes what the group consists of, e.g., a test procedure. TBD
loc indicates where in the input pattern data the pattern group is located.
USER RESPONSE:
None.

INFO (TND-435): Sequence sampling has been requested. Only the first n Test Sequences
in each Test Procedure will be simulated.
EXPLANATION:
condition. The message indicates that the full set of input patterns will not be simulated.
Instead, the first n test sequences in each test procedure will be simulated. Note that only
the simulated sequences will have data written to the output TBD file.
USER RESPONSE:
None.
INFO (TND-450): Initial Simulator State restored from filename.

EXPLANATION:
condition. The message indicates that the device under test (DUV) state has been
restored from the uncommitted file filename.
USER RESPONSE:
None.
INFO (TND-451): Final Simulator State saved to filename.

EXPLANATION:
condition. The message indicates that the Dynasim design state has been saved to the
uncommitted file filename.
USER RESPONSE:
None.
WARNING (TND-452): [Severe] Restore States error. diagnostic.

EXPLANATION:
This message means that an error was detected while reading TNDstate (the saved state
file) for a DynaSim restore state operation. The diagnostic field indicates the nature of
the error. Typically, errors are introduced into the saved state file when the file is edited.
USER RESPONSE:
First, verify that the file filename does exist. The error might be as simple as entering the
wrong name. If not, and the saved state file was edited, use the diagnostic message to

determine where the error was introduced. Then correct the problem in the file and run
the simulation again. If the saved state file has not been edited since it was created by
the simulator and your filename is correct, contact customer support (see Contacting
WARNING (TND-453): Save States error. diagnostic. Save not done.

EXPLANATION:
A failure occurred while attempting to create or write to the simulator save state file
TNDstate. The diagnostic field indicates the nature of the error.
USER RESPONSE:
Check the WORKDIR directory and ensure that you have sufficient access authority to
create files therein.
ERROR (TND-454): Unexpected End of Restore File. Processing terminates.

EXPLANATION:
The end of the saved state file (TNDstate) was encountered prematurely during a
DynaSim restoreState. Expected data is missing.
USER RESPONSE:
The TNDstate file was corrupted, probably by a user edit of the file. If so, the user should
attempt to repair the damage with another edit.
Keep in mind that its a good idea to backup the file before doing an edit. If the saved state
file was not edited since it was created by the simulator, contact customer support (see
ERROR (TND-500): The value parameter value specified for control parameter
parm is not valid. Valid values for this parameter are value range. Processing
terminates.
EXPLANATION:
USER RESPONSE:
Specify a different value for the indicated parameter in the range value range. Refer to
"analyze_vectors in the Encounter Test: Reference: Commands for additional
information.
ERROR (TND-501): Unrecognized keyword keyword following parm parm


EXPLANATION:
USER RESPONSE:
Specify a different value for the indicated parameter. Refer to "analyze_vectors in the
Encounter Test: Reference: Commands for
ERROR (TND-503): pulsexlimit must be specified to be a value that is greater than or equal
to pulserejectlimit. Processing terminates.
EXPLANATION:
The parameter pulsexlimit has been specified to a value that is less than pulserejectlimit.
These settings are not plausible. The pulsexlimit parameter is used to control the
conversion of pulses that are equal to or wider than pulserejectlimit, but less than
pulsexlimit, into X pulses. It does not make sense to specify pulsexlimit to be less than
pulserejectlimit.
USER RESPONSE:
Specify pulsexlimit to be greater than or equal to pulserejectlimit.
ERROR (TND-506): Insufficient memory to continue simulation. Processing terminates.

Failed allocation: allocation name.
EXPLANATION:
There is not enough memory to run this simulation.
USER RESPONSE:
Run the simulation on a machine with more memory or increase the amount of memory
available on this machine.
ERROR (TND-507): Unable to load the flat design model. Processing terminates. Verify that
your setting of WORKDIR is correct.
EXPLANATION:
The simulator was unable to load the design model.
USER RESPONSE:
Verify that the specified settings are correct and that the design model does exist (file
name flatModel). If both are true and the problem persists, contact customer support

ERROR (TND-508): Unable to load the design delay model. Processing terminates. Verify
that your setting of WORKDIR and delayModel is correct.
EXPLANATION:
The simulator was unable to load the delay model.
USER RESPONSE:
Verify that the specified settings are correct and that the delay model does exist (file
name delayModel.<delayModel>). If both are true and the problem persists, contact
WARNING (TND-509): An unknown primitive type was encountered. The type is block
EXPLANATION:
A block function not supported by DynaSim was found on block block name. The block
will not be simulated and its outputs will always be assumed to be at X. The test coverage
achieved for this design may be adversely affected.
USER RESPONSE:
WARNING (TND-510): An invalidly specified primitive type was encountered. The type is
primitive_type, and was found on block block_name. The block output(s) will be held
at X.
EXPLANATION:
The program detected an invalidly specified primitive type on the referenced block.
USER RESPONSE:
WARNING (TND-511): An unsupported primitive type was encountered. The type is block
EXPLANATION:
A block function not supported by DynaSim was found on block block name. The block
will not be simulated and its outputs will always be assumed to be at X. The test coverage
achieved for this design may be adversely affected.

USER RESPONSE:
WARNING (TND-520): Unable to create the diagnostic failset failset name. No TBDfail
file will be produced by this run. Ensure that the design parameters specified are correct, that
there is sufficient space in the file system and that file permissions are set correctly.
EXPLANATION:
The simulator was unable to create a diagnostic failset for recording miscompare data.
The creation of this data results in a TBDfail file that enables the use of the Encounter
Test Diagnostics analysis tools. The use of these tools will not be possible for any
miscompares that are encountered in this run.
USER RESPONSE:
Ensure that the design parameters specified are correct, that there is sufficient space in
WARNING (TND-530): The input TBD has a Tester_Loop with the

procedures_have_memory attribute that contains a Test_Procedure that does not have the
sequences_have_memory attribute. The simulator will proceed as if the
sequences_have_memory attribute was present. Test_Procedure tbd loc.
EXPLANATION:
It is contradictory to have procedures_have_memory and not sequences_have_memory.
procedures_have_memory implies that the design state is not reset at Test_Procedure
boundaries. However, if sequences_have_memory is not present, the design state will
be reset at every test sequence boundary, i.e., the first Test_Sequence in each
Test_Procedure, which is effectively at the Test_Procedure boundary.
USER RESPONSE:
If the patterns were manually generated, ensure that it is truly the intent to specify
procedures_have_memory. If so, modify your patterns to also specify
sequences_have_memory. If these patterns were generated by an Encounter Test
automatic test generator, contact customer support (see Contacting Customer Service
on page 23).
INFO (TND-534): One or more delays lack transition type. The delays are ignored.

EXPLANATION:
The delay cannot be used unless the transition type (rise/fall) is given along with the
delay. This is often deliberately done for delays which will not be used. The delay is
ignored. This message prints only once.
USER RESPONSE:
INFO (TND-550): The table name table overflowed and was reallocated in Memory.
EXPLANATION:
Some TND table sizes are unpredictable. If the allocated table size is about to be
exceeded, TND will allocate a larger area, copy the data from the old table to the new
and free the old area.
USER RESPONSE:
If you notice that the reallocation takes place frequently, notify customer support (see
Contacting Customer Service on page 23) so that the initial allocation can be increased
to reduce the chance of overflow and reallocation.
WARNING (TND-555): The wire delay from From pin name to To_pin_name has
multiple values:
EXPLANATION:
The delay model may contain several values for a wire delay depending on the type of
logic change on the wire, e.g.,a 0>1 delay may differ from a 1>>0 delays. To save space
and runtime, TND uses only a single value for all changes on a particular wire in the TND
run-time delay model. If the values in the "real" delay model differ, the run-time model
uses the average delay.
USER RESPONSE:
If the spread of the delays is small enough to justify the use of the mean, no action is
required. If the spread is large and could influence results, contact customer support
WARNING (TND-570): The initial design state parameter has been specified to a value
other than X. Correct simulation results cannot be guaranteed.
EXPLANATION:
You have requested that the initial state of the design be set either to all 0s or all 1s. This
may result in incorrect simulation results (measures and test coverage).

USER RESPONSE:
If the parameter was intentionally set, no response is required. If this option was
accidentally specified you MUST run the simulation again with an initial design state of X.
INFO (TND-575): The following nets and pins will have all change events recorded for them
for the input test pattern range: start loc to stop loc.
EXPLANATION:
condition. The message tells you where Dynasim will start and stop watching nets and
pins, and lists the nets and pins to be watched.
USER RESPONSE:
INFO (TND-576): The following nets and pins will have all change events recorded for them
for the input test pattern range(s) as specified by the input TBD:
EXPLANATION:
condition. The message tells you which nets and pins the simulator will be watching, and
that the starting and stopping of watching will be controlled by WATCH=ON,
WATCH=OFF statements in the input TBD.
USER RESPONSE:
INFO (TND-585): Net watching action at TBD location TBD loc.

EXPLANATION:
condition. The message indicates that Dynasim has either started or stopped recording
net change information (a waveform) at the specified TBD location. If the start or stop
point printed does not exactly match your specified watchstart or watchstop
specification, it means that the location you specified does not exist in the TBD. Starting
or stopping occurs at the next greater location.
USER RESPONSE:
INFO (TND-600): DynaSim simulator ended. Timestamp: date/time Simulation

signature: sim sig

EXPLANATION:
condition. The message indicates that Dynasim has completed processing. The
simulation signature field is useful to DynaSim developers in diagnosing problems.
USER RESPONSE:
None.

INFO (TND-601): DynaSim simulator ended. WARNINGS were issued during the
simulation. Review the preceding messages to determine the cause.
Simulation signature: signature
EXPLANATION:
This message indicates that simulation has completed, but that warning messages were
issued during the run. The simulation signature field is useful to DynaSim developers in
diagnosing problems.
USER RESPONSE:
Review the warning messages that were issued and assess whether they represent an
INFO (TND-602): DynaSim simulator ended. ERRORS were encountered during the
simulation. Review the preceding messages to determine the cause.
EXPLANATION:
This message indicates that simulation has completed, but that error messages were
issued during the run. The simulation signature field is useful to DynaSim developers in
diagnosing problems.
USER RESPONSE:
Review the error messages that were issued and assess whether they represent an
INFO (TND-603): DynaSim simulator ended. The simulation FAILED. Review the preceding
messages to determine the cause.
EXPLANATION:

This message indicates that simulation has did not successfully complete and generated
no results. The simulation signature field is useful to DynaSim developers in diagnosing
problems.
USER RESPONSE:
Review the error messages that were issued and determine the cause of failure. Take the
appropriate action to correct the failing condition(s).
INFO (TND-620): A pulse has been eliminated on net net name, at TBD location TBD
loc. The pulse width was n ps. The pulse shape was start val -> to val -> end
val.
EXPLANATION:
A pulse (glitch) was eliminated on net name that violated the pulse rejection limit
specified via the global pulserejectlimit control. Simulation proceeds as though the
pulse did not occur.
USER RESPONSE:
Verify that glitches on this net are expected and do not represent a problem with the
design or input test patterns.
INFO (TND-630): A pulse has been changed to X on net net name, at TBD location TBD
loc. The pulse width was n ps. The pulse shape was start val -> to val -> end
val.
EXPLANATION:
A pulse was changed to X on net name. The pulse violated the pulse X limit specified
via the global pulsexlimit control. Simulation proceeds with the signal set to X for the
duration of the pulse.
USER RESPONSE:
Verify that glitches on this net are expected and do not represent a problem with the
design or input test patterns.
WARNING (TND-700): A good machine oscillation has been detected on net net name at
TBD location TBD loc. The good machine logic value is set to X on this net.
EXPLANATION:
The indicated net changed value more times than the specified Good Machine
Oscillation Threshold (default is 254) for a single stimulus event. Typically this indicates
that the given net is part of an oscillating feedback design. In rare cases, the specified

net may not actually be oscillating and may legitimately need to change value more times
than the GM oscillation threshold.
USER RESPONSE:
If you believe that the design cannot oscillate, try increasing the GM Oscillation
Threshold value. The largest possible value for this parameter is 65535. Simulation run
time may increase when this parameter is increased.
WARNING (TND-710): [Severe] One or more miscompares have been detected for the
event type event at TBD location TBD loc. miscompare details
EXPLANATION:
states expressed in the input TBD patterns vs. design states predicted by DynaSim.
Miscompares may come about in two ways. First, if the input TBD includes Expect
events, DynaSim will compare the design node values in the Expect event to those
currently in DynaSims design state. If they do not match, a miscompare message is
issued. Second, if the Compare at Measure Commands option is selected, DynaSim will
compare the values in the input TBDs Measure Events to the measure values that will
be produced for the same measure event by DynaSim. A difference results in a
miscompare message. The event type field in the message indicates the kind of event at
which the miscompare occurred. The Expected logic val is the value that was predicted
in the input TBD event. The Found logic val is the value that DynaSim achieved.
USER RESPONSE:
Since a miscompare indicates the potential for failure of the test data at the tester,
investigation is required to determine its cause.
WARNING (TND-712): [Severe] A miscompare has been detected for the PO Measure
event at TBD location TBD loc at time n ps. The corresponding pin timing event is in
sequence definition seq def name for event # m.
@ netname - Expected: Lexpect val Found: Lfound val net index
EXPLANATION:
states expressed in the input TBD patterns vs. design states predicted by DynaSim. This
miscompare occurred at a primary output, and was triggered by a timed PO measure in
the dynamic pattern indicated by the TBD loc field.
The expect val is the value that was predicted in the input TBD event. The found val is
the value that DynaSim achieved.
USER RESPONSE:

Since a miscompare indicates the potential for failure of the test data at the tester,
investigation is required to determine its cause.
WARNING (TND-720): A Hard 3-state contention has been detected on net net name at
TBD location TBD loc, net index
EXPLANATION:
A net with multiple sources (i.e., a wired or dotted net) is being driven by conflicting strong
values - 0 vs. 1 or 1 vs. 0. The design may be damaged by this condition.
USER RESPONSE:
The offending test patterns should be removed from the input test data and the
simulation run again.
WARNING (TND-721): A Soft 3-state contention has been detected on net net name at
EXPLANATION:
A net with multiple sources (i.e., a wired or dotted net) is being driven by an X and a
strong known value - X vs. 1 or X vs. 0. The design may be damaged by this condition.
USER RESPONSE:
WARNING (TND-722): An all X 3-state contention has been detected on net net name at
EXPLANATION:
A net with multiple sources (i.e., a wired or dotted net) is being driven by an X and a
strong known value - X vs. 1 or X vs. 0. The design may be damaged by this condition.
USER RESPONSE:
WARNING (TND-739): [Severe] The following TND-740 message is caused by an

IGNORE MEASURE specified for the measure net.
EXPLANATION:
latchXremove and/or poXremove are/is set and an IGNORE MEASURE attribute is set
for the measure net. An IGNORE MEASURE forces a nets measure to be X.

USER RESPONSE:
Remove either the ignore or the Xremove.
WARNING (TND-740): The Measure event at input TBD odometer measured an X on

net name net type, Flat index: flat model index
EXPLANATION:
latchXremove and/or poXremove are/is set and a measure X was detected.
USER RESPONSE:
Analyze the situation to find the cause of the X.
WARNING (TND-750): A timing check violation was detected. The check was:
timing_check_violation
EXPLANATION:
A timing check specified in the Standard Delay File (SDF) for this design was violated by
the test patterns. Simulation proceeds. This test pattern may cause a failure at the tester.
USER RESPONSE:
The offending test patterns should be analyzed and corrected. If these patterns were
generated by an Encounter Test automatic test generator, contact customer support (see
WARNING (TND-755): A timing check margin violation has been detected. The check was:
EXPLANATION:
The timing check as specified in the Standard Delay File (SDF) for this design was
satisfied, however, the user specified timing check margin was violated. Simulation
proceeds. This test pattern may not provide sufficient margin to operate correctly across
a wide range of design delays and/or tester accuracies in manufacturing.
USER RESPONSE:
The offending test pattern should be analyzed and corrected. If these patterns were
WARNING (TND-760): A timing check with negative values has been detected. DynaSim
does not currently support negative timing checks.
EXPLANATION:

A timing check specified in the Standard Delay File (SDF) has a negative value. DynaSim
does not currently support timing checks with negative values. This check will not be
performed.
USER RESPONSE:
If you believe the execution of this check is critical to producing error-free test patterns,
WARNING (TND-770): A path delay with a negative value was encountered. Path input
pin name -> output pin name on cell cell name. The delay value was m ps. The
delay is set to 0 ps. No further messages will be issued for this condition, but all negative path
delays will be set to 0 ps.
EXPLANATION:
A path delay specified in the Standard Delay File (SDF) has a negative value. This is not
valid for simulation. The delay is treated as zero picoseconds.
USER RESPONSE:
Find out why the SDF is being produced with negative path delays and correct the
situation at the source.
WARNING (TND-775): The SDF for this design specifies one or more negative cell path
delays. All such delays will be treated as zero (0 ps). If miscompares occur in this run and if
any negative delay paths were utilized, message TND-776 will be produced at the end of this
run.
EXPLANATION:
A path delay specified in the Standard Delay File (SDF) has a negative value. This is not
valid for simulation. The delay is treated as zero picoseconds.
USER RESPONSE:
Find out why the SDF is being produced with negative path delays and correct the
situation at the source, as needed.
WARNING (TND-776): During the course of this run, one or more cell paths were utilized
for which a negative delay is specified in the SDF. These paths are treated as zero delay by
DynaSim. The usage of these negative delay paths may be connected to the occurrence of
miscompares in this run. To get information on the specific negative delay paths that were
traversed, specify the option report=negativepaths and resimulate.
EXPLANATION:

During the course of the run, DynaSim determines if any negative delay path is used
during the propagation of values through the design. If so, and if the run produces
miscompares, this message is produced. Note that the negative path delays may or may
not have any bearing on the miscompares. That can only be determined by additional
investigation.
USER RESPONSE:
The recommended course of action is to extract one of the test sequences that produce
a miscompare utilizing the Test Data Analysis tool. Resimulate this sequence with a
watch list that includes nets, blocks and pins that are in the back trace cone from the
miscompare point (latch or PO). Specify the option report=negativepaths when you
perform the resimulation. This will cause a message to be produced for each instance of
a negative delay path being utilized. These messages can be used in conjunction with
the Test Data Analysis Tool and SimVison to determine if the negative paths are involved
in causing the miscompares.
WARNING (TND-777): The SDF for this design specifies an interconnect greater than
65535 picoseconds. This is excessive for an interconnect delay and thus will be truncated to
65535 picoseconds.
The delay start point was: pinName
EXPLANATION:
An interconnect delay specified in the Standard Delay File (SDF) has a delay value
greater than 65535 picoseconds. This is excessive for a single interconnect delay, and is
beyond the expected range of values for this simulator. The delay is treated as the largest
interconnect delay value that can be handled by this simulator (65535 picoseconds).
USER RESPONSE:
Determine the cause for the SDF is being produced with large interconnect delays and
correct the situation at the source, as needed.
WARNING (TND-780): A path through a cell has been used but the SDF did not specify a
delay for this path. The path is input pin name -> output pin name,
transition vals on cell/block cell nameINSERT/block name. The default
cell output delay value of n ps was used. The TBD location is TBD loc.
EXPLANATION:
When propagating signal values through a cell, a path was followed for which there was
no delay defined in the SDF. This indicates that the SDF is missing a delay for this path.
It may be missing because it is not included in the cell definition. For cells that have some
path delays specified, DynaSim computes a default delay value to use for those paths
that are unspecified. This is simply the average of all the specified path delays for the cell
output. This value was used for the unspecified path delay.

USER RESPONSE:
Find out why the SDF does not contain a delay for this path and, if necessary, correct the
WARNING (TND-785): A path through a cell has been utilized for which the SDF specified
a negative delay. The path is input pin name -> output pin name, transition vals
on cell/block cell name/block name. A delay value of 0 ps was used instead. The TBD
location is TBD loc.
EXPLANATION:
When propagating signal values through a cell, a path was followed for which the SDF
specified a negative delay. This path was simulated with a delay value of zero.
USER RESPONSE:
If the run produces miscompares, use the information in this message to aid in
determining if the negative delay value being treated as zero could be the cause of the
miscompares.
WARNING (TND-790): The simulator propagated through a delay cell for which there are no
delays on the SDF.
The delay cell is cell name
The hier block is block name
A cell path delay of 0 ps was used. The TBD location is TBD loc.
EXPLANATION:
A delay cell through which the simulator propagated a signal had no SDF cell delays. A
delay value of zero picoseconds was used for the path through the cell.
USER RESPONSE:
Find out why the SDF does not contain delays for this cell and, if necessary, correct the
ERROR (TND-799): While Watching Nets an implicit Measure was needed. The pattern at
TBD location tbd_location. tried to generate an implicit Measure, as directed by the
TDR. Doing so would cause the Scope Data File and TBD to lose synchronization.
EXPLANATION:
USER RESPONSE:

A work-around is to make 2 TND runs: the first run with no Watch Nets will insert the
implicit Measures into the Output TBD; the second run can use the output TBD from the
first run as input and do the Net Watching.

ERROR (TND-800): Input pattern error encountered. The Begin Loop pattern at TBD
location TBD loc. contains no repeat event to specify the number of loop iterations.
EXPLANATION:
USER RESPONSE:
performed.
ERROR (TND-805): Input pattern error encountered. The Begin Loop pattern at TBD
location TBD loc. contains an event other than the repeat event. This is an invalid construct.
EXPLANATION:
USER RESPONSE:
specified.
WARNING (TND-810): [Severe] Input pattern error encountered. The design was not left
in the stability state at the end of an independent test. The independent test is the test
entity at TBD location TBD loc. Invalid test data may result. The following pins were in
error:
EXPLANATION:
When a test mode specifies test function pins and their stability values, these pins must
be at their stability value at certain boundaries in the test patterns. These boundaries are
determined by the attribute procedures_have_memory on the Tester Loop and
sequences_have_memory on the Test Procedure. When such a boundary is
encountered (the start of an independent test - i.e., a test that begins with a reset to
stability), the simulator assumes that the design is in the stable state. If this is not true,
then correct simulation measures will not be achieved. For this reason, the run is

terminated when this condition is detected. The message indicates the pin type and its
name, its stability value and the current value seen by DynaSim.
USER RESPONSE:
The input patterns must be corrected to leave the design in stability state at the end of
each independent test (i.e., Test Procedure or Test Sequence, depending on the setting
of your "_have_memory" attributes). If these are manually generated patterns, use the
"pins in error" information to correct the patterns. If these patterns were generated by an
Encounter Test automatic test generator, contact customer support (see Contacting
WARNING (TND-812): [Severe] Input pattern error encountered. The design was not in the
stability state when an event requiring a scan operation was encountered. The event is the
scan event at TBD location TBD loc. Invalid test data may result. The following pins
were in error:
EXPLANATION:
The scan operation is designed to take the design from the test generation (TG) stability
state to the scan state, prior to the actual scan. If the design is not in the TG stability state
when the scan operation is invoked, the design may not scan correctly. The pins that are
not at their stability value are listed in the message. The message indicates the pin type
and its name, its stability value and the current value seen by DynaSim.
USER RESPONSE:
The input patterns must be corrected. If these are manually generated patterns, use the
"pins in error" information to correct the patterns.
If these patterns were generated by an Encounter Test automatic test generator, contact
WARNING (TND-815): Input pattern error encountered. Unrecognized event type event
type encountered at TBD location TBD loc. The event type is ignored.
EXPLANATION:
The event specified in the message is not supported by DynaSim. Processing will
continue, but the event is ignored.
USER RESPONSE:
If the patterns were manually generated, be aware that the specified event will not
influence the simulation results. If these patterns were generated by an Encounter Test
on page 23).

ERROR (TND-820): Unsupported test section type tsect type was encountered at TBD
location TBD loc. Processing terminates. Eliminate this test section from the input patterns
EXPLANATION:
DynaSim does not support this type of test section.
USER RESPONSE:
ERROR (TND-825): Unsupported test type type was encountered at TBD location TBD
loc. Processing terminates. Eliminate this test section from the input patterns and run the
simulation again.
EXPLANATION:
DynaSim does not support this test type.
USER RESPONSE:
WARNING (TND-830): The termination domination value on the test section at TBD location
TBD loc conflicts with the value in the Tester Description Rule. The TDR specification is
term dom x, but the TBD specifies term dom y. term dom y domination will
be assumed by the simulator.
EXPLANATION:
See the message text. The term dom field denotes that either the Tester or Product
termination will dominate.
USER RESPONSE:
Ensure that you genuinely wish to override the termination domination as specified by
the Tester Description Rule.
WARNING (TND-834): [Severe] A Test Inhibit (TI) pseudo-primary input was pulsed away
from its stability value at TBD location TBD loc. The TI is pin name. The stability value is
logic val.
EXPLANATION:

the data.
USER RESPONSE:
to override a Test Inhibit pin. If these patterns were generated by an Encounter Test
on page 23).
WARNING (TND-835): A Test Inhibit (TI) primary input has been stimulated away from its
stability value at TBD location TBD loc. The TI is pin name. The stim value is logic
val and the stability value is logic val.
EXPLANATION:
USER RESPONSE:
on page 23).
WARNING (TND-836): [Severe] A Test Inhibit (TI) primary input was pulsed away from its
stability value at TBD location TBD loc. The TI is pin name. The stability value is logic
val.
EXPLANATION:
the data.
USER RESPONSE:
on page 23).
WARNING (TND-840): The global termination value on the test section at TBD location TBD
loc violates Tester Description Rule specified constraints. The TDR specification is term

x, whereas the TBD specifies term y. A termination of term y will be assumed by

the simulator.
EXPLANATION:
USER RESPONSE:
to override the Tester Description Rule termination. If these patterns were generated by
an Encounter Test automatic test generator, contact customer support (see Contacting
WARNING (TND-846): TBD location TBD loc stims a non-contacted pin but no PMUs are
available. The PI is pin name. The stim was simulated.
EXPLANATION:
When the number of Full Function tester pins is less than the number of product pins and
there are no parametric measuring units (PMU) available, the patterns may not stim an
uncontacted PI.
USER RESPONSE:
Tester Description Rule (TDR) tester pins limits. If these patterns were generated by an
Encounter Test automatic test generator, contact customer support (see Contacting
WARNING (TND-847): TBD location TBD loc changes the Output Inhibit state and stims
other pins. The OI is pin name
EXPLANATION:
The Output Inhibit control pin is being changed in the same pattern as other primary
inputs. The changing of Output Drivers can generate sufficient electrical noise to corrupt
latch values in the design.
USER RESPONSE:
If the patterns were manually generated and it is believed not to be a potential problem,
no change is needed. If the patterns were generated by an Encounter Test automatic test
generator, contact customer support (see Contacting Customer Service on page 23).

WARNING (TND-848): TBD location TBD loc changes a Clock with the Output Inhibit
pin(s) not at stability value. The clock is pin name.
EXPLANATION:
This allows the Output Drivers to change at the same time as clocks. The electrical noise
from the changing drivers could lead to unpredictable latch values.
USER RESPONSE:
If the patterns were manually generated, change them to put the clock and Output Inhibit
changes in separate patterns. If the patterns were generated by an Encounter Test
on page 23).
WARNING (TND-850): An unrecognized stim value was found in the stim event at TBD
location TBD loc. The stim is set to X. The stim point is pin name.
EXPLANATION:
A primary input or latch stim value was encountered that was not 0, 1, X, H, L, or Z for a
PI, or 0 or 1 for a latch. The stim value is assumed to be X. The output TBD file will
contain the original stim value and not the assumed X. This error results in an audit
violation flag being set in the global statistics data. This flag may be used by certain
manufacturing sites to evaluate the validity of the data.
USER RESPONSE:
If the patterns were manually generated, you should correct the unrecognized stim value.
If these patterns were generated by an Encounter Test automatic test generator, contact
WARNING (TND-851): An invalid stim value of stim val was found in the PPI stim event
at TBD location TBD loc. A PPI may only be stimmed to 0 or 1. The stim is set to X. The
stim point is pin name.
EXPLANATION:
A pseudo-primary input (PPI) stim value was encountered that was not 0, or 1. The stim
value is assumed to be X. The output TBD file will contain the original stim value and not
the assumed X. This error results in an audit violation flag being set in the global statistics
data. This flag may be used by certain manufacturing sites to evaluate the validity of the
data.
USER RESPONSE:

If the patterns were manually generated, you should correct the invalid stim value. If
these patterns were generated by an Encounter Test automatic test generator, contact
WARNING (TND-853): A pin timing event in sequence definition seq def name contains
a pin timing for event # n whose direction conflicts with the pins value in the corresponding
dynamic pattern event at TBD location TBD loc. The pin timing direction is transition
and the event pin value is logic val. The PI is pin name. The pin timing direction is
honored.
EXPLANATION:
See message text. The pin timing template in the sequence definition specified by seq
def name does not agree with the pattern event data. The pin timing transition value
will be used.
USER RESPONSE:
If the patterns were manually generated, change them to make the pin timing template
agree with the pattern event data. If the patterns were generated by an Encounter Test
on page 23).
WARNING (TND-854): A pin timing event in sequence definition seq def name contains
a pin timing for event # n whose direction specifies Rising or Falling, but the corresponding
dynamic pattern event at TBD location TBD loc specifies a pin value of logic val. A
logic val is applied. The PI is pin name. Flat net index.
EXPLANATION:
See message text. The pin timing template in the sequence definition specified by seq
def name does not agree with the pattern event data. The value from the pattern event
data is used.
USER RESPONSE:
If the patterns were manually generated, change them to make the pin timing template
agree with the pattern event data. If the patterns were generated by an Encounter Test
on page 23).
WARNING (TND-855): A non-three-state PI is stimmed to an illegal value. The stim value

of invalid logic val has been converted to valid logic val. The stim event is
at TBD location TBD loc. The PI is pin name.
EXPLANATION:

A primary input stimulus value was encountered that was H, L, or Z. It is converted to a

1, 0, or X, respectively.
USER RESPONSE:
WARNING (TND-860): In the stim or pulse event found at TBD location TBD loc, the stim
value on correlated PI pin name conflicts with the value it should be based on the PI it is
correlated to. Other conflicts may exist in this event. All correlated PI conflicts will be corrected
relative to the PI they are correlated to and processing will continue.
EXPLANATION:
USER RESPONSE:
value on the correlated PI is correct. If the value is not correct, change the value.
WARNING (TND-865): The Stop_Osc event at TBD location TBD loc specifies a
quiescent state value of quiescent val, which differs from the stability value of stab
val. The PI is set to quiescent val. The PI is pin name.
EXPLANATION:
The object of a Stop_Osc event is typically a clock PI, which should have an associated
stability (off state) value. In this case, the value specified to restore the oscillator was
something other than the stability value for the pin.
USER RESPONSE:
Ensure that the specified Stop_Osc event is intended to restore the oscillator to some
value other than stability. If not, change the Stop_Osc event to utilize the stability value.
WARNING (TND-866): At TBD location Input TBD location, PI block name is used
by a WaitOsc without having been referenced by a StartOsc. net index
EXPLANATION:
A PI cannot be used in a WaitOsc unless it has been defined as an Osc by a StartOsc
TBD command.

USER RESPONSE:
If the patterns were manually generated, modify the StartOsc or WaitOsc. to agree. If
these patterns were generated by an automatic test generator, contact customer support
WARNING (TND-870): There are active PI oscillators at the end of the setup sequence at
TBD location TBD loc. These primary inputs will be set to X at the beginning of each
subsequent test sequence, regardless of any event that may set them to a known value during
any test sequence. The active PI oscillators are as follows:
EXPLANATION:
One or more primary inputs were the subject of a Start_Osc event in the setup sequence
for the current test procedure, causing them to become active oscillators. The oscillator
on these PIs, however, was not deactivated (via a Stop_Osc or other stim event) prior to
the end of the setup sequence. Since sequences do not have memory for this test
procedure, each of these PIs will be set to X at the start of each test sequence, even if
they are stimmed or deactivated during the course of some test sequence. This is
USER RESPONSE:
Ensure that you really wished to leave the oscillator PIs active at the end of the setup
WARNING (TND-885): A Force event was encountered at TBD location TBD loc. The test
data produced by this run may be invalid since Force events are not applied at the tester.
Force values follow:
EXPLANATION:
A Force event was encountered in the at the specified TBD location. This event has the
potential to cause the simulator to create incorrect measure, resulting in a tester failure.
The values applied to the design by the Force event will not be applied at the tester.
USER RESPONSE:
Ensure that you wished to specify a Force event in your manual patterns and that the
values listed are correct.
WARNING (TND-890): For the Release event at TBD location TBD loc, netname is not
stable. The FORCEd value was logic value. The net is now changing to logic value.
EXPLANATION:

The mentioned block output net changed value as soon as the Force was Released. This
means that the Force value on this net was not justified based on source blocks inputs.
The value is changed to the calculated value based on the blocks inputs.
USER RESPONSE:
You should consider carefully why the Force value did not justify and ensure that it will
not result in problems at the tester.
INFO (TND-892): The design reset at TBD location TBD loc has automatically released
all current Force nets. num forced nets were released.
EXPLANATION:
All forced nets are released whenever the simulator performs a design reset.
USER RESPONSE:
WARNING (TND-894): The Release event at TBD location TBD loc, contained a net that
was not currently forced. The net was netname.
EXPLANATION:
No Force event had specified the named net, but this release event did.
USER RESPONSE:
Consider whether or not you had intended to force this net. If so, specify the net in a
preceding Force event. Otherwise, remove it from the Release.
ERROR (TND-900): [Internal] PROGRAM LIMITATION ENCOUNTERED. A simulation

time overflow occurred at TBD location TBD loc. Simulation times are limited to the range
0 -> max sim time.
EXPLANATION:
USER RESPONSE:
ERROR (TND-901): [Internal] PROGRAM ERROR ENCOUNTERED. A simulation time

overflow occurred at TBD location TBD loc. Simulation times should never become
negative.
EXPLANATION:


USER RESPONSE:
ERROR (TND-902): [Internal] PROGRAM ERROR ENCOUNTERED. A simulation time

overflow occurred at TBD location TBD loc. Simulation times are limited to the range 0 ->
time limit.
EXPLANATION:
USER RESPONSE:
ERROR (TND-903): Test data output integrity error. Unable to write a TBD entity into the
output test data file. Processing terminates. The failing file is file name.
EXPLANATION:
A failure occurred attempting to write test data to the file file name.
USER RESPONSE:
Ensure that sufficient space exists in the file system. If problems persist, contact
ERROR (TND-904): Test data output error. Unable to initialize an output test data repository.
Processing terminates. Initialization attempted with these parameters: Project = parm 1 Part
Entity/Iteration/Variation = parm 2 Test Mode = parm 3 Experiment = parm 4
EXPLANATION:
USER RESPONSE:
ERROR (TND-905): Test data output integrity error. Unable to copy attribute data from the
TBD entity at input TBD location TBD loc to the output test data. Processing terminates.
EXPLANATION:

USER RESPONSE:
ERROR (TND-906): TBD file OPEN failure. Unable to OPEN the TBD output file. Processing
terminates. OPEN attempted with these parameters:
Project = parm1
Part Entity/Iteration/Variation = parm2
Test Mode = parm3
Experiment = parm4
EXPLANATION:
USER RESPONSE:
the file system and that file permissions are set correctly.
page 23).
ERROR (TND-911): [Internal] PROGRAM ERROR ENCOUNTERED. Processing

terminates. Error in file file name at line line #. diagnostic message
EXPLANATION:
USER RESPONSE:
ERROR (TND-912): TERMINATING ERROR ENCOUNTERED.

Error in file fileName at line lineNumber.
diagnostic_message
EXPLANATION:
This message indicates a terminating failure occurred.
USER RESPONSE:
ERROR (TND-915): Unable to register the output experiment experiment name in the
globalData file. Processing terminates. No output test data was produced.
EXPLANATION:


USER RESPONSE:
ERROR (TND-916): Unable to update the globalData file. Processing terminates. Check
permissions for the workdir directory and globalData file.
EXPLANATION:
Refer to the text for this message.
USER RESPONSE:
page 23).
ERROR (TND-936): Initialization for recording scope data failed. See preceding messages
for more information.
EXPLANATION:
Refer to the text for this message.
USER RESPONSE:
page 23).

55
TNP - Delay Timing Messages
TNP-011 through TNP-099 on page 1713
TNP-011 through TNP-099

WARNING (TNP-011): Timing of sequence timing_sequence_name failed due to
infeasible|unboundedinfeasible|unbounded delay constraints. The sequence
may be timed at a slower rate.
EXPLANATION:
Conflicts in the timing constraints for this sequence prevent the generation of valid tester
timing data. This is not normally a problem unless it causes timing failures for most of the
test sequences. No scan bits will be ignored and timings will be run at the at a slower
speed or the speed described in the clockconstraint file. Timing constraint conflicts in
large numbers of sequences are most likely the result of problems with delay rules.
USER RESPONSE:
If many sequences fail with this message, contact your technology supplier or Technical
Support for assistance in diagnosing possible delay rule problems. Aditional information
is supplied in the TimingInfo file.
INFO (TNP-012): The TDR does not specify enough resources for sequence
timing_sequence_name.
EXPLANATION:
The tester actions for this sequence cannot be fit within the resources specified in the
TDR without violating the timing constraints imposed by the delay rules. A large number
of sequence failures due to resource limitations is most likely the result of problems with
delay rules.
USER RESPONSE:

TNP - Delay Timing Messages
If many sequences fail with this message, contact your technology supplier or customer
support (see Contacting Customer Service on page 23) for assistance in diagnosing
possible delay rule problems. Additional information is supplied in the TimingInfo file.
INFO (TNP-013): There are no timing relationships between release and capture events in
sequence timing_sequence_name.
EXPLANATION:
The timing constraints on this sequence do not specify any relationships between tester
events. This problem is most likely due to missing delay rules.
USER RESPONSE:
Contact your technology supplier or customer support (see Contacting Customer
Service on page 23) for assistance in diagnosing delay rule problems. Additional
information is supplied in the TimingInfo file.
INFO (TNP-014): Inconsistent event types were specified for one or more tester events in
sequence timing_sequence_name.
EXPLANATION:
This is an internal programming error in Encounter Test.
USER RESPONSE:
Contact your technology supplier or customer support (see Contacting Customer
Service on page 23) for assistance in diagnosing this problem. Additional information is
supplied in the TimingInfo file.
INFO (TNP-099): Additional information about failed sequences in this run has been saved
in the file TimingInfo_filename.
EXPLANATION:
Additional information related to the preceding TNP messages has been written to the
uncommitted TimingInfo file. This information may be useful to Customer Service
personnel in diagnosing the problems that caused the messages to be issued.
USER RESPONSE:
Make a copy of this file before making more runs against the same experiment name.

56
TNS - Netname Services Messages
TNS-001 through TNS-042 on page 1715
TNS-001 through TNS-042

WARNING (TNS-001): [Severe] Opening file filename failed. error description
EXPLANATION:
The program was unable to open the referenced file.
USER RESPONSE:
Review and resolve the error description, and rerun.
WARNING (TNS-002): File filename line line number:net name is not a valid net
name.
EXPLANATION:
The program detected the referenced invalid net name and lists the file and line number
where the invalid name was detected
USER RESPONSE:
Ensure a valid net name is specifed in the referenced file and rerun.
ERROR (TNS-003): [Internal] Programming error: error text

EXPLANATION:
USER RESPONSE:

WARNING (TNS-004): Name not found in model: object name

EXPLANATION:
The program was did not fine the referenced name in the model
USER RESPONSE:
Ensure a valid object is specified in the model and rerun.
INFO (TNS-005): Object name1 is previously resolved by name2.

EXPLANATION:
The program determined the referenced object name was already resolved.
USER RESPONSE:
WARNING (TNS-006): [Severe] Could not read input file filename.

EXPLANATION:
The program was unable to read the referenced input file.
USER RESPONSE:
Ensure the correct file is specified and that proper permissions exist, and rerun.
IWARNING (TNS-007): [Severe] Could not write to output file filename.

EXPLANATION:
The program was unable to write to the referenced input file.
USER RESPONSE:
Ensure the correct file is specified and that proper permissions exist, and rerun.
INFO (TNS-008): Start reading file filename.

EXPLANATION:

Parsing of the named file has started. If any errors are encountered, detailed messages
will be produced prior to TNS-009, which denotes that reading of the file is complete.
USER RESPONSE:
INFO (TNS-009): End reading file filename.

EXPLANATION:
Parsing of the named file has completed. If any errors are encountered, they will be
detailed by preceding messages.
USER RESPONSE:
WARNING (TNS-010): [Severe] The File is empty.

EXPLANATION:
The file does not contain useful watch list information.
USER RESPONSE:
Verify there is valid watch list information in the file. Refer to "Using Watch List" in the
Encounter Test: Guide 6: Test Vectors.
WARNING (TNS-011): [Severe] The File contains nothing to process

EXPLANATION:
The file does not contain useful watch list information.
USER RESPONSE:
Verify there is valid watch list information in the file. Refer to "Using Watch List" in the
Encounter Test: Guide 6: Test Vectors.
WARNING (TNS-012): [Severe] number_of_errors syntax errors were found

EXPLANATION:
This is a report of the number of syntax errors found while parsing the file. Preceding
messages have specified the cause of each error.
USER RESPONSE:
Fix the errors and rerun the application.

WARNING (TNS-013): [Severe] Maximum Syntax Errors Reached

EXPLANATION:
There is a maximum number of errors which are reported from parsing the file. This
number has been reached.
USER RESPONSE:
Make sure that the file is actually a watch list for the model being worked on.
INFO (TNS-014): Duplicate Facility facility_name: Members added to previous

specification
EXPLANATION:
The same facility name was found more than once in the same file. The objects defined
within the facility will be catenated with the objects of the previous instance of the same
facility.
USER RESPONSE:
None is required if there is no error.
WARNING (TNS-015): [Severe] line line_number: Nested Facility Statement

EXPLANATION:
An opening brace was found which indicates the start of a set of objects within a facility
but the previous facility was never closed. Nesting of facilities is not allowed.
USER RESPONSE:
Ensure that all facilities are correctly started and ended and that there are none nested
within an other.
WARNING (TNS-016): [Severe] line line_number: Unmatched Facility End Statement

EXPLANATION:
A closing brace was found which indicates the close or end of a set of objects within a
facility but the opening brace was never found.
USER RESPONSE:
Ensure that all facilities are correctly started and ended and that there are none nested
within an other.
WARNING (TNS-017): [Severe] message_text

EXPLANATION:
The model index given in the file is outside the range of model object IDs for this
USER RESPONSE:
Make sure that the index number in the file is within the correct range.
WARNING (TNS-018): [Severe] message_text

EXPLANATION:
The name given on the specified line number in the file could not be found in the logic
model as either a net, a pin or a block.
USER RESPONSE:
Make sure that the specified name is in the model for the design you are working on and
that the name is spelled correctly. Correct the unrecognized name and rerun the
application.
WARNING (TNS-019): Simple Name: name resolved to two|three Hier Model Objects:
block|pin|net. Only the net1pin2 will be used
EXPLANATION:
A simple name was given without an explicit object type of Pin, Net or Block and more
than one object type has the given name. If one of the objects is net, then the net is used.
Otherwise the pin is used.
USER RESPONSE:
If you wish the name to resolve to an explicit object type, then put that type before the
name in the file.
INFO (TNS-020): Duplicate watch item encountered: name1

EXPLANATION:
A model object was found more than once and an alias name was found on the later one.
The first object had no alias. The alias name is used.
USER RESPONSE:
INFO (TNS-021): Alias name encountered on duplicate watch item. The alias will be used.
EXPLANATION:

A hier model object was found more than once and an alias name was found on the later
one where the first one had none. The alias name is used.
USER RESPONSE:
If the alias is desired, no response is required. If the alias is not desired, remove the entry
that specifies the alias.
WARNING (TNS-022): [Severe] Unrecognized object names were found in the watch file.
EXPLANATION:
One or more model object names were unrecognized. A preceding message will contain
the unrecognized name.
USER RESPONSE:
Fix the unrecognized name(s) and rerun the application.
WARNING (TNS-023): [Severe] A facility statement was found with no closing brace.
EXPLANATION:
A facility statement was encountered that had no closing brace (}). Either the end of
the file has been reached or another facility statement was started before the current
facility statement was ended.
USER RESPONSE:
Ensure all facility statements have both opening and closing braces and then rerun if
necessary. Note that nested facility statements are not supported.
INFO (TNS-024): line number: Only book level pins supported for timing
EXPLANATION:
The application requested a time-able structure from the pins in the file. A pin was found
which is not on a cell boundary which can be timed.
USER RESPONSE:
Remove this pin from the file.
WARNING (TNS-025): [Severe] line number: Non Printable Character line2 error
EXPLANATION:
At the position above the asterisk in line <number> of the file, a syntax error was detected
where the program found a non-printable character

USER RESPONSE:
Fix the error and rerun the application.
WARNING (TNS-026): [Severe] Line number: First Character allowed only within Quotes
line error
EXPLANATION:
At the position above the asterisk in line <,number> of the file, a syntax error was
detected where the program found a special character outside of quotes
USER RESPONSE:
WARNING (TNS-027): [Severe] Line number: Unquoted / not followed by * or /. A slash

character must be part of a comment delimiter or part of an object \name that is enclosed in
double-quotes.
error
EXPLANATION:
A syntax error was detected at the position above the asterisk in the displayed line. The
program found a slash character outside of quotes. A comment delimiter was expected.
USER RESPONSE:
If the / character is part of an object name, enclose the entire name in double-quotes
("). If the / is meant to begin a comment, it must be followed by either another slash
(//) for a comment to the end-of-line, or an asterisk (/*) to begin a comment which is
subsequently closed by asterisk-slash (*/).
Fix the problem appropriately and rerun the application.
WARNING (TNS-028): [Severe] Line number: A double-quote may only begin and end a
model object name.
line error
EXPLANATION:
A syntax error was detected at the position above the asterisk in the displayed line in
which an unexpected double-quote character (") was found. Double-quotes may only
appear surrounding model object names.
USER RESPONSE:
Remove or reposition the double-quote character and rerun the application.

WARNING (TNS-029): [Severe] line number: Backslash may only be used within quotes
to define a quote
line error
EXPLANATION:
where the program found a back slash character in what may be a name
USER RESPONSE:
WARNING (TNS-030): [Severe] line number: Missing facility name

line error
EXPLANATION:
where the program found that a facility name was expected and none was found
USER RESPONSE:
WARNING (TNS-031): [Severe] line number: Braces Allowed only within Quoted Model
Names
line error
EXPLANATION:
where the program found a { or a } character where it could not parse the line
USER RESPONSE:
WARNING (TNS-032): [Severe] line number: Only within Quoted Model Names or first
character
number error
EXPLANATION:
A syntax error was detected at the position above the asterisk in line <number> of the
file. The program found a special character where the name must be enclosed in double
quotes
USER RESPONSE:

WARNING (TNS-033): [Severe] line number: Consecutive periods not allowed in Hier
Model Name line error
EXPLANATION:
At the position above the asterisk in line number of the file, a syntax error was detected
where the program found a Hier Model Name which does not conform to the Encounter
Test naming syntax
USER RESPONSE:
WARNING (TNS-034): [Severe] line number: Hier Model Name Syntax line error
EXPLANATION:
where the program found a Hier Model Name which does not conform to the Encounter
Test naming syntax
USER RESPONSE:
WARNING (TNS-035): [Severe] line number: Non Printable Character within Quotes
line error
EXPLANATION:
where the program found a non printable character within a quoted string Non printable
characters are not supported
USER RESPONSE:
WARNING (TNS-036): [Severe] line number: End of line within a Quoted Hier Model
Name line error
EXPLANATION:
where the program found an end of line within a quoted string. Quoted names must be
all on one line.

USER RESPONSE:
WARNING (TNS-037): [Severe] line number: Starting quote found where type not net,
pin, or block line error
EXPLANATION:
where the program found the start of a quoted string which was neither a proper
Encounter Test name nor preceded by block, pin, or net. Quoted simple names must be
preceded by the Hier Mode Object type.
USER RESPONSE:
WARNING (TNS-038): [Severe] line number: Special Character In Alias Name line
error
EXPLANATION:
where the program found an alias name but with an invalid special characters in it. The
Alias name must be a combination of alpha numeric and these special characters:
!#$%&()+,-.:<=>?@[]^_|~
USER RESPONSE:
WARNING (TNS-039): [Severe] line number: Facility name does not follow name rules
line error
EXPLANATION:
where the program expected a facility name which adhered to the followed the rules.
Must start with an alpha character followed by any combination of alpha numerics or the
special characters !#$%&()+,-.:;<=>/?@[]^_|~* with no white space in between
USER RESPONSE:
WARNING (TNS-040): [Severe] line number: Expected Facility name followed by open
brace followed by comment or end of line line error

EXPLANATION:
where the program expected a facility name followed by an open brace and then an
optional comment or end of line
USER RESPONSE:
WARNING (TNS-041): [Severe] line number: Expected comment or end of line line
error
EXPLANATION:
where the program expected a comment or end of line
USER RESPONSE:
WARNING (TNS-042): [Severe] line number: Syntax Error line error

EXPLANATION:
At the position above the asterisk in line number of the file, a syntax error was detected.
USER RESPONSE:


57
TOM - Objective Model Build and Access
Messages
TOM-001 through TOM-072 on page 1727

TOM-100 through TOM-722 on page 1739
TOM-001 through TOM-072

INFO (TOM-001): Objective Model Build started.
EXPLANATION:
The Objective Model Build program has been invoked.
USER RESPONSE:
WARNING (TOM002): [Severe] Dynamic memory allocation error.

EXPLANATION:
There was a problem allocating enough memory to run the fault model application.
USER RESPONSE:
If the CPU where the application was running is loaded with other processing, you can
wait and rerun the fault model application when there is more memory available.
If the CPU where the application was running does not really have more memory
available, run the fault model application on a different CPU.
WARNING (TOM-003): [Severe] Objective model file filename does not exist or could
not be opened as new | existing file.
EXPLANATION:

TOM - Objective Model Build and Access Messages
This indicates there was a problem trying to open the objective model file. See previous
USER RESPONSE:
WARNING (TOM-004): [Severe] EDAM file close error.

EXPLANATION:
This indicates there was a problem trying to close the fault model file. See previous
USER RESPONSE:
Resolve the problem(s) identified in previous EDAM error messages.
If you do not see the previous messages, or do not know what to do, contact customer
WARNING (TOM-005): [Severe] EDAM storage area open error.

EXPLANATION:
This indicates there was a problem trying to open a storage area in the fault model file.
See previous EDAM error messages for details of the problem.
USER RESPONSE:
WARNING (TOM-006): [Severe] EDAM storage area close error.

EXPLANATION:
This indicates there was a problem trying to close a storage area in the fault model file.
USER RESPONSE:

WARNING (TOM-007): [Severe] EDAM storage area get error.

EXPLANATION:
This indicates there was a problem trying to get a storage area from the fault model file.
USER RESPONSE:
WARNING (TOM-008): [Severe] EDAM storage area put error.

EXPLANATION:
This indicates there was a problem trying to put a storage area into the fault model file.
USER RESPONSE:
WARNING (TOM-009): [Severe] EDAMterm error.

EXPLANATION:
This indicates there was a problem trying to terminate the EDAM Paging Manager. See
USER RESPONSE:
INFO (TOM-010): Objective Model List started: time-date_1

EXPLANATION:
None
USER RESPONSE:

WARNING (TOM-012): [Severe] Unable to open logic model. TLMloadModel failed.

EXPLANATION:
This indicates there was a problem loading the logic model. See previous messages from
logic model utilities for details of the problem.
USER RESPONSE:
Resolve the problem(s) identified in previous utility error messages.
WARNING (TOM-013): [Severe] Unable to unload the logic model. TLMunloadModel error.
EXPLANATION:
This indicates there was a problem unloading the logic model. See previous messages
from logic model utilities for details of the problem.
USER RESPONSE:
Resolve the problem(s) identified in previous utility error messages.
WARNING (TOM-014): objectiveModel file fully qualified filename does not

exist or cannot be opened.
EXPLANATION:
The indicated objectiveModel file does not exist or cannot be opened.
USER RESPONSE:
If you are running from the command line, ensure that this is for the right design.
(WORKDIR specifications are accurate).
If you are running from the graphical used interface, the most likely cause of the error is
forgetting to run Build SDT/SNT Objectives. You must build the fault model before you
can run any applications that require it. Use build_sdtsnt_objectives or use the
"Build SDT/SNT Objectives on the Graphical User Interface.
If the file exists, there should be messages preceding this message that indicate why the
file could not be opened.
WARNING) (TOM-015): objectiveStatus file fully qualified filename does not

exist or cannot be opened.

EXPLANATION:
The objectiveStatus file indicated in the message does not exist.
USER RESPONSE:
If you are running from the command line, ensure you are using the right design
(WORKDIR and TESTMODE specified as input are accurate). If the input is correct, or
you are running from the graphical user interface, the problem is probably one of the
following:
log to determine if Build Fault Model, or Build Test Mode failed.
The objectiveStatus file has been removed with one of the Encounter Test
processes (Delete Test Mode(s)).
The objectiveStatus file has been removed manually. Use
build_sdtsnt_objectives or use the Build SDT/SNT Objectives on the
Graphical User Interface. If the file exists, there should be messages preceding
this message that indicate why the file could not be opened.
ERROR (TOM-017): [Internal] Open request incompatible with current open state.
EXPLANATION:
The application tried to open the objective model file and it was currently open.
USER RESPONSE:
If you have multiple applications that process objectives running simultaneously it may
be that you need to wait until one of them is done and then submit the other one.
If you do not understand what is causing the error and it resolve by resubmitting the
application, contact customer support (see Contacting Customer Service on page 23).
WARNING (TOM-018): [Severe] Invalid function parameter: keyword value

EXPLANATION:
An invalid parameter has been specified as input to one of the TOM executable
programs, and is shown in the message.
USER RESPONSE:
Correct the invalid parameter according to the help text available for the executable
program and reinvoke the program. To get the help text from the command line, invoke
the program with the -h parameter.

Refer to build_sdtsnt_objectives in the Encounter Test: Reference: Commands for

WARNING) (TOM-019): Testmode testmode name data does not exist in the objective
model.
EXPLANATION:
Information related to the indicated testmode does not exist in the objective model.
USER RESPONSE:
Ensure that the TESTMODE parameter is specified correctly and that it exists.
INFO (TOM-020): Objective Model List completed: time-date

EXPLANATION:
None
USER RESPONSE:
WARNING (TOM-021): [Severe] objectiveModel file younger than objectiveStatus file.

Rebuild all objectiveStatus files.
EXPLANATION:
The currently existing objectiveModel was built after the objectiveStatus file.
USER RESPONSE:
Ensure that the WORKDIR, TESTMODE, and EXPERIMENT values are
accurate.
Rerun Build SDT/SNT Objectives to reinitialize the objectiveStatus file
(build_sdtsnt_objectives -f). This will cause all test generation data to
be removed.
Repeat any previous test generation runs.
WARNING (TOM-022): [Severe] Testmode data is younger than experiment. Rebuild the
experiment file.

EXPLANATION:
The objective model data for the testmode was created after the experiment you are
trying to process.
USER RESPONSE:
Remove the objectiveStatus<.experiment> file and rerun the application that created it.
ERROR (TOM-023): [Internal] EDAMfdel error.

EXPLANATION:
There was a program error in the EDAM utility while trying to delete a file.
USER RESPONSE:
See preceding EDAM messages to understand the actual problem.
If you are unable to resolve the problem, contact customer support (see Contacting
ERROR (TOM-025): [Internal] EDAMsfre error.

EXPLANATION:
There was a program error in the EDAM utility while trying to free storage.
USER RESPONSE:
See preceding EDAM messages to understand the actual problem.
If you are unable to resolve the problem, contact customer support (see Contacting
ERROR (TOM-027): Input objective file file name could not be opened. Processing
terminates.
EXPLANATION:
The objective file specified as input to Objective Model Build via the objectivefile=
keyword could not be opened. Processing terminates.
USER RESPONSE:
Rerun build_sdtsnt_objectives with a valid objective file name specified.

WARNING (TOM-028): [Severe] Objective Model is incompatible with current level of

Objective Model Build. Rebuild the objective model with the current program level.
EXPLANATION:
According to the program level stored in the files, the objective model was built with an
earlier program level that is incompatible with the current level being run.
USER RESPONSE:
Rebuild the Objective Model by running Fault Model Build. If rebuilding the fault model is
not desired, run with the option to build only the objective model. The command line
option is sdtsnt=only.
WARNING (TOM-029): [Severe] Logic model younger than objective model. Rebuild all
objective model files.
EXPLANATION:
According to the dates stored in the files, the objective model was built before the logic
model. If you rebuild the logic model it should remove the objective model. Therefore, this
error should not occur under normal circumstances.
USER RESPONSE:
If you have been copying files from one directory to another, and think you may have
accidentally caused this problem, rebuild the objective model. Note that any existing test
data will be invalid with the new fault model.
If you think Encounter Test created this problem, contact customer support (see
WARNING (TOM-030): [Severe] Logic model create date cannot be verified

EXPLANATION:
The Fault Model Build program is unable to verify the logic models creation date. Either
the specified logic model files do not exist, or they have been damaged.
USER RESPONSE:
Review the log for this run and fix problems associated with any previous errors.
Review the log for Build Model.
If it indicates severe errors, correct the problems, re-import the design, and
rerun Build SDT/SNT Objectives.

If there were no problems indicated prior to this message (in either Build Model
or Build Fault Model), contact customer support (see Contacting Customer
WARNING (TOM-031): [Severe] Objective model file fully qualified filename

contains no header information. Rebuild the file.
EXPLANATION:
There is something wrong with the indicated objective model file. Most likely, the process
that attempted to generate the objective model file ended abnormally before it properly
closed the file. Another possibility is that during the creation of the objective model file,
the capacity of the file system was exceeded.
USER RESPONSE:
If the file indicated is objectiveModel or objectiveStatus, review messages from Build
SDT/SNT Objectives, fix any problems and rerun Build SDT/SNT Objectives.
If the file indicated is objectiveStatus.testmode.experiment, review messages from the
application that created it to determine why the file isnt valid.
Rerun the application that created the file.
WARNING (TOM-032): Syntax error in objective file file name on line line number.
EXPLANATION:
The objective file being processed has a syntax error on the indicated line number.
Create a Fault Model will continue with no objectives built for this line in the objective file.
USER RESPONSE:
None required. The user may choose to investigate this problem, correct the offending
pin name, and rerun Create a Fault Model.
WARNING (TOM-033): No TSD found for pin pin name on line line number of the
objective file objective file name. No objectives will be created for this pin pair.
EXPLANATION:
A tri-state driver (TSD) block is required to be driving the net associated with each pin
specified on an objective statement. A TSD could not be found for the pin specified in this
message. Create a Fault Model will continue with no objectives built for this line in the
objective file.
USER RESPONSE:

pin name, and rerun Create a Fault Model.
WARNING (TOM-034): Net associated with pin pair on line line number of objective file
objective file name is not a target net. No objectives will be created for this pin pair.
EXPLANATION:
The net associated with the pin pair on the line specified in the message would not
normally be targeted for Stuck Driver Test Generation.
Create a Fault Model will continue with no objectives built for this line in the objective file.
USER RESPONSE:
pin name(s), and rerun Create a Fault Model.
objective file name has no active drivers.
No objectives will be created for this pin pair. Processing continues.
EXPLANATION:
The net associated with the pin pair on the line specified in the message has no drivers
that would normally be targeted for Stuck Driver Test Generation. Create a Fault Model
will continue with no objectives built for this line in the objective file.
USER RESPONSE:
objective file name has no active receivers.
EXPLANATION:
The net associated with the pin pair on the line specified in the message has no receivers
that would normally be targeted for Stuck Driver Test Generation. Create a Fault Model
will continue with no objectives built for this line in the objective file.
USER RESPONSE:

WARNING (TOM-037): Primary and secondary driver for pin pair on line line number of
objective file objective file name are on the same chip.
EXPLANATION:
The two drivers associated with the pin pair on the line specified in the message are on
the same chip. This is not valid for Slow-to-Disable objectives. Create a Fault Model will
continue with no objectives built for this line in the objective file.
USER RESPONSE:
WARNING (TOM-038): Unable to create objectives for pin pair on line line number of
objective file objective file name. Processing continues.
EXPLANATION:
Either no valid primary driver, no valid secondary driver, or no valid receiver could be
found for the pin pair on the line specified in the message. A previous message should
provide more details on the problem. Create a Fault Model will continue with no
objectives built for this line in the objective file.
USER RESPONSE:
WARNING (TOM-039): Primary and secondary driver for pin pair on line line number of
objective file objective file name are not on the same net. Processing continues.
EXPLANATION:
The drivers associated with the pin pair on the line specified in the message are not on
the same net. They are required to be on the same net in order to define Slow-to-Disable
SDT objectives. Create a Fault Model will continue with no objectives built for this line in
the objective file.
USER RESPONSE:

WARNING (TOM-040): [Severe] Unable to obtain a read lock on the specified design. rc
= framework services return code (number)
EXPLANATION:
In order to process the fault model, the program must be able to read the information for
the design.
USER RESPONSE:
Ensure that the specified WORKDIR parameters are correct.
Ensure read permission to the directory containing the design and to the
individual files in that directory.
If multiple applications were running simultaneously on the same design, try
resubmitting this application.
If you are unable to determine why the design cannot be read, and rerunning
does not resolve the problem, contact customer support (see Contacting
WARNING) (TOM-043): PIN name pin name on line line number of objective file
objective file name could not be resolved in the Logic Model. No objectives will be
created for this pin pair. Processing continues.
EXPLANATION:
The pin name used in the objective file didnt exist in the logic model.
USER RESPONSE:
None required. The user may choose to check the name specified in the objective file
and ensure it is a valid pin name in the logic model, then correct the objective file and
rerun Create a Fault Model.
WARNING) (TOM-071): Experiment experiment name is not registered.

EXPLANATION:
The experiment indicated in the message is not registered on the globalData.
USER RESPONSE:
is probably that the application that should have created the experiment failed.
Check your log to determine if the application failed.

WARNING) (TOM-072): Unable to open Experiment file fully qualified filename.

EXPLANATION:
The uncommitted objectiveStatus file indicated in the message was unable to be opened
for processing.
USER RESPONSE:
Check for previous messages that indicate why the file was unable to be opened. If this
doesnt help, some things to check for:
accurate, especially if you are trying to work with an existing experiment.
If this is a new experiment, check to see that enough DASD is available to
create the file.
TOM-100 through TOM-722

INFO (TOM-100): objectiveModel file fully qualified filename exists and will not
be overwritten.
EXPLANATION:
The objectiveModel file already exists.
USER RESPONSE:
INFO (TOM-101): Reinitializing objectiveStatus file fully qualified filename.

EXPLANATION:
The objectiveStatus file indicated in the message is being reinitialized.
USER RESPONSE:
INFO (TOM-102): No objectives will be active for test mode test mode name based on
test mode definition parameter modedef parameter.
EXPLANATION:

This test mode will contain no active objectives due to either the "test_types" parameter
in the mode definition not specifying a test type of interconnect or iowrap, or the "faults"
keyword specifying "none".
USER RESPONSE:
No response required, this is informational. However if objective data is needed for this
test mode, the mode definition "test_types" parameter should be set to interconnect or
iowrap and the "faults" keyword should be set to something other than "none".
INFO (TOM-134): Unable to uncompress file fileName.

EXPLANATION:
USER RESPONSE:
uncompressed version of this file. If there is enough disk space, contact customer
INFO (TOM-135): Unable to compress file fileName.

EXPLANATION:
the specified file.
USER RESPONSE:
page 23).
INFO (TOM-150): Delete SDT/SNT Objective Model started.

EXPLANATION:
The Delete Objective Model command has been invoked. All objectiveModel and
objectiveStatus files will be deleted.
USER RESPONSE:
INFO (TOM-151): Removing file file_name and its dependent files.

EXPLANATION:
The referenced file is being deleted along with any files registered as dependent on this
file, and all registration records on the globalData file. For an objectiveModel, the
dependent files are the objectiveStatus file and the experimental
objectiveStatus files.
USER RESPONSE:
INFO (TOM-152): File file_name not found. Proceeding with attempts to remove
dependent files and registration records.
EXPLANATION:
The referenced file shown was not found by the delete_sdtsnt_objectives
command but processing will continue to remove files registered as dependent on this
file, and to remove all registration records on the globalData file.
USER RESPONSE:
ERROR (TOM-153): File file_name could not be deleted. See preceding messages.
EXPLANATION:
The referenced file could not be deleted. An internal program error message should have
been issued. Processing ends without removing dependent files or registration records.
The most likely reason for the failure is that another process is accessing the file and has
a lock on it. Another possibility is there is a permissions problem with the file.
USER RESPONSE:
Correct the error in the preceding message and rerun delete_sdtsnt_objectives.
If there is no preceding message, contact customer support (see Contacting Customer
INFO (TOM-155): Delete SDT/SNT Objective Model completed.

EXPLANATION:
The Delete Objective Model program has completed. If there are no error messages
preceding this message, all objectiveModel and objectiveStatus files have been
deleted.
USER RESPONSE:

INFO (TOM-190): Now building alternate fault model for Stuck Driver Test verification via
pattern simulation.
EXPLANATION:
An alternate fault model is being built to model the objectives as faults for pattern
simulation because at this time the simulators do not work on objectives.
USER RESPONSE:
INFO (TOM-199): Objective model build has completed successfully.

EXPLANATION:
The objectiveModel and objectiveStatus files have been built.
USER RESPONSE:
ERROR (TOM-674): [Internal] model type model type not recognized.

EXPLANATION:
A model type was not recognized.
USER RESPONSE:
WARNING (TOM-675): [Severe] Error opening model type model.

EXPLANATION:
The associated model could not be opened.
USER RESPONSE:
Check design info and permissions.
WARNING (TOM-676): [Severe] Error closing the model type model.

EXPLANATION:
An error was encountered while closing the model.
USER RESPONSE:

Check design info and permissions.
INFO (TOM-700): Objective Model Statistics started: time-date.

EXPLANATION:
None.
USER RESPONSE:
INFO (TOM-701): Objective Model Statistics completed: time-date.

EXPLANATION:
None.
USER RESPONSE:
ERROR (TOM-710): application report_sdtsnt_objective_statistics

| report_sdtsnt_objectives | build_sdtsnt_objectives can not
continue due to reason. Refer to sdterr for additional information.
EXPLANATION:
USER RESPONSE:
necessary.
ERROR (TOM-711): WORKDIR was not specified and is a required parameter.

EXPLANATION:
WORKDIR is a required parameter which specifies the top-level directory structure
where your imported design and the results of Encounter Test applications reside.
USER RESPONSE:
Specify WORKDIR on the command line or as an exported variable. Refer to
build_sdtsnt_objectives in the Encounter Test: Reference: Commands for

ERROR (TOM-713): TESTMODE was not specified and is a required parameter when used
in conjunction with the -m flag.
EXPLANATION:
TESTMODE specifies the name of a predefined test mode and is a required parameter
when used in conjunction with the -m flag.
USER RESPONSE:
Specify TESTMODE on the command line or as an exported variable. Refer to
ERROR (TOM-714): Unable to establish shared use of the hierModel. Processing

Terminates.
EXPLANATION:
The application was unable to obtain a read lock on the hierModel.
USER RESPONSE:
Ensure that the WORKDIR is set correctly for the design being processed.
Ensure that the hierModel file exists with file permissions that allow you read
access.
ERROR (TOM-717): [Internal] Unexpected error on unload of flat model.

EXPLANATION:
USER RESPONSE:
ERROR (TOM-722): EXPERIMENT was not specified and is a required parameter when
used in conjunction with the -e flag.
EXPLANATION:
EXPERIMENT specifies a file name qualifier of an uncommitted Vectors file and is a
required parameter when used in conjunction with the -e flag.
USER RESPONSE:

Specify EXPERIMENT on the command line or as an exported variable. Refer to



58
TPC - Parallel Processing
Communications Messages
TPC-001 through TPC-005 on page 1747
TPC-001 through TPC-005

ERROR (TPC-001): Unable to add host hostName to parallel processing configuration.
The most common cause for this is that remote access to selected hosts is not available via
the rsh command. In order to ensure remote access to all required directories execute the
following.
If you are starting the run from a HP machine, replace rsh with remsh in the commands.
rsh machine_name_in_this_message touch part_directory/name_of_some_file
rsh machine_name_in_this_message ls Install_Dir_For_Encounter Test
on the command line. If this fails, contact your system administrator.
If the preceding works, refer to the help text on this message for possible solutions. Also refer
to Prerequisite Tasks and Restriction sections in "Performing Test Generation/Fault
Simulation Tasks Using Parallel Processing" in the Automatic Test Pattern Generation
User Guide if you havent already done so.
EXPLANATION:
There was a problem encountered while adding the identified host to the parallel
processing environment.
USER RESPONSE:
If you are in the GUI environment, exit it.
Execute et -c if you are not already in the et -c shell.

TPC - Parallel Processing Communications Messages
Make sure that the environment variable PVM_ROOT is set to Encounter

Test_InstallPoint/pvmdir and the environment variable PVM_DPATH is set to
Encounter Test_InstallPoint/pvmdir/lib/pvmd.
Execute the ps command to see if a process named pvmd3 is running. If this
process is running, kill it. Change Directory (cd ) to the /tmp directory on the
host that you started the run on. Remove the file named
pvmd.your_uid_number if it exists. Your uid number can be obtained by issuing
the id command.
Repeat step 4 on the host identified in the message. Restart the application. If
this does not work, contact customer support (see Contacting Customer
ERROR (TPC-002): Error errorNumber obtaining the process id. Refer to help text on
this message for possible solutions.
EXPLANATION:
There was a problem encountered while obtaining the process id of one parallel
processes. The error number is identified. The process id is required to be able to pause
or kill the application.
USER RESPONSE:
Change Directory (cd ) to the pvmdir directory under the Installation point. Issue
the command ./pvm.
At the > prompt, issue the command conf. This will list the names of all hosts
that currently exist in the parallel configuration.
Issue the command add hostname for all hosts that you have selected for the
run that do not show up in the results of the conf command. If the add command
is unsuccessful for a host for any other reason besides Duplicate host execute
the ps command to see if a process named pvmd3 is running on the host. If this
process is running, kill it.
Change Directory (cd ) to the /tmp directory on this host. Remove the file named
pvmd.your_uid_number if it exists. Your uid number can be obtained by
issuing the id command on the UNIX command line.
Restart the application. If the problem persists, or the add command was
successful, call customer support (see Contacting Customer Service on
page 23).

ERROR (TPC-003): The environment variable envVariableName is not defined. This

environment needs to be defined to execute the child process. Refer to help text on this
message for possible solutions.
EXPLANATION:
The following environment variables specify where the application is located for a
particular platform:
TB_AIX41DIR AIX 4.1
The identified environment variable in the message needs to be set to the fully qualified
directory name <Install_Dir>/bin, where Install_Dir is the install point for
Encounter Test for the platform associated with the identified environment variable.
USER RESPONSE:
If you are running in a homogeneous environment (all machines on same platform) this
variable is set by et. Execute et -c to ensure this. If the variable is not set, call customer
support. If you are running in a heterogeneous environment the variable can be set by
using the Set System Environment screen if running in the GUI environment, setting it on
your command line or running the ppinit script. More information on the ppinit script
can be obtained from the readme file in the install directory for Encounter Test.
ERROR (TPC-004): Error errorNumber encountered while starting child process on host
hostName
EXPLANATION:
Error number -7 indicates that the executable for the application was not found. Error
number -6 or -14 indicate an error in the underlying parallel environment used to
parallelize the application. Error number -2 indicates a programming error and error
numbers -10 and -27 indicate running out of memory.
USER RESPONSE:
Error number -7:
Make sure the environment variables TB_AIX41DIR, TB_SOLDIR and TB_HPUX10DIR
are set up to point to the location of the executables for the AIX, Solaris and HP-UX
platforms respectively. These can be set using the Set System Environment screen if
running using the GUI environment, setting it on your command line or running the ppinit
script. More information on the ppinit script can be obtained from the readme file in the
in the install directory for Encounter Test.
Error number -6:
Perform the following steps:


Change Directory (cd ) to the pvmdir directory under the Installation point. Issue
the command ./pvm. At the > prompt, issue the command add hostname for
the hosts indicated in the message.
If the add command is unsuccessful for any other reason besides Duplicate
host, execute the ps command to see if a process named pvmd3 is running on
the host. If this process is running, kill it. Change directory (cd) to the /tmp
directory of the host and remove the file pvmd.your_uid_number if it exists. Your
uid number can be obtained by issuing the id command on the UNIX command
line. Restart the application.
If the problem persists or the add command was successful, call customer
Error number -14:
Perform the following:
Execute the ps command to see if a process named pvmd3 is running on the
host. If this process is running, kill it.
Change Directory (cd ) to /tmp and remove the file pvmd.your_uid_number if it
exists. Your uid number can be obtained by issuing the id command on the
UNIX command line. Restart the application.
If the problem persists, call customer support (see Contacting Customer
Error number -2, -10 or -27:
Call Customer Support.
ERROR (TPC-005): Error encountered while starting child process on host hostname. The
application was unable to find the executable corresponding to the child process. The
environment variables TB_AIX41DIR, TB_SOLDIR and TB_HPUX10DIR are used to
determine the location of the executable for the AIX, SOLARIS and HP-UX platforms
respectively and should be set up by et if you are running in a homogeneous environment.
run et -c and ascertain this. If the variables are not set contact customer support. If you are
running in a heterogeneous environment, read the help text on this message.
EXPLANATION:

The application was unable to find the executable corresponding to the child process.
The environment variables TB_AIX41DIR, TB_SOLDIR and TB_HPUX10DIR are used
to determine the location of the executable for the AIX, SOLARIS and HP-UX platforms
and should be set up by et if you are running in a homogeneous environment.
USER RESPONSE:
Run et -c and make sure the environment variables TB_AIX41DIR, TB_SOLDIR and
TB_HPUX10DIR are set up to point to the location of the executables for the AIX, Solaris
and HP-UX platforms respectively. If you are running in a homogeneous environment (all
machines on same platform) the variable corresponding to the platform is setup by et.
These environment variables can also be set using the Set System Environment screen
if running in the GUI environment, setting it on your command line or running the ppinit
script. More information on the ppinit script can be obtained from the readme file in the
install directory for Encounter Test.


59
TPD - Test Pattern Display Messages
TPD-100 through TPD-900 on page 1753
TPD-100 through TPD-900

WARNING (TPD-100): View Circuit Values was unable to establish the logic model context.
EXPLANATION:
View Circuit Values was not able to set up for utilizing flat model utilities.
USER RESPONSE:
WARNING (TPD-101): View Circuit Values was unable to load the logic model.
EXPLANATION:
View Circuit Values was not able to load the logic model.
USER RESPONSE:
WARNING (TPD-102): View Circuit Values was unable to the test mode for the logic model.
EXPLANATION:
View Circuit Values was not able to load the logic model.
USER RESPONSE:
WARNING (TPD-103): View Circuit Values was unable to operation the tbd_type file.
EXPLANATION:

View Circuit Values was not able to perform the specified action on the specified file.
Further processing cannot continue.
USER RESPONSE:
ERROR (TPD-200): View Circuit Values does not support processing of TBDseq data.
Please use Vectors file test data. View Circuit Values is being terminated.
EXPLANATION:
View Circuit Values does not provide support for processing test data in TBDseq files at
this time.
USER RESPONSE:
Select Vectors file test data for using View Circuit Values.
WARNING (TPD-201): View Circuit Values could not process the input sequence
odometer string odometer. This indicates a program error.
EXPLANATION:
View Circuit Values was unable to decipher the input string that was to be processed as
a test sequence odometer to be simulated. This situation would appear to be a program
error.
USER RESPONSE:
ERROR (TPD-202): View Circuit Values does not support processing of signature-based
test data (e.g. WRP, LBIST). Please select another type of data. View Circuit Values is being
terminated.
EXPLANATION:
View Circuit Values does not provide support for processing signature-based test data
such as WRP or LBIST. Stored pattern test data should be used.
USER RESPONSE:
Select stored pattern test data for using View Circuit Values.
WARNING (TPD-203): View Circuit Values has calculated that the number of events in this
sequence that would have simulation data saved is tbd_events_to_save. The program
maximum is program_max_num_events. Please note that simulation data for only the
LAST program_man_num_events events of the sequence will be saved.

EXPLANATION:
The actual number of events that would have simulation data saved exceeds the
programmed maximum. In this situation, data will be saved for only the maximum number
and will be for that number prior to the end of the sequence. Hence, some number of
events at the beginning of the sequence will not have simulation data available.
USER RESPONSE:
WARNING (TPD-204): View Circuit Values has found that insufficient storage was available
to save net value data for all actual_event_count events in the selected test
sequence. However storage was obtained to allow net value data to be saved for
reduced_event_count events. Please note that only the last
reduced_event_count events in the sequence will have simulation data available.
EXPLANATION:
Insufficient storage was available to allow for saving simulation net value data for all the
events in the test sequence. However enough storage was available to save data for a
reduced number of events. Data will be saved for the reduced number of events that
occur in the latter part of the sequence. Hence, some number of events at the beginning
of the sequence will not have simulation data available.
USER RESPONSE:
ERROR (TPD-205): View Circuit Values was unable to get sufficient storage to save any
net value data. Attempts were made to cover all actual_event_count events in the
selected test sequence, and then progressively less numbers of events. All attempts failed.
View Circuit Values will terminate.
EXPLANATION:
Insufficient storage was available to allow for saving simulation net value data for all the
events in the test sequence. Additional efforts to get storage for reduced numbers of
events also failed. The application is unable to run the simulation and will terminate.
USER RESPONSE:
If the CPU where the application was running is loaded with other processing, you can
wait and rerun the application when there is more memory available. If the CPU where
the application was running does not really have more available, run the application on
a different CPU.

WARNING (TPD-206): View Circuit Values was unable to provide data_type data in
response to a request for such data in order to complete a simulate action initiated in the
schematic display.
EXPLANATION:
View Circuit Values was unable to provide design state data to be loaded for simulation
of a requested simulate action in the schematic display. This circumstance indicates a
possible program problem.
USER RESPONSE:
If problem persists, contact customer support (see Contacting Customer Service on
page 23).
WARNING (TPD-207): View Circuit Values currently does not support providing design
state data for a simulate action in the schematic display. No action is being taken on this
request.
EXPLANATION:
Support does not exist at this time for loading TSM with a design state provided by
OmniSim for the View Circuit Values function. Hence, the simulate action cannot be
carried out.
USER RESPONSE:
No response required. Do not attempt to use the simulate pin action while using View
Circuit Values.
WARNING (TPD-208): View Circuit Values was unable to action shared memory in
order to provide design state data for a simulate request. (The system errno =
sys_errno) The simulate action cannot be completed.
EXPLANATION:
Shared memory is required in order to provide design state data to another function
which then carries out the simulate request. The required memory could not be obtained
and due to this, the simulate action cannot be carried out. The system errno was
returned from the operating system when the request for shared memory was
processed.
USER RESPONSE:
If the processor this application is running on is being heavily used, try running on a
different machine. If problems persist, contact customer support (see Contacting

ERROR (TPD-900): View Circuit Values received a terminating condition from the
simulation of sequence target_sequence. As a result of this, the View Circuit Values
function terminates. Please try a different sequence or resolve the terminating conditions by
direct simulation using the simulator simulator. The text of the simulator message is as
follows -- sim_terminating_msg_text
EXPLANATION:
Using the noted simulator to simulate the specified sequence, View Circuit Values
received a terminating response from the simulation.
This result causes the View Circuit Values function to terminate. Refer to the simulator
message (included) for a general idea of what the problem was. Depending on the
number of sequences simulated and viewed with the View Circuit Values function, any
odometer values in the actual simulator message may not be correct.
USER RESPONSE:
A different sequence may be viewed or use the simulator noted in the message to
resimulate the sequence for more complete information on the problem. Refer to
Simulate Vectors in the Encounter Test: Reference: GUI.


60
TPL - Pipeline Verification Messages
TPL-001 through TPL-050 on page 1759

TPL-060 through TPL-296 on page 1770
TPL-001 through TPL-050

INFO (TPL-001): There are no latches on this part. TPL
EXPLANATION:
No latch primitives exist in the logic model for this circuit. prepare_pipeline_sequence
looks for limitations of the test sequences in terms of how the latches are or are not
exercised. Since there are no latches in this circuit, the analyzer has nothing to do.
USER RESPONSE:
No action is required. Do not expect any useful information about the test sequences for
this circuit from prepare_pipeline_sequence.
ERROR (TPL-002): Required command line parameter parameter_name missing.

EXPLANATION:
A required parameter is missing from the prepare_pipeline_sequence command.
prepare_pipeline_sequence can not run without the information supplied by this
parameter.
USER RESPONSE:
Check the spelling on all the parameters. If you are not sure of all the required
parameters, determine the value for the missing parameter and try again.
WARNING (TPL-003): [Severe] Sequence definition sequence_name was not found.

EXPLANATION:

The named sequence definition was requested for verification, but it cannot be found in
the TBDseq file. Checking will proceed if other requested sequence definitions were
available.
USER RESPONSE:
Make sure you specified the correct sequence name. If the name is correct, then import
the sequence definition and rerun.
ERROR (TPL-004): None of the requested sequence definitions were found.

EXPLANATION:
None of the sequence definitions you asked to be checked could be found in the TBDseq
file. The pipeline verification program is quitting.
USER RESPONSE:
Import your sequence definitions and rerun.
ERROR (TPL-005): Experiment name not specified.

EXPLANATION:
You asked for the simulation results to be written (writepatterns=yes) but no
experiment name was specified. The experiment name is needed for naming the output
file.
USER RESPONSE:
Specify any arbitrary name for the experiment and rerun.
WARNING (TPL-007): [Severe] Sequence sequence_name turns on two oscillators at

once, primary inputs pin_name and pin_Name. Analysis proceeds with second pin set to
X.
EXPLANATION:
This is a limitation of Encounter Test. It performs a static simulation during the sequence
verification process, and therefore cannot synchronize two different oscillator signals.
USER RESPONSE:
If you get no other error messages from sequence verification, then there should be no
ill effects from this condition. However, this probably means that the second oscillator is
unnecessary for the operation that this sequence performs.
If other error messages appear, they may have been caused by this condition; if possible,
edit the sequence and remove one of the Start_Osc events. If you cannot do this and still

make the sequence work, then try reversing the order in which the oscillators are turned
on; this will cause the other one to be set to X for the verification. If this still does not work,
then the tool is unable to verify that the sequence is good.
WARNING (TPL-008): [Severe] Sequence sequence_name overrides TI pin

pin_Name with a event_name event.
EXPLANATION:
By definition, a TI pin is not allowed to be switched within the test mode in which this test
function attribute is specified. This message serves as a warning that this sequence
deviates from the designated test function of the pin, and subsequent processing of this
sequence by other Encounter Test application programs will also result in severe error
messages.
USER RESPONSE:
Edit the sequence definition and remove the event that is attempting to exercise this pin.
Re-import the sequence definition and rerun prepare_pipeline_sequence.
WARNING (TPL-009): [Severe] Sequence seqeuence_name overrides TC pin

pin_name with a event_name event.
EXPLANATION:
By definition, a TC pin is not allowed to be switched within a test sequence. This
message is printed only if the named sequence has a type of "test" and serves as a
warning that this sequence deviates from the designated test function of the pin.
Subsequent processing of this sequence by other Encounter Test application programs
will also result in severe error messages.
USER RESPONSE:
Re-import the sequence definition and rerun Sequence Effectiveness Checking.
WARNING (TPL-010): [Severe] The TC primary_input|pseudo_PI|latch

pin_name was set to the wrong state at the end of sequence sequence_name.
EXPLANATION:
Sequences of types other than "test" are allowed to exercise TC pins, but all sequences
(modeinit, scanop, setup) must leave the TC pins at their designated states. This pin was
not restored to its designated state by the named sequence.
USER RESPONSE:

Edit the sequence definition by adding a Stim event to set this pin to its designated state
(or add this pin to an existing Stim event). Re-import the sequence definition and rerun
prepare_pipeline_sequence.
WARNING (TPL-011): [Severe] Sequence sequence_name overrides TI|TC pseudo

PI pin_name with a event_name event.
EXPLANATION:
The named pseudo PI must remain constant throughout the sequence, by definition of
its TC/TI test function attribute. The named sequence deviates from this by specifying a
different value on the pseudo PI.
USER RESPONSE:
Examine the design model and the pattern sequence to determine how this pseudo PI
was switched. There is an error in the sequence, or in the design, or in the test function
attribute assigned to this pseudo PI. If the design is wrong, you will have to correct it and
rebuild the model. If it is a wrong attribute on the pseudo PI, this can be corrected by an
override in the mode definition file; edit the mode definition file and rerun Build Test
Mode. If the error is in the sequence definition, edit the sequence definition, re-import the
sequence definition, and rerun prepare_pipeline_sequence.
WARNING (TPL-012): [Severe] The sequence sequence_name specifies a

Scan_Load|Channel_Scan event but the design was not in the TG stability state.
EXPLANATION:
Scan operations (Scan_Load, Channel_Scan) must start and end with the design in the
test generation stability state. The design is said to be in the test generation stability state
if, and only if:
All clocks (both primary inputs and pseudo primary inputs) are at their defined
"off" states,
All TI signals (primary inputs, pseudo primary inputs, and fixed-value TI latches)
are at their defined states, and
All TC signals (primary inputs, pseudo primary inputs, and TC latches) are at
their defined states.
By the definition of the TG stability state, test sequences are constrained to that state,
except when pulsing a clock. Therefore, the scan operation always starts and ends with
the design in the TG stability state.
USER RESPONSE:

Examine this sequence to determine which pins (or pseudo PIs or latches) were not at
their TG stability state values. This includes all TI, clock, and TC primary inputs. Since a
deviation from a TI state causes another error message, the problem is almost sure to
be on a clock or TC signal. Use View Circuit Statistics on the View pulldown menu to get
a list of TC latches.
WARNING (TPL-014): [Severe] Force value on net net_name conflicts with normal
circuit activity at event event_id in sequence sequence_name.
EXPLANATION:
This message is issued when a Force event specifies a value to be placed on a net, or
is holding a value on the net, and the normal simulation would have put a different value
on the net. If the severity is WARNING, the normal simulation value is X (unknown). A
WARNING [Severe] message means that normal simulation would have predicted a
known value, different from what the net is being forced to. Usually, the Force event
(when it is needed at all) should be used only to convert an X to the correct known value,
because Encounter Test simulators tend to err on the side of pessimism so that the
known values they predict are correct. The Force event should be used only in complex
situations where the simulator cannot correctly predict the responses without help, and
the user understands exactly what he/she is doing.
USER RESPONSE:
Examine the sequence and the simulation results carefully to make sure that the Force
event was correctly specified. If not, then edit the sequence to remove it. Then re-import
the sequence and rerun prepare_pipeline_sequence.
WARNING (TPL-018): [Severe] conflict_type three-state conflict detected during

simulation of event event_ID in sequence sequence_name.
EXPLANATION:
Not all Encounter Test processes simulate the OPC logic; therefore, the sequence
verifier may be the only opportunity to catch three-state conflicts on nets in this logic. All
potential conflicts are flagged as problematic, because it is expected that the OPC logic
should seldom if ever contain any uninitialized nets (except very early in the mode
initialization sequence), and these contentions will not be removed by test generation,
since it does not process OPC logic.
USER RESPONSE:
Determine whether the problem was reported early in the mode initialization sequence
before all nets were brought to known states. If this is the case, you may be able to safely
ignore the message. Otherwise, you will need to modify the sequence to remove any
possibility of three-state conflicts. Edit the sequence definition, then re-import the
sequence and rerun prepare_pipeline_sequence.

WARNING (TPL-019): [Severe] conflict_type three-state conflict detected during

simulation of event event_id in sequence sequence_name.
EXPLANATION:
A definite three-state contention problem was discovered.
USER RESPONSE:
Edit the sequence definition to remove the contention. Re-import the sequence and
rerun prepare_pipeline_sequence.
WARNING (TPL-020): [Severe] An oscillator was activated at event event_ID in

sequence sequence_name, but the design is not stable. Subsequent events will not be
properly synchronized with the oscillator.
EXPLANATION:
The event being referred to is a Wait_Osc (Cycles=0) event. This implies that subsequent
design activity will be affected by the com ing events and the oscillator signal itself. This
design activity is predictable only if the design is currently in a stable state with the
oscillator running. Simulation of some number of oscillator cycles reveals that the design
is not yet stable, and therefore any further simulation will likely be invalid. Analysis
proceeds from the current (arbitrary) state.
USER RESPONSE:
Check the sequence definition to make sure that all events were correctly specified for
predictable operation of the circuit. Correct the sequence, re-import it, and rerun
If the sequence is correct, make sure that the verifier is running enough oscillator cycles
to allow the design to settle down. Maximum number of cycles required is specified as a
parameter on the Wait_Osc event. If this number was too small, edit and re-import the
sequence definition and rerun prepare_pipeline_sequence.
If the sequence is correct and the Wait_Osc cycles parameter is large enough, then
check the design. If the design is incorrect, correct it and re-import it.
If none of the above corrective actions apply, then you may have a complex design which
circulates through two or more design states in the "steady state" condition. If this is the
case, consider using a Force event to prescribe the arbitrary state from which simulation
will proceed.
WARNING (TPL-021): [Severe] The cycle count specified in the Wait_Osc event
event_id in sequence sequence_name did not allow the design to settle down.
Subsequent events may not be properly synchronized with the oscillator.

EXPLANATION:
The design was not in a steady-state condition after the specified number of oscillator
cycles. This is the number of oscillator cycles since the previous Wait_Osc event or the
previous Start_Osc event. Subsequent stimuli applied to the design with the free-running
oscillator will produce unpredictable results unless they are timed precisely in
relationship with the oscillator.
USER RESPONSE:
Verify that you intended to apply the input stimuli in lock-step with the oscillator pulses.
If this was intended, then make sure that the test equipment has the capability of doing
this. (You may have to consult with the manufacturer or whoever is responsible for the
test hardware.)
WARNING (TPL-023): [Severe] Test sequence sequence_name1 specifies setup

sequence sequence_name2, but sequence_name2 is not of type "setup". The
sequences are not verified.
EXPLANATION:
Setup sequences have different restrictions than some other sequences; for example,
measure events are not allowed within a setup sequence. This check ensures that only
valid setup sequences will be used as setup sequences.
USER RESPONSE:
Either the setup sequence was given the wrong type, or the test sequence is referring to
the wrong setup sequence. Edit the sequence definitions by either changing the
sequence type of the setup sequence to "setup" or changing the name of the setup
sequence referred to in the test sequence. Then re-import the sequence definition before
using it in a test generation run. It will not be necessary to rerun
WARNING (TPL-025): [Severe] Wait_Osc event encountered in pattern pattern_id

which contains a event_id event in sequence sequence_name.
EXPLANATION:
Wait_Osc events indicate whether the events have to be synchronized with the oscillator.
If the scan operation is under control of a free-running oscillator, the scanop sequence,
not this pattern, must contain the Wait_Osc event.
USER RESPONSE:
If the scan operation is controlled by the oscillator, make sure that the custom scan
sequence definition contains the appropriate Wait_Osc events. In either case, remove
the Wait_Osc event from this pattern.

WARNING (TPL-028): [Severe] A Wait_Osc event, event id event_id in sequence

sequence_name specifies pin pin_name, but this pin is not connected to an oscillator.
EXPLANATION:
Wait_Osc events indicate when the logic is "listening" to a free-running oscillator. This
Wait_Osc event specified a pin that is not currently connected to a free-running oscillator,
so it makes no sense. A Start_Osc event calling out the specific pin is required before
using a Wait_Osc event.
USER RESPONSE:
Check the sequence definition to make sure there is not a misplaced Stop_Osc event
that disconnected the oscillator before this Wait_Osc event was reached. Edit the
sequence definition by removing a Stop_Osc event or inserting a Start_Osc event so that
the oscillator is connected before the Wait_Osc event. If this is a test sequence with an
associated setup sequence, it is likely that you will want to put the Start_Osc event in the
setup sequence.
WARNING (TPL-029): Stop_Osc event for pin pin_name found in sequence

sequence_name but oscillator was not started on this pin.
EXPLANATION:
The Stop_Osc event has the same effect as a Stim_Clock event, but it is intended to be
used in cases where the pin was previously connected to a free-running oscillator. This
pin does not appear to have been connected to an oscillator, as no previous Start_Osc
event for this pin was in effect.
USER RESPONSE:
Make sure the pin was supposed to be oscillating. If so, then insert a Start_Osc event at
a previous point in the sequence where the oscillator was to have been connected. If not,
then change this Stop_Osc event to a Stim_Clock event.
WARNING (TPL-030): [Severe] Start_Osc event encountered in sequence

sequence_name but the specified pin pin_name is neither an OSC nor oTI.
EXPLANATION:
Oscillators can be connected only to pins that are defined to be OSCs or "tied" to an
oscillator (by having an oTI test function). The sequence checker will honor this event,
but you may run into trouble in manufacturing because the pin is not properly defined.
USER RESPONSE:

Make sure you specified the correct pin for the Start_Osc event. If this pin really is
supposed to be connected to a free-running oscillator, put an OSC or oTI test function
attribute on it and rebuild the test mode.
WARNING (TPL-037): [Severe] Signature observation sequences are not supported by

TPL.
EXPLANATION:
You specified a sequence that is not a test sequence. The Pipeline Sequence Analysis
works only on test sequences.
USER RESPONSE:
Make sure you did not intend to check a sequence with some other name. If this
sequence was just an extra sequence that was inadvertently specified, no action is
necessary.
WARNING (TPL-038): [Severe] A nonscanflush or scanfill sequence was defined

but no pulse events were defined in the sequence. Add pipeline clock pulse events to the
sequence to sufficiently load the pipeline latches and rerun.
EXPLANATION:
Clock pulse events must appear in the nonscanflush or scanfill sequence to load
the non-scan latches in the pipeline.
USER RESPONSE:
Ensure clock pulse events appear in the nonscanflush or scanfill sequence to
control the pipeline latches. Re-read the sequence definition and rerun Pipeline
Sequence Analysis.
WARNING (TPL-040): A stim PI or stim PPI event occurred in a non-scan flush or scan fill
sequence while the pipeline clocks were being pulsed. This is not recommended.
EXPLANATION:
Stim events must not occur while the pipeline clocks are being pulsed.
USER RESPONSE:
Move the stim event outside the pipeline clock pulse events. re-import the sequence
definition and rerun prepare_pipeline_sequence.

with pipeline clock clock_name but clock_name is not defined as a clock. Ensure the

correct clock is being used to control the pipeline. If it is, add a valid clock test function to this
pin.
EXPLANATION:
A clock pulse event appeared in the nonscanflush or scanfill sequence but the
clock does not have a clock test function attribute associated.
USER RESPONSE:
Ensure the correct clock is being used in the pulse event. If it is, add a valid clock test
function to this pin. Refer to System and Scan Clocks in the Encounter Test: Guide
2: Testmodes.
WARNING (TPL-042): A nonscanflush sequence and a scanfill sequence were

found in the sequence definition file. Only the nonscanfill sequence will be processed.
EXPLANATION:
When both a nonscanflush sequence and a scanfill sequence exist, only the
nonscanfill sequence is processed
USER RESPONSE:
If you do not want the nonscan flush sequence processed, either remove it from the the
sequence definition file or specify the desired sequence name on the command line
using the testsequence= keyword.
WARNING (TPL-043): [Severe] The sequence sequence_name is not a nonscan flush

or scan fill sequence. Only nonscan flush and scan fill sequences can be processed.
EXPLANATION:
An invalid sequence name has been entered on the command line using the
testsequence keyword. Only nonscan flush and scan fill sequences can be
processed.
USER RESPONSE:
Remove the named sequence from the testsequence keyword.
WARNING (TPL-044): [Severe] The num_pulses clock pulses in the non-scan flush or
scan fill sequence do not completely load the non-scan latches which have a calculated
maximum depth of max_depth.
EXPLANATION:
There are not enough clock pulses in the non-scan flush or scan fill sequence to
completely load the non-scan latches.

USER RESPONSE:
Check that there is a sufficient number of clock pulse events in the non-scan flush
sequence to load the non-scan flush or scan fill sequence toload the non-scan latches.
re-import the sequence definition and rerun prepare_pipeline_sequence.
WARNING (TPL-045): The num_pulses clock pulses in the non-scan flush or scan fill
sequence are more than what is necessary to load the non-scan latches which have a
calculated maximum depth of max_depth.
EXPLANATION:
There are more than enough clock pulses to completely load the non-scan latches.
USER RESPONSE:
Check the number of clock pulse events in the non-scan flush or scan fill sequence. Re-
import the sequence definition and rerun prepare_pipeline_sequence.
WARNING (TPL-046): A scanfill sequence was defined but no active non-scan latches
are clocked by the scanfill sequence. Ensure the pipeline clocks are correctly controlling
the pipeline latches.
EXPLANATION:
Active non-scan latches must be clocked on each pulse event in the scanfill
sequence to be considered a pipeline latch. No pipeline latches were found after
simulation of the scanfill sequence.
USER RESPONSE:
Ensure the clocks are correctly connected to the desired pipeline latches.

but no active non-scan latches are clocked by the nonscanflush or scanfill sequence.
Ensure the pipeline clocks are correctly controlling the pipeline latches.
EXPLANATION:
Active non-scan latches must be clocked on each pulse event in the nonscanflush or
scanfill sequence to be considered a pipeline latch. No pipeline latches were found
after simulation of the nonscanflush or scanfill sequence.
USER RESPONSE:
Ensure the clocks are correctly connected to the desired pipeline latches. Refer to
Pipelined Control Signals in the Encounter Test: Guide 2: Testmodes.

WARNING (TPL-048): A nonscanflush or scanfill sequence was defined but no scan

registers have been identified for the test mode. Ensure the latches are correctly configured.
EXPLANATION:
There are no scan latches identified on the part for this test mode but there are scan-in
PIs. This could cause a problem when bounding the pipelines.
USER RESPONSE:
Ensure the latches are correctly configured, combining scan and non-scan latches. Refer
to Pipelined Control Signals in the Encounter Test: Guide 2: Testmodes.
WARNING (TPL-049): Depth checking for the nonscan flush or scanfill sequence will not be
performed on user request.
EXPLANATION: You have chosen not to perform depth checking on the nonscan flush
or scanfill sequence.
USER RESPONSE: Ensure this option is what you intended to use.
WARNING (TPL-050): [Severe] An error was found in the lineholds for sequence
sequence_name.
EXPLANATION:
The linehold utility program found a problem in the lineholds specified within the
sequence definition. There should be other messages (prefix TLH) that explain the
problem.
USER RESPONSE:
Look for TLH messages to ascertain the problem. Verify that you intended to specify
linehold information within the sequence definition. Correct the problem by removing or
correcting the linehold information in the sequence definition, re-import the sequence
definition, and rerun Pipeline Sequence Analysis.
TPL-060 through TPL-296

INFO (TPL-060): Processing sequence sequence_name.
EXPLANATION:
The named sequence definition has been found in the TBDseq file and is currently being
processed.
USER RESPONSE:

No action is necessary.
WARNING (TPL-070): Scannable latch latch_name, port clock pin clock_name was
pulsed in sequence sequence_name.
EXPLANATION:
The non scan flush sequence caused a scannable latch to be pulsed causing the data
held in this latch to be corrupted.
USER RESPONSE:
Make sure the sequence is pulsing the correct clocks. If not, edit and re-import the
WARNING (TPL-072): Non-scan latch latch_name was not clocked in event event of
the non-scan flush sequence and will not be considered part of the pipeline.
EXPLANATION:
This event does not clock any port on this latch. Thus, data will not be propagated by this
sequence.
USER RESPONSE:
WARNING (TPL-074): Multiple ports on pipeline latch latch_name were clocked in

sequence sequence_name.
EXPLANATION:
This sequence pulsed more than one port on this pipeline latch. Thus, the pipeline data
will not be propagated correctly by this sequence.
USER RESPONSE:
WARNING (TPL-075): The first port of multi-port non-scan latch latch_name was clocked
in sequence sequence_name.
EXPLANATION:
The test generator may produce incorrect tests if the nonscanlatch value is set to
buffer.

USER RESPONSE:
WARNING (TPL-076): number_csls correlated stim latches and number_asls

alternate stim latches were pulsed in sequence sequence_name.
EXPLANATION:
The non-scan flush sequence caused scannable latches to be pulsed causing the data
held in these latches to be corrupted.
USER RESPONSE:
INFO (TPL-077): latch_name

EXPLANATION:
This message prints the name of a correlated or alternate stim latch that was pulsed
during the non-scan flush sequence.
USER RESPONSE:
Make sure the sequence is pulsing the correct clocks. If not, edit and reimport the
ERROR (TPL-080): A nonscanflush or scanfill sequence of depth depth was

defined but no non-scan latches have been identified for the test mode. Ensure the latches
are correctly configured.
EXPLANATION:
There are no non-scan latches identified on the part for this test mode. Pipeline latches
must be of the non-scan type.
USER RESPONSE:
Ensure the latches are correctly configured, combining scan and non-scan latches.
Refer to Pipelined Control Signals in the Encounter Test: Guide 2: Testmodes.
INFO (TPL-081): A scanfill sequence was defined but no non-scan latches have been
identified for the test mode. Ensure the latches are correctly configured.
EXPLANATION:

There are no non-scan latches identified on the part for this test mode. Pipeline latches
must be of the non-scan type.
USER RESPONSE:
Ensure the latches are correctly configured, combining scan and non-scan latches.
Refer to Pipelined Control Signals in the Encounter Test: Guide 2: Testmodes.
INFO (TPL-082): Pipeline latch_name was clocked in both the scanfill and non-scan flush
sequences.
EXPLANATION:
The identified latch was clocked when simulating both the scanfill and non-scan flush
sequences.
USER RESPONSE:
INFO (TPL-092): Pipeline latch latch_name was calculated to be at a depth of

pipeline_depth in the pipeline beginning with latch latch_name but was at a depth of
pipeline_depth in the pipeline beginning with latch latch_name.
EXPLANATION:
A pipeline latch is shared between pipelines, but is at different depths in those pipelines.
The program attempts to ensure that the length of the pipeline is consistant and the
number of pulses in the non-scan flush or scan fill sequence is sufficient to load all
pipeline latches.
USER RESPONSE:
Check that the pipeline latches are correctly configured. If not, edit and rebuild the model
and then rerun prepare_pipeline_sequence.
WARNING (TPL-094): [Severe] Feedback exists from pipeline latch latch_name back
to itself in the pipeline beginning with latch latch_name.
EXPLANATION:
A signal path was found extending from the specified pipeline latch back to itself.
USER RESPONSE:

WARNING (TPL-096): Latch latch_name in the pipeline starting with latch

latch_name has a calculated depth of depth which exceeds the maximum pipeline depth
of depth as determined by the number of clock pulse events in the nonscanflush or
scanfill sequence. Ensure the number of clock pulses in the sequence is correct and that
the pipeline is correctly configured.
EXPLANATION:
A pipeline latch was found at a depth which exceeded the number of clock pulses in the
nonscanflush or scanfill sequence. This implies that the latch would not be loaded
with the data placed on the starting pipeline latch.
USER RESPONSE:
WARNING (TPL-098): latch_count pipeline latches have exceeded the maximum

number of nodes specified when tracing to find the beginning of the pipelines. These
latches will not be considered pipeline latches.
EXPLANATION:
Pipeline latches are normally bound by scannable latches. If this is not the case,
the tracing function will spend much time tracing outside this boundary. To limit the
search time, specify a maximum number of trace nodes.
USER RESPONSE:
Check that the pipeline latches are correctly configured. If not, edit and reimport
the part then rerun Pipeline Sequence Analysis.
WARNING (TPL-100): [Severe] The file, file_name, is not writeable, therefore the
results of this prepare_pipeline_sequence run cannot be saved.
EXPLANATION:
USER RESPONSE:
WARNING (TPL-101): [Severe] The file, file_name, is not readable, therefore the
results of this prepare_pipeline_sequence run cannot be saved.
EXPLANATION:

USER RESPONSE:
WARNING (TPL-103): [Severe] The directory, directory_name, is not writeable,

therefore the results of this prepare_pipeline_sequence run cannot be saved.
EXPLANATION:
USER RESPONSE:
writeable.
WARNING (TPL-104): [Severe] The directory, directory_name, is not readable,

therefore prepare_pipeline_sequence cannot be run.
EXPLANATION:
USER RESPONSE:
readable.
WARNING (TPL-108): You have chosen not to run TPLmain at this time.
EXPLANATION:
When build_testmode calls TPLmain, there may not be enough resources for both
programs. This option will allow TPLmain to terminate and run later in standalone mode.
USER RESPONSE:
Run prepare_pipeline_sequence in standalone mode using the command line.
WARNING (TPL-110): [Severe] Attempt to register experiment experiment_name on

EXPLANATION:
The reason for the failure cannot be determined by prepare_pipeline_sequence.
USER RESPONSE:

corrective action.
WARNING (TPL-111): [Severe] Attempt to register a dependency of experiment|file

against the mode|experiment on the globalData file failed.
EXPLANATION:
The reason for the failure cannot be determined by MSV. Processing terminates.
USER RESPONSE:
corrective action.
WARNING (TPL-112): [Severe] Attempt to register file file_name on the globalData file
failed.
EXPLANATION:
USER RESPONSE:
WARNING (TPL-113): [Severe] Attempt to save file file_name in the globalData file
failed.
EXPLANATION:
USER RESPONSE:
Determine why the file could not be saved.
WARNING (TPL-120): [Severe] The TPL function, function_name, could not find the
file file_name.
EXPLANATION:
MSV attempted to open the file listed but the file does not exist. Processing terminates.
USER RESPONSE:
Ensure the file exists and rerun prepare_pipeline_sequence.

WARNING (TPL-121): [Severe] The TPL function, function_name, was unable to open
the file file_name.
EXPLANATION:
TPL attempted to open the file listed but was unsuccessful. Processing terminates.
USER RESPONSE:
Determine the reason (check things such as permission bits and file space), and rerun
WARNING (TPL-122): [Severe] The TPL function, function_name, could not write data
to the file file_name.
EXPLANATION:
TPL attempted to write to the file listed but was unsuccessful. Processing terminates.
USER RESPONSE:
the file name spelling is correct), and rerun prepare_pipeline_sequence.
WARNING (TPL-123): [Severe] The TPL function, function_name, could not read data
from the file file_name.
EXPLANATION:
TPL attempted to read from the file listed but was unsuccessful.
USER RESPONSE:
WARNING (TPL-124): [Severe] The TPL function, function_name, could not close the
file file_name.
EXPLANATION:
TPL was unable to close the file listed.
USER RESPONSE:

WARNING (TPL-125): [Severe] The file, file_name, has a file ID of file_Id1 in the
file header. The file ID should be file_Id2 in order to run this version of
EXPLANATION:
prepare_pipeline_sequence was unable to verify the file header for the filename
listed. The file was created with an old level of prepare_pipeline_sequence and
cannot be processed by the current level.
USER RESPONSE:
Re-run with the current level of prepare_pipeline_sequence.
ERROR (TPL-130): No sequence definitions were found in the Sequence Definitions file.
EXPLANATION:
file. The sequence checker is quitting.
USER RESPONSE:
ERROR (TPL-132): The Sequence Definitions file containing the nonscanflush or scanfill
sequence could not be opened.
EXPLANATION:
The Sequence Definitions file of the form TBDseq.{testmode} could not be opened.
Check the file permissions for write access. The pipeline verification program is quitting.
USER RESPONSE:
Change the permissions of the TBDseq file to read/write access and rerun.
WARNING (TPL-172): Non-scan flushed L1 latch latch_name was not clocked in event
event of the non-scan flush or scan fill sequence and will not be considered part of the
pipeline.
EXPLANATION:
The referenced event does not clock any port on the referenced flushed latch. Thus, data
may not be propagated by this sequence.
USER RESPONSE:
Ensure the sequence is pulsing the correct clocks. If not, edit, re-import the sequence
definition, and then rerun Pipeline Sequence Analysis.

WARNING (TPL-244): The num_pulses clock pulses from PI pin clock_name in the
nonscan flush or scan fill sequence do not completely load the nonscan latches for this clock
which has a calculated maximum clock depth of max_depth.
EXPLANATION:
There are not enough clock pulses from this clock in the nonscan flush or scan fill
sequence to completely load the nonscan latches.
USER RESPONSE:
Check that there are a sufficient number of clock pulses for this clock in the nonscan flush
of scan fill sequence to load the nonscan latches. Re-import the sequence definition and
rerun prepare_pipeline_sequence.
WARNING (TPL-245): The num_pulses clock pulses from PI pin clock_name in the
nonscan flush or scan fill sequence are more than what is necessary to load the nonscan
latches which has a calculated maximum clock depth of max_dept.
EXPLANATION:
There are more than enough clock pulses to completely load the non-scan latches from
this clock.
USER RESPONSE:
Check the number of clock pulses for this clock in the nonscan flush or scan fill sequence.
Re-import the sequence definition and rerun prepare_pipeline_sequence.
WARNING (TPL-272): Non-scan flushed L2 latch latch_name was not clocked in event
event of the non-scan flush or scan fill sequence and will not be considered part of the
pipeline.
EXPLANATION:
The referenced event does not clock any port on the referenced flushed latch. Thus, data
may not be propagated by this sequence.
USER RESPONSE:
Ensure the sequence is pulsing the correct clocks. If not, edit, re-import the sequence
definition, and then rerun Pipeline Sequence Analysis.
WARNING (TPL-290): The data in pipeline latch latch_name, controlled by clock

clock_name, may not be captured by successive latch latch_name because the clock for
this latch, clock_name, was not pulsed in time to capture the data.
EXPLANATION:

The data in a pipeline latch was not capture by a successive latch because the
successive latch's clock was not pulsed before its preceding latch was pulsed. This
message is issued only for non-scan flush sequences.
USER RESPONSE:
Check that the number of clock pulse events and clock pins are in the correct order. If
not, edit the non-scan flush sequence and rerun build_testmode.
WARNING (TPL-296): The number of clock pulses for pipeline latch latch_name in the
pipeline beginning with latch latch_name is insufficient to load the latch with the pipeline
contents. The primary input clock to this latch is clock_name which is pulsed num_pulses
times but the depth of this latch for this clock is latch_depth.
EXPLANATION:
When loading the pipeline, there must be a sufficient number of primary input clock
pulses to load all latches in the pipeline. This pipeline latch does not have enough clock
pulses to load the latch with the contents of the pipeline.
USER RESPONSE:
Ensure the pipeline latches and clocks are correctly configured. If it is apparent that the
number of primary input pulse events is the cause of the problem, add the correct
number of pulse events to the non-scan flush sequence and rerun

61
TPO - Messages
TPO-001 through TPO-099 on page 1781

TPO-001 through TPO-099

INFO (TPO-001): Ended at: date-time
EXPLANATION:
Indicates the end of the log (except for the summary section) and gives the date and time
the run ended.
USER RESPONSE:
None.
ERROR (TPO-002): PFILEdir keyword was not specified. You must specify the name of the
directory where the PLL and deskewer programming files are located. The run will stop.
EXPLANATION:

TPO - Messages
The pfiledir keyword is required, but it was not specified, so the PFILEs will be able
to be found.
USER RESPONSE:
Add the keyword pfiledir=<directorypath> to the command and submit the job
again.
ERROR (TPO-003): Cannot find test plan file testplan. The run will stop.
EXPLANATION:
Either the test plan file does not exist, or it was specified incorrectly on the command line.
USER RESPONSE:
Check to see that the file exists and that it was specified correctly on the testplan
keyword. Then correct the problem and resubmit the job. You may run the
prepare_opcg_input command without specifying a testplan keyword if you want
only to report the OPCG information in the model and the PFILEs, but it will not produce
any output files to allow the building of the testmode.
ERROR (TPO-004): Invalid keyword specified: keyword-value_string. The run will

stop.
EXPLANATION:
The value specified is not valid for this keyword.
USER RESPONSE:
Read the help text for this command and specify a valid value for this keyword. Then
resubmit the job.
ERROR (TPO-006): Can not find PFILE directory directorypath.

EXPLANATION:
The PFILE directory does not exist, or it was specified incorrectly.
USER RESPONSE:
Determine what directory the PFILEs are in, and specify this directory on the pfiledir
keyword. Check for incorrect spelling. Then resubmit the job.
ERROR (TPO-007): Invalid directory specified: keyword=directoryname The run will

stop.
EXPLANATION:

TPO - Messages
The indicated keyword specifies the directory for the corresponding output file, but the
specified directory does not exist.
USER RESPONSE:
Check for spelling errors. Specify the correct directory name and resubmit the job.
INFO (TPO-009): Keywords/Values information.

EXPLANATION:
the values specifed on the keywords in the command line and keywords that have
program-generated values. In the case of user-specified keywords, a "+" indicates that
the keyword specification was unnecessary because the keyword would have defaulted
to that value anyway.
USER RESPONSE:
None.
ERROR (TPO-010): build_testmode failed with a return code of returncode. Consult

the log file log_build_testmode_modename for further information.
EXPLANATION:
Before building the requested testmode, a temporary version of the testmode is first built
so that the analysis can be performed which is necessary to create the input files for the
final testmode build. That preliminary build_testmode command, which is invoked
automatically under the covers, failed as indicated by the printed return code.
USER RESPONSE:
It is seldom necessary to respond to this message unless the TPO-989 message
appears. If you wish to investigate, find the TTMdef.<modename>.temp log file and
look at its message summary to find the reason for the failure.
INFO (TPO-013): Writing linehold file directoryname/filename.

EXPLANATION:
This message gives the directory path and file name of the linehold file and asserts that
the file was produced.
USER RESPONSE:
None.
INFO (TPO-013): Writing linehold file directory name/filename.

TPO - Messages
EXPLANATION:
This message gives the directory path and file name of the linehold file and asserts that
the file was produced.
USER RESPONSE:
None.
INFO (TPO-014): Writing test generation command file directoryname/filename.

EXPLANATION:
This message gives the directory path and file name of the test generation command file
and asserts that the file was produced.
USER RESPONSE:
None.
INFO (TPO-016): Writing textstring file directoryname filename.

EXPLANATION:
This message gives the directory path and file name of the indicated output file and
asserts that the file was produced.
USER RESPONSE:
None.
ERROR (TPO-017): No OPCG registers were identified by netlist properties. The run is
stopping.
EXPLANATION:
The build_opcg_testmode command expects control registers to be defined by
which the on-product clock generation logic is programmed, and it gets confused if there
are no such registers. The check which produces this message provides for a graceful
exit when the build_opcg_testmode command is run on a non-opcg testmode for
which it was not designed to work.
USER RESPONSE:
Use the build_testmode command for a non-opcg testmode or for an opcg testmode
which has no internal control registers to be identified. If this testmode has internal
control registers, make sure they are properly specified in the netlist.

TPO - Messages
ERROR (TPO-018): No input specified in the parameter string. The run stops. See the
following help text.
EXPLANATION:
The verify_asst_frequencies command takes its input from the command line in
the form of a help keyword extendedhelp or -h or in the form of a list of decimal
numbers specifying the oscillator frequencies to be used. In this case, the command was
issued with no input, so verify_asst_frequencies does not know what to do,
except to print the help text which follows this message.
USER RESPONSE:
Read the help text to see how to use the command.
WARNING (TPO-019): The specified testperiod of decimal1 is less than the minimum
testperiod, which is decimal2. The calculations will use the specified testperiod, but this
may not work at the tester.
EXPLANATION:
The verify_asst_frequencies command has a built-in minimum testperiod
ofdecimal2 nanoseconds. This is the reciprocal of the maximum tester frequency.
The testperiod specified as decimal2 is less than the minimum. The specified
testperiod will be used.
USER RESPONSE:
Ignore this message if your tester can support the testperiod that was specified.
Otherwise, rerun the command with a testperiod that is supported by your tester.
ERROR (TPO-020): An invalid value was specified for the pathfiledir keyword.
pfiledir=textstring. This keyword must specify a complete directory name, but its
value field does not begin with the slash (/) character.\n Rerun the command with a fully-
specified directory name for the pathfiledir keyword.
EXPLANATION:
The pathfiledir keyword specifies a complete directory name, but this character string
does not begin with a slash (/) character, so it is not a complete directory name. The
build_opcg_testmode command will not make any assumptions regarding the
starting point for this directory path.
USER RESPONSE:
Rerun the command with the directory name on the pathfiledir keyword fully
specified. It must start with a slash.

TPO - Messages
INFO (TPO-021): No model properties found for commandname to process. Normal

build_testmode processing will occur.
EXPLANATION:
It might be expected that if either of the commands build_opcg_testmode or
build_internal_domains_testmode is being used, there should be some model
properties, such as TB_OPCG_PFILE or TB_INTERNAL_DOMAINS_PFILE (or
INSTANCE, or REGNAME) specified to guide the processing. Without such model
properties,these commands can not do any of the special processing they are designed
for. However, some people find it convenient to use one of these commands (for example,
build_internal_domains_testmode on circuits that do not need the extra
processing (because there are no cells with these special properties), instead of invoking
a different command (build_testmode). Accordingly, the
build_internal_domains_testmode and build_opcg_testmode commands
detect when these model properties do not exist, and in such a case, function as a
wrapper for the build_testmode command. This message is an alert that this
situation was found.
USER RESPONSE:
If you intended the invoked command (build_internal_domains_testmode or
build_opcg_testmode) to function as a wrapper for build_testmode when there is no
special processing for it to do, then no response is necessary. If the invoked command
was expected to do some special processing before calling build_testmode, then
investigate why these model properties were not found. It could be a case of using the
wrong cell library, or the model properties are improperly named in the netlist.
INFO (TPO-022): Audit information for PFILE filename: Date=date Time=time

Checksum=integer
EXPLANATION:
This is a copy of the audit information that is intended to be put on the TMD file. It is
included in the log for debug purposes when problems occur. In the event that the circuit
is reprocessed, and the results do not match, this information will tell if there is a
possibility that some programming file (PFILE) information has changed.
USER RESPONSE:
None.
INFO (TPO-023): No audit information found for PFILE filename. A dummy audit record
is being created.
EXPLANATION:

TPO - Messages
The programming file (PFILE) did not have a PFILE_DEFINITION record. A dummy
record is being constructed for inclusion in the TMD audits. The dummy record will
contain all zeros for the date, time, and checksum.
USER RESPONSE:
None.
ERROR (TPO-057): No INTERNAL_DOMAIN registers were identified by netlist properties.

The run is stopping.
EXPLANATION:
The build_internal_domains_testmode command expects control registers to be
defined by which the clock macro is programmed, and it gets confused if there are no
such registers. The check which produces this message provides for a graceful exit
when the build_internal_domains_testmode command is run on a testmode for
which it was not designed to work.
USER RESPONSE:
Use the build_testmode command if this is not an internal_domains testmode. If
this testmode has internal control registers, make sure they are properly specified in the
netlist.
ERROR (TPO-058): Unable to open testmode definition file filename. The run is stopping.
EXPLANATION:
The program was not able to read this file.
USER RESPONSE:
Make sure the file exists. Check for spelling errors in both the modedefpath and the
modedef keyword values. Correct the error and rerun the job.
ERROR (TPO-059): prepare=sidescantm was specified, but no sidescan control pin was
found. This pin would have been recognized by the test function combination TI and CTL. The
run is stopping.
EXPLANATION:
Specifying prepare=sidescantm requests build_internal_domains_testmode
to only create a special testmode initialization sequence and then call build_testmode.
This testmode initialization sequence initializes PREICG cells that are driven by out-of-
phase clocks by setting the scan state and pulsing a special clock with the circuit out of
the SIDESCAN testmode. The SIDESCAN testmode control is identified by one or more

TPO - Messages
pins that have the test functions TI and CTL. No such pin was found, so the special
SIDESCAN testmode initialization can not be performed.
USER RESPONSE:
Make sure this testmode is the SIDESCAN testmode. If it is not, correct the testmode
keyword and rerun the job. If it is the SIDESCAN testmode, determine which pin is
supposed to control the scan chain configuration, give it the CTL test function, and rerun
the job.
ERROR (TPO-060): prepare=sidescantm was specified, but no clock pin was found for
initializing the PREICG circuits. This pin would have been recognized by the test function
combination TI and SC. The run is stopping.
EXPLANATION:
Specifying prepare=sidescantm requests build_internal_domains_testmode
to only create a special testmode initialization sequence and then call
build_testmode. This testmode initialization sequence initializes PREICG cells that
are driven by out-of-phase clocks by setting the scan state and pulsing a special clock
with the circuit out of the SIDESCAN testmode. This special clock is identified by one or
more pins that have the test functions TI and SC. No such pin was found, so the special
SIDESCAN testmode initialization can not be performed.
USER RESPONSE:
Make sure this testmode is the SIDESCAN testmode. If it is not, correct the testmode
keyword and rerun the job. If it is the SIDESCAN testmode,determine which pin is
supposed to control the scan chains for other testmodes, make it a -SC,-TI (or +SC,+TI),
and rerun the job.
WARNING (TPO-061): No testplan file audit information was found for the diagnostic
testmode, testmodename.
EXPLANATION:
The testplan file audit consists of comparing the file name, date, time, and checksum for
the testplan file with the testplan file that was used when the diagnostic testmode was
built. If any of these items differ between the two testplan files, a warning message is
issued. In this case, no testplan file audit information can be found for the diagnostic
testmode, so the check is not possible. The warning message you are looking at does
not necessarily indicate a problem, but it is saying only that the comparison check could
not be done. Unless there is some software bug or system malfunction, this situation
would be caused by the diagnostic testmode having been built by an older level of
Encounter Test, which did not support this checking function.
USER RESPONSE:

TPO - Messages
Find out what level of Encounter Test was used to build the diagnostic testmode. If it is
the same level you are using now, report this condition to your customer support
representative (see Contacting Customer Service on page 23). Otherwise, it is
probably safe to ignore this message.
WARNING (TPO-062): The checksums for the testplan file and the testplan file used to build
the diagnostic testmode do not match. The diagnostic testmode is testmodename. The
testplan file used to build the diagnostic testmode was filename with a date of date and
checksum of textstring. The checksum of the testplan file for this run is textstring.
EXPLANATION:
issued. In this case, the checksums do not match.
USER RESPONSE:
Determine which testplan file is correct. If it is the one used for the diagnostic testmode,
specify that testplan, and rerun this job. If it is the one used for this job, rebuild the
diagnostic testmode, specifying this testplan, and then rerun this job. If the testplans
were supposed to be different, and the correct ones were used for both jobs, then ignore
this message.
WARNING (TPO-063): The dates for the testplan file and the testplan file used to build the
diagnostic testmode do not match. The diagnostic testmode is testmodename. The
testplan file used to build the diagnostic testmode was filename with a date of date. The
date of the testplan file for this run is date.
EXPLANATION:
issued. In this case, the checksums match but the dates do not match.
USER RESPONSE:
Diff the files to see if they are the same. If they are the same, ignore this message.
Otherwise, determine which testplan file is correct. If it is the one used for the diagnostic
testmode, specify that testplan, and rerun this job. If it is the one used for this job, rebuild
the diagnostic testmode, specifying this testplan, and then rerun this job. If the testplans
this message.

TPO - Messages
WARNING (TPO-064): The saved times for the testplan file and the testplan file used to build
the diagnostic testmode do not match. The diagnostic testmode is testmodename. The
testplan file used to build the diagnostic testmode was filename with a date-time of
date_time. The date-time of the testplan file for this run is date_time.
EXPLANATION:
issued. In this case, the checksums match and the dates match, but the saved times do
not match.
USER RESPONSE:
this message.
WARNING (TPO-065): The testplan file name is different from the name of the testplan file
used to build the diagnostic testmode. The diagnostic testmode is testmodename. The
testplan file used to build the diagnostic testmode was path/filename. The name of the
testplan file for this run is filename.
EXPLANATION:
issued. In this case, the checksums, the dates, and the times match, but the file names
are different. Note that the testplan file paths are not compared, although the path for
the diagnostic testmode's testplan file is printed in the message. The path for the current
testmode's testplan file can be found in the command line for this run.
USER RESPONSE:
this message.

TPO - Messages
WARNING (TPO-066): dologictestgen=yes was specified, but no testplan file was

specified. To force logic testgen, you must specify a test plan. dologictestgen will be
treated as no.
EXPLANATION:
As stated in the message text, an invalid keyword combination was specified.
USER RESPONSE:
Make sure the specification of no testplan is correct. If so, you can safely ignore the
message. If you intended to use a testplan, specify the name of the testplan file, and
rerun the job.
WARNING (TPO-067): lbist=yes was specified, but cutpointpropertyname was not

specified. The run will proceed, but no netlist-defined cutpoints will be included.
EXPLANATION:
The intention of LBIST support (lbist=yes) in build_opcg_testmode is to process
designs that have an on-board LBIST engine, which would normally require that the
LBIST engine be isolated from the rest of the logic by the use of cutpoints. Such
cutpoints, and their corresponding pseudo imary inputs (PPIs) and their corresponding
test functions, are normally defined via a netlist property. The name of this netlist
property is specified with the cutpointpropertyname keyword on the
build_opcg_testmode command. With this keyword missing,
build_opcg_testmode does not know how to find the cutpoint information in the
netlist.
USER RESPONSE:
Make sure lbist=yes was not specified by mistake. If it really is an LBIST testmode,
verify that there are cutpoints defined in the netlist. If there are no cutpoints defined in
the netlist, and no need for such cutpoint definitions (an alternative is to manually insert
the cutpoint definitions in the testmode definition file), then ignore this message. If you
choose to define the cutpoints via netlist properties. make sure those properties are
included in the netlist on the appropriate pins, and specify the property name with the
cutpointpropertyname keyword, then rerun the job.
WARNING (TPO-068): lbist=yes was specified, but latchinitpropertyname was

not specified. The run will proceed, but no latches will be initialized from information gained
through netlist properties.
EXPLANATION:
The intention of LBIST support (lbist=yes) in build_opcg_testmode is to process
designs that have an on-board LBIST engine, which would normally require that the

TPO - Messages
LBIST engine be isolated from the rest of the logic by the use of cutpoints. Such
cutpoints would normally be associated with pseudo primary inputs (PPIs) which have
corresponding test functions that require the cutpoint net to be initialized by the testmode
initialiation sequence. The initialization is commonly done with a parent-mode scan load
in the mode initialization sequence. The purpose of the latchinitpropertyname
keyword is to point to netlist properties that identify the latches to be scan-loaded along
with their required values. With this keyword missing, build_opcg_testmode does not
know how to find the latch initialization information in the netlist.
USER RESPONSE:
Make sure lbist=yes was not specified by mistake. If it really is an LBIST testmode,
verify that there are no latches that need to be initialized, other than register latches
which are defined via program file (PFILE) information. If there is indeed no such latch
initialization requirement, then ignore this message. If you choose to identify latch
initialization requirements via a netlist property. Make sure those properties are included
in the netlist on the appropriate pins, and specify the property name with the
latchinitpropertyname keyword, then rerun the job.
ERROR (TPO-069): Can not find the property file propertyfile. The run will stop.
EXPLANATION:
The keyword propertyfile=<filename> was specified, but the specified file,
<filename>, does not exist, or it was specified incorrectly.
USER RESPONSE:
Check to see that the file exists and that it was specified correctly on the propertyfile
keyword. This is an optional input, so if it is not needed, remove the propertyfile
keyword. Correct the problem and resubmit the job.
ERROR (TPO-070): Unable to parse this property statement in file propertyfile. The
statement is textstr. The run will stop.
EXPLANATION:
The format of each statement in the propertyfile is pin=<pinname>
<propertyname>=<propertyvalue>. The statement does not conform with this
syntax.
USER RESPONSE:
Make sure the keyword pin is specified. It is not case-sensitive. Make sure there are no
embedded blank characters and no equal signs in any of the fields <pinname>,
<propertyname>, or <propertyvalue>. Make sure the keyword pin and
<pinname> are separated by an equal sign. Make sure the <propertyname> and

TPO - Messages
<propertyvalue> keywords are separated by an equal sign. Correct the problem

and resubmit the job.
ERROR (TPO-071): An invalid pin name was found in the property file propertyfile.
The pin name is textstr. The run will stop.
EXPLANATION:
<propertyname>=<propertyvalue>. The specified <pinname> could not be
found in the model.
USER RESPONSE:
Make sure the pin name is spelled correctly. Look for the wrong character case, mistaken
zero for upper-case letter O, mistaken numeral 1 for upper-case letter I, and correct
specification of underscores, periods, and slashes in the pin name. Make sure a net
name or block name was not specified. The names of most internal pins are very similar
to block names. Correct the problem and resubmit the job.
ERROR (TPO-072): An invalid property name was found in the property file
propertyfile. The property name is textstr The run will stop.
EXPLANATION:
<propertyname>=<propertyvalue> The specified <propertyname> is not valid
in this context. Property overrides are supported only for the following properties related
to LBIST testmode processing (indicated with the keyword lbist=yes):
TB_LBIST_PRPG
TB_LBIST_MISR
The property specified by the cutpointpropertyname keyword. The property
specified by the latchinitpropertyname keyword. The property name identified in
the message text does not match any of these.
USER RESPONSE:
Make sure the property name is spelled correctly. The character case must match
exactly. If it is not one of the four property names specified in the above explanation,
remove it. Otherwise, correct the spelling. Then resubmit the job.
ERROR (TPO-073): Property textstr was specified twice on the same pin, 'pin
pinname' in the property file propertyfile. The run will stop.
EXPLANATION:

TPO - Messages
The same property should not be specified multiple times on the same pin. Either the
specifications are redundant, or they conflict, and when they conflict, the software does
not know which specification is correct.
USER RESPONSE:
Remove one of the property override statements to remove the conflict or the
redundancy, and resubmit the job.
ERROR (TPO-074): Invalid textstr1 property found on pin pinname in property file
filename. The property value is textstr2. The run will stop.
EXPLANATION:
The value of this property must be 1 or 0.
USER RESPONSE:
The property value is printed in the message text. Verify that this is the same as what
was specified on the identified pin in the property file. Correct the syntax by setting the
property value to either 1 or 0. Then rerun this job.
ERROR (TPO-075): A textstr property was specified on pin pinname in property file
filename but no single latch could be identified as driving this pin. The run will stop.
EXPLANATION:
This property is intended to identify a latch which must be initialized to the value specified
by the property (1 or 0). A backtrace from the pin identified in the message (containing
the property) does not terminate at a unique latch.
USER RESPONSE:
Display the named pin in the Encounter Test Graphical User Interface, and using the
tools menu, set the state to the TI state. Then backtrace along all "X" paths to see why
the latch could not be identified. The outcome will be either
a. It was a misplaced property. In this case, remove the property.
b. Or, the TI state is blocking the path between the latch output and the pin where the
property was specified. In this case, verify that the TI state is correct. If the TI state
is wrong, modify the TI assignments specified on the circuit pins. If the TI state is
correct, move the property to another pin. After making the correction, rerun this job.
ERROR (TPO-076): The textstr1 property was specified on pin pinname in property
file filename but the polynomial is not enclosed in parentheses. The property value is
textstr2 The run will stop.

TPO - Messages
EXPLANATION:
The syntax of this property value is (<integer list>),<seqno> where <integer list> is a
comma-separated list of LFSR tap positions, and <seqno> is an integer that specifies the
relative ordering of the various PRPGs or MISRs as they are to appear in the testmode
definition file which is generated by the build_opcg_testmode command. The ,<seqno>
part is optional. In this case the polynomial, represented by <integer list>, is not enclosed
within parentheses. With the addition of <seqno> to the syntax of this property, the
parentheses have become necessary to avoid confusion, lest the <seqno> value be
taken as part of the polynomial specification.
USER RESPONSE:
Change the property override file so that the polynomial (the integer list> $ described
above) is enclosed within parentheses. Then rerun this job.
ERROR (TPO-077): The textstr1 property was specified on pin pinname in property
file filename but the sequence number textstr2 is not recognized as an integer. The
property value is textstr3 The run will stop.
EXPLANATION:
The syntax of this property value is (<integer list>),<seqno> where <integer list> is a
comma-separated list of LFSR tap positions, and <seqno> is an integer that specifies the
relative ordering of the various PRPGs or MISRs as they are to appear in the testmode
definition file which is generated by the build_opcg_testmode command. The
<seqno> part is optional. In this case <seqno> (textstr2 in the message) is not an
integer.
USER RESPONSE:
Change the property override file so that the sequence number is an integer. Then rerun
this job.
INFO (TPO-078): The only properties found for build_internal_domains_testmode

are textstr1. The nonscanflush sequence will be created, and normal build_testmode
processing will occur.
EXPLANATION:
See the Explanation for Message TPO-021. Message TPO-078 is used in place of TPO-
021 when the netlist property TB_ASYNC_CLOCK is found, and the command being run
is build_internal_domains_testmode. As stated in the message text, the
nonscanflush sequence is created, and all other pre-processing normally performed by
build_internal_domains_testmode is skipped.
USER RESPONSE:

TPO - Messages
If you intended build_internal_domains_testmode to function as a wrapper for

build_testmode when there is no special processing for it to do (other than create the
nonscanflush sequence), then no response is necessary. If you are using some OPCG
registers for PLL or clock controls, then investigate why these model properties were not
found. It could be a case of using the wrong cell library, or the model properties are
improperly named in the netlist.

INFO (TPO-100): List of GO Primary Inputs:
EXPLANATION:
This is the header for a list of primary inputs that were found to have the +/-GO test
function attribute.
USER RESPONSE:
None.
INFO (TPO-101): There are no GO Primary Inputs defined.

EXPLANATION:
The program looked for primary inputs that have the +/-GO test function attribute, but this
test function was not found on any primary input. The GO signal triggers the on-chip
clock genration logic to produce the release and capture clocks for a test. As it plays
such a vital role in the test, the test function +/-GO is supported, and some checking on
its existence and proper use is perfomed by the software. Lacking a pin with this
attribute, you are likely to get error messages, but as long as the GO signals are properly
exercised in the test plan file, you can proceed without this test function attribute being
used.
USER RESPONSE:
If you want to avoid further complaints about not having GO primary inputs defined,
specify the +/-GO attribute on the appropriate pin(s) and rerun the job. Otherwise, you
can safely ignore this message.
INFO (TPO-109): Testmode modename1 will be built because it is different from testmode
testmode2 in that reason.
EXPLANATION:
One run of the prepare_opcg_input command can spawn more than one testmode.
There are several possible reasons for this. One example is the changing of the polarity

TPO - Messages
of a pseudo-primary input (PPI) clock, which effectively changes its behavior from
leading-edge to trailing edge. The polarities of clocks are fixed by the testmode defintion,
so if you want to apply tests using a different clock polarity, you have to define a new
testmode. This message tells you the reason more than one testmode is being created.
USER RESPONSE:
None.
INFO (TPO-110): PFILE Information:

EXPLANATION:
This is the header for the section of the log file that contains the
information found in the PFILE.
USER RESPONSE:
None. If you prefer not to have this message (and the PFILE information) printed,
remove the printpfiles=yes keyword from the command.
INFO (TPO-115): The following entities are combined by PFILE links: PFILE Block name
pfilenamelist blocknamelist
EXPLANATION:
Each of the listed entities is identified by PFILE name and block name. The group
identified by this list is defined by pairwise logical connections between the blocks, and
those connections are identified in the corresponding PFILEs. The first-listed entity is
treated as the master entity.
USER RESPONSE:
None.
INFO (TPO-120): Register Operation Table:

EXPLANATION:
This is the header for the section of the log file that contains information about the OPCG
registers.
USER RESPONSE:
INFO (TPO-130): Operational Mode Definitions:

TPO - Messages
EXPLANATION:
This is the header for the section of the log file that contains the operational mode
definitions found in the PFILE.
USER RESPONSE:
INFO (TPO-140): Sequence Definitions:

EXPLANATION:
This is the header for the section of the log file that contains the test sequence definition
information found in the PFILE.
USER RESPONSE:
INFO (TPO-150): Test Plan:

EXPLANATION:
This is the header for the section of the log file that contains the
test plan information.
USER RESPONSE:
None. If you prefer not to have this message (and the test plan information) printed,
remove the printtestplan=yes keyword from the command.
INFO (TPO-160): Oscillator pins:

EXPLANATION:
This is the header for a list of the oscillator pins found. These are pins which have the +/
-OSC test function attribute.
USER RESPONSE:
None.
WARNING (TPO-161): There are no OSC pins.

EXPLANATION:

TPO - Messages
No primary inputs have the +/-OSC test function attribute. It will not be possible to use
a continuously running oscillator to drive the test.
USER RESPONSE:
Edit the mode definition or assign file to add the +/-OSC test function to your input
oscillator, and resubmit the job. If you are not using an oscillator, then no action is
necessary.
INFO (TPO-170): Test Step stepname uses the following structures and definitions:
EXPLANATION:
This is the header for a section of the log that contains information found in
the test plan file for the named test step.
USER RESPONSE:
None.
INFO (TPO-180): Register Definitions:

EXPLANATION:
This is the header for the section of the log that contains the definitions of registers
defined in the netlist attributes.
USER RESPONSE:
None.
INFO (TPO-190): PLLs:

EXPLANATION:
This is the header for the section of the log that lists PLLs identified and the oscillator
pins that drive them.
USER RESPONSE:
None.
INFO (TPO-191): There are no PLLs.

EXPLANATION:
No PLLs were identified in the circuit.
USER RESPONSE:

TPO - Messages
Make sure you did not expect to find any PLLs. If that is true, then no USER
RESPONSE: is necessary. Otherwise, check for other TPO messages that might help
point out the problem. Make sure your PLLs have the TB_OPCG_INSTANCE and
TB_OPCG_PFILE attributes somewhere in the net list. Make sure the PFILE for the PLL
instances contains the OPCG_ENTITY = PLL statement.

INFO (TPO-201): Output pin pinname is not active on PLL entity blockname in testmode
modename.
EXPLANATION:
The named output pin of the PLL does not feed any active logic, so it does not need to
be processed nor recognized in this testmode.
USER RESPONSE:
Make sure you expected this logic to be inactive in this testmode. If so, then no response
is necessary. If the logic should have been active, the mose likely cause of the problem
is some incorrect +/-TI test function pin assignment. If it is not obvious which pin was
incorrectly assigned the TI attribute, then you may have to use the GUI schematic display
to find out what is blocking the logic from being observed.
INFO (TPO-202): skipttm was specified, but the temporary testmode modename does
not exist. The building of the temporary testmode will NOT be skipped.
EXPLANATION:
The purpose of the debug keyword skipbuildtestmode=yes is to save time when
repeated runs are being made. In this case, some input file(s) corresponding to the
temporary version of the test do not exist, so the temporary testmode will have to be
rebuilt. This message is helpful in explaining that the skipbuildtestmode keyword
was recognized, but could not be honored.
USER RESPONSE:
None.
INFO (TPO-203): Output pin pinname is not active on CLOCKDOMAIN entity

blockname in testmode modename.
EXPLANATION:
The named output pin of the clock generator does not feed any active logic, so it does
not need to be processed nor recognized in this testmode.

TPO - Messages
USER RESPONSE:
Make sure you expected this logic to be inactive in this testmode. If so, then no response
is necessary. If the logic should have been active, the mose likely cause of the problem
is some incorrect +/-TI test function pin assignment. If it is not obvious which pin was
incorrectly assigned the TI attribute, then you may have to use the GUI schematic display
to find out what is blocking the logic from being observed.
INFO (TPO-210): No linehold file is needed for test step stepname.

EXPLANATION:
All the fixed-value linehold (FLH) latches that are being defined for the test mode in which
this test step will be run have the correct default state for this test step. No overriding of
lineholds for these latches will be necessary.
USER RESPONSE:
None. The purpose of this message is to say that the absence of a linehold file for this
test step is not an oversight.
INFO (TPO-211): ppilimit=integer was specified, but the number of PPIs was not
reduced.
EXPLANATION:
The number of pseudo primary inputs (PPIs) in this testmode is less than or equal to the
limit that was specified, so no PPIs needed to be merged to satisfy the limit.
USER RESPONSE:
None.
INFO (TPO-212): ppilimit=integer1 was specified, and the number of PPIs was
reduced to integer2 from integer3.
EXPLANATION:
The number of pseudo primary inputs (PPIs) in this testmode would have been
<integer3>, but they were merged into <integer2> PPIs because a limit of
<integer1> was specified. Note that the limit specified is not strictly adhered to. The
merging process starts when the number reaches the limit, but the limit specification will
be exceeded when subsequent PPIs are processed which can not be merged.
USER RESPONSE:
None.

TPO - Messages
ERROR (TPO-213): Unable to open methodology input file filename. No methodology

output file will be created.
EXPLANATION:
The program was not able to read this file.
USER RESPONSE:
Make sure the file exists. Check for spelling errors. If you do not have a methodology
file to use as input, you must either create one or omit the inmethfile keyword from
the command line. If you choose to remove the inmethfile keyword, and there were
no other serious errors in the run, it is not necessary to rerun the job.
ERROR (TPO-214): Unable to open methodology output file filename. No methodology

output file will be created.
EXPLANATION:
The program was not able to open this file for output.
USER RESPONSE:
Make sure there is space on the volume where the file was to be located. Check for
spelling errors to make sure a valid directory path was specified. Make sure you have
write permission in the directory. You can proceed without a methodology file but if you
must have a methodology file updated by this command, then you will have to fix the
problem and rerun the job.
ERROR (TPO-215): The methodology input file filename contains a #TPO TSSUB
statement for experiment experimentname, but the line pointed to by the TSSUB
statement does not match the text on the TSSUB statement. The two lines are:
textstr1
textstr2
This substitution statement will be ignored.
EXPLANATION:
#TPO TSSUB statements are designed to allow the same edits to be applied repeatedly
to the same methodology file, in case the job fails for some reason either related or not
related to the methodology file updating, and has to be resubmitted. #TPO TSSUB
statements are not intended to be specified by the user, but are created automatically. If
the methodology file output from a previous iteration of this job setp has not been
manually edited, then a program bug is indicated.
USER RESPONSE:

TPO - Messages
Review your previous processing steps and confirm that the methodology input file to this
job has been manually edited subsequent to a previous automatic update, or has not
been manually edited subsequent to a previous automatic update. If manual editing is
involved, then start over with the process using a pristine methodology file. At the outset,
the methodology file should have been backed up prior to submitting it for automatic
updating by the program. If no manual edits have been made since the beginning of the
testmode build processing, then contact Cadence customer support (see Contacting
ERROR (TPO-216): Unable to find PFILE link when processing PFILE statement
LINK INPUT PIN = pinname1, ENTITY_NAME = textstr1, SOURCE PIN = pinname2
in programming file (PFILE) filename,
The connection described in this statement could not be found, or it was\n found but not
confirmed by a matching LINK OUTPUT PIN statement in the PFILE for textstr2.
EXPLANATION:
Distributed PFILES are associated by the LINK statements. If PFILES for A and B are
to be associated to describe a single PLL or clock macro where a logic connection exists
from A to B, then there must be a LINK OUTPUT PIN statement in the PFILE for A and
a matching LINK INPUT PIN statement in the PFILE for B. In this case, either the
connection could not be found, or the statements do not agree. The problem could be a
missing LINK OUTPUT PIN statement, or it could be that a pin name is misspelled in one
of the LINK statements, or one of the LINK statements may refer to the wrong name (for
example, instead of A referring to B, it refers to C).
USER RESPONSE:
Make sure each LINK INPUT PIN statement has a matching LINK OUTPUT PIN
statement in the PFILE for the entity that the LINK INPUT PIN statement refers to. Make
sure that the pin names in these two LINK statements agree. Make sure that both pin
names are spelled correctly.
ERROR (TPO-217): Unable to find PFILE link when processing PFILE statement
LINK OUTPUT PIN = pinname1, ENTITY_NAME = textstr1, SINK PIN = pinname2
in programming file (PFILE) filename,
The connection described in this statement could not be found for block blockname, or it
was found but not confirmed by a matching LINK INPUT PIN statement in the PFILE for
textstr2.
EXPLANATION:
Distributed PFILES are associated by the LINK statements. If PFILES for A and B are
to be associated to describe a single PLL or clock macro where a logic connection exists
from A to B, then there must be a LINK OUTPUT PIN statement in the PFILE for A and
a matching LINK INPUT PIN statement in the PFILE for B. In this case, either the

TPO - Messages
connection could not be found, or the statements do not agree. The problem could be a
missing LINK INPUT PIN statement, or it could be that a pin name is misspelled in one
of the LINK statements, or one of the LINK statements may refer to the wrong name (for
example, instead of B referring to A, it refers to C).
USER RESPONSE:
Make sure each LINK OUTPUT PIN statement has a matching LINK INPUT PIN
statement in the PFILE for the entity that the LINK OUTUT PIN statement refers to. Make
sure that the pin names in these two LINK statements agree. Make sure that both pin
names are spelled correctly.
ERROR (TPO-218): Unable to find pin pinname1 in block blockname1 while processing
the statement
LINK OUTPUT PIN = pinname1, ENTITY_NAME = blockname2, SINK PIN =
pinname2\
in PFILE filename.
This statement is ignored. Edit the PFILE and rerun the job.
EXPLANATION:
The statement
LINK OUTPUT PIN = <pinname1>, ENTITY_NAME = <blockname2>, SINK PIN =
<pinname2>links two cells which comprise a single PLL or clock generation macro,
whereeach of the cells has its own corresponding programming file (PFILE). In the
process of establishing this link, the program is looking for <pinname1> on the block
identified the message, which is described by the PFILE which is also identified in the
message. As stated in the message text, this pin could not be found on the block.
Therefore, the starting point for the link can not be established, and the linkage will be
ignored.
USER RESPONSE:
Make sure that the pin name in the LINK statement exists on the block. Make that the
pin name is spelled correctly in the LINK statement. Edit the PFILE and rerun the job.
ERROR (TPO-219): Unable to find pin pinname1 in block blockname1 while processing
the statement
LINK INPUT PIN = pinname1, ENTITY_NAME = blockname2, SOURCE PIN =
pinname2
in PFILE filename. This statement is ignored. Edit the PFILE and rerun the job.
EXPLANATION:
The statement

TPO - Messages
LINK INPUT PIN = <pinname1>, ENTITY_NAME = <blockname2>, SOURCE PIN

= <pinname2> links two cells which comprise a single PLL or clock generation macro,
where each of the cells has its own corresponding programming file (PFILE). In the
process of establishing this link, the program is looking for <pinname1> on the block
identified the message, which is described by the PFILE which is also identified in the
message. As stated in the message text, this pin could not be found on the block.
Therefore, the starting point for the link cannot be established, and the linkage will be
ignored.
USER RESPONSE:
Make sure that the pin name in the LINK statement exists on the block. Make that the
pin name is spelled correctly in the LINK statement. Edit the PFILE and rerun the job.
WARNING (TPO-220): Invalid PFILE linkage. textstr1 PFILE filename1 is linked with
textstr2 PFILE filename2.
One and only one of the PFILES in a linked group must be a type other than REGISTER.
PFILE filename2 will be treated as REGISTER.
EXPLANATION:
The two named programming files (PFILEs) are linked by their respective LINK INPUT
PIN and LINK OUTPUT PIN statements. However, the two PFILEs are describing
different kinds of OPCG macros as identified in their respective OPCG_ENTITY
statements. All except one of the PFILEs in a linked group must be registers
(OPCG_ENTITY = REGISTER). The kind of macro that is described by the linked group
is defined by the one and only one PFILE in the group that is not a register.
USER RESPONSE:
Decide which PFILE is intended to define the group, and make sure it has the correct
OPCG_ENTITY specified. Specify OPCG_ENTITY = REGISTER in all the other PFILEs
in this group. Then rerun the job.
ERROR (TPO-221): Invalid PFILE linkage. All the following PFILEs are linked, and none is
a type other than REGISTER. One, and only one, of the PFILEs in a linked group must be
type PLL, CLOCKDOMAIN, or ROOTDOMAIN. The linked PFILEs are: list
EXPLANATION:
The named programming files (PFILEs) are linked by their respective LINK INPUT PIN
and LINK OUTPUT PIN statements. None of the PFILEs entifies the kind of OPCG
macro that the group represents. All except one of the PFILEs in a linked group must be
registers (OPCG_ENTITY = REGISTER). The kind of macro that is described by the
linked group is defined by the one and only one PFILE in the group that is not a register.
USER RESPONSE:

TPO - Messages
Decide which PFILE is intended to define the group, and make sure it has the correct
OPCG_ENTITY specified. Specify OPCG_ENTITY = REGISTER in all the other PFILEs
in this group. Then rerun the job.
WARNING (TPO-222): Programming file (PFILE) filename contains a SUBJUGATE

LEVEL integer statement, but INSTANCE blockname which uses this PFILE is not that
deep in the structure hierarchy. Subjugation is ignored for this instance.
EXPLANATION:
One feature of the PFILE is the ability to package a single OPCG macro in two or more
separate cells, each described by its own PFILE. The pieces are combined in one of two
ways: via LINK statements or via the SUBJUGATE statement. In this case, the
SUBJUGATE statement was used, and it specifies that all OPCG entities (each described
by its own PFILE) which are contained within the same cell n levels up in the structure
hierarchy from the cell which this PFILE describes are to be combined into one OPCG
entity, for example, a CLOCKDOMAIN. The number n is specified as SUBJUGATE LEVEL
n. However, the instance named in this message is not n levels deep in the structure, so
the containing entity is undefined. One recourse would be to consider the entire
structure (the "top cut") as the containing entity, but this would encompass all other
OPCG entities in the device, and this is not likely the intention of the PFILE coder.
USER RESPONSE:
Determine if there is an error in the PFILE. If so, edit the PFILE by removing the
SUBJUGATE statement or entering the correct level number, and rerun the job. If the
PFILE is correct, then something must be missing from the logic design. In this case,
repair the netlist and re-import it.

WARNING (TPO-302): Reset conditions for two or more PLLs conflict at latch blockname.
EXPLANATION:
The named latch is a fixed-value latch which feeds two or more PLLs, and it needs to be
set to one state for one of the PLLs, and to the opposite state for another PLL. The
conflict will be ignored, but one of the PLLs may not work.
USER RESPONSE:
Trace forward from the named latch to see which PLLs it feeds, and determine what state
it must be in for those PLLs. If there is no conflict, then you can ignore this message.
Otherwise, you will have to either change the design or change the settings on some TI

TPO - Messages
primary inputs to select another control path for one or more of the PLLs, and then rerun
the job.
WARNING (TPO-304): More than 60 unique PLL reset signals found. Some PLLs may not
be reset properly.
EXPLANATION:
The program has backtraced from PLL reset inputs to identify primary inputs which can
be used to reset the PLLs. There have been more than 60 primary inputs found that feed
PLL reset pins, and this exceeds a limitation of the program. For its analysis, the program
uses bit strings where each position of a string represents a different primary input, and
in the format used by the program, 60 bits is the maximum. An attempt will be made to
derive the PLL reset sequence, but some possible inputs will be ignored, so the program
may fail to find the correct PLL reset sequence.
USER RESPONSE:
If there are no subsequent messages that indicate a failure to reset the PLLs, this
message can be ignored. Otherwise, you may have to derive the PLL reset sequence
and edit it into the mode initialization sequence definition.
WARNING (TPO-305): Conflicting reset states at node pinname for PLLs blockname1
and blockname2 Resetting of PLL blockname1 will be skipped.
EXPLANATION:
The same node which is identified by pin name in the message drives the reset inputs to
two PLLs, identified as blockname1 and blockname2, but the two PLLs have conflicting
reset polarities with respect to the identified pin. There is no way to simultaneously reset
both these PLLs. The program will not consider the first named PLL (blockname1) when
generating the PLL reset sequence.
USER RESPONSE:
Change the design so that both PLLs can be reset, or define two different testmodes so
as to use the PLLs one at a time for test.
ERROR (TPO-306): Latch blockname drives a PLL reset input, but it is not scan
controllable in the parent testmode. Expect the PLL reset sequence derivation to fail.
EXPLANATION:
The named latch needs to be initialized to a value so that the PLLs can be reset, but the
program has no way to initialize the latch because the latch can not be scanned in the
mode initialization sequence. Scan operations in the mode initialization sequence must

TPO - Messages
take place in a so-called parent test mode, but the named latch is not scannable in the
parent testmode.
USER RESPONSE:
There are several possible solutions, but they all require some work. Perform any one of
the following:
Change the design or the definition of the parent testmode so that the named latch
is scannable.
Define a different testmode in which the named latch is scannable, and use this new
testmode as the parent.
Change the design to simplify the logic which drives the PLL reset inputs.
Derive a PLL reset sequence yourself and edit it into the mode initialization
WARNING (TPO-307): Could not figure out how to reset PLL blockname1 and PLL
blockname2.
EXPLANATION:
The logic feeding the reset input of the named PLL is to complex for the program to derive
a reset sequence for the PLL. If more than one PLL is listed, it means the same signal
is driving all of their reset inputs.
USER RESPONSE:
Make sure the logic feeding the reset input of the named PLL is correct. If there is no way
to simplify it, you will have to derive the reset sequence yourself and edit it into the mode
initailization sequence definition.
WARNING (TPO-308): No primary inputs were identified by which the PLLs can be reset.
EXPLANATION:
Backtracing from the reset pins of the PLLs failed to identify the primary input(s) which
can toggle the reset pins.
USER RESPONSE:
Make sure the design is correct and that the correct pins were identified as resets on the
PLLs. If everything looks okay, then you will have to derive the PLL reset sequence
yourself and edit it into the mode intialization sequence definition.
ERROR (TPO-309): Got lost backtracing through apparent IO cell at block blockname, flat
model index flatindex.

TPO - Messages
EXPLANATION:
The problem occurred during the backtracing of the PLL reset logic. IO cells can be
difficult to navigate by the program when the primary input is a TI signal. The program
looks for a pin on the block with the name "PAD" or "P". The block named in this message
has a pin with one of these names, but no primary input could be found connected to this
pin. The backtrace will continue through the IO cell, but it may give strange results.
USER RESPONSE:
You may still get good results. To be safe, look for other messages which indicate that
the PLL reset sequence might be suspect.
INFO (TPO-310): PLL reset PIs:

EXPLANATION:
This is the header for a list of primary inputs that are candidates for being toggled to reset
the PLLs.
USER RESPONSE:
If this message appears, it means that a debug option was used. Check the list of pins
to see that the program found all the TI pins that feed reset inputs to the PLLs.
INFO (TPO-311): PLL reset latches:

EXPLANATION:
This is the header for a list of latches that need to be initialized to reset the PLLs.
USER RESPONSE:
If this message appears, it means that a debug option was used. Check the list of latches
to see that the program is resetting the PLLs in the manner intended.
INFO (TPO-312): Pins to be used for resetting the PLLs:

EXPLANATION:
This is the header for a list of primary input pins that will be toggled to reset the PLLs.
USER RESPONSE:
If this message appears, it means that a debug option was used. Check the list of pins
to see that the program is resetting the PLLs in the manner intended.
INFO (TPO-313): The following TI primary inputs can be used to reset the PLLs: pinname.
EXPLANATION:

TPO - Messages
The list of pins are primary inputs that could be toggled to reset the PLLs. This message
will appear for each solution found, but the last solution printed is the only one that will
be used. If it turns out that the last solution printed is unacceptable, then the information
in these messages may be useful for correcting the problem.
USER RESPONSE:
Verify that the solution printed in the last TPO-313 message is acceptable. If it is not, edit
the testmode initialization sequence to correct the problem, possibly by using the solution
printed in one of the other TPO-313 messages.
INFO (TPO-314): The following TI primary inputs will be used to reset the PLLs: pinname
EXPLANATION:
The list of pins are primary inputs that will be toggled to reset the PLLs.
USER RESPONSE:
Verify that the pins listed are acceptable for resetting the PLLs. If not, edit the testmode
initialization sequence or the setup sequence(s) to use the correct pin(s).
INFO (TPO-366): The ET_HIERTEST_CONFIG property was found in the netlist, but
neither keyword coremigrationdir nor coremigrationpath was specified for hierarchical test
processing. The ET_HIERTEST_CONFIG property will be ignored.
EXPLANATION:
The ET_HIERTEST_CONFIG property is placed on latches which must be initialized in
a specific way for hierarchical test to be performed properly, and for most tests to work
properly for a chip designed for hierarchical test, even when hierarchical test is not being
performed. Some of the information needed for properly initializing the
ET_HIERTEST_CONFIG latches (config latches) is passed in the core migration
directory, specified by the coremigrationdir keyword at the core out-of-context level,
and by the coremigrationpath keyword at the chip level. Neither of these keywords
was specified, so it is being assumed that the config latches do not need to be initialized.
USER RESPONSE:
Make sure the config latches do not need to be initialized for the processing that will be
done in this testmode. If they do need to be initialized, then specify either the
coremigrationdir keyword (if a core out-of-context is being processed) or the
coremigrationpath keyword (if a chip is being processed).

TPO - Messages

ERROR (TPO-405): Unrecognized statement in linehold file filename:textstring
Edit the linehold file and rerun the job.
EXPLANATION:
The first keyword appearing on the listed statement is not recognized as a valid linehold
file statement, or there is a missing semicolon at the end of the statement, or the syntax
is invalid.
USER RESPONSE:
Read the Encounter Test documentation for a description of the syntax of the linehold
file, Check for a spelling error in the statement. Make sure the statement ends with a
semicolon. Make sure there are the correct number of fields. Edit the linehold file and
rerun the job.
ERROR (TPO-406): Invalid content found in the filename field in the following statement
of linehold file fieldname:textstring Edit the linehold file and rerun the job.
EXPLANATION:
The named field in this linehold file statement has an invalid value.
USER RESPONSE:
Read the Encounter Test documentation for a description of the syntax of the linehold file
statement listed in the message. From the syntax description, find the acceptable values
of the named field. Then edit the linehold file and rerun the job.
ERROR (TPO-407): Unable to resolve textstring1s entityname in the following

statement of linehold file filename:textstring2 Edit the linehold file and rerun the job.
EXPLANATION:
The pin, net, or block identified in the message could not be identified, or, it could be
identified but is not capable of being manipulated by linehold file statements.
USER RESPONSE:
Make sure the name is spelled correctly, and if the keyword PIN, NET, or BLOCK was
specified, make sure the keyword is correct for this name. If PIN, NET, or BLOCK was not
specified, then the object must be a pin. Edit the linehold file to correct the keyword or
the object name and rerun the job.

TPO - Messages
ERROR (TPO-408): Unable to resolve PPI entityname in the following statement of

linehold file filename:textstring Edit the linehold file and rerun the job.
EXPLANATION:
The PPI identified in the message is not defined.
USER RESPONSE:
Make sure the PPI name is spelled correctly, and it is defined, either in the input mode
definition file, in the input assign file, or in the netlist. The linehold file input to
build_opcg_testmode can not refer to a PPI that is to be defined as the result of
build_opcg_testmode processing. Edit the linehold file to remove the statement or
correct the PPI name and rerun the job.
ERROR (TPO-409): Invalid syntax in the following statement in linehold file

filename:textstring Edit the linehold file and rerun the job.
EXPLANATION:
The statement could not be parsed. Either the value field is wrong, there are too many
fields, or the ending semicolon is missing.
USER RESPONSE:
Read the Encounter Test documentation for a description of the syntax of the linehold
file, Check for a spelling error in the statement. Make sure the statement ends with a
semicolon. Make sure there are the correct number of fields. Edit the linehold file and
rerun the job.
ERROR (TPO-410): The fieldname field was specified multiple times in the following
statement of linehold file filename:textstring Edit the linehold file and rerun the job.
EXPLANATION:
Either the same keyword value was specified twice, or conflicting keywords were
specified for the named field in the indicated linehold file statement. If it is the
propagation field of the TRANSITION statement, then the conflict may be that one
propagation keyword was specified and an entity list was also specified.
USER RESPONSE:
Remove the superfluous or conflicting keyword value from the linehold file and rerun the
job.
ERROR (TPO-411): Missing semicolon at end of the following statement of linehold file
filename:textstring Edit the linehold file and rerun the job.

TPO - Messages
EXPLANATION:
All linehold file statements must end with a semicolon.
USER RESPONSE:
Edit the linehold file to make sure all statements end with a semicolon and rerun the job.
ERROR (TPO-412): Invalid keyword (filename) found in the following statement of

linehold file keyword:textstring Edit the linehold file and rerun the job.
EXPLANATION:
The indicated keyword is not recognized in this linehold file statement.
USER RESPONSE:
Determine what keyword was intended. Edit the linehold file and rerun the job.
ERROR (TPO-413): Missing entity or missing value field before first comma in the following
statement of linehold file filename:textstring Edit the linehold file and rerun the job.
EXPLANATION:
Presence of comma in the TRANSITION statement means the PROPAGATION field
consists of a list of entities (pin, net, and/or block names). The symbol preceding the first
comma was taken to be the value field. Either the value field is missing and the first entity
was mistakenly interpreted as the value, or the first entity in the list is missing.
USER RESPONSE:
Determine the exact nature of the error, whether the value field is missing, the first entity
is missing, or the comma is misplaced. Edit the linehold file and rerun the job.
ERROR (TPO-414): Invalid name, 'PPI ppiname1', found in the following statement of
linehold file ppiname2:ppiname2 This PPI was combined with 'PPI textstring'
because they behave identically. Use 'PPI filename' instead. Edit the linehold file and rerun
the job.
EXPLANATION:
The pseudo primary input (PPI) name specified in the linehold file is defined in the
programming file (PFILE), but this PPI was combined with the second PPI identified in
the message, and the combined PPI is known by the second name. The first name, the
one specified in the linehold file, will be undefined in the testmode.
USER RESPONSE:

TPO - Messages
Edit the linehold file. Replace all instances of the invalid PPI name with the correct PPI
name as identified in the message. Then rerun the job.
ERROR (TPO-415): Unable to parse the field >textstring1<, found in the following
statement of linehold file filename:textstring2 Edit the linehold file and rerun the
job.
EXPLANATION:
The program thought it was parsing the propagation field of a TRANSITION statement in
the linehold file, consisting of a comma-separated list of observe points. Each observe
point is a hierarchical name of a pin, net, or block, optionally preceded by the keyword
PIN, NET, or BLOCK, respectively. In the absence of a keyword, the name is assumed
to be a pin. The failure to parse this item in the list is probably due to a null item (two
successive commas). The item is printed in the message between the >< characters.
USER RESPONSE:
Examine the list item as printed in the message. Make sure it is the same as it appears
in the linehold file input. Identify the syntax problem, then edit the linehold file and rerun
the job.
ERROR (TPO-450): Invalid textstr1 property found on pin pinname. The property
value is textstr2 The run will stop.
EXPLANATION:
This property value must have the form <ppiname>=<testfunctionvalue> In this
case, either there is a missing equal sign, or <ppiname> is missing, or
<testfunctionvalue> is missing.
USER RESPONSE:
was specified on the identified pin in the net list. Correct the syntax by making sure there
is one equal sign separating two non-blank tokens. The token on the left is the PPI name,
and the token on the right is the test function value. Then re-import the model, and rerun
this job.
ERROR (TPO-451): Invalid textstring1 property found on pin pinname. The property
value is textstring2. The run will stop.
EXPLANATION:
The property value must be 1 or 0.
USER RESPONSE:

TPO - Messages
was specified on the identified pin in the net list. Correct the syntax by setting the
property value to either 1 or 0. Then re-import the model, and rerun this job.
ERROR (TPO-452): A textstr property was specified on pin pinname, but no single
latch could be identified as driving this pin. The run will stop.
EXPLANATION:
This property is intended to identify a latch which must be initialized to the value specified
by the property (1 or 0). A backtrace from the pin identified in the message (containing
the property) does not terminate at a unique latch.
USER RESPONSE:
Display the named pin in the Encounter Test Graphical User Interface, and using the
tools menu, set the state to the TI state. Then backtrace along all "X" paths to see why
the latch could not be identified. The outcome will be either
1. It was a misplaced property. In this case, remove the property.
2. The TI state is blocking the path between the latch output and the pin where the property
was specified. In this case, verify that the TI state is correct. If the TI state is wrong,
modify the TI assignments specified on the circuit pins. If the TI state is correct, move the
property to another pin. After making the correction, re-import the circuit and rerun this
job.
INFO (TPO-453): A textstr property was specified on pin pinname, but it was
overridden by the property file filename. The value from the property file will be used, and
the property value on this pin in the netlist will be ignored.
EXPLANATION:
The purpose of the property file is to supplement the netlist properties. In this case, the
property file and the netlist specify the same property on the same pin. No check is being
made to see if the property values are in conflict, but the value from the property file is
being used, and the value from the netlist is being ignored.
USER RESPONSE:
It is being assumed that the property override via the property file is intentional. If this is
not the case, then remove from the property file the statement which specifies this pin
and property name combination, and rerun the job.
ERROR (TPO-454): The textstr1 property was specified on pin pinname, but the
polynomial is not enclosed in parentheses. The property value is textstr2 The run will
stop.

TPO - Messages
EXPLANATION:
The syntax of this property value is (<integer list>),<seqno> where <integer
list> is a comma-separated list of LFSR tap positions, and <seqno> is an integer that
specifies the relative ordering of the various PRPGs or MISRs as they are to appear in
the testmode definition file which is generated by the build_opcg_testmode
command. The ,<seqno> part is optional. In this case the polynomial, represented by
<integer list>, is not enclosed within parentheses. With the addition of <seqno>
to the syntax of this property, the parentheses have become necessary to avoid
confusion, lest the <seqno> value be taken as part of the polynomial specification.
USER RESPONSE:
Change the netlist source so that the polynomial (the <integer list> described
above) is enclosed within parentheses. Re-import the circuit and rerun this job.
ERROR (TPO-455): The textstr1 property was specified on pin pinname, but the
sequence number textstr2 is not recognized as an integer.
The property value is textstr3. The run will stop.
EXPLANATION:
The syntax of this property value is (<integer list>),<seqno> where <integer
list> is a comma-separated list of LFSR tap positions, and <seqno> is an integer that
specifies the relative ordering of the various PRPGs or MISRs as they are to appear in
the testmode definition file which is generated by the build_opcg_testmode
command. The ,<seqno> part is optional. In this case <seqno> (textstr2 in the
message) is not an integer.
USER RESPONSE:
Change the netlist source so that the sequence number is an integer. Re-import the
circuit and rerun this job.

ERROR (TPO-502): Register regname consists of fixed-value latches, but there is no
parent testmode defined. The fixed-value latches must be initialized by a scan operation in
the parent testmode. Define a parent testmode, or use OPCG scan to initialize the register.
EXPLANATION:
The means of automatically loading fixed-value latches is by way of a scan operation
using a different testmode, called the parent testmode. Fixed- value latches, by
definition, are not scannable in the target testmode. Because no parent testmode is

TPO - Messages
defined, there is no way to automatically derive a sequence to initialize the named

register, which consistes of fixed-value latches.
USER RESPONSE:
Determine how the identified register is supposed to be initialized. It may be by way of
a parent testmode scan operation (if the latch is fixed-value), by way of a scan operation
in the target testmode, or by way of a side-scan (OPCG scan) operation in the target
testmode. If the latch is fixed-value, you must define a parent testmode. Otherwise,
remove the conditions that are causing the latch to be fixed-value, and make the latch
loadable by a scan operation (normal scan or OPCG scan) in the target testmode.
ERROR (TPO-503): The cutpoint net netname, represented by a linehold PPI ppiname
is not connected to a latch in the TC state. It is not valid to linehold the PPI without some
means of controlling the net by a programmable register. Fix the design or the PFILE and
rerun the job.
EXPLANATION:
The automatic construction of test sequences involving lineheld pseudo primary inputs
(PPIs) depends upon the PPI being controlled directly by a programmable latch, i.e., a
latch that is identified as an OPCG register. The latch to control the identified net, which
is associated with a lineheld PPI, could not be found. As a result, not only is there no
way to ensure the validity of the tests if the PPI were to be lineheld, but there is no way
to automatically determine the correct state to linehold the PPI to for this experiment. No
linehold information will be generated for this PPI, and the PPI will be assumed to hold
its default linehold state throughout test generation. There is no assurance that the tests
generated will work in the hardware.
USER RESPONSE:
The problem may be an incorrect logic design, or a coding error in the programming file
(PFILE). Ensure that the net is supposed to have a cutpoint and that the correct pin was
specified in the PFILE. Edit the PFILE or repair the logic and rerun the job.
ERROR (TPO-504): The cutpoint net netname, represented by a linehold PPI ppiname
is fed by latch blockname, but this latch is not a defined OPCG register bit. It is not valid to
linehold the PPI without some means of controlling the net by a programmable register. Fix
the design or the PFILE and rerun the job.
EXPLANATION:
The automatic construction of test sequences involving lineheld pseudo primary inputs
(PPIs) depends upon the PPI being controlled directly by a programmable latch, i.e., a
latch that is identified as an OPCG register. A latch to control the identified net, which is
associated with a lineheld PPI, was found, but this latch is not a recognized OPCG
register bit. As a result, not only is there no way to ensure the validity of the tests if the

TPO - Messages
PPI were to be lineheld, but there is no way to automatically determine the correct state
to linehold the PPI to for this experiment. No linehold information will be generated for
this PPI, and the PPI will be assumed to hold its default linehold state throughout test
generation. There is no assurance that the tests generated will work in the hardware.
USER RESPONSE:
There may be an error in the register definitions, or a coding error in the programming
file (PFILE). Determine whether the identified latch is intended to be a defined control
register. If it is, then it should be identified by a netlist property, giving its register name
and its bit position in the register. If it is not, then there may be an error in the logic or in
the PFILE. In this case, ensure that the net is supposed to have a cutpoint and that the
correct pin was specified in the PFILE. Edit the PFILE or repair the logic and rerun the
job.
WARNING (TPO-505): The cutpoint net netname, represented by a testfunction PPI

ppiname is fed by latch blockname in register regname, but this latch is being
programmed in test step stepname to the opposite value. Fix PFILE pfilename and
rerun the job.
EXPLANATION:
The test step being processed identifies an operation for the named register, or allows
the default operation to be used for this register. The operation can be looked up in the
testplan (if it is not the default operation) or in the programming file (PFILE) (if the
operation is not specified in the testplan). This operation defines the register state and
points to the PFILE section that defines the cutpoint, the PPI, and the PPI test function.
The test function of the identified PPI calls for the associated cutpoint net to be held at a
constant state, but the cutpoint net is fed by the indicated register bit which is to be
loaded to the value which will drive the cutpoint net to the wrong state.
USER RESPONSE:
Note that the PFILE may specify inversion between the PPI and the associated cutpoint
net, and there may be inversion between the indicated register bit (latch) and the cutpoint
net. Taking these inversions into account, the message states that there is a conflict.
Assuming the logic design is correct, the conflict is in the PFILE between the register bit
state in the operation definition and the test function value pointed to by the operation
definition. Use the register name and the test step name identified in the message to find
the testplan statement that is programming the register. If there is no such testplan
statement, then it would be the default operation identified in the PFILE by the name
"default" or as the first defined operation for this register. Make the register bit value for
this operation consistent with the value on the test function for the PPI. After editing the
PFILE, rerun the job.

TPO - Messages

ppiname is not connected to a latch in the TC state. The PPI is forced to value by the force
keyword in the PFILE. Without direct control by a latch there is no assurance that the force
is valid.
EXPLANATION:
One example of where the force keyword is used in the programming file (PFILE) is
where the cutpoint net is controlled by a sidescan register. Since sidescan registers are
not loaded in the testmode initialization sequence, there is no way for the simulation that
occurs during the building of the testmode to verify that the PPI is at its stability state at
the end of the testmode initialization process. The checking that produced this message
has the purpose of verifying correct operation by a structural analysis in lieu of
simulation. The check failed because the cutpoint net is not directly controlled by a
sidescan latch/flop.
USER RESPONSE:
Verify that the cutpoint is properly placed, and the correct test function and stability state
are specified for the PPI. If the test vectors fail in simulation or at the tester, this may be
a fruitful area for investigation.

ppiname is fed by latch blockname, but this latch is not a defined OPCG register bit. The
PPI is forced to value by the force keyword in the PFILE. With the function of this latch being
unknown, there is no assurance that the force is valid.
EXPLANATION:
One example of where the force keyword is used in the programming file (PFILE) is
where the cutpoint net is controlled by a sidescan register. Since sidescan registers are
not loaded in the testmode initialization sequence, there is no way for the simulation that
occurs during the building of the testmode to verify that the PPI is at its stability state at
the end of the testmode initialization process. The checking that produced this message
has the purpose of verifying correct operation by a structural analysis in lieu of
simulation. The check failed because the latch/flop that controls this cutpoint net is not
directly controllable as an OPCG register.
USER RESPONSE:
Verify that the cutpoint is properly placed, and the correct test function and stability state
are specified for the PPI. If the test vectors fail in simulation or at the tester, this may be
a fruitful area for investigation.

TPO - Messages

WARNING (TPO-603): Missing register name for the TB_OPCG_REGNAME property value on
entityname. The value specified was textstring. This property will be ignored.
EXPLANATION:
A TB_OPCG_REGNAME property was found on the named block, pin, or net, but there was
no period (".") delimiter separating the register name and the bit position. It appears that
the register name is missing.
USER RESPONSE:
Correct the syntax of the TB_OPCG_REGNAME property value. Reimport the circuit and
rerun the job.
WARNING (TPO-604): Missing bit number for the TB_OPCG_REGNAME property value on
entityname. The value specified was textstring.This property will be ignored.
EXPLANATION:
A TB_OPCG_REGNAME property was found on the named block, pin, or net,
but there was no period (".") delimiter separating the register name and the bit position.
It appears that the bit position field is missing, but it could be only a missing delimiter.
USER RESPONSE:
rerun the job.
WARNING (TPO-605): Invalid bit number for the TB_OPCG_REGNAME property value on
entityname. The value specified was textstring. This property will be ignored.
EXPLANATION:
A TB_OPCG_REGNAME property was found on the named block, pin, or net, but the bit
position field following the period (".") contains one or more non-decimal characters. The
bit position must be an integer.
USER RESPONSE:
rerun the job.
WARNING (TPO-606): Mismatched quotation marks on TB_OPCG_REGNAME property value

on entityname. The value specified was textstring. This property will be ignored.

TPO - Messages
EXPLANATION:
A TB_OPCG_REGNAME property was found on the named block, pin, or net, but the value
contains a mismatched double quote character ("). It is not clear whether the value was
intended to be enclosed in quotation marks, or if some other character was intended in
place of the quote character.
USER RESPONSE:
rerun the job.
WARNING (TPO-608): Unable to find pin with a name of name, constructed from the
TB_OPCG_REGNAME property value textstring on entityname. The property will be
ignored.
EXPLANATION:
The identified pin can not be found. This pin name is composed of the pin name from
the TB_OPCG_REGNAME property appended to the name of the block to which this
property was attached.
USER RESPONSE:
Make sure the pin name is spelled properly on the TB_OPCG_REGNAME property. Find
the correct pin name, correct the property value, then re-import the circuit and rerun the
job.
WARNING (TPO-609): Unable to find latch feeding name identified by the

TB_OPCG_REGNAME property value textstring on entityname. The property will be
ignored.
EXPLANATION:
This TB_OPCG_REGNAME property points to a recognized signal in the circuit, but in
searching for the latch that controls this signal, no latch was found.
USER RESPONSE:
Determine which latch this TB_OPCG_REGNAME property is supposed to refer to, and
make sure that the signal named in the property is one that is controlled exclusively by
this latch. Correct the property value, re-import the circuit, and rerun the job.
WARNING (TPO-610): Too many paths feeding name to find a unique controlling latch.
name was identified by the TB_OPCG_REGNAME property value textstring on
entityname. The property will be ignored.
EXPLANATION:

TPO - Messages
This TB_OPCG_REGNAME property points to a recognized signal in the circuit, but in

searching for the latch that controls this signal, no unique control point was found.
USER RESPONSE:
Make sure the correct signal was specified. If this is not the correct signal, change it to
the correct one. If it is the correct signal, then it will still be necessary to specify a different
signal that is closer to the register latch, so that the latch can be readily identified. Then
correct the property value, re-import the circuit, and rerun the job.
WARNING (TPO-611): The same register points to two different PFILE names.
entityname1points to PFILE pfilename1 and entityname2 points to PFILE
pfilename2. Both contain bits in register regname. PFILE pfilename1 will be used for
this register.
EXPLANATION:
Two different "entities," say, blocks, refer to two different PFILEs and they define bits in
the same register. The bits are in the same register by virtue of the fact that they have
the same name and these entities are within the same block identified with a
TB_OPCG_INSTANCE property. This is a problem because one register can not be
described by two different PFILEs. According to the message, the first PFILE mentioned
is the one that will be used for this register.
USER RESPONSE:
The most likely cause of the problem is an extra TB_OPCG_PFILE property that should
be removed. Another possibility is that the wrong register name was used in one of the
entities. See if the two entities do contain bits in the same register. If they do, then they
must point to the same PFILE. If one of the entities contains registers that are defined
by different PFILEs, then you may be able to resolve the problem by moving the
TB_OPCG_REGNAME and TB_OPCG_PFILE properties to a lower level of the structure
hierarchy. After diagnosing the problem, correct the properties in the netlist, re-import
the circuit, and rerun the job.
WARNING (TPO-612): Processing REGNAME property on entityname, there was no

corresponding TB_OPCG_INSTANCE property to identify which register this bit is part of, nor
which PLL or clock domain it controls. The property will be ignored. Make sure the model is
not cloaked. entityname
EXPLANATION:
The TB_OPCG_REGNAME property must be associated with a TB_OPCG_PFILE property,
and in many cases, it must be associated with other TB_OPCG_REGNAME properties
which define other bits in the same register. These associations are made by the
specification of a containing block at the same or a higher level of the structure hierarchy.
The containing block is identified by means of the TB_OPCG_INSTANCE property. Since

TPO - Messages
no TB_OPCG_INSTANCE property was found for this TB_OPCG_REGNAME property, the

TB_OPCG_REGNAME property is not meaningful.
USER RESPONSE:
Make sure the model is not cloaked, as cloaking is a frequent cause of this situation. If
cloaking is not the problem, then identify a block at some level of the hierarchy that
contains all the pieces of the PLL or clock generation circuit that you are defining, and
place the TB_OPCG_INSTANCE property on this block. Then re-import the circuit and
rerun the job.
WARNING (TPO-613): There are no valid register bits. The run is stopping.
EXPLANATION:
Either there were no register bits defined (no TB_OPCG_REGNAME properties), or all the
register bit definitions were found to be invalid for one reason or another. Since there are
no register bits defined to control the PLLs and the clock generation logic for this circuit,
it is unlikely that subsequent processing will be successful.
USER RESPONSE:
Look for other messages indicating why the register definitions were not valid. If you
have no register definitions, make sure that your PLL and clock generation controls all
come from primary inputs. If all the controls are from primary inputs, then you should be
able to ignore this message and proceed.
WARNING (TPO-614): Bits bitposition1 through bitposition2 are missing from

register regname. In subsequent log messages, bit positions bitposition3 and higher
will be off by number to fill the gap. Output files will not be generated.
EXPLANATION:
The bit positions in OPCG registers are identified by consecutive integers, beginning with
0. A gap was found in the sequence for this register, so the bits will be renumbered so
that there are no gaps.
USER RESPONSE:
If this was only a misunderstanding about how to number the bits, then perhaps this
message can be safely ignored. Most likely, it indicates an error either in the numbering
of the bits, or a typographical error in the register name. In the latter case, you may get
another TPO-614 message complaining about bit numbers being wrong for the register
with the phony name.
ERROR (TPO-615): Register regname has a mixture of fixed-value latches and non-fixed-
value latches. One of its fixed-value latches is blockname1 One of its non-fixed-value

TPO - Messages
latches is blockname2. The register will be defined as though all its latches are fixed-value,
but this can not be expected to work.
EXPLANATION:
OPCG control registers have to be initialized. One means of initialization is with a "parent
mode" scan operation applied in the mode initialization sequence. This is the case for
fixed-value latches. OPCG control registers comprised of non-fixed-value latches are
usually initialized by means of a side scan, or they may be scannable in the target
testmode. Encounter Test accommodates all three ways of initializing OPCG registers,
but not more than one initialization means for different bits in the same register.
USER RESPONSE:
Make sure there is not some mistake in the definition of the circuit. Maybe the OPCG
register should be broken up and defined as two smaller registers. Or maybe the
behaviors of some of the latches are wrong--some fixed-value latches should not be, or
vice-versa.
ERROR (TPO-616): Bit bitposition of register regname was defined twice. It was
defined on block blockname1 via the textstring1 property on textstring2, and it
was also defined on block blockname2 via the textstring3 property on
textstring4. The second-mentioned property will be ignored. Fix the incorrect netlist
property and re-import the netlist.
EXPLANATION:
The TB_OPCG_REGNAME property was found in two different places in the netlist, with
the same register name and bit position, and both places also pointed to the same
programming file (PFILE) via the TB_OPCG_PFILE property. Three possible causes of
the error are: one of the TB_OPCG_REGNAME properties contains wrong information
(either the wrong bit position or wrong register name); one of the TB_OPCG_PFILE
properties points to the wrong PFILE; or these properties should not have been specified
at one of these places.
USER RESPONSE:
Determine which of the properties is wrong, and edit the netlist accordingly. Then re-
import the netlist.
WARNING (TPO-643): Missing register name for the TB_INTERNAL_DOMAINS_REGNAME

property value on entityname. The value specified was textstring. This property will
be ignored.
EXPLANATION:

TPO - Messages
A TB_INTERNAL_DOMAINS_REGNAME property was found on the named block, pin, or

net, but there was no period (".") delimiter separating the register name and the bit
position. It appears that the register name is missing.
USER RESPONSE:
Correct the syntax of the TB_INTERNAL_DOMAINS_REGNAME property value. Reimport
the circuit and rerun the job.
WARNING (TPO-644): Missing bit number for the TB_INTERNAL_DOMAINS_REGNAME

be ignored.
EXPLANATION:
net, but there was no period (".") delimiter separating the register name and the bit
position. It appears that the bit position field is missing, but it could be only a missing
delimiter.
USER RESPONSE:
Correct the syntax of the TB_INTERNAL_DOMAINS_REGNAME property value. Reimport
WARNING (TPO-645): Invalid bit number for the TB_INTERNAL_DOMAINS_REGNAME

be ignored.
EXPLANATION:
net, but the bit position field following the period (".") contains one or more non-decimal
characters. The bit position must be an integer.
USER RESPONSE:
Correct the syntax of the TB_INTERNAL_DOMAINS_REGNAME property value.
Reimportthe circuit and rerun the job.
WARNING (TPO-646): Mismatched quotation marks on

TB_INTERNAL_DOMAINS_REGNAME property value on entityname. The value specified
was textstring. This property will be ignored.
EXPLANATION:

TPO - Messages

net, but the value contains a mismatched double quote character ("). It is not clear
whether the value was intended to be enclosed in quotation marks, or if some other
character was intended in place of the quote character.
USER RESPONSE:
Correct the syntax of the TB_INTERNAL_DOMAINS_REGNAME property value.
Reimport the circuit and rerun the job.
WARNING (TPO-648): Unable to find pin with a name of name, constructed from the
TB_INTERNAL_DOMAINS_REGNAME property value textstring on entityname. The
property will be ignored.
EXPLANATION:
The identified pin can not be found. This pin name is composed of the pin name from
the TB_INTERNAL_DOMAINS_REGNAME property appended to the name of the block to
which this property was attached.
USER RESPONSE:
Make sure the pin name is spelled properly on the TB_INTERNAL_DOMAINS_REGNAME
property. Find the correct pin name, correct the property value, then re-import the circuit
and rerun the job.
WARNING (TPO-649): Unable to find latch feeding name identified by the

TB_INTERNAL_DOMAINS_REGNAME property value textstring on entityname. The
property will be ignored.
EXPLANATION:
This TB_INTERNAL_DOMAINS_REGNAME property points to a recognized signal in the
circuit, but in searching for the latch that controls this signal, no latch was found.
USER RESPONSE:
Determine which latch this TB_INTERNAL_DOMAINS_REGNAME property is supposed to
refer to, and make sure that the signal named in the property is one that is controlled
exclusively by this latch. Correct the property value, re-import the circuit, and rerun the
job.
WARNING (TPO-650): Too many paths feeding name to find a unique controlling latch.
name was identified by the TB_INTERNAL_DOMAINS_REGNAME property value
textstring on entityname. The property will be ignored.
EXPLANATION:

TPO - Messages
This TB_INTERNAL_DOMAINS_REGNAME property points to a recognized signal in the

circuit, but in searching for the latch that controls this signal, no unique control point was
found.
USER RESPONSE:
Make sure the correct signal was specified. If this is not the correct signal, change it to
the correct one. If it is the correct signal, then it will still be necessary to specify a different
signal that is closer to the register latch, so that the latch can be readily identified. Then
correct the property value, re-import the circuit, and rerun the job.
WARNING (TPO-652): Processing REGNAME property on entityname, there was no

corresponding TB_INTERNAL_DOMAINS_INSTANCE property to identify which register this
bit is part of, nor which PLL or clock domain it controls. The property will be ignored. Make
sure the model is not cloaked.
EXPLANATION:
The TB_INTERNAL_DOMAINS_REGNAME property must be associated with a
TB_INTERNAL_DOMAINS_PFILE property, and in many cases, it must be associated
with other TB_INTERNAL_DOMAINS_REGNAME properties which define other bits in the
same register. These associations are made by the specification of a containing block at
the same or a higher level of the structure hierarchy. The containing block is identified
by means of the TB_INTERNAL_DOMAINS_INSTANCE property. Since no
TB_INTERNAL_DOMAINS_INSTANCE property was found for this
TB_INTERNAL_DOMAINS_REGNAME property, the TB_INTERNAL_DOMAINS_REGNAME
property is not meaningful.
USER RESPONSE:
Make sure the model is not cloaked, as cloaking is a frequent cause of this situation. If
cloaking is not the problem, then identify a block at some level of the hierarchy that
contains all the pieces of the PLL or clock generation circuit that you are defining, and
place the TB_INTERNAL_DOMAINS_INSTANCE property on this block. Then re-import
WARNING (TPO-653): There are no valid register bits. The run is stopping.
EXPLANATION:
Either there were no register bits defined (no TB_INT_DOMAINS_REGNAME properties),
or all the register bit definitions were found to be invalid for one reason or another. Since
there are no register bits defined to control the PLLs and the clock generation logic for
this circuit, it is unlikely that subsequent processing will be successful.
USER RESPONSE:

TPO - Messages
Look for other messages indicating why the register definitions were not valid. If you
have no register definitions, make sure that your PLL and clock generation controls all
come from primary inputs. If all the controls are from primary inputs, then you should be
able to ignore this message and proceed.
ERROR (TPO-656): Bit bitposition of register regname was defined twice. It was
defined on block blockname1 via the textstring1 property on textstring2, and it
was also defined on block blockname2 via the textstring3 property on
textstring4. The second-mentioned property will be ignored. Fix the incorrect netlist
property and re-import the netlist.
EXPLANATION:
The TB_INT_DOMAINS_REGNAME property was found in two different places in the
netlist, with the same register name and bit position, and both places also pointed to the
same programming file (PFILE) via the TB_INT_DOMAINS_PFILE property. Three
possible causes of the error are: one of the TB_INT_DOMAINS_REGNAME properties
contains wrong information (either the wrong bit position or wrong register name); one of
the TB_INT_DOMAINS_PFILE properties points to the wrong PFILE; or these properties
should not have been specified at one of these places.
USER RESPONSE:
Determine which of the properties is wrong, and edit the netlist accordingly. Then re-
import the netlist.

ERROR (TPO-700): Unable to open programming file pfilename. This run will stop.
EXPLANATION:
The program was not able to read this file. The most likely cause is the directory path
specified via the pfiledir keyword is not complete.
USER RESPONSE:
Make sure the file exists in one of the directories specified in the pfiledir keyword. If
it does, make sure the file name is spelled correctly, being careful to check for proper use
of upper case and lower case characters. Also check for the correct spelling of the
directory names in the pfiledir keyword. If the file is not there, find out where it is and
add this directory to the pfiledir specification.

TPO - Messages
WARNING (TPO-701): Unrecognized statement found in programming file pfilename.

The statement is
textstr.This statement was ignored.
EXPLANATION:
The program is not able to parse the identified statement, because the statement does
not begin with any recognized keyword.
USER RESPONSE:
If the statement is purely a comment, the message can be ignored. In this case, the
message can be avoided in the future by inserting comment characters at the beginning
of the statement ("#","//"). If it is not a comment statement, correct the syntax and rerun
the job. It may be a matter of a missing section header, such as
START_PROGRAM_DEFINITIONS{.
WARNING (TPO-702): Missing the fieldname from program definition in file pfilename. The
inputted statement is
textstr The run will stop.
EXPLANATION:
The identified field name is empty in this PFILE statement. The operation name and the
register name are both required fields.
USER RESPONSE:
Add the required information to the statement in the PFILE and rerun the job.
WARNING (TPO-703): Invalid contents, fielddata, found in timing adjust field of the
following register operation definition in programming file pfilename. The inputted
statement is
textstr The integer 1 will be used.
EXPLANATION:
The identified field name in this programming file (PFILE) did not contain a single real
number. Either non-numeric characters were found, or there was something wrong with
the syntax, such as embedded commas or blanks.
USER RESPONSE:
Edit the PFILE to replace this field with a single positive integer, and rerun the job.
WARNING (TPO-704): Incorrect syntax found when parsing keyword keyword of

PLL_RESET statement in file pfilename. The statement is
PLL_RESET textstr This keyword value was ignored.

TPO - Messages
EXPLANATION:
The syntax of this statement is incorrect with respect to the identified keyword.
Processing continues as though the keyword was not specified on this statement.
USER RESPONSE:
Correct the syntax of this statement in the identified PFILE. Rerun the job.
WARNING (TPO-705): The timing adjust field of the following register operation definition in
programming file pfilename is not a positive integer. The input statement is textstr.
The integer fielddata will be used.
EXPLANATION:
The identified field name in this programming file (PFILE) contains a fraction, or a mixed
or negative number. Only positive integers are allowed. The number was rounded down
to an integer, or rounded up to 1, if it was less than 1, and the sign is ignored (assumed
positive).
USER RESPONSE:
Edit the PFILE to replace this field with a single positive integer, and rerun the job.
WARNING (TPO-706): Unrecognized statement in definition of mode opmodename:

:textstr This information is ignored.
EXPLANATION:
The printed statement was found in the START_MODE_DEFINITIONS{ section of the
PFILE identified by the prefix attached to the operational mode name identified in the
message. The statement could not be parsed, and is therefore being ignored.
USER RESPONSE:
Carefully check the syntax of the printed statement, correct it, and rerun the job.
WARNING (TPO-707): Processing Test Step stepname, there are conflicting definitions
for the same cut point at pin pinname. Connected to PPI ppiname1 in operational mode
opmodename1 and to PPI ppiname2 in operational mode opmodename2. The
connection to PPI ppiname1 will be used.
EXPLANATION:
This cut point was defined in the START_MODE_DEFINITIONS{ section of the PFILE
identified by the prefix on the name of operational mode in this message. The problem
is, it was associated with two different pseudo primary inputs (PPIs), probably as the
result of being defined in two different operational modes. A cut point net can not be

TPO - Messages
associated with more than one PPI. Processing will continue, but the results are
questionable.
USER RESPONSE:
It is unusual for two different PPI names to be associated with the same cut point, so the
programming file (PFILE) is suspect. If the PFILE is correct, then the conflict may be
caused by the test plan calling for the wrong operation for some register. If a bad PFILE
is suspected, check the spelling of the PPIs (maybe it should be the same PPI in both
cases). The conflict must be resolved by either eliminating one of the cut point definitions,
by connecting the net to the same PPI in both cases, by connecting two different nets to
the two PPIs, or by changing the operations called for in the test plan (so that both
definitions are not simultaneously in use). After making the necessary corrections to the
PFILE or to the test plan, rerun the job.
WARNING (TPO-708): Processing Test Step stepname, there is conflicting polarity

between cut point at pin pinname and PPI ppiname.Polarity is polarity1 in operational
mode opmodename1 and polarity2 in operational mode opmodename2. The
polarity1 polarity will be used.
EXPLANATION:
This cut point was defined in the START_MODE_DEFINITIONS{ section of the PFILE
identified by the prefix on the name of the operational mode in this message. The
problem is, it has two opposing polarities with respect to its associated pseudo primary
input (PPI), probably as the result of being defined in two different operational modes.
Processing will continue, but the results are questionable.
USER RESPONSE:
It is possible for the same operation (on two different registers) to identify two different
operational modes, but this would be unusual, so the most likely cause is a wrong
operation specified for some register in the test plan. If the PFILE is suspect, first check
for correct polarities. It may be a typographical error. Check that the correct mode was
specified for each register operation. After making the necessary corrections to the
PFILE or to the test plan, rerun the job.
WARNING (TPO-710): Test function attributes for PPI ppiname have been defined twice
in processing Test Step stepname. They were defined first in mode opmodename1 as
textstr1, and redefined in mode opmodename2 as textstr2.\n The earlier attributes
will be used.
EXPLANATION:
The named pseudo primary input (PPI) is defined in the START_MODE_DEFINITIONS{
section of the PFILE identified by the prefixes on the names of the operational modes in

TPO - Messages
this message. The test function attributes on a PPI can not be redefined. Processing
will continue using the test function attributes first encountered for this PPI.
USER RESPONSE:
It is unusual for two different operational modes to be specified for the same entity for the
same test step, so a likely cause of this error is a wrong operation specified for some
register in the test plan. If, on the other hand, the PFILE is suspect, check that the correct
mode was specified for each register operation. After making the necessary corrections
to the PFILE or to the test plan, rerun the job.
WARNING (TPO-711): Processing Test Step stepname, found conflicting polarities for PPI
ppiname as testfunction pin. Specified as polarity1 in mode opmodename1 and
polarity2 in mode opmodename2. polarity1 testfunction will be used.
EXPLANATION:
The named pseudo primary input (PPI) is defined in the START_MODE_DEFINITIONS{
section of the PFILE identified by the prefixes on the names of the operational modes in
this message. The test function attributes on a PPI can not be redefined, and in this case,
they conflict. Processing will continue using the test function polarity first encountered for
this PPI.
USER RESPONSE:
It is unusual for two different operational modes to be specified for the same entity for the
same test step, so a likely cause of this error is a wrong operation specified for some
register in the test plan. If, on the other hand, the PFILE is suspect, check that the correct
mode was specified for each register operation. After making the necessary corrections
to the PFILE or to the test plan, rerun the job.
WARNING (TPO-712): PFILE filename, mode opmodename defines a cut point at pin
pinname, but block blockname has no such pin. This cut point definition will be ignored
for this instance.
EXPLANATION:
The START_MODE_DEFINITIONS{ section of the named programming file (PFILE)
specifies a cut point to be placed on the net driven by the named pin, but this pin can not
be found. The block, identified in the message, which holds the TB_OPCG_INSTANCE
property with which this PFILE is associated, has no pin with this name.
USER RESPONSE:
Make sure the correct pin name was specified in the PFILE. If it is the correct pin name,
then the TB_OPCG_INSTANCE property must have been placed on the wrong block. If

TPO - Messages
you need to change the properties in the net list, re-import the circuit and rerun the job.
If it is a PFILE error, you need only change the PFILE and rerun the job.
WARNING (TPO-713): PFILE filename contains two definitions for the same register and
operation: Register name is regname, operation opname. The first definition will be used:
textstr1, textstr2, textstr3, textstr4, textstr5.
EXPLANATION:
The named operation was defined twice for the same register. The definition first
encountered is the one that will be used.
USER RESPONSE:
Check for correct spelling of the operation name and the register name. It could be a
typographical error where a different operation or register was intended. If it is a
duplicate definition, then decide which definition is the correct one and erase the other.
After editing the programming file (PFILE), rerun the job.
ERROR (TPO-714): PFILE filename1 specifies OPCG_TYPE=opcgtype1 and\n

PFILE filename2 specifies OPCG_TYPE=opcgtype2. OPCG_TYPE opcgtype1 will be
used.
EXPLANATION:
There are three defined values for OPCG_TYPE: "Standard", "Custom", or "None". This
program is limited to supporting only one OPCG_TYPE per circuit, although theoretically,
there could be a different OPCG_TYPE per testmode. Two programming files (PFILEs)
specified different values for OPCG_TYPE. The first one encountered is the value that will
be used for all the test modes created by this run.
USER RESPONSE:
Make sure the chosen OPCG_TYPE is correct. If it is not, change the PFILEs to the
correct value and rerun the job. To avoid future occurrences of this message, make sure
all the PFILEs are consistent.
ERROR (TPO-715): PFILE filename1 specifies LOAD_TYPE=loadtype1 and PFILE

filename2 specifies LOAD_TYPE=loadtype2. LOAD_TYPE loadtype1 will be used.
EXPLANATION:
There are three defined values for LOAD_TYPE: "serial_setup", "scan", or "1149.1". This
program is limited to supporting only one LOAD_TYPE per circuit, although theoretically,
there could be a different LOAD_TYPE per testmode. Two programming files (PFILEs)
specified different values for LOAD_TYPE. The first one encountered is the value that will
be used for all the testmodes created by this run.

TPO - Messages
USER RESPONSE:
Make sure the chosen LOAD_TYPE is correct. If it is not, change the PFILEs to the
correct value and rerun the job. To avoid future occurrences of this message, make sure
all the PFILEs are consistent.
ERROR (TPO-716): OPCG_TYPE was not specified in any PFILE. No output files will be
created.
EXPLANATION:
There are three defined values for OPCG_TYPE: "Standard", "Custom", or "None". It is
most likely that you would want to use "Custom." For "None," you would not be running
this program, and you would not need a programming file (PFILE). Similarly, for
"Standard," it is not likely that you would be using this program. OPCG_TYPE must be
specified in at least one of the PFILEs, and all PFILEs must be consistent (if specified,
they must all agree, but some of them may omit the OPCG_TYPE statement).
USER RESPONSE:
Add the correct value for OPCG_TYPE to your PFILEs and rerun the job.
ERROR (TPO-717): LOAD_TYPE was not specified in any PFILE. No output files will be
created.
EXPLANATION:
There are three defined values for LOAD_TYPE: "serial_setup", "scan", or "1149.1". At
least one of the PFILEs must specify the LOAD_TYPE, and all PFILEs must be
cvonsistent (if specified, they must all agree, but some of them may omit the LOAD_TYPE
statement).
USER RESPONSE:
Add the correct value for LOAD_TYPE to your PFILEs and rerun the job.
INFO (TPO-718): PFILE filename, mode opmodename defines a cut point at pin
pinname, but this pin on block blockname is inactive. This cut point definition will be
ignored for this instance.
EXPLANATION:
In this testmode, the identified pin has no effect on any observable circuit
behavior. There would be no reason to define a cut point here.
USER RESPONSE:

TPO - Messages
None. The purpose of this message is to explain why you may have a smaller number
of cut points defined than you may have expected.
ERROR (TPO-719): Mismatched quotes found when parsing the mode definition statements
for operational mode opmodename. The statement is textstr.
EXPLANATION:
The programming file (PFILE) identified by the prefix on the operational mode name
contains in the START_MODE_DEFINITIONS{ section a statement with mismatched
quotation marks. This will cause confusion in parsing the statement, so the statement is
ignored.
USER RESPONSE:
Determine where the opening or closing quotation mark character should go, edit the file,
and rerun the job. Note that statements may span multiple lines; the opening and closing
quotation mark characters need not be on the same line in the file. Note also that
comments (which start with either "#" or "//") are allowed between quotation marks. If
this is the case, the closing quotation mark character must be on a different line, because
the comment would extend to the end of the line. The closing quotation mark character
may have gotten lost within a comment field.
ERROR (TPO-720): Unable to parse the following mode definition statement for operational
mode opmodename in programming file (PFILE) filename. The statement is
textstr.
EXPLANATION:
The programming file (PFILE) named in the message contains in its
START_MODE_DEFINITIONS {section a statement which could not be parsed.
USER RESPONSE:
Make sure the file name is correct. If it is the correct file, look at the context of this
statement within the file. Perhaps the statement is out of order or there is a missing
section header. Check the punctuation and the spelling of the keywords on the statement
to make sure they are correct. After you diagnose the problem, edit the programming file
and rerun the job.
ERROR (TPO-721): Invalid fieldname field contents: textstr1 found in the following
statement in programming file (PFILE) pfilename.textstr2 The run will stop.
EXPLANATION:
The data field of the statement is supposed to contain a binary vector to be loaded into
the register. This statement has a character other than 0 or 1 in the data field.

TPO - Messages
USER RESPONSE:
Edit the PFILE by specifying a binary vector (all 1's and 0's) in the data field. Then rerun
the job.
ORIGINAL EXPLANATION: (This is irrelevant with existing code because the only
field that is curently checked is the data field, as explained above.) The named
programming file (PFILE) contains the printed statement which has invalid data in the
named field. The fields are positional, and their names are defined in the first statement
appearing in the START_PROGRAM_DEFINITIONS or
START_INTERNAL_DOMAIN_PROGRAM_DEFINITIONS section of the PFILE. If the first
statement in this section does not consist of a series of field names, then the default
ordering is assumed. The default order of the fields is op, reg, mode, seq, timadj, data
where "op" is the field containing operation names "reg" is the field containing register
names "mode" is the field containing names of the operational modes "seq" is the field
containing names of the test sequences "timadj" is the field containing coefficients for
specifying timing in the test sequences "data" is the field containg the binary vector to be
loaded into the register
ERROR (TPO-722): Unrecognized statement in definition of mode opmodename:

textstr This mode definition will be ignored, and the run will stop.
EXPLANATION:
The printed statement is the first statement in the named mode definition. The
programming file (PFILE) is identified by the first part of the mode name. This statement
begins with an unrecognized keyword.
USER RESPONSE:
Edit the PFILE and correct the mode definition statement. Then rerun the job.
ERROR (TPO-723): Programming file (PFILE) pfilename operation opname for register
regname refers to mode opmodename, but mode opmodename is not defined in the
PFILE. The run will stop.
EXPLANATION:
The programming file (PFILE) contains a reference to an operational mode, but this
operational mode is not defined. The reference is in a statement in the
START_PROGRAM_DEFINITIONS or
START_INTERNAL_DOMAIN_PROGRAM_DEFINITIONS
section of the PFILE, and this statement is identifiable by the operation name and the
register name which are printed in the message text.
USER RESPONSE:

TPO - Messages
Make sure the name of the operational mode is spelled correctly, both in the referenced
PROGRAM_DEFINITION statement and in the MODE_DEFINITION statement, Make
sure the use of upper-case and lower-case characters is consistent. Either the name is
misspelled, or the MODE_DEFINITION statement is missing. Edit the PFILE to correct
the problem and rerun the job.
ERROR (TPO-724): Programming file (PFILE)pfilename operation opname for register

regname refers to sequence seqname, but sequence seqname is not defined in the
PFILE. The run will stop.
EXPLANATION:
The programming file (PFILE) contains a reference to a sequence definition, but this
sequence is not defined. The reference is in a statement in the
START_PROGRAM_DEFINITIONS section of the PFILE, and this statement is identifiable
by the operation name and the register name which are printed in the message text.
USER RESPONSE:
Make sure the name of the sequence is spelled correctly, both in the referenced
PROGRAM_DEFINITION statement and in the SEQUENCE_DEFINITION statement,
Make sure the use of upper-case and lower-case characters is consistent. Either the
name is misspelled, or the sequence definition is missing. Edit the PFILE to correct the
problem and rerun the job. If the PFILE sequence definition contains a
testmode=<namelist> { statement, check that <namelist> includes the exact
name of the testmode as specified in the build_opcg_testmode command. If you
want to use a different testmode name from any of those in the <namelist> list, include
the pfilemodename=<name> keyword, where <name> is the appropriate name from
<namelist>.
ERROR (TPO-725): Mismatched parenthesis or square bracket in the following line of

filetype filename
textstr1 following
textstr2. The run will stop.
EXPLANATION:
The named file contains a line, printed as <textstr1>, which could not be parsed
because of mismatched parentheses () or square brackets [].
USER RESPONSE:
Find the mismatched character in the printed statement. It is the character immediately
following the character string printed as <textstr2>. Determine if this is an extra
punctuation character which should be deleted, or if a matching punctuation character
needs to be added to the statement. Edit the PFILE accordingly and rerun the job.

TPO - Messages
ERROR (TPO-726): Wrong number of fields provided in the following line of filetype
filename. Expected integer1, found integer2.
textstr. The run will stop.
EXPLANATION:
The named file contains a line, printed as textstr1, which could not be parsed
because it contains the wrong number of fields. The correct number is printed as
<integer1>. The file statement contained <integer2> fields. The fields are
separated by commas.
USER RESPONSE:
From the message, it is clear whether there are too many or too few comma delimiters
in the statement. In either case, it may be a typographical error. If all the punctuation is
correct, then it is a matter of having too few or too many fields specified. After
determining the nature of the problem, edit the PFILE and rerun the job.
ERROR (TPO-727): Unrecognized statement in START_MULTIPLIER_DEFINITIONS

section of programming file (PFILE) pfilename.
textstr. The run will stop.
EXPLANATION:
Each MULTIPLIER_DEFINITIONS statement consists of a pin name followed by three
comma-separated fields: PINNAME frequency-ratio,#pulsesout,latency; The pin name
and the first field (the frequency-ratio) are separated by one or more spaces. The
statement was not recognized either because there is no space between the pin name
and the frequency-ratio, or because something is missing (no pin name or no non-blank
comma-separated fields following the pin name).
USER RESPONSE:
See what is missing from the MULTIPLIER_DEFINITIONS statement, then edit the
PFILE and rerun the job.
ERROR (TPO-728): Pin pinname, referenced in the

START_MULTIPLIER_DEFINITIONS section of PFILE pfilename, is not defined in this
PFILE as an output pin. The run will stop.
EXPLANATION:
comma-separated fields: PINNAME frequency-ratio,#pulsesout,latency; The pin name
must be defined as an output pin in the PFILE PLL_OUT_OSC statement if the PFILE is
for a PLL or in the DOMAIN_OUT_CLOCK statement if the PFILE is for a clock generation
macro.

TPO - Messages
USER RESPONSE:
Make sure all the pin names are spelled properly in the above-referenced PFILE
statements. Look for mismatches in the case (upper-case vs. lower- case characters).
The pin name may be missing from the PLL_OUT_OSC/ DOMAIN_OUT_CLOCK
statement. Correct the problem by editing the PFILE and rerun the job.
WARNING (TPO-729): Pin pinname in PFILE pfilename is not included in the

START_MULTIPLIER_DEFINITIONS section of the PFILE. pinname
textstr1,textstr2,textstr3 will be used. Correct the PFILE and rerun the job.
EXPLANATION:
comma-separated fields: PINNAME frequency-ratio,#pulsesout,latency; There must be
one statement for each pin defined as an output pin in the PFILE PLL_OUT_OSC
statement if the PFILE is for a PLL or in the DOMAIN_OUT_ CLOCK statement if the
PFILE is for a clock generation macro.
USER RESPONSE:
Make sure all the pin names are spelled properly in the above-referenced PFILE
statements. Look for mismatches in the case (upper-case vs. lower- case characters).
Add another MULTIPLIER_DEFINITIONS statement if the pin is really missing. Correct
the problem by editing the PFILE and rerun the job.
INFO (TPO-730): Reading programming file (PFILE) pfilename.

EXPLANATION:
The purpose of this message is to tell which PFILE was used in cases where the
pfiledir keyword specifies multiple directories, and the same PFILE exists in more
than one of these directories. The directory appears as part of the PFILE name in the
message.
USER RESPONSE:
If there are unexpected results reported in the log which may have been caused by a
back-level or wrong version of a PFILE being used, check the list of TPO-730 messages
to verify that the correct PFILE was used.
ERROR (TPO-732): Programming file (PFILE) pfilename contains an ASSIGN statement for
pseudo primary input (PPI) ppiname in the START_MODE_DEFINITIONS section for mode
opmodename, but this PPI is not defined in a CUTPOINT statement for this mode. Correct
the PFILE and rerun the job.
EXPLANATION:

TPO - Messages
The START_MODE_DEFINITIONS section of the PFILE contains the information to

define where cutpoints are to be placed and the test functions to be assigned to their
associated pseudo primary inputs (PPIs). A PPI is defined when it is connected to a
cutpoint. This message is saying that a PPI is being assigned a test function, but the PPI
has not been defined (is not associated with any cutpoint). If the program had continued,
the test function assignment would have been ignored, because the PPI does not exist.
There are two likely causes for the error. Either the CUTPOINT statement that defines the
PPI is missing, or the spelling of the PPI name in the ASSIGN statement does not match
its spelling in the CUTPOINT statement. A more unlikely EXPLANATION: is that the
ASSIGN statement is superfluous.
USER RESPONSE:
Determine whether the PPI is supposed to exist. If not, remove the ASSIGN statement
from the PFILE. If it is supposed to exist, determine whether there is a missing
CUTPOINT statement or if there is a spelling error in one of the statements. After editing
the PFILE, rerun the job.
ERROR (TPO-733): Programming file (PFILE) pfilename does not define an output pin.
PLL and CLOCKDOMAIN macros must have a defined output pin.\n Correct the PFILE and
rerun the job.
EXPLANATION:
The named programming file (PFILE) did not contain an output statement
(PLL_OUT_OSC for PLLs, DOMAIN_OUT_CLOCK for CLOCKDOMAIN PFILES) which
identifies the clock output pin of the macro. As stated in the message text, this is
required.
USER RESPONSE:
Examine the macro and identify the clock output pin. After editing the PFILE, rerun the
job.
ERROR (TPO-734): Programming file (PFILE) pfilename is an unrecognized

OPCG_ENTITY. OPCG_ENTITY=textstr was specified. It must be either PLL,
CLOCKDOMAIN, or REGISTER. Correct the PFILE and rerun the job.
EXPLANATION:
The named programming file (PFILE) has an invalid value specified for OPCG_ENTITY.
PLL, CLOCKDOMAIN, and REGISTER are the only recognized entities. The REGISTER
entity is the most flexible, and should be used if and only if the macro does not produce
a PLL or clock signal.
USER RESPONSE:

TPO - Messages
Determine what type of macro is being described and specify the OPCG_ENTITY as
PLL, CLOCKDOMAIN, or REGISTER. After editing the PFILE, rerun the job.
ERROR (TPO-735): An unrecognized statement was found in the

START_INTERNAL_DOMAIN_REGISTER_DEFINITIONS section of programming file
(PFILE) pfilename. The statement is
textstr
Correct the PFILE and rerun the job.
EXPLANATION:
The START_INTERNAL_DOMAIN_REGISTER_DEFINITIONS section of the named
programming file (PFILE) contains the statement that was printed in the message. The
statement could not be parsed. The program was looking for the keyword type (without
the quotation characters), followed by a single (non-blank) character string that identifies
the register type.
USER RESPONSE:
Make sure the keyword type was spelled correctly, Make sure there are no embedded
blanks in the type value (following the keyword). Make sure the keyword and the value
are separated by a single equal sign and/or one or more blanks. If the line contains a
comment, make sure a valid comment character was used (# or //). After editing the
PFILE, rerun the job.
ERROR (TPO-736): An unrecognized register type was specified for register regname in
programming file (PFILE) pfilename. The statement is
textstr. Valid register types are BLOCK_DOMAIN_INPUTS, CLOCK_GATE, and
SOURCE_SELECT. Correct the PFILE and rerun the job.
EXPLANATION:
The START_INTERNAL_DOMAIN_REGISTER_DEFINITIONS section of the named
programming file (PFILE) contains a TYPE statement with an invalid value. The only
valid internal domain register types are BLOCK_DOMAIN_INPUTS, SOURCE_SELECT,
and CLOCK_GATE.
USER RESPONSE:
Specify one of the above valid register types. After editing the PFILE, rerun the job.
ERROR (TPO-737): Unable to find mode information for programming file (PFILE)
pfilename referenced by pinname. Correct the PFILE and rerun the job.
EXPLANATION:

TPO - Messages
The identified node (block, pin or net) points to the named programming file (PFILE)
through a netlist property, but it has no corresponding register name netlist property. In
this case, the only relevant information in the PFILE would be the mode information,
which defines cutpoints and pseudo-primary inputs (PPIs) and specifies the test function
for these PPIs. In this case, the PFILE has no such information, so the property on this
node carries no useful information.
USER RESPONSE:
It would be unusual for a PFILE not to have any mode information. If, however this is the
case, then the specification of this PFILE on a node that has no register name property
is in error. There are three possible scenarios:
The PFILE is wrong and should contain node information. Edit the PFILE.
The PFILE should not have been specified on this node. Edit the netlist.
The node should have a register name property. Edit the netlist.
After editing the PFILE, rerun the job. If the netlist must be changed, rebuild the model
and resume processing from that point in the methodology.
WARNING (TPO-738): Programming file (PFILE) pfilename was referenced on

pinname but this was not defined to be a register bit, and the PFILE has registers defined
within it. It appears that the wrong PFILE name may have been specified or the
TB_OPCG_PFILE property was specified on the wrong signal. Correct the netlist and rerun
the job.
EXPLANATION:
The identified node (block, pin or net) points to the named programming file (PFILE)
through a netlist property, but it has no corresponding register name netlist property. In
this case, the only relevant information in the PFILE would be the mode information,
which defines cutpoints and pseudo-primary inputs (PPIs) and specifies the test function
for these PPIs. In this case, the PFILE also defines register bits, so it appears that the
wrong PFILE was identified in the netlist, the PFILE contains extraneous information, or
the PFILE property was placed on the wrong node in the netlist.
USER RESPONSE:
There are four possible scenarios:
The PFILE is wrong and should not contain register information. In this case, the
message can be ignored. Edit the PFILE to eliminate this message in future jobs.
The PFILE should not have been specified on this node. Edit the netlist.
The wrong PFILE was specified. Edit the netlist.

TPO - Messages
The node should have a register name property. Edit the netlist.
After editing the netlist, rebuild the model and resume processing from that point in the
methodology.
WARNING (TPO-739): One or more TB_ASYNC_ENABLE properties were found, but no

TB_ASYNC_CLOCK properties were found. The TB_ASYNC_ENABLE property(ies) on the
following pin(s) will be ignored: pin pinname
EXPLANATION:
The TB_ASYNC_CLOCK property identifies a pin that is to be used as a clock for
initializing floating (non-scan) latches/flops following the scan load operation for a test.
The TB_ASYNC_ENABLE property identifies a pin that enables such clocks. There is no
reason to use the TB_ASYNC_ENABLE property unless some TB_ASYNC_CLOCK is
specified.
USER RESPONSE:
If the intent is to specify how to load any floating latches/flops that exist in the design,
then one or more TB_ASYNC_CLOCK properties must be specified. Edit the netlist and
resume the processing with the build_model step. If this was not the intent, then the
TB_ASYNC_ENABLE property is harmless, and the message can be safely ignored.
ERROR (TPO-740): Pin pinname has the TB_ASYNC_CLOCK property, but it does not have
a clock test function attribute. Correct the netlist or the assign file and rerun the job.
EXPLANATION:
initializing floating (non-scan) latches/flops following the scan load operation for a test. It
must therefore also be identified as a clock via the test function pin attributes. This pin
did not have a clock test function.
USER RESPONSE:
If the pin was improperly identified as a TB_ASYNC_CLOCK, or the TB_ASYNC_CLOCK
property was placed on the wrong pin, correct the netlist, then restart the process
beginning with the build_model step. If the TB_ASYNC_CLOCK property is correct, then
add the appropriate test function to the identified pin via the assign file and rerun this job.
ERROR (TPO-741): Pin pinname has the TB_ASYNC_CLOCK property, but its clock
sequence number (textstr) is not an integer or is a negative integer. Correct the netlist
and resume processing with the build_model step.
EXPLANATION:

TPO - Messages

initializing floating (non-scan) latches/flops following the scan load operation for a test,
and it specifies a "sequence number" that tells the order in which clocks are to be pulsed
in case there are more than one TB_ASYNC_CLOCK pins. The sequence number must
be a non-negative integer. This TB_ASYNC_CLOCK property either specified a non-
integer or it specified a negative integer.
USER RESPONSE:
Edit the netlist and restart the process beginning with the build_model step.
INFO (TPO-742): Unsupported statement found in programming file filename. This

function is planned for possible future use. The statement is textstr. This statement was
ignored.
EXPLANATION:
The printed statement was found in the indicated programming file (PFILE), and it was
recognized, but it is not supported. As stated in the message, there is an intent to
support the statement in a future software release. This message serves as a reminder
that the function is not yet supported.
USER RESPONSE:
None.
ERROR (TPO-743): Pin pinname has the TB_RASKEW_CLOCK property, but it does not
have a clock test function attribute. Correct the netlist or the assign file and rerun the job.
EXPLANATION:
The TB_RASKEW_CLOCK property identifies a pin that is to be used as a clock for loading
the B-clocked latches in a register array prior to a scan unload event. It must therefore
also be identified as a clock via the test function pin attributes. This pin did not have a
clock test function.
USER RESPONSE:
If the pin was improperly identified as a TB_RASKEW_CLOCK, or the TB_RASKEW_CLOCK
property was placed on the wrong pin, correct the netlist, then restart the process
beginning with the build_model step. If the TB_RASKEW_CLOCK property is correct,
then add the appropriate test function to the identified pin via the assign file and rerun
this job.
ERROR (TPO-744): Pin pinname has the TB_RASKEW_CLOCK property, but its clock
sequence number (textstr) is not an integer or is a negative integer. Correct the netlist
and resume processing with the build_model step.

TPO - Messages
EXPLANATION:
the B-clocked latches in a register array prior to a scan unload event, and it specifies a
"sequence number" that tells the order in which clocks are to be pulsed in case there are
more than one TB_RASKEW_CLOCK pins. The sequence number must be a non-negative
integer. This TB_RASKEW_CLOCK property either specified a non-integer or it specified a
negative integer.
USER RESPONSE:
Edit the netlist and restart the process beginning with the build_model step.
WARNING (TPO-745): One or more TB_RASKEW_ENABLE properties were found, but no

TB_RASKEW_CLOCK properties were found. The TB_RASKEW_ENABLE property(ies) on the
following pin(s) will be ignored : pin pinname
EXPLANATION:
the B-clocked latches in a register array prior to a scan unload event. The
TB_RASKEW_ENABLE property identifies a pin that enables such clocks. There is no
reason to use the TB_RASKEW_ENABLE property unless some TB_RASKEW_CLOCK is
specified.
USER RESPONSE:
If the intent is to specify clocking for B-clocked latches within a register array, then one
or more TB_RASKEW_CLOCK properties must be specified.
Edit the netlist and resume the processing with the build_model step. If this was not
the intent, then the TB_RASKEW_ENABLE property is harmless, and the message can be
safely ignored.
WARNING (TPO-752): PFILE filename, mode opmodename defines a cut point at pin
pinname, but block blockname has no such pin. This cut point definition will be ignored
for this instance.
EXPLANATION:
The START_MODE_DEFINITIONS{ section of the named programming file (PFILE)
specifies a cut point to be placed on the net driven by the named pin, but this pin can not
be found. The block, identified in the message, which holds the
TB_INT_DOMAINS_INSTANCE property with which this PFILE is associated, has no pin
with this name.
USER RESPONSE:

TPO - Messages
Make sure the correct pin name was specified in the PFILE. If it is the correct pin name,
then the TB_INT_DOMAINS_INSTANCE property must have been placed on the wrong
block. If you need to change the properties in the net list, re-import the circuit and rerun
the job. If it is a PFILE error, you need only change the PFILE and rerun the job.
WARNING (TPO-753): Unrecognized statement found in programming file (PFILE)

pfilename. Looking for a statement of the form
modename. The PFILE statement is textstr. This statement was ignored.
EXPLANATION:
The program is looking for the start of a PFILE register mode definition. The statement
would appear as modename { The statement found, as printed in the message text, is
not a character string followed by an opening brace, so it is not recognized. The
statement may simply be missing the opening brace. Or perhaps the entire statement is
missing, and the text found, as printed in the message, is part of the mode definition
body.
USER RESPONSE:
Determine the exact nature of the error. Then edit the PFILE and rerun the job.
ERROR (TPO-754): PPI ppiname has a specified test function of testfunction in mode
textstr, and the keyword force was specified in the PFILE. Forcing of testfunction
cutpoints is not supported. The run will stop.
EXPLANATION:
The programming file (PFILE) defined the named pseudo primary input (PPI), and
specified that the corresponding cutpoint should be forced to its "stability" value in the
modeinit sequence. The PFILE can be identified as the first part of the mode name
printed in the message, and is also part of the PPI name. The problem is that the test
function of this PPI does not allow it to be forced to value in the modeinit sequence using
the Force event. For example, if the PPI is a linehold (say, -LH), forcing the cutpoint net
to 0 in the modeinit sequence is not valid, because lineholds can be overridden at run
time, and then the Force event would be wrong. This could cause the suppression of
serious TTM messages (specifically, TTM-438).
USER RESPONSE:
Edit the PFILE by removing the force keyword, or changing the test function of the PPI
to a clock, TC, or TI. Then rerun the job.
WARNING (TPO-755): PPI ppiname has no test function specified for mode textstr in PFILE
filename.
EXPLANATION:

TPO - Messages
The programming file (PFILE) defines the named pseudo primary input (PPI), but does
not specify any test function pin attribute for this PPI. Encounter Test will treat such a PPI
as an X-state source. This is likely not the desired outcome; hence, the warning
message.
USER RESPONSE:
Make sure the PPI was not intended to be an X-state source. If that was the intention,
then you should ignore this message. Otherwise, determine the correct test function
attribute that should be assigned to the PPI, and edit the PFILE accordingly. Then rerun
the job.
ERROR (TPO-756): The formula specified for the input/output frequency ratio for pin
piname in PFILE filename integer produces a negative number for test step integer.
The run will stop. The PFILE formula is textstr1 After substitutions, the formula is
textstr2.
EXPLANATION:
In the named programming file (PFILE), the first field of the
START_MULTIPLIER_DEFINITIONS statement is the input/output frequency ratio for
the named macro output pin. The ratio may be expressed as a formula, using numbers
from the PFILE's START_PROGRAM_DEFINITIONS section as variables. In this case,
the formula returned a negative value, which has no meaning. This indicates an error in
the formula.
USER RESPONSE:
Make sure the formula as printed in the message is the same as what was specified in
the PFILE, to rule out a software error. Make sure any substitutions are correct, also to
rule out software error. This verification will require a meticulous review of the test plan
to check on the loading of the control registers. If no software error is found, review the
formula to find the mistake which is causing the calculated ratio to be negative in this
case. Then edit the PFILE and rerun the job.
ERROR (TPO-757): The formula specified for the number of output pulses for pin piname
in PFILE filename produces a negative number for test step integer. The run will stop.
The PFILE formula is textstr1 After substitutions, the formula is textstr2
EXPLANATION:
In the named programming file (PFILE), the second field of the
START_MULTIPLIER_DEFINITIONS statement is the number of output pulses for the
named macro output pin. The number may be expressed as a formula, using numbers
from the PFILE's START_PROGRAM_DEFINITIONS section as variables. In this case,
the formula returned a negative value, which has no meaning. This indicates an error in
the formula.

TPO - Messages
USER RESPONSE:
formula to find the mistake which is causing the calculated number to be negative in this
ERROR (TPO-758): The formula specified for the latency for pin piname in PFILE
filename produces a negative number for test step integer. The run will stop. The
PFILE formula is textstr1. After substitutions, the formula is textstr2.
EXPLANATION:
In the named programming file (PFILE), the third field of the
START_MULTIPLIER_DEFINITIONS statement is the latency for the named macro
output pin. Latency is defined as an adder which is used to calculate the required
number of input clock pulses to produce some specified number of output pulses. The
total number of input clock pulses required is equal to the number of output pulses
divided by the input/output frequency ratio, plus the latency. The latency may be
expressed as a formula, using numbers from the PFILE's
START_PROGRAM_DEFINITIONS section as variables. In this case, the formula
returned a negative value, which has no meaning. This indicates an error in the formula.
USER RESPONSE:
formula tofind the mistake which is causing the calculated latency to be negative in this
ERROR (TPO-759): Test function attributes for PPI ppiname in programming file (PFILE)
filename are defined twice.They were defined first in mode opmodename1 as
textstr1, and redefined in mode opmodename2 as textstr2. The run will stop.
EXPLANATION:
The named pseudo primary input (PPI) is defined in the START_MODE_DEFINITIONS
{section of the named PFILE under the operational modes in this message. Only one set
of test function attributes on a PPI is allowed. If the PPI has multiple test functions, they
must all be specified on the same statement in a comma-separated list.
USER RESPONSE:

TPO - Messages
ERROR (TPO-760): Processing programming file (PFILE) filename, found conflicting

polarities for PPI ppiname as testfunction pin. Specified as polarity1 in mode
opmodename1 and polarity2 in mode opmodename2. The run will stop.
EXPLANATION:
The named pseudo primary input (PPI) is defined in the START_MODE_DEFINITIONS
section of the PFILE named in the message. In this case, the PPI was repeatedly given
the same test function attribute, but with opposite polarities. The pin cannot
simultaneously have different polarities for the same test function. The run will stop.
USER RESPONSE:
WARNING (TPO-761): Programming file filename, mode opmodename defines a clock

PPI on pin pinname, but this cutpoint pin is not included in the list of outputs of this macro.
EXPLANATION:
A cutpoint, especially one that is assigned a clock test function, would seem to be
producing an output signal for the macro. As stated in the message, this cutpoint pin is
not listed as one of the functional macro outputs in the programming file (PFILE). Timing
information for the clocks is dependent upon the information in the
START_MULTIPLIER_DEFINITIONS section of the PFILE, which is 1-to-1 with the list
of outputs. Since this cutpoint pin is not listed as an output in the PFILE
DOMAIN_OUT_CLOCK statement, No timing information will be available for the waveform
produced by this signal.
USER RESPONSE:
Look for error messages that result from the lack of timing information. If this cutpoint/
PPI is not switching in any dynamic patterns, its absence from the DOMAIN_OUT_CLOCK
statement should not cause a problem. If it is used in a dynamic pattern, an error
message should appear. To eliminate this warning message, add the pin name
appearing in this message to the DOMAIN_OUT_CLOCK statement in the named PFILE,
and add the timing information to the START_MULTIPLIER_DEFINITIONS section of
the PFILE.
INFO (TPO-762): Pseudo primary input (PPI) ppiname is connected to more than one
cutpoint net: netname1 and netname2
EXPLANATION:

TPO - Messages
There is nothing wrong with one PPI controlling two or more cutpoint nets. The software
is checking for this condition because it needs to be able to look up the cutpoint
associated with a given PPI. Appearance of this message may cause some other
messages, such as TPO-952, to be misleading, identifying the wrong cutpoint.
USER RESPONSE:
If you did not expect the programming file (PFILE) to define two cutpoints to be
connected to the same PPI, then examine the PFILE to see why this happened, and then
correct the PFILE and rerun the job, if necessary. If this was expected, then no action is
needed.
ERROR (TPO-763): No header record found in the PGT input file filename.The run will stop.
EXPLANATION:
The PGT input file lists the module instances for which the partial-good test methodology
is being applied, and specifies the testmode number and scanout number for each. The
testmode number and scanout number translate into row and column, respectively.
There are also several other items of information, some of which are optional, and most
of which are not used by build_internal_domains_testmode. The record format
is flexible, the fields being defined by a header record, which is the first record of the file.
This message is saying that the header record contains no recognizable field names.
Thus, the software does not know how to parse the information, and therefore cannot
proceed to do the PGT processing. The recognized field names are:
Mode_#
Scanout_#
Scanout_Name
Customer_PGB_ID_#
PGB_Name
BISTCNTL_Enumeration_#s
Customer_PGB_Name
PGB_Hierarchical_Instance_Name
USER RESPONSE:
Make sure the header record exists, and that the field names are spelled correctly. Make
sure the header record does not have comment characters # or // at the beginning of the
line. Make sure the header record is the first non-blank, non-commented line in the file.
Edit the file as needed, and then rerun the job.

TPO - Messages
ERROR (TPO-764): The field textstr is not defined in the PGT input file filename. The
run will stop.
EXPLANATION:
This message is saying that the header record does not identify the named field. This
field is needed by the software, and therefore PGT processing cannot proceed.
USER RESPONSE:
Make sure this field is included in the header record, and that the field name is spelled
correctly. Make sure there are no missing commas, which could cause two adjacent field
names to be misinterpreted as a single field. Edit the file as needed, and then rerun the
job.
ERROR (TPO-765): An unrecognized block name usageblockname was found in the

textstr field of line integer of the PGT input file filename. This record will be ignored,
and the run will stop.
EXPLANATION:
This message is saying that some record refers to an instance block name which can not
be found in the model. This record is being ignored, and the run will not complete.
USER RESPONSE:
The integer printed in the message identifies the line number in the file. Verify that this
line in the file contains the block name that was printed in the message. Determine the
correct spelling of the block name, and edit the file accordingly. Then rerun the job.
ERROR (TPO-766): The PGT input file filename, line integer, field textstr1 for
block usageblockname, contains textstr2, which is not recognized as an integer.
textstr1 should be an integer. This record will be ignored, and the run will stop.
EXPLANATION:

TPO - Messages
This message is saying that some record has an invalid identifier for the testmode
number or the scanout number. This record is being ignored, and the run will not
complete.
USER RESPONSE:
The integer printed in the message identifies the line number in the file. Verify that this
line in the file contains the block name that was printed in the message. Determine the
correct integer to be specified for the named field, and edit the file accordingly. Then
rerun the job.
ERROR (TPO-767): PGT module pin pinname1 in Row integer is fed by clock macro pin
pinname2, and the corresponding module pin pinname3 in Row 1 is fed by clock macro
pin pinname4 but clock macro blockname1 has already been paired with clock macro
blockname2 which feeds row 1. The run will stop.
EXPLANATION:
An attempt is being made to pair up the clock macros so that the clocks which control the
PGT modules in row 1 of the PGT array can have their programming copied to the
corresponding clocks which feed other rows of the PGT array. This is an essential step
in the PGT pattern reuse methodology. In this case, the pairing cannot be accomplished
because the same clock macro is feeding two different PGT modules (in different
columns) of row n, and the corresponding PGT modules in Row 1 are fed by different
clock macros which are not necessarily programmed identically.
USER RESPONSE:
Without redesigning the logic, you will have to run test generation on each row of the PGT
matrix (you cannot use the pattern re-use methodology). It might be possible to define
multiple, non-overlapping PGT matrices and run test generation once for each matrix, but
this could get messy.
ERROR (TPO-768): Mismatched clock macros are paired. PGT module pin pinname1 in
Row integer is fed by clock macro pin pinname2, and the corresponding module pin
pinname3 in Row 1 is fed by clock macro pin pinname4, but the two clock macros have
different cell names (cellname1 and cellname2). The run will stop.
EXPLANATION:

TPO - Messages
in the PGT pattern reuse methodology. In this case, the two clock macros to be paired
are not the same cell type, so the test generation software would not know how to
program them identically.
USER RESPONSE:
ERROR (TPO-769): Comparing the connections between clock macro blockname1 and
PGT module blockname2 in row 1 with the connections between clock macro
blockname3 and PGT module blockname4 in row integer, the connection between
pins pinname1 and pinname2 in row integer has no counterpart in row 1. The run will
stop.
EXPLANATION:
in the PGT pattern reuse methodology. In this case, the interconnections between the
clock macro and the PGT module are different between the two rows. Even though we
might find the correlation between the clock macros and program them identically, there
is high risk that the behavior will be different between the two rows because of the
difference in how the clocks are connected.
USER RESPONSE:
ERROR (TPO-770): PGT module pin pinname1 in Row integer is fed by clock macro
pin pinname2, but no clock macro pin could be identified feeding the corresponding module
pin pinname3 in Row 1. The run will stop.
EXPLANATION:

TPO - Messages
USER RESPONSE:
ERROR (TPO-771): PGT module pin pinname1 in Row integer1 is fed by clock macro
pin pinname2, and the corresponding module pin pinname3 in Row 1 is fed by clock
macro blockname, but the connections between the clock and PGT modules do not
correspond between the two rows. Row 1 has integer2 connections and row integer1
has integer3 connections . The run will stop.
EXPLANATION:
USER RESPONSE:
ERROR (TPO-772): Row 1 of the partial-good array has integer1 modules, fewer than
row integer2 which has integer3 modules. The run will stop.
EXPLANATION:
in the PGT pattern reuse methodology. In this case, row 1 is shorter than the row n
identified in the message text, so it is not possible to match up the extra modules in row

TPO - Messages
n with their row 1 counterparts. Even worse, we would not have expect data for those
extra module positions.
USER RESPONSE:
matrix (you cannot use the pattern re-use methodology). It might be possible to redefine
the PGT matrix so that the longest row is row 1.
ERROR (TPO-773): Two different cells used in the same column of the partial-good array.\n
The module in row 1, column integer1 is cellname1 The module in row integer2,
column integer3 is cellname2. The run will stop.
EXPLANATION:
in the PGT pattern reuse methodology. In this case, the two PGT macros to be paired
are not the same cell type, so it is unlikely that they would behave identically even if
provided he same test pattern input.
USER RESPONSE:
ERROR (TPO-775): PGT module pin pinname1 in row integer is fed by clock pin
pinname2 but the corresponding pin pinname3 in row 1 is fed by clock pin pinname4.
The run will stop.
EXPLANATION:
USER RESPONSE:

TPO - Messages
ERROR (TPO-776): PGT module pin pinname1 In row 1 is fed by clock pin pinname2
but the corresponding pin pinname3 in row integer is not fed by a clock. The run will
stop.
EXPLANATION:
An attempt is being made to pair up the clock macros so that the clocks which $ control
the PGT modules in row 1 of the PGT array can have their programming copied to the
in the PGT pattern reuse methodology. In this case, no clock was found to be driving the
identified module pin in row n, where the corresponding module pin in row 1 is driven by
a clock. Thus, the clock interconnections are clearly different between the two rows, and
there is no way to guarantee identical behavior for the two rows.
USER RESPONSE:
matrix (you cannot use the pattern re-use methodology).
ERROR (TPO-777): PGT module pin pinname1 In row pinname2 is fed by clock pin integer
but the corresponding pin pinname3 in row 1 is not fed by a clock. The run will stop.
EXPLANATION:
An attempt is being made to pair up the clock macros so that the clocks which $ control
the PGT modules in row 1 of the PGT array can have their programming $ copied to the
in the PGT pattern reuse methodology. In this case, no clock was found to be driving the
identified module pin in row 1, where the corresponding module pin in row n is driven by
a clock. Thus, the clock $ interconnections are clearly different between the two rows,
and there is no way to guarantee identical behavior for the two rows.
USER RESPONSE:
Without redesigning the logic, you will have to run test generation on each $ row of the
PGT matrix (you cannot use the pattern re-use methodology).
WARNING (TPO-779): Block blockname, defined in the PGT Module List file as a PGT
module,\n does not have the ET_CORE=PG netlist property.
EXPLANATION:

TPO - Messages
The ET_CORE=PG property is intended for the imply_fault_rows command. It has no

effect upon how the testmode is built. For building the testmode, the information about
the partial-good matrix is supplied by the PGT Module List input file. This message is an
early warning of potential problems ahead when the imply_fault_rows command is
executed.
USER RESPONSE:
As stated in the message text, the recommended action is to specify the coremodules
keyword on the imply_fault_rows command to match the information in the PGT
Module List. Alternatively, you could add the ET_CORE=PG property to the netlist and re-
import the circuit.
WARNING (TPO-780): Block blockname, has the ET_CORE=PG netlist property,\n but it
is not defined in the PGT Module List file as a PGT module. The ET_CORE=PG property on
this block will be ignored in building the testmode, but it will cause trouble for the
imply_fault_rows command, unless overridden by the coremodules keyword.
EXPLANATION:
The ET_CORE=PG property is intended for the imply_fault_rows command. It has
no effect upon how the testmode is built. For building the testmode, the information about
the partial-good matrix is supplied by the PGT Module List input file. This message is an
early warning of potential problems ahead when the imply_fault_rows command is
executed.
USER RESPONSE:
As stated in the message text, the recommended action is to specify the coremodules
keyword on the imply_fault_rows command to match the information in the PGT
Module List. Alternatively, you could remove the ET_CORE=PG property from the netlist
and re-run.

WARNING (TPO-801): Unrecognized statement in test plan file filename. The statement
is
textstr. This statement was ignored.
EXPLANATION:
The program could not parse the statement from the test plan file.
USER RESPONSE:

TPO - Messages
Make sure the file name is correct. If it is the correct file, look at the context of this
statement within the file. Perhaps the statement is out of order or there is a missing
section header. Check the punctuation and the spelling of the keywords on the
statement to make sure they are correct. After you diagnose the problem, edit the test
plan file and rerun the job.
WARNING (TPO-802): Instance blockname is associated with two different PFILEs:

PFILE filename1 was identified on entityname1. PFILE filename2 was earlier
associated with entityname2. filename2 will be used.
EXPLANATION:
The TB_OPCG_PFILE property appeared multiple times within the named instance
block. The program does not know which programming file (PFILE) to use for registers
defined within this instance. The first one found, which is the second one listed in the
message, is the one that will be used.
USER RESPONSE:
Make sure there is not a TB_OPCG_INSTANCE property missing. Instances may reside
inside other instances, and when this happens, all registers below (within) the lower-level
instance will be grouped together and described by a PFILE identified within this lower-
level instance, while all registers and PFILE properties outside the lower-level instance,
but inside the higher-level instance, will be grouped together to form a distinct OPCG
item (PLL or clock domain). If it is not a case of a missing TB_OPCG_INSTANCE property,
then it is most likely one of the TB_OPCG_PFILE properties is misplaced. Correct the
properties, re-import the circuit, and rerun the job.
ERROR (TPO-803): OPCGPGM statement in test step stepname of the test plan file
contains an unrecognized block name: blockname. No output files will be produced.
EXPLANATION:
The identified block name was used in the test plan, but no such block was found in the
circuit. The OPCGPGM statement can not be processed.
USER RESPONSE:
Check the spelling of the block name. Edit the test plan file by correcting this OPCGPGM
statement, and rerun the job.
ERROR (TPO-804): Cannot identify register regname in block blockname, referenced in

an OPCGPGM statement in test step stepname of the test plan file. No output files will be
produced.
EXPLANATION:

TPO - Messages
An OPCGPGM statement in the test plan file refers to a register and a block that is
supposed to contain this register, but it does not. Both the block name and the register
name were recognized, but there is no such register inside the named block, so the
register can not be identified.
USER RESPONSE:
There are four possible causes for this problem: (1) The wrong block is named in the
OPCGPGM statement; (2) The wrong register is named in the OPCGPGM statement; (3)
The OPCGPGM statement is meaningless and should be deleted; or (4) There are missing
TB_OPCG_REGNAME properties in the net list. If it is missing net list properties, add them
to net list, re-import the circuit, and rerun the job. Otherwise, edit the test plan file and
rerun the job.
WARNING (TPO-805): Block blockname, referenced in an OPCGPGM statment in test step

stepname, has no TB_OPCG_INSTANCE property, so it can not contain an OPCG register.
This OPCGPGM statement is ignored.
EXPLANATION:
The named block appeared in an OPCGPGM statement in the test plan, but this is not the
block identified via the TB_OPCG_INSTANCE property that is defined as the containing
entity for the PLL or clock domain registers.
USER RESPONSE:
Check the spelling of the block name. Scan the output log for references to the named
register which will identify the containing block by name. Edit the test plan file and specify
the correct block name, then rerun the job.
WARNING (TPO-806): An OPCGPGM statment in test step stepname refers to register

regname in block blockname1, but this register could not be identified. A register with the
same name was found in block blockname2 which has the TB_OPCG_INSTANCE property.
This OPCGPGM statement is ignored.
EXPLANATION:
The first-named block appeared in an OPCGPGM statement in the test plan, but this is not
the block identified via the TB_OPCG_INSTANCE property that is defined as the
containing entity for the PLL or clock domain registers. The message is suggesting that
a different block, the second-named block in the message, may be the one that was
intended. The program does not presume to substitute the suggested block, however.
Instead, the OPCGPGM statement is ignored.
USER RESPONSE:

TPO - Messages
Verify that the suggested block, second-named in the message, is the correct one. If it
is not, scan the output log for other references to the named register which may identify
the containing block by name. Edit the test plan file and specify the correct block name,
then rerun the job.
WARNING (TPO-807): Unable to parse the frequency specification in the following CLKIN
statement in test step stepname textstr. This CLKIN statement is ignored.
EXPLANATION:
Either the frequency is not expressed as a decimal number, or the frequency units are
not recognized. The frequency units must be either kHz, MHz or GHz.
USER RESPONSE:
Make sure the frequency is expressed as a decimal number. Check for proper use of the
decimal point and any commas that may have been inserted in the number for readability.
If units were specified make sure the units are expressed as kHz, MHz, or GHz. Edit the
test plan and rerun the job.
ERROR (TPO-808): Could not find OSC pin pinname referenced in the test step
stepname statement CLKIN=textstr The run will stop.
EXPLANATION:
The named pin was referenced in the printed CLKIN statement, but this pin can not be
found in the circuit or the pin does not have the OSC test function.
USER RESPONSE:
Check the spelling. Verify that the correct pin is being identified. Make sure the pin has
a +/-OSC test function pin attribute. Then edit the test plan file by specifying the correct
pin name and rerun the job.
WARNING (TPO-809): Unable to parse the frequency specification in the following CLKIN
statement in test step stepname. textstr This CLKIN statement is ignored.
EXPLANATION:
The frequency units are not recognized. The frequency units must be either kHz, MHz
or GHz.
USER RESPONSE:
If units were specified make sure the units are expressed as kHz, MHz, or GHz. If there
is some other text besides frequency units following the number, remove it. Edit the test
plan and rerun the job.

TPO - Messages
WARNING (TPO-810): The following OPCGPGM statement in Test Step stepname of the
test plan refers to an undefined operation.OPCGPGM=textstr. This OPCGPGM statement
is ignored.
EXPLANATION:
The operation field of the listed OPCGPGM statement appears to be incorrect. There is no
such operation defined in the programming file (PFILE) for this register. This statement
will not be used.
USER RESPONSE:
Verify that the correct register name was used. If so, then the operation name is indeed
incorrect, and must be changed. It is possible that the operation name is correct, and
the wrong register name was specified. More unlikely, perhaps, but it is also possible that
the wrong block name was specified, and that some other entity contains the specified
register with the specified operation. After diagnosing the problem, edit the test plan file
and rerun the job.
WARNING (TPO-811): The following OPCGPGM statement appears to be duplicated in Test

Step stepname of the test plan file. OPCGPGM=textstr
EXPLANATION:
The register identified in the printed test plan statement was referenced in a previous
OPCGPGM statement within the same test step, with the same operation specified. This
statement appears to be a duplicate.
USER RESPONSE:
Make sure that a different register or a different operation (or a different block name) was
not intended. If this statement truly is a duplicate, then this message can be ignored.
Otherwise, edit the test plan to correct this statement and rerun the job.
WARNING (TPO-812): Conflicting OPCGPGM statements found in Test Step stepname of

the test plan file. OPCGPGM=blockname,regname,opname OPCGPGM=textstr.
The same register can not use two different operations in the same test plan step. Operation
opname will be used.
EXPLANATION:
The register identified in the printed test plan statement was referenced in a previous
OPCGPGM statement within the same test step, with a different operation specified. The
operation specified on the first OPCGPGM statement for this register will be used. If one
of these statements was intended to specify a different register, then the results will be
wrong.
USER RESPONSE:

TPO - Messages
Decide which of the two statements is the correct one for this register. Then decide which
register was intended to be specified on the other statement, or if the other statement
should be deleted. Edit the test plan file and rerun the job.
WARNING (TPO-813): An unrecognized field was found in an OPCGPGM statement in test

step stepname . The complete statement is textstr1 This statement will be ignored.
EXPLANATION:
The fourth comma-separated field in this OPCGPGM statement should be null or contain
a time offset in the format OFFSET=integer. The field was non- blank, but it could not
be parsed. The entire statement will be ignored.
USER RESPONSE:
Decide if an offset needs to be specified for this entity, and edit the test plan file by either
eliminating this field or specifying an integer as shown above.
ERROR (TPO-814): Invalid time value found on the following statement in Test Step
stepname of the test plan file. STIMGO = textstr No output files will be produced.
EXPLANATION:
The time value following the pin name should be a real number, optionally followed by
time units. It contains either some non-decimal characters, an extra period, or an
unrecognized time unit.
USER RESPONSE:
Edit the test plan file to make this statement containa a real number with valid time units
and rerun the job.
ERROR (TPO-815): Invalid STIMGO statement in Test Step stepname of the test plan file.
STIMGO = textstr. This statement will be ignored.
EXPLANATION:
This STIMGO statement did not specify ON or OFF in the field immediately following the
STIMGO keyword.
USER RESPONSE:
Add the keyword ON or OFF to the statement, immediately following the STIMGO keyword
(with one or more intervening blanks, of course).
After editing the test plan file, rerun the job.
ERROR (TPO-816): Unknown pin pinname referenced in STIMGO statement in Test Step
stepname of the test plan file. STIMGO = textstr This pin will be ignored.

TPO - Messages
EXPLANATION:
The STIMGO statement references one or more primary inputs by pin name. The named
pin could not be found. Processing will proceed and this unidentified pin name will be
ignored. If the "unknown pin" looks like a list, then you probably are using the wrong
delimiter to separate them. The pins should be separated by commas, with white space
allowed next to each comma.
USER RESPONSE:
Determine what pin was intended, and correct the statement. After editing the test plan
file, rerun the job.
ERROR (TPO-817): Pin pinname referenced in STIMGO statement in Test Step stepname
of the test plan file is not an input pin. STIMGO = textstr This pin will be ignored.
EXPLANATION:
The STIMGO statement references one or more primary inputs by pin name. The named
pin is not a primary input. Processing will proceed and this pin name will be ignored.
USER RESPONSE:
See if this is a spelling error or if a different pin (some primary input) was intended. If the
named internal pin is the one intended, then you will have to substitute some primary
input that controls this internal signal and use that instead. Edit the test plan file and rerun
the job.
ERROR (TPO-818): Pin pinname referenced in STIMGO statement in Test Step

stepname of the test plan file does not have the GO test function. STIMGO = textstr This
pin will be ignored. The testmode is modename
EXPLANATION:
The STIMGO statement references one or more primary inputs by pin name. These pins
should have the +/-GO test function. The named pin is a primary input, but it does not
have the requisite GO test function. Processing will proceed and this pin name will be
ignored.
USER RESPONSE:
Make sure the correct pin was specified on the STIMGO statement. If it is the correct pin,
change the mode definition file or the assign file to add the GO test function to the pin.
If it is not the correct pin, change the test plan file to refer to the correct pin. After editing
the appropriate file, rerun the job.

TPO - Messages
ERROR (TPO-819): Test step integer1 and test step integer2 in test plan file
filename both have the same name, stepname. Correct the test plan by giving each test
step a unique name.
EXPLANATION:
Two test steps in the named test plan file have the same name. The step name is used
as a qualifier in the constraints file names, commands, sequence names, and
experiments that will be generated. The name of each test step must be unique.
USER RESPONSE:
Edit the test plan file and give each test step a unique name. Then rerun the job.
ERROR (TPO-820): Test step stepname has conflicting offsets for registers
blockname1 and blockname2. The run will stop. Correct the test plan by making all the
offsets the same for registers in the same entity.
EXPLANATION:
The named test step has two OPCGPGM statements that refer to the same block (entity),
but have different timing offsets specified. The timing offset must be the same for all
registers in the same block. The run will stop.
USER RESPONSE:
Edit the test plan file and make sure all offsets are consistent for each block. Then rerun
the job.
ERROR (TPO-821): Invalid time value time1 found on the following statement in Test Step
stepname of the test plan file. textstr The time is less than the previous time of time2.
No output files will be produced.
EXPLANATION:
The optional time field on the STIMGO statement specifies the time when the GO signal
is to be switched. The STIMGO statements must appear in chronological order, but this
STIMGO statement specifies a time less than the current time as determined by a
previous STIMGO statement. (Or it is negative.)
USER RESPONSE:
Determine the correct timings for switching each of the GO signals, and specify them in
the correct (ascending) order in the testplan. Rerun the job.
ERROR (TPO-822): Missing PFILE name for the register bit defined by a
TB_OPCG_REGNAME property on entityname. Output files will not be produced. Add a
TB_OPCG_PFILE property to entityname and rebuild the model.

TPO - Messages
EXPLANATION:
The programming file (PFILE) is vital for processing on-product clock generation (OPCG)
register definitions. The block containing the named pin, block, or net on which the
register bit was defined also contains other register bits which are associated with
multiple PFILEs. The program is not able to infer which PFILE should be used to define
the register bit defined on the named pin, block, or net.
USER RESPONSE:
Add a TB_OPCG_PFILE property to the same source statement (the pin, block, or net
named in the message). Then resume processing starting with the build_model
command.
ERROR (TPO-823): Missing PFILE name for registers contained in block entityname.
Output files will not be produced. Add a TB_OPCG_PFILE property to entityname or to a
pin, block, or net contained within it, and rebuild the model.
EXPLANATION:
The programming file (PFILE) is vital for processing on-product clock generation (OPCG)
register definitions. The named block contains some register definitions (via the
TB_OPCG_REGNAME property), but there is no TB_OPCG_PFILE property associated
with any of them.
USER RESPONSE:
Add a TB_OPCG_PFILE property to one or more of the source statements that have the
TB_OPCG_REGNAME property. Then resume processing starting with the build_model
command.
ERROR (TPO-824): Block blockname is referenced in Test Step stepname of the test
plan, but there is no programming file (PFILE) associated with this block. The test plan
statement is: textstr Specify the correct block name in the test plan and rerun.
EXPLANATION:
As suggested by the message, the most probable cause is the wrong block name
specified in the OPCGPGM statement. Check for the wrong block name or a typographical
error. If the correct block name is specified, then there is a missing TB_OPCG_PFILE
property in the model source.
USER RESPONSE:
Edit the test plan file to correct the block name, or add a TB_OPCG_PFILE property to
this block in the model source. In the latter case, processing must resume with the
build_model command.

TPO - Messages
ERROR (TPO-825): The following test plan statement in test step stepname does not
include a programming file (PFILE) name and it refers to block blockname which has more
than one associated PFILE. textstr Specify the PFILE name in the test plan and rerun.
EXPLANATION:
Register operations are identified in the test plan OPCGPGM statement by four comma-
separated fields:
<blockname>,<PFILEname>,<registername>,<operation> The PFILEname
field was missing, and the specified block has more than one PFILE associated with it
from the model properties, so the PFILE name can not be inferred. In the case at hand,
where the block has multiple PFILEs, <PFILEname> must be specified. Possibly some
other field is missing, but the program assumes the missing field is <PFILEname>
because this is the only optional field.
USER RESPONSE:
Edit the test plan file and include all four fields for this OPCGPGM statement, as described
above in the explanation. Then rerun.
ERROR (TPO-828): Test step stepname specified the following invalid combination of
keywords for the commandname: textstr The run will stop.
EXPLANATION:
The keyword values specified by the testplan TGKEYWORD statement, when used in
combination with the default keyword values (including those specified by the
build_opcg_testmode command), are invalid for the test generation command
identified in the message text. It is not clear which specific keyword, keywords, or
keyword combination, is invalid.
USER RESPONSE:
Look carefully at the test generation keywords specified in the test plan, along with the
default settings produced by the build_opcg_testmode command (you may need to
consult the test generation command produced by another build_opcg_testmode
run). Consult the documentation or on-line help text for valid settings of each of the
keywords. Edit the test plan file and rerun the job.
ERROR (TPO-829): There is no STIMGO statement for test step stepname. The run will
stop. Add the STIMGO statement to the test plan file and rerun the job.
EXPLANATION:
The GO signal stim must be specified in the test plan with the use of a STIMGO
statement.
USER RESPONSE:

TPO - Messages
Edit the test plan file and rerun the job.
INFO (TPO-830): STIMGO OFF statement found in test step stepname is ignored. The
amount of time for GO signals to be kept active is calculated from information contained in
the programming file (PFILE). Remove the STIMGO OFF statement from the test plan file in
the future to avoid possible confusion.
EXPLANATION:
The STIMGO OFF statement is no longer being used. As explained in the message text,
the duration of the GO signal is calculated by the program, and the placement in the test
sequence of the turning off of the GO signal is done automatically.
USER RESPONSE:
Remove STIMGO OFF statements from your test plan files to eliminate future
appearances of this message.
ERROR (TPO-831): Operation opname for register regname in programming file (PFILE)
pfilename specifies a data vector, textstr, of integer1 bits, but register regname
has integer2 bit positions. The run will stop. Fix the PFILE or the netlist and rerun the
job.
EXPLANATION:
The register named in this message has a length, as determined by the netlist properties,
that is different from the length of the register as defined in the programming file (PFILE).
USER RESPONSE:
Determine whether the PFILE is correct or the netlist properties are correct in the number
of bits in this register. Then correct the appropriate file (the PFILE or the netlist) and
rerun. If it is the netlist that must be corrected, then the netlist must be re-imported.
ERROR (TPO-832): The highest frequency specified, decimal1 mHz, is faster than the
tester can support. The maximum supported frequency is decimal2 mHz.
EXPLANATION:
The tester is not capable of supplying an oscillator frequency as high as is being
requested. The program does not know how to reconcile the frequencies to allow them
to run on the tester, so it will not change them from their specifications in the test plan
file. The tests probably will fail in some later processing step, perhaps in the tester
environment.
USER RESPONSE:

TPO - Messages
Find out if the specified frequencies really will work on the tester. If so, you may ignore
this message. If not, then edit the test plan file to specify valid oscillator frequencies and
rerun the job.
ERROR (TPO-833): The linehold file textstr specified in test step stepname can not
be found. Edit the test plan file filename to specify the correct linehold file and rerurn the
job.
EXPLANATION:
The indicated file could not be opened. This message is assuming therefore that the file
does not exist.
USER RESPONSE:
If the file does not exist, either the name is specified wrong in the test plan statement or
it is in the wrong directory. If the file name as given in the test plan statement begins with
a slash ("/"), then it is assumed to be the full path name. In this case, look for a spelling
error or a missing file. If the file name as given in the test plan statement does not begin
with a slash character, then it is assumed to be relative to the location of the test plan file.
The full path where the program expected to find the linehold file is printed in the
message. Verify the existence of the linehold file and specify it correctly in the test plan
file. If its location is not in a subdirectory where the test plan file is located, then the
specification must include the full path, starting with the slash character.
WARNING (TPO-834): The file name is missing on the PATHFILE statement in test step
stepname. Edit the create_path_delay_tests command for this experiment before
running the command.
EXPLANATION:
A PATHFILE statement was found in the test plan file, indicating that the experiment is
for generating path delay tests. The PATHFILE statement did not specify the name of a
path file. A create_path_delay_tests command will be composed for this
experiment, but the command will not include the pathfile keyword.
USER RESPONSE:
Determine whether the path file input was intended for this experiment. If not, then no
action is necessary. If the path file input is intended to be used, then add the pathfile
keyword with the path file name to the create_path_delay_tests command before
running the command.
ERROR (TPO-835): Test step stepname in test plan file filename specifies a pathfile
name, but the pathfiledir keyword was not specified. Rerun the command with a
complete directory name specified on the pathfiledir keyword.

TPO - Messages
EXPLANATION:
When the PATHFILE statement is used in the test plan, the pathfiledir keyword is
required on the build_opcg_testmode command. The file name is specified in the
test plan, and the directory name is specified on the command line via the pathfiledir
keyword. The file name is meaningless without the directory name.
USER RESPONSE:
This is most likely a command line error where the pathfiledir keyword was
inadvertantly omitted. Rerun the build_opcg_testmode command with the
pathfiledir keyword specified. On the other hand, if the path file was not to have
been specified in the test plan, edit the test plan file and rerun.
ERROR (TPO-836): Test step stepname in test plan file filename contains a SET
statement that can not be parsed. The statement is textstr. Make sure the statement
includes a variable name and either an INCLUDE or EXCLUDE keyword, or both. Edit the file
and rerun the job.
EXPLANATION:
The syntax of the SET statement is SET <variablename> <keywords> where
<variablename> is any character string with no embedded blanks, and <keywords>
includes the INCLUDE(<string>) keyword and optionally the EXCLUDE(<string>)
keyword. This message would be produced if either the <variablename> field and
the <keywords> field are missing, or there is no space separating the two fields.
USER RESPONSE:
Correct the syntax and rerun the job. Make sure the entire statement is on a single line,
and both the variable name and the INCLUDE(<string>) keyword are present.
statement but its identifier1 keyword value can not be parsed. The statement is
textstr Make sure the identifier2 keyword value is a non-blank comma-separated
list enclosed in matching parentheses. Edit the file and rerun the job.
EXPLANATION:
The syntax of the SET statement is SET <variablename> INCLUDE(<string1>)
[EXCLUDE(<string2>)] Either <string1> or <string2> could not be parsed,
depending on whether the message refers to the INCLUDE keyword or the EXCLUDE
keyword. The format of both <string1> and <string2> is the same; a comma-
separated list of non-blank tokens (each token can not include a space character). The
most probable cause of the error is missing parentheses. The entire list for each keyword
must be enclosed in matching parentheses ().

TPO - Messages
USER RESPONSE:
Correct the syntax and rerun the job. Make sure the value of the INCLUDE or EXCLUDE
keyword referred to in the message is enclosed in matching parentheses.
statement but no blocks were selected by its INCLUDE keyword. The statement is textstr
Edit the file and rerun the job.
EXPLANATION:
There is no purpose in defining a symbolic variable that does not refer to anything, so the
run stops when this occurs. The INCLUDE keyword specifies a comma-separated list of
tokens, and this message indicates that none of the tokens matched any of the macro
usage blocks defined in the netlist with the INSTANCE property.
USER RESPONSE:
Check that no typographical errors exist in the tokens specified by the INCLUDE keyword.
Make sure the wildcard character (*) is used properly. For example, if you are looking for
all INSTANCEs that start with the character string ABC, you need to have a wildcard
character at the end (ABC*). Similarly, if you intend to include all INSTANCEs that have
the embedded string ABC, you need both a starting and ending wildcard (*ABC*).
statement but it has no INCLUDE keyword. The statement is textstr. Remove the SET
statement or add an INCLUDE keyword with some blocks selected. Then rerun the job.
EXPLANATION:
run stops when this occurs. Without an INCLUDE keyword, this SET statement can not
refer to any blocks.
USER RESPONSE:
If there was no intention of including any blocks in this symbolic variable definition,
remove the SET statement. Otherwise, add the INCLUDE keyword and specify one or
more comma-separated character strings to be used to select the desired blocks. Then
rerun the job.
ERROR (TPO-840): Test step stepname in test plan file filename contains a SET statement
with an EXCLUDE keyword, but no blocks were selected by the EXCLUDE keyword value. The
statement is textstr. Edit the file and rerun the job.
EXPLANATION:

TPO - Messages
The EXCLUDE keyword specifies a comma-separated list of tokens, and this message
indicates that none of the tokens matched any of the macro usage blocks defined in the
netlist with the INSTANCE property. Therefore, the EXCLUDE keyword has no effect in
this SET statement.
USER RESPONSE:
Check that no typographical errors exist in the tokens specified by the EXCLUDE
keyword. Make sure the wildcard character (*) is used properly. For example, if you
wanted to exclude all INSTANCEs that start with the character string ABC, you need to
have a wildcard character at the end (ABC*). Similarly, if you intend to exclude all
INSTANCEs that have the embedded string ABC, you need both a starting and ending
wildcard (*ABC*).
ERROR (TPO-841): Test step stepname in test plan file filename refers to operation
opname. This is a special-purpose operation which is not usable in the test plan. The
statement is textstr. Edit the file and rerun the job.
EXPLANATION:
The TSVXLH operation is a reserved operation used for checking purposes, but not
available for use in the test plan. The test plan refers to this operation in the statement
printed with this message. The TSVXLH operation is expected to specify X states for
some register bits, but there is no way to load X states into the memory elements.
USER RESPONSE:
Verify that the TSVXLH operation as defined in the programming file (PFILE) specifies X
for some register bit position(s). If it does not, then the problem may be that the wrong
name was used for the operation. In this case, edit the PFILE and the test plan to
rename this operation. Then rerun the job. If the operation specifies X for some bit
positions, then the wrong operation is being specified in the test plan file. Determine the
correct operation, edit the test plan, and rerun the job. If there really are don't care states
for some register bits, it is necessary to arbitrarily set them to 0 or 1 by defining some
other operation.
ERROR (TPO-844): Can not identify register regname in block blockname referenced in
an OPCGPGM statement in test step stepname of the test plan file. No output files will be
produced.
EXPLANATION:
An OPCGPGM statement in the test plan file refers to a register and a block that is
supposed to contain this register, but it does not. Both the block name and the register
name were recognized, but there is no such register inside the named block, so the
register can not be identified.

TPO - Messages
USER RESPONSE:
There are four possible causes for this problem:
a. The wrong block is named in the OPCGPGM statement
b. The wrong register is named in the OPCGPGM statement
c. (3) The OPCGPGM statement is meaningless and should be deleted, or
d. There are missing TB_INT_DOMAINS_REGNAME properties in the net list. If it is

missing net list properties, add them to net list, re-import the circuit, and rerun the
job.
Otherwise, edit the test plan file and rerun the job.
WARNING (TPO-845): Block blockname referenced in an OPCGPGM statment in test step

stepname, has no TB_INTERNAL_DOMAINS_INSTANCE property, so it can not contain an
OPCG register. This OPCGPGM statement is ignored.
EXPLANATION:
The named block appeared in an OPCGPGM statement in the test plan, but this is not the
block identified via the TB_INTERNAL_DOMAINS_INSTANCE property that is defined as
the containing entity for the PLL or clock domain registers.
USER RESPONSE:
Check the spelling of the block name. Scan the output log for references to the named
register which will identify the containing block by name. Edit the test plan file and specify
the correct block name, then rerun the job.
WARNING (TPO-846): An OPCGPGM statment in test step stepname refers to register

regname in block blockname1, but this register could not be identified. A register with the
same name was found in block blockname2 which has the
TB_INTERNAL_DOMAINS_INSTANCE property. This OPCGPGM statement is ignored.
EXPLANATION:
The first-named block appeared in an OPCGPGM statement in the test plan, but this is not
the block identified via the TB_INTERNAL_DOMAINS_INSTANCE property that is defined
as the containing entity for the PLL or clock domain registers. The message is
suggesting that a different block, the second-named block in the message, may be the
one that was intended. The program does not presume to substitute the suggested
block, however. Instead, the OPCGPGM statement is ignored.
USER RESPONSE:

TPO - Messages
Verify that the suggested block, second-named in the message, is the correct one. If it
is not, scan the output log for other references to the named register which may identify
the containing block by name. Edit the test plan file and specify the correct block name,
then rerun the job.
ERROR (TPO-850): In test step stepname net netname is a cutpoint attached textstr
to PPI ppiname with a test function of testfunction. But with all the registers loaded for
this test step, this net is at the wrong value (logicvalue). The test data is almost certain
to fail. Make sure the PPI's test function is correct, or change the programming of the registers
for this test step.
EXPLANATION:
This check is to make sure that the cutpoints are initialized properly according to the test
function specified on the associated pseudo primary input (PPI). The circuit is placed in
the TC and Clocks Off state, and the register values specified for the test step are
applied. A simulation is performed, and the resulting state on each cutpoint is checked
for consistency with its associated PPI test function. An inconsistency was detected for
this cutpoint net, indicating that after the OPCG registers are loaded, the cutpoint is not
at the state prescribed by the PPI test function. This is almost certain to cause the tests
to fail.
USER RESPONSE:
Make sure the test function was specified correctly, and that the correct cutpoint net was
identified. If inversion was specified between the PPI and the cutpoint, be sure to
account for that. If these are correct, then the programming of the control registers may
be incorrect. Verify that the operations are defined correctly in the programming file
(PFILE) and that the correct operation(s) is/are specified in the test plan. If all these
are correct, then it is possible that the OPCG registers do not completely control the
cutpoint. In that case, additional register definitions or test function assignments on the
primary inputs may be necessary. If the cutpoint is controlled by a state machine that
can not be described by OPCG registers, the tests may work, but extreme care must be
exercised, and the tests should be simulated prior to applying them to hardware.
ERROR (TPO-862): Missing PFILE name for the register bit defined by a
TB_INTERNAL_DOMAINS_REGNAME property on entityname. Output files will not be
produced. Add a TB_INTERNAL_DOMAINS_PFILE property to entityname and rebuild the
model.
EXPLANATION:
The programming file (PFILE) is vital for processing on-product clock generation
(OPCG) register definitions. The block containing the named pin, block, or net on which
the register bit was defined also contains other register bits which are associated with

TPO - Messages
multiple PFILEs. The program is not able to infer which PFILE should be used to define
the register bit defined on the named pin, block, or net.
USER RESPONSE:
Add a TB_INTERNAL_DOMAINS_PFILE property to the same source statement (the
pin, block, or net named in the message). Then resume processing starting with the
ERROR (TPO-863): Missing PFILE name for registers contained in block entityname.
Output files will not be produced. Add a TB_INTERNAL_DOMAINS_PFILE property to
entityname or to a pin, block, or net contained within it, and rebuild the model.
EXPLANATION:
The programming file (PFILE) is vital for processing on-product clock generation
(OPCG) register definitions. The named block contains some register definitions (via the
TB_INTERNAL_DOMAINS_REGNAME property), but there is no
TB_INTERNAL_DOMAINS_PFILE property associated with any of them.
USER RESPONSE:
Add a TB_INTERNAL_DOMAINS_PFILE property to one or more of the
sourcestatements that have the TB_INTERNAL_DOMAINS_REGNAME property. Then
resume processing starting with the build_model command.
ERROR (TPO-864): Block blockname is referenced in Test Step stepname of the test
plan, but there is no programming file (PFILE) associated with this block. The test plan
statement is: textstr. Specify the correct block name in the test plan and rerun.
EXPLANATION:
As suggested by the message, the most probable cause is the wrong block name
specified in the OPCGPGM statement. Check for the wrong block name or a typographical
error. If the correct block name is specified, then there is a missing
TB_INT_DOMAINS_PFILE property in the model source.
USER RESPONSE:
Edit the test plan file to correct the block name, or add a TB_INT_DOMAINS_PFILE
property to this block in the model source. In the latter case, processing must resume
with the build_model command.
statement with extraneous information that could not be parsed. The statement is textstr.
Correct the statement and rerun the job.
EXPLANATION:

TPO - Messages
There was some information on the SET statement that is not recognized. The syntax of
the SET statement is SET <variablename> INCLUDE(<string1>)
[EXCLUDE(<string2>)]. Any other information outside a comment field would cause
this message. The message would be printed if <variablename> contained some
embedded whitespace.
USER RESPONSE:
Look for a misspelled INCLUDE or EXCLUDE keyword. Look for a missing comment
character (either # or //). Look for whitespace in the <variablename> field. Edit the
file and rerun the job.
statement that tries to define a symbolic variable with the same name as a usage block in the
circuit. The statement is textstr. To avoid confusion, use a name that is unique. Correct
the statement and rerun the job.
EXPLANATION:
The name following the SET keyword is the name of an INSTANCE block in the circuit.
This can not be used as a symbolic name for a list of blocks because references to this
name in OPCGPGM statements would be ambiguous.
USER RESPONSE:
Use a different name that is unique for the symbolic variable. Edit the file and rerun the
job.
ERROR (TPO-872): Test step stepname in test plan file filename contains multiple
FOREACH statements. The following statement is considered redundant and is being ignored
: textstr. Delete all but one of the FOREACH statements in this test step and rerun the job.
EXPLANATION:
The capability exists to replicate a test step section in the testplan and create from it
several experiments which vary based on a single symbolic variable. The capability does
not exist for anything more sophisticated, such as creating a multi-dimensional array of
experiments based on more than one symbolic variable. Therefore, only a single
FOREACH statement is allowed in a test step.
USER RESPONSE:
Decide on a single symbolic variable to control the variation between the experiments
defined by this test step. Then delete the other FOREACH statements. Rerun the job after
editing the testplan file.

TPO - Messages
ERROR (TPO-873): Test step stepname in test plan file filename contains a FOREACH
statement which references an undefined symbol, identifier. Correct the symbolic name
and rerun the job.
EXPLANATION:
The symbol specified in the FOREACH statement must be a symbolic variable name that
was defined in a preceding SET statement. This symbol is not recognized as such. It may
be a spelling error, or a missing SET statement.
USER RESPONSE:
Make sure the symbol is spelled the same on the FOREACH statement and the SET
statement that defines it. Make sure the SET statement precedes the FOREACH
statement, and is not inside some other test step. Edit the test plan file and rerun the job.
INFO (TPO-874): scope symbolic variable identifier is defined in test step

stepname of the test plan to represent the following INSTANCE list : blocknamelist
EXPLANATION:
This is an informational message that tells the result of the selection process using the
INCLUDE and EXCLUDE tokens to define the named symbolic variable. The message
reports the scope of the variable (global or local to the test step) and denotes by way of
the word "defines" or "redefines" whether this is a new variable being defined or a
previously used variable taking on a new definition. This message may be useful in cases
where the specification is complex, involving wildcards, lists, previously defined symbolic
variables, and the EXCLUDE keyword. Also, the message could be very valuable if it
states that the symbolic variable is being redefined, and the intention was to use different
symbols.
USER RESPONSE:
Verify that the result is what was intended.
INFO (TPO-875): Replicating test step stepname for each member of the symbolic
variable identifier.
EXPLANATION:
This is an informational message that serves as a reminder that the test step contained
a FOREACH statement that causes multiple experiments to be created.
USER RESPONSE:
No response is needed.

TPO - Messages
ERROR (TPO-877): A SET statement in test step stepname of the test plan defines
symbolic variable identifier but all candidate blocks were discarded by the EXCLUDE
value. The statement is textstr. Edit the file and rerun the job.
EXPLANATION:
run stops when this occurs. In this case, the EXCLUDE keyword removed all the items
from the list that would have been selected.
USER RESPONSE:
Examine the INCLUDE and EXCLUDE keywords on the SET statement and make sure
they were both specified properly. The problem may be that EXCLUDE selected too many
blocks, and some of them should have been kept on the list, or that the INCLUDE
keyword omitted some blocks that should have been selected and kept by the EXCLUDE
keyword. Change the INCLUDE and/or EXCLUDE keyword values and rerun the job.
WARNING (TPO-878): Test Step stepname contains multiple TGCOMMAND statements.

textstr1 is replaced by textstr2.
EXPLANATION:
The identified test step contains two or more TGCOMMAND statements. Information from
multiple TGCOMMAND statements within a test step are not combined; only one
TGCOMMAND statement is used, and it must be complete. When multiple TGCOMMAND
statements appear in a test step, the second through last cause this message to be
printed, and only the last one is used.
USER RESPONSE:
If the last TGCOMMAND statement appearing within this test step is the correct one, then
you may proceed and ignore this message. Otherwise, remove all the incorrect ones, and
rerun the job.
WARNING (TPO-879): Test Step stepname contains a TGCOMMAND statement that

specifies an unrecognized command, textstr1. Correct the command name and rerun the
job.
EXPLANATION:
The identified test generator command is not in the list of valid commands that can be
processed by this command.
USER RESPONSE:
Make sure you spelled the command correctly. Correct the command name in the
testplan file and rerun the job. If it is a valid command and is spelled correctly, then you

TPO - Messages
will have to consult with your customer service representative (see Contacting
Customer Service on page 23) to see if it is possible to have it added to the list.
statement but no blocks were selected by its INCLUDEPGM keyword. The statement is
textstr. Edit the file and rerun the job.
EXPLANATION:
run stops when this occurs. The INCLUDEPGM keyword specifies a comma-separated list
of tokens, and this message indicates that none of the tokens matched any of the
programming files (PFILEs) used by any of the OPCG macros defined in the netlist.
USER RESPONSE:
Check that no typographical errors exist in the tokens specified by the INCLUDEPGM
keyword. Make sure the wildcard character (*) is used properly. For example, if you are
looking for all PFILEs that start with the character string ABC, you need to have a
wildcard character at the end (ABC*). Similarly, if you intend to include all PFILEs that
have the embedded string ABC, you need both a starting and ending wildcard (*ABC*).
statement with an EXCLUDEPGM keyword, but no blocks were selected by the EXCLUDEPGM
keyword value. The statement is textstr. Edit the file and rerun the job.
EXPLANATION:
The EXCLUDEPGM keyword specifies a comma-separated list of tokens, and this
message indicates that none of the tokens matched any of the programming files
(PFILEs) used by any of the OPCG macros defined in the netlist. Therefore, the
EXCLUDEPGM keyword has no effect in this SET statement.
USER RESPONSE:
Check that no typographical errors exist in the tokens specified by the EXCLUDEPGM
keyword. Make sure the wildcard character (*) is used properly. For example, if you
wanted to exclude all PFILEs that start with the character string ABC, you need to have
a wildcard character at the end (ABC*). Similarly, if you intend to exclude all PFILEs that
have the embedded string ABC, you need both a starting and ending wildcard (*ABC*).
INFO (TPO-882): No test generation command was specified in test step stepname. Will
use textstr
EXPLANATION:

TPO - Messages
Either there was no TGCOMMAND statement in this step of the test plan file, or it was
syntactically incorrect, and was ignored. The default command printed in the message
will be used.
USER RESPONSE:
If the default command is correct, ignore the message. If you are not using the
TG_<testmodename>_<experimentname> output script, you can ignore the
message. Or you can edit the output script before using it. Otherwise, specify the correct
command on the TGCOMMAND statement in the test plan and rerun the job.
ERROR (TPO-883): OPCGPGM statement in test step stepname of the test plan file
filename contains an unrecognized field at the end of the statement: textstr No output
files will be produced.
EXPLANATION:
The unrecognized text printed in the message was found while looking for the
EVENTTIMING keyword (eventtiming=normalized|real). This keyword is
optional. As stated in the message, it should appear at the end of the OPCGPGM
statement separated by a comma from the rest of the statement.
USER RESPONSE:
Look for a misspelled keyword or a missing equal sign. Correct the statement and
rerun the job.
ERROR (TPO-884): The eventtiming keyword was specified with conflicting values in
test step stepname of test plan file filename for the domain textstr The run will stop.
EXPLANATION:
The EVENTTIMING keyword was specified on two or more OPCGPGM statements for
the same instance in the same test step. This is okay, as long as they are in agreement.
In this case they disagree.
USER RESPONSE:
Find all the OPCGPGM statements for this instance and this test step. Look for global
OPCGPGM statements (outside the boundaries of any test step) that refer to this
instance. Then decide which setting is desired for this instance, and change (or simply
remove) all those keywords for this instance and test step which are wrong.
ERROR (TPO-885): In test step stepname, there are conflicting CLKIN statements for pin
pinname. One CLKIN statement specifies a frequency of frequency mHz and\n another
CLKIN statement specifies a frequency of frequency mHz The run will stop.
EXPLANATION:

TPO - Messages
Two CLKIN statements were found in the same test step of the test plan file for the same
pin, but with different frequencies specified. A pin cannot be producing/receiving two
different waveforms at the same time.
USER RESPONSE:
Determine the correct frequency for this pin, for this test step. Edit the test plan file and
specify only one CLKIN statement for this pin, using the correct frequency. Then rerun
the job.

ERROR (TPO-900): There are no primary inputs to this circuit.
EXPLANATION:
When identifying the oscillator inputs, a request for the input pins of the top-level block
returned an empty list. Processing will proceed with the assumption that there are no
oscillators.
USER RESPONSE:
Verify that there are indeed no input pins to the circuit. If there are input pins, this
message indicates a serious bug in the system. If there are no primary inputs, you are
likely to encounter other problems.
ERROR (TPO-901): PLL reset pin filename on block blockname could not be found.
This pin was referenced in a PLL_RESET statement in programming file filename.
EXPLANATION:
The named programming file (PFILE) contains a PLL_RESET statement that references
a pin name, but this pin can not be found on the block, identified by a
TB_OPCG_INSTANCE property, which contains the TB_OPCG_PFILE property that
points to this PFILE.
USER RESPONSE:
There are several possible causes for this problem, but the most likely cause is a wrong
pin name on the PLL_RESET statement in the PFILE. Other possibilities are the
TB_OPCG_INSTANCE property is misplaced, or the wrong PFILE was identified. Edit the
PFILE, or edit the net list to fix the bad TB_OPCG_INSTANCE or TB_OPCG_PFILE
property. If editing the net list, you must re-import the circuit. Then rerun the job.

TPO - Messages
WARNING (TPO-902): PLL oscillator output pin pinname on block blockname could not
be found. This pin was referenced in a PLL_OUT_OSC statement in programming file
filename.
EXPLANATION:
The named programming file (PFILE) contains a PLL_OUT_OSC statement that
references a pin name, but this pin can not be found on the block, identified by a
USER RESPONSE:
pin name on the PLL_OUT_OSC statement in the PFILE. Other possibilities are the
TB_OPCG_INSTANCE property is misplaced, or the wrong PFILE was identified. Edit the
PFILE, or edit the net list to fix the bad TB_OPCG_INSTANCE or TB_OPCG_PFILE
ERROR (TPO-903): Oscillator pindirection pin pinname on block blockname could not
be found. This pin was referenced in a textstr statement in programming file filename.
EXPLANATION:
The named programming file (PFILE) contains a statement that references a pin name,
but this pin can not be found on the block, identified by a TB_OPCG_INSTANCE property,
which contains the TB_OPCG_PFILE property that points to this PFILE.
USER RESPONSE:
pin name in the PFILE. Other possibilities are the TB_OPCG_INSTANCE property is
misplaced, or the wrong PFILE was identified. Edit the PFILE, or edit the net list to fix
the bad TB_OPCG_INSTANCE or TB_OPCG_PFILE property. If editing the net list, you
must re-import the circuit. Then rerun the job.
ERROR (TPO-904): PFILE filename used by PLL blockname has no PLL_OUT_OSC

defined.
EXPLANATION:
The output pin name is missing from the named programming file (PFILE). The definition
of the PLL will be incomplete.
USER RESPONSE:
Identify the oscillator outputs of the PLL this PFILE describes, and add the
PLL_OUT_OSC statement to the PFILE. After editing the PFILE, rerun the job.

TPO - Messages
ERROR (TPO-905): Pseudo primary input ppiname referenced in sequence seqname in

PFILE filename is not defined. The PPI name used in the sequence definition must be the
same as defined in the CUTPOINT and ASSIGN_PPI statements within the mode definition
section.
EXPLANATION:
The named sequence definition fragment in the named programming file (PFILE) refers
to a pseudo primary input (PPI) that is undefined. The PPI must be defined in the
START_MODE_DEFINITIONS{ section of the same PFILE, via theCUTPOINT statement.
USER RESPONSE:
Make sure the correct PPI name is used in both the sequence definition and the
CUTPOINT statement. If one of them is wrong, it is only a matter of correcting that
statement. Otherwise, there is a missing CUTPOINT statement which must be added to
the START_MODE_DEFINITIONS{ section of the PFILE. After making the necessary
edits to the PFILE, rerun the job.
ERROR (TPO-906): Multiple Time statements found within a dynamic pattern in sequence
seqname in PFILE filename. The earlier statements within this pattern will be ignored.
EXPLANATION:
The Time statement within a sequence definition tells when the following event(s) should
be applied within the test cycle. The relative timing of events within a dynamic pattern is
specified by a time keyword that is placed on each individual event, and is relative to the
start of the dynamic pattern. For example: Event Pulse_PPI
(timed_type=capture, time=40): "clk1PPI"=-; The Time statements
referred to in this message are placed between the events, and within a dynamic pattern,
they serve only to establish the beginning of the dynamic pattern. Only the last Time
statement within a dynamic pattern will be honored.
USER RESPONSE:
Remove the extra Time statements from the dynamic pattern by editing the
programming file (PFILE). Make sure the correct action was taken in this case, and if not,
rerun the job after completing the PFILE edit.
ERROR (TPO-907): Unsupported event found in sequence seqname in PFILE

filename.textstr1 textstr2 This event will be ignored.
EXPLANATION:
The named programming file (PFILE) was found to contain an unrecognized event within
the named sequence. This event will be dropped from the test sequence.
USER RESPONSE:

TPO - Messages
Replace this event with the intended event. It is likely a typographical error. After editing
ERROR (TPO-909): GO pin pinname on block blockname. could not be found. This pin
was referenced in programming file filename.
EXPLANATION:
The named programming file (PFILE) contains a STIMGO statement that references a
pin name, but this pin can not be found on the block, identified by a TB_OPCG_INSTANCE
property, which contains the TB_OPCG_PFILE property that points to this PFILE.
USER RESPONSE:
pin name in the PFILE. Other possibilities are the TB_OPCG_INSTANCE property is
misplaced, or the wrong PFILE was identified. Edit the PFILE, or edit the net list to fix
the bad TB_OPCG_INSTANCE or TB_OPCG_PFILE property. If editing the net list, you
must re-import the circuit. Then rerun the job.
ERROR (TPO-910): The input modeinit sequence specifies a different parent testmode
from the one specified by the parentmode keyword, modename1. The one found in the
sequence definition, modename2, will be used.
EXPLANATION:
A user-supplied mode initialization sequence was specified, but it specifies a different
parent testmode from what was specied on the parentmode keyword for this command.
The mode initialization sequence produced by this program will use the same parent
testmode that was specified in the original mode initialiation sequence. This may not
work because all the checking done by this program used the parent testmode specified
on the parentmode keyword.
USER RESPONSE:
Ignore this message at the peril of failure in subsequent processing, or, in the extreme,
miscompares in the final test generation results. If no subsequent test generation-related
processes produce serious errors, it is unlikely that miscompares would happen. The
recommended action is to decide which parent testmode is the correct one, then make
sure it is correctly specified in both the input mode initialization sequence and the
command keyword, and rerun the job.
ERROR (TPO-911): Domain output pin pinname on block blockname could not be
found. This pin was referenced in a DOMAIN_OUT_CLOCK statement in programming file
filename.
EXPLANATION:

TPO - Messages
The named programming file (PFILE) contains a DOMAIN_OUT_CLOCK statement that

references a pin name, but this pin can not be found on the block, identified by a
USER RESPONSE:
pin name on the DOMAIN_OUT_CLOCK statement in the PFILE. Other possibilities are
the TB_OPCG_INSTANCE property is misplaced, or the wrong PFILE was identified. Edit
the PFILE, or edit the net list to fix the bad TB_OPCG_INSTANCE or TB_OPCG_PFILE
ERROR (TPO-912): Syntax error in time keyword of sequence sequencename in

programming file (PFILE) pfilename. The bad syntax was on the following statement:textstr
Fix the PFILE and rerun the job. This will cause errors in downstream processing.
EXPLANATION:
The sequence definition in the named programming file has an Event with an associated
time keyword, but there was no information following "time=".
USER RESPONSE:
Either remove the time keyword from this event, or add the intended formula for
calculating the time displacement for the event. After editing the PFILE, rerun the job.
ERROR (TPO-913): Mismatched parentheses in the properties field of an event in sequence

sequencename in programming file (PFILE) pfilename. The bad syntax was on the
following statement : textstr Fix the PFILE and rerun the job. This will cause errors in
downstream processing.
EXPLANATION:
Processing can not successfully continue because unmatched parentheses in the event
make it impossible to parse the event properties. The event properties must be enclosed
within parentheses. Some properties allow nested parentheses, but in all cases, an open
parenthesis must be matched by a corresponding close parenthesis.
USER RESPONSE:
Make sure there are matching open and close parentheses on this event statement.
After editing the PFILE, rerun the job.
ERROR (TPO-914): Processing test sequence sequencename for test step stepname,
a textstr event was found for pseudo primary input (PPI) ppiname. No timing information
is available for this PPI. The run will stop.

TPO - Messages
EXPLANATION:
The named event had a time parameter specified in the sequence definition found in the
programming file (PFILE). To resolve the time, the frequency of the clock (the named
PPI) must be known. The frequency of this PPI for this test step could not be determined.
USER RESPONSE:
Look for a TPO-761 message stating that the cutpoint pin associated with the named PPI
is not identified as an output for the clock generation macro. Look for a TPO-930
message stating that the source clock for this clock generation macro could not be
identified. If such messages are found, follow the instructions for eliminating those
messages. If there are no such messages that apply to this PPI, contact your customer
service representative.
ERROR (TPO-915): Mismatched square brackets in the properties field of an event in

sequence sequencename in programming file (PFILE)pfilename. The bad syntax was
on the following statement: textstr. Fix the PFILE and rerun the job. This will cause errors
in downstream processing.
EXPLANATION:
Processing can not successfully continue because unmatched square brackets in the
event make it impossible to parse the formula descried by the time property. Any open
or close parentheses inside the square brackets would have caused this message. The
square brackets can not be nested. The square brackets enclose references to register
properties defined elsewhere in the PFILE, and without being able to parse the time
formula and make the proper substitutions, the forumla can not be evaluated.
USER RESPONSE:
Make sure there are matching open and close square brackets surrounding all
references to register properties on this event statement, with no intervening
parentheses. After editing the PFILE, rerun the job.
ERROR (TPO-916): Unrecognized field name in the time formula for an event in sequence
sequencename in programming file (PFILE) pfilename. This was found on the following
statement : textstr The formula will evaluate to the default value of 1.
EXPLANATION:
Within a substitutable field, bounded by square brackets ([]), an unrecognized keyword
was found in the "field name" field. The format is [<registername>,<fieldname>],
and the only field name currently recognized is "timing_adjust".
USER RESPONSE:
Edit the PFILE by changing all the fieldnames to "timing_adjust" and rerun the job.

TPO - Messages
ERROR (TPO-917): Missing register name in the time formula for an event in sequence
sequencename in programming file (PFILE) pfilename. This was found on the following
statement: textstr The formula will evaluate to the default value of 1.
EXPLANATION:
Within a substitutable field, bounded by square brackets ([]), the register name was not
found. The format is [<registername>,<fieldname>]. Both fields are required.
USER RESPONSE:
Edit the PFILE by specifying the register names in all the time properties and rerun the
job.
ERROR (TPO-918): Missing comma within the square brackets in the time formula for an
event in sequence sequencename in programming file (PFILE) pfilename. This was
found on the following statement : textstr The formula will evaluate to the default value of
1.
EXPLANATION:
Within a substitutable field, bounded by square brackets ([]), there was no comma to
separate the register name and the field name. The format is
[<registername>,<fieldname>]. Both fields are required.
USER RESPONSE:
Edit the PFILE by correctly specifying the register names and the field names,
separating them by commas, and rerun the job.
ERROR (TPO-919): Can not identify register instancename.regname. The register

name regname is referenced in textstr1 in programming file (PFILE) pfilename.
This was found textstr2 :textstr3 The formula will textstr4.
EXPLANATION:
Within a substitutable field, bounded by square brackets ([]), a register name was used
that can not be found within the instance being processed.
USER RESPONSE:
Make sure the correct register name was used and that it is spelled correctly. Check the
spelling against the register definition in the START_PROGRAM_DEFINITIONS section of
the programming file (PFILE). Edit the PFILE and rerun the job.
ERROR (TPO-920): textstr in sequence sequencename in programming file (PFILE)

pfilename. This was found on the following statement:textstr. The formula will evaluate
to the default value of 1.

TPO - Messages
EXPLANATION:
There is a syntactical error in this formula. The nature of the error is stated in the
character string at the beginning of the message, and the formula is on an event in the
named sequence in the named PFILE. The formula could not be evaluated, and it will
be replaced by the number "1".
USER RESPONSE:
Look carefully at the message to understand the nature of the error and the specific
mistake in the formula that caused it. Then edit the PFILE and rerun the job.
ERROR (TPO-921): Unable to parse the time formula for an event in sequence
sequencename in programming file (PFILE)pfilename. This was found on the following
statement:textstr The formula will evaluate to the default value of 1.
EXPLANATION:
It appears that the event contains a time parameter, but the time parameter could not be
parsed because the syntax seems to be incorrect. It is an unexpected syntax error that
the program can not recognize. Since there does appear to be a time parameter, a value
of 1 will be used.
USER RESPONSE:
Carefully examine the syntax of the Event and its parameters to see what might be
wrong. The error could be an unrecognized keyword of the form xxxtime=<value>, or
it could be mismatched parentheses in the Event. Correct the syntax error by editing the
PFILE and rerun the job.
ERROR (TPO-922): No outputs of PLL or Domain block blockname are active. This PLL/
Domain will be defined for inactive pin pinname.
EXPLANATION:
If some outputs of a PLL or clock generation circuit (DOMAIN) are inactive, they are
normally skipped; they are not included in the PLL/DOMAIN definition. If all the outputs
of a PLL or DOMAIN are inactive, however, the PLL/DOMAIN is defined with reference to
one of the inactive output pins. This message is to clarify this because earlier messages
should already have appeared stating that each of this PLL/DOMAIN's outputs are
being skipped.
USER RESPONSE:
None. The sole purpose of this message is to avoid confusion due to some previous
message stating that the output named in this message was being skipped.

TPO - Messages
ERROR (TPO-923): Output pin pinname on PLL or Domain block blockname, defined in
programming file pfilename, does not drive a cutpoint net. This pin will be skipped in the
PLL/DOMAIN definitions.
EXPLANATION:
Encounter Test requires that each PLL output and each DOMAIN output be represented
as a pseudo primary input (PPI). That is, each output pin must drive a cutpoint net. No
cutpoint was defined for this PLL/DOMAIN output, so this output is being skipped to avoid
the introduction of an unwanted cutpoint at this output net, and subsequent processing
errors.
USER RESPONSE:
Modify the programming file (PFILE) to make each defined output pin be a cutpoint.
Then rerun the job.
WARNING (TPO-924): Unrecognized information in sequence seqname in programming

file (PFILE) pfilename. This was found on the following statement: textstr The
information is ignored.
EXPLANATION:
The program was looking for a statement beginning with one of the following:
[ Define_Sequence
[ Pattern
Event
] Pattern
] Define_Sequence
But the statement printed in this message was found instead. This statement was
skipped.
USER RESPONSE:
Determine what statement was intended and edit the PFILE. If the statement was
intended to be a comment, prefix it with the comment characters // or #<blank> where
<blank> is the space character.
ERROR (TPO-925): Domain input pin pinname on block blockname could not be found.
This pin was referenced in a DOMAIN_IN_CLOCK statement in programming file
pfilename. The run will stop.
EXPLANATION:

TPO - Messages
The named block is the containing block (having the TB_OPCG_INSTANCE property) for
a clock macro which is identified by TB_OPCG_REGNAME and TB_OPCG_PFILE
properties, but the named programming file (PFILE) references a pin that does not
match any of the input pins on the named block. There are many possible causes: The
pin name in the PFILE may be misspelled (check for correct use of upper- and lower-
case characters); the wrong pin may have been identified in the PFILE; the netlist may
be pointing to the wrong PFILE; the TB_OPCG_INSTANCE property may be misplaced
(belongs to a higher or a lower level of the hierarchy).
USER RESPONSE:
Check the block named in this message and make sure it is the correct hierarchical level
for the macro being described by this PFILE. Make sure the correct PFILE was
referenced, and check the pin name in the DOMAIN_IN_CLOCK statement. Edit the
netlist or the PFILE to correct the problem, and rerun the job. If the netlist is edited, re-
import it before proceeding.
ERROR (TPO-926): PLL input pin pinname on block blockname could not be found. This
pin was referenced in a PLL_IN_OSC statement in programming file pfilename. The run
will stop.
EXPLANATION:
a PLL which is identified by TB_OPCG_REGNAME and TB_OPCG_PFILE properties, but
the named programming file (PFILE) references a pin that does not match any of the
input pins on the named block. There are many possible causes: The pin name in the
PFILE may be misspelled (check for correct use of upper- and lower-case characters);
the wrong pin may have been identified in the PFILE; the netlist may be pointing to the
wrong PFILE; the TB_OPCG_INSTANCE property may be misplaced (belongs to a higher
or a lower level of the hierarchy).
USER RESPONSE:
Check the block named in this message and make sure it is the correct hierarchical level
for the macro being described by this PFILE. Make sure the correct PFILE was
referenced, and check the pin name in the PLL_IN_OSC statement. Edit the netlist or the
PFILE to correct the problem, and rerun the job. If the netlist is edited, re-import it before
proceeding.
ERROR (TPO-927): Register regname, found in block blockname, is not defined in the
associated programming file (PFILE) pfilename. The run will stop. Correct the netlist or
the programming file and rerun.
EXPLANATION:

TPO - Messages
a PLL or clock macro which is identified by TB_OPCG_REGNAME and TB_OPCG_PFILE
properties, but the named programming file (PFILE) has no reference to the named
register. There are several likely causes:
the netlist may be pointing to the wrong PFILE
the register name is misspelled in either the TB_OPCG_REGNAME property or in the
PFILE
or, the register is missing from the PFILE.
USER RESPONSE:
Make sure the correct PFILE was referenced, and check the register name in the
TB_OPCG_REGNAME property. Check for a misspelling in the PFILE by searching for a
register name that is similar. Edit the netlist or the PFILE to correct the problem, and
rerun the job. If the netlist is edited, re-import it before proceeding.
ERROR (TPO-928): Wrong number of fields coded in the following statement in the
START_PROGRAM_DEFINITIONS section of programming file (PFILE) pfilename:
textstr Expected integer1 commas, found integer2. The run will stop. Edit the
PFILE and rerun.
EXPLANATION:
This statement from the START_PROGRAM_DEFINITIONS section of the PFILE does
not have the right number of comma-separated fields. There are no optional fields in
these statements. The message states how many commas were expected, and there
should be this many plus one fields (the commas appear only between the fields, and not
at the beginning nor end). The fields are:
op, reg, mode, seq, timadj, data
where:
op is the field containing operation names
reg is the field containing register names
mode is the field containing names of the operational modes
seq is the field containing names of the test sequences
timadj is the field containing coefficients for specifying timing in thetest sequences
data is the field containg the binary vector to be loaded into the register

TPO - Messages
and they should appear in this order unless the first statment of this PFILE section is a
header statement containing these keywords in some other order.
USER RESPONSE:
Determine which field is missing. Edit the PFILE and rerun the job.
WARNING (TPO-929): Missing { character on TESTMODES statement in definition of

sequence seqname in programming file (PFILE) pfilename. The statement is: textstr. The {
character will be assumed.
EXPLANATION:
The PFILE syntax calls for the sequence definition for the testmode named in a
TESTMODES statement to be enclosed in matching curly braces {}. The opening curly
brace is missing, but the intent appears to be clear, so processing proceeds as though
the opening curly brace was specified.
USER RESPONSE:
Examine the PFILE and make sure the closing curly brace } was specified and placed
properly. Edit the PFILE to add the opening curly brace, which will prevent future
occurrences of this message. Look at the test sequence that was generated for this
testmode and make sure it is correct. If the test sequence is incorrect, rerun the job after
editing the PFILE.
ERROR (TPO-930): Could not find source clock in backtrace from textstr1 textstr2
input pin pinname. The clock tree information will be incomplete, and the GO signal duration
may be incorrect. Change the logic model and/or the PFILE so that unbroken clock paths exist
between the PLL and CLOCKDOMAIN macros.
EXPLANATION:
The program is attempting to find the clock macro, PLL, or oscillator pin that is driving the
clock macro or PLL that is named in the message as textstr2. It traced backwards
from the textstr2 input pin, but could find no pin that is an oscillator pin or the output
of another clock macro or PLL. The tracing is limited to logic that is at X (unknown state)
when the TC and TI signals are applied.
USER RESPONSE:
Make sure the logic is connected properly. Make sure the PFILE specifies the correct
pin as the input on the DOMAIN_IN_CLOCK or PLL_IN_OSC statement. See if there is
some TC or TI signal blocking the connection. Fix the problem and rerun the job.
ERROR (TPO-931): textstr1 evaluating the formula textstr2 in PFILE pfilename.

The formula will be evaluated as 0, and the run will stop.

TPO - Messages
EXPLANATION:
The program is attempting to find the clock macro, PLL, or oscillator pin that is driving the
clock macro or PLL that is named in the message as textstr2. It traced backwards
from the textstr2 input pin, but could find no pin that is an oscillator pin or the output
of another clock macro or PLL. The tracing is limited to logic that is at X (unknown state)
when the TC and TI signals are applied.
USER RESPONSE:
Make sure the logic is connected properly. Make sure the PFILE specifies the correct
pin as the input on the DOMAIN_IN_CLOCK or PLL_IN_OSC statement. See if there is
some TC or TI signal blocking the connection. Fix the problem and rerun the job.
ERROR (TPO-932): Unrecognized field name in the START_MULTIPLIER_DEFINITIONS

section of programming file (PFILE) pfilename in the following formula:textstr. The
formula will be evaluated as 0 and the run will stop.
EXPLANATION:
Within a substitutable field, bounded by square brackets ([]), an unrecognized keyword
was found in the "field name" field. The format is [<registername>,<fieldname>],
and the only field names currently recognized are timing_adjust and op_name.
USER RESPONSE:
Edit the PFILE by changing all the fieldnames to "timing_adjust" or "op_name" and
rerun the job.
ERROR (TPO-933): Missing register name in the following

START_MULTIPLIER_DEFINITIONS formula in programming file (PFILE) pfilename textstr.
The formula will be evaluated as 0 and the run will stop.
EXPLANATION:
Within a substitutable field, bounded by square brackets ([]), in a
MULTIPLIER_DEFINITION statement, the register name was not found. The format is
[<registername>,<fieldname>]. Both fields are required.
USER RESPONSE:
Edit the PFILE by specifying the register name and rerun the job.
ERROR (TPO-934): In Test Step stepname, textstr1 textstr2 is programmed for

passthru, and one or more downstream OPCG circuits are calling for clock pulses, but its input/
output frequency ratio is 0 for the operation specified in the test plan for the register(s)
specified in the PFILE MULTIPLIER_DEFINITION formula.

TPO - Messages
EXPLANATION:
The named PLL or clock macro feeds another clock macro which is active for this test
step, but this PLL or clock macro is programmed to divide its input frequency by 0. The
frequency divisor of 0 would be interpreted as an assertion that this macro is inactive
(turned off), but this is not consistent with the need to drive a downstream clock macro
that is active (not off). The inconsistency is in the programming file (PFILE), which
specified via some MULTIPLIER_DEFINITION statement that the macro is both
running (copying input pulses) and stopped (dividing the frequency by 0).
USER RESPONSE:
Find the inconsistent MULTIPLIER_DEFINITION statement in the PFILE and correct
it. Then rerun the job.
ERROR (TPO-935): In Test Step stepname, textstr1 textstr2 is turned on, but its
input/output frequency ratio is 0 for the operation specified in the test plan for the register(s)
specified in the PFILE MULTIPLIER_DEFINITION formula.
EXPLANATION:
The named clock macro is active (turned on) for this test step, but this clock macro is
programmed to divide its input frequency by 0. The frequency divisor of 0 would be
interpreted as an assertion that this macro is inactive (turned off), but this is not
consistent with its active status. The inconsistency is in the programming file (PFILE),
which specified via some MULTIPLIER_DEFINITION statement that the macro is both
active and stopped (dividing the frequency by 0). Its active status is indicated by the non
zero value of its output pulses field in the MULTIPLIER_DEFINITION statement.
USER RESPONSE:
Find the inconsistent MULTIPLIER_DEFINITION statement in the PFILE and correct it.
Then rerun the job.
ERROR (TPO-936): In Test Step stepname, CLOCKDOMAIN textstr is turned on, but
its clock source, pin pinname, is turned off. The run will stop. Correct the test plan file and
resubmit the job.
EXPLANATION:
The named PLL or clock macro is active (turned on) for this test step, but it is driven by
another clock macro, PLL, or oscillator input that is turned off. The pin name identified in
the message is the oscillator input or the output pin of the driving clock macro or PLL.
USER RESPONSE:

TPO - Messages
Edit the test plan file to turn on the driving pin. If the driver is another PLL or clock macro,
the editing will involve selecting some other operation for one or more registers in the
driving PLL or clock macro. Then rerun the job.
ERROR (TPO-938): In Test Step stepname, CLOCKDOMAIN textstr is programmed for

passthru, but its input waveform is an oscillating signal. CLOCKDOMAINS must produce a
finite number of pulses. The run will stop. Correct the test plan file and resubmit the job.
EXPLANATION:
The named clock macro is active (turned on) for this test step, programmed to copy its
input waveform (perhaps at a different frequency). It is driven by an oscillator pin or a
PLL, which produces either a continuous oscillating waveform or an indeterminate
number of pulses. A clock macro must produce a limited, predictable number of output
pulses so that the tests can be simulated and applied deterministically at the tester.
USER RESPONSE:
Change the test plan to select another mode of operation for this clock macro which will
produce a predetermined number of output pulses. Then rerun the job.
ERROR (TPO-939): In Test Step stepname, CLOCKDOMAIN textstr1 is fed by another

CLOCKDOMAIN, textstr2, but it is not programmed for passthru. When CLOCKDOMAINS
are cascaded, the downstream CLOCKDOMAIN must operate in passthru mode. The run will
stop. Correct the test plan file and resubmit the job.
EXPLANATION:
The named clock macro (CLOCKDOMAIN) is active (turned on) for this test step
programmed to produce a predetermined number of output pulses. To guarantee reliable
operation, this requires that its input be a continuous oscillating waveform from an
oscillator pin or a PLL. Thus, clock macros which are driven by other clock macros must
operate in passthru mode, copying the input waveform, perhaps at a different frequency.
USER RESPONSE:
Change the test plan so that each clock macro that is fed by an oscillator pin or a PLL
produces a predetermined number of output pulses and each clock macro that is fed by
another clock macro is in passthru mode. Then rerun the job.
ERROR (TPO-941): In Test Step stepname, PLL textstr1 is turned on and it drives
CLOCKDOMAIN textstr2, which is also turned on, but the clock source of PLL
textstr1, pin pinname, is turned off. The run will stop. Correct the test plan file by either
turning off the clock domain or turning on the oscillator/PLL and resubmit the job.
EXPLANATION:

TPO - Messages
The named PLL is active (turned on) for this test step, but it is driven by another PLL or
oscillator input that is turned off, and this PLL drives the named clock domain which is
programmed to produce some specific number of output pulses. For this to work, the
input PLL or oscillator pin, identified by the pin name in the message, must be activated
to produce a pulse train.
USER RESPONSE:
Change the test plan file. Either turn off the named clock domain or turn on the named
input PLL or oscillator pin. Then rerun the job.
ERROR (TPO-942): In Test Step stepname, PLL textstr is turned on, but its clock
source, pin pinname, is turned off. The run will stop. Correct the test plan file and resubmit
the job.
EXPLANATION:
The named PLL is active (turned on) for this test step, but it is driven by another PLL or
oscillator input that is turned off. The pin name identified in the message is the oscillator
input or the output pin of the driving PLL. This situation is intended to be reported by the
TPO-941 message, but a problem was encountered in gathering the additional
information for the TPO-941 message.
USER RESPONSE:
Due to the failure to print the TPO-941 message for this PLL, you should contact
WARNING (TPO-943): Test Step stepname uses sequences textstr1 but none of
these sequences contains a textstr2 event. No clock constraints file will be produced for
this experiment.
EXPLANATION:
The sequences named in the list printed in the messsage text were selected by the
named test step, and were combined into a single sequence for use in the test generation
experiment. But none of these sequences has a dynamic event of the named type
(release or capture). The clock constraints file is created from the compiled sequence
definition, and consists of all clock edge pairs matched as (release,capture). Each
release edge in the composite (compiled) sequence is paired with each capture edge,
and all such pairs are included in the clock constraints file. But no pairs were able to be
created because one of the constituent members of each pair does not exist. Note that
a propagate event is considered to be both release and capture, so this means that
besides the named type, no propagate events are specified in any of the named
sequences.
USER RESPONSE:

TPO - Messages
There are three possible choices:
a. Edit the programming file (PFILE) so that both release and capture events exist in
the composite sequence. If you want some event to serve as both release and
capture, code it as a "propagate" event. After editing the PFILE, rerun this job.
b. Edit the generated create tests command by removing the clockconstraints

keyword, and proceed.
c. Manually create a clockconstraints file and proceed.
ERROR (TPO-944): End of file reached before closing brace ('}') was found in programming
file (PFILE) pfilename. Edit the PFILE and rerun the job.
EXPLANATION:
An opening brace (the { character) has no matching closing brace (}) in the named
programming file (PFILE). The program is proceeding as though the file ends with a
closing brace, but this is very unlikely to produce good results.
USER RESPONSE:
Determine if there is any other information missing from the PFILE. Determine where
the closing brace should be. Make the necessary corrections by editing the PFILE.
Then rerun the job.
WARNING (TPO-945): Output pin pinname on block blockname could not be found.
This pin was referenced in a PLL_OUT_OSC statement or a DOMAIN_OUT_CLOCK statement
in programming file pfilename.
EXPLANATION:
The named pin was specified in the named programming file (PFILE) which provides
information about the named block, but this pin was not found inside nor as an I/O of the
named block.
USER RESPONSE:
This is most likely an error in the PFILE, either the wrong pin name was specified, or it
is a typographical error. Carefully check the pin name in the PFILE. Use the Encounter
Test schematic window to browse the model and find the intended pin. Copy the pin
name as found in the schematic into the PFILE (removing the block name and the
seperator character from the beginning of the pin name). After editing the PFILE, rerun
the job.
ERROR (TPO-946): Processing a Stim_NLproperty event in sequence sequencename in

programming file pfilename, the pin pin was found, but pin was not found as the value

TPO - Messages
of a TB_SEQUENCE_CONTROL property on any pin. This pin will be ignored in further

processing, and the run will stop.
EXPLANATION:
The Stim_NLproperty event is used only within a programming file (PFILE), and it
identifies one or more I/O pins to be stimmed, not by pin name, but by the found on the
TB_SEQUENCE_CONTROL property that is attached to the pin in the netlist. This pin was
not found on any TB_SEQUENCE_CONTROL property. Any TB_SEQUENCE_CONTROL
property attached to anything other than an I/O pin (such as one attached to a block or
an internal pin) would have been ignored.
USER RESPONSE:
The problem could have many causes, ranging from a mis-spelling of the pin to the use
of the wrong sequence definition through an error in the test plan whereby some register
was loaded to the wrong state, thus, selecting an incorrect sequence. Make sure you
intended to use a sequence definition that contains the Stim_NLproperty event. If so,
make sure the netlist contains the TB_SEQUENCE_CONTROL properties, that the
properties are specified on the I/O pins, and that the spelling of the pin is consistent
between the property value and the PFILE. Depending on the cause of the problem, you
may need to edit the netlist, the PFILE, or the test plan file. If the netlist must be edited,
re-import the model. After the problem is corrected, rerun this job.
WARNING (TPO-947): Writing sequence definition sequencename for testmode

testmodename, experiment experimentname, there are conflicting values for flop/pin/
PPI objectname on a eventname event. Value logicvalue will be used, and this
event is flagged with a comment in the filename file.
EXPLANATION:
This error was likely caused by the merging together of two different test sequence
definitions from different programming files (PFILEs), or from the same PFILE that
describes two different instantiations of a clock macro which are being programmed
differently in the testplan file. Two events (we will here refer to them as Stim_PI events,
but they could be Stim_PPI, Pulse, or any of a number of other events) named in the
message refer to the same object (an I/O pin, a flop, or a pseudo primary input (PPI)) but
are applying different values to this object, and the two events were merged into a single
event in the process of merging the two sequence definitions for the two macros. In such
a case, only the last value specified on the object in this event will be honored.
USER RESPONSE:
Use a text editor to look at the sequence definition file, named in the message. Find the
named sequence definition, and look for the comment "# Note conflicting values on <flop/
pin/PPI name>". Examine the sequence definitions as they appear in the PFILE(s) to find

TPO - Messages
the sources of the conflicting values. The relevant PFILE sequence definitions are listed
in a comment at the beginning of the sequence definition in the output file named in the
message. Then determine whether those two events from the PFILE sequence
definitions should have been combined into a single event. If so, then either one of the
PFILE sequence definitions is wrong, or the testplan file is specifying the wrong
operation for some register, which caused the wrong sequence definition in the PFILE to
be selected. In this case, edit the PFILE or the testplan and rerun the job. If the two
events should not have been merged into a single event, then it is a software bug. In this
case, contact your customer service representative (see Contacting Customer Service
on page 23).
WARNING (TPO-948): GO signal pinname is being turned off in one of the sequences
sequencenamelist But this GO signal was already off. This redundant event will remain
in the test sequence.
EXPLANATION:
The message gives a list of sequence names from the input programming file(s)
(PFILEs) that are being merged into a single test sequence definition. One or more of
these PFILE sequence definitions turns on a GO signal, and an incidence was found
where one of them is turning off a GO signal that has not been turned on (or has already
been turned off). There is no real harm in a redundant stim event, but the danger is that
there may be a missing stim event to turn this GO signal on.
USER RESPONSE:
Use a text editor to examine the sequence definition files named in the message. Pay
careful attention to all Stim_PI events that reference the named pin, looking for
instances where it is being stimmed to its *off* state redundantly. Determine if this is a
redundant stim *off*, or if there is a missing stim *on* event. The message may be
caused by confusion about the GO signal polarity. Its *off* state is what is specified by
the test function pin attribute specified on the pin. If it is a wrong test function polarity
specified in the netlist, the testmode definition file, or the assignfile, correct the error and
rebuild the model if it is a netlist error. If it is a missing Stim event in the sequence
definition, edit the PFILE. Then resubmit the job.
WARNING (TPO-949): A GO signal is being turned off in one of the sequences

sequencenamelistn. But no GO signals are turned on in any of these sequences. The
GO signal stims will be automatically derived, and the GO signal *off* stim specified in the
sequence will be ignored in the timing calculations. The tests may not work in the hardware.
EXPLANATION:
(PFILEs) that are being merged into a single test sequence definition. One or more of
these PFILE sequence definitions turns off a GO signal, but no incidence was found

TPO - Messages
where one of them is turning on a GO signal. Since no GO signals are being turned on
by the PFILE sequence definitions, the GO signal stim events will be added
automatically. The GO signal stim *off* event in the sequence definition will be ignored in
this automatic GO signal processing, but it will be retained in the sequence definition,
and thus, it may prematurely turn off the GO signal, which could result in truncating the
clock pulse train that is being generated in the hardware, causing failures at the tester.
USER RESPONSE:
Determine if the intent was to specify the GO signal stims in the PFILE, or allow them to
be added automatically. If they are to be added automatically, remove the GO signal stim
*off* event(s) from the PFILE sequence definition. If they are to be specified in the PFILE
sequence definition, then add the necessary GO signal stim *on* event(s) in the
appropriate place(s). After editing the PFILE, resubmit the job.
WARNING (TPO-950): GO signal pinname is being turned on in one of the sequences

sequencenamelist But this GO signal was already on. This redundant event will remain
in the test sequence.
EXPLANATION:
(PFILEs) that are being merged into a single test sequence definition. An incidence was
found where one of them is turning on a GO signal that is already on. There is no real
harm in a redundant stim event, but the danger is that there may be a missing stim event
to turn this GO signal off. In that case, lack of a transition on the pin here will cause the
clock generation logic not to be activated, and the test will fail in the hardware.
USER RESPONSE:
Use a text editor to examine the sequence definition files named in the message. Pay
careful attention to all Stim_PI events that reference the named pin, looking for
instances where it is being stimmed to its *on* state redundantly. Determine if this is a
redundant stim *on*, or if there is a missing stim *off* event. The message may be
caused by confusion about the GO signal polarity. Its *off* state is what is specified by
the test function pin attribute specified on the pin. If it is a wrong test function polarity
specified in the netlist, the testmode definition file, or the assignfile, correct the error
and rebuild the model if it is a netlist error.If it is a missing Stim event in the sequence
definition, edit the PFILE. Then resubmit the job.
a textstr event was found for pseudo primary input (PPI) ppiname.\n The frequency of
this PPI is unknown. Will assume this clock macro is driven by a decimal mHz clock. The
run will stop.
EXPLANATION:

TPO - Messages
The named event had a time parameter specified in the sequence definition found in the
programming file (PFILE). To resolve the time, the frequency of the clock (the named
PPI) must be known. The frequency of this PPI for this test step could not be determined.
A frquency is being assumed, but the run will stop anyway.
USER RESPONSE:
Look for a TPO-762 message for this PPI which indicates that it controls more than one
cutpoint. If that is the case, then the wrong cutpoint net may have been identified in this
TPO-952 message, and then diagnosis of the problem will be difficult. You will have to
consider all the nets identified by TPO-762 messages as being controlled by this PPI.
The following instructions assume there was no TPO-762 message for this PPI. Look for
a TPO-761 message stating that the cutpoint pin associated with the named PPI is not
identified as an output for the clock generation macro. Look for a TPO-930 message
stating that the source clock for this clock generation macro could not be identified. If
such messages are found, follow the instructions for eliminating those messages.
a textstr event was found for the pseudo primary input (PPI) ppiname.The polarity
specified on this event is wrong. It will be changed to a pulse polarity and the run will
stop.
EXPLANATION:
The Pulse_PPI event specified a polarity that is not consistent with the "off" state of the
clock as defined by the PPI's test function pin attribute. The attribute and the pulse
polarity should always be opposite, because the attribute specifies the "off" state of the
clock pin/PPI and the Pulse event specifies the active state. When they are not
consistent, strange things happen during Encounter Test simulation of the tests, and
those strange things will go completely unnoticed except for the appearance of the TCL-
087 message. One effect of the incorrect simulation is wrong dynamic fault coverage if
the Pulse event is inside a dynamic pattern. Another effect may be incorrect predicted
responses, resulting in zero-yield. As stated in the message, the software assumes the
test function pin attribute is correct, and it has changed the Pulse polarity to be in
agreement. Thus, the TCL-087 message will not appear, and provided that the test
function pin attribute is indeed correct, the results will be accurate.
USER RESPONSE:
If the test function pin attribute is correct, edit the PFILE by correcting the pulse polarity
in the sequence definition. If the pulse polarity is correct, and the test function pin
attribute is wrong, edit the PFILE by correcting the test function pin attribute. After editing
ERROR (TPO-970): Unable to relinquish model for build_testmode.

TPO - Messages
EXPLANATION:
The extension language method TBX::cleanUp() was invoked to free up the circuit
model so that the build_testmode command can be invoked, but TBX::cleanUp()
returned an error condition. This is most likely a software problem.
USER RESPONSE:
Examine the log file for any unusual conditions or messages that might suggest why
there is a problem. Make sure you do not have any other processes running on this
circuit. If you are unable to fix the problem, contact your customer service representative
ERROR (TPO-980): Failed to open workdir

EXPLANATION:
The TBX::selectWorkDir(workdir) was invoked to open the circuit for processing,
but this extension language method returned an error condition. The process can not
proceed.
USER RESPONSE:
Make sure the workdir keyword on this command was properly specified, and that the
circuit is not being used by some other process.
ERROR (TPO-982): Parent testmode modename does not exist.

EXPLANATION:
The required parentmode keyword was specified, but the specified testmode could not
be opened for processing.
USER RESPONSE:
Make sure the correct testmode name was specified on the parentmode keyword. Make
sure the parent testmode has not been deleted, or that the circuit has not been re-
imported after the parent testmode was built.
ERROR (TPO-983): Unable to read file filename.

EXPLANATION:
The tilatchlist keyword was specified, but the program was unable to open the file
that was specified as the tilatchlist keyword value.
USER RESPONSE:

TPO - Messages
Make sure the specification of the tilatchlist keyword was intentional. If so, then
specify the correct name of the input file containing the list of TI latches.
ERROR (TPO-984): Can not open log file filename.

EXPLANATION:
This program begins processing by running the build_testmode command, and it
uses the log file output from the build_testmode command to identify the location of
some other inputs that it needs, such as the mode definition file. The named file was
specified as the output log for the build_testmode command, but upon completion of
build_testmode, this output log file could not be opened.
USER RESPONSE:
This is likely a host system error. Make sure sufficient DASD is available to run the job.

EXPLANATION:
The named file is a programming file (PFILE), but processing of it could not commence.
Its processing involves piping through two reformatting scripts, and the most likely cause
of this message is a break in the pipes, possibly due to these scripts not being properly
installed. The script names are clrcmnts and fixbrace. Processing can not continue.
USER RESPONSE:
Make sure the software was properly installed. Then rerun the job.

EXPLANATION:
The named file is the test plan file, but processing of it could not commence. Its
processing involves piping through a reformatting script, and the most likely cause of this
message is a break in the pipe, possibly due to this script not being properly installed.
The script name is clrcmnts. Processing can not continue.
USER RESPONSE:
Make sure the software was properly installed. Then rerun the job.
ERROR (TPO-987): The keyword prepare=no was specified, but the run can not proceed
because the filename file can not be found in the tbdata directory.
EXPLANATION:

TPO - Messages
The prepare keyword specification controls which phases of the command are
executed in the current job. This job specified prepare=no, meaning that the input files
for build_testmode have already been built, and the only remaining steps are to run
build_testmode and read_sequence_definition. The command lines for these
two steps are constructed along with the other input files, and saved in the identified file
in the tbdata directory. Because this command file is missing, this job can not proceed.
USER RESPONSE:
If the command file was inadvertantly removed, it will have to be reconstructed by
running with prepare=yes (the default) or prepare=only. If the command file is still
available because it was inadvertantly moved, or omitted from a copy of the circuit to a
new directory structure, then you can copy (or move) it into the tbdata directory and rerun
this job with prepare=no.
ERROR (TPO-989): Failed to open the preliminary testmode testmodename. Consult the
log file pathname TTMdef.testmodename for further information.
EXPLANATION:
Before building the requested testmode, a temporary version of the testmode is $ first
built so that the analysis can be performed which is necessary to create the input files for
the final testmode build. After attempting to build the temporary testmode, it has been
discovered that the temporary testmode cannot be opened, and that the build process
returned an error condition, indicating that the temporary testmode probably was not
built.
USER RESPONSE:
This message should never occur unless there is an accompanying TPO-010 message.
Find the TTMdef.<modename>.temp log file and look at its message summary to find
the reason for the failure. There are many possible reasons for the failure, and they can
not be anticipated here. Re-submit the job after correcting the problem.
ERROR (TPO-990): [internal] An unexpected condition occurred in the Encounter(TM)

Test commandname code. Contact customer support(see Contacting Customer Service
on page 23) to report this error and give them the following information: textstr.
EXPLANATION:
This error indicates a program error that only the Encounter(TM) Test team can fix. The
information provided in the message is not intended to be meaningful to you, but it will
USER RESPONSE:

TPO - Messages
using your normal process: sourcelink, email, or direct call to the customer support line,
fix the problem more quickly. If there is a potential workaround in the message, you may
try it to continue experimenting. However, you will need to rerun the command once a
fix is provided by customer support (see Contacting Customer Service on page 23).
ERROR (TPO-991): Stopping without building testmode due to severe errors.

EXPLANATION:
The testmode can not be built because of problems encountered during the processing.
USER RESPONSE:
Examine the other messages to find out what is keeping the testmode from being built.
WARNING (TPO-992): The following OPCGPGM statement in Test Step stepname of the
test plan refers to an undefined operation. OPCGPGM=textstr This OPCGPGM statement is
ignored.
EXPLANATION:
The operation field of the listed OPCGPGM statement specifies an operation that is not
recognized. This statement will not be used.
USER RESPONSE:
Determine which operation was intended. Correct the name by editing the test plan file
and rerun the job.
WARNING (TPO-994): No test sequence is specified for Test Step stepname.

EXPLANATION:
None of the operations specified in the test plan for this test step has an associated test
sequence definition. No test sequence will be created for this test step.
USER RESPONSE:
There are several possible scenarios that could result in this situation.
1. Some register operation specification was omitted from the test plan.
2. The register operation was specified, but with the wrong register or operation.
3. The sequence name was inadvertently omitted from the register-operation definition in
the programming file (PFILE).
4. You intend to write the test sequence definition yourself.

TPO - Messages
In cases 1, 2, or 3, edit the input file that is wrong and rerun the job. In case # 4, create
the test sequence definition and run the read_sequence_definition command to
import the sequence definition before running create_logic_delay_tests. If you
are using the automatically generated create_logic_delay_tests command, you
will have to add the testsequence keyword to it.
ERROR (TPO-995): Failed to open testmode modename.

EXPLANATION:
The TBX::selectTestMode(modename) method was invoked to do processing in the
named testmode, but it returned an error condition, indicating that the testmode is invalid.
The modename would be either the name of the target testmode, specified on the
command line, or the parent testmode, also specified on the command line.
USER RESPONSE:
This message should never occur. If it does, look for other messages that might indicate
user error. If everything else looks okay, contact your customer service representative
ERROR (TPO-996): Error in setting the statename state.

EXPLANATION:
The TBX::setCircuitState(statename) method was invoked to set internal
circuit values to the indicated state for analysis, but this method returned an error
condition.
USER RESPONSE:
ERROR (TPO-997): Error in propagating from pinlogicvalue pinname.

EXPLANATION:
The TBX::stimCircuitFromNodeValue(nodeindex,logicvalue) method was
invoked to set and propagate the indicated value on the named pin for analysis, but this
method returned an error condition.
USER RESPONSE:

TPO - Messages
ERROR (TPO-998): The testmode definition file, filename, does not exist in the specified
path: modedefpath
EXPLANATION:
The named file is supposed to be the mode definition file, existing in the directory
identified as modedefpath, but it does not exist there.
USER RESPONSE:
Move the mode definition file into the specified directory, or specify the correct directory
on the modedefpath keyword. Then rerun the job.
ERROR (TPO-999): Encounter Test Perl Extensions failed to load.

EXPLANATION:
This indicates a problem in the Encounter Test installation.
USER RESPONSE:
Check with the person responsible for installing Encounter Test at your site.

62
TPT - Path Test Analysis Messages
TPT-001 through TPT-317 on page 1907
TPT-001 through TPT-317

WARNING (TPT-001): [Severe] Syntax Error in Path File filename. The Pin/Net/Block
name or Pin index name was not found in the Encounter Test Model. Correct or remove the
name and rerun.
EXPLANATION:
The specified pin, net or block does not exist in the model, or there is a syntax error in
the file. Blanks are used as separators, so ensure that the path identifier and the
specified pin/net/block name do not contain blanks.
USER RESPONSE:
Enter the name in the Encounter Test display to see if the name exists in the model, if
not, review the possible names. Second, review the syntax of the file.
WARNING (TPT-002): The collection of points identified by path_identifier in

filename could not be connected to form a path. Correct the path and rerun.
EXPLANATION:
Paths are formed by connecting all the points that are part of a path identifier. In this
case, one or more of the points can not be reached by the other points and the names in
the list. The connection algorithm does not trace through latches or arrays.
USER RESPONSE:
Enter the points in the list on the Encounter Test Displays path menu. By analyzing in
sets of two you can see which points can not be connected to the others.
ERROR (TPT-003): Failed to obtain a feature_string license. Run terminates. Verify

that the required license is installed and available.

EXPLANATION:
This application requires the indicated license to run under Encounter Test. In this case,
the license could not be obtained either because it does not exist, or was unavailable at
the time of invocation. The run cannot proceed without the required license.
USER RESPONSE:
Ensure the availability of the required license, then rerun.
ERROR (TPT-004): User sequence Name: seqName was not found in the sequence file for
testmode modeName. Ensure the sequence name is correct and has been read in using
EXPLANATION:
The named sequence was not found in the sequence file for the testmode.
USER RESPONSE:
Make sure that sequence name is specified correctly. If so, make sure the sequence was
read in properly using the read_sequence_definition command, or via the
ERROR (TPT-101): Test Generation / Fault Simulation step not run because of failures in
running Path Fault Build.
EXPLANATION:
The application was run to create path faults but failed to complete with a successful
return code. Any further processing of Test Generation and Fault Simulation on this set
of path faults may yield invalid results. The processing stops.
USER RESPONSE:
Determine why the Path Fault build step failed and rerun the application.
WARNING (TPT-301): [Severe] No path faults were produced from Path File filename.
This could be because the testsequence, clockconstraints file, dynseqfilter, or
selectpathid is too restrictive.
EXPLANATION:
No path faults were identified using the input from the provided file. One of the reasons
could be that the testsequence, clockconstraints or dynseqfilter keywords
do not specify clock domains that include any of the paths or the path selected by
selectpathid is not in the pathfile. Previous messages may provide more information.
USER RESPONSE:

Review any previous messages and determine why no path faults were produced. If
there were no previous messages, verify that the testsequence,
clockconstraints, and/or dynseqfilter settings are correct for the paths being
tested. If they are correct, remove the testsequence and clockconstraints
keywords and set dynseqfilter=any. :
WARNING (TPT-302): [Severe] Could not open input Path File filename. Ensure that
the filename is correct and that it has read permission set.
EXPLANATION:
The application could not open the specified file.
USER RESPONSE:
Ensure that the given file name and path is correct and that the file can be read.
WARNING (TPT-303): [Severe] Empty input Path File filename. Ensure that the given
file name and path is correct and that the file contains data.
EXPLANATION:
The given file has no contents which can be read.
USER RESPONSE:
Ensure that the given file name and path is correct and that the file contains data.
WARNING (TPT-304):In path path_identifier entity name was not found in the
Encounter Test Model. Ensure that the name is correct.
EXPLANATION:
The specified pin, net, or block does not exist in the model, or there is a syntax error in
the file. Blanks are used as separators so ensure that the path identifier and pin/net/block
names do not contain blanks.
USER RESPONSE:
Enter the name in the Encounter Test display to see if the name exists in the model, if
not, review the possible names. Second, review the syntax of the file.
WARNING (TPT-305): [Severe] User specified Path Group groupname was not found in
the input Path File filename. Ensure that the selectgroup keyword is set properly.
EXPLANATION:
The selectgroup=<groupname> option was specified but the given groupname was
not found in the input path file.

USER RESPONSE:
Ensure that the given group is in the file and that the syntax is correct.
WARNING (TPT-306): [Severe] No Path Groups were found in the input Path File
filename. Ensure that the Path File contains valid paths.
EXPLANATION:
The input file did not produce any potential path fault groups to work with.
USER RESPONSE:
Ensure that there are path groups in the file and that the syntax is correct.
WARNING (TPT-307): Path path_identifier is not added to the path fault model,
since it is in blocked at nodename. Ensure that the correct path has been provided.
EXPLANATION:
The given point in Encounter Test model unable to be observed because the logic is
blocked. This logic could be blocked either at the given node or further downstream.
USER RESPONSE:
Ensure that the intended path characterizations can be done in the testmode.
INFO (TPT-308): User specified path group pathname has pathnum path faults defined.
EXPLANATION:
The given path group was able to produce the number of path faults reported.
USER RESPONSE:
Review the message to see if this is the desired result.
INFO (TPT-309): The specified Alternate Fault Model (ALTFAULT=altname) cannot be

used. It is ignored.
EXPLANATION:
The alternate fault model name must be determined by the Path Fault build program. The
specified alternate fault model cannot be used and will be ignored.
USER RESPONSE:
No response required unless ignoring the ALTFAULT name is a problem.

since it is in inactive logic at nodename. Ensure that the correct path has been provided.
EXPLANATION:
The given point in Encounter Test model is not active in the test mode so it can not be
observed. The fault is not added to the fault model.
USER RESPONSE:
INFO (TPT-311): The Path build application has finished.

EXPLANATION:
The Path build application has finished.
USER RESPONSE:
INFO (TPT-312): Maximum number of path faults maxtot reached.

EXPLANATION:
The maximum number of path faults for the given fault model has been reached. All
generation of more path faults stops. The default is no limit, but a limit can be specified
with the option maxtotalpaths=<number>.
USER RESPONSE:
If more path faults are required, either increase the value for maxtotalpaths or break
the task up into several jobs.
ERROR (TPT-313): Path faults cannot be built on testmode testmodeName since dynamic
faults are not allowed in this test mode. Modify the modedef file for this testmode to include
dynamic faults and rebuild the testmode.
EXPLANATION:
Since dynamic faults are not allowed in the test mode, path faults (a type of dynamic fault)
cannot be built for this testmode.
USER RESPONSE:
Use the TTMgetData executable to verify whether dynamic faults are allowed. Modify
the modedef file for this testmode to include dynamic faults, rebuild the test mode, and
rerun the application.

INFO (TPT-314): pathnum paths were dropped for path group pathname because the
measure point was a PO and dynpomeasure=no was specified. To include these paths,
either rerun with dynpomeasure=yes or edit the path file to allow the paths to be observed
at latches.
EXPLANATION:
Paths that are observed at a PO are only created if dynpomeasure=yes is specified.
This allows test generation to use POs as a measure point.
USER RESPONSE:
If the desired paths are not created, either rerun with dynpomeasure=yes or adjust the
path file to measure at latches rather than POs.
INFO (TPT-315): pathnum path groups are defined.

EXPLANATION:
This message indicates the total number of created path groups. For each path identifier
in the input path file, there may be up to 2 groups of path faults created.
USER RESPONSE:
ERROR (TPT-316): A pathfile or pathname is missing. A pathfile must be specified

to build a path faultmodel or pathname specified to process already built paths.
EXPLANATION:
A path file must be specified with the pathfile keyword when creating a path fault
model with the create_path_delay_tests or prepare_path_delay commands.
A path name must be specified with the pathname keyword if creating tests for a
previously created path fault model with the create_path_delay_tests command.
USER RESPONSE:
Specify the pathfile or pathname keyword to the applicable command and rerun.
WARNING (TPT-317): Path secondPath is ignored, since it is a duplicate of

originalPath.
EXPLANATION:
Duplicate path specifications within the path file were detected. The first path
specification is retained.
USER RESPONSE:

WARNING (TPT-318): Path pathname is untestable because non-scannable latch is found

for all paths. Should set measureonlyendofpath=yes/no when generating test for this
path.
EXPLANATION:
Non-measurable latch found at the endpoint of paths.
USER RESPONSE:
None.
since it is tied at nodename. Ensure that the correct path has been provided.
EXPLANATION:
The given point in Encounter Test model is at a tied value in the test mode so transitions
are not possible. This pat It cannot participate in the identification of the path faults.
USER RESPONSE:
since it is in unpowered logic at nodename. Ensure that the correct path has been provided.
EXPLANATION:
The given point in Encounter Test model is unpowered in the test mode so transitions are
not possible. This pat It cannot participate in the identification of the path faults.
USER RESPONSE:
since it is not within the domain at nodename. The logic within the domain is specified by
either the testsequence, clockconstraint or seqfilter.
EXPLANATION:
The given point in Encounter Test model is not with in the logic that can be tested based
on the testsequence, clockconstraints or dynseqfilter.
USER RESPONSE:

Determine if is is the expected result or whether more logic should be allowed to tested.
The logic can be increased by adding a testsequence, clock constraintor changing
dynseqfilter.

63
TPU - Test Pattern Utility Messages
TPU-002 through TPU-972 on page 1915
TPU-002 through TPU-972

ERROR (TPU-002): [Internal] Space allocation failed. program cannot allocate space for
table.
EXPLANATION:
USER RESPONSE:
ERROR (TPU-003): [Internal] TPU latchfill function failed. Contact customer support.
EXPLANATION:
The TPU latchfill routine failed while applying the specified values the Scan_Load
vector.
USER RESPONSE:
Contact customer support (see Contacting Customer Service on page 23) for further
investigation.
ERROR (TPU-004): [Internal] TPU Failed attempting to get the OPCG statistics for
testmode mode_name.
EXPLANATION:
The test pattern utility failed attempting to get the OPCG register data. It cannot continue
processing.
USER RESPONSE:

ERROR (TPU-005): The specified test cannot be simulated using

controlpipeline=skip. Specify controlpipeline=fm or controlpipeline=gm
and rerun.
EXPLANATION:
Encounter Test was asked to simulate using the original unmanipulated scan latch
values. These values are saved within the Internal_Scan_Load event during
manipulation of the vectors. No Internal_Scan_Load event was found. This indicates
that the patterns were manipulated by an earlier release of Encounter Test. Without the
initial scan latch values, Encounter Test cannot simulate the unmanipulated scan latch
values.
USER RESPONSE:
Specify controlpipeline=fm or controlpipeline=gm and rerun.
ERROR (TPU-006): Checking of the ignoremeasure file failed due to msgString. If you
cannot correct the problem, contact Cadence Customer Support for assistance.
EXPLANATION:
Checking of the ignoremeasure data failed.
USER RESPONSE:
Message contains a short message string which explains the problem. Correct problem
and rerun. For example, the job may have failed due to a lack of space. Contact customer
WARNING (TPU-007): [Severe] The Cellname you have provided cellname does not
exist for this design. Check the syntax in the ignoremeasures file before continuing.
EXPLANATION:
Invalid Cellname String.
USER RESPONSE:
Verify Cell Name syntax is correct: Block.f.l.<cellname>.nl if the problem
persists verify the block you are including is a valid cell that can be used for ignoring
latches/POs. If you cannot correct the problem, contact Cadence Customer Support for
assistance (Contact customer support (see Contacting Customer Service on page 23).
.

WARNING (TPU-008): The Cellname you have provided cellname is block Zero for the
design. Including this cell in the ignoremeasures file will ignore all Measure Latches and is
not recomended.
EXPLANATION:
Cellname Is Block 0, verify this is what is intended.
USER RESPONSE:
Verify Cell Name is correctly specified: Block.f.l.<cellname>.nl and is intended
to be block zero for the part.
WARNING (TPU-400): The input vectors contain a Scan_Load event immediately following
a Compact_Scan_Load event. No Scan_Load event will be added by the
TPUfillTestPro. Contact customer support for assistance.
EXPLANATION:
The program adds a Scan_Load event following each Compact_Scan_Load event.
Values are then added to the Scan_Load event based on the Compact_Scan_Load
event and the fill option specified for test generation. The addition of this Scan_Load
event allows Encounter Test simulators to skip over the Compact_Scan_Load events
and use the fully specified latch values in the Scan_Load events. A Scan_Load event
was found immediately following the Compact_Scan_Load event in the input test
vectors and a second Scan_Load event will not be added.
USER RESPONSE:
The program may have been called more then once for this Test Procedure. Contact
WARNING (TPU-401): No Scan_Load or Compact_Scan_Load event was found within

Test_Sequence sequence_number. OPCG register values could not be loaded for this
test_sequence.
EXPLANATION:
The Setup sequence for the current Test_Procedure being processed contains a
Load_OPCG_Controls event. One or more OPCG registers within the
Load_OPCG_Controls event must be loaded as part of the scan load operation. The
processed Test_Sequence did not contain a scan load operation and prevented the
loading of OPCG registers
USER RESPONSE:
If these are manual patterns ensure that all Test_Sequences contain a Scan_Load or
Compact_Scan_Load event. Re-import the test vectors and rerun analyze_vectors.

If the test vectors were produced by Encounter Test, contact customer support (see
WARNING (TPU-850): The stim to stim value on net name, flat index flat index
overrides the non-default LINEHOLD to linehold_value. The stim value will be
simulated.
EXPLANATION:
A non-default linehold is overridden by a stim. The override is allowed.
USER RESPONSE:
Ensure that the override is correct.
WARNING (TPU-860): In a stim or pulse event, the stim value on correlated PI pinname
is not the value required by the correlation. Other conflicts may exist in this event. Processing
continues.
EXPLANATION:
USER RESPONSE:
value on the correlated PI is correct. If the value is not correct, change the value and
rerun.
ERROR (TPU-911): [Internal] PROGRAM ERROR ENCOUNTERED. Processing

terminates. Error in file filename at line line_number. diagnostic message
Contact customer support.

EXPLANATION:
USER RESPONSE:
INFO (TPU-960): Ignore Measure file: filename opened successfully

EXPLANATION:
The measure latches and POs specified in this file will be ignored for measurement and
fault detection by simulation

USER RESPONSE:
INFO (TPU-961): Ignoring measure at objectname

EXPLANATION:
This PO or Measure Latch will be ignored for measurement and fault detection by
simulation
USER RESPONSE:
ERROR (TPU-962): TPU error on line linenumber. objectname is not a PO or

Measurable Latch. Correct this naming problem before rerunning your command.
EXPLANATION:
Specify only Primary Outputs and Measurable Latches in the Ignore Measure file. Use
fully specified names.
USER RESPONSE:
Fix problem on the specified line in the file identified with the ignoremeasures
keyword.
INFO (TPU-963): number latches and number POs will be ignored for measurement and
fault detection.
EXPLANATION:
The indicated number of POs and Latches will not be considered measure points by the
simulator.
USER RESPONSE:
ERROR (TPU-964): Error opening filetype measure file: filename

EXPLANATION:
The referenced file cannot be opened
USER RESPONSE:
Ensure adequate permissions for the file specified with the ignoremeasures or
keepmeasures keyword and rerun..

INFO (TPU-965): Keep Measure file: filename opened successfully

EXPLANATION:
The measure latches and POs specified in this file will be measured. All other latches
and POs will be ignored for measurement and fault detection by simulation
USER RESPONSE:
INFO (TPU-966): Measure at objectname

EXPLANATION:
The indicated PO/measure latch will be measured
USER RESPONSE:
INFO (TPU-967): number latches and number POs will be measured. All other latches will
be ignored for measurement and fault simulation.
EXPLANATION:
This number of latches and POs will be considered measure points by the simulator. All
other latches will be ignored for measurement and fault simulation
USER RESPONSE:
INFO (TPU-968): Ignore Non-Scan PO Measures file: filename opened successfully.

EXPLANATION:
The POs specified in this file will be ignored for measurement and fault detection by
simulation during the scanchain test.
USER RESPONSE:
None
WARNING (TPU-969): Both an ignoremeasure and a keepMeasure file were specified.

Both files can not be specified for the same run. The ignoremeasure file will be used.
EXPLANATION:

You can specify one or the other but not both. If both are specified the
ignoremeasures file is used.
USER RESPONSE:
Change your command line to specify either ignoremeasures or keepmeasures, but
not both. Then rerun your command.
ERROR (TPU-970): Specified name name does not exist for this design.
EXPLANATION:
Specified name was not found in this design.
USER RESPONSE:
Correct the the naming problems in the ignoremeasure file.
ERROR (TPU-971): One or more ignoremeasure file names is incorrect. Correct these
naming problems before rerunning your command.
EXPLANATION:
Problems were found with one or more names as they were read from the
ignoremeasures file. Review all TPU-962 and TPU-970 messages found in the logfile.
USER RESPONSE:
Using the information found in the TPU-962 and TPU-970 messages, correct the naming
problems before rerunning your command.
ERROR (TPU-972): TPU parsing error on line linenumber. line data.

EXPLANATION:
Parse failed processing the indicated line.
USER RESPONSE:
Fix problem on the specified line in the ignoremeasures file.
ERROR (TPU-976): One or more ignorenonscanpomeasures file names are incorrect.

Correct these naming problems before rerunning your command.
EXPLANATION:
Problems were found with one or more names as they were read from the
ignoremeasures file. Review all TPU-962 and TPU-970 messages found in the logfile.
USER RESPONSE:

Using the information found in the TPU-962 and TPU-970 messages, correct the naming
problems before rerunning your command.
INFO (TPU-977): number POs will be ignored for measurement and fault detection during
the scanchain test.
EXPLANATION:
This number of Primary Outputs will not be considered measure points by the simulator
during the scanchain test.
USER RESPONSE:
None
INFO (TPU-978): objectname was specified in the ignorenonscanpomeasures file.

All Primary Outputs that are not ScanOut or MisrObserve pins will be ignored during your
scanchain test.
EXPLANATION:
ScanOut and MisrObserve pins may not be ignored during the scanchain test. _allPOs
was specified in your ignorenonscanpomeasures file. All except the ScanOut and
MisrObserve pins will be ignored measurement and fault detection by simulation.
USER RESPONSE:
None
ERROR (TPU-979): objectname was specified in the ignorenonscanpomeasures file.

Observable latches, ScanOut pins and MisrObserve pins can not be ignored during
scanchain test.
EXPLANATION:
The specified name was either a Observable latch, a ScanOut or a MisrObserve pin.
These pins may not be ignored during the scanchain test.
USER RESPONSE:
Remove all Observable latches, ScanOut pins and MisrObserve pins from your
ignorenonscanpomeasures file before rerunning your command.

64
TRA - Random Resistant Fault Analysis
Messages
TRA-001 through TRA-050 on page 1923

TRA-051 through TRA-600 on page 1935
TRA-001 through TRA-050

NFO (TRA-001): index has high correlation and may affect number undetected faults.
Ratio between calculated and observed probabilities is ratio.
EXPLANATION:
The signal probabilities observed at the output of this object in random pattern simulation
are not the same as those calculated from the input probabilities. The calculated
probabilities assume that all the inputs are statistically independent. A discrepancy
between calculated and observed probabilities is an indication that the inputs of the
identified node are correlated. If the nodes output is constant, this may indicate a logical
redundancy. The discrepancy between these two probabilities is reported along with the
total number of undetected faults in the objects backward cone. Note that correlated
nodes are reported only if they may affect untested faults.
USER RESPONSE:
Consider modifying the logic feeding this block to improve the detectability of the
untested faults.
INFO (TRA-002): pin/block objectName has high correlation and may affect
faultCount undetected faults. Ratio between calculated and observed probabilities is
probabilityDiscrepancy.
EXPLANATION:
The signal probabilities observed at the output of this object in random pattern simulation
are not the same as those calculated from the input probabilities. The calculated

TRA - Random Resistant Fault Analysis Messages
probabilities assume that all the inputs are statistically independent. A discrepancy
between calculated and observed probabilities is an indication that the inputs of the
identified node are correlated. If the nodes output is constant, this may indicate a logical
redundancy. The discrepancy between these two probabilities is reported along with the
total number of undetected faults in the objects backward cone. Note that correlated
nodes are reported only if they may affect untested faults.
USER RESPONSE:
Consider modifying the logic feeding this block to improve the detectability of the
untested faults.
INFO (TRA-003): pin/block objectName has stuck-at-

faultDetectionProbability fault detection probability faultStuckValue,
controllability-controllability observability and
controlObserveLogicValue-observability value.
EXPLANATION:
This message reports low stuck fault detection probability for the specified object. The
fault detection probability is the product of the controllability and observability values,
also reported, for the logic state opposite the stuck value.
USER RESPONSE:
If the controllability and observability values are not acceptable analyze the design to see
why the values are low and correct it if necessary.
INFO (TRA-004): pin/block objectName has logic controllability

controllability of logicValue.
EXPLANATION:
This message reports the controllability of a logic 0 or logic 1 for the specified object. The
controllability is computed based on random pattern simulation.
USER RESPONSE:
If the controllability value is not acceptable, analyze your logic and change it if required.
INFO (TRA-005): pin/block objectName has logic observability observability

of logicValue.
EXPLANATION:
This message provides the observability of a logic 0 or logic 1 for the specified object.
The observability is computed based on random pattern simulation.

USER RESPONSE:
If the observability value is not acceptable, analyze your logic and change it if required.
INFO (TRA-006): pin/block objectName is an input of a regionBlockCount-block

region which is hard to control and may affect blockedFaultCount blocked and
unexcitedFaultCount unexcited faults.
EXPLANATION:
This block is one of the inputs to a region of adjacent blocks, all of whose signal
probabilities outside the range defined by the cluster threshold, clustProb. This
message reports the total number of untested faults in the entire region and its backward
cone.
USER RESPONSE:
If tests for some of the faults in the region cannot be generated, modifying the design to
eliminate the skewed signal probability at or near the input(s) of the region is likely to
improve the circuits test coverage.
INFO (TRA-007): pin/block objectName is the root of a clusterBlockCount-block

cluster which may affect blockedFaultCount blocked and unexcitedFaultCount
unexcited faults.
EXPLANATION:
The {clusterBlockCount} blocks in the fanin of this block all have signal probabilities
outside the range defined by the cluster threshold, clustProb. This message reports the
total number of untested faults in the backward cone of the entire cluster.
USER RESPONSE:
If tests for some of the faults in the cluster cannot be generated, modifying the design to
eliminate the skewed signal probability at the input(s) of the cluster(s) is likely to improve
the circuits test coverage.
INFO (TRA-008): Pin/Block objectName is an input to cluster count clusters and may
affect totalFaultCount untested faults (cumulativeFaultCount faults so far.)
EXPLANATION:
The skewed signal probability at this blocks output contributes to skewed signal
probability at the outputs of the other blocks in the clusters. This message reports the
total number of untested faults blocked by the cluster blocks fed by this input, along with
the number of faults blocked by all the cluster inputs reported so far.
USER RESPONSE:

If tests for some of the faults in the cluster cannot be generated, modifying the design to
eliminate the skewed signal probability at the input(s) of the cluster(s) is likely to improve
the circuits test coverage.
ERROR (TRA-009): Unable to load circuit.

EXPLANATION:
An attempt was made to load the model file but determined that the file does not exist.
USER RESPONSE:
Ensure the necessary pre-requisite steps have been performed (model import, test
mode define etc.), prior to rerunning Random Resistant Fault Analysis.
ERROR (TRA-010): Unable to register experiment.

EXPLANATION:
This is a program error. The run terminates.
USER RESPONSE:
This indicates a problem with the globalData file. Re-import the design and rerun. If this
does not fix the problem, contact customer support (see Contacting Customer Service
on page 23).
ERROR (TRA-011): Unable to register test mode.

EXPLANATION:
USER RESPONSE:
on page 23).
ERROR (TRA-012): Unable to open fault model.

EXPLANATION:
The program was unable to open the file faultStatus.xxx.TRA where xxx is the test
mode name.
USER RESPONSE:
If you are running without gmonly=yes, make sure the file faultStatus.xxx.TRA
(where xxx is the test mode name) exists. If it does not, remove the file named

SigProb.xxx.TRA and rerun RRFA. If this does not fix the problem or you are running
with gmonly=yes, contact customer support (see Contacting Customer Service on
page 23).
ERROR (TRA-013): Unable to allocate memory.

EXPLANATION:
There does not appear to be enough storage to satisfy a memory allocation request.
USER RESPONSE:
Consider the following:
Are there any other jobs running that may be requiring storage?
Are there other machines available to run this job on?
If the problem occurs frequently contact customer support (see Contacting
ERROR (TRA-015): No WORKDIR defined.

EXPLANATION:
The WORKDIR name was not specified. The run terminates.
USER RESPONSE:
Specify WORKDIR, either by exporting or on the command line, and rerun.
ERROR (TRA-016): No PARTID defined.

EXPLANATION:
The PARTID name was not specified. The run terminates.
USER RESPONSE:
Specify PARTID, either by exporting or on the command line, and rerun.
ERROR (TRA-017): No TESTMODE defined.

EXPLANATION:
The TESTMODE name was not specified. The run terminates.
USER RESPONSE:
Specify TESTMODE, either by exporting or on the command line, and rerun.

ERROR (TRA-018): Process has ended with severe error while registering the message file.
EXPLANATION:
USER RESPONSE:
on page 23).
ERROR (TRA-019): Unable to open/close the message file

EXPLANATION:
Some condition exists which prevents access to the file TRAmessageFile.xxx.TRA
where xxx is the name of the testmode. This could be a permissions problem.
USER RESPONSE:
Check to see that the file exists. If it does not rerun the program. If it does exist check the
permissions on the file.
ERROR (TRA-020): Unable to write to the message file.

EXPLANATION:
Some condition exists which prevents access to the file TRAmessageFile.xxx.TRA
where xxx is the name of the testmode. This could be a permissions problem.
USER RESPONSE:
Check to see that the file exists. If it does not rerun the program. If it does exist check the
permissions on the file.
ERROR (TRA-021): Unable to register status or save global data file.

EXPLANATION:
USER RESPONSE:
on page 23).
ERROR (TRA-022): Unable to collect probability data

EXPLANATION:
The simulation run just completed did not create a signal probability file. This is most
likely due to a terminating error in the in the pattern simulation program, but may be due
to some other transient system condition not reported as an error.
USER RESPONSE:
Fix any problems identified in terminating messages in the preceding log, then rerun
analyze_random_resistance.
ERROR (TRA-023): Processing was interrupted.

EXPLANATION:
Processing was terminated because of a interrupt signal.
ERROR (TRA-024): Unable to obtain license.

EXPLANATION:
The program was unable to obtain the license required for Random Resistant Fault
Analysis.
USER RESPONSE:
Ensure the availability of the necessary license.
WARNING (TRA-025): Existing experiment data is incompatible with the current release. It
will be ignored.
EXPLANATION:
The data associated with the specified experiment is incompatible with this release of
USER RESPONSE:
None.
ERROR (TRA-026): Sampling=samplingtype is not supported for testmodes that use

linear or sequential decompression. Specify sampling=cop.
EXPLANATION:
The random simulation feature is not supported for test modes that use linear or
sequentail decompression. Sampling=cop must be used.
USER RESPONSE:

> $ Rerun analyze_random_resistance with sampling=cop, or remove the sampling

keyword from the command.
WARNING (TRA-027): [Severe] Data from only randomPatternsRun random patterns

was collected. If this number is insufficient, start a fresh analyze_random_resistance
run with randpatterns=randomPatternsToTry to force collection from the
randomPatternsRequested patterns originally requested.
EXPLANATION:
RRFA was unable to predict for data collection purposes the number of patterns that
would occur in flat random simulation. The most likely reason is some condition that
caused the simulation to end prematurely. The RRFA analysis will be done on the data
that was collected.
USER RESPONSE:
If the number of completed patterns is acceptable, use the analysis data that follows. If
not, and if the simulation ended prematurely, correct the condition that stopped the
simulation. Otherwise, to collect data on the number of patterns you originally requested,
remove the current experiment and start a fresh analyze_random_resistance run
using the value suggested in the message for randpatterns. The next run will also
issue this message, but the number of patterns actually run should be at least as large
as the original required number.
ERROR (TRA-028): Data Collection failed on terminating error. Refer to previous messages
for details.
EXPLANATION:
The simulation run just ended due to a terminating error in simulation.
USER RESPONSE:
Fix any problems identified in terminating messages in the preceding log, then rerun
INFO (TRA-029): The preceding EDAM120 message for file handle

hexFileHandleValue can be safely ignored.
EXPLANATION:
Occasionally an EDAM120 message may occur when the Encounter Test GUI
terminates after displaying signal probability data. The condition that causes this
message is harmless.
USER RESPONSE:

ERROR (TRA-030): No clock templates were specified. Clock templates are required for
LBIST test modes.
EXPLANATION:
The simulation phase of RRFA cannot generate clock templates for LBIST test modes.
You must supply clock templates that will exercise the logic to be tested in a manner that
will permit RRFA to assess the random BIST testability of your circuit.
USER RESPONSE:
Import the test sequences you require and specify their names using the
testsequence= parameter.
ERROR (TRA-034): Unable to create uncommitted fault statistics.

EXPLANATION:
The program was unable to create an uncommitted fault status file.
USER RESPONSE:
Review preceding system messages to determine the cause of the problem.
ERROR (TRA-035): Unable to open RRFA signal probability file.

EXPLANATION:
The program was unable to open the RRFA simulation statistics file.
USER RESPONSE:
Ensure that the PARTID, TESTMODE, and EXPERIMENT match a previous good
machine only RRFA run.
WARNING (TRA-037): [Severe] Unable to open RRFA signal probability file for experiment
EXPERIMENT.
EXPLANATION:
The program was unable to open the specified RRFA simulation statistics file. The run
continues without using the RRFA signal probability data.
USER RESPONSE:
Verify that the RRFA experiment was specified correctly and that the previous RRFA run
completed successfully. There may have been an error writing the signal probability file.

INFO (TRA-038): Test point selection will be performed using the multiple test point
algorithm because the design size is greater than 100,000 gates.
EXPLANATION:
The test point selection algorithm was specified as preferred. Due to the size of the
circuit, RRFA prefers to use the multiple test point selection algorithm because it
determines multiple test points at one time.
USER RESPONSE:
If you would like to specify an explicit test point insertion algorithm, specify
tpselect=value, where value is the name of the algorithm (alternate, single or
multiple).
See "analyze_random_resistance" in the Encounter Test: Reference: Commands for
INFO (TRA-039): Test point selection will be performed using the alternate algorithm
because no control points are requested (maxctlpts = 0).
EXPLANATION:
The test point selection algorithm was specified as preferred. When only observe points
are requested (no control points), the alternate algorithm usually provides equally good
test points in much less time. Therefore, RRFA prefers this algorithm.
USER RESPONSE:
multiple).
WARNING (TRA-040): The simulated test coverage is significantly lower than the estimated
test coverage, test Points may be suspect. This may be due to reconvergent fanout in the
design. Specifying tpselect=alternate may provide better test points.
EXPLANATION:
Simulation of the circuit indicates that a significant amount of reconvergent fanout exists
which can give the default test point selection algorithms false information. An alternate
test point identification algorithm exists, but in most cases provides inferior test points to
the default algorithm. This algorithm may perform better on circuits with significant
reconvergent fanout.

USER RESPONSE:
multiple), and then rerun.
INFO (TRA-041): Collapsed Static %%Tcov before test point identification is coverage%.
EXPLANATION:
The test point identification algorithm uses an estimated fault coverage based on
probability of detection. It is usually optimistic when compared to actual fault coverage.
This estimate is only used to guide the test point selection process and should not be
regarded as a true measure of random pattern testability.
USER RESPONSE:
INFO (TRA-042): Test Point identification is complete. No test points could be identified.
EXPLANATION:
The test point identification algorithm completed, but was unable to identify any test
points. If random pattern testability is still not sufficient, there may be redundant faults in
the design that RRFA is unable to identify. Or there may be pattern faults in the design.
RRFA does not support test point insertion to detect pattern faults.
USER RESPONSE:
If your fault model was built using pattern faults, you might consider building the fault
model using the option to replace automatic pattern faults with pin faults.
Then rerun RRFA to see if any test points are identified. Even if you want to use the
pattern faults for test generation, it may be beneficial to use the pin fault model to perform
test point identification. Once the test points are inserted into the design, then build a
pattern fault model for test generation.
To identify redundant faults in the design, run Deterministic Fault Analysis. You can then
pass the redundant fault information into RRFA by specifying the dfaexperiment
option on the RRFA command line. Both of these suggestions may improve RRFAs
ability to identify test points. See "Fault Analysis" in the Encounter Test: Guide 4:
Faults for additional information.

INFO (TRA-043): Estimated Collapsed Static numtp%.Tcov after inserting all identified test
points will be coverage%.
EXPLANATION:
The test point identification algorithm uses an estimated fault coverage based on
probability of detection. It is usually optimistic when compared to actual fault coverage.
This estimate is only used to guide the test point selection process and should not be
regarded as a true measure of random pattern testability. If random pattern testability is
still not sufficient, there may be redundant faults in the design that RRFA is unable to
identify. Or there may be pattern faults in the design.
RRFA does not support test point insertion to detect pattern faults.
USER RESPONSE:
If your fault model was built using pattern faults, you might consider building the fault
model using the option to replace automatic pattern faults with pin faults.
Then rerun RRFA to see if any test points are identified. Even if you want to use the
pattern faults for test generation, it may be beneficial to use the pin fault model to perform
test point identification. Once the test points are inserted into the design, then build a
pattern fault model for test generation.
To identify redundant faults in the design, run Deterministic Fault Analysis. You can then
pass the redundant fault information into RRFA by specifying the dfaexperiment
option on the RRFA command line. Both of these suggestions may improve RRFAs
ability to identify test points. See "Fault Analysis" in the Encounter Test: Guide 4:
Faults for additional information.
INFO (TRA-044): Test point selection will be performed using the single algorithm.
EXPLANATION:
The test point selection algorithm was specified as preferred. RRFA prefers to use the
single test point selection algorithm because it usually recommends the best test points
and can be completed in a reasonable amount of time.
USER RESPONSE:
multiple).

WARNING (TRA-045): The simulated test coverage is significantly lower than the estimated
test coverage, test Points may be suspect. Only number_of_patterns patterns were
simulated for each test sequence which may be causing low test coverage. Specify
randpatterns=nnnn to simulate more patterns or specify gmonly=yes to estimate test
coverage from the good machine simulation.
EXPLANATION:
A relatively small number of patterns per sequence was simulated. As a result, actual
fault coverage may be lower than the estimated coverage derived from the controllability/
observability data. This situation will reduce the effectiveness of the test point insertion
algorithm. Simulating more patterns may improve the test coverage. Or, specifying
gmonly=yes will avoid this problem by deselecting fault simulation and using only the
estimated coverage. However, when a small number of patterns per test sequence are
simulated, controllability/observability data may less accurate. If gmonly=yes is
specified, increasing the number of simulated patterns with the randpatterns keyword
is recommended.
USER RESPONSE:
Increase the number of simulated random patterns and/or specify gmonly=yes and
then rerun analyze_random_resistance.
INFO (TRA-050): Computing probability data based on randomPatterns random

patterns.
EXPLANATION:
RRFA is calculating signal probability data using a topological algorithm, instead of
performing simulation. This probability data uses the specified pattern count to calculate
probability of detecting faults if that number of random patterns were in fact simulated.
USER RESPONSE:
TRA-051 through TRA-600

INFO (TRA-051): The following analysis is taken from data based on randomPatterns
random patterns.
EXPLANATION:
The number of patterns used is reported for information purposes. This number may
differ from the number of patterns reported at the end RRFA Random Pattern Simulation,
but in any case it can be compared to the randpatterns=parameter. The

difference is due to the fact that some test sequences (counted by Random Pattern
Simulation) contain more than one "measure event"; for its own purposes RRFA counts
each "measure event" as a pattern.
USER RESPONSE:
INFO (TRA-052): Starting data collection by simulating randomPatterns random

patterns.
EXPLANATION:
RRFA is simulating the specified number of patterns to determine signal probability data.
USER RESPONSE:
INFO (TRA-053): Static Fault coverage at the end of RRFA data collection:
PinfaultCoveragePercentage% stuck pin faults,
TotalfaultCoveragePercentage% total.
EXPLANATION:
This message reports, for information purposes, the adjusted coverage percentage of
stuck pin faults and all static faults (stuck faults and pattern faults which were marked as
detected at the end of RRFA Random Pattern Simulation. This number comprises the
faults detected during RRFA Random Pattern Simulation and any faults detected by test
patterns committed in the current test mode or COMET.
USER RESPONSE:
INFO (TRA-054): The following RRFA parameters have been supplied.

EXPLANATION:
The lines following this message list the required RRFA run time parameters along with
the parameters which differ from the default settings and those which are derived from
the characteristics of the design being processed.
USER RESPONSE:
INFO (TRA-055): The scan chain test is being run to reduce the number of untested faults
for RRFA to analyze.

EXPLANATION:
RRFA has found that the scan chain test has not yet been saved for this test mode. Since
the scan chain test is are normally run and could mark faults tested that may not be
tested by the simulation of random patterns, RRFA is running the scan chain test to
eliminate these faults from RRFA analysis.
USER RESPONSE:
No action is necessary. However, RRFA will not save the results of the scan chain test it
performs. Once the scan chain test has been run and saved for this test mode, RRFA will
use the saved results and will no longer need to run this test as part of its normal process.
WARNING (TRA-056): Unable to open faultStatus file for input experiment exp.
faultStatus will not be updated prior to additional data collection.
EXPLANATION:
The faultStatus file for the specified input experiment could not be opened. RRFA is
unable to use this faultStatus information when performing additional data collection.
USER RESPONSE:
If you intended to use the faultStatus information from the specified input experiment, you
may need to rerun the input experiment to re-create the faultStatus information. If you did
not intend to use faultStatus information from a previous input experiment, do not specify
an inputExperiment when running RRFA.
INFO (TRA-057): Initializing faultStatus with status from input experiment exp.
EXPLANATION:
The faultStatus file for the specified input experiment is being used as the starting point
for performing RRFA data collection and analysis. This includes the status for tested,
possibly tested, untestable and redundant faults.
USER RESPONSE:
INFO (TRA-058): Updating faultStatus with redundant and untestable faults from experiment
exp.
EXPLANATION:
This experiment is being updated with the redundant and untestable fault status from the
specified experiment. This option is useful if you run Deterministic Fault Analysis and

want RRFA to exclude redundant and untestable faults from its analysis, and want RRFA
to work on the faults marked tested by Deterministic Fault Analysis.
USER RESPONSE:
INFO (TRA-059): Initializing SigProb file with signal probabilities from input experiment exp.
EXPLANATION:
The SigProb file for the specified input experiment is being used as the starting point for
performing RRFA data collection and analysis.
USER RESPONSE:
WARNING (TRA-060): Unable to copy SigProb file for input experiment exp. SigProb will
not be updated prior to additional data collection.
EXPLANATION:
The SigProb file for the specified input experiment could not be copied. RRFA is unable
to use this information when performing additional data collection.
USER RESPONSE:
If you intended to use the signal probability file information from the specified input
experiment, you may need to rerun the input experiment to re-create it. If not, do not
specify an inputExperiment when running RRFA.
WARNING (TRA-064): Unable to obtain test generation license for scan chain test.
EXPLANATION:
The program was unable to obtain the license required for the scan and LSSD flush test.
USER RESPONSE:
Ensure the availability of the test generation license to run scan chain test.
INFO (TRA-101): Cluster analysis will not be performed because good-machine-only

simulation was specified.
EXPLANATION:
The cluster analysis function sorts cluster roots by the number of undetected faults they
inhibit. Valid fault status data must be available to enable this sorting operation.

USER RESPONSE:
If cluster analysis is desired, ensure that the design has a fault model, then turn off the
good-machine-only option before rerunning RRFA.
INFO (TRA-102): All RRFA analysis has been turned off so no output will be generated.
EXPLANATION:
Since all analysis functions have been turned off, RRFA will not produce any output.
Existing signal probability data will be preserved but no new data will be collected.
USER RESPONSE:
Turn on at least one analysis function.
INFO (TRA-103): No signal probability data will be collected.

EXPLANATION:
Since all analysis functions have been turned off, there is no need to collect signal
probability data, since RRFA will not produce any output. This message follows TRA-102
if no signal probability data is present.
USER RESPONSE:
Turn on at least one analysis function.
INFO (TRA-110): loopcount feedback loops were found during design levelization.
EXPLANATION:
When RRFA loads the logic model it performs a rank ordering ("levelization") on all the
blocks in the circuit. Rank ordering must perform special processing on feedback loops.
USER RESPONSE:
INFO (TRA-120): Faults not considered for fault effect propagation:
Count First Reason

numPatternOrStuckFaults firstIDPatternOrStuckFault [1] pattern or other non-stuck
fault
numNotActivated firstIDNotActivated [2] no activation

Count First Reason

numFaultsLatchRamRom firstIDFaultsLatchRamRom [3] fault on latch/RAM/ROM input
numFaultsFeedClock firstIDFaultFeedsClock [4] fault on net feeding clock
numPOfaults firstIDPOfault [5] fault on PO
numTiedNetFaults firstIDTiedNetFault [6] fault on tied net
numUnsensitizedFaults firstIDUnsensitizedFault [7] no 1-level sensitization
num1LevelBlockedFaults firstID1LevelBlockedFault [8] insufficient sensitization
through first gate
numSuspectedRedundant firstIDSuspectedRedundant [9] suspected redundancy or
correlation
numAlongScanPath numFaultsConsidered [10] faults along scan path
Total faults considered: numFaultsConsidered; Faults retained:

numFaultsRetained numCandidateObservePoints candidate observe points
with max maxObservePointFaults, mean meanObservePointFaults faults.
EXPLANATION:
Before performing observe test point selection, RRFA eliminates from consideration the
faults which would not have a reasonable chance of being detected at any observe test
points. The reasons for eliminating the faults are listed along with the number of faults
eliminated for each reason.
Key to Reasons Listed:
[1] not a static stuck fault
[2] activating signal probability at fault site is zero
[3,4] faults on nets feeding clocks and at inputs to latches, RAMs and ROMs are not
propagated
[5,6] PO faults and faults on tied nets do not benefit from observe points
[7] sensitization through first gate is zero
[8] fault effect sensitization through first gate is below minObsCtlSens
[9] detection probability at fault site is above detectCutoff (STAFAN calculations do not
explain why fault is detected)

[10] fault is along the scan path. RRFA will not insert test points that could alter the scan
path.
USER RESPONSE:
ERROR (TRA-133): Unable to open probability file filename. Random Resistant Fault
Analysis is Terminating.
EXPLANATION:
The probability input file for hierarchical RRFA processing could not be found.
USER RESPONSE:
Specify the correct file name or remove the probabilityFile parameter and rerun
RRFA.
WARNING (TRA-134): message text

EXPLANATION:
An error was found processing the probability input file.
USER RESPONSE:
You should correct the problem identified by the message and rerun RRFA. Failure to do
so will affect the quality of the test point recommendations produced.
INFO (TRA-136): Checkpoint interval of checkpointInterval minutes expired at

elapsedTime elapsed time. A checkpoint is now being taken. patternCount patterns
simulated so far.
EXPLANATION:
Taking checkpoint. Note that the elapsed time since the last checkpoint (or the start of
the run) may be greater than the specified checkpoint interval.
USER RESPONSE:
INFO (TRA-137): Data collection complete at elapsedTime elapsed time. No checkpoint

data remains. patternCount patterns actually simulated.
EXPLANATION:
Data collection was completed successfully so checkpoint data is no longer required.
The raw signal statistics have been saved in the Signal Probability File. Any checkpoint

data taken during this run has been deleted. Note that the number of patterns simulated
may be slightly larger than the number of patterns requested due to the parallel nature
of the simulator.
USER RESPONSE:
INFO (TRA-138): Restart from previously created checkpoint was successful.

EXPLANATION:
Data collection continues from the last saved checkpoint
USER RESPONSE:
ERROR (TRA-139): Restart from previously created checkpoint failed.

EXPLANATION:
The checkpoint could not be reloaded.
USER RESPONSE:
None
INFO (TRA-140): The existing checkpoint has been deleted.

EXPLANATION:
A checkpoint exists but the restart=no option has been specified. Therefore, the
checkpoint has been deleted.
USER RESPONSE:
INFO (TRA-141): The analyze_random_resistance command parameters must be

changed as follows in order to restart RRFA:
EXPLANATION:
In order to obtain valid results when restarting an RRFA run from a checkpoint, certain
command parameters must match the values from the run that created the checkpoint.
Those parameters are gmonly, holdlhpins, linehold, and testsequence.
USER RESPONSE:

Modify the command parameters as directed to match the checkpoint or select the "no"
or "delete" restart option.
INFO (TRA-151): Control-controlState test point at block blockName pin pinName

has control strength probability and may affect faultCount faults in clusterCount
clusters.
EXPLANATION:
A test point record has been written for the indicated pin.
USER RESPONSE:
INFO (TRA-152): Unable to control entityName effectively by test point at cell boundary.
faultCount faults may be affected.
EXPLANATION:
The block identified has a controllability problem which cannot be fixed by improving
controllability at macro inputs, because it is too deeply embedded.
USER RESPONSE:
Consider modifying the affected macro or the surrounding logic.
INFO (TRA-153): Observe test point at block blockName pin pinName may affect
faultCount faults.
EXPLANATION:
USER RESPONSE:
INFO (TRA-154): type test point at block blockName pin pinName will increase test
coverage to approximately testCoverage%.
EXPLANATION:
USER RESPONSE:

WARNING (TRA-160): probability for Pin pinName could not be resolved. Default value of
default is used.
EXPLANATION:
A connection or probability for the specified pin could not be found when searching the
hierarchical probability data. A default probability value for the pin will be used.
USER RESPONSE:
If you suspect that probability data for the specified pin should have been found, verify
that the probability data for the connecting macro pin exists in the macros probability file
and the directory containing this file is listed in the probpath directory. Otherwise, no
action is necessary, as a default probability will be used by RRFA.
ERROR (TRA-161): Encounter Test Perl Extensions failed to load.

EXPLANATION:
Encounter Test was unable to load the Perl extension language functions. This is most
likely due to an incorrect setting of the environment variables PATH, LIBPATH,
LD_LIBRARY_PATH or SH_LIBPATH. Verify that these environment variables include
the Encounter Test code directories and run again.
USER RESPONSE:
If you cannot correct the problem by setting the PATH, LIBPATH, LD_LIBRARY_PATH
and/or SH_LIBPATH environment variables correctly, contact customer support (see
ERROR (TRA-162): Filename fileName could not be promoted because it does not exist.
EXPLANATION:
You requested that the specified probability file be moved to a common directory
(promotedir), to be used when running RRFA on other connecting circuits.
However, this probability file does not exist.
USER RESPONSE:
Verify that you have sufficient space and permission to write to the current design
directory, and that writeprobabilities=yes was specified as a parameter.
ERROR (TRA-163): The size of promoted file new_fileName does not match the original
file original_fileName. Verify that there is sufficient space and that permissions are set
correctly.
EXPLANATION:

After copying the probability file created in this experiment to a common directory, the
size of the new file does not match the file being copied.
USER RESPONSE:
Verify that you have sufficient space in target directory and that the proper permissions
are set.
INFO (TRA-164): Probabilities for primary inputs and outputs are being extracted from the
TRAprobabilityFiles of connecting entities. The controllability for missing primary input
connections will be p. The observability for missing primary output connections will be 1.0.
The extracted probabilities may be viewed by browsing file: fileName.
EXPLANATION:
Ordinarily, RRFA assumes that the observability of primary outputs is 1.0 and that the
controllability of primary inputs is 0.5, unless overridden by the
randompiweightfactor parameter.
Since you specified TOPLEVEL and PROBPATH, RRFA is using the hierModel in the
TOPLEVEL directory to determine connectivity between the entity being processed and
other entities in the TOPLEVEL model. RRFA then searches the PROBPATH directories
to find TRAprobabilityFiles for the connecting entities.
The probabilities associated with the connecting entities will be used by RRFA as the
probabilities of the Primary Inputs and Primary Outputs of this entity. Any missing
connections will use the specified default probability.
This process improves RRFAs ability to identify test points because it provides more
accurate primary input/output probability information.
USER RESPONSE:
You may browse the specified file to ensure that the probabilities extracted from
connecting entities are as expected. No other action is required.
INFO (TRA-165): The controllability for type will be p.

EXPLANATION:
Ordinarily, RRFA assumes that the controllability of primary inputs and scannable latches
is 0.5. Since you specified randompiweightfactor and/or
randomlatchweightfactor, the default probability for the specified type of gate will
be changed.
USER RESPONSE:

INFO (TRA-166): Approximately 5.2n of flops are assumed scannable.

EXPLANATION:
In an assumed scan mode, most flops should be scannable. This message reports an
estimated percentage of flops that analyze_random_resistance considers
scannable. If this percentage appears abnormally low, there may be a problem with the
testmode. Most likely, clocks to some flops are not off in the Test Constraint and Clocks
Off state causing the flops to be removed from the assumed scan chain.
USER RESPONSE:
Use report_test_structures to report floating latches and flops if you suspect an
issue with the percentage of scannable flops.
ERROR (TRA-167): append=yes not allowed when signal probability data exists for an
experiment. Delete the experiment and rebuild the fault subset, remove append=yes or use
existingdata=yes.
EXPLANATION:
append=yes may only be used to pass a fault subset experiment into
analyze_random_resistance. This experiment already has signal probability (and
fault status) data from a previous analyze_random_resistance run. Additional data
cannot be collected for this experiment.
USER RESPONSE:
Either remove append=yes which will essentially remove the entire experiment and
overwrite it, specify existingdata=yes to re-analyze existing signal probability / fault
status data, or if this is a fault subset experiment, rebuild the fault subset experiment and
then re-run analyze_random_resistance with append=yes.
WARNING (TRA-597): The parmName parameter is no longer supported. Its value will be
ignored.additionalInstructions
EXPLANATION:
The parameter <parmName> is no longer supported.
USER RESPONSE:
Follow additional instructions if provided, otherwise consult
analyze_random_resistance -h or "analyze_random_resistance" in the Encounter
WARNING (TRA-598): The sigProbIn parameter is no longer supported. Its value will be
ignored.

EXPLANATION:
The sigProbIn parameter is unnecessary since RRFA now supports the
EXPERIMENT parameter.
USER RESPONSE:
Use the EXPERIMENT parameter to refer to an existing signal probability file for analysis.
WARNING (TRA-600): Extracting the Encounter Test License.

EXPLANATION:
Analyze Random Resistance requires an Encounter Test License.
USER RESPONSE:
Verify a license is available.


65
TSM - Simulation Messages
TSM-003 through TSM-900 on page 1949
TSM-003 through TSM-900

INFO (TSM-003): The environment variable TSMnoTDR was set to TSMnoTDR=The
setting of TSMnoTDR.
EXPLANATION:
The June 2000 maintenance release of Encounter Test 2000 improves the simulators
method of deriving the termination values of 3 state nets. The program will now attempt
to get termination parameters from the TDR. Formerly, the program set those parameters
to default values. If the TSMnoTDR environment variable is set to TSMnoTDR=yes, the
program will not attempt to read the TDR.
TSMnoTDR=yes tells the program to set the TDR termination parameters to the default
values. This message prints whenever the environment variable TSMnoTDR is set.
export TSMnoTDR=yes sets the environment variable. unset TSMnoTDR removes the
environment variable.
USER RESPONSE:
ERROR (TSM-004): [Internal] Unable to register dependency in file:

source_file_name line: line_number. Contact Customer Support.
EXPLANATION:
A register dependency attempt failed.
USER RESPONSE:

INFO (TSM-100): The RAM Contents were compressed to The byte count of the RAM
Contents before compression bytes from The byte count of the RAM Contents after
compression bytes before being written to the Contents File.
EXPLANATION:
This message is a reminder of how much DASD is saved by the automatic compression
of the RAM Contents.
USER RESPONSE:
INFO (TSM-101): The RAM Contents were expanded to The byte count of the RAM
Contents after expansion bytes from The byte count of the RAM
Contents before expansion bytes after being read from the Contents File.
EXPLANATION:
This message is a reminder of how much DASD is saved by the automatic compression
of the RAM Contents.
USER RESPONSE:
ERROR (TSM-102): Failed copying contents checkpoint file.

source file: source_file_name
target file: target_file_name
EXPLANATION:
The program failed to copy the source file to the target file.
USER RESPONSE:
Refer to message TSM-106 for details of the failure.
ERROR (TSM-103): The stats on copied file copied_filename failed.

EXPLANATION:
The file successfully copied but the program failed to obtain statistics for the copied file.
USER RESPONSE:
ERROR (TSM-104): Cant open the file file_name for file_open_access access..

EXPLANATION:
The file failed to open with the referenced access.
USER RESPONSE:
Determine whether another user process is currently accessing the file.
ERROR (TSM-105): Cant close the file file_name..

EXPLANATION:
The file failed to close.
USER RESPONSE:
Determine whether another user process is currently accessing the file.
ERROR (TSM-106): Failed copying a char from source file to target file. The error mesage
error_message.
EXPLANATION:
The program was unable to copy a character from the source file to the target file.
USER RESPONSE:
Use the error message to determine the cause of the failed copy.
ERROR (TSM-107): Ram Size in contents file header is negative.

EXPLANATION:
The message states that there is a negative ram size in the contents file header.
USER RESPONSE:
ERROR (TSM-108): Number of bytes written to file is negative.

EXPLANATION:
The message states a negative number of bytes has been written to the file.
USER RESPONSE:
ERROR (TSM-109): Cannot find valid checkpointed contents file.

EXPLANATION:
The checkpoint ID to be used for restart does not match the ID stored in
contents_chk(n).<testmode>.<experiment>. Det3ermine whether
checkpoint contents file exist.
USER RESPONSE:
WARNING (TSM-700): An oscillation was detected on machine machine at net name

The logic value of the machine on that net was forced to X.
EXPLANATION:
This named net/machine changed 10,000 times for one stimulus event in the simulator.
The net is either in an oscillating feedback loop or is a <streamer> from a an oscillating
feedback loop. All nets changing after this detection are set to X to dampen the
oscillation.
Note: The program simulates 2 machines in parallel. They are referred to machine 0 and
machine 1.
USER RESPONSE:
Analyze the design to determine the source of the oscillation.
WARNING (TSM-710): Type of miscompare miscomp. Expected LExpected

logic value, got LObserved logic value. Flat model node Flat node net
name
EXPLANATION:
The simulator was told to verify the value on a net. The simulated value did not agree
with the predicted values.
USER RESPONSE:
Analyze the design and patterns to find the source of the difference,
INFO (TSM-900): TBD Expect event summary: The count of good Expect
comparisons good compares, The count of bad Expect comparisons bad
compares.
EXPLANATION:
This message does not print if both counts are = 0. A summary statistic. For Information
only.

USER RESPONSE:


66
TSC - Test Sequence Effectiveness
Checker Messages
TSC-001 through TSC-050 on page 1955

TSC-061 through TSC-130 on page 1964
TSC-001 through TSC-050

INFO (TSC-001): There are no latches on this design.
EXPLANATION:
No latch primitives exist in the logic model for this design. The Sequence Effectiveness
Checker looks for limitations of the test sequences in terms of how the latches are or are
not exercised. Since there are no latches in this design, the checker has nothing to do.
USER RESPONSE:
No action is required. Do not expect any useful information about the test sequences for
this design from the Sequence Effectiveness Checker.
ERROR (TSC-002): Required command line parameter parameter_name missing.

EXPLANATION:
A required parameter is missing from the command. The command cannot run without
the information supplied by this parameter.
USER RESPONSE:
Check the spelling on all the parameters. If you are not sure of all the required
parameters, consult analyze_sequences in the Encounter Test: Reference:
Commands. Determine the value for the missing parameter and try again.
WARNING (TSC-003): [Severe] Sequence definition sequence_name was not found.

EXPLANATION:

TSC - Test Sequence Effectiveness Checker Messages
The named sequence definition was requested for verification, but it cannot be found in
the TBDseq file. Checking will proceed if other requested sequence definitions were
available.
USER RESPONSE:
Make sure you specified the correct sequence name. If the name is correct, then import
the sequence definition and rerun.
ERROR (TSC-004): None of the requested sequence definitions were found.

EXPLANATION:
USER RESPONSE:
ERROR (TSC-005): Experiment name not specified.

EXPLANATION:
You asked for the simulation results to be written (writepatterns=yes) but no
experiment name was specified. The experiment name is needed for naming the output
file.
USER RESPONSE:
Specify any arbitrary name for the experiment and rerun.
WARNING (TSC-006): [Severe] Sequence sequence_name turns on two clocks at once,

primary_input|pseudo_PI pin_name and primary_input|pseudo_PI
pin_name.
EXPLANATION:
All Encounter Test design analysis and structure checks assume only one clock at a time
may be away from its stability state. This sequence violates the assumption, and
therefore invalid test data may result due to critical races. No audit is set, since other
applications should be checking this condition again when this sequence is used.
USER RESPONSE:
Edit the sequence definition and remove the condition that turns on multiple clocks. Re-
import the sequence definition and repeat the verification.

WARNING (TSC-007): [Severe] Sequence sequence_name turns on two oscillators at

once, primary inputs pin_name and pin_name. Verification proceeds with second pin set
to X.
EXPLANATION:
This is a limitation of Encounter Test. It performs a static simulation during the sequence
verification process, and therefore cannot synchronize two different oscillator signals.
USER RESPONSE:
If you get no other error messages from sequence verification, then there should be no
ill effects from this condition. However, this probably means that the second oscillator is
unnecessary for the operation that this sequence performs.
WARNING (TSC-008): [Severe] Sequence sequence_name overrides TI pin

EXPLANATION:
By definition, a TI pin is not allowed to be switched within the test mode in which this test
function attribute is specified. This message serves as a warning that this sequence
deviates from the designated test function of the pin, and subsequent processing of this
sequence by other Encounter Test application programs will also result in severe error
messages.
USER RESPONSE:
re-import the sequence definition and rerun Sequence Effectiveness Checking.
WARNING (TSC-009): [Severe] Sequence sequence_name overrides TC pin

EXPLANATION:
By definition, a TC pin is not allowed to be switched within a test sequence. This
message is printed only if the named sequence has a type of "test" and serves as a
warning that this sequence deviates from the designated test function of the pin.
Subsequent processing of this sequence by other Encounter Test application programs
will also result in severe error messages.
USER RESPONSE:
re-import the sequence definition and rerun Sequence Effectiveness Checking.

WARNING (TSC-010): [Severe] The TC primary_input|pseudo_PI|latch

pin_name was set to the wrong state at the end of sequence sequence_name.
EXPLANATION:
Sequences of types other than "test" are allowed to exercise TC pins, but all sequences
(modeinit, scanop, setup) must leave the TC pins at their designated states. This pin was
not restored to its designated state by the named sequence.
USER RESPONSE:
Edit the sequence definition by adding a Stim event to set this pin to its designated state
(or add this pin to an existing Stim event). re-import the sequence definition and rerun
Sequence Effectiveness Checking.
WARNING (TSC-011): [Severe] Sequence sequence_name overrides TI|TC pseudo

PI pin_name with a event_name event.
EXPLANATION:
The named pseudo PI must remain constant throughout the sequence, by definition of
its TC/TI test function attribute. The named sequence deviates from this by specifying a
different value on the pseudo PI.
USER RESPONSE:
Examine the design model and the pattern sequence to determine how this pseudo PI
was switched. There is an error in the sequence, or in the design, or in the test function
attribute assigned to this pseudo PI. If the design is wrong, correct it and re-import the
design. If it is a wrong attribute on the pseudo PI, this can be corrected by an override in
the mode definition file; edit the mode definition file and rerun Create Test Mode. If the
error is in the sequence definition, edit the sequence definition, re-import the sequence
definition, and rerun Sequence Effectiveness Checking.
WARNING (TSC-012): [Severe] The sequence sequence_name specifies a

Scan_Load|Channel_Scan event but the design was not in the TG stability state.
EXPLANATION:
Scan operations (Scan_Load, Channel_Scan) must start and end with the design in the
test generation stability state. The design is said to be in the test generation stability state
if, and only if all of these conditions exist:
All clocks (both primary inputs and pseudo primary inputs) are at their defined
"off" states
All TI signals (primary inputs, pseudo primary inputs, and fixed-value TI latches)
are at their defined states

All TC signals (primary inputs, pseudo primary inputs, and TC latches) are at
their defined states.
By the definition of the TG stability state, test sequences are constrained to that state,
except when pulsing a clock. Therefore, the scan operation always starts and ends with
the design in the TG stability state.
USER RESPONSE:
Examine this sequence to determine which pins (or pseudo PIs or latches) were not at
their TG stability state values. This includes all TI, clock, and TC primary inputs. Since a
deviation from a TI state causes another error message, the problem is almost sure to
be on a clock or TC signal. Use View Circuit Statistics on the View pull-down menu to get
a list of TC latches.
WARNING (TSC-014): [Severe] Force value on net net_name conflicts with normal
design activity at event event_ID in sequence sequence_name.
EXPLANATION:
This message is issued when a Force event specifies a value to be placed on a net, or
is holding a value on the net, and the normal simulation would have put a different value
on the net. If the severity is WARNING, the normal simulation value is X (unknown). A
WARNING [Severe] message means that normal simulation would have predicted a
known value, different from what the net is being forced to. Usually, the Force event
(when it is needed at all) should be used only to convert an X to the correct known value,
because Encounter Test simulators tend to err on the side of pessimism so that the
known values they predict are correct. The Force event should be used only in complex
situations where the simulator cannot correctly predict the responses without help, and
the user understands exactly what he/she is doing.
USER RESPONSE:
Examine the sequence and the simulation results carefully to make sure that the Force
event was correctly specified. If not, then edit the sequence to remove it. Then re-import
the sequence and rerun Verify OPC Sequences. Refer to On Product Clock Sequence
Verification in the Encounter Test: Guide 3: Test Structures for related information.
WARNING (TSC-018): [Severe] conflict_type three-state conflict detected during

simulation of event event_ID in sequence sequence_name.
EXPLANATION:
Not all Encounter Test processes simulate the OPC logic; therefore, the sequence
verifier may be the only opportunity to catch three-state conflicts on nets in this logic. All
potential conflicts are flagged as problematic, because it is expected that the OPC logic
should seldom if ever contain any uninitialized nets (except very early in the mode

initialization sequence), and these contentions will not be removed by test generation,
since it does not process OPC logic.
USER RESPONSE:
See if the problem was reported early in the mode initialization sequence before all nets
were brought to known states. If this is the case, you may be able to safely ignore the
message. Otherwise, you will need to modify the sequence to remove any possibility of
three-state conflicts. Edit the sequence definition, then re-import the sequence and rerun
Verify OPC Sequences. Refer to On Product Clock Sequence Verification in the
Encounter Test: Guide 3: Test Structures for related information.
WARNING (TSC-019): [Severe] conflict_type three-state conflict detected during

simulation of event event_Id in sequence sequence_name.
EXPLANATION:
A definite three-state contention problem was discovered.
USER RESPONSE:
Edit the sequence definition to remove the contention. re-import the sequence and rerun
Verify OPC Sequences. Refer to On Product Clock Sequence Verification in the
Encounter Test: Guide 3: Test Structures for related information.
WARNING (TSC-020): [Severe] An oscillator was activated at event event_ID in

sequence sequence_name, but the design is not stable. Subsequent events will not be
properly synchronized with the oscillator.
EXPLANATION:
The event being referred to is a Wait_Osc(Cycles=0) event. This implies that subsequent
design activity will be affected by the coming events and the oscillator signal itself. This
design activity is predictable only if the design is currently in a stable state with the
oscillator running. Simulation of some number of oscillator cycles reveals that the design
is not yet stable, and therefore any further simulation will likely be invalid. Verification
proceeds from the current (arbitrary) state.
USER RESPONSE:
Check the sequence definition to make sure that all events were correctly specified for
predictable operation of the design. Correct the sequence, re-import it, and rerun Verify
OPC Sequences. Refer to On Product Clock Sequence Verification in the Encounter
Test: Guide 3: Test Structures for related information.
If the sequence is correct, make sure that the verifier is running enough oscillator cycles
to allow the design to settle down. The maximum number of cycles required is specified

as a parameter on the Wait_Osc event. If this number was too small, edit and re-import
the sequence definition and rerun Verify OPC Sequences.
If the sequence is correct and the Wait_Osc cycles parameter is large enough, then
check the design. If the design is incorrect, correct it and re-import it.
If none of the above corrective actions apply, then you may have a complex design which
circulates through two or more design states in the "steady state" condition. If this is the
case, consider using a Force event to prescribe the arbitrary state from which simulation
will proceed.
WARNING (TSC-021): [Severe] The cycle count specified in the Wait_Osc event
event_ID in sequence sequence_name did not allow the design to settle down.
Subsequent events may not be properly synchronized with the oscillator.
EXPLANATION:
The design was not in a steady-state condition after the specified number of oscillator
cycles. This is the number of oscillator cycles since the previous Wait_Osc event or the
previous Start_Osc event. Subsequent stimuli applied to the design with the free-running
oscillator will produce unpredictable results unless they are timed precisely in
relationship with the oscillator.
USER RESPONSE:
Make sure you intended to apply the input stimuli in lock-step with the oscillator pulses.
If this was intended, then make sure that the test equipment has the capability of doing
this. (You may have to consult with the manufacturer or whoever is responsible for the
test hardware.)
If it was not intended to apply the input stimuli in lock-step with the oscillator, then
examine the patterns and the design to make sure the correct wait duration is specified.
Correct the sequence definition, re-import it, and rerun Verify OPC Sequences. Refer to
On Product Clock Sequence Verification in the Encounter Test: Guide 3: Test
Structures for related information.
WARNING (TSC-023): [Severe] Test sequence sequence_name1 specifies setup

sequence sequence_name2, but sequence_name1 is not of type setup. The
sequences are not verified.
EXPLANATION:
Setup sequences have different restrictions than some other sequences; for example,
measure events are not allowed within a setup sequence. This check ensures that only
valid setup sequences will be used as setup sequences.
USER RESPONSE:

Either the setup sequence was given the wrong type, or the test sequence is referring to
the wrong setup sequence. Edit the sequence definitions by either changing the
sequence type of the setup sequence to "setup" or changing the name of the setup
sequence referred to in the test sequence. Then re-import the sequence definition before
using it in a test generation run. It will not be necessary to rerun Sequence Effectiveness
Checking.
Refer to "Test_Sequence" in the Encounter Test: Reference: Test Pattern Formats
WARNING (TSC-025): [Severe] Wait_Osc event encountered in pattern pattern_ID

which contains a event_name event in sequence sequence_name.
EXPLANATION:
Wait_Osc events indicate whether the events have to be synchronized with the oscillator.
If the scan operation is under control of a free-running oscillator, the scanop sequence,
not this pattern, must contain the Wait_Osc event.
USER RESPONSE:
If the scan operation is controlled by the oscillator, make sure that the custom scan
sequence definition contains the appropriate Wait_Osc events. In either case, remove
the Wait_Osc event from this pattern.
WARNING (TSC-028): [Severe] A Wait_Osc event, event id event_ID in sequence

sequence_name specifies pin pin_name, but this pin is not connected to an oscillator.
EXPLANATION:
Wait_Osc events indicate when the logic is "listening" to a free-running oscillator. This
Wait_Osc event specified a pin that is not currently connected to a free-running oscillator,
so it makes no sense. A Start_Osc event calling out the specific pin is required before
using a Wait_Osc event.
USER RESPONSE:
Check the sequence definition to make sure there is not a misplaced Stop_Osc event
that disconnected the oscillator before this Wait_Osc event was reached. Edit the
sequence definition by removing a Stop_Osc event or inserting a Start_Osc event so that
the oscillator is connected before the Wait_Osc event. If this is a test sequence with an
associated setup sequence, it is likely that you will want to put the Start_Osc event in the
setup sequence.
Refer to "Test_Sequence" in the Encounter Test: Reference: Test Pattern Formats

WARNING (TSC-029): Stop_Osc event for pin pin_name found in sequence

sequence_name but oscillator was not started on this pin.
EXPLANATION:
The Stop_Osc event has the same effect as a Stim_Clock event, but it is intended to be
used in cases where the pin was previously connected to a free-running oscillator. This
pin does not appear to have been connected to an oscillator, as no previous Start_Osc
event for this pin was in effect.
USER RESPONSE:
Make sure the pin was supposed to be oscillating. If so, then insert a Start_Osc event at
a previous point in the sequence where the oscillator was to have been connected. If not,
then change this Stop_Osc event to a Stim_Clock event.
WARNING (TSC-030): [Severe] Start_Osc event encountered in sequence

sequence_name but the specified pin pin_name is neither an OSC nor oTI.
EXPLANATION:
Oscillators can be connected only to pins that are defined to be OSCs or "tied" to an
oscillator (by having an oTI test function). The sequence checker will honor this event,
but you may run into trouble in manufacturing because the pin is not properly defined.
USER RESPONSE:
Make sure you specified the correct pin for the Start_Osc event. If this pin really is
supposed to be connected to a free-running oscillator, put an OSC or oTI test function
attribute on it and rebuild the test mode.
WARNING (TSC-035): [Severe] The setup sequence sequence_name for test sequence
sequence_name was not found.
EXPLANATION:
The test sequence refers to a setup sequence by name, but the setup sequence
definition has not yet been imported. You will not be able to run test generation until this
is resolved, either by removing the reference to the setup sequence or by importing it.
This condition will not affect the results of Sequence Effectiveness Checking.
USER RESPONSE:
Either import the setup sequence definition, or edit the test sequence definition by
removing or changing the reference to the setup sequence, and re-import the test
sequence. The situation must be corrected before running test generation. It is not
necessary to rerun Sequence Effectiveness Checking.

WARNING (TSC-037): [Severe] Signature observation sequences are not supported by

TSC.
EXPLANATION:
You specified a sequence that is not a test sequence. The Sequence Effectiveness
Checker works only on test sequences.
USER RESPONSE:
Make sure you did not intend to check a sequence with some other name. If this
sequence was just an extra sequence that was inadvertently specified, no action is
necessary.
WARNING (TSC-050): [Severe] An error was found in the lineholds for sequence
sequence_name.
EXPLANATION:
The linehold utility program found a problem in the lineholds specified within the
sequence definition. There should be other messages (prefix TLH) explaining what the
trouble is.
USER RESPONSE:
Look for some TLH messages to ascertain the cause of the trouble. Make sure you
intended to specify linehold information within the sequence definition. Correct the
problem by removing or correcting the Linehold information in the sequence definition,
re-import the sequence definition, and rerun Sequence Effectiveness Checking.
TSC-061 through TSC-130

WARNING (TSC-061): Latch latch_name, port clock pin port_number was not
exercised in sequence sequence_name.
EXPLANATION:
This sequence does not clock this port to the latch. Thus, faults in the logic that feeds this
latch port cannot be tested by this sequence.
USER RESPONSE:
sequence definition and rerun Sequence Effectiveness Checking.
WARNING (TSC-063): Clock PI clock_name was not pulsed in sequence

sequence_name.

EXPLANATION:
The named sequence does not use this clock.
USER RESPONSE:
If this clock was not intended to be used for testing, and the program detected no test
effectiveness problems, then you can ignore this message. If the clock was intended to
be used in some test sequence(s), then you must write one or more new sequences or
edit the existing ones to use this clock, re-import the sequence definitions, and rerun
Sequence Effectiveness Checking.
WARNING (TSC-064): The system data in latch latch_name, clocked by latch clock
clock_name, was overwritten when latch clock clock_name was pulsed in sequence
sequence_name, pattern pattern_id.
EXPLANATION:
System data was clocked into the specified latch by the latch clock during a prior clock
pulse. Another clock pulse occurred on a different port of the same latch that overwrote
the previous system data.
USER RESPONSE:
Make sure the sequence is pulsing the correct clocks. If they are, then you will need to
write another sequence to test logic feeding the latch ports that resulted in this error
message. Correct the sequence or write a new one, then re-import and rerun Sequence
Effectiveness Checking.
WARNING (TSC-065): The system data in latch latch_name was not captured by any
other latch or primary output by the end of sequence sequence_name.
EXPLANATION:
The identified latch is holding system data that was never captured by another latch or
PO. Thus, logic that feeds this latch will not be tested.
USER RESPONSE:
add a measure event to the test sequence to capture the data in this latch. Correct the
sequence, then re-import and rerun Sequence Effectiveness Checking.
WARNING (TSC-070): Latch latch_name was not exercised by any of the sequences
processed.
EXPLANATION:

The named latch is not clocked by any of the test sequences examined by this run. Thus,
logic that feeds this latch will not be tested.
USER RESPONSE:
Make sure the sequences are pulsing the correct clocks. If they are, then you will need
to write another sequence to test logic feeding the latches that resulted in this error
message. Correct the sequences or write a new one, then re-import and rerun Sequence
WARNING (TSC-071): Latch latch_name, port clock port_number was not exercised
by any of the sequences processed.
EXPLANATION:
The identified latch port is not clocked by any of the test sequences examined by this run.
Thus, logic that feeds this latch port will not be tested.
USER RESPONSE:
to write another sequence to test logic feeding the latch ports that resulted in this error
WARNING (TSC-080): number_clocks latch clock(s) fed by clock PI(s)

clock_name(s) were not exercised in sequence sequence_name. The first latch in the
group is latch_name and its clock is latch_clock_name.
EXPLANATION:
A group of latch ports were not clocked in this test sequence. These latch ports are fed
by the same set of clock PIs. Thus, logic that feeds these latch ports will not be tested.
USER RESPONSE:
WARNING (TSC-082): A port on latch latch_name was not exercised in sequence

sequence_name. The port is clocked by pin port_number.
EXPLANATION:
The identified latch port is not clocked or system data is not captured in this test
sequence. Thus, logic that feeds this latch port will not be tested.

USER RESPONSE:
WARNING (TSC-083): A port on latch latch_name was not exercised by any of the
sequences processed. The port is clocked by pin port_number.
EXPLANATION:
The identified latch port is not clocked by any of the test sequences examined by this run.
Thus, logic that feeds this latch port will not be tested.
USER RESPONSE:
WARNING (TSC-084): A PO measure event was not encountered in sequence

sequence_name.
EXPLANATION:
This sequence does not measure POs. Thus, faults in the logic that feed POs cannot be
tested by this sequence.
USER RESPONSE:
Make sure the sequence is measuring POs. If not, edit and re-import the sequence
definition and rerun Sequence Effectiveness Checking.
WARNING (TSC-085): A PO measure event was not encountered by any of the sequences
processed.
EXPLANATION:
POs were not measured by any of the test sequences examined by this run. Thus, logic
that feeds this PO will not be tested.
USER RESPONSE:
Make sure the sequences are measuring POs. Correct the sequences or write a new
one, then re-import and rerun Sequence Effectiveness Checking.

INFO (TSC-090): Latch error at latch_name results in number_faults static and

number_faults dynamic untested faults.
EXPLANATION:
The identified latch was not exercised or system data residing in the latch was not
captured. Thus, logic that feeds this latch will not be tested.
USER RESPONSE:
INFO (TSC-091): PO error results in number_faults static and number_faults

dynamic untested faults.
EXPLANATION:
The identified PO was not measured during this sequence. Thus, logic that feeds this
latch will not be tested.
USER RESPONSE:
Make sure the sequences are measuring the correct POs. If they are, then you will need
to write another sequence to test logic feeding the PO that resulted in this error message.
Correct the sequences or write a new one, then re-import and rerun Sequence
INFO (TSC-092): Latch/PO errors in sequence sequence_name result in

number_faults static and number_faults dynamic untested faults.
EXPLANATION:
The identified sequence contains untested static and dynamic faults because of latches
that were not exercised or system data that was not captured.
USER RESPONSE:
INFO (TSC-094): Latch/PO errors during the run results in number_faults static and
number_faults dynamic untested faults.

EXPLANATION:
The run contains untested static and dynamic faults because of latches that were not
exercised or system data that was not captured.
USER RESPONSE:
WARNING (TSC-098): An error occurred while loading the fault model. No fault information
will be provided. The run continues.
EXPLANATION:
The run requires a fault model file if fault information processing is desired. If the program
cannot find the fault model file, no fault information processing can be done. The run will
continue without providing fault information.
USER RESPONSE:
Ensure that a fault model file exists in the designs directory and that the appropriate
permission bits are set to make the file readable.
WARNING (TSC-100): [Severe] The file, file_name, is not writeable, therefore the
results of this TSCmain run cannot be saved.
EXPLANATION:
USER RESPONSE:
WARNING (TSC-101): [Severe] The file, file_name, is not readable, therefore the
results of this TSCmain run cannot be saved.
EXPLANATION:
USER RESPONSE:

WARNING (TSC-103): [Severe] The directory, directory_name, is not writeable,

therefore the results of this TSCmain run cannot be saved.
EXPLANATION:
USER RESPONSE:
writeable.
WARNING (TSC-104): [Severe] The directory, directory_name, is not readable,

therefore TSCmain cannot be run.
EXPLANATION:
USER RESPONSE:
readable.
WARNING (TSC-110): [Severe] Attempt to register experiment experiment_name on

EXPLANATION:
The reason for the failure cannot be determined by TSCmain. Processing terminates.
USER RESPONSE:
corrective action.
WARNING (TSC-111): [Severe] Attempt to register a dependency of

experiment|file against the model|experiment on the globalData file failed.
EXPLANATION:
The reason for the failure cannot be determined by MSV. Processing terminates.
USER RESPONSE:
corrective action.

WARNING (TSC-112): [Severe] Attempt to register file file_name on the globalData file
failed.
EXPLANATION:
USER RESPONSE:
WARNING (TSC-113): [Severe] Attempt to save file file_name in the globalData file
failed.
EXPLANATION:
USER RESPONSE:
Determine why the file could not be saved.
WARNING (TSC-120): [Severe] The TSC function, function_name, could not find the
file file_name.
EXPLANATION:
MSV attempted to open the file listed but the file does not exist. Processing terminates.
USER RESPONSE:
Ensure the file exists and rerun TSCmain.
WARNING (TSC-121): [Severe] The TSC function, function_name, was unable to

open the file (file_name).
EXPLANATION:
The program attempted to open the file listed but was unsuccessful. Processing
terminates.
USER RESPONSE:
Determine the reason (check things such as permission bits and file space), and rerun.
WARNING (TSC-122): [Severe] The TSC function, function_name, could not write
data to the file file_name.
EXPLANATION:

The program attempted to write to the file listed but was unsuccessful. Processing
terminates.
USER RESPONSE:
the file name spelling is correct), and rerun.
WARNING (TSC-123): [Severe] The TSC function, function_name, could not read
data from the file file_name.
EXPLANATION:
The program attempted to read from the file listed but was unsuccessful.
USER RESPONSE:
WARNING (TSC-124): [Severe] The TSC function, function_name, could not close the
file file_name.
EXPLANATION:
The program was unable to close the indicated file.
USER RESPONSE:
WARNING (TSC-125): [Severe] The file, file_name, has a file ID of file_ID1 in the
file header. The file ID should be file_ID2 in order to run this version of TSCmain.
EXPLANATION:
The program was unable to verify the file header for the filename listed. The file was
created with an old level of the program and cannot be processed by the current level.
USER RESPONSE:
Rerun with the current level of the program.
ERROR (TSC-130): No sequence definitions were found in the Sequence Definitions file.
EXPLANATION:

USER RESPONSE:


67
TSR - Scan and LSSD Flush Test
Messages
TSR-001 through TSR-360 on page 1975
TSR-001 through TSR-360

INFO (TSR-001): Scan Chain Test Generator Program level is date.
EXPLANATION:
Gives the last date the source code for the scan chain test generator was changed.
USER RESPONSE:
This message is potentially useful for debug. To eliminate the message, remove the
TSRDEBUG parameter from the command that invoked this program.
WARNING (TSR-010): The test generator ran into unresolvable conflicts while trying to
protect against three-state contention.
EXPLANATION:
There are three-state nets in the design that can not be protected against contention. No
primary input pattern was found to exist, consistent with the scan operation, that can
prevent three-state contention on all nets simultaneously. Scan chain test generation will
proceed, with the risk of generating simulator messages stating that three-state
contention has occurred.
USER RESPONSE:
Look for simulator messages that point out the three-state nets on which contention
actually occurs. In the extremely unlikely event that there are no such simulator
messages, you can ignore the TSR-010 message. In nearly all cases, there will be
contention causing the scan chain test to be truncated and rendering it almost useless.
You should first verify that you did not specify some lineholds which made it impossible
to protect the three-state nets. If lineholds were used, try again without lineholds If you

TSR - Scan and LSSD Flush Test Messages
get three-state contention in the absence of a linehold file, then you should add control
test points or redesign the logic so that the contention can not occur or is more easy to
prevent.
See "Three-State Logic" in the Encounter Test: Guide 1: Models for related
information.
WARNING (TSR-011): The test generator aborted while trying to protect against three-state
contention.
EXPLANATION:
There are three-state nets in the design that can not be protected against contention due
to practical limitations in the test generator, such as run time. Scan chain test generation
will proceed, with the risk of generating simulator messages stating that three-state
contention has occurred.
USER RESPONSE:
There are two possible courses of action if the simulator detects three-state contention
problems:
Change the design so that three-state contention can not occur. Then re-import
the design
Use whatever means may be available to find a contention-free pattern
consistent with the scan operation, and use a linehold file to direct the
generation of the test.
See "Three-State Logic" in the Encounter Test: Guide 1: Models for related
information.
ERROR (TSR-301): [Internal] A programming error has been detected during create LSSD
flush tests or create scan chain tests.
EXPLANATION:
The create lssd flush tests or the create scan chain tests routine got a bad return code
from one of the utility programs. This is probably due to a program error.
USER RESPONSE:
ERROR (TSR-302): Insufficient storage to allocate tablesize bytes for tablename

table.
EXPLANATION:

A storage request was denied for the indicated number of bytes to temporarily hold
information in the indicated table.
USER RESPONSE:
Check the design statistics to make sure the design is a reasonable size. Look for any
unusual conditions or messages that could indicate a problem. This table should not
overflow any reasonable workstation configuration. If you can not pinpoint a problem, try
running on a bigger machine, and if the problem persists, contact customer support (see
ERROR (TSR-309): [Internal] Error initializing model or TBD for flush/scan chain test
generation.
EXPLANATION:
The flush/scan chain test generation routine got a bad return code during its initialization
phase from a model access or test data access subroutine. This is probably due to a
program error.
USER RESPONSE:
ERROR (TSR-310): [Internal] Bad TBD return code during flush/scan chain test
generation.
EXPLANATION:
The flush/scan chain test generation routine got a bad return code from a test data
access subroutine (TBD). This is probably due to a program error.
USER RESPONSE:
ERROR (TSR-311): [Internal] Unable to interpret pin pinname in scanop sequence.

EXPLANATION:
A StartOsc, WaitOsc, SetScanData, or Pulse event within the scan operation was being
processed, but the translation to a pin index indicates this is not a pin.
USER RESPONSE:
ERROR (TSR-312): [Internal] Unable to initialize the test generator.

EXPLANATION:
An unrecoverable error was encountered. There is insufficient information available to
analyze the problem without programmer assistance.
USER RESPONSE:
ERROR (TSR-313): [Internal] Error return from the test generator.

EXPLANATION:
An unrecoverable error was encountered. There is insufficient information available to
analyze the problem without programmer assistance.
USER RESPONSE:
ERROR (TSR-320): No srtesttype test can be generated for any of the scan chains in
this design.
EXPLANATION:
srtesttype is either flush or scan. There are several reasons an LSSD flush test or
scan chain test can not be generated. If one of these applies to any scan chain, that scan
chain is ignored for purposes of generating the LSSD flush and scan chain tests. This
message means that for each scan chain, one of the following applies:
The scan chain register is not both controllable and observable.
The scan data input is not a contacted primary input.
The scan data output is not a primary output.
The scan data output is not contacted (applies only to LSSD flush test).
USER RESPONSE:
Make sure you are running in the correct test mode. The test mode must have one or
more scan chains that meet all the above conditions.
You can not run the stored-pattern flush or scan chain test in a typical LBIST test mode,
where the scan chains are connected to a PRPG and MISR.
Check your design to verify that one or more of the above listed conditions applies to
each of the scan chains. Correct the design as necessary and re-import the design.

If your design and test mode are correct, this message means that there is no flush nor
scan chain test and further, that scan-based test generation will likely be ineffective on
this design unless it is primarily combinational. You will have to rerun test generation
without requesting a flush or scan chain test, and may also have to request sequential
test generation. Lacking a flush or scan chain test makes it more difficult to diagnose
failures; requiring sequential test generation makes it difficult to achieve fault coverage
objectives and may also have serious impacts on both test generation run time and test
application time.
WARNING (TSR-322): [Severe] The LSSD flush test for this design requires holding one
or more scan clock pseudo PIs "on" while toggling the scan data input. It must be generated
manually. This automatically generated test will not work in the hardware.
EXPLANATION:
The design has one or more pseudo primary inputs designated as shift A or shift B
clocks. The LSSD flush test is not directly created from the custom scan sequence, so
the Stim_PPI events that turn on and hold the shift A and shift B pseudo PIs are almost
guaranteed not to work in the hardware.
USER RESPONSE:
Do not commit this test to be sent to manufacturing. If this job included other tests
besides the scan chain LSSD flush test, omit this test and rerun the job.
If you want an LSSD flush test, you should first export the uncommitted vectors and edit
the resulting TBDpatt file, inserting the necessary primary input stimuli to produce the
correct states on the cut points represented by the scan clock pseudo primary input(s).
Then you can import this edited LSSD flush test and simulate it.
ERROR (TSR-330): The scansequence is missing for scan section

scansectionnumber.
EXPLANATION:
Within the scan section identified by scansectionnumber, no scan sequence was
found. The scan chain test generator uses the scan sequence definition to generate
tests. Since the scan sequence definition is missing for one or more scan sections, no
scantest will be generated.
USER RESPONSE:
If the scan sequence(s) were user-specified, then there should have been messages
appearing when the test mode was built. The indicated scan section should invoke (via
the Apply event) another sequence that has the type of scansequence. Correct the
sequence definition file that was used for building the test mode; then rebuild the test
mode. If Encounter Test generated the scan sequence automatically, this message

indicates a program error. Contact customer support (see Contacting Customer

ERROR (TSR-340): This design has number scan sections. Multiple scan sections are not
supported by the LSSD flush test generator.
EXPLANATION:
The scan chain test program does not generate an LSSD flush test if there is more than
one scan section. If this message appears, number should be greater than 1, and an
LSSD Flush Test therefore cannot be generated automatically.
USER RESPONSE:
Make sure the scan sequences were defined properly. If there are really more than one
scan section, then you will not be able to generate an LSSD Flush Test automatically.
ERROR (TSR-360): The values specified for the zeros and ones parameters must add up
to be an odd number.
EXPLANATION:
The total of the values specified for the "zeros" and "ones" parameters was an even
number. For the dynamic scanchain tests, the total of the values specified for the "zeros"
and "ones" parameters must add up to be an odd number; if the total is an even number,
processing will terminate.
USER RESPONSE:
Either let "zeros" and "ones" defaults, or specify values for them such that the sum of the
two values is an odd number.
ERROR (TSR-361): A value specified for the zeros or ones parameters was too large; the
maximum allowable value for this part is number.
EXPLANATION:
The value specified for either the "ones" or "zeros" parameters (or both) was too large.
The maximum value for the "ones" or "zeros" parameter is 20% of the length of the
longest scan chain. For extremely small parts, if 20% of the longest scan chain is less
than 5, the maximum allowed value is 5 instead of the 20% restriction. If the value
specified for either parameter exceeds that, processing will terminate.
USER RESPONSE:
Either let "zeros" and "ones" default, or specify a smaller value.

INFO (TSR-362): format=normal was specified for a BOUNDARY=MIGRATE test mode.

normal format is not allowed due to non-contacted scan data inputs, run will continue with
format=simplified.
EXPLANATION:
The test mode being run was created with BOUNDARY=MIGRATE, which must be run
with format=simplified specified or defaulted. The job will continue with the correct
format.
USER RESPONSE:
No response is neccessary; remove format=normal from the command line to run
without getting this message.
ERROR (TSR-363): The pattern or patternfile keywords cannot be specified when

running with a test mode which uses compression or decompression. The run will terminate.
EXPLANATION:
The test mode being run uses compression or decompression. The pattern and
patternfile options are not allowed for the scan chain test for this testmode.
USER RESPONSE:
Remove the pattern or patternfile keywords from your command, or specify a
different test mode.
ERROR (TSR-364): Invalid character specfied in the pattern. Only 0s and 1s are allowed.
The run will terminate.
EXPLANATION:
The repeating pattern specified in the pattern keyword or in the specified patternfile
contained characters other than 0, 1 or blank.
USER RESPONSE:
Change the pattern string so that it contains only 0s and 1s. Blanks are also allowed.
ERROR (TSR-365): The repeating pattern specified in the pattern keyword or in the
specified patternfile did not contain both 0s and 1s.
EXPLANATION:
The repeating pattern specified in the pattern keyword or in the specified patternfile
did not contain both 0s and 1s.
USER RESPONSE:

Change the pattern string so that it constains at least one '0' and at least one '1'.

68
TSS - Signature Observation Sequence
Messages
TSS-001 through TSS-117 on page 1983
TSS-001 through TSS-117

INFO (TSS-001): TSSmain has started.
EXPLANATION:
Signature observation sequence creation/checking has started.
USER RESPONSE:
INFO (TSS-002): TSSmain has ended.

EXPLANATION:
Signature observation sequence creation/checking has ended.
USER RESPONSE:
INFO (TSS-003): TSSmain found no sigobs sequences in the TBDseq file.

EXPLANATION:
No signature observation sequences were detected. Checking did not occur.
USER RESPONSE:
Create the signature observation sequence before running TSSmain.

TSS - Signature Observation Sequence Messages
WARNING (TSS-004): Testmode testmode has not yet been built, this sigobs cannot be
created.
EXPLANATION:
The named testmode is used in the signature observation sequence, but it has not
been built yet. The testmodes used in the sequence must exist before the target
sequence can be created.
USER RESPONSE:
Build the named testmode and rerun.
INFO (TSS-005): Processing sigobs signature_observation_sequence_name.

EXPLANATION:
The referenced signature observation sequence is being processed.
USER RESPONSE:
INFO (TSS-006): Sigobs signature_observation_sequence_name marked

Pass | Fail in the TBDseq file.
EXPLANATION:
The signature observation sequence has been checked and the resulting pass or fail
indication has been written into the TBDseq file.
USER RESPONSE:
INFO (TSS-007): TSSmain is creating a sigobs sequence named

signature_observation_sequence_name.
EXPLANATION:
A signature observation sequence was created for this test mode with the name in the
message.
USER RESPONSE:
INFO (TSS-008): TSSmain is creating a sigobsrtn sequence named

signature_observation_return_sequence_name.

EXPLANATION:
A sigobsrtn sequence was created for this testmode with the name in the message.
USER RESPONSE:
None.
ERROR (TSS-009): No signature observation mode was specified in the mode definition or
assign file.
EXPLANATION:
The observation of the MISRs for this testmode is performed by the serial MISR
observation method (a sigobs sequence) and the MISRs are to be reset to the all zero
state by that sequence as indicated by the specification of TEST_SERIAL_RESET for the
type when SIGNATURES=YES was included in the TEST_TYPES statement in the mode
definition or assign file.
When the TEST_SERIAL_RESET option is used the SIGNATURE_OBSERVATION_MODE
must also be included in the mode definition or assign file.
USER RESPONSE:
Include the SIGNATURE_OBSERVATION_MODE in the mode definition or assign file.
ERROR (TSS-010): The signature observation testmode specified in the sequence file does
not match mode definition file specification.
EXPLANATION:
definition or assign file. When the TEST_SERIAL_RESET option is used the
SIGNATURE_OBSERVATION_MODE must also be included in the mode definition or
assign file. The testmode identified in the Going_To_Mode object for the sigobs
sequence does not match the the testmode identified by the
SIGNATURE_OBSERVATION_MODE statement of the mode definition or assign file.
USER RESPONSE:
Correct the mode definition or assign file and the sigobs sequence of the sequence file
so that they match.
ERROR (TSS-011): The sequence file contains multiple sigobs sequences.

EXPLANATION:
definition or assign file. When the TEST_SERIAL_RESET option is used the
SIGNATURE_OBSERVATION_MODE must also be included in the mode definition or
assign file. The sequence file contains multiple sigos sequences.
USER RESPONSE:
Remove the unneeded sequences from the file.
012 ERROR (TSS-012): The testmode specified in the sigobsrtn sequence is not the
current testmode.
EXPLANATION:
The provided sigobsrtn sequence must return to the current testmode.
USER RESPONSE:
Correct the Going_To_Mode object for the sigobsrtn sequence to identify the current
testmode.
ERROR (TSS-013): The sequence file contains multiple sigobsrtn sequences.

EXPLANATION:
Only one sigobsrtn sequence is allowed in the sequence file.
USER RESPONSE:
Remove the unneeded sequences from the file.
ERROR (TSS-014): The sequence file contains either a sigobs sequence or a signobsrtn
sequence but not both.
EXPLANATION:
When a custom sigobs is specified in the sequence file a custom sigobsrtn sequence
must also be included. When a custom sigobsrtn is specified in the sequence file a
custom sigobs sequence must also be included.
USER RESPONSE:
Correct the sequence file to contain both a sigobs sequence and a sigobsrtn sequence.

ERROR (TSS-099): There are no MISRs present in this testmode. Processing terminates.
EXPLANATION:
Verification of the observation sequence is only for test modes that include MISRs.
USER RESPONSE:
Change the testmode keyword to point to a testmode with MISRs and rerun.
ERROR (TSS-100): TSSmain could not load the file_type.

EXPLANATION:
The file identified in the message could not be loaded. This indicates one of the following
conditions:
The application that creates the file was not run.
The file has been deleted or corrupted.
The machine being used for execution lacks sufficient memory to include the
data.
USER RESPONSE:
Ensure the pre-requisite applications have been run and that the files they created still
exist in the part directory. Look for other messages in the log indicating a memory
problem. Contact customer support (see Contacting Customer Service on page 23) for
additional help if necessary.
WARNING (TSS-101): [Severe] TSSmain could not initialize TBD.

EXPLANATION:
TBD is the internal program used to access the TBDseq file. It is required to perform
checking.
USER RESPONSE:
Review the log for previous TBD messages that indicate the cause of the problem.
additional help if necessary.
WARNING (TSS-102): [Severe] TSSmain could open TBDseq file.

EXPLANATION:
The TBDseq file is the file that contains the observation sequence. The program was
unable to open the file, therefore no processing occurred.

USER RESPONSE:
Ensure no other applications that use sequences are running and rerun.
WARNING (TSS-103): [Severe] TSSmain could close TBDseq file.

EXPLANATION:
The TBDseq file is the file that contains the observation sequence. The program was
unable to close the file, therefore the contents may be suspect.
USER RESPONSE:
Ensure no other applications that use sequences are running and rerun.
WARNING (TSS-104): [Severe] No parent mode exists.

EXPLANATION:
The parent test mode must exist before the target test mode that uses it is defined. The
parent testmode was not found.
USER RESPONSE:
Ensure the Begin_testmode statement in the sequence points to the correct name.
Ensure the the parent testmode has been built prior to building the target test mode.
WARNING (TSS-105): [Severe] TSSmain could not find an observation testmode for
sigobs sequence sequencename.
EXPLANATION:
In order to observe the MISR, there must be an observation testmode defined that allows
the latches to be scanned out. This observation testmode could not be found.
USER RESPONSE:
Provide an observation testmode.
WARNING (TSS-106): In_Test_Mode name was encountered. Node_name is at the

wrong value. Expected value = value; Actual value = value
EXPLANATION:
The referenced node was detected with a wrong value when the In_Test_Mode pattern
was applied.
USER RESPONSE:

Correct the signature observation sequence to ensure that setting the control PI does not
cause the referenced node to go to the Actual value.
WARNING (TSS-107): Latch latch_Name has more than 1 clock input which is not off.
EXPLANATION:
The referenced latch has more than clock that is not off; either both are on, or one or
more of the clocks are at X. This means more than one port of the latch may be active at
the same time, and the value in the latch is unknown.
USER RESPONSE:
Redefine the logic or the testmode to ensure only one clock is on at a time; and the other
clocks are off (not X).
WARNING (TSS-108): Latch latch_Name is changed by the signature observation

sequence.
EXPLANATION:
The referenced latch changes value when the signature observation sequence is
applied.
USER RESPONSE:
If this latch must maintain its value while observing the MISR, change the design, the test
mode, or the signature observation sequence to ensure the latch doesnt change value.
WARNING (TSS-109): Latch latch_Name does not have a sensitized 1/0 path to PO
pin_Name following the Measure_PO event.
EXPLANATION:
There is no path from the referenced latch that allows either value, 1 or 0, to propagate
to the required primary output as a result of the Measure_PO event.
USER RESPONSE:
Redefine the test mode to allow a path from the referenced latch to the referenced PO.
WARNING (TSS-110): [Severe] Representative MISR Latch latch_Name is not an RML

in OTM.
EXPLANATION:
The representative MISR latch (RML) named in the message is not a representative
measure latch in the observation test mode (OTM).

All MISR latches in the target testmode must be able to be observed in the observation
test mode.
USER RESPONSE:
Redefine the observation test or select a different observation test mode and rerun.
WARNING (TSS-111): [Severe] Severe error write locking file_name.

EXPLANATION:
A severe error occurred when attempting to write-lock the file.
USER RESPONSE:
Correct the write-locking error and rerun.
WARNING (TSS-112): [Severe] TSSmain was unable to readlock circuit.

EXPLANATION:
The program was unable to read-lock the test mode.
USER RESPONSE:
Resolve the read-lock condition and rerun.
WARNING (TSS-113): [Severe] TSSmain was unable to readlock testmode test_mode.

EXPLANATION:
The program was unable to read-lock the test mode.
USER RESPONSE:
Resolve the read-lock condition and rerun.
WARNING (TSS-114): TSSmain terminating due to TBDread failure.

EXPLANATION:
The program terminated during processing of input vectors.
USER RESPONSE:
Resolve the condition and rerun.
WARNING (TSS-115): Oscillator(s) running at end of sigobs.

EXPLANATION:

The program has detected running oscillator(s) at the end of a signature observation
sequence.
USER RESPONSE:
Resolve the condition and rerun.
WARNING (TSS-116): The signature observation mode has TI latches that are not TI at the
same value in the BIST mode. The sigobs sequence will require manual editing.
EXPLANATION:
Encounter Test has no tool that can automatically determine how to initialize fixed value
latches, particularly without affecting the channel and MISR latches that are desired to
be scanned out. The fixed value TI latches for the signature observation mode must be
initialized but Encounter Test is unable to do it.
As a possible help in creating the signature observation sequence, an automatic
sequence is being generated, but it will not pass the checks, and is almost guaranteed
not to work.
USER RESPONSE:
Export the sequence definitions for this test mode and copy the signature observation
sequence definition into a new file. Edit this sequence definition by adding the necessary
sequencing to initialize the TI latches for the observation test mode. Then import the
sequence definition and create the signature observation sequence. Refer to Reading
Sequence Definition Data (TBDseq) in the Automatic Test Pattern Generation User
Guide.
WARNING (TSS-117): [Severe] The designated signature observation mode mode is not
scannable, and therefore cannot be used to create an automatic signature observation
sequence.
EXPLANATION:
When Encounter Test automatically creates a signature observation sequence, it
assumes a scan operation will be used. A scan operation is not possible in the
designated signature observation mode, so Encounter Test is unable to create the sigobs
sequence.
USER RESPONSE:
Make sure you specified the correct name for the signature observation mode. If this is
the correct name, then the signature will have to be observed by some means other than
scanning, and you will have to write this sequence yourself. After coding the sequence
in TBDpatt form, run Import Sequence Definition data, then create the signature

observation sequence to check the sequence. Refer to Reading Sequence Definition

Data (TBDseq) in the Automatic Test Pattern Generation User Guide.

69
TST - Sequential Stored Pattern Test
Generation Messages
TST-001 through TST-405 on page 1993
TST-001 through TST-405

WARNING (TST-001): [Internal] Unrecognized simulation function found for the block. The
test generator does not support the specified logic primitive. If only supported logic primitives
were used, then contact customer support for assistance (see Contacting Customer Service
on page 23). Otherwise, use the correct logic primitives and rerun the design.
EXPLANATION:
Unrecognized simulation function found for a block in the design. The test generator does
not support the specified logic primitive.
USER RESPONSE:
Ensure that logic primitives used are supported by Encounter Test. See "Modeling Logic
Structures and Attributes" in the Encounter Test: Guide 1: Models .
If only supported logic primitives were used, then contact customer support (see
Contacting Customer Service on page 23) for assistance. Otherwise, use the correct
logic primitives and rerun.
WARNING (TST-002): [Internal] Unsupported fault type

EXPLANATION:
The test pattern generator encountered a non-supported fault type. This particular fault
will be skipped. Static test pattern generation does not handle non-DC faults.
USER RESPONSE:
Ensure that fault types are supported by Encounter Test and rerun the design.

TST - Sequential Stored Pattern Test Generation Messages
WARNING (TST-004): Unable to load the logic model context

EXPLANATION:
The test generator was unable to load information related to the logic model. The logic
model files might not exist, or there might not be enough storage on the machine which
your are running on.
USER RESPONSE:
Ensure that the Encounter Test logic model files exist. Also ensure that there is adequate
storage on the machine to run the design.
WARNING (TST-005): Unable to load design logic model. The logic model files might not
exist, or there might not be enough storage on the machine which you are running on. Ensure
that the Encounter Test logic model files exist, and that there is adequate storage on the
machine to run the design.
EXPLANATION:
The test pattern generator was unable to load the logic model. The logic model files might
not exist, or there might not be enough storage on the machine which you are running on.
USER RESPONSE:
Ensure that the Encounter Test logic model files exist. Also ensure that there is adequate
storage on the machine to run the design.
WARNING (TST-006): Unable to set the test mode. Ensure that the test mode has been
defined.
EXPLANATION:
The test pattern generator was unable to load the test mode.
USER RESPONSE:
Ensure that the test mode has been defined, and rerun.
WARNING (TST-007): Unable to load design model access methods

EXPLANATION:
USER RESPONSE:
WARNING (TST-012): Unable to access the fault model

EXPLANATION:
The test pattern generator was not able to access the fault model.
USER RESPONSE:
WARNING (TST-014): [Internal] An internal program error occured. Processing will

continue. Test data produced is valid but coverage may be impacted. If the test coverage is
not acceptable, contact customer support for assistance (see Contacting Customer Service
on page 23).
EXPLANATION:
An error internal to the test pattern generator has occurred. This error does not result in
corrupted data, however it may impact the test coverage.
USER RESPONSE:
If the test coverage is not acceptable, contact customer support (see Contacting
WARNING (TST-016): [Internal] Error while accessing vectors. Contact customer support
(see Contacting Customer Service on page 23) for assistance.
EXPLANATION:
The test pattern generator could not access the Cadence test vectors.
USER RESPONSE:
assistance.
WARNING (TST-021): Memory allocation error. Kill unneccessary processes on the

machine, or run on a machine with more memory.
EXPLANATION:
The test pattern generator failed to allocate the required memory.
USER RESPONSE:
Kill unneccessary processes on the machine, or run on a machine with more memory.
WARNING (TST-027): [Internal] Error occured while reading/writing parameter bank.

Contact customer support (see Contacting Customer Service on page 23) for assistance.
EXPLANATION:

Error while accessing test generation parameters.

USER RESPONSE:
assistance.
WARNING (TST-028): Design has number asynchronous loop(s)

EXPLANATION:
The design has asynchronous loops. This may result in inaccurate results.
USER RESPONSE:
generation results.
WARNING (TST-029): Unable to retrieve line hold information. Ensure that the linehold file
exists and that it is created correctly.
EXPLANATION:
USER RESPONSE:
Ensure that a linehold file exists and that it is created correctly. Then rerun the design.
INFO (TST-038): Estimated sequential depth: number

EXPLANATION:
The program estimated the sequential depth of the design to be N; for example, in the
worst case, it may take N time images to initialize a latch or flip-flop to a given logic value.
USER RESPONSE:
WARNING (TST-043): rrfa=yes was specified, but rrfa data was not available. Run will
continue using SCOAP heuristics.
EXPLANATION:
rrfa=yes was specified, but no RRFA (Random Resistant Fault Analysis) data was
found. The run will continue using SCOAP heuristics instead of RRFA data.
USER RESPONSE:

If you want to use RRFA data to guide test generation, then run Random Resistant Fault
Analysis (under Testability Analysis), then rerun test generation.
WARNING (TST-044): Clock chopper table could not be built. Clock choppers will not be
handled correctly; resulting test coverage may be low.
EXPLANATION:
An internal table could not be built. There may be preceding messages explaining why.
The run will continue, but coverage may be low due to incomplete handling of clock
choppers.
USER RESPONSE:
Look at preceding messages to determine why the table could not be built, and fix any
problems indicated. You may need to run on a larger machine. Then rerun test
generation.
WARNING (TST-045): Three-state net hierarchical netnameof the unsafe

net is unsafe and cannot be protected. Tests will be generated but may cause contention for
this net.
EXPLANATION:
There is a 3-state net which, in the test generation state, may have 3-state contention
and therefore cannot be protected. The run will continue, but coverage may be low due
to 3-state contention.
USER RESPONSE:
Look at the design and the TSV run to determine if the design will actually have 3-state
contention on this dott. If there are design problems causing contention, then fix them
and rerun.


70
TSU - Segment/Symbol Utilities
Messages
TSU-001 through TSU-200 on page 1999
TSU-001 through TSU-200

WARNING (TSU-100): [Severe] Failed to open segment file filename.
EXPLANATION:
The system failed to open the file filename. The most likely causes are incorrect file
name for an existing file, or no permission to access the file.
USER RESPONSE:
Make sure the file qualifiers are correct and permissions are valid.
INFO (TSU-101): Insufficient memory to map the number of bytes-byte file

filename.
EXPLANATION:
The system failed to map the file filename because there was not enough memory to
load the file.
USER RESPONSE:
Determine why the system failed. If possible, terminate some applications and try again.
WARNING (TSU-102): [Severe] Max Segments (max_segs) mapped.

EXPLANATION:
The internal limit of max_segs mapped segments has been reached. This is an internal
programming limit that can be extended if you contact your support group. The most
likely cause of this is an application using too much storage.

TSU - Segment/Symbol Utilities Messages
USER RESPONSE:
Contact your support group and inform them of the error. Further analysis may show that
the limit needs to be increased.
WARNING (TSU-103): [Severe] sys_reason Bad return code from unmap() = error.
EXPLANATION:
The system failed to unmap a file, for reasons specified in sys_reason.
USER RESPONSE:
again.
WARNING (TSU-105): [Severe] sys_reason Error trying to find size of file filename.
EXPLANATION:
The system failed to report the size of file filename. The reason for the failure is provided
by sys_reason.
USER RESPONSE:
again.
WARNING (TSU-110): [Severe] Application error: Unknown Segment address

(bad_pointer).
EXPLANATION:
An application program has provided a bad pointer. It does not match any known mapped
areas.
USER RESPONSE:
WARNING (TSU-111): [Severe] sys_reason Error unmapping Segment (area).

EXPLANATION:
The system failed to unmap the area pointed to by area. The reason for the failure is
provided by sys_reason.
USER RESPONSE:

again.
WARNING (TSU-112): [Severe] sys_reason Error closing file filename.

EXPLANATION:
The system failed to close the file filename. The reason for the failure is provided by
sys_reason.
USER RESPONSE:
again.
WARNING (TSU-121): [Severe] sys_reason Error unmapping Segment (ptr1). File

filename to be mapped disp = offset and size = size1. Original file size was
orig_size. File was mapped to (ptr2. Attempting to free size size2.
EXPLANATION:
The system failed to unmap a portion of file filename. The reason for the failure is
provided by sys_reason. We were attempting to free a portion of mapped area to allow
for extending the file. The various variables printed can help the application programmer
to debug the problem if it is not due to a system failure.
USER RESPONSE:
again. You may need to contact your support group if this problem persists.
WARNING (TSU-122): [Severe] sys_reason Error mapping anonymous Segment

(pointer).
EXPLANATION:
The system failed to map a free section of memory starting at the address pointer. The
reason for the failure is provided by sys_reason.
USER RESPONSE:
again.
WARNING (TSU-123): [Severe] sys_reason Error attempting to seek to offset in file

filename.
EXPLANATION:

The system failed to seek to the offset offset within the file filename. The reason for the
failure is provided by sys_reason.
USER RESPONSE:
again.
WARNING (TSU-124): [Severe] sys_reason Error attempting to append numbytes

bytes to file filename.
EXPLANATION:
The system while attempting to append size bytes to file filename. The reason for the
failure is provided by sys_reason.
USER RESPONSE:
again.
WARNING (TSU-131): [Severe] Error mapping file filename. Due to Bugs in the AIX3.2
mmap() function, it is not possible to map this file. The system fails..
EXPLANATION:
The system failed trying to map a very large file, filename. The reason for the failure is
due to a system limitation.
USER RESPONSE:
WARNING (TSU-132): [Severe] Error mapping file filename. No Segments available.

This implies that the system is out of memory.
EXPLANATION:
The system failed to map file filename. The reason for the failure is due to a system
limitation, most likely because there is insufficient memory available.
USER RESPONSE:
Check that the available swap space is sufficient to run this job.
INFO (TSU-133): Segment of size numBytes at address address for file filename.
EXPLANATION:

This message provides some additional information to help diagnose problems when file
mapping fails. This chunk of storage (called a segment) is comprised of numBytes bytes
of memory and is located at address in memory and represents a mapping for file
filename.
Note: a filename of TFWsm represents the Encounter Test Framework Storage
Manager and such entries reflect memory used for normal application data storage and
does not represent a real file.
USER RESPONSE:
INFO (TSU-134): Number of mapped segments = numSegs. Total Segment storage space
allocated for files = numBytes1 Bytes. Total Segment storage space allocated for pages =
numBytes2 Bytes.
EXPLANATION:
This message provides some additional information to help diagnose problems when file
mapping fails. There are numSegs segments in use by the Encounter Test Segment-
storage Utility. Of these, numBytes1 bytes are for mapping files and numBytes2 are for
mapping temporary storage - usually for malloc or paging space use.
USER RESPONSE:
ERROR (TSU-200): Error closing paging dataset filename. Reason:

failure_reason
EXPLANATION:
An internal paging file used by Encounter Test could not be closed. The reason for the
failure is also specified. Some reasons for the failure may include inadequate space in
the file system, or improper file permissions.
USER RESPONSE:
If you cannot correct the error based on the reason specified, contact customer support
(see Contacting Customer Service on page 23) for assistance.


71
TSV- Test Structure Verification
Messages
TSV-001 through TSV-050 on page 2005

TSV-001 through TSV-050

WARNING (TSV-001): [Severe] Feedback exists from objectName to itself.
EXPLANATION:
A signal path was found extending from the specified object to itself without encountering
any clocked memory elements.
Guideline or Restriction:
Guideline TB.2 states that no signal outside clocked latches may feed back upon itself
unless exclusive gating logic exists to prevent the signal from feeding itself.

TSV- Test Structure Verification Messages
The generation of this violation may be affected by the verify_test_structures

constraints option. Refer to the description of this keyword in the
verify_test_structures section of the Encounter Test: Reference: Commands.
Intent:
Feedbacks may cause oscillations, races or memory-like behavior in logic, which
complicates the test generation process. Encounter Test Design Guidelines require all
internal memory elements to be implemented in clocked latches or RAMs.
USER RESPONSE:
Select the specific message from the Specific Message List. This updates the
schematic display to show the feedback path, with the design state required to
enable the path.
If the feedback is not obvious, use Actions on the Encounter Test View
Schematic Window to identify the individual blocks, pins, and nets comprising
the feedback.
To correct the deviation, do one of the following:
Use a Encounter Test supported latch in place of the feedback loop.
Use a Test Inhibit (TI) or TIE block signal to block the feedback.
WARNING (TSV-002): [Severe] Mutual Exclusive Gating (MEG) checking aborted with the
specified EFFORT level while processing this message:
Feedback exists from objectName to itself.
EXPLANATION:
verify_test_structures looks for mutually exclusive (MEG) gating to render this
condition inoperative, but this message indicates verify_test_structures stopped
checking for gating that would prevent the error before reaching a resolution.
verify_test_structures uses the specified EFFORT level to determine how much
time and effort it should expend in trying to prove that the conditions that cause the
violation cannot occur.
If the MEG checking completes and the violation message is issued, then conditions
exist that cause the violation. If the MEG checking aborts before completion then the
conditions which produce the violation may or may not be possible.
A signal path was found extending from the specified object to itself without encountering
any clocked memory elements.

Guideline TB.2 states that no signal outside clocked latches may feed back upon itself
unless exclusive gating logic exists to prevent the signal from feeding to itself.
verify_test_structures section of the Encounter Test: Reference: Commands
Intent:
Feedbacks may cause oscillations, races or memory-like behavior in logic which
complicates the test generation process. Encounter Test Design Guidelines require all
internal memory elements to be implemented in clocked latches or RAMs.
USER RESPONSE:
Select the specific message from the Specific Message List. This updates the
schematic display to show the feedback path.
If the feedback is not obvious, use Actions on the Encounter Test View
Schematic Window to identify the individual blocks, pins, and nets comprising
the feedback.
Use a Encounter Test supported latch in place of the feedback loop.
Use a Test Inhibit (TI) or TIE block signal to block the feedback.
If you suspect this is not a true feedback, rerun this test with a higher effort level.
The default effort level if none was specified is effort=medium which is
equivalent to effort=5. To rerun this test add reruntests=yes to the
command line. Increasing the effort level may cause the test to run longer, and
the test may still abort on this violation.
WARNING (TSV-003): [Severe] Edge clocks (EC/ES) are present in the test mode which
has a scan type of LSSD.
EXPLANATION:
Encounter Test supports ECs (identified with an EC or ES flag) only for General Scan
Design (GSD) support. The current test mode specifies a scan type of LSSD.
Intent:
LSSD restricts memory elements to be level sensitive. ECs are not allowed in LSSD.
USER RESPONSE:

Select the specific message from the Specific Message List. The product is
displayed as a large block with its input and output pins identified. The ECs are
identified by a unique color. The default is red. The design state is set to the Test
Inhibit state.
To analyze the message:
Use the mouse pointer to verify the ECs. The Information Window will show the
test function pin attributes which verify_test_structures used to identify
the pin as an EC.
To correct the deviation, do the following:
- If the product contains edge-triggered devices, or a relaxed scan strategy is
desired, select a mode definition file which specifies a scan type of GSD and
reprocess the design.
- If you desire to process the product with an LSSD scan type, then change the
test function pin attributes of the highlighted pins to the appropriate values for
LSSD (AC, AS, BC, BS, PC, PS, or SC).
INFO (TSV-006): Analyze Test Clocks Control of Memory Elements was invoked. However,
there are no active memory elements on the circuit.
EXPLANATION:
Analyze Test Clocks Control of Memory Elements was invoked but there are no active
memory elements on the product under test.
USER RESPONSE:
WARNING (TSV-007): The product under test has multiple Output Inhibit (OI) pins.
EXPLANATION:
As Encounter Test guideline TBL.5 states, Encounter Test supports only one OI pin. The
OI is used to ensure that noise generated by output devices simultaneously changing
values does not occur. If multiple OI pins are present, Encounter Test does not know the
order in which they should be set, so it will set all OI pins in the same test pattern.
This may cause multiple output devices to change simultaneously and noise problems
may still exist.
Intent:

This limitation is required so that Encounter Test does not require additional user input
concerning the staging of the simulation of the OI pins. For more information, refer to
"Guideline TBL.5 - Output Inhibit (OI) Test Function" in the Encounter Test: Guide 3:
Test Structures.
USER RESPONSE:
Select the specific message from the Specific Message List. The schematic
display is updated to show the design with the OI pins identified with a default
color. The default color is red. The design is set to the Test Inhibit state.
To correct the deviation, identify a single pin to be used as an OI. It should
control all three-state drivers (TSDs) to high impedance.
WARNING (TSV-008): [Severe] Clock objectName on memory element objectName

was not off (at logic zero) in the Test Inhibit and Clocks off state.
EXPLANATION:
Encounter Test "Guideline TB.1 - Clocked DC Latches" and Encounter Test "Guideline
TB.4 - Identification of Clock Pins state that memory elements (latches and arrays) must
have all clock inputs off (at logic zero) when in the Test Inhibit and Clocks off state. In
addition, the Guidelines ensure that arrays contents and Non-Scan Latches (L5s) will not
change value during the Level Sensitive Scan Design (LSSD) operation.
Intent:
The intent of this check is to verify that all memory elements (latches and RAMs) are
controlled so they can never change values unless a clock pin is active. This allows
Encounter Test to produce race free tests. For more information, refer to GSD Analyze
Test Clocks Control of Memory Elements in the Encounter Test: Guide 3: Test
Structures.
USER RESPONSE:
Select the specific message from the Specific Message List. The block is
displayed and the pin with the incorrect value is identified by a unique color. The
default is red. The simulation state listed in the message is applied.
- Use the mouse pointer to verify the displayed block. The Information Window
indicates the pins of interest and their expected values for the specified state.
- Trace backward from the highlighted pin to identify the source of the incorrect
value.

For more information, refer to "Clock Affiliation" in the Encounter Test: Guide 3:
Test Structures.
To correct the deviation, modify the design or change the test function pin
attributes so the clock input is properly controlled off.
INFO (TSV-009): The product under test has memory element(s) active in the current mode,
but no clock pins are defined.
EXPLANATION:
Guidelines TB.2 and TB.4 state that latches and RAMs must be controlled by the clock
pins of the product, so the contents of the memory elements are predictable.
Intent:
The intent is to identify the pins that control the memory elements so Encounter Test test
generation and simulation algorithms can generate race-free test data.
For more information GSD Analyze Test Clocks Control of Memory Elements in the
Encounter Test: Guide 3: Test Structures.
USER RESPONSE:
If this was the design intention then no action is required. Since there are active
memory elements it is assumed that the clock inputs would be controllable from
clock pins identified by test functions in the testmode.
A mode definition includes proper identification of test clocks, definition of Test
Inhibit (TI) control pins, or both. When this is done, this message is not
produced.
display is updated to show the logic under test. The design is set to the Test
Inhibit state. Refer to the following messages:
- TSV-008
- TSV-010
- TSV-011
- TSV-012
- TSV-013
- TSV-015

To correct the deviation, add the proper test function pin attributes to the mode
definition file. Run build a test mode again, and then repeat Verify Test
Structures.
WARNING (TSV-010): [Severe] Latch objectName is not properly controlled off during
the stateName state.
EXPLANATION:
Encounter Test "Guideline TB.4 - Identification of Clock Pins" section 2 states that the L1,
L2, L3 and L4 latches of scan chains must be controlled by their scan clocks (A Clocks,
B Clocks, P Clocks and B Clocks, respectively) while scanning. The states names
inserted in the above message are as follows:
AonScan : All scan control pins at scan value except the A clock
pins are on.
BonScan : All scan control pins at scan value except the B clock
pins are on.
PonScan : All scan control pins at scan value except the P clock
pins are on.
The scan control pins are: all Clocks, Scan Enable (SE), Test Inhibit (TI) Clock Isolation
(CI) and Output Inhibit (OI).
Intent:
This test verifies that latches are controlled by appropriate scan clocks so that they can
be loaded and unloaded via the scan path. For more information GSD Analyze Test
Clocks Control of Memory Elements in the Encounter Test: Guide 3: Test
Structures.
USER RESPONSE:
Select the specific message from the Specific Message List. The memory
element is displayed and the pin(s) with the incorrect value is identified by a
default color. The default color is red. The simulation state listed in the message
is applied.
To analyze the message, trace backward from the clock pin (which should be
controlled by a scan control clock) to identify why this pin is at the incorrect
value. For more information, refer to "Clock Affiliation" in the Encounter Test:
Guide 3: Test Structures.
To correct the deviation, modify the design so the proper scan control value is
achieved at the highlighted pin.

WARNING (TSV-011): [Severe] Latch objectName has an identified latch type, however
the appropriate scan clock(s) (when scan state is stateName) does not control it.
EXPLANATION:
"Guideline TB.4 - Identification of Clock Pins" section 2 states that the L1, L2, L3 and L4
latches of scan chains must be controlled by their scan clocks (A Clocks, B Clocks, P
Clocks and B Clocks, respectively) while scanning. The states names inserted in the
above message are as follows:
AonScan : All scan control pins at scan value except the A clock
pins are on.
BonScan : All scan control pins at scan value except the B clock
pins are on.
PonScan : All scan control pins at scan value except the P clock
pins are on.
The scan control pins are: all Clocks, Scan Enable (SE), Test Inhibit (TI) and Clock
Isolation (CI).
Intent:
This test verifies that latches are controlled by appropriate scan clocks so they can be
loaded and unloaded via the scan path. For more information GSD Analyze Test Clocks
Control of Memory Elements in the Encounter Test: Guide 3: Test Structures.
USER RESPONSE:
element is displayed and the pin(s) with the incorrect value is identified by a
default color. The default color is red. The simulation state listed in the message
is applied.
To analyze the message, trace backward from the clock pin (which should be
controlled by a scan control clock) to identify why this pin is at the incorrect
value. For more information, refer to Carries Clock" in the Encounter Test:
Reference: GUI.
To correct the deviation, modify the design or change the test function pin
attributes so the clock input is properly controlled off.
WARNING (TSV-012): [Severe] Clock input objectName on non-scannable memory

element objectName was not off (at logic zero) when in the scan state state with all scan
clocks at logic X.
EXPLANATION:

Encounter Test "Guideline TB.1 - Clocked DC Latches" and "Guideline TB.4 -

Identification of Clock Pins" state that non-scan memory elements must have all their
clock inputs off. The occurrence of this message generally indicates one or the other of
two possible problems:
The identified memory element is a latch that is part of an intended scan chain,
but this scan chain was not properly identified. One possible cause is that an SI
test function attribute is missing from the scan-in primary input pin.
The identified memory element is intended to be non-scannable but is
unintentionally corrupted by the scan operation.
Intent:
The intent of this check is to verify that all non-scannable memory elements are
controlled so they never change values during the scan process. This allows Encounter
Test to make simulation more efficient.
USER RESPONSE:
Use the mouse pointer to verify the displayed block. The Information Window
Trace backward from the highlighted pin to identify the source of the incorrect
value.
Test Structures.
To correct the deviation, modify the design so that the clock input is properly
controlled off by either a system clock or TI input pins. (Using a TI pin to control
the clock input, may cause faults feeding the data input(s) of the memory
elements to be untested.)
If this memory element is meant to be non-scannable, then to correct this
deviation the design must be modified so that the clock input to this memory
element is controlled off by a system clock input pin. On the other hand, if this
memory element is meant to be scannable, then trace the scan path and fix the
point of breakage.

WARNING (TSV-013): Latch objectName did not have a clock input to only one port on
(at logic one) in the ABon state. A LSSD Flush Test cannot be generated for the scan chain
whose Scan In (SI) is objectName, Scan Out (SO) is objectName.
EXPLANATION:
The LSSD Flush Test requires that the scan clock inputs of each scan latch be held ON
by the application of the scan control pins at their scan values while the scan A and B
clock pins are ON.
Intent:
The intent is to verify that it is possible to generate an LSSD Flush Test. Chopping a scan
clock or having one scan clocks ON signal gate the other scan clock, are two possible
conditions that would prohibit generation of a LSSD Flush Test.
USER RESPONSE:
display is updated to show the specified latch block with the design set to the
ABonScan state simulated.
- Use the mouse pointer to verify the clock pin(s). Use the Information Window
to determine which clock input receives the scan clock. Look for a Clock
Affiliation value with either the Scan A (AC or AS for L1) or Scan B (BC or BS
for L2).
- Trace back on the clock input to determine where the controlling signal value
originates. It may be the result of a clock chopper on the scan clock, or that one
scan clocks ON value gates the path of a second clock.
To correct the deviation, remove the clock chopper logic on the Scan A or B
clock. Modify the design such that under the given state, one and only one clock
input to this latch is active.
WARNING (TSV-014): [Severe] A memory element has active clocks on multiple ports
when pulsing at most one clock.
Memory element memoryElementName, port1 number, port2 number.
EXPLANATION:
The simultaneous enabling of multiple ports to memory elements may result in excessive
current drain.


Intent:
It should not be possible to write into a memory element simultaneously on two different
ports by pulsing at most one clock. This restriction is intended to alert you and
manufacturing to a condition (two ports on) which may preclude successful testing of the
design and in some cases result in damage to the hardware.
USER RESPONSE:
Select the specific message from the Specific Message List. The the memory
element in question will be displayed.
The clock pins to the ports in question will be highlighted and the design values
will be displayed.
- Install logic such that it is impossible to turn both clock inputs on
simultaneously, and rerun the test.
Refer to Additional TSV Message Help on page 2811 for additional self-help
information.
WARNING (TSV-015): [Severe] Latch objectName has multiple clock inputs ON (at logic
one) during the stateName state.
EXPLANATION:
Encounter Test Guideline TB.4 - Identification of Clock Pins" section 2 states that the L1,
L2, L3, and L4 latches of scan chains must be controlled by their scan clocks such that
pulsing the scan clocks will result in data moving latch by latch through the scan chain.
Intent:
Encounter Test does not support a port dominance scheme on its latches, therefore
verify_test_structures ensures that no two clock inputs of a latch may be active
simultaneously. During a Level Sensitive Scan Design (LSSD) operation, Encounter Test
will exercise all scan clocks of the same type (types are Scan A, Scan B, and Scan P)
simultaneously. This may result in the error defined below.
Further severe errors from Encounter Test will also be produced in the additional checks.
Refer to the following:

GSD Analyze Flip-Flop and Latch Scan Characteristics in the Encounter

Test: Guide 3: Test Structures
GSD Analyze Potential Clock Signal Races in the Encounter Test: Guide 3:
Test Structures
GSD Analyze Test Clocks Control of Memory Elements in the Encounter Test: Guide
3: Test Structures.
Definitions of States
AonScan This design state is achieved by setting the design to the Scan state
and then simulating all A-SHIFT_CLOCKs to their active (opposite to
stability) values. Therefore, a -AC clock input would be set to logic 1.
BonScan This design state is achieved by setting the design to the Scan state
and then simulating all B_SHIFT_CLOCKs to their active (opposite to
stability) values. Therefore, a -BC clock input would be set to logic 1.
PonScan This design state is achieved by setting the design to the Scan state
and then simulating all P-clocks to their active (opposite to stability)
values. Therefore, a -PC clock input would be set to logic 1.
USER RESPONSE:
displayed and the clock pins which are ON are identified by a unique color. The
value.
Test Structures.
To correct the deviation, modify the design so that only one clock input is active
during the scan operation. The invalid clock path can be gated by either a tie
signal, test inhibit (TI) pin, or by a scan enable (SE). Using the SE may result in
no error here, but could still allow an error in the race checking if all clock paths
are not gated by the same SE signal so only one clock input can be active at
any time (even when the SE signals can be changed from their scan value).

WARNING (TSV-016): Clock input pinName memory element memoryElementName is

OFF (at logic zero) when the Test Inhibit state.
EXPLANATION:
Guideline TB.1 states that clocked DC latches are latches controlled by clock signals
such that the data stored in the memory elements cannot be changed by any other input
when the clocks are "OFF" (at logic zero) and the memory element takes the data input
value when the clock is "ON" (at logic one).
Intent:
The indicated clock is in the OFF state only when the TIE and TI values (the Test Inhibit
state) are applied to the circuit. Therefore, new values at the data input will not be
captured by the memory element since the clock will remain OFF.
This message is issued only if TI (Test Inhibit) values cause the clock to be OFF in the
Test Inhibit state. The intent of this guideline is to ensure that clock signals control all the
ports of all memory elements. This will aid in maximizing the test coverage of the circuit.
USER RESPONSE:
displayed and the pin with the incorrect value is identified by a unique color (the
default is red). The design is set to the Test Inhibit state.
value.
- To correct the deviation, modify or change the test function pin attribute so the
clock input is properly controlled by a clock.
information.
WARNING (TSV-017): All clock inputs to memory element memoryElementName are tied
OFF (at logic value).
EXPLANATION:
Guideline TB.1 states that clocked DC memory elements are memory elements
controlled by clock signals such that the data stored in the memory elements cannot be

changed by any other input when the clocks are "off" and the memory element takes the
data input value when the clock is "on".
Intent:
The intent of this guideline is that clock signals control all the ports of all memory
elements, but for the identified memory element this control is not in place. There will be
an adverse effect on test coverage due to the inability to clock either scan data or system
data into this memory element.
USER RESPONSE:
Select the specific message from the Specific Message List. The latch block is
displayed with the design in the Test Inhibit state.
To analyze the message trace backward from the clock pins of the memory
element to identify the source of the tied value.
To correct the deviation modify the logic so that the memory element no longer
has all its clock inputs tied off.
WARNING (TSV-018): Clock convergence violation. A pulse on one clock input cannot
propagate through blockName when another clock input is OFF. This may affect the
testability of the blocked clock input paths.
EXPLANATION:
Guideline TBT.2 states that clock signals originating from different sources must not be
logically ANDed together.
Intent:
This guideline ensures that the design will not have untestable faults in the clock trees.
When one clock is logically ANDed with the invert of another clock, a pulse on the first
clock can get through when the second clock is OFF, but a pulse on the second clock
cannot get through when the first clock is OFF. Since ATPG normally will turn only one
clock ON at a time, some faults within the clock tree for the second clock may remain
ATPG-untestable. Allowing ATPG to turn more than one clock ON at one time is very
risky since the analysis for clock control is done with the assumption that there will be at
most one clock ON at a time.
Refer to "Guideline TBT.2 - Reconvergence of Clock Signals" in the Encounter Test:
USER RESPONSE:

Select the specific message from the Specific Message List. The path from the
block or net specified in the message to the clock input pins will be displayed.
To analyze the condition, use the mouse pointer to identify the individual blocks,
pins, and nets which comprise the path.
To eliminate the condition modify the logic such that only one clock topologically
feeds the block or net.
In some cases, the clock OFF polarity can be switched to cause a logical clock
ORing condition instead of a logical clock ANDing condition. This solution is not
possible when the offending clock feeds to both a clock ANDing and a clock
ORing convergence. Switching the clock polarity causes existing logical clock
ORing to then appear to be logical clock ANDing. In such cases, it may be
beneficial to define two test modes: one mode defines the clock OFF state as
0 and the other mode defines the clock OFF state as 1.
WARNING (TSV-019): Clock reconvergence violation. objectName is fed by two or more

clocks which have the same phase in the state state. This may affect the testability of the
clock input paths blocked when one of the clocks is OFF.
EXPLANATION:
Intent:
When two clocks are logically ANDed, faults on the input clock trees may be ATPG-
untestable. No input clock pulses can get through the ANDing gate since the clock OFF
state of one clock blocks other clock pulses. Since ATPG will normally not turn ON more
than one clock at a time, the clock input trees will not be tested for any faults that must
pass through blockName in order to be detected. Also, the convergent gate will appear
to be at a constant output value - the clock path down stream will never turn ON.
When one clock is logically ANDed with another clock, a pulse on either clock cannot get
through when the other clock is OFF. Since ATPG normally will turn only one clock ON
at a time, some faults within the input clock trees may remain ATPG-untestable. Allowing
ATPG to turn more than one clock ON at one time is very risky since the analysis for clock
control is done with the assumption that there will be at most one clock ON at a time.

USER RESPONSE:
To analyze the condition use the mouse pointer to identify the individual blocks,
To eliminate the condition, modify the logic such that only one clock
topologically feeds the block or net.
WARNING (TSV-020): [Severe] A clock pinName feeds the address input to a RAM/ROM
blockName which has a read control that is always active resulting in a possible glitch. The
address input is objectName.
EXPLANATION:
Guideline TB.3, section 5 prohibits clocks from feeding the data of memory elements.
Intent:
This check is intended to eliminate the unintended chopping of clock signal by data
controlled by the same clock. Specifically, these simultaneously occurring conditions
could cause the RAM/ROM to act as a clock chopper:
A port of RAM/ROM is read enabled (read control is active)
A clock signal feeds an address input of the read-enabled port
The clock feeding address input also feeds gating logic which is driven by data
outputs of RAM/ROM
A clock transition will cause the address of the RAM/ROM to change and thus
potentially change the output of the gating logic possibly generating a glitch by
the chopping of the clock.
USER RESPONSE:
array input to the clock primary input will be displayed.
To analyze the condition use the mouse pointer to identify the individual blocks,
To eliminate the condition do one of the following:
- Modify the logic so the clock does not feed the address input of the RAM/ROM.

- Gate the clock with a signal from a Test Inhibit (TI) pin or a TIE block such that
no topological path exists to the address input of the RAM/ROM from the clock
pin.
WARNING (TSV-021): [Severe] Invalid apparent clock chopper will not be treated as a
clock chopper in the state state. The clock path reconverges at reconvergentName, but
the clock OFF state does not produce known, opposite values at this block.
The xSimName will be simulated as if it were tied to an unknown value (X) to avoid
generating bad test data.
EXPLANATION:
LSSD Guideline TBL.4 section 4 and GSD Guideline TG.7 section 2 state that no clock
signal can converge with itself with opposite phases except when used in a validly
defined clock chopper. Valid clock choppers must adhere to the rules specified in
Encounter Test Limitations Guideline TBL.4. LSSD Guideline TB.7 further requires that
all valid clock choppers be explicitly defined.
This message is issued only when the resulting clock signal feeds the clock port of an
active memory element.
Intent:
Since the block has multiple inputs fed by the same clock, this condition may produce a
glitch. This condition is often referred to as a clock chopper.
Encounter Test simulation is usually done in "zero-delay" mode; that is, it does not take
into account the design delays and simulates more on a clock cycle-basis.
A clock chopping design implemented by reconvergent, out-of-phase clock signals
generates a pulse (or glitch) because of the difference in delay between the reconvergent
paths. Therefore, a zero-delay simulator such as Encounter Tests must perform special
processing to properly simulate the effects of a clock chopper. This can be accomplished
only if the clock chopping circuits follow specific rules as defined in DFT guidelines TB.7,
TG.9 and TBL.4.
Failure to properly model a clock chopper will cause Encounter Test to either perform
incorrect simulation of the chopper function, or it may perform pessimistic simulation -
resulting in either incorrect test data or low fault coverage or both.
For more information, refer to:
Guideline TBL.4 - Clock Choppers in the Encounter Test: Guide 3: Test
Structures

GSD Guideline TG.9 - Clock Choppers in the Encounter Test: Guide 3: Test
Structures
Analyze Clock Choppers for GSD in the Encounter Test: Guide 3: Test
Structures
Test Structures
The glitch produced by this block may cause Encounter Test simulation results to differ
from the hardware.
USER RESPONSE:
Select the specific message from the Specific Message List. The logic from the
clock source(s) to the net identified in the message is displayed with the clock
off design state applied.
To analyze the message, use the mouse pointer to identify the pins feeding the
net which have the same clock. The Information Window is updated to show the
Clock Affiliation. For more information, refer to "Clock Affiliation" in the
- Modify the design so only one clock path feeds to the block.
- Modify the logic so that it can be identified as a validly defined clock chopper.
WARNING (TSV-024): [Severe] The select input of MUX pinName is fed by a clock
objectName.
EXPLANATION:
Guideline TB.4 section 4 states that no clock signal can converge with itself with opposite
phases.
Intent:
Since the block is fed by opposite phases of the same clock, the signal produced by the
block may be a shortened pulse. This shortened pulse may not be sufficient for the latch
up time of the memory elements and thus cause the Encounter Test simulated results to
differ from the hardware. Additionally, Encounter Test applications require that all clock
choppers be identified so they may be properly controlled during the generation of test
vectors. For more information, refer to GSD Analyze Potential Clock Signal Races in
the Encounter Test: Guide 3: Test Structures.

USER RESPONSE:
clock source(s) to the block identified in the message is displayed with the clock
To correct the deviation, modify the logic such that the clock does not feed the
select input to the MUX.
information.
WARNING (TSV-025): [Severe] Invalid apparent clock chopper will not be treated as a
clock choppe in the state state. The clock path fans out at fanOutName and reconverges
at reconvergentName, but both paths have the same amount of (unit) delay.
EXPLANATION:
LSSD Guideline TB.4 section 4 and GSD Guideline TG.7 section 2 state that no clock
Intent:
glitch. This condition is often referred to as a clock chopper. Both paths feeding the
reconvergent block have the same amount of unit delay which violates clock chopper
guidelines. There must be defined long and short delay paths feeding the reconvergent
block and there are none in this case.
into account the design delays and simulates more on a clock cycle-basis. A clock
chopping design implemented by reconvergent, out-of-phase clock signals generates a
pulse (or glitch) because of the difference in delay between the reconvergent paths.
Therefore, a zero-delay simulator such as Encounter Tests must perform special

TG.9 and TBL.4.
Failure to model a clock chopper properly will cause Encounter Test to either perform
Structures
"Guideline TG.7 - Clock Requirements" in the Encounter Test: Guide 3: Test
Structures
Structures
Structures
Test Structures
from the hardware.
USER RESPONSE:
To correct the deviation, do one of the following
- Modify the logic so that it can be identified as a validly defined clock chopper
by inserting more units of delay (buffers or even numbers of inverters) into the
path that is supposed to have more delay in the physical implementation.
WARNING (TSV-026): [Severe] Implicit chopperType Edge clock chopper was

unexpected and therefore will be treated as a invalid clock chopper in the state state. The

clock path reconverges at reconvergentName. The xSimName will be simulated as if it

were tied to an unknown value (X) to avoid generating bad test data.
EXPLANATION:
Intent:
glitch. This condition is often referred to as a clock chopper. The identified implicit clock
chopper complies with the clock chopper guidelines but was not expected by the user. If
the user expects implicit clock choppers in the design they need to specify "Implicit
Choppers=Yes" in the test mode definition file when the testmode is created. The default
for "Implicit Choppers" is "No" meaning that all legal implicit clock choppers will receive
this error as they were not expected by the user.
TG.9 and TBL.4.
Structures
Structures

Structures
Structures
Test Structures
from the hardware.
USER RESPONSE:
block which have the same clock. The Information Window is updated to show
the Clock Affiliation. For more information, refer to "Clock Affiliation" in the
- Identify this logic as a Encounter Test supported clock chopper.
- Modify the test mode definition file by adding IMPLICIT_CHOPPERS=YES to
indicate that implicitly defined clock choppers are to be allowed for this test
mode. See "IMPLICIT CHOPPERS" in the Encounter Test: Guide 2:
Testmodes for details.
WARNING (TSV-028): Implicit chopper_type Edge clock chopper will be treated as valid
in the state state. The chopper design reconverges at reconvergentName and can
disabled by holding disableName.
EXPLANATION:
This message is issued for General Scan Design (GSD) products where correctly
designed implicit clock choppers are permitted. This message indicates that an implicitly
defined clock chopper was found and that the user has specified for Encounter Test to
allow such clock choppers to be processed as if they were approved by the technology
provider.

Encounter Test will process these implicit clock choppers assuming they are valid, but
this message serves as a warning to the user and sets an audit to alert manufacturing
that the test data may be suspect. Encounter Test LSSD Guideline TB.7, GSD Guideline
TG.9 and Limitation Guideline TBL.4 define how clock chopper circuits can be defined
for use by Encounter Test.
Intent:
TG.9 and TBL.4.
Failure to properly model a clock chopper properly will cause Encounter Test to either
perform incorrect simulation of the chopper function, or it may perform pessimistic
simulation - resulting in either incorrect test data or low fault coverage or both.
Structures
Structures
Structures
Structures
Test Structures
Be aware that Encounter Test zero-delay simulators assume that clock choppers
produce an infinitely wide pulse width - wide enough to allow all signals to settle out
before switching back off. Implicitly defined clock choppers generally have not been
verified to produce pulse widths sufficiently wide to ensure that Encounter Test
simulation results will match the hardware.
USER RESPONSE:

If the design was not intended to be a clock chopper, do one of the following:
- Rebuild the test mode and remove the IMPLICIT_CHOPPERS=YES
statement from the test mode definition file. Implicit choppers will no longer be
allowed. Pessimistic simulation will be performed to avoid generating bad test
data. See "IMPLICIT CHOPPERS" in the Encounter Test: Guide 2:
Testmodes for details.
- Modify the design so that it no longer performs a clock chopping function.
To remove this message for intentional clock chopper circuits within a
technology cell library when the design timings are known to work correctly,
insert the appropriate special Encounter Test CHOP primitive(s) as defined in
Guideline TBL.4.
WARNING (TSV-029): [Severe] Implicit chopperType Edge clock chopper will be

treated as valid in the state state. The chopper design reconverges at
reconvergentName and can disabled by holding disableName.
EXPLANATION:
This message is issued for Level Sensitive Scan Design (LSSD) products where implicit
clock choppers are not permitted.
LSSD Guideline TB.7 defines how clock chopper circuits are to be explicitly defined for
use by Encounter Test. This message points out that an implicitly defined clock chopper
was found and that implicitly defined clock choppers were specifically allowed when the
test mode was defined; however, strict LSSD guidelines require that all clock choppers
be explicitly defined in the technology cell library using special Encounter Test CHOP
primitives to ensure that the technology provider has verified that the chopper works
under all conditions.
Intent:


TG.9 and TBL.4.
Failure to properly model a clock chopper properly will cause Encounter Test to either
perform incorrect simulation of the chopper function, or it may perform pessimistic
simulation - resulting in either incorrect test data or low fault coverage or both.
Structures
Structures
Structures
Structures
Test Structures
Be aware that Encounter Test zero-delay simulators will perform pessimistic simulation
of clock choppers that are not explicitly defined or for implicit clock choppers that are not
expressly allowed.
USER RESPONSE:
If the design was not intended to be a clock chopper, do one of the following:
- Nothing. Accept the pessimistic simulation results.
- Modify the design so that it no longer performs a clock chopping function.

If the design is intentionally a clock chopper that will work, do one of the
following:
- To remove this message for intentional clock chopper circuits within a
technology cell library when the design timings are known to work correctly,
insert the appropriate special Encounter Test CHOP primitive(s) as defined in
Guideline TBL.4.
- To remove this message for user (not technology) defined clock choppers,
change the test mode definition to be a scan type of GSD rather than LSSD.
- Ignore this message if you want Encounter Test to treat the implicit chopper
as a valid chopper.
WARNING (TSV-030): Invalid keeper device on 3-state netName. Weak feedback loop
input objectName is not a constant value, nor is it an enable or gate input to a TSD or
transistor primitive.
EXPLANATION:
Encounter Test does not support keeper devices with arbitrarily complex inputs that
affect the weak feedback loop. These feedback loops must either be constant value nets
(e.g., TIEd to 0 or 1) or function as enable inputs to three-state driver or transistor
primitives.
Guidelines TB.2 and TG.2 define recognized memory elements as being either latches,
RAM cells or three-state keeper devices.
Refer to "Guideline TG.2 - No Feedback Loops" in the Encounter Test: Guide 3: Test
Structures for more information.
Intent:
To simplify the identification of three-state keeper devices, Encounter Test imposes a
specific structure. This configuration violates that structure, and could cause a loss of
test coverage or poor performance.
USER RESPONSE:
Select the specific message from the Specific Message List. The feedback loop
is displayed with the input pin or net that is the offending input to the feedback
loop highlighted.
To analyze the message use the mouse pointer to trace from the offending pin
or net to identify the sources of the feedback loop input.

To correct the deviation, modify the design so that the weak feedback loop input
to the keeper device is either a constant value or else is an enable or gate input
to a TSD or transistor primitive.
WARNING (TSV-031): Invalid keeper device on 3-state netName. A feedback loop through
this net does not guarantee a weak value is supplied to the net when the loop is sensitized.
EXPLANATION:
Encounter Test supports only keeper devices which supply a weak value to the 3-state
net either from a transistor or directly from a resistor.
Intent:
USER RESPONSE:
is displayed with any resistor primitives in the loop highlighted.
To analyze the message use the mouse pointer to trace from the feedback loop
to identify the source of the feedback value.
To correct the deviation modify the design so that the feedback loop through this
net guarantees that a weak value is supplied to the net when the loop is
sensitized.
WARNING (TSV-032): Invalid keeper device on 3-state netName. More than one 3-state
dotted net found in the feedback loop.
EXPLANATION:
The keeper device had multiple three-state multi-source nets in the feedback path.
Encounter Test does not support keepers with arbitrarily complex functions in the weak
feedback loop.

Intent:
USER RESPONSE:
To analyze the message use the mouse pointer to trace out the logic in the
feedback loop.
To correct the deviation modify the design by removing the improper logic from
the feedback loop.
WARNING (TSV-033): Apparent keeper device on 3-state netName, holds neither a weak
zero (L) nor a weak one (H). Encounter Test will not treat this as a keeper device.
EXPLANATION:
A legitimate keeper device must be capable of holding at least one of the weak signal
values.
Guideline TB.8 defines recognized memory elements as being either latches, RAM cells
or three-state keeper devices.
Refer to "Analyze Three-stae Drivers for Conention" in the Encounter Test: Guide 3:
Test Structures for more information.
Intent:
USER RESPONSE:

To analyze the message, use the mouse pointer to identify the nets which
comprise the keeper device.
To correct the deviation, modify the design so that a weak logic value can be
held by the keeper device.
WARNING (TSV-034): [Severe] Keeper device on objectName1 is exposed to glitches

at objectName2.
EXPLANATION:
A keeper device that is exposed to glitches may indicate a possible design error.
Guidelines TB.8 defines recognized memory elements as being either latches, RAM
cells or three-state keeper devices.
Refer to Analyze Three-stae Drivers for Conention" in the Encounter Test: Guide 3:
Intent:
A keeper that is exposed to glitches can cause decreased test coverage and poor
performance, due to the need to make pessimistic assumptions in simulation. Without
these pessimistic assumptions the simulator may predict incorrect responses.
USER RESPONSE:
Select the specific message from the Specific Message List. The three-state
net is displayed, along with the entire path back from the enable or gate input
that is exposed to glitches.
To correct the deviation modify the design so that the glitch source is prevented
from gating the keeper in this test mode.
WARNING (TSV-035): [Severe] Keeper device on objectName, is exposed to potential

races between the data and enable inputs to the strong sources on the 3-state net.
EXPLANATION:
A keeper device that is exposed to races may indicate a possible design error.
Guidelines TB.8 defines recognized memory elements as being either latches, RAM
cells or three-state keeper devices.

Refer to "Analyze Three-stae Drivers for Conention" in the Encounter Test: Guide 3:
Intent:
A keeper that is exposed to races can cause decreased test coverage and poor
performance, due to the need to make pessimistic assumptions in simulation. Without
these pessimistic assumptions the simulator may predict incorrect responses.
USER RESPONSE:
Select the specific message from the Specific Message List. The three-state
net is displayed along with the entire path back from the enable (or gate) and
data inputs that are exposed to races.
To correct the deviation, modify the design to prevent the race from occurring in
this test mode.
WARNING (TSV-036): A feedback loop containing an invalid keeper device has been
detected. The apparent keeper device was identified at resistor objectName.
EXPLANATION:
Encounter Test supports only keeper devices which supply a weak value to the 3-state
net either from a transistor or directly from a resistor.
Structures define recognized memory elements as being either latches, RAM cells or
three-state keeper devices.
Intent:
USER RESPONSE:
To analyze the message use the mouse pointer to trace from the feedback loop
to identify the source of the feedback value.
To correct the deviation, modify the design so that the feedback loop through
this net guarantees that a weak value is supplied to the net when the loop is
sensitized.

WARNING (TSV-037): [Severe] Invalid apparent clock chopper changed chopper types
when changing design states. The clock path reconverges at reconvergentName and is
a xSimName Edge Chopper in the state1 state but changes to a chopperType1 Edge
Chopper in the state2 state.
The chopperType2 will be simulated as if it were tied to an unknown value (X) to avoid
EXPLANATION:
A valid clock chopper must maintain its chopper type in all design states. This chopper
changed type when the design state changed.
USER RESPONSE:
Select the specific message from the Specific Message List. The reconvergent
block is displayed with the second design state applied.
To correct the deviation, modify the design so that the clock chopper maintains
its type for all design states.
WARNING (TSV-038): [Severe] Apparent clock chopper produces multiple pulses at the
reconvergent block and will not be treated as a clock chopper in the state state. The clock
path fans out at fanOutName and reconverges at reconvergentName.
EXPLANATION:
all valid clock choppers
be explicitly defined.

Intent:
glitch. This condition is often referred to as a clock chopper. In this case the design
produces multiple pulses at the reconvergent block from a single clock transition. This
violates clock chopper guidelines since the accurate simulation of these multiple pulses
is not possible.
TG.9 and TBL.4.
Structures
Structures
Structures
Structures
Test Structures
from the hardware.
USER RESPONSE:

To correct the deviation, modify the design so that only one pulse is produced.
WARNING (TSV-039): [Severe] Apparent clock chopper contains illegal gating in the
state state. The clock path fans out at fanOutName and reconverges at
reconvergentName.
EXPLANATION:
Intent:
glitch. This condition is often referred to as a clock chopper.
TG.9 and TBL.4.

Structures
Structures
Structures
Structures
Test Structures
from the hardware.
USER RESPONSE:
To correct the deviation, modify the design to remove the illegal gating. and
rerun
WARNING (TSV-040): [Severe] Apparent clock chopper does not maintain its chopper type
in all states. The clock path reconverges at reconvergentName and is a xSimName Edge
Chopper in the state1 state but is not choppertype1 Edge Chopper in the state2
state.
The choppertype1 will be simulated as if it were tied to an unknown value (X) to avoid
EXPLANATION:

A valid clock chopper must maintain its chopper type in all design states. This chopper
could be identified as a chopper in one state but was not identifiable as a clock chopper
in the other state.
USER RESPONSE:
Select the specific message from the Specific Message List. The recovergent
block is displayed with the second design state applied.
To correct the deviation, modify the design so that the clock chopper maintains its type
for all design states and rerun.
WARNING (TSV-041): [Severe] chopperType edge clock chopper contains invalid fan-
out from sourceName in the state state. The clock path reconverges at
reconvergentName and the chopper would be disabled by holding disableName.
The IxSimName will be simulated as if it were tied to an unknown value (X) to avoid
EXPLANATION:
Guideline TBL.4 states that the block which Encounter Test applications will use to
disable the clock chopper cannot fan out.
For leading-edge clock choppers, the last block in the long path must feed only to the
reconvergent block. For trailing-edge clock choppers there must be at least one block in
the short path and the last node on both paths must feed only to the reconvergent block.
This is a general Encounter Test limitation.
The build_testmode application identifies the chopper type based on how it actually
behaves, not on the existence of any explicit chopper primitives. If the chopper type
identified in the message is not the chopper type intended, then the polarity of the input
clock may be incorrect.
Intent:

To simplify the processing of clock choppers, Encounter Test imposes a specific

structure. The configuration found violates that structure, and thus some clock chopping
logic may be unrecognized.
Structures
Structures
USER RESPONSE:
Select the specific message from the Specific Message List. The paths from the
chop block to its multiple destinations are displayed. The design is set to the
Test Inhibit state.
To analyze the message, find the blocks which feed the reconvergent block. at
value.
For all clock choppers, the last node on the longest reconverging path must feed
only to the reconvergent block. For trailing-edge clock choppers there must be
at least one block in the short path and the last block in the short path must feed
only to the reconvergent block. Modify the logic to conform to this restriction.
WARNING (TSV-042): All clock inputs to a scan latch or flop memoryElementName are
OFF in the Test Generation state.
EXPLANATION:
Intent:
The clock(s) to the identified scan latch or flop are held off in the Test Generation state.
This prevents the this latch or flop from being updated during the capture sequence.
USER RESPONSE:
Select the specific message from the Specific Message List. The latch or flop
block is displayed with the circuit in the Test Generation state.
To analyze the message trace backward from the clock pins of the memory
element to identify the source of the value.
To correct the deviation modify the logic so that the scan latch or flop no longer
has all its clock inputs off.

WARNING (TSV-044): [Severe] Apparent clock chopper contains more than 2

reconvergent paths in the state state. The reconvergent block is reconvergentName
which is fed by more than 2 paths from the fan-out block.
EXPLANATION:
Guideline TBL.4 states that for a validly defined clock chopper, the reconvergent block
must have exactly two inputs which are fed from the fan-out block.
Intent:
To simplify the identification of clock choppers, Encounter Test imposes a specific
structure. The configuration found violates that structure. Encounter Test is forced to
presume that this clock chopping design was unintentional and as such will be required
to perform pessimistic simulation, resulting in lower fault coverage.
Structures
Structures
USER RESPONSE:
Select the specific message from the Specific Message List. The invalid
network is displayed. The design is set to the Test Inhibit state. Included will be
the reconvergent block, the fan-out block and all the paths from the fan-out block
to the reconvergent block.
To analyze the message, identify each of the inputs to the reconvergent block
(it should be the right most block on the display) to ascertain which ones belong
according to Encounter Tests clock chopper modeling technique.
- Modify the design so that it conforms to the requirements specified in
Guideline TBL.4 - Clock Choppers
- Modify the design to remove the apparent clock chopping function.

WARNING (TSV-045): [Severe] Apparent clock chopper fan-out point cannot be found in
the state state. The reconvergent node is reconvergentName and no single fan-out
point can be found which feeds exactly two paths to this reconvergent node.
EXPLANATION:
Guideline TBL.4 states that a validly defined clock chopper design contains a single point
of fan-out which feeds exactly two paths to the reconvergent node.
Intent:
Structures
Structures
USER RESPONSE:
Select the specific message from the Specific Message List. The invalid network is
displayed. The design is set to the Test Inhibit state. Included will be the reconvergent
block and the sources of all non-tied signals to that block.
To correct the deviation, do one the following:
Guideline TBL.4 - Clock Choppers.
WARNING (TSV-046): [Severe] Apparent clock chopper reconvergent block is not an AND,
NAND, OR or NOR in the state state. The reconvergent node is reconvergentName.

EXPLANATION:
Guideline TBL.4 states that the reconvergent block of a validly defined clock chopper
must be an AND, NAND, OR or NOR logic gate. Use of other gates such as MUX, XOR
or XNOR primitives is not allowed.
Intent:
Structures
Structures
USER RESPONSE:
Select the specific message from the Specific Message List. The clock chopper
is displayed. The design is set to the Test Inhibit state.
To analyze the message, trace back from the chopper block to see where there
are two or more clock paths reconverging.
Guideline TBL.4 - Clock Choppers. Specifically, make the reconvergent block
an AND, NAND, OR or NOR gate.
WARNING (TSV-048): [Severe] Trailing Edge clock chopper feeds Trailing Edge clock
chopper in the state state. First clock chopper fan-out is fanOutName1 and reconverges
at reconvergentName1. Second clock chopper fan-out is fanOutName2 and
reconverges at reconvergentName2.

EXPLANATION:
Guideline TBL.4 section 2 states that a trailing edge clock chopper is not allowed to feed
another trailing edge clock chopper.
Intent:
This restriction is in place so Encounter Test can reasonably support clock choppers.
Allowing trailing-edge clock choppers to be cascaded implies that a single edge on a
clock primary input signal could result in an extended series of internally generated
pulses from the cascaded trailing-edge clock choppers. Circuits which perform functions
like this are more appropriately dealt with by using the Encounter Test support for on-
product clock generation (OPCG).
Structures
Clock and Controller Logic Design Guidelines in the Encounter Test: Guide
3: Test Structures
Structures
Encounter Tests analysis programs such as Verify Test Structures will likely report
additional errors because of their inability to support cascaded trailing-edge clock
choppers. Encounter Test test generators will likely generate invalid tests that fail to
detect certain faults. Encounter Test simulators will attempt to simulate the cascading
effect as accurately as possible, but it should be understood that such a cascading may
delay the settling out of the signals so long that the tester timing may have to be slowed
down to accommodate this extra delay.
USER RESPONSE:
source pin of the first trailing edge-triggered clock chopper to the output of the
clock chopper of the second trailing edge-triggered clock chopper is displayed
The design is set to the Test Inhibit state.
To analyze the message, take note of the trailing-edge-triggered clock choppers
and the memory elements they feed.

To correct the deviation, remove the cascading of the clock choppers.
WARNING (TSV-050): [Severe] A memory element captures data from another memory
element and both elements are fed by the same clock objectName. Memory element
objectName, capture input objectName, capture clock objectName. Source element
objectName, source clock objectName.
EXPLANATION:
Guideline TB.3 section 1 states that data from a memory element (either a latch or a
RAM/ROM) may not feed to a memory element which is clocked by the same clock.
Intent:
This Guideline ensures that the design will be free of races between data and its
capturing clock. Since the actual delay between the memory elements and the clock to
the memory elements is unknown, the simulation of this design may not match the
behavior of the hardware. For more information, refer to GSD Analyze Potential Clock
Signal Races in the Encounter Test: Guide 3: Test Structures.
USER RESPONSE:
Select the specific message from the Specific Message List. The path(s) from
the source element to the memory element and the paths from both elements
to the clock primary inputs will be displayed.
To analyze the message, use the mouse pointer to identify the individual blocks,
pins and nets which comprise the clock and data paths. If the Mutually
Exclusive Gating (MEG) option was specified the design values required to turn
the clocks on at both the source and capture memory elements while a path is
sensitized from the source to the capture element will be displayed.
- If the checks were run with the MEG option set to no and logic exists such that
it is impossible to turn the clock inputs to both the source and memory elements
on simultaneously while a path is sensitized from the source to the capture
element and rerun the test with the MEG option set to yes.
- If the MEG option is set to no or no logic exists so it is impossible to turn the
clock inputs to both the source and capture elements on simultaneously while
a path is sensitized from the source to the capture element, install such logic
and rerun the test with the MEG option set to yes.
- Change the clock signal to either the source or the memory element so both
elements are not controlled by the same clock.

- Eliminate any path that has no functional use.

WARNING (TSV-051): [Severe] Clock feeds data race. Port memoryElementName with
data input pinName1 of memory element pinName2 has both the clock and data driven
from a common source clock number.
EXPLANATION:
Guideline TB.3 states that a clock cannot feed the data input of a latch or RAM. Since
this clock also feeds the clock input of the same port, there may be a race.
Guideline TG.4 states that a clock cannot feed both the data and clock inputs of the same
port of a memory element. Since this clock also feeds both the clock and data input of
the same port, there may be a race.
Intent:
This guideline ensures that the design will be free of races between data and its
capturing clock. Since the data input to the memory element may be changing as the
clock is turning off at the memory element, the contents of the memory element are
unpredictable. That is, the Encounter Test simulation application cannot correctly predict
whether new data or old data was captured by the memory element. The value captured
by the memory element may be unpredictable if the overlap between clock and data is
less than the minimum latch-up time.
"Guideline TG.4 - Clock vs. Data Races" in the Encounter Test: Guide 3: Test
Structures
Test Structures
USER RESPONSE:
If the clock feeds the data input because there is explicit modeling of clock precharge
paths for dynamic logic, this violation may be able to be ignored if it can be guaranteed
that the captured value is always the value appearing at the data input prior to the clock
PI providing the capturing clock edge; otherwise, the violation should be repaired.
Analyze the violation by following these steps:

the clock input and data input to the clock primary input will be displayed.
pins, and nets which comprise the clock and data paths.
To correct the deviation, remove the logical path from the clock primary input to
the data input to the memory element.
information.
WARNING (TSV-052): [Severe] Simultaneous writes from two ports violation. A memory
element has two ports which may be simultaneously updating the memory with clock
pinName at its ON value.
Memory element memoryElementName, port1 number1, port2 number1.
EXPLANATION:
Guidelines TB.6 and TG.6 state that multiple data ports of memory element (either a
Flop, latch or a RAM/ROM) may not be controlled by the same clock.
Intent:
This Guideline is intended to eliminate uncertainty as to which data port was the last to
control the memory element. Since the value captured by the memory element when
both ports are active is indeterminate, Encounter Test simulation of the clock may result
in the capturing of the wrong value.
If it is possible to create a high current condition that could damage the device when
simultaneously writing opposing values from two ports, aconstraint should be defined to
force Encounter Test to prevent such tests from being created.
"Guideline TG.6 - Only One Port Active" in the Encounter Test: Guide 3: Test
Structures
Test Structures
USER RESPONSE:

clock primary input to the memory elements clock inputs will be displayed.
Exclusive Gating (MEG) option was specified the design values will also be
displayed.
it is impossible to turn the clock inputs to both ports on simultaneously, rerun
the test with the MEG option set to yes.
- If the MEG option is set to no or no logic exists so it is impossible to turn both
clock inputs on simultaneously, install such logic and rerun the test with the
MEG option set to yes.
- Change the clock signal to either clock input of the memory element so each
port is controlled by a unique clock.
- Add a constraint to the model that prevents simultaneous writes from
occurring. For a two write port RAM, this could be as simple as enforcing that
the low-order address bits must be opposite value (to ensure the addresses will
not be the same).
WARNING (TSV-054): [Severe] Clock feed data violation. A flop flopName is fed by a
clock or clocks through its data input pinName1 and its clock input pinName2.
EXPLANATION:
Guideline TB.3 states that a clock cannot feed the data input of a latch or RAM.
Guideline TG.4 states that a clock cannot feed both the data and clock inputs of the same
port of a memory element. As this clock feeds both the clock and data input of the flop,
there may be a race between data and its capturing clock.
Intent:
This guideline helps to ensure that the design is free of races between data and its
capturing clock. As the data input to the memory element may be changing as the clock's
capturing edge appears at the memory element, the contents of the memory element are
unpredictable. That is, zero-delay and unit-delay simulation cannot correctly predict
whether the new or old data is captured by the memory element. The value captured by
the memory element may be unpredictable in case of a hold-time violation.


Guideline TG.4 - Clock vs. Data Races in the Encounter Test: Guide 3: Test
Structures
USER RESPONSE:
If the clock feeds the data input because there is explicit modeling of clock precharge
paths for dynamic logic, this violation may be ignored if it is ensured that the captured
value is always same as the value appearing at the data input prior to the clock PI
providing the capturing clock edge. Otherwise, the violation should be repaired.
You can analyze the violation by following these steps:
Select the message from the Specific Message List. The flop will be displayed with
the clock input and data input highlighted.
To analyze the message, use the mouse pointer to identify the clock(s) that feed both
the clock and data pins.
Information Window is updated to show the clock affiliation when the pin is
selected.
Trace back from both the clock and data pins of the flop using the clock affiliation
data to determine the paths that are in error.
To correct the deviation, remove the logical path from the clock's primary input or
inputs to the data input of the flop.
WARNING (TSV-055): [Severe] A flop flopName is fed by a common clock or clocks

through its CLR input pinName1 and its SET input pinName2.
EXPLANATION:
A potential race condition exists in the design that could affect ATPG. The SET and CLR
inputs of the identified flop are fed by a common clock signal. This design error should
be corrected to get better results.
USER RESPONSE:
Modify the design to supply independent control signals to the CLR and SET inputs of
the flop. You can analyze the violation by following these steps:
Select the specific message from the Specific Message List.
The flop will be displayed with the CLR and SET inputs highlighted.
To analyze the message, use the mouse pointer to identify the clock or clocks which
feed both the CLR and SET pins.

The Information Window is updated to show the Clock Affiliation when the pin is
selected.
Trace back from both the CLR and SET pins of the flop using the Clock Affiliation
data to determine which paths are in error.
To correct the deviation, remove the logical path from the clock or clocks primary
input or inputs to the CLR or SET input to the flop.
WARNING (TSV-058): [Severe] Illegal clock gating violation. The clock being gated is
objectName at objectName.
EXPLANATION:
Guideline or Restriction
For edge-clocked test modes, Guideline TG.4 states that a memory element should not
be used to gate the same clock signal that controls it except when value V at the clock
source launches new data from the memory element, that same value V must also
dominate the gating signal to prevent any potential glitches.
constraints option. Refer to the constraints description in the verify_test_structures
Intent
This guideline ensures that the clock input to the memory element does not depend on
data that is controlled by the same clock. For more information, refer to
Guideline TG.4 - Clock vs. Data Races in the Encounter Test: Guide 3: Test
Structures
USER RESPONSE:
Select the specific message from the
Specific Message List.
WARNING (TSV-059): [Severe] Illegal clock gating violation. A potential clock/data race
exists that could produce a glitch where the clock is gated by a value from a memory element
that is updated by the same clock signal.
The clock being gated is commonClockPinName. The gated clock feeds to capture
element memoryElementName1, with data input dataPinName1 and clock input
clockPinName1.
The source element that gates the clock is memoryElementName2, with clock input
clockPinName2.

EXPLANATION:
For LSSD test modes, Guideline TB.3 states that memory elements (latches and RAM)
must be controlled by clocks such that raising and lowering the clocks will result in race-
free operation.This case is referred to as a "data gates clock" type of clock race since the
data of the upstream source memory element creates a potential clock race condition
with the downstream capture memory element.
Intent:
data that is controlled by the same clock.
Structures
Test Structures
USER RESPONSE:
To analyze the message use the mouse pointer to identify the individual blocks,
pins, and nets which comprise the clock and the data paths. If the Mutually
Exclusive Gating (MEG) option was specified the design values will also be
displayed.
To correct the deviation do the following:
- If the checks were run with the MEG option set to no and logic exists so it is
impossible to turn the clock input to the upstream source element on while a

path is sensitized from the source element to the clock input of the downstream
capture element and rerun the test with the MEG option set to yes.
- If MEG option is set to no or no logic exists so it is impossible to turn the clock
input to the upstream source element on while a path is sensitized from the
source element to the clock input of the capture element, install such logic and
rerun the test with the MEG option set to yes.
- Change the clock signal to either the upstream source or downstream capture
memory element so both elements are not controlled by the same clock.
WARNING (TSV-060): [Severe] MEG checking aborted with the specified EFFORT level.
A memory element captures data from another memory element and both elements are fed
by the same clock objectName. Memory element objectName, capture input
objectName, capture clock objectName. Source element objectName, source clock
objectName.
EXPLANATION:
verify_test_structures looks for mutually exclusive gating to render this condition
inoperative, but this message indicates verify_test_structures stopped checking
for gating that would prevent the error before reaching a resolution.
Guideline TB.3 section 1 states that data from a memory element (either a latch or a
RAM/ROM) may not feed to a memory element which is clocked by the same clock.
Intent:
This Guideline ensures that the design will be free of races between data and its
capturing clock. Since the actual delay between the memory elements and the clock to
the memory elements is unknown, the simulation of this design may not match the
behavior of the hardware. For more information, refer to GSD Analyze Potential Clock
Signal Races in the Encounter Test: Guide 3: Test Structures.
USER RESPONSE:
pins and nets which comprise the clock and data paths.


- Change the clock signal to either the source of the memory element so both
- If you suspect this is not a true error condition, rerun this test with a higher
effort level. The default effort level if none was specified is effort=medium
which is equivalent to effort=5. To rerun this test add reruntests=yes to
the command line. Increasing the effort level may cause the test to run longer,
and the test may still abort on this violation.
specified EFFORT level while processing this message: A memory element has two ports
which may be enabled with clock pinName at its ON value.
Memory element memoryElementName, port1 number1, port2 number2.
EXPLANATION:
time and effort it should expend trying to prove that the conditions that cause the violation
cannot occur.
exist that cause the violation.
If the MEG checking aborts before completion then the conditions which produce the
violation may or may not be possible.
Guideline TB.6 states that multiple data ports of memory element (either a latch or a
RAM/ROM) may not be controlled by the same clock.
Intent:
This Guideline is intended to eliminate uncertainty as to which data port was the last to
control the memory element. Since the value captured by the memory element when
both ports are active is indeterminate, Encounter Test simulation of the clock may result
in the capturing of the wrong value.

Additionally, since the actual delay in the clock paths is unknown, the simulation of this
path may result in a value which does not match the actual hardware.
"Guideline TG.6 - Only One Port Active" in the Encounter Test: Guide 3: Test
Structures
Test Structures
USER RESPONSE:
clock primary input to the memory elements clock inputs will be displayed.
To correct the deviation, perform the following:
which is equivalent to effort=5 To rerun this test add reruntests=yes to
WARNING (TSV-065): The Analyze Test Clocks Control of Memory Elements was invoked
and severe clock violations were detected. Keyword stoponerrorclockusage=yes
causing verify_test_structures to automatically stop further processing.
EXPLANATION:
Intent:
This message indicates that the Analyze Test Clocks Control of Memory Elements test
was run and severe violations were found. The stopinerrorclockusage keyword
controls whether verify_ test_structures continues processing the other
selected checks or stops immediately. In this case the stoponerrorclockusage keyword
was set to yes so processing was stopped.
Severe clock violations should always be the first violations addressed since they can
effect other verify_test_structures checks. Futhermore they can significantly
impact run times on other checks which are sensitive to proper clock design.

The intent of the stoponerroclockusage keyword to underscore the importance of

resolving severe clock violations first before running other verify_test_structures
tests.
USER RESPONSE:
Either correct the severe clock errors and rerun verify_test_structures
or
Set stoponerrorclockusage=no when invoking
verify_test_structures so that verify_test_structures will run all
selected checks even when severe clock violations are detected.
INFO (TSV-068): The length of the longest scan chain is length1 bit positions, which is
percentage% of the average scan chain length length2 (based on bits total scan-out bits
and chains valid scan-out chains).
EXPLANATION:
Test cost is directly affected by the time it takes to scan in/out each individual test. To help
minimize the time, it is important that the length of the scan chains be minimized. In
general, having more scan chains allows each chain to be shorter, thus reducing test
time. However, test time will be dictated by the length of the longest scan chain, so it is
important to try to keep the longest register as close to the length of the average scan
chain as possible (i.e. the chains should be balanced).
Because the extra test time associated with non-balanced scan chains can be quite
costly, some chip manufacturers have published guidelines for their customers to help
keep test costs under control. These guidelines establish simple numerical targets for
scan chain count and scan chain length balancing. verify_test_structures issues
this message to report the relevant statistics.
USER RESPONSE:
No response is required for Encounter Test to process the design correctly. If your chip
manufacturer has guidelines for scan chain length, verify that the length of the longest
chain in the message is within these guidelines.
Illegal clock gating violation. A potential clock/data race exists that could produce a glitch
where the clock is gated by a value from a memory element that is updated by the same clock
signal.
The clock being gated is commonClockpinName. The gated clock feeds to capture
element memoryElementName1 at data input dataPinName1, with clock input
clockPinName1.

The source element that gates the clock is memoryElementtName2, with clock input
clockPinName2.
EXPLANATION:
cannot occur.
If the MEG checking aborts before completion, then the conditions which produce the
free operation. This case is referred to as a "data gates clock" type of clock race since
the data of the upstream source memory element creates a potential clock race condition
with the downstream capture memory element.
Intent:
data that is controlled by the same clock.
Structures
Test Structures

USER RESPONSE:
To analyze the message use the mouse pointer to identify the individual blocks,
pins, and nets which comprise the clock and the data paths.
To correct the deviation do the following:
INFO (TSV-070): The product under test has number Scan In (SI) pins flagged and number
Scan Out (SO) pins flagged. The number of valid scan chains is number.
EXPLANATION:
Guideline TB.5 states that each scan chain must have an identified SI and SO.
Intent:
Each scan chain must be fed by a product input pin which is identified as a SI. The scan
chain must consist of alternating L1 and L2 latches. The last L2 must control a product
output pin which is identified as the SO. The scan chains must be constructed so all the
scan chains can be scanned in parallel. For more information, refer to GSD Analyze Flip-
Flop and Latch Scan Characteristics in the Encounter Test: Guide 3: Test
Structures.
USER RESPONSE:
If no severe scan chain errors were detected, this message identifies the
number of complete scan chains for the circuit. No action is necessary.
If severe scan chain errors were detected, refer to the analysis for the specific
errors that were issued.

WARNING (TSV-071): [Severe] Product Scan In (SI) objectName does not control a
data input of a latch or a Scan Out (SO) pin.
EXPLANATION:
Guideline TB.5 states that each scan chain must be fed by a product input pin which is
identified as a SI. The scan chain must consist of alternating L1 and L2 latches.
Intent:
The Encounter Test test generation applications assume that L1 and L2 latches can be
used as control points for creating test vectors. The method for achieving values in these
latches is a scan operation. Each scan chain must be fed by a product input pin which is
identified as a SI. For more information, refer to GSD Analyze Flip-Flop and Latch Scan
Characteristics in the Encounter Test: Guide 3: Test Structures.
USER RESPONSE:
display is updated to show the SI flagged pin with all scan control pins at value
except A clocks are on.
To analyze the message, trace forward from the pin to identify the L1 that should
receive the value of the SI pin during the scan operation.
- If a path to the data input of an L1 exists, but the clock to that port is not on,
modify the logic to correct the L1 clocking problem.
- If a path to an L1 exists, but the value at the data input of the latch is not always
the value of the SI pin (or its inverse), sensitize the path by defining additional
scan enables (SE) to change the stability value on an existing scan.
- If a path to an L1 does not exist, either remove the SI flag from the product
input pin or install a path to an L1.
WARNING (TSV-072): [Severe] Latch objectName captures data from product Scan In
(SI) objectName when the P clocks are on.
EXPLANATION:
The Scan P clock controls the L3 latch when the design is in the scan state. It must
receive its data from the associated L1 latch during scan. The scan chain must consist

of alternating L1 and L2 latches. The last L2 must control a product output pin which is
identified as the scan out (SO).
Intent:
Support a stable latch. In LSSD, these are controlled by P clocks and receive that data
from L1s. For more information, refer to GSD Analyze Flip-Flop and Latch Scan
USER RESPONSE:
display is updated to show the path from the SI flagged pin to the SO latch with
all scan control pins at value except P clocks are on.
pins and nets comprising the path.
To correct the deviation, use a different clock to control the latch or feed its data
from an L1.
WARNING (TSV-073): [Severe] An L1 objectName feeds another L1 objectName in

the scan state.
EXPLANATION:
identified as a scan in (SI). The scan chain must consist of alternating L1 and L2 latches
that are controlled by the appropriate scan control clock.
Intent:
The Encounter Test applications assume that L1 and L2 latches can be used as control
points for creating test vectors. The method for achieving values in these latches is a
scan operation. To accurately predict the contents of a scan chain, each scan chain must
be fed by a product input pin which is identified as a SI. The scan chain must consist of
alternating L1 and L2 latches that are controlled by the appropriate scan control clock
and the last L2 must control a product output pin which is identified as the scan out (SO).
An L1 must be controlled by an A clock and an L2 must be controlled by a B clock.
Alternating the L1 and L2 assume a reliable race-free scan operation. For more
information, refer to GSD Analyze Flip-Flop and Latch Scan Characteristics in the
USER RESPONSE:

display is updated to show the path from the highlighted pin of the first L1 to the
highlighted pin of the second L1 with all scan control pins at value except A
clocks are on.
To correct the deviation, modify the design as follows:
- Remove the path from the first L1 to the second L1.
- Install a path from the first L1 to an appropriate L2.
- Insert the second L1 into a valid scan chain. Install a path from an appropriate
L2 or SI primary input to the second L2.
WARNING (TSV-074): An L2 objectName feeds an L3 objectName in the scan state.

EXPLANATION:
Guideline TB.4 - Identification of Clock Pins" (2) states that an L3 latch must receive data
only from its associated L1 in the scan state, under control of the Scan P clock.
Intent:
Support a stable latch. In Level Sensitive Scan Design (LSSD), these are controlled by
L3s and receive that data from L1s. For more information, refer to GSD Analyze Flip-
Structures.
USER RESPONSE:
display is updated to show the path from the L2 to the L3 latches with all scan
control pins at value except P clocks are on."
To correct the deviation, remove the path from the B_SHIFT_CLOCKed latch
(L2) to the P-clocked latch (L3).
WARNING (TSV-075): Product Scan In (SI) objectName is correlated to another product

input pin(s).
EXPLANATION:

To efficiently identify each scan chain, Encounter Test does not support any pins
correlated to a Scan In (SI) pin or a SI flagged product input pin. SI pins cannot be part
of a correlated set. Encounter Test only traces forward in the scan chain from the
representative pins. If other latches are fed by pins in the correlated set, Encounter Test
will not find them.
Intent:
The Encounter Test programs assume that L1 and L2 latches can be used as control
points for creating test vectors. The method for loading values in these latches is a scan
operation. To accurately predict the contents of a scan chain, each scan chain must be
fed by a product input pin which is identified as a Scan In (SI). For more information, refer
to GSD Analyze Flip-Flop and Latch Scan Characteristics in the Encounter Test:
USER RESPONSE:
display is updated to show the flagged pin.
You can ignore this message if it is known that the correlated pins do not feed
to other latches.
To correct the deviation, perform one of the following:
- Modify the logic such that no pin is correlated to a SI flagged pin.
- Use a non-correlated pin to feed the scan chain.
WARNING (TSV-076): [Severe] Product Scan In (SI) objectName feeds an L2

objectName in the scan state.
EXPLANATION:
Guideline TB.5 section 3 states that an L1 must be the first latch in a scan chain.
Intent:
latches is a scan operation. To accurately predict the contents of a scan chain each scan
chain must be fed by a product input pin which is identified as a SI. The scan chain must
consist of alternating L1 and L2 latches that are controlled by the appropriate scan
control clock and the last L2 must control a product output pin which is identified as the

SO. For more information, refer to GSD Analyze Flip-Flop and Latch Scan
USER RESPONSE:
display is updated to show the path from the specified product SI pin to the
highlighted pin of the L2 with all scan control pins at value except B clocks are
on.
- Remove the path from the product SI to the L2.
- Install a path from the product SI to an appropriate L1.
- Install a path from an appropriate L1 to the L2.
WARNING (TSV-077): [Severe] An L2 or L4 objectName feeds another L2 or L4

objectName in the scan state.
EXPLANATION:
identified as a scan in (SI). The scan chain must consist of alternating L1 and L2 latches
that are controlled by the appropriate scan control clock.
Intent:
scan operation. To accurately predict the contents of a scan chain each scan chain must
alternating L1 and L2 latches that are controlled by the appropriate scan control clock
and the last L2 must control a product output pin which is identified as the scan out (SO).
An L1 must be controlled by an A clock and an L2 must be controlled by a B clock.
Alternating the L1 and L2 latches assures a reliable race-free operation. For more
information, refer to GSD Analyze Flip-Flop and Latch Scan Characteristics in the
USER RESPONSE:

highlighted pin of the second L2 with all scan control pins at value except B
clocks are on.
- Install a path from the first L2 to an appropriate L1 or SO pin.
- Install a path from an appropriate L2 to the second L2.
WARNING (TSV-079): [Severe] Latch objectName feeds more than one latch pin or
product Scan Out (SO) pin in the scan state.
EXPLANATION:
Guideline TB.5 section 4 states that each latch or product SO pin must be a function of
only the preceding latch or product Scan In (SI) pin.
Intent:
alternating L1
and L2 latches that are controlled by the appropriate clock and the last L2 must control
a product output pin which is identified as the SO. An L1 must be controlled by an A clock
and an L2 must be controlled by a B clock. The scan chain path cannot split into two
parallel paths because the latches in the parallel paths could not be loaded with
independent values. For more information, refer to GSD Analyze Flip-Flop and Latch
Scan Characteristics in the Encounter Test: Guide 3: Test Structures.
USER RESPONSE:
specified latch to the pins it controls are displayed with all scan control pins at
value and all clocks off.
To analyze the message, trace along the paths to determine which is the correct
path and which are the erroneous paths.

To correct the deviation, modify the design by removing the erroneous path(s)
and insert the remaining latches into valid scan chains.
WARNING (TSV-080): Product Scan In (SI) objectName feeds more than one latch pin
or product Scan Out (SO) pin in the scan state.
EXPLANATION:
Guideline TB.5 section 4 states that each latch or product SI pin must control only the
succeeding latch or product SO pin.
Intent:
alternating L1 and L2 latches that are controlled by the appropriate clock and the last L2
must control a product output pin which is identified as the SO. An L1 must be controlled
by an A clock and an L2 must be controlled by a B clock. The scan chain path cannot
split into two parallel paths because the latches in the parallel paths could not be loaded
with independent values. For more information, refer to GSD Analyze Flip-Flop and
Latch Scan Characteristics in the Encounter Test: Guide 3: Test Structures.
USER RESPONSE:
specified product SI pin to the pins it controls are displayed with all scan control
pins at value except the A clocks are on.
INFO (TSV-081): Scan chain has Scan In (SI) objectName, with Scan Out (SO)
objectName. The number of observable bit positions is number.
EXPLANATION:
identified as a SI. The scan chain must consist of alternating L1 and L2 latches that are

controlled by the appropriate scan clock. The last L2 must control a product output pin
which is identified as the SO.
Intent:
The Encounter Test programs assume that L1 and L2 can be used as control points for
creating test vectors. The method for loading values in these latches is a scan operation.
To accurately predict the contents of a scan chain, each scan chain must be fed by a
product input pin which is identified as a SI. The scan chain must consist of alternating
L1 and L2 latches that are controlled by the appropriate scan clock and the last L2 must
control a product output pin which is identified as the SO. An L1 must be controlled by
an A clock and a L2 must be controlled by a B clock. For more information, refer to
Analyze Flip-Flop and Latch Scan Chacteristics in the Encounter Test: Guide 3: Test
Structures.
USER RESPONSE:
(severity) (TSV-082): ) Zero length scan chain found. Scan In (SI) objectName Scan
Out (SO) objectName.
EXPLANATION:
A zero length scan chain (no memory elements) was found in the design. This may not
be intended and should be verified.
USER RESPONSE:
The user should check the identified scan-in pin for an unintentional SI or TDI test
function pin attribute and the identified scan-out pin for an unintentional SO or TDO
attribute and remove them in either the model or mode definition file. Note that if these
pins are still intended to be tester contacted, then some other appropriate test function
pin attribute should be used, e.g., the BOUNDARY_DATA_PIN (BDY) attribute. If the SI/
TDI and SO/TDO attributes have been intentionally placed on these pins, then the user
should ensure that their manufacturing vendor allows this condition before continuing.
WARNING (TSV-083): [Severe] Latch objectName is not included in a scan chain.

EXPLANATION:
Guideline TB.5 states that all latches must be in a scan chain during scanning. The
specified latch was not found to be in any scan chain.
Intent:

The Encounter Test programs assume all L1 and L2 latches are in scan chains and are
controllable to any value by the scan operation. For more information, refer to GSD
Analyze Flip-Flop and Latch Scan Characteristics in the Encounter Test: Guide 3:
Test Structures.
USER RESPONSE:
display is updated to show the specified latch with all scan control pins at value
except the appropriate scan clocks are on.
To analyze the message, use the mouse pointer to verify all the clock inputs to
the latch. Use Carries Clock to identify the scan port of the latch. This clock
input should be on. If the clock input is not on, trace back on the clock input to
find the source of the incorrect value. If the clock input is on, trace back on the
data input to the same port to determine why this latch is not in a valid scan
chain.
To correct the deviation, modify the design to insert this latch into a valid scan
chain.
WARNING (TSV-084): [Severe] Incomplete scan chain. Latch objectName does not
control a latch or product Scan Out (SO) pin.
EXPLANATION:
Encounter Test is trying to alert you to latches that appear to be part of a scan chain, but
the scan chain is incomplete. The path from the latch that is listed to the next latch in the
scan chain is blocked, possibly because a scan enable was not correctly identified.
Another possibility is that there is scan chain gating logic present that contains logical
redundancies. verify_test_structures may be unable to properly identify scan
chains in the presence of such redundancies.
Guideline TB.5 states that all latches must be in a scan chain during scanning, and
Guideline TBL.2 states that redundant signals in the scan path logic are not allowed. The
specified latch does not feed a latch data input pin or a SO flagged product output pin.
Intent:
operation. To accurately predict the contents of a scan chain each scan chain must be
fed by a product input pin which is identified as a Scan In (SI). The scan chain must
consist of alternating L1 and L2 latches and the last L2 must feed a product output pin

which is identified as the SO. For more information, refer to GSD Analyze Flip-Flop and
Latch Scan Characteristics in the Encounter Test: Guide 3: Test Structures.
USER RESPONSE:
except the appropriate scan clocks (those that would allow the specified latchs
value to be captured by the appropriate succeeding latch) are on.
To analyze the message, trace forward from the latch to identify the latch that
should receive the value of the specified latch during the scan operation.
- If a path to the data input of a latch exists, but the clock to that port is not on,
modify the logic to correct the latchs clocking problem.
- If a path to a latch exists, but the value at the data input of the latch is not
always the value of the specified latch (or its inverse), modify the logic so the
latch data input value reflects the value (or its inverse) of the specified latch.
- If a path to a latch does not exist, install a path to a latch of the appropriate
type.
WARNING (TSV-085): [Severe] Incomplete scan chain. Latch objectName is not

controlled by a latch or product Scan In (SI) pin.
EXPLANATION:
Encounter Test is trying to alert you to latches that appear to be part of a scan chain, but
the scan chain is incomplete. The path to the latch that is listed from the preceding latch
in the scan chain is blocked, possibly because a scan enable was not correctly identified.
Another possibility is that there is scan chain gating logic present that contains logical
redundancies. verify_test_structures may be unable to properly identify scan
chains in the presence of such redundancies.
Encounter Test "Guideline TB.5 - Scan Chain" states all latches must be in a scan chain
during scanning. The specified latch is not fed by a latch or a SI flagged product input pin.
Intent:
operation. To accurately predict the contents of a scan chain, each scan chain must be
fed by a product input pin which is identified as a Scan In (SI). The scan chain must

consist of alternating L1 and L2 latches and the last L2 must feed a product output pin
which is identified as the SO.
For more information, refer to GSD Analyze Flip-Flop and Latch Scan Characteristics
in the Encounter Test: Guide 3: Test Structures.
USER RESPONSE:
except the appropriate scan clocks (scan clocks that would allow the specified
latch to capture the value from the appropriate preceding latch/scan-in) are on.
The paths back from the specified latch to all possible candidate latches and
product inputs are also shown.
To analyze the message, trace backward from the latch to identify the latch or
product input that should feed its value to the specified latch during the scan
operation.
- If a path from a scannable latch or product scan-in exists, but the value at the
data input of the specified latch is not always the value of the preceding
scannable latch/scan-in (or its inverse), modify the logic so the data input value
of the specified latch reflects the value of the preceding scannable latch/scan-
in.
- If a path from a scannable latch or product scan-in pin does not exist, then
install such a path.
WARNING (TSV-086): [Severe] Scan Out (SO) objectName is not used in a scan chain.
EXPLANATION:
Guideline TB.5 states that all latches must be in a scan chain during scanning. Each scan
chain terminates at a SO pin.
Intent:
be fed by a product input pin which is identified as a Scan In (SI). The scan chain must
consist of alternating L1 and L2 latches that are controlled by the appropriate scan
control clock and the last L2 must control a product output pin which is identified as the
SO. Having an extra SO pin is indicative that some scan chains may be broken or the

wrong pin may have been used for SO. For more information, refer to GSD Analyze Flip-
Structures.
USER RESPONSE:
Analyze any TSV-084 messages first, they may be indicative that some scan chains may
be broken or the wrong pin may have been used for SO.
display is updated to show the design with all scan control pins at value except
B clocks are on.
To analyze the message, trace backward from the specified SO pin to locate the
L2 that should control this SO pin during the scan operation.
- If a path to an L2 exists, but the value at the SO pin is not always the value of
the L2 (or its inverse), sensitize the path by means of additional or changed
scan enable (SE) inputs.
- If a path to an L2 does not exist, either remove the SO flag from the product
input pin or install a path from an L2 to the SO pin.
INFO (TSV-090): The three-state driver checks were invoked, however there are no three-
state drivers (TSDs) on the circuit.
The selected check is called: Ensure three-state drivers are disabled.
EXPLANATION:
Intent:
The three-state driver checks were selected by the user but there are no TSDs on the
circuit.
USER RESPONSE:
WARNING (TSV-091): [Severe] The design contains three-state drivers (TSDs) that feed
product output pins however no Test Inhibit (TI), Test Constraint (TC), or Bidirectional Inhibit
(BI) test function pins were defined.
EXPLANATION:

Guideline TBT.7 section 2 states there must exist product input pins Test Inhibit (TI), Test
Constraint (TC) or Bidirectional (BI) pins, which when set to their stability value, force all
TSDs that feed to product outputs to the high impedance state.
Intent:
The main purpose of this guideline is to allow your manufacturing site to easily generate
a parametric test to verify that TSDs can achieve the high impedance state. Also, this
ability to achieve high impedance is sometimes used to calibrate drivers and level
detectors on TSD nets.
These capabilities can help prevent product damage during testing, as well as improve
diagnosis when a problem exists with a TSD output net.
For more information, refer to "Guideline TBT.7 - Three-State Drivers" and "Ensure
External Three-state Drivers are Disabled" for GSD in the Encounter Test: Guide 3:
Test Structures.
USER RESPONSE:
display is updated to show the design with the Test Inhibit (TI), Test Constraint
(TC), and Bidirectional Inhibit (BI) pin at value.
To analyze the message, use the mouse pointer to verify the pins intended for
TI, TC, and BI. The Information Window will indicate that no control definition
exists for these pins.
To correct the deviation, add a test function pin attribute of TI, TC, or BI to the
product input pins which require these controls.
WARNING (TSV-092): [Severe] Three-state driver (TSD) objectName is not at high

impedance when all Test Inhibit (TI), Test Constraint (TC), and Bidirectional Inhibit (BI) test
function pins are at their specified value.
EXPLANATION:
Guideline TBT.7 section 2 states there must exist product input pins Test Inhibit (TI), Test
Constraint (TC) or Bidirectional (BI) pins, which when set to their stability value, force all
TSDs that feed to product outputs to the high impedance state.
Intent:
The main purpose of this guideline is to allow your manufacturing site to easily generate
a parametric test to verify that TSDs can achieve the high impedance state.

Also, this ability to achieve high impedance is sometimes used to calibrate drivers and
level detectors on TSD nets.
These capabilities can help prevent product damage during testing, as well as improve
diagnosis when a problem exists with a TSD output net.
For more information, refer to "Guideline TBT.7 - Three-State Drivers" and "Ensure
External Three-state Drivers are Disabled" for GSD in the Encounter Test: Guide 3:
Test Structures.
USER RESPONSE:
display is updated to show the TSD with the Test Inhibit (TI), Test Constraint
(TC), and Bidirectional Inhibit (BI) pin at value.
To analyze the message, use the mouse pointer to verify the value of the input
pins for the TSD. Trace backward to find the source of the incorrect value(s).
To correct the deviation, modify the logic so that the enable input of this TSD is
controlled by TI, TC or BI pins.
WARNING (TSV-093): [Severe] During the scan operation scanSectionName three

state netName is sourced by sourceName1 and sourceName2 which may
simultaneously drive opposite values resulting in 3-state contention.
EXPLANATION:
Note: If there are multiple scan sections, then the scan section name appears in the
message test. If there is a single scan section, the scan section name is blank.
Guideline TB.8 section 1 states that the application of test data to a product must not
damage the product due to multiple inputs to a three-state net being simultaneously
driven to opposite values.
Note: Consider All DOTTs which burn (they have 3-state contention) in the Scan State
as X-Sources.
Intent:
Ensure that the loading of data into the scan chains during the scan operation does not
destroy the product by causing a 3-state contention burn-out condition. Three-state

contention can also result in excess power consumption as well as possible damage to
the product and invalid signatures.
The Encounter Test applications assume that the scan operation is free of three-state
contentions.
For more information, refer to Analyze Three-state Drivers for Contention for GSD in
USER RESPONSE:
Select the specific message from the Specific Message List. The net and blocks
listed in the message are displayed. The design is set to the Scan state with
simulation values applied which drive the net to opposite values.
pins and nets comprising the paths.
To correct the deviation, install logic which prevents both blocks feeding the net
from being simultaneously driven to opposite values.
specified EFFORT level while processing this message: During the scan operation
scanSectionName three state netName is sourced by sourceName1 and
sourceName2 which may simultaneously drive opposite values resulting in 3-state
contention.
EXPLANATION:
Note: If there are multiple scan sections then the scan section name appears in the
message test. If there is only a single scan section, the scan section name is blank.
cannot occur.

Guideline TB.8 section 1 states that the application of test data to a product, must not
damage the product due to multiple inputs to a net being simultaneously driven to
opposite values.
Intent:
To ensure that the loading of data into the scan chains does not destroy the product.
Three-state contention can also result in excess power consumption as well as possible
damage to the product and invalid signatures.
contentions.
USER RESPONSE:
listed in the message are displayed. The design is set to the Scan state.
If you suspect this is not a true error condition, rerun this test with a higher
which is equivalent to effort=5.
To rerun this test add reruntests=yes to the command line. Increasing the effort
level may cause the test to run longer, and the test may still abort on this violation.
WARNING (TSV-095): A flop or latch objectName of the scan chain changes value at the
same time the next latch or flop of the scan chain objectName captures its value. The pulse
width of the clock must be wide enough for the value to propagate to the down-stream flop or
latch.
EXPLANATION:
Each register (latch or flop) of a scan chain must capture the value of the upstream
register (latch or flop) in a race free manner.
Intent

A cycle of the scan clocks must result in the downstream register of an internal scan
chain capturing the data which is loaded into the upstream register during the preceding
cycle of the scan clocks.
USER RESPONSE:
Select the specific message from the Specific Message List. The path between the
scan chain registers will be displayed. The design is set to the Scan state.
To analyze the message, identify the scan clocks which control the respective
registers.
To correct the deviation, modify the design or scan sequence such that the clocks to
the registers are controlled properly or ensure that the pulse width of the clock is
wide enough for the value to propagate to the down-stream flop or latch.
If the identified latches or flops are clocked in the same event of the scan sequence then
the most likely cause is a missing lock-up latch.
WARNING (TSV-096): A flop or latch objectName of the pipeline changes value at the
same time the next latch or flop of the pipeline objectName captures its value.The pulse
width of the clock must be wide enough for the value to propagate to the down-stream flop or
latch.
EXPLANATION:
Each register (latch or flop) of a pipeline must capture the value of the upstream register
(latch or flop) in a race free manner.
Intent
A cycle of the scan clocks must result in the downstream register of the pipeline capturing
the data which is loaded into the upstream register during the preceding cycle of the scan
clocks.
USER RESPONSE:
pipeline registers will be displayed. The design is set to the Scan state.
registers.
the registers are controlled properly or or ensure that the pulse width of the clock is
wide enough for the value to propagate to the down-stream flop or latch.

If the identified latches or flops are clocked in the same event of the scan sequence then
the most likely cause is a missing lock-up latch.
WARNING (TSV-097): A flop or latch objectName of the channel mask shift register
changes value at the same time the next latch or flop of the channel mask shift register
objectName captures its value. The pulse width of the clock must be wide enough for the
value to propagate to the down-stream flop or latch.
EXPLANATION:
Each register (latch or flop) of a channel mask shift register must capture the value of the
upstream register (latch or flop) in a race free manner.
Intent
A cycle of the channel mask shift register clocks must result in the downstream register
capturing the data which is loaded into the upstream register during the preceding cycle
of the clocks.
USER RESPONSE:
pipeline registers will be displayed. The design is set to the channel mask load state.
To analyze the message, identify the channel mask load clocks which control the
respective registers.
To correct the deviation, modify the design or channel mask load sequence such
that the clocks to the registers are controlled properly or ensure that the pulse width
of the clock is wide enough for the value to propagate to the down-stream flop or
latch.
If the identified latches or flops are clocked in the same event of the channel mask load
sequence then the most likely cause is a missing lock-up latch.
WARNING (TSV-098): A flop or latch objectName of the OPCG shift register changes
value at the same time the next latch or flop of the OPCG shift register objectName
captures its value. The pulse width of the clock must be wide enough for the value to
propagate to the down-stream flop or latch.
EXPLANATION:
Each register (latch or flop) of a OPCG shift register must capture the value of the
upstream register (latch or flop) in a race free manner.

Intent
A cycle of the OPCG shift register clocks must result in the downstream register
capturing the data which is loaded into the upstream register during the preceding cycle
of the clocks.
USER RESPONSE:
OPCG registers will be displayed. The design is set to the OPCG load state.
registers.
To correct the deviation, modify the design or OPCG load sequence such that the
clocks to the registers are controlled properly or ensure that the pulse width of the
clock is wide enough for the value to propagate to the down-stream flop or latch.
If the identified latches or flops are clocked in the same event of the OPCG load
sequence then the most likely cause is a missing lock-up latch.
ERROR (TSV-099): Severe processing error, verify_test_structures has terminated

early. error description
EXPLANATION:
A condition was encountered from which verify_test_structures cannot recover.
All verify_test_structures checking is suspect.
Intent:
A problem exists in the data verify_test_structures uses to perform its checks.
This message is issued to protect verify_test_structures from abnormal
terminations.
USER RESPONSE:
A brief explanation concerning the verify_test_structures scenario in
which you failed.


WARNING (TSV-101): [Severe] Unpredictable signal value (X) from xSource Type
objectName1 may be observed at objectName2.
EXPLANATION:
Guideline TBS.2 - Unpredictable Signal Values states that unknown or oscillating signal
values must not be observable in signature-based testing.
The block or pin designated as the observe point will be either a primary output or an
active memory element. The memory element may not be directly observable but is
eventually observable through a primary output or observable memory element. If an x-
source feeds an inactive memory element, the inactive memory element will not be used
as an observe point. If no active observe points can be found, then the x-source does not
effect any observable logic and therefore is not a violation.
Examples of X source types inserted in the above message are as follows:
Tie X Block
Data-out of an uninitialized RAM
Unterminated TSD
Floating Latch
MISR Latches (except in On-Product MISR testmodes)
Product Pins not connected to the tester
Scannable Latches which are corruptible to X
Clock Choppers Requiring Pessimistic Simulation
Dotts with Proven 3-state Contention (from TSD Contention Check)
Unclamped outputs of power domains that are turned off
Refer to GSD Guideline TBS.2 - Unpredictable Signal Values" in the Encounter Test:
Guide 3: Test Structures for a complete list of all the sources of X that are checked.
Intent:
This guideline ensures that predictable and repeatable results will be accumulated in
signature collection devices when signature based testing is employed.
USER RESPONSE:
display is updated to show the path from the X source to the observe point, with
the design state required to enable the path.

To correct the deviation, install logic to block all paths from the source of X to
memory elements, RAMs, and primary outputs.
WARNING (TSV-102): [Severe] Unpredictable signal value (X) from a non-Test

EXPLANATION:
In the internal test mode using RPCT Boundary Scan, non-test pins are supposed to be
blocked from affecting the test operation. This ensures that the tests are still valid when
applied in an environment where these pins are not accessible. This restriction is
especially important in signature-based testing. For stored-pattern testing, this is still
considered to be an important guideline but the test generator can place an X on the
offending pin to ensure that the effect of the pins actual value is ignored.
The block or pin designated as the observe point will be either a primary output or an
active memory element. The memory element may not be directly observable but is
eventually observable through a primary output or observable memory element. If an x-
source feeds an inactive memory element, the inactive memory element will not be used
as an observe point. If no active observe points can be found, then the x-source does not
effect any observable logic and therefore is not a violation.
Intent:
USER RESPONSE:
display is updated to show the path from the non-Test pin to the observe point,
with the design state required to enable the path.
Unpredictable signal value (X) from xSource Type

EXPLANATION:
cannot occur.
Guideline TBS.2 states that unknown or oscillating signal values must not be observable
in signature-based testing.
Examples of X source types inserted in the above message are as follows:
Tie X Block
Data-out of an uninitialized RAM
Unterminated TSD
Floating Latch
MISR Latches (except in On-Product MISR testmodes)
Product Pins not connected to the tester
Scannable Latches which are corruptible to X
Clock Choppers Requiring Pessimistic Simulation
Guide 3: Test Structures for a complete list of all the sources of X that are checked.
Intent:
Refer to "Ensure X-sources Cannot be Observed" for GSD in the Encounter Test:
Guide 3: Test Structures for more information.
USER RESPONSE:
effort level. The default effort level if none was specified is
effort=medium which is equivalent to effort=5. To rerun this test add

reruntests=yes to the command line. Increasing the effort level may cause
the test to run longer, and the test may still abort on this violation.
display is updated to show the path from the X source to the observe point.
Unpredictable signal value (X) from a non-Test objectName1 may be observed at
objectName2.
EXPLANATION:
cannot occur.
In the internal test mode using RPCT Boundary Scan, non-test pins are supposed to be
blocked from affecting the test operation. This ensures that the tests are still valid when
applied in an environment where these pins are not accessible.
This restriction is especially important in signature-based testing. For stored-pattern
testing, this is still considered to be an important guideline but the test generator can
place an X on the offending pin to ensure that the effect of the pins actual value is
ignored.
Intent:

USER RESPONSE:
display is updated to show the path from the non-Test to the observe point.
WARNING (TSV-105): [Severe] MISR memory element was found to be feeding

observable logic. MISR memoryElementName may be observed at observeName.
EXPLANATION:
A MISR is not allowed to feed observable logic for 2 reasons:
This is a Encounter Test limitation. Signature computation is significantly
speeded up by simulating successive tests in parallel. This means that when a
given test is being simulated, the MISR state resulting from that test is not yet
known.
When diagnosing failing devices, it is often useful to collect data for several
failing tests. In signature analysis, this is possible by predicting the effect of a
failure upon subsequent states of the signature register. This technique does
not work if the failing signature affects subsequent tests through the logic.
USER RESPONSE:
Select the specific message from the "Specific Message List". The schematic
display is updated to show the path from the MISR memory element to the
observe point, with the design state required to enable the path.
To correct the deviation, install logic to block all paths from the MISR source to
memory elements, RAMs and ROMs.
It is recommended that this blocking be placed as close to the MISR as possible
to minimize the amount of untestable logic that may result.

WARNING (TSV-106): [Severe] MISR memory element feeding observable logic checking
aborted with the specified EFFORT level. MISR memoryElementName may be observed
at observeName.
EXPLANATION:
Verify Test Structures looks for mutually exclusive gating to render this condition
inoperative, but this message indicates checking stopped for gating that would prevent
the error before reaching a resolution.
This is a Encounter Test limitation. Signature computation is significantly
speeded up by simulating successive tests in parallel. This means that when a
given test is being simulated, the MISR state resulting from that test is not yet
known.
When diagnosing failing devices, it is often useful to collect data for several
failing tests. In signature analysis, this is possible by predicting the effect of a
failure upon subsequent states of the signature register. This technique does
not work if the failing signature affects subsequent tests through the logic.
USER RESPONSE:
display is updated to show the path from the MISR Latch source to the observe
point.
To correct the deviation, install logic to block all paths from the MISR Latch
source to memory elements, RAMs, and ROMs.
It is recommended that this blocking be placed as close to the MISR as possible
to minimize the amount of untestable logic that may result.
WARNING (TSV-107): [Severe] A Cascaded Series of uninitialized floating registers

produces unpredictable signal values (X).The first register in the series is
memoryElement1, the last register is memoryElement2 and there are count stable
registers in the series.
EXPLANATION:
A cascading series of uninitialized floating registers (flops or latches) has been found.
Each register is an instance of an observable X-source and every register in the series

has a common un-initialized floating register source. Throughout the cascaded series
each uninitialized floating register that follows the x-source register is both the capture
point for the x-source as well as being an x-source itself. The first and last registers in the
cascaded series are given in the message and can be used as starting and ending points
in helping to resolve the other uninitialized register x-sources in the cascading series.
Intent:
USER RESPONSE:
display is updated to show the first and last stable uninitialized floating.registers
in the cascaded series. The last uninitialized floating register in the cascaded
series will appear as an x-source in a TSV-101 message with the appropriate
observe point indicated.
scannable registers, RAMs, and primary outputs
INFO (TSV-108): The X-Source check was invoked before the TSD Contention check was
run. The TSD Contention check will now be automatically invoked. When the TSD Contention
check completes, the X-Source check will be run.
EXPLANATION:
The X-Source check includes detecting X-Sources in DOTTs that have proven three-
state contention errors. However, when the X-Source check was invoked the TSD
Contention check had not yet been run and will now be automatically run prior to invoking
the X-Source check.
Intent:
DOTTs that have proven three-state contention are considered potential X-Sources. To
ensure that any such DOTTs are not observable, the TSD Contention check must be run
prior to invoking the X-Source check so they can be checked as potential X-Sources.
USER RESPONSE:
WARNING (TSV-110): Latch latchname has a user-specified fixed value latch test
function of vtf, but this is not a fixed value latch. The test function is ignored.

EXPLANATION:
Guidelines TB.9 and TG.11 describe the design requirements for fixed value latches. It
is not necessary to specify a test function for every fixed value latch, but a latch must be
fixed value for a test function to be specified for it.
Intent:
The only test functions that are supported on latches are test_inhibit (TI) and
fixed_value_latch_line_hold (FLH), and these test functions are not valid on a
latch unless it is fixed value. This check ensures that the test function specification was
valid.
USER RESPONSE:
display is updated to show the port(s) on the latch that are not fixed value.
For a port to be fixed value, either the clock must be held "off" or the data input
must be at the fixed value. You should find out by consulting the product
designer which method was intended; then you can trace back from the
appropriate latch input (clock or data) to see where the necessary gating should
have been put.
To correct the deviation, either gate the clock or the data input with a TI signal
so that in this test mode the requirement stated in Step 2 is satisfied for this
input.
WARNING (TSV-111): Latch latchName has a user-specified test function of vtf, but its
initial value is value. Its effective test function is effectiveTestFunction.
EXPLANATION:
One purpose of the test mode initialization sequence is to set all fixed value latches to
their designated states. In this case, the initial value, determined by the mode
initialization sequence, is different from the state designated by the test function
specification.
Intent:
The test function value used by Encounter Test is determined from the mode initialization
sequence. This check provides you a warning that this is different from what was
specified in the test function for this latch.
USER RESPONSE:

Change the mode initialization sequence to put the correct initial value into the latch,
which agrees with the test function specified. Rebuild the test mode and rerun all
subsequent processing.
WARNING (TSV-115): Latch latchName is a fixed value latch, but no test function was
specified for it. The test function defaulted to vtf.
EXPLANATION:
Encounter Test supports two kinds of fixed value latch: Those that cannot be overridden
(TI) and those that can be overridden when a test generation run is made (FLH). The test
function attribute can be specified either in the model source or in the mode definition. If
it is not specified in either place, then a default test function (specified in the mode
definition) is used. If the FIXED_VALUE_DEFAULT is not specified in the mode
definition, then this parameter itself defaults to test_inhibit (TI).
Intent:
This ensures that Encounter Test treats each fixed value latch in a consistent manner.
This check informs the user which kind of fixed value latch was assumed for each one
that did not have an explicit test function.
USER RESPONSE:
display is updated to show the latch along with the logic that makes it fixed value
(the clock gating logic if it is by clock gating, and the data path if it is
implemented by data gating).
Make sure that the latch is being treated correctly by Encounter Test. If so, then
no action is necessary; otherwise, specify the correct test function in the mode
definition and rebuild the test mode, or edit the design source to specify the test
function and re-import the circuit. If most of the fixed value latches are wrong,
then you may prefer to change the FIXED_VALUE_DEFAULT in the mode
definition and rebuild the test mode.
WARNING (TSV-118): Clock convergence violation. A pulse on one clock input cannot
propagate through blockName when another clock input is OFF in the state state. One of
the clocks is clockName1 and the other clock is clockName2 . This may affect the
testability of the blocked clock input paths.
EXPLANATION:

Intent:
When two clocks are logically ANDed, faults on the input clock trees may be ATPG-
untestable. In this case, there is a logical ANDing of one clock with the invert of one or
more other clocks.
This allows pulses on one clock o get through when the other clock is OFF, but prevents
pulses on this second clock from getting through when the first clock is OFF. Since ATPG
will normally not turn ON more than one clock at a time, the inverted clock input trees will
not be tested for any stuck-OFF faults that must pass through blockName in order to
be detected.
When one clock is logically ANDed with the invert of another clock, a pulse on the first
clock can get through when the second clock is OFF, but a pulse on the second clock
cannot get through when the first clock is OFF. Since ATPG normally will turn only one
clock ON at a time, some faults within the clock tree for the second clock may remain
ATPG-untestable. Allowing ATPG to turn more than one clock ON at one time is very risky
since the analysis for clock control is done with the assumption that there will be at most
one clock ON at a time.
USER RESPONSE:
To analyze the condition, use the mouse pointer to identify the individual blocks,
To eliminate the condition modify the logic such that only one clock topologically
feeds the block or net.
In some cases, the clock OFF polarity can be switched to cause a logical clock
ORing condition instead of a logical clock ANDing condition. This solution is not
possible when the offending clock feeds to both a clock ANDing and a clock
ORing convergence. Switching the clock polarity causes existing logical clock
ORing to then appear to be logical clock ANDing. In such cases, it may be
beneficial to define two test modes: one mode defines the clock OFF state as 0
and the other mode defines the clock OFF state as 1.

WARNING (TSV-120): OPC logic objectName is fed by a scannable memory element

objectName.
EXPLANATION:
The logic driving this cut point appears to be partially controlled by the scannable
memory element identified. If the value on this cut point really does depend upon this
latch, then all sequence definitions in this test mode must either block the paths between
this memory element and the cut point or must load the memory element to some
specific state before the cut point value is used by the downstream logic. See "Guideline
OPC.4 - OPC Scannable Latches" in the Encounter Test: Guide 3: Test Structures
for further explanation.
USER RESPONSE:
display is updated to show the path from the scannable memory element to the
OPC logic. The design is set to the Test Inhibit state.
Make sure that all the user-supplied clock sequences control this memory
element deterministically, that is, it must be load with a specific value by the
sequence. In a test sequence which contains Scan_Load events, the memory
element state must be specified in the Scan_Load event to prevent the state
from being set arbitrarily by the test vector.
WARNING (TSV-121): OPC logic objectName is fed by an active non-scannable memory

element objectName.
EXPLANATION:
The logic driving this cut point appears to be partially controlled by the non-scannable
memory element identified, and the memory element is in the active logic (i.e.,
observable). The danger is that the test generator may think it can control this memory
element, since it is in the active region, but if the memory element is really contributing
to the behavior of the OPC logic, then it must be controlled directly by the user-provided
sequence definitions. Hence, poor test coverage may result.
USER RESPONSE:
display is updated to show the path from the active non-scannable memory
element to the OPC logic. The design is set to the Test Inhibit state.
If the memory element is not part of the OPC logic, check for missing TI
attributes that would block its signal from propagating to any cut point. If there
are no missing TI attributes, then make sure that all sequences are disabling
the latch from controlling a cut point.

If you intended this memory element to be part of the OPC logic and you are
using stored pattern or WRP tests, then you may want to specify lineholds to
help direct the test generator from trying to use this latch incorrectly.
Refer to Linehold File in the Automatic Test Pattern Generation User Guide
WARNING (TSV-122): OPC logic objectName is fed by a linehold fixed value latch
objectName.
EXPLANATION:
The logic driving this cut point appears to be partially controlled by the latch identified. If
the value on this cut point really does depend upon the memory element, then its
behavior cannot be fully specified by user-supplied clocking sequences. Encounter Test
depends upon the user-supplied clocking sequences to model the logic driving the cut
point; therefore the configuration found here is not supported. See "Guideline OPC.2 -
OPC Fixed Value Latches" in the Encounter Test: Guide 3: Test Structures for further
explanation.
USER RESPONSE:
display is updated to show the path from the linehold fixed value latch to the
OPC logic. The design is set to the Test Inhibit state.
Make sure that all the user-supplied clock sequences will block this memory
element from affecting the cut point. If they do not, then it will be necessary to
change the logic or specify a TI attribute on the fixed value latch.
WARNING (TSV-123): OPC logic objectName is fed by a RAM objectName.

EXPLANATION:
The logic driving this cut point appears to be partially controlled by the RAM identified. If
the value on this cut point really does depend upon the RAM outputs, then its behavior
cannot be specified by a user-supplied clocking sequence unless the sequence loads the
required RAM state before the RAM output is used. Encounter Test does not support any
method of verifying that a sequence will work if it writes and reads RAMs in the
generation of OPC signals. See "Guideline OPC.5 - OPC RAMs" in the Encounter Test:
Guide 3: Test Structures for further explanation.
USER RESPONSE:
display is updated to show the path from the RAM to the OPC logic. The design
is set to the Test Inhibit state.

To eliminate this message, you will have to change the OPC logic or respecify
the cut points so that no cut point is downstream from a RAM output. If the logic
must operate as described, then if possible you should at least make sure that
all sequence definitions block all the paths from RAM outputs to cut points. If
this too is impossible, then you can still proceed and get valid tests by making
sure that the RAM is properly initialized before being used by any clocking
sequence.
WARNING (TSV-124): OPC logic objectName is fed by a Pseudo-Random Pattern

Generator (PRPG) memory element objectName.
EXPLANATION:
The logic driving this cut point appears to be partially controlled by the Pseudo-Random
Pattern Generator (PRPG) memory element identified. If the value on this cut point really
does depend upon the PRPG state, then its behavior cannot be fully specified by user-
supplied clocking sequences.
USER RESPONSE:
display is updated to show the path from the PRPG latch to the OPC logic. The
design is set to the Test Inhibit state.
Change the OPC logic or respecify the cut points so that no cut point is
downstream from a PRPG memory element.
WARNING (TSV-125): OPC logic objectName is fed by a Multiple-Input Signature

Register (MISR) memory element objectName.
EXPLANATION:
The logic driving this cut point appears to be partially controlled by the Multiple-Input
Signature Register (MISR) identified. If the value on this cut point really does depend
upon the MISR state, then its behavior cannot be fully specified by user-supplied clocking
sequences.
USER RESPONSE:
display is updated to show the path from the MISR memory element to the OPC
logic. The design is set to the Test Inhibit state.
Change the OPC logic or respecify the cut points so that no cut point is
downstream from a MISR memory element.

WARNING (TSV-126): [Severe]: Register Type objectName Register Type

and objectName are in the OPCG scan chain bit therefore they cannot be loaded to
independent values.
EXPLANATION:
The OPCG scan chain includes both of the identified latches or flops in the same bit
position. This condition prevents those latches or flops from being loaded independently.
The opcg programming may require different values in those latches or flops which
cannot be achieved as they are correlated.
USER RESPONSE:
Select the specific message from the Specific Message List. The circuit display is
updated to show two latches or flops. The circuit is set to the OPCG load state.
Change the OPCG scan chain logic to allow the flops or latches to load
independently.
WARNING (TSV-127): [Severe]: Register Type objectName and Register

Type objectName are in the scan chain bit therefore they cannot be loaded to independent
values.
EXPLANATION:
The scan chain includes both of the identified latches or flops in the same bit position.
This condition prevents those latches or flops from being loaded independently. The
opcg programming may require different values in those latches or flops which cannot be
achieved as they are correlated.
USER RESPONSE:
The circuit display is updated to show two latches or flops.
The circuit is set to the Scan state.
Change the scan chain logic to allow the flops or latches to load independently.
WARNING (TSV-130): Latch or FLOP objectName is part of OPCG programming register

regName, but does not appear to hold its value once loaded.
EXPLANATION:
The latch or DFF is part of a OPCG programming register but does not appear to hold
its value once loaded. It is possible the OPCG logic will not perform as expected.
USER RESPONSE:


The OPCG latch/DFF is displayed and the design is set to the Test Constraint
state.
Ensure the OPCG Register programming will hold until reprogrammed.
WARNING (TSV-131): Latch or FLOP objectName is part of PLL programming register

regName, but does not appear to hold its value once loaded.
EXPLANATION:
The latch or DFF is part of a PLL programming register but does not appear to hold its
value once loaded. It is possible the PLL logic will not perform as expected.
USER RESPONSE:
The PLL latch/DFF is displayed and the design is set to the Test Constraint
state.
Ensure the PLL Register programming will hold until reprogrammed.
WARNING (TSV-132): OPCG programming register regName has inconsistent or missing

load methods for one or more bits.
EXPLANATION:
This message is issued for one of two reasons:
One or more bits of the register have no loading method
One or more bits of the register has a different loading method than other bits
of the register
An OPCG programming register must be loaded for a given test mode using one of the
following methods:
Loaded by the Modeinit of the parent (Register bits act as fixed value latches in
target test mode)
Loaded via the Scan Load Operation
Loaded via the OLI input as a separate serially loaded register
The referenced OPCG register contained bits loaded by a combination of these loading
methods or had no loading method.
USER RESPONSE:


Correct the design by loading this register using only one of the Explanations
described loading methods for all bits.
WARNING (TSV-133): PLL programming register regName has inconsistent or missing

load methods for one or more bits.
EXPLANATION:
This message is issued for one of two reasons:
One or more bits of the register have no loading method
One or more bits of the register has a different loading method than other bits
of the register
A PLL programming register must be loaded for a given test mode using one of the
following methods:
Loaded by the Modeinit of the parent (Register bits act as fixed value latches in
target test mode)
Loaded via the Scan Load Operation
Loaded via the OLI input as a separate serially loaded register
The referenced PLL register contained bits loaded by a combination of these loading
methods or had no loading method.
USER RESPONSE:
Correct the design by loading this register using only one of the Explanations
described loading methods for all bits.
WARNING (TSV-140): [severity] The scan sequence must be stored as a single

vector, stimming objectName during custom scan sequence, sequence name is not
allowed.
EXPLANATION:
At the tester, the scan sequence (definition of one shift cycle) is stored as a single vector
with an associated timing template. Each element in the vector corresponds to one
associated primary input and tells some action to perform on that PI. The action in this
case is typically a pulse. Stims are outlawed because, since only a single pin action is
supported here, a stim would be tantamount to lineholding that pin throughout the scan
process.

USER RESPONSE:
Change the custom scan sequence to only pulse pins.
WARNING (TSV-141): [severity] The scan sequence must be stored as a single

vector, objectName stimming|plusing more than once during custom scan
sequence, sequence name is not allowed.
EXPLANATION:
This limitation allows no more than one pulse on the same pin during a loopable
(scansequence) sequence, and one stim on the same pin during a non-loopable
(scanlastbit) sequence.
USER RESPONSE:
The loopable scan sequence must be modified to pulse the same pin only once.
The non-loopable scan sequence must be modified to stim the same pin only
once.
WARNING (TSV-142): [severity] The scan sequence sequence name must consist
of only one pattern
EXPLANATION:
The TDR requires the scan sequence to be stored as a single pattern, containing no
stims and at most one pulse per clock pin.
USER RESPONSE:
Modify the scan sequence so it has only one pattern.

WARNING (TSV-163): Scan chain register memoryElementName changes value during
the same scan cycle as scan chain register memoryElementName. The upstream and
downstream registers are changing on the same cycle but the clocks are in different domains
which may cause the scan chain to fail to shift properly.
EXPLANATION:
A cycle of the scan clocks must result in a race free shift of the scan chain. When
successive registers of a scan chain are clocked within the same scan cycle but from
different domains the downstream register may capture either the old value in the
upstream register or the new value depending on the actual circuit delays. In a validly
constructed scan chain the upstream register (latch or flop) of the scan chain must feed

to a downstream register (latch or flop) which does not update on the same cycle of the
scan sequence or is in the same clock domain.
USER RESPONSE:
Select the specific message from the Specific Message List. The upstream and
downstream scan chain registers will be displayed. The design is set to the Scan
state.
registers.
the registers are controlled to update the scan chain registers on different cycles of
the scan sequence or change the clocking such that both registers use the same
clock.
WARNING (TSV-173): [Severe] Multiple-Input Signature Register (MISR) input to memory

element memoryElementName has multiple sources.
EXPLANATION:
Each MISR data input must be fed from a single scan chain output.
Intent:
This message indicates that during scanning the MISR input is monitoring multiple
memory elements and primary inputs.
This is not supported due to the extra expense that would be involved in signature
calculation.
Also, unless the function of the multiple source is an XOR, there would be information
loss, resulting in inaccurate test coverage reporting.
USER RESPONSE:
Select the specific message from the "Specific Message List".
The latch specified in the message is displayed with the TI state applied.
Trace back from the data input to find the stray path(s).
To correct the deviation, modify the design so the MISR memory element
indicated in the message monitors the output of a single channel or Scan In (SI)
primary input or the XOR of PRPG outputs.
INFO (TSV-175): A non-Scan In (SI) PI piName feeds into Multiple-Input Signature Register
(MISR) latch data input dataInputName.

EXPLANATION:
MISR inputs must come from valid channels for Encounter Test to properly calculate
signatures. Encounter Test does allow for a channel to have zero length (no memory
elements) but the null channel must have a proper channel input. The channel input may
be a single scan data primary input, or a function of PRPG latches. Under this guideline,
the channel input must be either a single scan data primary input, a single PRPG
memory element, the XOR function of several PRPG memory elements, or an arbitrary
function of PRPG memory elements and primary inputs.
Intent:
Encounter Test allows only internal channels or channels identified by a SI flag to feed
to MISR inputs during scan.
USER RESPONSE:
If all your memory elements are included in channels and your channels are connected
properly to MISR inputs, probably this is an extra MISR input that can either be gated off
during scan, connected to a Pseudo Random Pattern Generator (PRPG) memory
element , or an SI pin. Otherwise, there may be a wrong connection whereby the PI is
feeding the MISR instead of some channel memory element.
INFO (TSV-181): Multiple-Input Signature Register (MISR) was found. The first memory
element of the MISR is firstMemoryElementName the last memory element is
lastMemoryElementName.
EXPLANATION:
No rules or restrictions, as this message is informational in nature.
Intent:
To identify the first and last memory elements of a Linear Feedback Shift Register (LFSR)
which operates as a MISR.
USER RESPONSE:
WARNING (TSV-182): [Severe] Last memory element of Linear Feedback Shift Register
(LFSR) could not be found from the identified objectName.
EXPLANATION:

Intent:
Encounter Test recognizes a Pseudo Random Pattern Generator (PRPG) or Multiple
Input Signature Register (MISR) by its constituent latch primitives.
The indicated net is supposed to identify the LFSRs output net. If there is any fan-in
between the memory element and the indicated output net, Encounter Test will fail to find
any of the constituent memory elements.
USER RESPONSE:
The net specified in the message is displayed with the TI state applied.
Trace back on the inputs to the net to identify the memory element which should
have fed to the net.
To correct the deviation, modify the logic such that the last memory element of
the LFSR is the only memory element which feeds the net.
WARNING (TSV-183): [Severe] Linear Feedback Shift Register (LFSR) memory element
objectName does not have any clock inputs on (1) in the unload simulation states.
EXPLANATION:
Intent:
Encounter Test requires that an identified LFSR operate according to the polynomial
specified on the Pseudo Random Pattern Generator (PRPG) or Multiple Input Signature
Register (MISR) attribute.
For this to occur an LFSR latch must accept data from other LFSR latches.
If no clock input ever achieves the on (one) state this is impossible.
USER RESPONSE:
The memory element specified in the message is displayed with the TI state
applied.
Trace back on the clock input(s) to the memory element to identify why the scan
clock is not controlling the input.
To correct the deviation, modify the logic such that the application of the scan
clock causes the clock input of the memory element to be on.

WARNING (TSV-184): [Severe] Pseudo-Random Pattern Generator (PRPG) memory

element objectName is fed by more than 1 candidate for the preceding memory element
of the PRPG.
EXPLANATION:
Intent:
Encounter Test requires that an identified Linear Feedback Shift Register (LFSR) operate
according to the polynomial specified on the PRPG or Multiple Input Shift Register
(MISR) attribute.
For this to occur a PRPG memory element must accept data only from other PRPG
memory elements.
There is no valid configuration in which a PRPG memory element could accept data from
more than one memory element that has not already been identified as part of this PRPG
when working backwards from the last memory element of the PRPG.
USER RESPONSE:
Trace back on the data input(s) to the memory element to identify the potential
candidates for preceding memory elements of the PRPG.
To correct the deviation, modify the logic such that only one of the memory
elements of the PRPG feeds the data input of the specified memory element.
INFO (TSV-185): Multiple-Input Signature Register (MISR) latch objectName feeds more
than 1 candidate for the next memory element of the MISR.
EXPLANATION:
The use of on-board signature analysis is specified by on-board scan output and the
identification of a MISR through the source logic description or the mode definition file.
verify_test_structures determines which latches comprise the MISR through a
logic trace from the MISR net identified in the logic source or mode definition.
Intent:
verify_test_structures was unable to completely trace out the MISR memory
elements.
USER RESPONSE:


applied.
Trace forward from the specified memory element to identify the other (non-
MISR) memory element(s) or some MISR memory element other than the next
succeeding memory element in the LFSR.
If any such path exists and it is not a logic error, then there must be a test inhibit (TI)
signal or fixed-value latch signal that blocks the path when operating in the test
mode.
To correct the deviation, modify the logic such that the specified MISR memory
element that feeds the data input of only the succeeding MISR memory
element. If you are still unable to find the problem, maybe the LFSR was
identified incorrectly.
For a multiplier LFSR, the first memory element is the only one that should come
from more than one MISR memory element. The memory element at the other end
of the register, the "last memory element" is the one that is to be used in the logic
source or mode definition file to identify the MISR.
WARNING (TSV-186): [Severe] Multiple-Input Signature Register (MISR) memory element

objectName is fed by a MISR memory element from a different MISR.
EXPLANATION:
Intent:
according to the polynomial specified on the Pseudo Random Pattern Generator (PRPG)
or MISR attribute.
For this to occur a MISR memory element may accept data only from other memory
elements of the same MISR.
USER RESPONSE:
applied.
Trace back on the data input(s) to the memory element to identify the MISR
memory elements which feed the specified latch.
To correct the deviation, modify the logic such that only one memory element of
the same MISR feeds the data input of the specified memory element.

INFO (TSV-187): Last latch of Multiple-Input Signature Register (MISR) objectName

feeds multiple memory elements.
EXPLANATION:
verify_test_structures determines which memory elements comprise the MISR
through a logic trace from the MISR net identified in the logic source or test mode
definition.
Intent:
elements.
USER RESPONSE:
applied.
Trace forward from the memory element to identify the memory element(s)
which are not the first memory element of the MISR.
To correct the deviation, modify the logic such that the specified memory
element feeds only the first memory element of the same MISR.
WARNING (TSV-189): Unable to identify Multiple-Input Signature Register (MISR). MISR

attribute objectName.
EXPLANATION:
Intent:
elements. The use of on-board signature analysis is specified by on-board scan output
and the identification of a MISR through the source logic description or the mode
definition file.
through a logic trace from the MISR net identified in the logic source or mode definition.
USER RESPONSE:

Trace back on the net to identify the memory elements which should comprise
the LFSR.
To correct the deviation, modify the logic such that a properly constructed LFSR
exists.
For help in identifying the cause of the problem, look for accompanying messages
"TSV-220", "TSV-221", "TSV-223", or "TSV-225".
If none of these messages appear, then look for a sneak path from the MISR into
some other (non-MISR) memory elements or check for some data path within the
MISR (either a forward or a feedback path) that is blocked by Test Inhibit (TI) or scan
enable (SE) signals.
WARNING (TSV-193): [severity] In the Test Constraint state three state netName is
sourced by sourceName1 and sourceName2 which may simultaneously drive opposite
values resulting in 3-state contention.
EXPLANATION:
This message has a variable severity: W if stored pattern test, S if LBIST or WRPT.
Guideline TBS.1 states that the application of random test vectors to a product must not
expose it to damage due to the possibility of conflicting values at a three-state net.
Intent:
If this guideline is not followed, a test may be generated that causes a three-state
contention. This may result in damage to the product or invalid signatures or both. Three-
state contention can also result in excess power consumption as well as possible
contentions.
USER RESPONSE:

listed in the message are displayed. The design is set to the Test Constraint
state with simulation values applied which drive the net to opposite values.
WARNING (TSV-194): [severity] Mutual Exclusive Gating (MEG) checking aborted

with the specified EFFORT level while processing this message: During the Test Constraint
state three state netName is sourced by sourceName1 and sourceName2 which may
simultaneously drive opposite values resulting in 3-state contention.
EXPLANATION:
This message has a variable severity: W if stored pattern test, S if LBIST or WRPT.
verify_test_structures looks for mutually exclusive gating to render this condition
inoperative, but this message indicates verify_test_structures stopped checking
for gating that would prevent the error before reaching a resolution.
Guideline TBS.1 section 1 states that the application of test data to product, must not
damage the product due to multiple inputs to a net being simultaneously driven to
opposite values.
Intent:
If this guideline is not followed, a test may be generated that causes a three-state
contention. This may result in damage to the product or invalid signatures or both. Three-
state contention can also result in excess power consumption as well as possible
USER RESPONSE:
listed in the message are displayed. The design is set to the Test Constraint
state.

reruntests=yes to the command line. Increasing the effort level may
cause the test to run longer, and the test may still abort on this violation.

WARNING (TSV-201): [Severe] MRE, MRD, MRST, or MO pins are defined, but this mode
is not using the Scan to MISR methodology.
EXPLANATION:
Encounter Test supports MRE, MRD, MRST, and MO pins only for Scan to MISR modes.
The current mode did not have "out=to_misr" specified on the SCAN statement of the
mode definition file, so it is assumed to not be a Scan to MISR mode. This will cause
Encounter Test to ignore the use of these specific test function pin types.
Intent:
MISR Enable (MRE), MISR Read (MRD), MISR Reset (MRST), and MISR Observe) MO
pins are not allowed in modes which are not used for the scan to MISR methodology
USER RESPONSE:
Select the specific message from the Specific Message List. The product is
displayed as a large block with its input and output pins identified. The MRE,
MRD, MRST, and MO pins are identified by a unique color. The default is red.
To analyze the message:, use the mouse pointer to verify the highlighted pins.
The Information Window will show the test function pin attributes which
verify_test_structures used to identify the pin as MEs, MRDs,
MRSTs, and/or MOs.

- If the methodology is not Scan to MISR, remove the pin attributes (ME, MRD,
MRST, and MO).
- If the methodology is Scan to MISR correct the scan statement of the mode
definition file to include out=to_misr
WARNING (TSV-202): [Severe] PRPG objectName was specified in Scan to MISR

mode.
EXPLANATION:
verify_test_structures detected a PRPG output net identified in either the source
logic description or the mode definition file.
Intent:
Modes utilizing the Scan To MISR methodology do not support the use of PRPGs.
USER RESPONSE:
The net specified in the message is displayed with the Test Inhibit state applied.
Use the mouse pointer to verify the highlighted net.
To correct the deviation, remove the PRPG attribute from the indicated net.
WARNING (TSV-203): [Severe] No MISR cells were identified.

EXPLANATION:
The methodology identified for the mode was Scan To MISR and Encounter Test was
unable to identify a MISR. The lack of an on-board MISR prevents Encounter Test from
achieving the efficiency improvements associated with the Scan to MISR methodology.
Intent:
Mode build was unable to identify a MISR.
USER RESPONSE:
Properly specify a MISR (if the Scan to MISR methodology is intended) or remove the
out=to_misr designation from the SCAN statement of the mode definition file.
WARNING (TSV-204): [Severe] MISR cell objectName does not feed MO flagged PO.

EXPLANATION:
For the Scan to MISR methodology channel latch values can be observed only by a
Measure MISR Data event. Since this event will measure only MISR Observe (MO) pins
the identified MISR cell (and the channel which feeds it) will not be directly measurable.
Intent:
Every fault propagated to a channel latch should be observable through a MISR cell at
an MO primary output. Without the MISR Observe pins correctly identified, it will not be
possible to obtain correct fault detection information.
USER RESPONSE:
The MISR latch specified in the message is displayed with the MISR Observe
state applied.
Use the mouse pointer to verify the latch.
To correct the deviation, modify the part such that the identified MISR cell feeds
an MO primary output.
WARNING (TSV-205): [Severe] PRPG(MIPG) cell objectName of PRPG(MIPG)

objectName is not fed by the XOR of the PRPG(MIPG) cells (as indicated by the
polynomial) and a single scan in (if present).
EXPLANATION:
LFSR present on the part must be correctly represented by the specified polynomial.
This allows the Encounter Test test generation and simulation applications to predict the
contents of the LFSR via calculation, as opposed to simulation, thus reducing the time
needed to produce and evaluate the test vectors. See Guideline TBB.1 - Pseudo
Random Pattern Generator (PRPG) and Guideline TBB.2 - Multiple-Input Signature
Register (MISR) in the "Design Concepts and Applications" for more information.
Intent
This check is intended to ensure that the LFSR implementation matches the polynomial
which was specified for that LFSR. If the LFSR implementation and polynomial
specification do not match, miscompares may occur at the tester.
USER RESPONSE:

Select the specific message from the Specific Message List. The display will consist
of the following:
The failing latch of the LFSR cell, with the latch at which the simulation does not
match the polynomial.
The latches of the PRPG(MIPG) which make up any cell indicated by the
polynomial to feed the failing cell.
The scan in (if present) which feeds the failing cell.
The failing latch will be highlighted (default color red) and the circuit state
displayed will have the PRPG(MIPG) latches and scan in at the values which
did not produce a simulated value matching the calculated value. To eliminate
the condition do one of the following:
-- Modify the polynomial to properly reflect the hardware implementation of the
LFSR.
-- Modify the logic such that the LFSR implementation matches the polynomial
specified.
WARNING (TSV-206): [Severe] MISR cell objectName of MISR objectName is not fed
by the XOR of the MISR cells (as indicated by the polynomial) and a single channel (if
present).
EXPLANATION:
LFSR present on the design must be correctly represented by the specified polynomial.
needed to produce and evaluate the test vectors.
Intent:
USER RESPONSE:
Select the specific message from the "Specific Message List". The display will
consist of the following:
The failing latch of the LFSR cell, with the latch at which the simulation does not
match the polynomial.

The latches of the MISR which make up any cell indicated by the polynomial to
feed the failing cell.
The end of the channel (if present) which feeds the failing cell.
The failing latch will be highlighted (default color red) and the design state displayed
will have the MISR latches and end of channel at the values which did not produce
a simulated value matching the calculated value.
- Modify the polynomial to properly reflect the hardware implementation of the
LFSR.
- Modify the logic such that the LFSR implementation matches the polynomial
specified.
WARNING (TSV-207): LFSR validation threshold exceeded. verify_test_structures

will simulate 65536 patterns.
EXPLANATION:
Encounter Test verifies the presence of an XOR network (as indicated by the polynomial)
via simulation of the contributing LFSR latches to the cell under test.
Intent:
To insure reasonable performance a limit of 65536 patterns will be simulated. This limit
is sufficient to exhaustively simulate a sixteen term multiplier type LFSR. This message
is printed if there are more than 16 inputs feeding a specific LFSR bit.
verify_test_structures uses simulation to verify that the polynomial represents
the implementation of the LFSR (e.g. a PRPG or MISR). If a given LFSR bit has "n" inputs
then 2**n simulations are done to validate that the LFSR bit value is the XOR of the n
inputs.
Since an LFSR bit can have an arbitrary number of inputs a reasonable limit is set on
how many simulations are performed to verify the XOR natureof the n inputs feeding the
LFSR bit. This limit is set to 65,536 (2**16) which means that LFSR bits with 16 or fewer
inputs will be exhaustively tested to see of its value is the XOR of its inputs.
If an LFSR has more than 16 inputs (requiring more that 65,536 simulations
toexhaustively verify its XOR behavior) the simulation is stopped at this limit and this
message is printed indicating that the LFSR was not exhaustively simulated to verify that
it functioned as an XOR. Exhaustive simulation of more than 16 inputs would require a
large runtime so the tool performs a reasonable check of the LFSR bit using this limit.

As a matter of practicality, if an LFSR bit has behaved like an XOR for the first 65,536
input patterns then it likely is an XOR function. If any pattern tried does not behave as
the XOR of its inputs, a severe TSV-290 message is printed indicating this and the
verification of that bit position ceases.
In short, receiving a TSV-207 notifies that the specific LFSR bit was not exhaustively
simulated to guarantee it functions as the XOR of its inputs. It does not indicate the LFSR
design is bad.
USER RESPONSE:
WARNING (TSV-208): [Severe] PRPG(MIPG) latch objectName is not reset to a known

state by the MIPG Reset Sequence.
EXPLANATION:
Sequential Decompression requires all PRPG(MIPG) latches to be set to a known state
via the application of the MIPG Reset Sequence.
Intent
To provide a known, repeatable starting state for the PRPG(MIPG) latches so that the
stimulus for each test will be independent from the preceding test.
USER RESPONSE:
The PRPG(MIPG) latch specified in the message is displayed with the MIPG Reset
state applied.
Correct the MISR Reset Sequence or logic such that the MIPG Reset sequence sets
all PRPG(MIPG) latches to a known value.
WARNING (TSV-209): [Severe] MISR latch objectName is not reset to a known state by
the MISR Reset Sequence.
EXPLANATION:
The Scan to MISR methodology requires all MISR latches to be set to a known state via
the application of the MISR Reset Sequence.

Intent:
To provide a known, repeatable starting state for the MISR latches so that the signature
for each test will be independent from the preceding test.
USER RESPONSE:
The MISR latch specified in the message is displayed with the Stability state
applied.
To correct the deviation modify MISR Reset Sequence to set all MISR latches
to a known value.
INFO (TSV-210): Pseudo-Random Pattern Generator (PRPG) was found. The first latch of
the PRPG is objectName the last latch of the PRPG is objectName.
EXPLANATION:
Intent:
To identify the first and last latches of a Linear Feedback Shift Register (LFSR) which
operates as a PRPG.
USER RESPONSE:
INFO (TSV-211): Multiple-Input Signature Register (MISR) was found. The first memory
element of the MISR is objectName the last memory element is objectName.
EXPLANATION:
Intent:
To identify the first and last latches of a Linear Feedback Shift Register (LFSR) which
operates as a MISR.
USER RESPONSE:

WARNING (TSV-212): [Severe] Multiple-Input Signature Register (MISR) input to memory

element objectName has multiple sources.
EXPLANATION:
Each MISR data input must be fed from a single scan chain output.
Intent:
This message indicates that during scanning the MISR input is monitoring multiple
memory elements and primary inputs. This is not supported due to the extra expense
that would be involved in signature calculation. Also, unless the function of the multiple
source is an XOR, there would be information loss, resulting in inaccurate test coverage
reporting.
USER RESPONSE:
applied.
Trace back from the data input to find the stray path(s).
indicated in the message monitors the output of a single channel or Scan In (SI)
primary input or the XOR of PRPG outputs.

objectName is fed by multiple Pseudo-Random Pattern Generator (PRPG) memory
elements but a single XOR output node could not be found.
EXPLANATION:
be a single scan data primary input, or a function of the PRPG memory elements. Under
this guideline, the channel input must be either a single scan data primary input, a single
PRPG memory element, the XOR function of several PRPG memory elements, or an
arbitrary function of PRPG memory elements and primary inputs.
Intent:

The only allowable configuration in which multiple memory elements may feed to a MISR
input during scan is an XORing of PRPG outputs feeding a null channel. The identified
MISR memory element is fed by multiple PRPG latches but the XOR function of these
memory elements could not be identified.
USER RESPONSE:
applied.
Trace back from the data input to identify the PRPG memory elements which
feed the indicated MISR memory element.
indicated in the message is feed by the output of a single channel or Scan In
(SI) primary input or the XOR of the PRPG outputs.
INFO (TSV-214): A non-Scan In (SI) PI objectName feeds into Multiple-Input Signature

Register (MISR) memory element data input memoryElementName.
EXPLANATION:
be a single scan data primary input, or a function of the PRPG memory elements . Under
this guideline, the channel input must be either a single scan data primary input, a single
PRPG memory element, the XOR function of several PRPG memory elements, or an
arbitrary function of PRPG memory elements and primary inputs.
Intent:
Encounter Test allows only internal channels or channels identified by a SI flag to feed
to MISR inputs during scan.
USER RESPONSE:
If all memory elements are included in channels and the channels are connected
properly to MISR inputs, probably this is an extra MISR input that can either be gated off
during scan, connected to a Pseudo Random Pattern Generator (PRPG) memory
element, or an SI pin. Otherwise, there may be a wrong connection whereby the PI is
feeding the MISR instead of some channel memory element.

WARNING (TSV-216): Pseudo-Random Pattern Generator (PRPG) memory element

objectName is not initialized by the test mode initialization sequence.
EXPLANATION:
Not applicable. This message does not imply that the design deviates from any of the
design guidelines for testability.
Intent:
The PRPG and MISR memory elements must be initialized at the beginning of the LBIST
test sequence. One way to accomplish the initialization is by way of the test mode
initialization sequence. Since this is not done, you must specify seed values for the
PRPG latches when you run the LBIST Pattern Generation application.
USER RESPONSE:
applied.
To correct the deviation, update the initialization sequence so the memory
element specified in the message is initialized to a value (zero or one).
WARNING (TSV-217): Multiple-Input Signature Register (MISR) memory element

objectName is not initialized by the test mode initialization sequence.
EXPLANATION:
Not applicable. This message does not imply that the design deviates from any of the
design guidelines for testability.
Intent:
The PRPG and MISR memory elements must be initialized at the beginning of the LBIST
test sequence. One way to accomplish the initialization is by way of the test mode
initialization sequence. Since this is not done, you must specify seed values for the MISR
memory element when you run the LBIST Pattern Generation application.
USER RESPONSE:
applied.

To correct the deviation, update the initialization sequence so the memory

element specified in the message is initialized to a value (zero or one).
WARNING (TSV-218): [Severe] Pseudo-Random Pattern Generator (PRPG) memory

element objectName clock(s) is not at value (0 or 1) in the Test Constraint and Clocks off
state.
EXPLANATION:
Not applicable.
Intent:
All PRPG memory elements must hold their value when the design is in the Test
Constraint and Clocks off state. Otherwise there is risk of disrupting the pseudo-
randomness of the sequence that will be generated, resulting in low test coverage.
USER RESPONSE:
The memory element specified in the message is displayed. The design is set
to the Test Constraint and Clocks off state.
Trace back on the clock inputs which are not at value (are at X) to determine
why no clock was controlling the memory element clock input to value in the
Test Constraint and Clocks off state.
- Modify the logic so that the memory element clock input is controlled to a value
in the Test Constraint and Clocks off state.
- Modify the pin flags so that the specified values of the clock primary input pins
control the clock input of the memory element to a value.

objectName clock(s) is not at value (0 or 1) in the Test Constraint and Clocks off state.
EXPLANATION:
Not applicable.
Intent:

All MISR memory elements must hold their value when the design is in the Test
Constraint and Clocks off state. Otherwise there is risk of contaminating the signature,
which would cause the test coverage to be lower than reported by Encounter Test
USER RESPONSE:
The memory element specified in the message is displayed. The design is set
to the Test Constraint and Clocks off state.
Trace back on the clock inputs which are not at value (are at X) to determine
why no clock was controlling the memory element clock input to value in the
Test Constraint and Clocks off state.
- Modify the logic so that the memory element clock input is controlled to a value
in the Test Constraint and Clocks off state.
- Modify the pin flags so that the specified values of the clock primary input pins
control the clock input of the memory element to a value.
WARNING (TSV-220): [Severe] Last memory element of Linear Feedback Shift Register
(LFSR) could not be found from the identified objectName.
EXPLANATION:
Intent:
Encounter Test recognizes a Pseudo Random Pattern Generator (PRPG) or Multiple
Input Signature Register (MISR) by its constituent memory elements. The indicated net
is supposed to identify the LFSRs output net. If there is any fan-in between the memory
element and the indicated output net, Encounter Test will fail to find any of the constituent
latches.
USER RESPONSE:
Trace back on the inputs to the net to identify the memory element which should
have fed to the net.
To correct the deviation, modify the logic such that the last latch of the LFSR is
the only memory element which feeds the net.

WARNING (TSV-221): [Severe] Linear Feedback Shift Register (LFSR) memory element
objectName does not have any clock inputs on (1) in the unload simulation states.
EXPLANATION:
Intent:
Encounter Test requires that an identified LFSR operate according to the polynomial
specified on the Pseudo Random Pattern Generator (PRPG) or Multiple Input Signature
Register (MISR) attribute. For this to occur, an LFSR memory element must accept data
from other LFSR memory elements. If no clock input ever achieves the on (one) state,
this is impossible.
USER RESPONSE:
applied.
Trace back on the clock input(s) to the memory element to identify why the scan
clock is not controlling the input.
To correct the deviation, modify the logic such that the application of the scan
clock causes the clock input of the memory element to be on.
WARNING (TSV-222): [Severe] Pseudo-Random Pattern Generator (PRPG) latch

objectName is fed by more than 1 candidate for the preceding memory element of the
PRPG.
EXPLANATION:
Intent:
according to the polynomial specified on the PRPG or Multiple Input Shift Register
(MISR) attribute. For this to occur, a PRPG memory element must accept data only from
other PRPG latches. There is no valid configuration in which a PRPG memory element
could accept data from more than one memory element that has not already been
identified as part of this PRPG when working backwards from the last memory element
of the PRPG.
USER RESPONSE:
applied.

Trace back on the data input(s) to the latch to identify the potential candidates
for preceding memory elements of the PRPG.
To correct the deviation, modify the logic such that only one of the memory
elements of the PRPG feeds the data input of the specified memory element.
INFO (TSV-223): Multiple-Input Signature Register (MISR) memory element objectName

feeds more than 1 candidate for the next memory element of the MISR.
EXPLANATION:
through a logic trace from the MISR net identified in the logic source or mode definition.
Intent:
elements.
USER RESPONSE:
applied.
Trace forward from the specified memory element to identify the other (non-
MISR) memory element(s) or some MISR memory element other than the next
succeeding memory element in the LFSR. If any such path exists and it is not
a logic error, then there must be a test inhibit (TI) signal or fixed-value latch
signal that blocks the path when operating in the test mode.
To correct the deviation, modify the logic such that the specified MISR memory
element feeds the data input of only the succeeding MISR memory element. If
you are still unable to find the problem, maybe the LFSR was identified
incorrectly. For a multiplier LFSR, the first memory element is the only one that
should come from more than one MISR memory element. The memory element
at the other end of the register, the "last memory element", is the one that is to
be used in the logic source or mode definition file to identify the MISR.

objectName is fed by a MISR memory element from a different MISR.
EXPLANATION:

Intent:
according to the polynomial specified on the Pseudo Random Pattern Generator (PRPG)
or MISR attribute. For this to occur a MISR memory element may accept data only from
other latches of the same MISR.
USER RESPONSE:
applied.
Trace back on the data input(s) to the latch to identify the MISR memory
elements which feed the specified latch.
To correct the deviation, modify the logic such that only one memory element of
the same MISR feeds the data input of the specified memory element.
INFO (TSV-225): Last latch of Multiple-Input Signature Register (MISR) objectName

feeds multiple memory elements.
EXPLANATION:
through a logic trace from the MISR net identified in the logic source or test mode
definition.
Intent:
elements.
USER RESPONSE:
applied.
Trace forward from the latch to identify the memory element(s) which are not
the first memory element of the MISR.

To correct the deviation, modify the logic such that the specified memory
element feeds only the first memory element of the same MISR.
WARNING (TSV-227): Unable to identify Pseudo-Random Pattern Generator (PRPG).

PRPG attribute objectName.
EXPLANATION:
Intent:
verify_test_structures was unable to trace out the complete PRPG. Built-in Self
Test using on-board scan inputs requires a PRPG to drive the scan chain scan inputs.
The latches that comprise a PRPG are identified by tracing backward from a PRPG
output net identified in either the source logic description or the mode definition file.
USER RESPONSE:
Trace back on the net to identify the latches which should comprise the LFSR.
exists.
For help in identifying the problem, look for message "TSV-220", or "TSV-222". If
neither of these messages was produced, then probably there is no feedback (or the
feedback is blocked) into the first cell of the Linear Feedback Shift Register (LFSR),
or the path through the LFSR is blocked.
WARNING (TSV-228): Unable to identify Multiple-Input Signature Register (MISR). MISR

attribute objectName.
EXPLANATION:
Intent:
verify_test_structures was unable to completely trace out the MISR latches. The
use of on-board signature analysis is specified by on-board scan output and the
verify_test_structures determines which latches comprise the MISR through a
logic trace from the MISR net identified in the logic source or mode definition.
USER RESPONSE:

Trace back on the net to identify the latches which should comprise the LFSR.
exists.
For help in identifying the cause of the problem, look for accompanying messages
"TSV-220", "TSV-221", "TSV-223", or "TSV-225". If none of these messages appear,
then look for a sneak path from the MISR into some other (non-MISR) latches or
check for some data path within the MISR (either a forward or a feedback path) that
is blocked by test inhibit (TI) or scan enable (SE) signals.
WARNING (TSV-229): Controllable scan chain starting at objectName is not fed by XOR
or XORN network.
EXPLANATION:
When the weight select primary inputs are set to their designated states, then the scan
chain input must be either the identity function (true or complement) of a single PRPG
cell or the XOR function (true complement) of two or more cells of the same PRPG.
Note: Designs with PRPG Spreader network pipelines will always receive this message
because they add a sequential behavior to the XOR computation. This message is
issued because the resulting spreader network values are not solely determined by the
state of the PRPG.
Intent:
The intent of this check is to make sure the scan chain input signal is equiprobable 1s
and 0s to assume maximum test coverage in the general case.
A single PRPG latch
Two or more PRPG latches when the intervening function is the XOR or XORN
of the inputs
USER RESPONSE:
Trace back from the data input(s) to the latch to identify the logic feeding the
latch.

To correct the deviation, modify the design so the internal controllable scan
chain is fed by one of the following when the design is in the scan state:
- A single PRPG latch
- Two or more PRPG latches when the intervening function is the XOR or XORN
of the inputs.
WARNING (TSV-231): [Severe] A system clock feeds LFSR memory element

objectName clock input objectName.
EXPLANATION:
Not applicable.
Intent:
To ensure the LFSR function is not corrupted by system clock signals. If the LFSR is a
PRPG, this may disrupt the pseudo-randomness of the sequence that will be generated,
resulting in low test coverage. If the LFSR is a MISR, there may be information loss
resulting in inaccurate test coverage reporting, depending upon the function of the MISR
memory elements when they are controlled by the system clock.
USER RESPONSE:
Select the specific message from the Specific Message List. The LFSR
memory element and the path to the clock primary input pin will be displayed.
To analyze the message, trace back from the clock input to see why the system
clock is reaching this memory element.
To correct the problem, modify the logic such that no system clock signal feeds
the memory element in error.
WARNING (TSV-232): [Severe] LFSR memory element objectName is fed by more than
1 type of scan clock.
EXPLANATION:
Intent:
Encounter Test supports Linear Feedback shift Registers (LFSR) in which the clocking
of the memory elements comprising a single LFSR is uniform. To be clocked uniformly,
a latch must be fed by only 1 type of scan clock (A, B or E). Mixing the two types of
clocking in one LFSR would impose additional restrictions upon how the scan clocks can
be pulsed in order to avoid disruption of the LFSR operation.

USER RESPONSE:
LFSR memory element to the clock inputs will be displayed. The design is set
to the Test Inhibit (TI) state.
To correct the deviation, modify the design so the LFSR memory element is only
fed by 1 type of scan clock (A, B or E) when the design is set to the Test Inhibit
state.
WARNING (TSV-233): [Severe] Illegal clock gating on LFSR memory element

objectName clock input objectName.
EXPLANATION:
Encounter Test supports Linear Feedback Shift Registers (LFSR) in which the clocking
of the memory elements comprising a single LFSR is uniform. To be clocked uniformly,
the signal used to clock the individual memory elements of a given clock type (A or B or
E) cannot be gated.
Intent:
This check is intended to ensure that the LFSR function is not corrupted by system clock
signals or by shifting only some of the memory elements of the LFSR.
USER RESPONSE:
The gated signal path to the memory element indicated in the message will be
identified by the default color of red.
- Modify the logic such that all memory elements of the same type are fed by
the same clock gating signal.
- Modify the logic such that the LFSR clocks are not gated.
WARNING (TSV-234): [Severe] LFSR contains memory elements clocked by E clocks and
A or B clocks. The first memory element of the LFSR is objectName the last memory
element of the LFSR is objectName.
EXPLANATION:
Intent:

Encounter Test requires that memory elements within the LFSR either comprise a single
group (E clocked memory elements) or two groups which are A clocked memory
elements and B clocked memory elements. That is, Encounter Test does not support a
mixture of edge-sensitive and level-sensitive memory elements in the same LFSR.
USER RESPONSE:
Select the specific message from the Specific Message List. The first memory element
of the LFSR will be displayed. The design is set to the Test Inhibit state.
To correct the problem, modify the logic such that the LFSR is clocked by a single group
(E clocked memory elements) or two groups which are A clocked memory elements and
B clocked memory elements.
WARNING (TSV-235): [Severe] LFSR memory element objectName corrupted when

switching to/from the parent test mode.
EXPLANATION:
None. This operation was not covered by the Design Guidelines.
Intent:
This check is to verify that the same test mode used to initialize the LFSRs can be used
to read out the signatures. It cannot be used if the LFSR does not hold its value when
switching back to that test mode.
USER RESPONSE:
LFSR latch to the inputs will be displayed.
The design state will be set to the Test Constrain and clocks off state except
those PIs that have a different stability state value between the parent and child
mode will be set to X.
To correct the deviation, modify the design so the LFSR memory element
cannot be corrupted by switching between the target test mode and the parent
test mode.
WARNING (TSV-237): [Severe] MISR memory element objectName, clock input

objectName, is not off when all scan clocks are at X, all MISR Enable (ME) pins are
opposite their respective stability state values, and all other scan state pins are at their scan
states.
EXPLANATION:

Not applicable.
Intent:
Encounter Test requires that if there are Multiple-Input Signature Register (MISR) enable
pins identified (+-ME), the MISR memory elements will be stable when all ME pins are
set opposite their specified values. The scan operation must act normally without
changing the values in the MISR memory elements.
USER RESPONSE:
Select the specific message from the Specific Message List. The MISR memory element
and the paths to the ME inputs will be displayed with the following design state applied:
All scan clocks are at X
All ME pins set opposite their specified values
All other scan pins set to their specified values
To correct the problem, modify the logic such that the MISR memory element clock will
be off when all scan clocks are at X, all (ME) pins are set opposite their specified values,
and all other scan pins are set to their specified values.
WARNING (TSV-238): [Severe] MISR Enable (ME) objectName feeds objectName

and may contaminate the scan operation.
EXPLANATION:
Not applicable.
Intent:
Encounter Test requires that the scan operation act normally upon the Pseudo-Random
Pattern Generator (PRPG) latches and channel latches when all Multiple Input Signature
Register (MISR) enable pins are held opposite their specified values or all are held at
their specified values. This will ensure that the MISR enable pins feed only to MISR latch
clock inputs.
USER RESPONSE:
the MISR Enable pin to the offending logic will be displayed with the design set
to the Test Inhibit (TI) state.

To correct the deviation, modify the design so the MISR Enable pin feeds only
to MISR latch clock inputs when the design is in the TI state.
WARNING (TSV-239): [Severe] Observable scan chain ending at objectName is not a

controllable scan chain.
EXPLANATION:
Guideline TBS.2 states that unknown signals must not propagate into a signature
register. An observable scan chain, by definition, can propagate into a signature register.
Therefore, during the scan operation, the logic signals that get scanned into it must be
known, so it must also be a controllable scan chain.
Intent:
This check is intended to ensure that the observable scan chain can be loaded with a
known repeatable state. This prevents the contamination of the signature collection
devices with unpredictable values.
USER RESPONSE:
Select the specific message from the Specific Message List. The latch block
which is at the head of the observable scan chain associated with the specified
unload node will be displayed.
- Modify the logic such that the observable scan chain is also a controllable scan
chain. That is, the most upstream latch of the observable scan chain is fed by
a valid source of random data (either a PRPG output or a scan in pin.
- Modify the logic such that the observable scan chain is blocked from feeding
the signature collection device.
WARNING (TSV-241): LFSR may be corrupted when the design is not in the scan state. The
first memory element of the LFSR is firstMemoryElementName the last memory
element of the LFSR is lastMemoryElementName.
EXPLANATION:
If an LFSR is corruptible, it means there is some design state which reconfigures it such
that it does not function as an LFSR.
Intent:
The PRPG is expected to produce a pseudo-random pattern sequence, and not repeat
the sequence. For the non-repetitiveness to occur, the PRPG size and polynomial must

be selected so that its period is longer than the expected number of patterns that will be
needed for testing the circuit, and the period must not be interrupted by any intermediate
reset ("corruption") after the design has been initialized for the test mode. The MISR is
expected to trap failing responses in such a way that the final signature reflects whether
any failures occurred. An intermediate reset would mask any failures that occurred prior
to the reset.
USER RESPONSE:
Put the design into the TIE/TI state.
Look at the value of any LFSR input that is at X in this state.
Find out which of these pins may cause the LFSR to be reset, and modify the
design to prevent the offending value from appearing on this pin when in this
test mode.
INFO (TSV-242): m of the n possible primary input gating states were checked for correct
operation of the LFSR whose first memory element is firstMemoryElementName and
last memory element is lastMemoryElementName. p is the number of primary inputs
that gate the latch data inputs of this LFSR.
EXPLANATION:
Each LFSR must behave as specified by its polynomial, and its behavior must not be
altered by the presence of memory element data gating. The data inputs to the memory
elements of this LFSR are gated by primary inputs. A complete check that this LFSR
operates in accordance with its polynomial would require that its operation be checked
in all 2**p primary input gating states. To prevent exorbitant run time the number of states
checked is limited by a user command line parameter, maxlfsrgatingstates. The
maxlfsrgatingstates specified is less than the number of primary input gating
states.
Intent:
USER RESPONSE:
If the number of states checked gives you a high level of confidence that the LFSR and
its gating are correctly implemented then no user action is required. If, on the other hand,
the number of states checked is judged to be inadequate then the
verify_test_structures LBIST checks should be rerun, with the Maximum number

of LFSR-gating primary input states to check for correct LFSR operation specified high
enough to ensure an adequate LFSR check.
WARNING (TSV-243): [Severe] Latch objectName corrupted when switching to and

from the parent test mode.
EXPLANATION:
Not applicable.
Intent:
This check is to verify that the same test mode (the "parent") used in the initialization for
this test mode can be used to scan out the latch values at the end of an LBIST test
sequence. As in stored pattern test, only the observable latches are considered eligible
for observation via scan. The parent mode cannot be used for this purpose if any
observable or fixed value latch does not hold its value when switching back to the parent
test mode.
USER RESPONSE:
corrupted latch to the inputs are displayed.
The design state will be set to the Test Constraint and Clocks off state except
those that have a different stability state value between the parent and child
mode will be set to X.
To correct the deviation, modify the design so the latch cannot be corrupted by
switching between the target test mode and the parent test mode.
WARNING (TSV-244): B_SHIFT_CLOCKed MISR memory element objectName, clock

input objectName, is not off when all scan clocks are at X, all MISR Enable (ME) pins are
opposite their respective stability values, and all other scan state pins are at their scan states.
EXPLANATION:
Not applicable.
Intent:
Encounter Test requires that if there are Multiple-Input Signature Register (MISR) enable
pins identified (+-ME), the MISR memory elements will be stable when all ME pins are
set opposite their specified values. The scan operation must act normally without
changing the values in the MISR memory elements.

USER RESPONSE:
Select the specific message from the Specific Message List. The MISR memory
element and the paths to the ME inputs will be displayed with the following
design state applied:
- All scan clocks are at X
- All ME pins set opposite their specified values
- All other scan pins set to their specified values
To correct the problem, modify the logic such that the MISR memory element
clock will be off when all scan clocks are at X, all (ME) pins are set opposite their
specified values, and all other scan pins are set to their specified values.
WARNING (TSV-245): [Severe] Memory Element objectName is a fixed value memory

element in both the child mode (the mode under test) and the parent mode, but has different
values in each mode.
EXPLANATION:
This check identifies conditions which preclude the conversion of child mode test
patterns into patterns in the parent test mode. If uncorrected this condition may cause
the converted patterns to simulate incorrectly.
USER RESPONSE:
Select the specific message from the "Specific Message List" form.
The memory element in error will be displayed.
WARNING (TSV-246): [Severe] Memory Element objectName is a fixed value memory

element in the child mode (the mode under test) and an observe only memory element in the
parent mode.
EXPLANATION:
patterns into patterns in the parent test mode.
If uncorrected this condition may cause the converted patterns to simulate incorrectly.
USER RESPONSE:

WARNING (TSV-247): [Severe] Latch objectName is a floating latch in the child mode
(the mode under test) and a fixed value latch in the parent mode.
EXPLANATION:
USER RESPONSE:
The latch in error will be displayed.
WARNING (TSV-248): [Severe] Latch objectName is a floating latch in both the child
mode (the mode under test) and the parent mode, but during scan the value of the latch is
corrupted to a different value in each mode (or not corrupted in one mode and corrupted in
the second mode).
EXPLANATION:
USER RESPONSE:
WARNING (TSV-249): [Severe] Memory Element objectName is a controllable and

measurable latch in the child mode (the mode under test) and a fixed value latch in the parent
mode.
EXPLANATION:
USER RESPONSE:


measurable latch in the child mode (the mode under test) and a floating latch in the parent
mode.
EXPLANATION:
USER RESPONSE:

measurable latch in the child mode (the mode under test) and an observe only memory
element in the parent mode.
EXPLANATION:
USER RESPONSE:
WARNING (TSV-252): [Severe] Memory Element objectName is a controllable latch in

the child mode (the mode under test) and a fixed value latch in the parent mode.
EXPLANATION:
USER RESPONSE:



the child mode (the mode under test) and a floating latch in the parent mode.
EXPLANATION:
USER RESPONSE:

the child mode (the mode under test) and a observable only memory element in the parent
mode.
EXPLANATION:
USER RESPONSE:
WARNING (TSV-255): [Severe] Memory Element objectName is an observable only

latch in the child mode (the mode under test) and a fixed value latch in the parent mode.
EXPLANATION:
USER RESPONSE:

WARNING (TSV-256): [Severe] Memory Element objectName is an observable only

memory element in the child mode (the mode under test) and a floating latch which is not
corrupted to x during scan in the parent mode.
EXPLANATION:
USER RESPONSE:
WARNING (TSV-257): [Severe] Fixed value latch objectName is not stable when
switching from the child to the parent mode.
EXPLANATION:
USER RESPONSE:
INFO (TSV-258): Mode compatibility checks were requested, but there is no parent mode.
Further processing of the mode compatibility checks will be skipped.
EXPLANATION:
Mode compatibility checks were requested, but a parent mode does not exist.
USER RESPONSE:
No response required. For related information, refer to Ensure Compatibility between
Parent and Child Modes in the Encounter Test: Guide 3: Test Structures.
WARNING (TSV-260): FAST_FORWARD will not be supported for the following reason: text.
EXPLANATION:

Intent:
If any Pseudo Random Pattern Generator (PRPG) has the FAST_FORWARD attribute
specified, Encounter Test requires the following conditions be met:
All PRPGs must have the FAST FORWARD attribute specified.
Scan-in PIs must not exist on the circuit.
A PRPG save sequence is required.
A PRPG restore sequence is required.
USER RESPONSE:
Correct the condition specified in the message text above.
Note: No graphical analysis is supported for this violation.
WARNING (TSV-261): No shadow memory elements found for the PRPG cell beginning
with memory element objectName.
EXPLANATION:
Intent:
Encounter Test support of LBIST Fast Forward requires that the state of the PRPG be
saved in PRPG save register memory elements, through the application of a PRPGSAVE
sequence and that the PRPG state be restored from PRPG save register memory
elements, through the application of a PRPGRESTORE sequence.
USER RESPONSE:
element in the failing cell of the PRPG will be displayed. The design is set to the
Test Inhibit state.
- Modify the design so PRPG save register latch(es) exists for the failing cell of
the PRPG when the PRPGSAVE and PRPGRESTORE sequences are applied.
- Modify the PRPG definition statement such that LBIST Fast Forward is not
requested.
WARNING (TSV-262): [Severe] PRPG memory element objectName not restored when
the PRPGSAVE and then the PRPGRESTORE sequences are applied.
EXPLANATION:

All Pseudo Random Pattern Generator (PRPG) memory elements must be restored to
their starting values when the PRPGSAVE and PRPGRESTORE sequences are applied.
Intent:
This check is intended to ensure that the specified PRPGSAVE and PRPGRESTORE
sequences allow the contents of the PRPG memory elements to be saved and then
restored.
USER RESPONSE:
element block specified in the message will be displayed.
- Modify the logic such that the PRPG memory element value is successfully
captured by the associated PRPG save register memory element by the
PRPGSAVE sequence and then is restored by the application of the
PRPGRESTORE sequence.
- Modify the PRPGSAVE sequence and/or PRPGRESTORE sequence such
that the PRPG memory element value is successfully captured by the
associated PRPG save register latch.
- Modify the PRPG definition statement such that LBIST Fast Forward is not
requested.
WARNING (TSV-263): PO objectName is contaminated when the

PRPGSAVE|PRPGRESTORE sequences are applied.
EXPLANATION:
Intent:
Encounter Test requires that the PRPGSAVE sequence, which moves the PRPG latch
values into the PRPG save register and the PRPGRESTORE sequence, which moves
the latch values from the PRPG save register into the PRPG latches do not contaminate
other latches or POs.
USER RESPONSE:
Select the specific message from the Specific Message List. The PO will be
displayed. The design is set to the Test Inhibit state.
To correct the problem, modify the logic such that the PO is not contaminated
when the PRPGSAVE or PRPGRESTORE sequence is applied.

WARNING (TSV-264): Memory Element/RAM/ROM objectName is contaminated when

the PRPGSAVE|PRPGRESTORE sequences are applied.
EXPLANATION:
Intent:
Encounter Test requires that the PRPGSAVE sequence, which moves the PRPG
memory element values into the PRPG save register, and the PRPGRESTORE
sequence, which moves the values from the PRPG save register into the Pseudo-
Random Pattern Generator (PRPG) memory elements, do not contaminate other
memory elements, RAMs, ROMs or POs.
USER RESPONSE:
Select the specific message from the Specific Message List. The block specified in the
message will be displayed. The design is set to the Test Inhibit state.
To correct the problem modify the logic such that the block specified in the message is
not contaminated when the PRPGSAVE or PRPGRESTORE sequence is applied.
WARNING (TSV-265): PI objectName is not at its stability value after application of the
PRPGSAVE|PRPGRESTORE sequence.
EXPLANATION:
All clock primary inputs and all test inhibit primary inputs must be at their specified value
after the application of either the PRPGSAVE or PRPGRESTORE sequences.
Intent:
This check is intended to ensure that the application of the PRPGSAVE and
PRPGRESTORE sequences will not corrupt the contents of the channels or the on
product Multiple Input Signature Registers (MISR) (if present).
USER RESPONSE:
Select the specific message from the Specific Message List. The primary input
pin specified in the message will be displayed.
To eliminate the condition, modify the offending sequence such that the
specified pin is returned to the appropriate value at the end of the application of
the sequence.
WARNING (TSV-266): [Severe] The PRPG state influences the save operation, so the
PRPG save register cannot be clearly identified. The first memory element of the PRPG is

firstMemoryElementName the last memory element of the PRPG is

lastMemoryElementNameName.
EXPLANATION:
It is supposed to be able to hold a copy of the PRPG state, regardless of which state the
PRPG is in. If the identification of the save register depends upon the PRPG state, then
either the save operation does not work at all, or it is too complicated for Encounter Test
to figure out.
Intent:
verify_test_structures must first identify the save register before it can verify that
it is properly interconnected with the PRPG.
USER RESPONSE:
Place the design in the TIE/TI state.
Look at the save register input pins (you must first identify the save register
boundary; this is easy if the register is represented as an entity in the
hierarchical model) and sort out the control pins from the data inputs from the
PRPG.
Look for a path from the PRPG into one of the save register "control" inputs,
then modify the logic to deactivate the influence of the PRPG on this save
register input.
WARNING (TSV-267): [Severe] PRPG save register memory element objectName does
not hold its value in the Test Inhibit state.
EXPLANATION:
Intent:
The purpose of the save register is to hold the PRPG state during the application of a
scan and test cycle. If this register is not stable with the Test Inhibit state applied, then it
cannot be expected to perform its function.
USER RESPONSE:
Clock gating must be used to cause the PRPG save register to hold its state.
Place the design in the Test Inhibit (TI) state and simulate all PV pins opposite
their designated values.

Look at each clock input pin on each memory element in the save register. Each
of these pins should be 0 (off state for the memory element clock).
Modify the logic so that the TI input state holds off all save register clocks.
WARNING (TSV-268): [Severe] A PRPG save and restore cycle results in the incorrect
state in the PRPG. The first memory element of the PRPG is
firstMemoryElementName the last memory element of the PRPG is
lastMemoryElementName.
EXPLANATION:
Intent:
The intent of this check is to ensure that after the PRPG has been saved and
subsequently restored from the save register, that the state is correct. The restored state
should match exactly the PRPG state at the end of the save operation; for "fast forward
sequences" operation (see Guideline TBB.5) this state is the same as the state at the
beginning of the save operation, while for "fast forward pins" operation it is one PRPG
shift cycle advanced from the state at the beginning of the save operation.
USER RESPONSE:
Verify that the restore operation does not modify the state as it is copied from the save
register into the PRPG.
If using fast forward sequences, verify that the state is not modified during the
save operation.
If using fast forward pins, verify that the PRPG and channels scan
simultaneously with the save operation; check to see which PRPG state is
being copied into the save register; it should be the PRPG state resulting from
the scan cycle, and not the PRPG state at the beginning of this scan cycle.
INFO (TSV-270): The design has number channel starts and number channel ends
identified. The number of valid channels is number.
EXPLANATION:
Intent:
Each channel (scan chain) must be fed by either a scan-in (SI) primary input pin or the
XOR function of one or more Pseudo Random Pattern Generator (PRPG) latches. The
output of the channel must feed a signature register, either an on-board Multiple Input
Signature Register (MISR) or a scan-out (SO) primary output pin. The channels are all
scanned in parallel. This message reports the number of valid channels that were
identified in the circuit.

USER RESPONSE:
If there were no severe errors reported and the numbers in this message all match, no
action is necessary. If the numbers in this message do not match, you should investigate
the reason. Otherwise, the number of valid channels found may offer a clue in resolving
other severe messages.
WARNING (TSV-271): [Severe] A channel start objectName does not feed to a Scan
Out (SO), a Multiple-Input Signature Register (MISR) input, or a channel.
EXPLANATION:
Intent:
Each channel (scan chain) must feed a signature register, either an on-board MISR or a
SO primary output pin. For purposes of signature calculation, Encounter Test supports
"null channels" -- a channel input feeding directly to a signature register with no
intervening scannable latches. This channel input does not feed any channel latches nor
a signature register, hence it is not a valid channel input.
USER RESPONSE:
Select the specific message from the Specific Message List. The channel start
pin will be displayed with the scan state applied.
Trace forward from the indicated channel input ("start") to see what it feeds.
Look for a blockage in a path from this pin to some signature register (MISR or
SO primary output).
To correct the problem, modify the logic such that the channel start pin feeds a
MISR.
WARNING (TSV-272): [Severe] A channel start objectName controls an L3

objectName.
EXPLANATION:
Not applicable.
Intent:
L3s, or P-clocked latches, are not considered to be scanned out, and the P clock is not
repeatedly pulsed during the scan operation; therefore, an L3 cannot be in a channel.
Encounter Test simulation of the L3 assumes it is fed from an associated L1 latch. The
situation being reported by this message is likely to cause incorrect simulation results.
USER RESPONSE:

display is updated to show the path from the SI flagged pin to the SO latch with
all scan control pins at value except P clocks are on.
To correct the deviation, use a different clock to control the latch or feed its data
from an L1.
WARNING (TSV-273): [Severe] An L1 objectName controls another L1 objectName.

EXPLANATION:
Intent:
points for test vectors. The method of achieving values in these latches is a scan
operation. To accurately predict the contents of a scan chain, each scan chain must
consist of alternating L1 and L2 latches (and for General Scan Design (GSD) circuits,
intervening flip-flops where desired) that are controlled by separate scan control clocks.
Alternating the L1 (A-SHIFT_CLOCKed latches) and L2 (B_SHIFT_CLOCKed latches)
assures a reliable race-free scan operation.
USER RESPONSE:
highlighted pin of the second L1 with all scan control pins at value except A
clocks are on.
- Install a path from the first L1 to an appropriate L2.
- Insert the second L1 into a valid scan chain. Install a path from an appropriate
L2 or channel start pin to the second L2.
WARNING (TSV-274): An L2 objectName controls an L3 objectName.

EXPLANATION:

By definition, an L3 stable LSSD latch is supposed to receive its data from an L1 latch
when its associated P scan clock is pulsed in the scan state of the circuit.
Intent:
The Scan P clock controls the L3 latch when the design is in the scan state. It must
receive its data from the associated L1 latch during scan.
Note: Encounter Test can handle this, however other test systems may not.
USER RESPONSE:
display is updated to show the path from the L2 to the L3 latches with all scan
control pins at value except P clocks are on.
To correct the deviation, remove the path from the B_SHIFT_CLOCKed latch
(L2) to the P-clocked latch (L3).
WARNING (TSV-276): [Severe] A channel start objectName controls an L2

objectName.
EXPLANATION:
Not applicable.
Intent:
latches is a scan operation. To accurately predict the contents of a scan chain each scan
chain must be fed by a product input pin which is identified as a Scan In (SI) or an internal
channel starting point. The scan chain must consist of alternating L1 and L2 latches that
are controlled by the appropriate scan control clock and the last L2 must control either a
product output pin which is identified as the Scan Out (SO) or a Multiple Input Signature
Register (MISR) latch.
USER RESPONSE:
display is updated to show the path from the channel start to the L2 with all scan
control pins at value except B clocks are on.

- Remove the path from the channel start to the L2.
- Install a path from the channel start to an appropriate L1.
- Install a path from an appropriate L1 to the L2.
WARNING (TSV-277): [Severe] An L2 objectName controls another L2 objectName.

EXPLANATION:
Intent:
points for test vectors. The method of achieving values in these latches is a scan
operation. To accurately predict the contents of a scan chain, each scan chain must
consist of alternating L1 and L2 latches (and for General Scan Design (GSD) circuits,
intervening flip-flops where desired) that are controlled by separate scan control clocks.
Alternating the L1 (A-SHIFT_CLOCKed latches) and L2 (B_SHIFT_CLOCKed latches)
assures a reliable race-free scan operation.
USER RESPONSE:
highlighted pin of the second L2 with all scan control pins at value except B
clocks are on.
- Install a path from the first L2 to an appropriate L1, Scan Out (SO) pin or
Multiple Input Signature Register (MISR) input.
- Install a path from an appropriate L2 to the second L2.
WARNING (TSV-279): [Severe] Latch objectName controls multiple pins of other latch
blocks or product Scan Outs (SOs).
EXPLANATION:

Not applicable.
Intent:
Each latch in a channel must be a function of only the preceding latch or channel input.
Conversely, each latch must feed only one succeeding latch or channel output during the
scan operation. If the channel splits into two parallel paths, the latches in the two paths
cannot be loaded with independent values. This will result in a potential loss of test
coverage.
USER RESPONSE:
specified latch to the pins it controls are displayed with all scan control pins at
value and all clocks off.
WARNING (TSV-280): [Severe] A channel start objectName controls multiple pins of

latches or product Scan Outs (SOs).
EXPLANATION:
Not applicable.
Intent:
The channel should not be split into two parallel paths because a serious loss of test
coverage could potentially result.
USER RESPONSE:
specified channel start to the pins it controls are displayed with all scan control
pins at value except the A clocks are on.

INFO (TSV-281): Channel has channel start objectName, with channel end
objectName. The length of the scan chain is number bit positions.
EXPLANATION:
Intent:
This message identifies the point within the design that is considered to be the channel
(scan chain) input. For Logic Built-In Self Test (LBIST), this is usually an internal pin, fed
from an on-design Pseudo-Random Pattern Generator (PRPG).
USER RESPONSE:
WARNING (TSV-283): Latch objectName is not included in a Self Test Structure.

EXPLANATION:
Intent:
All non-RAM storage elements (latches and flip-flops) should be scannable unless they
are part of a Pseudo Random Pattern Generator (PRPG), Multiple-Input Signature
Register (MISR) or are fixed-value. A latch that is not part of one of these structures is a
floating latch. Floating latches must not change state during scan; if they do, they are set
to X, and then they could corrupt the signatures.
USER RESPONSE:
except the appropriate scan clocks are on.
To analyze the message, use the mouse pointer to verify all the clock inputs to
the latch. Use Carries Clock to identify the scan port of the latch. This clock
input should be on. If the clock input is not on, trace back on the clock input to
find the source of the incorrect value. If the clock input is on, trace back on the
data input to the same port to determine why this latch is not in a valid scan
chain.
To correct the deviation, modify the design to insert this latch into a valid scan
chain.
WARNING (TSV-284): [Severe] Incomplete channel. Latch objectName does not control
a latch (Multiple-Input Signature Register (MISR) or channel) or product Scan Out (SO)
output pin.
EXPLANATION:

Intent:
All channels must be observed by an on-design MISR or a SO primary output (PO). Lack
of observability will result in a serious loss of test coverage.
USER RESPONSE:
except the appropriate scan clocks (those that would allow the specified latchs
value to be captured by the appropriate succeeding latch) are on.
To analyze the message, trace forward from the latch to identify the latch that
should receive the value of the specified latch during the scan operation.
- If a path to the data input of a latch exists, but the clock to that port is not on,
modify the logic to correct the latchs clocking problem.
- If a path to a latch exists, but the value at the data input of the latch is not
always the value of the specified latch (or its inverse), modify the logic so the
latch data input value reflects the value (or its inverse) of the specified latch.
- If a path to a latch does not exist, install a path to a latch of the appropriate
type.
WARNING (TSV-285): [Severe] Incomplete channel. Latch objectName is not controlled

by a latch or product Scan In (SI) pin.
EXPLANATION:
Intent:
All channels must be controllable by an on-design PRPG or by a SI primary input (PI).
Lack of controllability will result in a serious loss of test coverage.
USER RESPONSE:
except those appropriate scan clocks (those that would allow the specified latch
to capture the value from the appropriate preceding latch) are on. The paths
back from the specified latch to all possible candidate latches and product
inputs are also shown.
To analyze the message, trace backward from the latch to identify the latch or
product input that should feed its value to the specified latch during the scan
operation.


- If a path to a latch or product input exists, but the value at the data input of the
latch is not always the value of the specified latch (or its inverse), modify the
logic so the latch data input value reflects the value (or its inverse) of the
specified latch.
- If a path to a latch or product input does not exist, install such a path.
WARNING (TSV-286): [Severe] Channel end objectName is not used in any channel.
EXPLANATION:
Intent:
All Multiple Input Signature Register (MISR) inputs must be fed by either a channel
output, the XOR function of some Pseudo-Random Pattern Generator (PRPG) latches,
a scan-in (SI) primary input (PI), or a constant value. Any other source is not simulated
during the scan process, and therefore the calculation of the MISR signature would be
incorrect. Thus, the signature of a good design will not match the expected signature.
USER RESPONSE:
Analyze any TSV-084 messages first, they may be indicative that some scan
chains may be broken or the wrong pin may have been used for SO.
display is updated to show the design with all scan control pins at value except
B clocks are on.
To analyze the message, trace backward from the specified SO pin to locate the
L2 that should control this SO pin during the scan operation.
- If a path to an L2 exists, but the value at the SO pin is not always the value of
the L2 (or its inverse), sensitize the path by means of additional or changed
scan enable (SE) inputs.
- If a path to an L2 does not exist, either remove the SO flag from the product
input pin or install a path from an L2 to the SO pin.
WARNING (TSV-288): Odd Number of Inversions found in Scan Chain.

The start of the scan chain is objectName.
The end of the scan chain is objectName.
EXPLANATION:

Not applicable.
Intent:
A data input value from the scan data input (or channel input block) shifted through the
identified register will arrive inverted at the scan data output (or channel output block).
USER RESPONSE:
If this is a BIST test mode, make sure that the channel input and channel output blocks
are identified properly. If there really is an inversion in the scan chain, fix the design and
re-import the circuit. If the design is correct with the inversion in the scan chain, then
either disregard this message or rerun verify_test_structures with selecting the
scan chain inversion check.
WARNING (TSV-290): [Severe] LFSR simulation does not match the polynomial. Cell
cellNumber of PRPG|MISR lfsrRedId is not fed by the XOR of the LFSR cells as
indicated by the polynomial and a single channel (in the case of MISRs).
EXPLANATION:
LFSR present on the design must be correctly represented by the specified polynomial.
needed to produce and evaluate the test vectors.
Intent:
USER RESPONSE:
Select the specific message from the "Specific Message List". The display will
consist of the following:
- The failing latch of the LFSR cell, with the latch at which the simulation does
not match the polynomial.
- The latches of the LFSR which make up any cell indicated by the polynomial
to feed the failing cell.
- The end of the channel (if present) which feeds the failing cell.

The report_test_structures command can be used to display PRPG and

MISR information including the polynomial as well as the latches which make up
each LFSR cell bit position.
Specify report_test_structures -h for details on available reporting options
or refer to report_test_structures in the Encounter Test: Reference:
Commands.
The failing latch will be highlighted (default color red) and the design state displayed
will have the LFSR latches and end of channel at the values which did not produce
a simulated value matching the calculated value.
- Modify the polynomial to properly reflect the hardware implementation of the
LFSR.
- Modify the logic such that the LFSR implementation matches the polynomial
specified.
WARNING (TSV-291): [Severe] A system clock feeds MISR memory element

objectName clock input objectName in an On-Product MISR testmode.
EXPLANATION:
Not applicable
Intent:
To ensure the On-Product MISR function is not corrupted by system clock signals.There
may be information loss resulting in inaccurate test coverage reporting, depending upon
the function of the MISR memory elements when they are controlled by the system clock.
USER RESPONSE:
Select the specific message from the "Specific Message List". The MISR
memory elemen and the path to the clock primary input pin will be displayed.
To analyze the message, trace back from the clock input to see why the system
clock is reaching this memory element.
To correct the problem, modify the logic such that no system clock signal feeds
the memory element in error.
WARNING (TSV-292): [Severe] MISR memory element objectName is fed by more than
1 type of scan clock in an On-Product MISR testmode.

EXPLANATION:
Intent:
Encounter Test supports Multiple-Input Signature Registers (MISR) in which the clocking
of the memory elements comprising a single MISR is uniform. To be clocked uniformly,
a latch must be fed by only 1 type of scan clock (A, B or E). Mixing the two types of
clocking in one MISR would impose additional restrictions upon how the scan clocks can
be pulsed in order to avoid disruption of the MISR operation.
USER RESPONSE:
Select the specific message from the "Specific Message List". The paths from
the MISR memory element to the clock inputs will be displayed. The design is
set to the Test Inhibit (TI) state.
To correct the problem, modify the design so the MISR memory element is only
fed by one type of scan clock (A, B, or E) when the design is set to the Test
Inhibit state..
WARNING (TSV-293): [Severe] Illegal clock gating on MISR memory element

objectName clock input objectNameo in an On-Product MISR testmode.
EXPLANATION:
Encounter Test supports Multiple-Input Signature Registers (MISR) in which the clocking
of the memory elements comprising a single MISR is uniform. To be clocked uniformly,
the signal used to clock the individual memory elements of a given clock type (A or B or
E) cannot be gated.
Intent:
This check is intended to ensure that the MISR function is not corrupted by system clock
signals or by shifting only some of the memory elements of the MISR.
USER RESPONSE:
The gated signal path to the memory element indicated in the message will be
identified by the default color of red.
To eliminate the condition, do one of the following:
- Modify the logic such that all memory elements of the same type are fed by
the same clock gating signal.

- Modify the logic such that the MISR clocks are not gated.
WARNING (TSV-294): [Severe] MISR contains memory element clocked by E clocks and
A or B clocks in an On-Product MISR testmode.The first memory element of the MISR is
objectName the last memory element of the MISR is objectName.
EXPLANATION:
Intent:
Encounter Test requires that memory elements within the MISR either comprise a single
group (E clocked memory elements) or two groups which are A clocked memory
elements and B clocked memory elements. That is, Encounter Test does not support a
mixture of edge-sensitive and level-sensitive memory elements in the same MISR.
USER RESPONSE:
Select the specific message from the "Specific Message List". The first memory
element of the MISR will be displayed. The design is set to the Test Inhibit state..
To correct the problem, modify the logic such that the MISR is clocked by a
single group (E clocked memory elements) or two groups which are A clocked
memory elements and B clocked memory elements.
WARNING (TSV-295): MISR may be corrupted when the design is not in the scan state in
an On-Product MISR testmode.
The first memory element of the MISR is firstMemoryElementName. The last
memory element of the MISR is lastMemoryElementName.
EXPLANATION:
If a MISR is corruptible, it means there is some design state which reconfigures it such
that it does not function as an MISR.
Intent:
The MISR is expected to trap failing responses in such a way that the final signature
reflects whether any failures occurred. An intermediate reset would mask any failures
that occurred prior to the reset.
USER RESPONSE:
Place the design into the TIE/TI state.
View the value of any MISR input that is at X in this state.

Determine which of these pins may cause the MISR to be reset, and modify the
design to prevent the offending value from appearing on this pin when in this
test mode.
INFO (TSV-296): m of the n possible primary input gating states were checked for correct
operation of the MISR whose first memory element is firstMemoryElementName, and
last memory element is lastMemoryElementName. p is the number of primary inputs
that gate the memory element data inputs of this MISR. This is an On-Product MISR
testmode.
EXPLANATION:
Each MISR must behave as specified by its polynomial, and its behavior must not be
altered by the presence of memory element data gating. The data inputs to the memory
elements of this MISR are gated by primary inputs. A complete check that this MISR
operates in accordance with its polynomial would require that its operation be checked
in all 2**p primary input gating states. To prevent exorbitant run time the number of states
checked is limited by a user command line parameter, maxlfsrgatingstates. The
maxlfsrgatingstates specified is less than the number of primary input gating
states.
Intent:
This check is intended to ensure that the MISR implementation matches the polynomial
which was specified for that MISR. If the MISR implementation and polynomial
USER RESPONSE:
If the number of states checked gives you a high level of confidence that the MISR and
its gating are correctly implemented then no user action is required. If, on the other hand,
the number of states checked is judged to be inadequate then the
verify_test_structures Analyze flip-flop and latch scan characteristics check
should be rerun, with the Maximum number of MISR-gating primary input states to
check for correct MISR operation specified high enough to ensure an adequate MISR
check.

WARNING (TSV-305): The embedded pipeline register memoryElementName is clocked
by a scan sequence event which occurs after the clockof embedded pipeline register
memoryElementName. All embedded pipeline registers must be clocked in the same
event of the scan sequence.

EXPLANATION:
All lactches and/or flops of the embedded pipelines must be clocked in the same event
of the scan sequence.
Intent
Uniform clocking of embedded pipelines is required to accurately identify the stages of
the embedded pipelines.
USER RESPONSE:
Select the specific message from the Specific Message List. The embedded
pipeline registers identified in the message will be displayed. The design is set
to set to the Scan state.
registers.
To correct the deviation, modify the design or scan sequence such that the
clocks to the registers are pulsed in the same event of the scan sequence.
WARNING (TSV-306): The value in Scan_In pipeline register memoryElementName

changes value before it can be captured by internal scan chain register
memoryElementName, because the clock controlling the pipeline register occurs before
the clock controlling the internal scan chain register.
EXPLANATION:
The first register (latch or flop) of an internal scan chain must be fed by a Scan_In or a
Scan_In pipeline register (latch or flop) which does not update until after the internal
scan chain register captures the value in the Scan_In pipeline register during the scan
cycle.
Intent:
A cycle of the scan clocks must result in the first register of an internal scan chain
capturing the data which is loaded into the Scan_In pipeline register during the
preceding cycle of the scan clocks.
USER RESPONSE:
Select the specific message from the Specific Message List. The internal scan
chain register will be displayed with the path back to the Scan_In pipeline
register highlighted. The design is set to the Scan state.

registers.
clocks to the registers are controlled to update the internal scan chain register
before the Scan_In pipeline register updates within a given scan cycle.
If the identified latches or flops are clocked in the same event of the scan sequence, then
the most likely cause is a missing lock-up latch for the last bit of the Scan_In pipeline
register.
WARNING (TSV-307): The value in internal scan chain register memoryElementName

changes value before it can be captured by Scan_Out pipeline register
memoryElementName, because the clock controlling the internal scan chain register
occurs before the clock controlling the Scan_Out pipeline register.
EXPLANATION:
The first register (latch or flop) of a Scan_Out pipeline must capture the value of the
internal scan chain register(s) (latch or flop) before the internal scan chain register(s) is
clocked during the scan cycle.
Intent:
A cycle of the scan clocks must result in the first register of the Scan_Out pipeline
capturing the data which is loaded into the internal scan chain by either the capture
sequence or the preceding cycle of the scan clocks.
USER RESPONSE:
Select the specific message from the Specific Message List. The internal scan
chain register will be displayed with the path back to the Scan_Out pipeline
register highlighted. The design is set to the Scan state.
registers.
clocks to the registers are controlled to update the internal scan chain register
after the Scan_Out pipeline register updates within a given scan cycle.
If the identified latches or flops are clocked in the same event of the scan sequence, then
the most likely cause is a missing lock-up latch for the last bit of the internal scan chain
register.

WARNING (TSV-308): [Severe] The value in PRPG(MIPG) cell memoryElementName

changes value before it can be captured by internal scan chain register
memoryElementName, because the clock controlling the PRPG(MIPG) cell occurs before
the clock controlling the internal scan chain register.
EXPLANATION:
The first register (latch or flop) of an internal scan chain must be fed by a PRPG(MIPG)
cell which does not update until after the internal scan chain register captures the value.
Intent
A cycle of the scan clocks must result in the first register of an internal scan chain
capturing the data which is loaded into the PRPG(MIPG) cell during the preceding cycle
of the scan clocks.
USER RESPONSE:
Select the specific message from the Specific Message List. The internal scan chain
register will be displayed with the path back to the PRPG(MIPG) cell highlighted.
The design is set to the Scan state.
registers.
the registers are controlled to update the internal scan chain register before the
PRPG(MIPG) cell updates within a given scan cycle.
If the identified latches or flops are clocked in the same event of the scan sequence
then the most likely cause is an inversion in the clock path to the internal scan chain.
WARNING (TSV-310): [Severe] One or more clock inputs of memory element

memoryElement are at the unknown value X (neither logic zero nor logic one) when the
design is in the Test Constraint and Clocks off state.
EXPLANATION:
Guideline TG.3 states that clock primary inputs (PIs) must be identified such that when
all clock PIs are at their defined stable state, the clock inputs to all memory elements
must be forced to a known value. Known values include logic zero and logic one.

Intent:
This guideline ensures that the design will be free of memory elements which contain
unpredictable values when the design is at Test Constraint and Clocks off state.
Failure to meet this requirement will cause the Encounter Test test generation and
simulation applications to consider failing memory elements to be sources of
unpredictable values (X).
This may reduce test coverage.
USER RESPONSE:
element specified in the message will be displayed. The design is set to the Test
Inhibit and Clocks off state.
To analyze the message use the mouse pointer to trace back on those clock
inputs which are at X to determine why they are not controlled to a value when
the Test Inhibit and Clocks off state is applied.
To correct the deviation, modify the logic so the application of the designated
stability value to the clock PIs causes the clock inputs to the memory element
to be at value (one or zero). The most likely cause is the failure to identify the
appropriate clock pins.
information.
WARNING (TSV-311): [Severe] More than one clock input to memory element
memoryElementName is not off (at logic zero) during the scan operation.
EXPLANATION:
The application of the scan clocks must cause only one clock input to a memory element
to be at value other than zero.
Intent:
This guideline ensures that a memory element can be reliably loaded to a specified value
through the scan operation. If multiple ports to a memory element are active, the
simulation of the latch behavior is greatly complicated.
For more information, refer to "Guideline TG.7 - Clock Requirements" section 1 and GSD
Analyze Test Clocks Control of Memory Elements in the Encounter Test: Guide 3:
Test Structures.

USER RESPONSE:
element specified in the message will be displayed. The design will be
displayed with all the scan control pins at their value and all the scan clocks at
X and system clocks are off.
inputs to determine why the clock to more than one latch port was not off when
the scan clocks are applied in their specified order.
To correct the deviation, modify the logic so that the application of the scan
clocks cause only one port to be active.
information.
WARNING (TSV-312): One or more clock inputs of register registerName are at the
unknown value X (neither logic zero nor logic one) when the design is in the Test Constraint
and clocks off state and the scan corrupt values are applied.
EXPLANATION:
Guideline TG.3 states that clock primary inputs (PIs) must be identified such that when
all clock PIs are at their defined stable state the clock inputs to all memory elements must
be forced to a known value. Known values include logic zero and logic one.
Intent:
Failure to meet this requirement may preclude successful transition fault testing. This
may reduce test coverage.
For more information, refer to "Guideline TG.3 - Stable State" and GSD Analyze Test
Clocks Control of Memory Elements in the Encounter Test: Guide 3: Test
Structures.
USER RESPONSE:
Select the specific message from the Specific Message List. The register
specified in the message will be displayed. The design is set to the Test
Constraint and Clocks off state with the scan corrupt values applied.
inputs to determine why they are not controlled to a value when the Test
Constraint and Clocks off state with the scan corrupt values enforced is applied.

To correct the deviation, modify the logic so that the application of the Test
Constraint and Clocks off state with the scan corrupt values causes the clock
inputs to the register to be at value (one or zero). The most likely cause is the
failure to identify the appropricate clock pins.
INFO (TSV-314): A Flush Test cannot be generated for the register whose Scan In (SI) is
scanInPinName and Scan Out (SO) is scanOutPinName.
EXPLANATION:
A path must exist from the SI of the scan chain to its SO when the Scan A and B clocks
are held active (opposite of their stability value). Thus any value placed on the SI pin will
propagate to the SO, either inverted or in phase. This test is applied to GSD designs
when A and B scan clocks are present.
Intent:
The intent of this check is to identify to the designer and manufacturing which scan
chains will have an LSSD Flush Test generated.
USER RESPONSE:
This is strictly an informational message, and no analysis is necessary and so
none is performed. If you wish to identify why this message was produced,
perform the following analysis.
To analyze the condition:
- First, on the View Schematic window, select Tools, Reset design state, and
Flush Scan Chain to simulate all test function pins which control scanning to
their stable value. (Note this will simulate all clocks to their stable value, which
is defined as "off".) Make sure that the clock choppers are enabled (also listed
under Set design state pull-down).
- Display block 0 (View, Block, enter index 0) to show the inputs and outputs of
the product. Select the scan clocks using the mouse (default is left mouse
button), then simulate it to the opposite of its stability value (simulation of a pin
is on the pull-down menu for pins displayed when the right mouse button is held
down).
- Use View, Pin, and enter the SO pin name from the message to identify the
end of the scan chain. Trace back on signal values of logic X through the latches
of an array. Any latch along the scan chain which does not have exactly one
clock input active is the reason this scan chain was identified as invalid for an
LSSD Flush Test.

- If an LSSD Flush Test is desired, modify the design so every latch is correctly
controlled during the normal scan operation, AND that a single clock input is
active when all the scan clocks are on.
WARNING (TSV-315): Memory element memoryElementName is not in a scan chain and

is corruptible during the scan operation. The memory element may be clocked through
pinName during the scan sequence scanSectionName.
EXPLANATION:
Note: If there are multiple scan sections, then the scan section name appears in the
message text. If there is a single scan section, the scan section name is blank.
If this is not the design intent, correct and rerun. If this is the design intent, then it violates
design guidelines in that the non-scan memory element may be clocked during the scan
operation.
Guideline TG.8 point 7 states that clocks to RAMs should be held off and clocks to non-
scan latches and flip-flops should be held stable. The clocks to stable latches should be
held to constant zero and the clocks to flush latches should be held to constant one.
The occurrence of this message generally indicates one or the other of two possible
problems:
The identified memory element is a latch that is part of an intended scan chain,
but this scan chain was not properly identified. One possible cause is that an SI
test function attribute is missing from the scan-in primary input pin.
The identified latch may be part of a scan chain, but this latch is neither
controllable nor measurable, due to having one or more clock inputs that are not
at logic 0 in the Test Constraint and Clocks off state.
Intent:
The intent of this check is to ease test generation and improve its performance by not
requiring simulation of the scan sequence.
Refer to "Guideline TG.8 - Section Scan State", point 7, in the Encounter Test: Guide
3: Test Structures for more information.
USER RESPONSE:

default is red. The simulation state shown for the circuit is the scan state with
the logic values for the scan clocks at OFF/ON.
value.
Test Structures.
memory element is meant to be scannable, then trace the scan path to see if it
is broken and in need of repair. If the scan path is unbroken then make certain
that it is correct for your design that this latch have a clock input which is not at
logic 0 in the Test Constraint and Clocks off state.
information.
WARNING (TSV-316): [Severe] An address or data input of RAM ramName is at value

(either logic zero or logic one) when the circuit is in the Test Constraint and Clocks off state
and that value is controlled by a clock. This condition creates a clock/data race as the address
or data input to the RAM may change as the write clock of the RAM changes value. This
condition precludes further race checking for the RAM.
EXPLANATION:
free operation. This case is referred to as a "data gates clock" type of clock race since
the data of the upstream source memory element creates a potential clock race condition
with the downstream capture memory element. For edge-clocked test modes, Guideline
TG.4 states that a memory element should not be used to gate the same clock signal
that controls it except when value V at the clock source launches new data from the
memory element, that same value V must also dominate the gating signal to prevent any
potential glitches.


constraints option. Refer to the constraints description in the verify_test_structures
Intent:
data that is controlled by the same clock. For more information, refer to Guideline TB.3 -
Memory Elements, <l lid=dbh0tgD>Guideline TG.4 - Identification of Clock Pins and
Analyze Potential Clock Signal Races in the "Design Concepts and Applications".
USER RESPONSE:
Select the specific message from the specific Message List. The memory
element specified in the message will be displayed. The circuit is set to the Test
Constraint and Clocks off state.
To analyze the message use the mouse pointer to trace back on those address
or data inputs which are at value to determine why they are controlled to a value
when the Test Constraint and Clocks off state is applied.
To correct the deviation, modify the logic so the clocks do not feed the address
or data of the RAM.
WARNING (TSV-320): [Severe] A Mask All Channels state is defined but does not mask
all channels when applied. There are unmaskedChannelCount channels which are not
masked to known values in this state
EXPLANATION:
No rules or restrictions.
Intent:
If a Mask All Channel state is defined, verify that all channels are masked when this state
is applied. This is included as part of the channel masking checks.
USER RESPONSE:
WARNING (TSV-321): An Invalid CME state was found. The reason for the invalid state is:
reasontext.
EXPLANATION:

Intent:
If a Mask All Channel state is defined, verify that all channels are masked when this state
is applied. This is included as part of the channel masking checks.
USER RESPONSE:
WARNING (TSV-322): [Severe] Channel Masking Enable (CME) cmePinName feeds

objectName and may contaminate the scan operation.
EXPLANATION:
Intent:
Encounter Test requires that the scan operation act normally upon the channel memory
elements when all Multiple Input Signature Register (MISR) enable pins are held at their
specified stability values. This will ensure that the Channel Masking Enable pins feed
only to MISR memory element clock inputs.
USER RESPONSE:
the Channel Mask Enable pin to the offending logic will be displayed. The
design is set to the Scan state.
To correct the deviation, modify the design so the Channel Masking Enable pin
feeds only to MISR memory clock inputs when the design is in the Scan state.
INFO (TSV-323): Channel Masking Input (CMI) cmePinName does not feed into a Channel
Mask Scan Register.
EXPLANATION:
USER RESPONSE:
Select the specific message from the Specific Message List. The CMI pin is
displayed. The design is set to the Channel Mask Load state.

To correct the deviation, modify the design so the Channel Masking Input (CMI)
feeds a Channel Mask Scan Register if that was the intent.
WARNING (TSV-325): [Severe] Channel mask register memoryElementName is

enabled by multiple CME states. The redundant CME state is marked as invalid.
EXPLANATION:
Each Channel Mask Enable (CME) state must select either no channel mask register bits
or a unique channel mask register bit.
Intent:
The indicated channel mask register flop or latch was capable of masking a channel in
multiple CME states in violation of the restriction that it does so in at most one CME state.
The redundant state was marked as invalid and will not be used during further
processing.
USER RESPONSE:
the Channel Mask Enable pin(s) to the offending logic will be displayed. The
design is set to the Scan state.
To correct the deviation, modify the design so the Channel Masking Enable
states enable the channel mask register latch or flop in only one CME state.
WARNING (TSV-327): [Severe] MISR memory element memoryElementName has a

clock input that is not OFF during load Channel Mask Loading sequence. A total of count
MISR memory elements are corrupted. The Channel Mask Load sequence is unusable.
EXPLANATION:
Not applicable.
Intent:
This checks that MISR cells cannot be corrupted during the Channel Mask Load
sequence.
USER RESPONSE:
Select the specific message from the Specific Message List. The first corrupted
MISR memory element is displayed and the design set to the Channel Mask
Load state.

To correct the deviation, modify the design so the Channel Mask Load Clock is
not logically active at MISR memory clock inputs when the design is in the
Channel Mask Load state.
INFO (TSV-328): The length of the longest Channel Mask Scan Register is length1 bit
positions, which is percentage% of the average Channel Mask Scan Register length of
length2 (based on bits total Channel Mask Scan Register bits and
numChanMaskRegs Channel Mask Scan Registers). In addition, there are a total of
chanMaskLen Channel Mask Registers and each has a length of numBits bits.
EXPLANATION:
Test cost is directly affected by the time it takes to scan in/out each individual test. To help
minimize the time, it is important that the length of the scan chains be minimized. In
general, having more scan chains allows each chain to be shorter, thus reducing test
time; however, test time will be dictated by the length of the longest scan chain, so it is
important to try to keep the longest scan chain as close to the length of the average scan
chain as possible (i.e. the chains should be balanced).
Because the extra test time associated with non-balanced scan chains can be quite
costly, some chip manufacturers have published guidelines for their customers to help
keep test costs under control. and package. These guidelines establish simple numerical
targets for scan chain count and scan chain length balancing.
verify_test_structures issues this message to report the relevant statistics.
USER RESPONSE:
No response is required for Encounter Test to process the design correctly; however,
some chip manufacturers may complain or charge more for designs whose scan chains
are exceptionally unbalanced.
WARNING (TSV-329): An Invalid CME state was found. The reason for the invalid state is:
reasonText. The unload net is unloadNet.
EXPLANATION:
None
Intent:
The CME states are examined and any invalid states are reported. This is similar to
message TSV-321 except that an unload net is included in the message. The CME check
is included as part of the channel masking checks.
USER RESPONSE:

WARNING (TSV-330): [Severe] Channel Masking Enable (CME) signal name feeds scan-
out or scan-out pipeline name and may contaminate the scan operation.
EXPLANATION:
Channel Mask Enable signals are not allowed to affect scan-outs other than enabling the
channel masking.
Intent:
Encounter Test requires that the Channel Mask Enable pins do not affect scan-outs other
than enabling the channel masking. This ensures that the values observed at the scan-
outs are the function (XOR/XNOR) of the channels or the applied mask values for the
channels. verify_test_structures has determined that a path or paths exist from the CME
pin to the scan-out pin that is not part of the channel masking logic.
USER RESPONSE:
Select the specific message from the Specific Message List. The path(s) from the
Channel Mask Enable pin or Channel Mask Enable pipeline flop to the scan-out pin
or scan out pipeline flop will be displayed. The circuit is set to the scan state.
To correct the deviation, modify the design so the Channel Masking Enable pin or
pipeline flop does not feed to the scan-out or scan-out pipeline except through the
channel masking logic in the scan state.
WARNING (TSV-331): [Severe] An observable latch or flop name was corrupted by the
Channel Mask Load sequence. Since the value captured by this latch or flop may be
overwritten, this latch or flop is removed from the scan chain.
EXPLANATION:
The application of the Channel Mask Load sequence, which occurs prior to the scan
sequence, corrupts an observable element of the scan chain before it has had a chance
to be shifted out. This message states that during the Channel Mask Load sequence the
value which was captured in the latch or flop may be overwritten. Since the captured
value may be compromised the identified latch or flop is removed from the Encounter
Test observable scan chain. Since this reduces the number of available capture
elements reduced fault coverage, increased pattern count, and increased test time may
result.
USER RESPONSE:

In most cases, eliminating the corruption will require a change in the logic, the test
function pin definitions, or the Channel Mask Load sequence to allow the normal scan
latches to remain stable until the scan sequence is reached. TSV analysis displays the
corrupted latch or flop. The specific event can be identified by running
build_testmode with reportremovedscanelemnts=yes specified. A TTM-362
message will be issued identifying the odometer reading at which the corruption
occurred. The Sequence Analyzer can then be used to view the values which caused
the corruption.
WARNING (TSV-332): [Severe] A channel mask shift register element name was
corrupted by the scan sequence. This condition may prevent the masking of the observable
register masked by this channel mask shift register element.
EXPLANATION:
The application of the scan sequence corrupts the channel mask shift register element.
This message states that value which was loaded into the latch or flop of the Channel
Mask Shift Register may be overwritten. Since the value loaded by the Channel Mask
Load sequence may be compromised masking may not work properly.
USER RESPONSE:
TSV analysis displays the corrupted channel mask shift register element.The specific
event can be identified by the TTM-344 message issued during build_testmode
which includes the odometer reading at which the corruption occurred. The Sequence
Analyzer can then be used to view the values which caused the corruption. Change the
logic or sequences to eliminate the corrupt of the channel mask shift registers.
WARNING (TSV-334): [Severe] Leaked Channel Masking Enable (CME) signal from
name feeds channel output name and may corrupt the scan data.
EXPLANATION:
When channel masking is used, the scan chain outputs must be controlled by the CME
primary input pins when no pipelines exist for the CMEs or by the terminal stage of the
CME pipeline when those pins are pipelined. When pipelines are used for the CME pins
the primary input and the stages of the CME pipelines which precede the terminal stage
are not allowed to control the scan chain outputs. The application of the masking data
will not work properly when the CME signals from interim stages of the pipelines or
directly from the CME pins control the scan chain outputs.
USER RESPONSE:
Select the specific message from the Specific Message List. The path(s) from the
Channel Mask Enable pin or Channel Mask Enable pipeline flop to the channel output
will be displayed. The circuit is set to the scan state.

To correct the deviation, modify the design so that the specified Channel Masking Enable
pin or pipeline flop does not feed channel outputs in scan state.
WARNING (TSV-340): Controllable Register StimregNumber with the Load Point

loadNode comes from a Spreading Network with an invalid function.
EXPLANATION:
When a Spreading Network is placed between Scan In pins or PRPG flops, it must
evaluate to one of the following functions:
An XOR function of the Scan In pins or PRPG Flops
An XNOR function of the Scan In pins or PRPG Flops
A direct connection from the Scan In or PRPG flop
Inverted from the Scan In pin or PRPG flop
Any other function of the Scan In pins (or PRPG flops) is invalid since aliasing of stimulus
data may occur.
USER RESPONSE:
Select the specific message from the Specific Message List. The Controllable
Load point is displayed in the Scan State and is traced back to the Scan In (or
PRPG flops) that drive the Spreading Network.
To correct the deviation, modify the design so the Spreading Network function
is one of the functions listed in the message explanation.
WARNING (TSV-342): Scan Out scanout has an invalid compaction function.

EXPLANATION:
When a Compaction Network is placed between Channel Unload Pins and a Scan Out,
it must evaluate to one of the following functions:
An XOR function of the Channel Unload pins
An XNOR function of the Channel Unload pins
A direct connection from the Channel Unload pin
Inverted from the Channel Unload pin
Any other function of the Channel Unload pins is invalid since aliasing of observe data
may occur.
USER RESPONSE:

Select the specific message from the Specific Message List. The Scan Out pin
is displayed in the Scan State and is traced back to the Channel Unload pins
that drive the Compaction Network.
To correct the deviation, modify the design so the Compaction Network function
is one of the functions listed in the message explanation.
WARNING (TSV-343): CME pipeline element name is corrupted during the scan operation.
This condition may prevents the creation of a single Load Channel Mask event for use by
multiple test sequences.
EXPLANATION:
The application of scan operation corrupts the CME pipeline element. This message states
that the value which was loaded into the latch or flop of the CME pipeline may be overwritten.
Since the value loaded into the CME pipeline may be compromised the mask enable valued
load in one test sequence cannot be used by any subsequent test sequence. This requires
that each test sequence requiring masking contains its own Load Channel Mask event.
USER RESPONSE:
TSV analysis displays the corrupted CME pipeline element. The specific event can be
identified by the TTM-340 message issued during build_testmode which includes the
odometer reading at which the corruption occurred. The Sequence Analyzer can then be
used to view the values which caused the corruption. Change the logic or sequences to
prevent the corruption of the CME pipeline or accept the possible reloading of identical mask
data.
WARNING (TSV-344): Channel mask shift register element name is corrupted during the
scan operation. This condition may prevents the creation of a single Load Channel Mask
event for use by multiple test sequences.
EXPLANATION:
The application scan operation corrupts the channel mask shift register element. This
message states that the value which was loaded into the latch or flop of the Channel Mask
Shift Register may be overwritten. Since the value loaded by the Channel Mask Load
sequence may be compromised the mask values loaded in one test sequence cannot be
used by any subsequent test sequence. This requires that each test sequence requiring
masking contains its own Load Channel Mask event.
USER RESPONSE:
TSV analysis displays the corrupted channel mask shift register element. The specific event
can be identified by the TTM-341 message issued during build_testmode which includes

the odometer reading at which the corruption occurred. The Sequence Analyzer can then be
used to view the values which caused the corruption. Change the logic or sequences to
prevent the corruption of the Channel Mask Shift Register or accept the possible reloading of
identical mask data.
INFO (TSV-345): CME pipeline element name may be corrupted in the Test Generation
state. This condition may prevents the creation of a single Load Channel Mask event for use
by multiple test sequences.
EXPLANATION:
The CME pipeline element may be corrupted in the Test Generation state by the application
of the launch/capture sequence.This message states that the value which was loaded into the
latch or flop of the CME pipeline may be overwritten. Since the value loaded into the CME
pipeline may be compromised the mask enable valued load in one test sequence cannot be
USER RESPONSE:
Change the logic or sequences to prevent the corruption of the CME pipeline or accept the
possible reloading of identical mask data.
INFO (TSV-346): Channel mask shift register element name may be corrupted in the Test
Generation state. This condition may prevents the creation of a single Load Channel Mask
event for use by multiple test sequences.
EXPLANATION:
The channel mask shift register element may be corrupted in the Test Generation state by the
application of the launch/capture sequence.
This message states that the value which was loaded into the latch or flop of the Channel
Mask Shift Register may be overwritten. Since the value loaded by the Channel Mask Load
sequence may be compromised the mask values loaded in one test sequence cannot be
USER RESPONSE:
Change the logic or sequences to prevent the corruption of the Channel Mask Shift Register
or accept the possible reloading of identical mask data.
WARNING (TSV-350): Pulse width clock race. A memory element captures data from
another memory element and both elements are fed by the same clock

commonClockPinName such that the value captured by the receiving element depends on
the width of the clock pulse.
Capture element memoryElementName1, with data input dataPinName1 and clock
input clockPinName1.
Source element memoryElementName2, with source clock input clockPinName2.
EXPLANATION:
Guideline TG.4 states that data from a level-sensitive memory element (either a latch or
a RAM/ROM) may not feed to a level-sensitive memory element clocked by the same
phase of the same clock nor to an edge sensitive memory element that captures on the
edge of the same clock that turns the clock OFF at the level-sensitive memory element.
It also states that an edge sensitive memory element may not feed to another edge
sensitive memory element that is on the opposite edge of the same clock nor to a level-
sensitive memory element whose clock input turns ON when the edge sensitive memory
element captures its data input.
A check for the existence of minimum pulse-width conditions in the logic is performed to
determine whether a clock pulse that is too narrow can cause errors from zero-delay
simulation; inclusive of when pulses meet minimum pulse requirements at memory
elements.
The following figure illustrates this check.

This violation indicates a possible clock pulse width violation between the source and
capture memory elements. It is possible that by lengthening the pulse width of the
primary input clock that the data arriving at the capture memory element would be based
on the new values appearing on the output of the source memory element thus removing
any ambiguity. If the capture clock input is chopped, lengthening the pulse width at the
primary input pin may not prevent the capture of old data while simulation will predict that
the new data would be captured.
Intent:
This guideline helps to ensure that the design will be free of races (other than those
which occur naturally in an edge_sensitifve design) between data and its capturing clock.
All simulation will be performed as if the clock pulses are very wide, i.e. wide enough to
allow all signals to stabilize before the pulse falls.
For more information, refer to "Guideline TG.4 - Clock vs. Data Races" and
Test Structures.

USER RESPONSE:
Exclusive Gating (MEG) option was specified, the design values required to
turn the clocks on at both the source and capture memory elements while a
path is sensitized from the source to the capture element will be displayed.
element, then rerun the test with the MEG option set to yes.
information.

WARNING (TSV-351): [Severe] Pulse width clock race with chopped capture clock. A
memory element captures data from another memory element and both elements are fed by
the same clock commonClockPinNamesuch that the value captured by the receiving
element depends on the width of the clock pulse.
EXPLANATION:

capture memory elements.Since the capture clock input is chopped, lengthening the
pulse width at the primary input pin of the capture memory element may not prevent the
capture of old data while simulation will predict that the new data would be captured.
Intent:
which occur naturally in an edge-sensitive design) between data and its capturing clock.
For more information, refer to "Guideline TG.4 - Clock vs. Data Races" and GSD
Analyze Potential Clock Signal Races in the Encounter Test: Guide 3: Test
Structures.
USER RESPONSE:


element, then rerun the test with the MEG option set to yes.
information.
WARNING (TSV-353): [Severe] Pulse width clock race. A RAM captures data from another
memory element and that memory element may launch a new address input value while the
write clock is actively writing the RAM. Both memory elements are fed by the same clock
commonClockPinName.
Capturing RAM memoryElementName1, with address input addressPinName1 and
clock input clockPinName1.
EXPLANATION:
Address inputs to RAM write ports must remain stable while actively writing the RAM. An
edge sensitive RAM write port may be modeled using the level-sensitive RAM primitive
with address and data inputs buffered with Latches clocked on the opposite phase of the
write clock. It may also be possible to model edge-clock writing behavior using a clock
chopping circuit, but that may not help to resolve this specific issue unless the address
inputs remain stable during the phase of the chopped clock that writes the RAM.
sensitivememory element that is on the opposite edge of the same clock nor to a level-
capture memory elements.

Since the capture clock input is chopped, lengthening the pulse width at the primary input
pin of the capture memory element may not prevent the capture of old data while
simulation will predict that the new data would be captured.
Intent:
Structures.
USER RESPONSE:
the clock primary input to the memory elements clock inputs will be displayed.
element then rerun the test with the MEG option set to yes.

WARNING (TSV-360): Mutual Exclusive Gating (MEG) checking aborted with the specified
EFFORT level while processing this message: Pulse width clock race. A memory element
captures data from another memory element and both elements are fed by the same clock
commonClockPinName such that the value captured by the receiving element depends on
the width of the clock pulse.
EXPLANATION:
cannot occur.
capture memory elements. It is possible that by lengthening the pulse width of the
primary input clock that the data arriving at the capture memory element would be based
on the new values appearing on the output of the source memory element thus removing
any ambiguity. If the capture clock input is chopped, lengthening the pulse width at the
primary input pin may not prevent the capture of old data while simulation will predict that
the new data would be captured.

Intent:
This guideline ensures that the design will be free of races (other than those which occur
naturally in an edge-sensitive design) between data and its capturing clock.
Structures..
USER RESPONSE:
specified EFFORT level while processing this message: Pulse width clock race with chopped
capture clock. A memory element captures data from another memory element and both
elements are fed by the same clock commonClockPinName such that the value captured
by the receiving element depends on the width of the clock pulse.
EXPLANATION:


cannot occur.
Intent:
Structures.
USER RESPONSE:

specified EFFORT level while processing this message: Pulse width clock race. A RAM
captures data from another memory element and that memory element may launch a new
address input value while the write clock is actively writing the RAM. Both memory elements
are fed by the same clock commonClockPinName.
Capturing RAM memoryElementName1, with address input addressPinName1 and
clock input clockPinName1.
EXPLANATION:
cannot occur.

Address inputs to RAM write ports must remain stable while actively writing the RAM.
An edge sensitive RAM write port may be modeled using the level-sensitive RAM
primitive with address and data inputs buffered with Latches clocked on the opposite
phase of the write clock. It may also be possible to model edge-clock writing behavior
using a clock chopping circuit, but that may not help to resolve this specific issue unless
the address inputs remain stable during the phase of the chopped clock that writes the
RAM.
Intent:
Structures.
USER RESPONSE:

To correct the deviation, perform the following:
- If you suspect this is not a true error condition rerun this test with a higher
INFO (TSV-369): There are number controllable scan chains fed by Primary Inputs.
EXPLANATION:
No rules or restrictions, as this message is informational in nature. A controllable scan
chain is a scan chain which can be loaded from Scan In (SI) pins.
Intent:
To identify the number of SIs which feed to controllable scan chains.
USER RESPONSE:
INFO (TSV-370): There are number observable scan chains feeding to Primary Outputs.
EXPLANATION:
An observable scan chain is a scan chain that has a defined unload operation and
associated scan data output.
"Guideline TG.8 - Section Scan State" in the Encounter Test: Guide 3: Test
Structures describe the scan chains for the various scan protocols that are supported
by Encounter Test.
Intent:
To identify the number of SOs which are fed by observable scan chains.

USER RESPONSE:
WARNING (TSV-373): [Severe] A flop flopName is in regtype scan chain number and
its clock is gated in a manner which may cause the scan chain to shift in an inconsistent
manner.
EXPLANATION:
Scan chains which contain flops with gated clocks may not shift as expected when the
gated clock does not control the clock input to the flop and the off value of the clock
results in the flop behaving as a trailing edge flop.
Intent:
This restriction helps to ensure that the scan chain will shift properly.
USER RESPONSE:
Modify the design or the clock polarity such that one of the following conditions is
true.
The off value of the clock controls the gate (this will result in a non-X state at
the clock input to the flop in the Scan State)
The off value of the clock results in the flop behaving as a leading edge flop
You can analyze the violation by performing the following steps:
Select the specific message from the Specific Message List. The flop will be
displayed.
To analyze the message, use the mouse pointer to identify the clock or clocks which
fed the clock pins. The Information Window is updated to show the Clock Affiliation
when the pin is selected.
Using the Clock Affiliation data, trace back from the clock pin of the flop to determine
the paths that are erroneous.
To correct the deviation, modify the gate or change the polarity of the clock such that
the clock off state controls the gate or inverts the signal to the clock input of the flop
such that the flop behaves as a leading edge flop.
INFO (TSV-378): Scan chain beginning at pin pinname and ending at pinname is
controllable and observable. The length of the scan chain is number bit positions.

EXPLANATION:
by Encounter Test.
Intent:
To identify the beginning and end of the scan chain.
USER RESPONSE:
INFO (TSV-379): Observable scan chain ending at pin pinname is not a controllable scan
chain. The length of the scan chain is number bit positions.
EXPLANATION:
by Encounter Test.
Intent:
USER RESPONSE:
INFO (TSV-380): Controllable scan chain beginning at pinname is not observable scan
chain. The length of the scan chain is number bit positions
EXPLANATION:

by Encounter Test.
Intent:
USER RESPONSE:
INFO (TSV-381): Scan chain is controllable and observable.

The Scan In (SI) pin to the scan chain is scanInPinName. The Scan Out (SO) pin of the
scan chain is scanOutPinName. The length of the scan chain is number bit positions.
EXPLANATION:
by Encounter Test.
Intent:
USER RESPONSE:
WARNING (TSV-382): Controllable scan chain branches at objectName into two or more
observable scan chains.
EXPLANATION:
Guideline TG.8 identifies the need for all latches and flip-flops to be fully scannable.
Intent:
The latch or scan-in identified in this message can be used as a control point, but it feeds
to multiple observable scan chains. While this deviation from full scan is allowed under
General Scan Design guidelines, it nonetheless is flagged as an error condition, under
the assumption that a latch that can be scanned into from a scan-in PI should feed to a
single scan-out PO. This condition is most likely symptomatic of a design error rather
than a reflection of true designer intent.

For additional information, refer to "Guideline TG.8 - Section Scan State", in the
USER RESPONSE:
Select the specific message from the Specific Message List. The latch or scan-
in that failed this check is displayed with the appropriate scan state applied.
Additionally, the downstream controllable flops/latches and intervening logic is
displayed.
To analyze the message, use the mouse pointer to trace forward to determine
why the scan chain branches.
INFO (TSV-383): There are number floating latches.

EXPLANATION:
Structures describes floating (non-scannable) latches.
Intent:
To identify the number of latches which are not in a controllable or observable scan chain.
USER RESPONSE:
No response required. To list floating latches in a design, execute
report_test_structures with option reportregsfloat=all or
reportregsfloat=active if only requiring active floating latches in the test mode.
Refer to either report_test_structures in the Encounter Test: Reference:
Commands or Report Test Structures in the Encounter Test: Reference: GUI.
WARNING (TSV-384): Controllable scan chain beginning at objectName is not a

observable scan chain.
EXPLANATION:
Guideline TG.8 - Section Scan State states that all latches and flip-flops must be
contained in scan chains with identified scan-in and scan-out pins.
Intent:
This message is intended to alert you that the design contains a scan chain that is
controllable but not observable. The presence of controllable-only scan chains will not

result in bad test data but may reduce test coverage if the scan chain is needed to
capture response data.
Test generation for a GSD design is optimized for processing time, coverage, and pattern
count by having all latches and flip-flops scannable to primary output pins.
Refer to "Guideline TG.8 - Section Scan State", in the Encounter Test: Guide 3: Test
USER RESPONSE:
If the specified Scan-In pin is shared by one or more scan chains that are observable and
controllable, then the existence of the controllable-only scan chain is most likely not a
cause for concern. If the Scan-In pin is not used as the functional input to any observable
scan chain, there is a strong possibility that the scan chain is broken and the following
procedure should be used to determine the cause.
Select the specific message from the Specific Message List. The schematic display is
updated to show the specified Scan-In pin and the deepest register of the controllable-
only scan chain.
The circuit is set to the Scan state with the logic values for the scan clocks at OFF/ON.
Trace forward from the register to identify why the scan chain is broken.
The following are possible causes:
Missing scan_enable (SE) pins
Incorrect stability values on SE or clock PIs which prevent the scan chain from
being observable
For mux scan designs, the scan path data input of the mux is not selected by
the scan state.
A gated clock path exists such as having a non-fixed value non-scan latch/flop
driving unknown values into the clock gating network, thus blocking either the
data path or clock path (or both).
The scan clocks to the flops are controlled by the scan clock pins but are X
when the scan clock pins are on.
To correct the deviation, modify the logic such that this controllable scan chain is properly
controlled and can be observed at a Scan-Out or by a MISR cell.
WARNING (TSV-385): Observable scan chain ending at objectName is not a controllable

scan chain. The last observation flop that was found in the scan chain is lastObsLatch.
EXPLANATION:

The potential reasons for not identifying the last observation flop could be:
All the observe flops of the channel are scan corrupted or build_testmode was not
able to find any observe flops for this channel.
Guideline TG.8 states that all latches and flip-flops must be contained in scan chains with
identified scan-in and scan-out pins.
Intent:
Test generation for a GSD design is optimized for processing time, coverage, and pattern
count when all latches and flip-flops are contained in scan chains which can be controlled
by scanning data through scan-in pins.
USER RESPONSE:
Select the specific message from the Specific Message List. The schematic display is
updated to show the specified Scan Out pin. The circuit is set to the Scan state with the
logic values for the scan clocks at OFF/ON. The following are possible causes:
Missing scan_enable (SE) inputs
Incorrect stability values on SE or clock PIs which prevent the scan chain from
being observable
For mux scan designs, the scan path data input of the mux does not match the
select value for the scan state
A gated clock path exists such as a having a non-fixed value non-scan latch/flop
driving unknown values into the clock gating network, thus blocking either the
data path or clock path (or both).
Scan clocks may be off in stability but become X when the scan clock PI is set
to opposite the stability state
To correct the deviation, modify the logic such that this observable scan chain is correctly
controlled and scannable from a Scan In pin.
WARNING (TSV-386): A Scan Out (SO) scanOutPinName was not fed by a observable
scan chain.
EXPLANATION:

by Encounter Test.
Intent:
To identify those SOs which are not fed by observable scan chains. When SOs are
present it is assumed that they are intended to be connected to the last bit of an
observable scan chain. Having an extra SO pin is possibly indicative that some scan
chain may be broken or that the wrong pin may have been specified as an SO.
USER RESPONSE:
Select the specific message from the Specific Message List. A backtrace from
the scan-out primary output is shown with the TI/TIE design state applied.
To analyze the message use the mouse pointer to trace backward from this
primary output to determine why there is no path from a scan-in primary input.
Correct the deviation by installing a path from a scan-in primary input.
WARNING (TSV-387): Controllable memory element memoryElementName is not

contained in a observable scan chain.
EXPLANATION:
Guideline TG.8 identifies the need for all latches and flip-flops to be fully scannable.
Refer to ""Guideline TG.8 - Section Scan State", in the Encounter Test: Guide 3: Test
Structures.
Intent:
The memory element identified in this message can be scanned into for use as a control
point, but it has no path to a scan-out primary output. Therefore this memory element
cannot be used as a observe point. This will impair test generation effectiveness and
efficiency.
While this deviation from full scan is allowed under General Scan Design guidelines, it
nonetheless is flagged as an error condition, under the assumption that a memory
element that can be scanned into from a scan-in PI but cannot be scanned out to a scan-
out PO is most likely symptomatic of a design error rather than a reflection of true
designer intent.
USER RESPONSE:

element that failed this check is displayed. The circuit is set to the Scan state
with the logic values for the scan clocks at OFF/ON.
Some of the possible causes may include missing scan_enable (SE) inputs,
incorrect stability values on the scan inputs (scan clocks, SE), improperly gated
clock paths, etc. which prevent the scan chain from being observable.
To analyze the message use the mouse pointer to trace forward from this latch
to determine why there is no path to a scan-out primary output.
Correct the deviation by installing a path to a scan-out primary output from this
latch.
information.
WARNING (TSV-388): Observable memory element memoryElementName is not

contained in a controllable scan chain.
EXPLANATION:
Guideline identifies the need for all latches and flip-flops to be fully scannable.
Intent:
The memory element identified in this message can be scanned out for use as a observe
point, but it cannot be scanned into from a scan-in primary input. Therefore this memory
element cannot be used as a control point. This will impair test generation effectiveness
and efficiency. While this deviation from full scan is allowed under General Scan Design
guidelines, it nonetheless is flagged as an error condition, under the assumption that a
memory element that can be scanned out to a scan-out PO but cannot be scanned into
from a scan-in PI is most likely symptomatic of a design error rather than a reflection of
true designer intent.
USER RESPONSE:
Select the specific message from the Specific Message List. e memory element
that failed this check is displayed. The circuit is set to the Scan state with the
logic values for the scan clocks at OFF/ON.

Some of the possible causes may include missing scan_enable (SE) inputs,
incorrect stability values on the scan inputs (scan clocks, SE), improperly gated
clock paths, etc. which prevent the scan chain from being controllable.
To analyze the message use the mouse pointer to trace back from this memory
element to determine why there is no path back to a scan-in primary input.
Correct the deviation by installing a path from a scan-in primary input to this
memory element.
information.
INFO (TSV-389): There are number inactive (non-scan) latches.

EXPLANATION:
"Guideline TG.8 - Section Scan State", in the Encounter Test: Guide 3: Test
Structures identifies the need for all latches and flip-flops to be fully scannable.
Intent:
To identify the number of inactive latches which are not in a controllable or observable
scan chain. Inactive latches do not feed to primary outputs, hence cannot be used to
observe fault effects nor to activate observable faults.
USER RESPONSE:
WARNING (TSV-390): There are number inactive (non-scan) latches.

EXPLANATION:
Intent:
To identify the number of inactive latches which are not in a controllable or observable
scan chain. Inactive latches do not feed to primary outputs, hence cannot be used to
observe fault effects nor to activate observable faults.
USER RESPONSE:
It is not normal for latches to be unobservable for a BOUNDARY=NONE or
BOUNDARY=INTERNAL test modes. If this condition is expected then no response is
required. If not, then check that all scan-in and scan-out pins are correctly identified and
that there are no Test Inhibit (TI) pins blocking latch scanability or observability.

To list floating latches in a design, execute report_test_structures with option

reportregsfloat=all or reportregsfloat=active if only requiring active
floating latches in the test mode. Refer to either report_test_structures in the
Encounter Test: Reference: Commands or Report Test Structures in the
Encounter Test: Reference: GUI.
WARNING (TSV-391): MISR cell misr cell latch does not feed MISR Observe (MO)
misr observe latch either directly or through an XOR/XNOR network with other MISR
bits.
EXPLANATION:
MISR Observe pins must be fed either directly from a MISR cell or from a combination
of MISR cells through an XOR or XNOR network.
If this message is accompanied by a TSV-204 message, this is a severe condition which
indicates that the MISR cell does not feed any MISR Observe pin in any fashion.
If an accompanying TSV-204 message is not produced, this indicates that there is a path
from this MISR cell to a MISR Observe pin but it is not fed directly or through an XOR/
XNOR network.
Notes:
The TSV-391 check is done on all MISR cells which feed a particular MISR
Observe pin whether or not they are contributing terms to that specific MISR
Observe pin.
For the case that the TSV-391 message is issued without an accompanying
TSV-204 message: if a MISR cell reconverges on itself, it is not an error
condition but probably a non-contributing MISR cell to MISR Observe pin being
checked.
USER RESPONSE:
Select the specific message from the "Specific Message List"
All MISR cell latches feeding to the MISR Observe pin specified in the message
are displayed with the MISR Observe state applied. The Misr Cell latches
feeding the Misr Observe pin are placed at the values where the network
between them first failed to function as an XOR or XNOR of the feeding Misr
Latches.
Trace back from the MISR Observe pin to the MISR latches to identify the logic
feeding the pin.

To correct the deviation, modify the design so the MISR Observe pin is fed by
one of the following when the design is in the MISR Observe state:
- A direct path from the misr cell latch to the misr observe pin
- The MISR Observe pin is fed by an XOR or XNOR of the incoming MISR cell
latches.
WARNING (TSV-392): MISR cell misr cell latch is XORed with count other bits
from the same MISR when observed at MISR Observe (MO) misr observe pin.
EXPLANATION:
XORing multiple bits from the same MISR increases the chance that aliasing will occur,
which can mask defective responses from being observed. Since defect coverage may
be effected, it is strongly recommended that mixing MISR bits from the same MISR be
avoided.
USER RESPONSE
All MISR cell latch from the same MISR feeding the same MISR Observe pin
are displayed with the MISR Observe state applied.
If this was not your intention, modify the design so the MISR Observe pin is not
fed by more than one MISR cell latch from the same MISR.
WARNING (TSV-393): MISR cell misr cell latch feeds count Misr Observe Pins.
Encounter Test supports MISR cells that feed multiple MISR Observe Pins, but this may
cause signature aliasing.
EXPLANATION:
For On-Product-Misr-Plus testmodes, a MISR cell is allowed to feed multiple MISR
Observe latches.
USER RESPONSE:
All MISR Observe pins fed from the same MISR cell are displayed with the
MISR Observe state applied.

WARNING (TSV-397): ISR observe validation threshold exceeded. verify_test_structures

will simulate 65536 patterns.
EXPLANATION:
Encounter Test verifies the presence of an XOR network for MISR observe pins via
simulation of the contributing MISR cells which feed the possible XOR network.
Intent:
To insure reasonable performance, a limit of 65536 patterns will be simulated. This limit
is sufficient to exhaustively simulate a sixteen term XOR network. This message is
printed if there are more than 16 MISR cells feeding a specific MO pin.
Since an MO pin can have an arbitrary number of MISR cells inputs, a reasonable limit is
set on how many simulations are performed to verify the XOR nature of the n MISR cells
feeding the MO pin. This limit is set to 65,536 (2**16) which means that MO pins with 16
or fewer inputs (MISR cells) will be exhaustively tested to see of its value is the XOR of
its inputs.
If an MO pin has more than 16 inputs (requiring more that 65,536 simulations to
exhaustively verify its XOR behavior), the simulation is stopped at this limit and this
message is printed indicating that the MO pins source network was not exhaustively
simulated to verify that it functioned as an XOR. Exhaustive simulation of more than 16
inputs would require a large runtime, so a reasonable check of the MO pin is performed
using this limit.
As a matter of practicality, if an MO pin has behaved like an XOR of MISR cells for the first
65,536 input patterns, it likely is an XOR function. If any pattern tried does not behave as
the XOR of its inputs, a severe TSV-391 message is printed indicating this and the
verification of that bit position ceases.
In short, receiving a TSV-397 requires no specific action; the message is intended to
notify that the specific network was not exhaustively simulated to guarantee that the MO
pin functions as the XOR of its inputs.
USER RESPONSE:
WARNING (TSV-400): [Severe] Fuse fuse name does not feed any latch in an
observable scan chain.
EXPLANATION:

Burlington Manufacturing Electronic Chip ID Specification requires each ECID fuse be

connected to a measurable latch. Furthermore, the fuses must be connected in a manner
such that the corresponding observe latches are contiguous, compatible (all RMLs or all
BMLs) and in ascending order.
Intent:
To identify ECID fuses which do not meet the ECID specification. The fuse identified by
this message does not feed any latch in an observable scan chain.
USER RESPONSE:
The fuse will be displayed.

WARNING (TSV-401): [Severe] Candidate candidate number (fuse 0 latch
name, bit bit of observable scan chain register) for fuse fuse 0 name does not have
a compatible candidate for fuse fuse 1 name (the valid candidate would be next latch
name, bit next bit of observable scan chain register).
EXPLANATION:
Intent:
To identify ECID fuses which do not meet the ECID specification. The fuse fuse 1
name identified by this message, based on selecting fuse 0 latch name as a
starting point for fuse 0 name does not feed a latch which meets this specification.
Either: the latch fed by fuse 1 name is not contiguous in the observation register, the
latch is the incorrect type, or the fuse 1 name is not in ascending order. The correct
latch, based on the ECID criteria would be next latch name.
USER RESPONSE:


WARNING (TSV-402): [Severe] A valid set was found beginning with fuse fuse 0 name
(the observable latch latch name, bit bit of observable scan chain register) but a
simultaneous isolation path from the fuses to the observable scan chain could not be
established.
EXPLANATION:
Intent:
To identify ECID fuses which do not meet the ECID specification. Given the selection of
latch name as the starting point in the observable scan chain register, paths from
each fuse to every selected ECID latch could not be simultaneously established. It is
possible that an incorrect starting point has been chosen if there are more than one
fuse 0 name ECID latch candidates. If so, the invalid path must be removed so the
correct latch selection can be made.
USER RESPONSE:
WARNING (TSV-403): [Severe] Candidate candidate number (fuse 0 latch

name, bit bit of observable scan chain register) for fuse fuse 0 name does not have
a compatible candidate for fuse fuse 1 name (the observe register does not contain
enough bits).
EXPLANATION:

Intent:
To identify ECID fuses which do not meet the ECID specification. This is similar to TSV-
400, but in this case there are not enough contiguous bits in the identified observable
scan chain register when bit bit is selected for fuse 0 latch name.
WARNING (TSV-404): [Severe] Fuse fuse number is missing.

EXPLANATION:
Intent:
To identify fuses which do not meet the ECID specification. Fuses must be contiguously
numbered and ascending in order. In this case, fuse number is missing or not in order.
USER RESPONSE:
No analysis is possible.
WARNING (TSV-420): [Severe] Macro scanout pin objectName was not fed by a latch
having one of the allowed measure bit positions designated in the Macro scanout pins
TB_OBS_REG_POSITION attribute. The measure bit position of the failing pin is
objectName. A value of minus one (-1) indicates that the Macro pin is not in the scan path.
EXPLANATION:
This check is run only in Macro testmodes and is skipped if the mode uses custom scan
sequences.
Intent:
The purpose of this check is to verify that the scan latch that feeds the macro scanout
pin has an allowed measure bit position. The allowed positions are those listed in the
TB_OBS_REG_POSITION attribute. This error indicates that the latch feeding the

identified macro scanout pin does not occupy any of the allowed measure bit positions
or this pin is not in the scan chain.
USER RESPONSE
From the Encounter Test GUI, click Show-Messages-Verify Test Structures.
This brings up a summary list of the messages for this test mode.
From the Verify Test Structures Message Summary., select message TSV-420
and click OK (or double-click on the message). This brings up a list of specific
instances of message TSV-420.
From the Specific Message List., select the specific message and click OK (or
double-click on the message).
A backtrace from the specified macro scanout pin is displayed with all scan
control pins at value and all clocks off.
Look at the displayed backtrace.
If there is no latch that precedes the macro scanout pin; then the macro scanout
pin is not in the scan chain.
If there is a latch that precedes the macro scanout pin; then find the allowed
positions in the TB_OBS_REG_POSITION attribute and determine if the
preceding latch meets that criteria:
Perform the following tasks to find the allowed positions:
- Select the macro scanout pin and use the custom mouse button (usually the
right mouse button) to get a list of "Pin Actions"
- Select Edit to get a cascading menu of "Edit" Actions
- Select Pin Properties to get the "Edit Properties" Window with a list of the -
properties on this pin.
- Read the value(s) for the TB_OBS_REG_POSITION attribute. Each value
between the commas is a valid position for the latch preceding this pin.
- Click Cancel to close the window
Perform the following tasks to determine the position of the latch you found in
the backtrace,
- Put your mouse on the latch and look in the Information Window to find
Observable scan chain information (it should tell you the register number, the
scan out name, and the Bit Position number). Look for the Bit Position number

- If the Observable scan chain does not appear in the Information Window, take
the following actions:
- If it appears as though the data may be below what you can see, press
Ctrl+s to suppress the Information Window update and then move the mouse
to the Information Window and press PageDown . Alternatively, you may click
on the dashed line above the Information Window to make it into a separate
window that you can resize. (Press Ctrl+s again, or click on the schematic
display to restart the Information Window update).
- If the data does not appear, click Options-Information Window. From the list
on the right, select Function: Latch Scan Data and click the left pointing
arrow to move it to the bottom of the list on the left. This will add the Latch Scan
Data into the Information Window.
- If the data still does not appear in the Information Window, the latch probably
is not recognized as part of the scan chain; look for other
verify_test_structures messages to determine why the latch isnt
scannable.
If there is a scannable latch in the sensitized path to the macro scanout pin, but
its Observable scan chain Bit Position doesnt match any of the positions in the
TB_OBS_REG_POSITION attribute, you need to change the order of the scan
chain (in Test Synthesis or Physical Design).
If there is a scannable latch (with a valid Bit Position number) that appears to
feed the macro scanout pin, then Encounter Test was unable to sensitize the
path between the latch and the scanout pin (i.e., the data from the latch cant
get to the scanout pin). Check for gating logic that blocks the path or for clocking
problems.
Refer to GSD Analyze Flip-Flop and Latch Scan Characteristics in the
WARNING (TSV-450): [Severe] Required State Violation: hierIndexofInput is not at

required state.
Required state is requiredState but the actual state is actualState.
EXPLANATION:
Intent:
To ensure that all pins with the required state attribute (+/- RS) are at the required state
at the end of the first pattern in the mode initialization sequence.
USER RESPONSE:

Select the specific message from the "Specific Message List". The design is set
to the state at the end of the first pattern of the mode initialization sequence.
Trace backwards from the displayed block to discover why the designated pin
was not at the required state.
Correcting this may require changing the first pattern pattern of the mode
initialization sequence, changing the values of any Initial State (+/- IS) pins or
both.
INFO (TSV-569): There are number controllable scan chains fed by on-product Pseudo-
Random Pattern Generator (PRPGs).
EXPLANATION:
A controllable scan chain is a scan chain that has a defined load operation and
associated scan data input.
Intent:
To identify the number of controllable scan chains which are fed by on-product PRPGs.
USER RESPONSE:
INFO (TSV-570): There are number observable scan chains feeding to on-product Multiple-
Input Signature Register (MISRs).
EXPLANATION:
A controllable scan chain is a scan chain that has a defined unload operation and
Intent:
To identify the number of observable scan chains which feed to on-product MISRs.
USER RESPONSE:
WARNING (TSV-571): [Severe] A Scan In (SI) objectName does not feed to a Scan Out
(SO), a Multiple-Input Signature Register (MISR) input, or a controllable latch.
EXPLANATION:

by Encounter Test.
Intent:
Each pin identified as an SI must feed either an SO pin, a MISR input or a controllable
flop/latch.
USER RESPONSE:
Trace forward from the indicated SI to see what it feeds. Look for a blockage on a path
from the SI to a MISR or a latch.
INFO (TSV-581): Scan chain is controllable and observable. The Pseudo-Random Pattern
Generator (PRPG) output feeding to the scan chain is objectName. The Multiple-Input
Signature Register (M ISR) input fed by the scan chain is objectName. The length of the
scan chain is number bit positions.
EXPLANATION:
A controllable scan chain is a scan chain that has a defined load operation and
associated scan data input. An observable scan chain is a scan chain that has a defined
unload operation and associated scan data output.
by Encounter Test.
Intent:
To identify a scan chain which is both a controllable and an observable scan chain.
USER RESPONSE:
INFO (TSV-590): number information level message(s) was/were suppressed during

verify_test_structures test name
EXPLANATION:
This message is produced if verify_test_structures is run with
suppressmsg=yes and there were suppress message attributes identified in the logic
for a specific message.

None.
Intent:
Allow the suppression of messages which you do not want displayed.
USER RESPONSE:
WARNING (TSV-591): number warning level message(s) was/were suppressed during

EXPLANATION:
None.
Intent:
USER RESPONSE:
WARNING (TSV-592): number error level message(s) was/were suppressed during

EXPLANATION:
None.
Intent:
USER RESPONSE:

WARNING (TSV-593): [Severe] number severe level message(s) was/were suppressed

during verify_test_structures test name
EXPLANATION:
None.
Intent:
USER RESPONSE:
WARNING (TSV-594): verify_test_structures processing ended before all selected

tests were complete.
EXPLANATION:
verify_test_structures did not complete all of the selected tests for one of the
following reasons.
verify_test_structures processing was stopped through a stoponerror
option (e.g. stoponerrorclockusage=yes)
verify_test_structures processing was stopped early by a signal
interrupt.
The message cut off option messagecounttotal=n,
messagecountsevere=n, messagecounterror=n was reached.
USER RESPONSE:
WARNING (TSV-595): MUX objectName with unset select has both inputs fed by the
same clock.
EXPLANATION:

Both inputs of the Mux are fed by the same clock. The path delay between the clock and
Mux Data0 input could be different from the path delay between the clock and Mux Data1
input. This may lead to clock skew. As a result there is a delta cycle delay between the
transition of the two input clocks. Because they are seen as different, the X from the
Select input is propagated onto the output of the Mux as a delta-cycle glitch.
Encounter test assumes that the Mux is at a known value when both inputs to the Mux
are fed by the same clock. This known value being the value of the input clock.
USER RESPONSE:
Ensure that there is no skew between the clocks feeding the two inputs of the Mux or
change their design to avoid feeding the inputs of the Mux by the same clock.
WARNING (TSV-596): This COMPRESSION/DECOMPRESSION testmode has a zero

length scan chain beginning at pinname and ending at pinname.
EXPLANATION:
A zero length scan chain (no memory elements) was found in the design. This may not
be intended and should be verified.
USER RESPONSE:
If the design intent is for all scan chains to have at least one scannable flop modify the
design to insure that this scan chain contains at least one flop which is observable.

INFO (TSV-900): verify_test_structures processing has started localDateTime.
EXPLANATION:
Intent:
To indicate that verify_test_structures processing has started.
USER RESPONSE:
INFO (TSV-901): No verify_test_structures license available at this time.

EXPLANATION:

verify_test_structures was unable to obtain the needed license. This indicates
that all of your verify_test_structures licenses were in use.
Intent:
The running of the verify_test_structures checks is dependent on the obtaining
of a valid verify_test_structures license. No licenses were available at the time
when verify_test_structures was started. verify_test_structures did not
continue to perform the selected checks.
USER RESPONSE:
Select the verify_test_structures application when a
verify_test_structures license is available.
INFO (TSV-902): Unable to obtain lock on design at this time. No

verify_test_structures checking was performed.
EXPLANATION:
verify_test_structures must be able to read the model information which is
needed for the verify_test_structures processing. The running of the
verify_test_structures tests is dependent on reading the model. Another
Encounter Test session has locked the model so verify_test_structures could not
read the model data it needed to process.
Intent:
verify_test_structures did not continue to perform the selected tests. Use locking
for data integrity.
USER RESPONSE:
Select the verify_test_structures application when model data is available.
INFO (TSV-903): Unable to obtain lock on testmode at this time. No

verify_test_structures checking was performed.
EXPLANATION:
verify_test_structures must be able to load the test mode information which is
needed for verify_test_structures processing. The running of the
verify_test_structures test is dependent on reading the test mode data. Another

Encounter Test session has locked the test mode so verify_test_structures could
not read the test mode data it needed to process.
Intent:
verify_test_structures did not continue to perform the selected tests. Use locking
for data integrity.
USER RESPONSE:
Select the verify_test_structures application when the test mode data is
available.
INFO (TSV-904): Another verify_test_structures session is already running on this

design and test mode. No verify_test_structures checking was performed.
EXPLANATION:
For any mode only one verify_test_structures run may be active at a time.
Intent:
To ensure data integrity.
USER RESPONSE:
Wait for the design to become available and then select Verify Test Structures.
INFO (TSV-905): verify_test_structures can not be run on a test mode of scan type
of 1149.1.
EXPLANATION:
Test modes are checked by Encounter Tests IEEE 1149.1 Boundary Scan verification.
USER RESPONSE:
Run IEEE 1149.1 Boundary Scan Verification from the Test Structure Analysis (TSA)
menu.
ERROR (TSV-906): Invalid scan type identified for this test mode.
EXPLANATION:

verify_test_structures processes only the following scan types: Level Sensitive

Scan Design (LSSD), General Scan Design (GSD), and NONE.
Intent:
verify_test_structures checks that the scan type identified by the test mode
definition can be processed.
USER RESPONSE:
Check your mode definition and make sure you specify a valid scan type. Fix mode
definition and rerun Create a Test Mode.
INFO (TSV-907): This invocation of verify_test_structures did not produce any

messages.
EXPLANATION:
Intent:
verify_test_structures indicates whether it produces any messages for this
invocation.
USER RESPONSE:
INFO (TSV-908): verify_test_structures processing complete.

EXPLANATION:
Intent:
verify_test_structures indicates that all processing is complete for the current
invocation.
USER RESPONSE:
INFO (TSV-909): Methodology of LBIST not allowed with Scan type of none.
EXPLANATION:

verify_test_structures will not process a test methodology of LBIST when a scan
type of none has been specified in the mode definition.
Intent:
verify_test_structures checks that a test methodology of LBIST has not been
specified when a scan type of none has been identified in the test mode definition.
USER RESPONSE:
INFO (TSV-910): Incompatible version of TSV. Rebuild testmode and rerun TSV.
EXPLANATION:
Intent:
verify_test_structures has determined that it is necessary to rebuild the
testmode and then rerun verify_test_structures to ensure valid results are
obtained.
USER RESPONSE:
Rebuild the mode and rerun Verify Test Structures.
ERROR (TSV-912): Error reading Mode Def statistics record from globalData.
EXPLANATION:
verify_test_structures encountered a problem while trying to read globalData.
The running of the verify_test_structures checks is dependent on reading the
Mode Def statistics.
Intent:
verify_test_structures did not continue to perform the selected tests. This
message is issued to protect verify_test_structures from abnormal terminations.
USER RESPONSE:


which you failed.
ERROR (TSV-913): Error reading test methodology from globalData.

EXPLANATION:
verify_test_structures did not find a valid test methodology on globalData.
verify_test_structures processes only the following test methodologies: Stored
Pattern Test Generation (SPTG), Weighted Random Pattern Test (WRPT), and Logic
Built-in-Self Test (LBIST).
Intent:
verify_test_structures checks that the test methodology identified by the test
mode definition can be processed. verify_test_structures did not continue to
perform the selected tests.
USER RESPONSE:
A brief explanation concerning the verify_test_structures scenario in which you
failed.
INFO (TSV-915): The srdiag command is no longer supported in

verify_test_structures. Identification of partial scan chains is now part of the normal
checking.
The report generated from srdiag=yes can be obtained using reportscanchains=yes.

EXPLANATION:
The srdiag command (srdiag=yes/no) is no longer supported . Identification of
partial scan chains is now part of the normal checking.
Intent:

Indicates that this command is no longer supported. verify_test_structures will

continue to perform the selected tests.
USER RESPONSE:
Remove srdiag=yes/no from your command line. The report that was previously
generated by srdiag=yes can be obtained using report=scanchains=yes.
If srdiag=yes is specified verify_test_structures will continue to output
complete and partial scan chain information.
If srdiag=no is specified verify_test_structures will ignore this command.
INFO (TSV-920): verify_test_structures remove files option has been run.

EXPLANATION:
The program specification to remove files has been run.
USER RESPONSE:
WARNING (TSV-921): verify_test_structures has been terminated early.

EXPLANATION:
The program has ended early.
USER RESPONSE:
WARNING (TSV-922): This test has been run previously and will not be rerun.
EXPLANATION:
Refer to previous log or view messages to see the complete set of messages. Messages
from the previous run are included in the summary at the end of this log.
USER RESPONSE:
ERROR (TSV-999): Severe processing error, verify_test_structures has terminated

early.
EXPLANATION:

A condition was encountered from which verify_test_structures cannot recover.

All verify_test_structures checking is suspect.
Intent:
A problem exists in the data verify_test_structures used to perform its checks.
This message is issued to protect verify_test_structures from abnormal
terminations.
USER RESPONSE:
which you failed.

72
TSY - Test Synthesis Messages
TSY-001 through TSY-050 on page 2207

TSY-001 through TSY-050

ERROR (TSY-001): Could not read fileName specified for keyword keyword.
EXPLANATION:
insert_scan attempted to open the file listed, but was unable to. The insert_scan
command will terminate.
USER RESPONSE:
Ensure the file exists and is readable, then rerun insert_scan.
ERROR (TSY-002): Could not write to file/directory fileName specified for keyword
keyword.
EXPLANATION:

insert_scan attempted to write to the file listed, but was unable to. The insert_scan
command will terminate.
USER RESPONSE:
Ensure the file/directory exists and is writable, then rerun insert_scan.
ERROR (TSY-003): [Internal] Could not open/create the file fileName when trying to
action.
EXPLANATION:
The executed command attempted to open/create to the file listed, but was unable to.
The command will terminate.
USER RESPONSE:
Contact Encounter Test Customer Support (see Contacting Customer Service on
page 23).
ERROR (TSY-004): Unable to determine the number of scan chains desired. More input is
required.
EXPLANATION:
The insert_scan command needs to be supplied some information in order to
determine the number of scan chains desired. This message indicates that
insert_scan could not determine this number based on the inputs provided.
USER RESPONSE:
Either supply an IOSpecList (using the iospeclistin keyword), or use the command
line keyword numscanchains to provide enough information for insert_scan to
determine the number of scan chains to be inserted.
ERROR (TSY-005): Invalid value specified with pin pinName for the keywordName
keyword.
EXPLANATION:
The value specified is invalid. If specified, only the values 0 or 1 are valid.
USER RESPONSE:
Correct the specified keyword value and rerun.
ERROR (TSY-006): The keyword keyword must be specified.

EXPLANATION:

insert_scan requires the named keyword to be specified.

USER RESPONSE:
ERROR (TSY-007): OPMISR logic can only be inserted with RTL compiler
(scanengine=rc).
EXPLANATION:
OPMISR logic insertion is only supported with RTL compiler.
USER RESPONSE:
Verify RC is installed RC and ensure the rc executable is in the PATH.
ERROR (TSY-008): The RC script file_name is not a readable file.

EXPLANATION:
The program is trying to execute an RTL Compiler script that cannot be read.
USER RESPONSE:
Perform either or both of the following actions, then rerun:
If executescript is specified, ensure the specified file exists and is readable.
Ensure proper file system permissions are established for the specified file.
ERROR (TSY-009): Could not write to file/directory file_name.

EXPLANATION:
The program is prohibited from writing to the referenced directory or file.
USER RESPONSE:
Ensure proper file system permissions are established for the referenced file and rerun.
ERROR (TSY-010): The build_top_shell command could not read file fileName
specified for keyword keyword.
EXPLANATION:
build_top_shell attempted to open the file listed, but was unable to. The
build_top_shell command will terminate.
USER RESPONSE:

Ensure the file exists and is readable, then rerun build_top_shell.
ERROR (TSY-011): The build_top_shell command could not write to file/directory

fileName specified for keyword keyword.
EXPLANATION:
build_top_shell attempted to write to the file listed, but was unable to. The
USER RESPONSE:
Ensure the file/directory exists and is writable, then rerun build_top_shell.
ERROR (TSY-012): [Internal] The build_top_shell command could not open/create

the file fileName when trying to action.
EXPLANATION:
build_top_shell attempted to open/create to the file listed, but was unable to. The
USER RESPONSE:
Contact Encounter Test Customer Support (see Contacting Customer Service on
page 23).
ERROR (TSY-013): The keyword keyword must be specified for the build_top_shell
command.
EXPLANATION:
build_top_shell requires the named keyword to be specified.
USER RESPONSE:
ERROR (TSY-014): Unable to locate the executable executable_name. Ensure your

PATH is set up to point to the Encounter Test Installation directories.
EXPLANATION:
The command was unable to locate an executable version of the listed command.
USER RESPONSE:
Ensure an executable version of the listed command exists, and that it can be found in
your PATH environment variable, then rerun.

ERROR (TSY-015): Parameter opmisr is set to yes. The original OPMISR macro can only
be inserted by build_top_shell. Switching parameter opmisr to plus.
EXPLANATION:
The specified opmisr option must be no or plus when specifying scanengine=rc.
USER RESPONSE:
Specify opmisr=plus and rerun.
ERROR (TSY-016): numchains has to be equal or greater than number when scanio
is scanio_value.
EXPLANATION:
An invalid combination of parameters has been specified. OPMISR insertion requires a
minimum number of scan chains to be specified.
USER RESPONSE:
Increase the numchains value and rerun
ERROR (TSY-017): Option numchains OR option scanins is required to perform

insert_scan without an IOSpecList.
EXPLANATION:
When an IOSpecList is not specified, the keywords numchains or scanins must be
specified.
USER RESPONSE:
Specify one of the two options or specify an IOSpecList and rerun.
ERROR (TSY-018): numchains has to be even and equal or greater than number when
scanio is scanio.
EXPLANATION:
An invalid combination of keywords has been specified. The OPMISR option
scanio=bidi requires an even number of scan chains to be specified.
USER RESPONSE:
Modify the misrsize parameter and rerun.
ERROR (TSY-019): When opmisr=plus, either numchains or misrsize must also be

specified.

EXPLANATION:
An option required for OPMISR+ insertion is missing.
USER RESPONSE:
Specify one of the stated options and rerun.
ERROR (TSY-020): Command-line option fanout must be specified when opmisr=plus.

is specified.
EXPLANATION:
An option required for OPMISR+ insertion is missing.
USER RESPONSE:
Specify the fanout option and rerun.
ERROR (TSY-021): numchains has to be even when greater than 16 and scanio is uni.
EXPLANATION:
An invalid combination of parameters has been specified.
USER RESPONSE:
Specify the numchains keyword value and rerun.
ERROR (TSY-022): Renaming file file1 to file2 failed Reason: cause.

EXPLANATION:
The rename operation returned an error.
USER RESPONSE:
Check the filesystem permissions for possible causes of failure, resolve the problems
and rerun.
ERROR (TSY-023): Could not check out the required Encounter Test license needed to
invoke RTL Compiler.
EXPLANATION:
The program does not detect the license required to invoke the RTL Compiler.
USER RESPONSE:
Ensure the required license is available. If using a server make sure the CDS_LIC_FILE
environment variable is properly defined and rerun.

ERROR (TSY-024): Checkout of license license failed.

EXPLANATION:
The program failed to obtain the referenced license.
USER RESPONSE:
Ensure the required license is available. If using a server make sure the CDS_LIC_FILE
environment variable is properly defined and rerun.
ERROR (TSY-025): Error while processing IOspeclist Parser API command_name. The
command line option command_option is not recognized.
EXPLANATION:
The IOspeclist Parser attempted to execute the specified command, but was unable to
do so because the specified input command option was not recognized. Processing will
terminate.
USER RESPONSE:
Specify a valid command option and rerun. Refer to build_jtag_macro in the Encounter
ERROR (TSY-026): Cannot use reserve word port_name as a port name.

EXPLANATION:
Use of reserve words as port names is disallowed.
USER RESPONSE:
Ensure that all port names are not reserved words (that is, in the BsdlReservewords
list). Refer to the Customer-Specific User Guide.
ERROR (TSY-027): jtag_inline requires that a jtag_inline string be specified and one
has not been specified.
EXPLANATION:
The syntax iospec2::convert_jtag_inline requires that a jtag_inline string
be specified.
USER RESPONSE:
Ensure that a jtag_inline string has been specified either in the IOSpecList that is
read in or on the command line and rerun. Refer to build_jtag_macro in the Encounter

ERROR (TSY-028): In the jtag_inline section, register register has been specified with
more than one length. A register may only have one length value.
EXPLANATION:
A register may only have one length value in the jtag_inline section.
USER RESPONSE:
Ensure a register only has one length value in the jtag_inline section and rerun.
ERROR (TSY-029): The length of the DEVICE_ID register specified for the instruction
instruction must be 32 bits.
EXPLANATION:
The length of the USERCODE and IDCODE registers must be 32 bits.
USER RESPONSE:
Ensure that 32bit length values are specified for the USERCODE and IDCODE registers.
32 bits is assumed if a length value is not specified.
ERROR (TSY-030): command_name requires that a entity is specified using the

flag_name option.
EXPLANATION:
The IOspeclist Parser was unable to execute the specified command because the
required value for the command line option was not specified. Processing will terminate.
USER RESPONSE:
Ensure that the required command line options are used, then rerun. Refer to
build_jtag_macro in the Encounter Test: Reference: Commands.
ERROR (TSY-031): Incorrect IOSPECIFYDATA value entered. IOSPECIFYDATA must

equal BSDL_INLINE|JTAG_INLINE|WRAPPER_INLINE. Processing will terminate.
EXPLANATION:
IOSPECIFYDATA must equal BSDL_INLINE|JTAG_INLINE|WRAPPER_INLINE.
USER RESPONSE:
Ensure that IOSPECIFYDATA equals
BSDL_INLINE|JTAG_INLINE|WRAPPER_INLINE and rerun.
ERROR (TSY-032): jtag_inline requires that the global keyword TOP_MODULE_NAME

be specified in order to generate a proper BSDL file and one has not been specified.

EXPLANATION:
iospec2::convert_jtag_inline requires that the global keyword
TOP_MODULE_NAME be specified in order to generate a proper BSDL file
USER RESPONSE:
Specify the global keyword TOP_MODULE_NAME and rerun.
ERROR (TSY-033): The number of scan in (number_si) and scan out ports
(number_so) do not match.
EXPLANATION:
The number of specified scan-in port and scan-out ports much be the same.
USER RESPONSE:
Rerun the command specifying the same number of scan-in port and scan-out ports.
ERROR (TSY-034): When option parameter1 is specified, parameter2 must also be

specified.
EXPLANATION:
The referenced options must be specified together, but only one has been specified.
USER RESPONSE:
Rerun the command with the missing parameter specified.
ERROR (TSY-035): The specified module module_name is not found in the loaded
design.
EXPLANATION:
The specified module name was not present in the loaded design.
USER RESPONSE:
Verify or correct the spelling of the specified module, verify all design files have been
specified and correctly loaded, and then rerun.
ERROR (TSY-036): When opmisr=plus, the fanout parameter also must be specified.
EXPLANATION:
A co-requisite option required for OPMISR+ insertion was not specified.
USER RESPONSE:

Specify the missing option and rerun.
ERROR (TSY-037: The IOSpecList line line has invalid characters.

EXPLANATION:
The IOSpecList has a line which can be interpreted as either a port definition or a global
keyword.
USER RESPONSE:
Correct the syntax eror on the indicated line and rerun.
ERROR (TSY-040): The keyword keyword must be specified for build_1500_wrapper.

Enter the keyword with a valid value and rerun.
EXPLANATION:
The build_1500_wrapper command requires the referenced keyword to be specified.
USER RESPONSE:
Specify the keyword with a valid value and rerun. Refer to build_1500_wrapper in the
Encounter Test: Reference: Commands for keyword values or use interactive
command help to obtain information on valid values. Refer to Getting Help in the
Encounter Test: Reference: Commands for details.
ERROR (TSY-041): Could not read file filename specified for the
build_1500_wrapper keyword keyword. Ensure the file name is correct and that you
have read permission and rerun.
EXPLANATION:
The build_1500_wrapper command failed to open the referenced file and
terminated.
USER RESPONSE:
Ensure the file exists and is readable, then rerun build_1500_wrapper.
ERROR (TSY-042): Could not write to file/directory filename specified for

build_1500_wrapper keyword keyword. Ensure the name is correct and that you have
permission to write to the directory and rerun.
EXPLANATION:
The build_1500_wrapper command failed to write to the referenced file and
terminated.

USER RESPONSE:
Ensure the file/directory exists and is writable, then rerun build_1500_wrapper.
ERROR (TSY-043): Could not create the directory directory.

EXPLANATION:
The mkdir() command failed when attempting to create the specified directory.
USER RESPONSE:
Ensure the parent directory exists and permissions are in place to create this directory,
and rerun.
ERROR (TSY-044): An IOSpecList with TOP_MODULE_SCAN=YES has been specified but

scanengine=bg is also specified. TOP_MODULE_SCAN=YES can only be used when RTL
Compiler is used to insert scan (scanengine=rc).
EXPLANATION:
If scanengine=bg was not specified on the command-line, the RTL Compiler
executable was not found in the PATH and the requested feature requires RTL Compiler.
USER RESPONSE:
Ensure scanengine=bg is not specified and RTL Compiler is in the PATH, and rerun.
Note: RTL Compiler may not be supported on some platforms supported by Encounter
Test.
ERROR (TSY-045): Incorrect number of arguments to command.

EXPLANATION:
If scanengine=bg was not specified in the command string, the RTL Compiler
executable was not found in the PATH. The requested feature requires RTL Compiler.
USER RESPONSE:
Ensure scanengine=bg is not specified and RTL Compiler is in the PATH, and rerun.
Note: RTL Compiler may not be supported on some platforms supported by Encounter
Test.
ERROR (TSY-046): Unknown option option to command

EXPLANATION:
An invalid option has been specified.

USER RESPONSE:
Specify a valid option for the command and rerun. Refer to the Encounter Test:
Reference: Commands for valid keywords.
ERROR (TSY-047): Input filetype filename not found.

EXPLANATION:
The referenced file cannot be found.
USER RESPONSE:
Ensure the file is correctly specified and rerun.
ERROR (TSY-048): Global keyword BOUNDARY_TYPE in the IOSpecList is set to a value

other than IEEE_11491 or IEEE_11496. The supported values for this keyword are
IEEE_11491 and IEEE_11496. IEEE_11491 is the default value if this keyword is not
specified.
EXPLANATION:
The specified boundary type is not supported. Only BOUNDARY_TYPE=IEEE_11491
and BOUNDARY_TYPE=IEEE_11496 are supported.
USER RESPONSE:
If the intent is to insert IEEE 1149.1 or IEEE 1149.6 compliant Boundary Scan logic,
change the value of the keyword BOUNDARY_TYPE to the supported value IEEE_11491
or IEEE_11496 and rerun.
ERROR (TSY-049): Since there are ports in the input IOSpecList, the technology library for
the iocells on these ports must be specified using the synlibs keyword.
EXPLANATION:
Presence of ports in an input IOSpecList requires specification of synlibs.
USER RESPONSE:
If ports are present in the netlist, specify synlibs and rerun.
ERROR (TSY-050): Unable to determine technology library libfile in library.

EXPLANATION:
The program cannot find the referenced library file in the referenced library.
USER RESPONSE:

Ensure the correct library file and library are specified and rerun.

ERROR (TSY-051): Unable to locate the SRULE for a generic IO cell in the installation path.
EXPLANATION:
The program cannot find a required SRULE for a generic IO cell.
USER RESPONSE:
Ensure the SRULE is in the installation path and rerun.
ERROR (TSY-052): Directory, directory does not exist. Ensure the directory exists and
is writable and rerun this command.
EXPLANATION:
The referenced directory does not exist.
USER RESPONSE:
Ensure the directory exists and is writable and rerun this command.
ERROR (TSY-053): The instruction instruction requires that a keyword be specified

with a value.
EXPLANATION:
The referenced JTAG instruction requires a legal keyword-value pair and a correct pair
has not been entered.
USER RESPONSE:
Ensure that a legal keyword-value pair has been entered for the specified JTAG
instruction and rerun the command. Refer to the Customer-Specific User Guide.
ERROR (TSY-054): The instruction instruction requires that a keyword be specified

and one is missing.
EXPLANATION:
The referenced JTAG instruction requires requires the referenced keyword which has not
been specified.
USER RESPONSE:

Specify the referenced keyword and rerun the command.
ERROR (TSY-055): The cell name cellname specified in the IOSpecList is not present in
the technology libraries specified to the command. Ensure the technology library for the
specified cell is provided and rerun this command.
EXPLANATION:
The referenced cell does not exist in the technology libraries that have been specified to
the command.
USER RESPONSE:
Ensure that the cell is present in the technology libraries and rerun the command.
ERROR (TSY-056): Unable to identify and/or understand iocell on tapporttype TAP port
portname. The iocell for a TAP port is essential for the Boundary Scan logic to be inserted
correctly. Refer to preceding messages for more details.
EXPLANATION:
Preceding warnings have been generated regarding iocell identification for the specified
TAP port. Without an iocell for a TAP port, the boundary scan connections will be
incomplete.
USER RESPONSE:
Address the preceding warning messages in order for the TAP ports to be processed
correctly and rerun.
ERROR (TSY-057): tapporttype TAP port portname does not have an iocell
connected to it in the design. The iocell to be connected to the TAP port must be specified on
the CELL keyword in the input IOSpecList.
EXPLANATION:
The iocell to be instantiated in the design for a TAP port must be specified in the input
IOSpecList.
USER RESPONSE:
Use the CELL keyword in the IOSpeclList to specify the iocell to use for the TAP port and
rerun.
ERROR (TSY-058): Port portname has an unsupported trailing character char in its
name. Remove this unsupported character and rerun this command.
EXPLANATION:

The executed detects errors if the names of the TAP ports and the scanin and scanout
ports specified with the command string have any trailing characters on them like
hyphens (-) and plus signs (+). Such trailing characters are only allowed on command
options like testenables, scanenables, testclocks, and so on.
USER RESPONSE:
Remove the specified unsupported character and rerun the command.
ERROR (TSY-059): TAP port of type tapporttype does not exist either on the design or
in the input information. TAP information must be provided since identifying an appropriate
iocell for the TAP ports is currently not supported.
EXPLANATION:
If a TAP port is not present in the design or has not been specified through the inputs
(command string or IOSpecList), then Boundary Scan connections will be incomplete
since there is no way of knowing which iocell to use for that port. Therefore, the TAP port
name and corresponding iocell to be instantiated in the design must be specified in the
input IOSpecList.
USER RESPONSE:
Specify the TAP port information in the input IOSpecList and rerun the command.
ERROR (TSY-060): Port portname has been specified as a TAP port of type
tapporttype but has an incorrect iocell type of iocelltype. This TAP port must have
iocelltype iocell on it.
EXPLANATION:
TAP ports must have a specific type of iocell on them. A TDO TAP port must have a tri-
state iocell on it, whereas the other TAP ports must have iocells capable of input mode.
USER RESPONSE:
Use the correct iocell on the specified TAP port and rerun the command.
ERROR (TSY-061): Port portname connects to non-PAD pin pinname on the iocell.
Ensure the iocell PAD pin has the is_pad=true attribute on it in the liberty file. TAP ports
must be connected properly to iocells. Processing will terminate
EXPLANATION:
TAP ports must be connected properly to iocells.
USER RESPONSE:

ERROR (TSY-062): Unable to determine the name of the iocell connected to TAP port
portname on the design. Processing will terminate.
EXPLANATION:
The specified TAP port has an IOcell associated with it, but the cell name is
unrecognized.
USER RESPONSE:
ERROR (TSY-063): Processing terminates since ports have been flagged as being ignored
for boundary scan processing. The number of flagged ports is numports. Refer to Table 2
and to preceding warnings indicating the reason why these ports have been flagged. Either
add these ports must be added to the excludeports option or they have the
bdy_use=none keyword specified or the design error must be corrected.
EXPLANATION:
One or more ports have associated Warnings that cause these ports to be ignored during
boundary scan processing.
USER RESPONSE:
If the intent is to ignore these ports during boundary scan, specify the bdy_use=none
keyword on them or specify these ports with the excludeports command option and
rerun.
ERROR (TSY-064): The name section has not been properly closed. It must be opened with
the start string and closed with the end string. Processing will terminate.
EXPLANATION:
The JTAG_INLINE string was not closed in the IOSpecList.
USER RESPONSE:
Enter the JTAG_INLINE string on its own line on the last line of the JTAG_INLINE
section and then rerun.
ERROR (TSY-100): command script generation aborted with errors.

EXPLANATION:
This message Indicates that generation of the BuildGates or RTL Compiler script by
Encounter Test Synthesis terminated with major errors.
USER RESPONSE:

Examine the error messages issued by Encounter Test Synthesis and respond
accordingly.
ERROR (TSY-101): [Internal] command script generation terminated with programming

error messages.
EXPLANATION:
This script generation state of the program terminated due to programming errors.
USER RESPONSE:
ERROR (TSY-102): Encounter Test Synthesis processing aborted with major errors.
EXPLANATION:
The Encounter Test Synthesis processing required by the command terminated with
major errors.
USER RESPONSE:
accordingly.
ERROR (TSY-103): [Internal] Encounter Test Synthesis processing terminated with

programming error messages
EXPLANATION:
The Encounter Test Synthesis processing required by the command terminated with
programming errors.
USER RESPONSE:
accordingly.
ERROR (TSY-104): command script generation aborted with errors. Correct the errors
identified in file filename and rerun.
EXPLANATION:

The generation of the BuildGates or RTL Compiler script by Encounter Test Synthesis
terminated with major errors.
USER RESPONSE:
accordingly.
ERROR (TSY-105): [Internal] command script generation terminated with programming

error messages. Contact Cadence Customer Support and provide the information in
filename.
EXPLANATION:
The generation of the script by Encounter Test Synthesis terminated with programming
errors.
USER RESPONSE:
Contact the customer support team using your normal process; Cadence Online
Customer Support, email, or direct call to the customer support line, and provide the
complete text of the message. This will allow the programmer to find and fix the problem
more quickly.

ERROR (TSY-200): Could not establish the directory path.
EXPLANATION:
The program was unable to establish the fully qualified location of the specified path.
USER RESPONSE:
Ensure the directory structure and specified path names are properly set up and rerun.
ERROR (TSY-201): Port port_name with sys_use=sys_use_value has a wrong

cell=cell_type_value (cell type is cell_type).
EXPLANATION:
The wrong cell is specified for this port in the IOSpecList and causes program
termination.
USER RESPONSE:

Check the cell from the library, ensure the selected cell is correct for the port with
sys_use and then rerun.
ERROR (TSY-202): Port port_name with sys_use=sys_use_value has a wrong

cell=cell_type_value (cell type is cell_type).
EXPLANATION:
The wrong cell is specified for this port in the IOSpecList and caused an abnormal
termination.
USER RESPONSE:
Check the cell from the library. Ensure the selected cell is correct for the port with
sys_use and then rerun.
ERROR (TSY-203): Port port_name with test_use=test_use_value does not have

a test_in or core_test_in keyword.
EXPLANATION:
Either the test_in or core_test_in keyword is required for a port with the specified
test_use value.
USER RESPONSE:
Add test_in or core_test_in to the IOSpecList and rerun.
ERROR (TSY-204): Port port_name with test_use=test_use_value does not have

a test_out or core_test_out keyword.
EXPLANATION:
Either the test_put or core_test_out keyword is required for a port with the
specified value for test_use.
USER RESPONSE:
Add test_out or core_test_put to the IOSpecList and rerun.
ERROR (TSY-205): Port port_name with sys_use=sys_use_value should not have

sys_out or sys_enable keyword.
EXPLANATION:
The keywords sys_out or sys_enable cannot be specified for a port with the
referenced sys_use value.
USER RESPONSE:

Remove or change the speciified value for sys_use, sys_out, or sys_enable and
rerun.

sys_out or sys_enable keyword.
EXPLANATION:
The keywords sys_out or sys_enable cannot be specified for a port with the specified
sys_use value.
USER RESPONSE:
Remove or change the speciified value for sys_use, sys_out, or sys_enable and
rerun.

the sys_in keyword.
EXPLANATION:
The keyword sys_in cannot be specified for a port with the specified sys_use value.
USER RESPONSE:
Remove or change the speciified value for sys_use or sys_in and rerun.
ERROR (TSY-208): Port port_name with sys_use=sys_use_value is missing the

sys_enable keyword.
EXPLANATION:
The keyword sys_enable must be specified with the specified sys_use value.
USER RESPONSE:
Specify the keyword sys_use and and rerun.
ERROR (TSY-209): When HIGHZ=YES, port port_name must have a tri-state output
iocell.
EXPLANATION:
The cell selected in the IOSpecList does not satisfy the requirement of the port during
HIGHZ mode.
USER RESPONSE:
Select a tri-state output iocell for this port and rerun.

ERROR (TSY-210): When IOWRAP=YES, functional port port_name must have a BIDIR
iocell.
EXPLANATION:
The cell selected in the IOSpecList does not satisfy the requirement of the port during
IOWRAP mode.
USER RESPONSE:
Specify a BIDIR output iocell for this port and rerun.
ERROR (TSY-211): A test_use must be specified for test port port_name.

EXPLANATION:
The test port must have test_use specified in the IOSpecList.
USER RESPONSE:
Specify the test_use keyword in the IOSpecList and rerun.
ERROR (TSY-212): Port port_name is shared and therefore requires specification of the
cell keyword.
EXPLANATION:
A sharing port must have a cell keyword to enable proper processing.
USER RESPONSE:
Specify the cell keyword and rerun.
ERROR (TSY-213): The IOSpecList has invalid ports, build_top_shell terminates.

EXPLANATION:
The IOSpecList contains incorrectly specified information that caused abnormal
termination.
USER RESPONSE:
Correct the IOSpecList and rerun. Refer to the Customer-Specific User Guide.
ERROR (TSY-214): Could not find iocell cell in the loaded libraries. The cell cell was
requested to be inserted on port port_name. Check the spelling and verify all the library
files have been specified.
EXPLANATION:

The program did not detect the specified IOSpecList cell in the loaded library.
USER RESPONSE:
Reload the library with the cell in it or change the cell in the IOSpecList and then rerun.
ERROR (TSY-215): Cannot find port with test_use=TE comp_enab=0 to distribute to SIO
cells.
EXPLANATION:
A test enable signal is required to distribute to SIO cells.
USER RESPONSE:
Specify test_se=TE to one port so it can be used as the test enable signal and then
rerun.
ERROR (TSY-216): Cannot find port with test_use =TE comp_enab=0 to distribute to
SIO cells.
EXPLANATION:
A test enable signal is required to distribute to SIO cells.
USER RESPONSE:
Specify test_se=TE to one port so it can be used as the test enable signal and then
rerun.
ERROR (TSY-217): IOcell is not found to insert sharing logic for port port_name.
EXPLANATION:
The IO cell is required in order to connect with sharing logic.
USER RESPONSE:
Ensure the cell keyword is specified for the port and rerun.
ERROR (TSY-218): The SIO instance sio_instance for port port_name is already
created for another port. Resolve the port name conflict in the IOSpecList and rerun.
EXPLANATION:
The SIO instance was created with the same name during in a previous step. Duplicate
SIO names are not allowed. An example of such a conflict is where one port is
portA[0] and another port is portA_0_.
USER RESPONSE:

Change the port name to eliminate the name conflict and rerun.
ERROR (TSY-219): Cannot find an SE signal to distribute to SIO macro sio_instance.

It is required to have a port with keyword values test_use=SE comp_enab=0 so the scan
enable signal can be identified and connected to the SE pin of the share IO macros.
EXPLANATION:
The program cannot find an SE signal; this is a program error.
USER RESPONSE:
Define an SE signal in the IOSpecList by specifying test_use=SE for a port and then
rerun.
ERROR (TSY-220): Cannot find a TE signal to distribute to sio macro sio_instance.

EXPLANATION:
The program cannot detect a TE signal; this is a program error.
USER RESPONSE:
Define an TE signal in the IOSpecList by specifying test_use=TE for a port and then
rerun.
ERROR (TSY-221): Unable to determine Encounter Test installation directory. Processing

will terminate.
EXPLANATION:
The program cannot detect the installation directory referenced by the environment
variable Install_Dir..
USER RESPONSE:
Contact the system administrator to verify the location of the install directory. If there is
no problem with the installlation, then contact customer support (see Contacting
ERROR (TSY-222): Unable to make the connection to test_in_hookup pin

test_in_hookup. Contact customer support.
EXPLANATION:
The program cannot make the right connection to the hook-up pin. This is likely a
program error.
USER RESPONSE:

direct call to the customer support line. Refer to Contacting Customer Service on
page 23. Provide the information in the specified file to allow the programmer to find and
fix the problem more quickly.
ERROR (TSY-223): There are multiple instances defined for one core module in the
connection file. This is not allowed.
EXPLANATION:
The core can only have one instance defined in the connection file.
USER RESPONSE:
Modify the connection file to ensure one instance is defined per core module and rerun.
ERROR (TSY-224): Connection file signal connection_signal is specified as a multi-

source net.
EXPLANATION:
A multisource net is specified in the connection file.
USER RESPONSE:
Remove the multiple sources for the signal in the connection file and then rerun.
ERROR (TSY-225): Connection file signal connection_signalshould be connecting to

pins which are all bidirectional.
EXPLANATION:
If one pin connected to the signal is bidirectional, then all the other pins should be
bidirectional.
USER RESPONSE:
Change all the pins connected to the signal to be bidirectional in the connection file and
rerun.
ERROR (TSY-226): Cannot find PAD pin of cell cell_name. Use the IOCELL_PAD global
keyword in the IOSpecList or set dft_pin_function=IO_PAD in the premodel attribute
file..
EXPLANATION:
The global keyword IOCELL_PAD is required if the library does not contain the attribute
for the program to identify the pin and neither the pin is attributed in the premodel
attribute file.

USER RESPONSE:
Add the global keyword IOCELL_PAD or set dft_pin_function attribute to IO_PAD
for the pin in the premodel attribute file and rerun.
ERROR (TSY-227): Cannot find output pin of cell cell_name, Use the IOCELL_OUTPUT
global keyword in the IOSpecList.
EXPLANATION:
A global keyword is required If the library does not contain the attribute for the program
to identify the pin.
USER RESPONSE:
Add the global keyword to the IOSpecList and rerun.
ERROR (TSY-227): Cannot find output pin of cell cell_name, Use the IOCELL_OUTPUT
EXPLANATION:
USER RESPONSE:
ERROR (TSY-228): Cannot find input pin of cell cell_name. Use the IOCELL_INPUT
EXPLANATION:
USER RESPONSE:
ERROR (TSY-229): Cannot find enable pin of cell cell_name. Use the IOCELL_ENABLE
EXPLANATION:
to identify the pin..
USER RESPONSE:

ERROR (TSY-230): Cannot obtain port type for port port_name.

EXPLANATION:
The port type must be identified in order to create the port.
USER RESPONSE:
Ensure the the cell, sys_use, test_use keywords correctly identify the port type in
the IOSpecList and rerun.
ERROR (TSY-231): Cell type cannot be identified for cell=cell_name port=port_name.

Ensure the cell in the library has proper attributes.
EXPLANATION:
The cell type cannot be identified for the referenced cell. The cell type is is required in
order to create a port with correct type.
USER RESPONSE:
Ensure the cell in the library has proper attributes and rerun.
ERROR (TSY-232): Cell is not specified for port port_name. Unable to determine the port
type.
EXPLANATION:
A cell must be specified in order for the program to determine the port type before
creating the port.
USER RESPONSE:
Add the cell keyword to the IOSpecList and rerun.
ERROR (TSY-233): Cannot find the PADN pin on iocell master_cell for differential port
port_name. Use the IOCELL_PADN global keyword in the IOSpecList.
EXPLANATION:
USER RESPONSE:

ERROR (TSY-234): Bus port_name_only has been created with direction of

direction. The inferred port type port_type for port port_name does not match with
the existing bus. The bus might have strands specified with a different direction.
EXPLANATION:
A bus must have strands with same direction specified.
USER RESPONSE:
Correct the bus and rerun.
ERROR (TSY-235): The iocell instance iocell_instance for port port_name is

already created for another port. Check for a port conflict in the IOSpecList.
EXPLANATION:
An iocell instance was created with the same name during in a previous step. Duplicate
iocell instance names are not allowed. An example of such a conflict is where one port
is portA[0] and anothe port is portA_0_.
USER RESPONSE:
Change the port name to eliminate the name conflict and rerun.
ERROR (TSY-236): Cannot find the PAD pin on iocell cell_name.

EXPLANATION:
The program was unable to identify the PAD pin on the iocell.
USER RESPONSE:
Verify the library attributes or add the IOCELL_PAD global keyword and then rerun.
ERROR (TSY-237): Enable signal core_enable cannot be found.

EXPLANATION:
The program was unable to identify the full path to the referenced pin.
USER RESPONSE:
Verify the library attributes or add the IOCELL_ENABLE global keyword and then rerun.
ERROR (TSY-238): When SCANIO=BIDI, scan in port port_name must have a BIDIR
iocell.
EXPLANATION:

The scan-in port must be bi-directional for this type of compression.

USER RESPONSE:
Ensure the the iocell for this port is correctly specified and rerun.
ERROR (TSY-239): When SCANIO=BIDI, scan in port port_name must have a BIDIR
iocell.
EXPLANATION:
The scan-out port must be bi-directional for this type of compression.
USER RESPONSE:
Ensure the the iocell for this port is correctly specified and rerun.
ERROR (TSY-240): Port port_name is missing sys_value keyword.

EXPLANATION:
The sys_in or sys_out value must be specified when certain sys_use values are
used. Default values for sys_in or sys_out is no longer supported.
USER RESPONSE:
Add the appropriate sys values and rerun.
ERROR (TSY-241): Processing terminates due to undetected tr_cell tr_cell for port
port_name in the loaded library.
EXPLANATION:
The tr_cell specified in the IOSpecList cannot be found in the library.
USER RESPONSE:
Ensure the tr_cell is correctly spelled in the library or the library containing the
tr_cell is loaded and then rerun.
ERROR (TSY-242): Processing terminates due to undetected TR_ZT pin on tr_cell

instance tr_inst for port port_name. Make sure the TR_ZT pin is properly attributed in
the premodelattr file.
EXPLANATION:
The TR_ZT pin on the test receiver cell to must be connected to the IO_ZJ pin on the
iocell cell.
USER RESPONSE:

Ensure the TR_ZT pin is properly attributed in the premodelattr file and then rerun.
ERROR (TSY-243): Processing terminates due to undetected IO_ZJ_INVERTED pin on

iocell instance cell_inst for port port_name. Make sure the IO_ZJ_INVERTED pin is
properly attributed in the premodelattr file.
EXPLANATION:
The IO_ZJ_INVERTED pin on the differential IO cell must be connected to the test
receiver.
USER RESPONSE:
Ensure the IO_ZJ_INVERTED pin is properly attributed in the premodelattr file and
then rerun.
ERROR (TSY-244): Processing terminates due to undetected IO_ZJ pin on iocell instance
cell_inst for port port_name. Make sure the IO_ZJ pin is properly attributed in the
premodelattr file.
EXPLANATION:
The IO_ZJ pin on the differential IO cell must be connected to the test receiver.
USER RESPONSE:
Ensure the IO_ZJ pin is properly attributed in the premodelattr file and then rerun.
ERROR (TSY-245): Cannot find SE signal to connect to iocell enable pin

iocell_enable_inst_pin of scan output port port_name. It is required to have a
port with keyword values test_use=SE comp_enab=0 so the scan enable signal can be
identified and connected to control the scan outputs.
EXPLANATION:
This Scan Output port is using a BIDIR or OUTPUT3 iocell. The enable pin on the iocell
cell must be controlled by the scan enable
USER RESPONSE:
Define an SE signal in the IOSpeclLst by adding test_use=SE comp_enab=0 for a port
in the IOSpeclLst and then rerun.
ERROR (TSY-246): Port port_name has differential=differential, but the

differential port differential does not exist in the IOSpecList data structure.
EXPLANATION:

Both elements of the differential port pair must appear in the IOSpecList. One of the pair
is missing from the IOSpecList.
USER RESPONSE:
Add the missing differential leg of the pair to the IOSpecList and rerun.
ERROR (TSY-247): The port port_name has sys_in=sys_in. The same

sys_in=sys_in is specified for other ports in the IOSpecList. This configuration will create
a multi-source signal and theerfore it is not allowed.
EXPLANATION:
The same sys_in value cannot be specified on multiple ports
USER RESPONSE:
Correct the values in the IOSpecList and rerun.
ERROR (TSY-249): The JTAG_TEST_CLOCK on the JTAG_MACRO must be preconnected

in the connections file or specified in the IOSpecList file with the keyword value
jtagtestclock=YES on a test clock with test_use=TCLK when TOP_MODULE_SCAN is
YES and the TAP TCK port port_name is shared or is a non-test location.
EXPLANATION:
When the global keyword TOP_MODULE_SCAN=YES is specified, this clock port will be
connected to the JTAG_TEST_CLOCK pin on the JTAG_MACRO and will be used to clock
the sequential logic within the JTAG_MACRO during the test modes. This allows a design
test clock to be used to scan the JTAG_MACRO during the test modes instead of using
TCK as a scan clock. TCK regains control of the JTAG_MACRO logic during the functional/
JTAG mode of operation.
USER RESPONSE:
Add the jtagtestclock keyword to the test_use=TCLK port and rerun.
ERROR (TSY-250): When IOWRAP=YES and TAPPIN_IOWRAP_ENABLE=YES are

specified, the TAP port port_name must have a BIDIR iocell to facilitate IOWRAP testing.
EXPLANATION:
The global TAPPIN_IOWRAP_ENABLE keyword will enable SIOM_TAPIN_NT to be
inserted for the TAP ports if they are not shared with test functions. This share IO macro
contains a flip-flop to enable the IOWrap testing. By default, no share IO macro will be
inserted for the TAP ports to be backward compatible with the previous behavior.
USER RESPONSE:

Add the global keyword TAPPIN_IOWRAP_ENABLE accordingly and rerun.
ERROR (TSY-251): The keyword tr_cell can only be specified to be shared on the
negative leg of the differential ports. It cannot be shared on the positive legs or on any other
type of ports. Port port_name has a wrong tr_cell value of tr_cell_value specified.
EXPLANATION:
The tr_cell keyword specification must conform to one of the following scenarios:
Scenario 1 TRCellName1 contains both positive and negatiive tr

cells. P_port_1 cell=IOCellName
tr_cell=TRCellName1 N_port_1 tr_cell=shared
Scenario 2 TRCellName2 contains both positive and negative tr
cells. P_port_2 cell=embedded
tr_cell=TRCellName2
N_port_2 tr_cell=shared
Scenario 3 Both positive and negative tr cells are embedded within
IOCellName. P_port_3 cell=IOCellName
tr_cell=embedded N_port_3 tr_cell=shared.
Scenario 4 Both positive and negative tr cells are embedded;
connections specified in connections file. The tr cells may
or may not be shared within a single technology cell
P_port_4 cell=embedded tr_cell=embedded
N_port_4 tr_cell=embedded.
USER RESPONSE:
Review the IOSpecList and ensure the tr_cell keyword specification conforms to one
of the scenarios, and then rerun.
ERROR (TSY-252): When a negative port port_name is specified with tr_cell=shared

and its positive leg is specified with tr_cell=embedded, the positive legs iocell must be a
valid technology cell. It cannot be embedded or NONE.
EXPLANATION:
When the differential negative leg has a tr_cell of shared and the positive leg has
tr_cell of embedded, the program assumes the iocell is a valid technology cell and all
the necessary tr cell pins are on the iocell with proper attributes. It is required to use

tr_cell of embedded for a negative leg if the iocell is also embedded. Refer to the
following supported scenarios.

cells. P_port_1 cell=IOCellName
tr_cell=TRCellName1
N_port_1 tr_cell=shared.
cells. P_port_2 cell=embedded
tr_cell=TRCellName2
N_port_2 tr_cell=shared.
Scenario 3 Both positive and negative tr cells are embedded within
IOCellName. P_port_3 cell=IOCellName
tr_cell=embedded N_port_3 tr_cell=shared.
Scenario 4 Both positive and negative tr cells are embedded;
connections specified in the connections file. The tr cells
may or may not be shared within a single technology cell.
P_port_4 cell=embedded tr_cell=embedded
N_port_4 tr_cell=embedded.
USER RESPONSE:
Review the IOSpecList and ensure the tr_cell keyword specification conforms to one
of the scenarios, and then rerun.
ERROR (TSY-253): Cannot find master trcell master_tr_cell for port port_name in
the loaded library. Ensure the tr_cell is loaded and rerun.
EXPLANATION:
The tr_cell library must be loaded in order for the instance to be created.
USER RESPONSE:
Ensure the tr_cell is in the loaded libraries and rerun.
ERROR (TSY-254): Cannot find port port_names sys_enable sys_enable declaration

in the IOSpecList. sys_enable sys_use=ENABLE is required in the IOSpecList. Add the
enable signal declaration into the IOSpecList and rerun.
EXPLANATION:
The enable signal must be separately declared in the IOSpecList.
USER RESPONSE:

Add the enable signal declaration into the IOSpecList and rerun.
ERROR (TSY-255): Unsupported configuration port port_names may not have both an
embedded boundary cell and an embedded iocell when the port is shared with a test function
test_use=test_use.
EXPLANATION:
In a typical mode without an embedded boundary scan cell, if the port is shared, the
program creates a shared IO macro and connects the iocell and boundary scan cell. The
scenario for an embedded boundary scan cell and an embedded iocell is not supported
when the port is shared for test.
USER RESPONSE:
Add the shared IO macro into the embedded macro and rerun.
ERROR (TSY-256): Port port_names is specified with sys_use of CLOCK and

test_use of test_use; test_use can only be one of tclk, tclkneg, sclk or
sclkneg.
EXPLANATION:
The test_use for the CLOCK pin is used for the tool to put the proper ATPG test flag to the
pin.
When test_use=SCLK/SCLKNEG is specified:
Pin is: Asynchronous set/reset, functional clock, or non-scanlatch clock
sys_in value (Required)
When test_use=TCLk/TCLKNEG is specified:
Pin is: Functional and Test clock
sys_in value (Required)
USER RESPONSE:
Correct the keywords for the CLOCK pin and rerun Build Top Shell.
ERROR (TSY-257): TAP Port port_name cannot be shared with a test clock with
test_use of test_use.
EXPLANATION:
A TAP pin cannot be shared with one of the following test_use options: tclk, tclkneg,
sclk, sclkneg, tclkasy or tclkasyneg.

USER RESPONSE:
Remove the sharing of the disallowed test_use value or replace with a supported
test_use option and rerun.
ERROR (TSY-258): When an 1149.6 input port or bidirectional port port_name has an
embedded boundary cell, its test receiver cell and IO cell must also be embedded as
indicated by the tr_cell=embedded and cell=embedded keywords in the same level of
the hierarchy.
EXPLANATION:
Some interconnections are beyond Build Top Shells capability if boundary cells are
embedded for an 1149.6 input or bidirectional port. Some examples are a trcell output to
the ACTR boundary cell and an analog input from the iocell to the tr_cell input.
USER RESPONSE:
Redesign the embeddedBC macro to include cell and tr_cell, make
interconnections within the macro, and then rerun.
ERROR (TSY-259): Cannot find instance bc_inst in the design. Ensure the instance is
specified in the connection file.
EXPLANATION:
The bc_inst value is specified in the IOSpecList pointing to the name of the macro
where a boundary cell is embedded. This macro has to be declared in the connection file
with its proper pin names, for example TDI, TDO, MODE_A,CLOCKDR, and so on so
the tool will automatically connect them.
USER RESPONSE:
Specify the bc_inst instance in the connection file and rerun.
ERROR (TSY-260): Cannot find tdo_pin=tdo_pin on instance bc_inst for

bc_segment bc_segment. Ensure this pin is specified in the connection file.
EXPLANATION:
The tdo_pin is specified in the IOSpecList, but it is not found in the design model. The
program constructs the logic for embedded boundary scan cells from the connection file
specification.
USER RESPONSE:
Ensure the instance and pin are specified in the connection file and then rerun.

ERROR (TSY-261): Cannot find a matching tdi_pin keyword for tdo_pin=tdo_pin on

instance bc_inst in the IOSpecList. Ensure the tdo_pin and tdi_pin are paired up in
the IOSpecList per the guidelines.
EXPLANATION:
The program collects the segment information based on the bc_inst, tdo_pin. and
tdi_pin keywords.
The following example shows that an embedded bc segment exists on a PRE_BC_BIDIR
instance. The segments head and tail are TDI_BIT0 and TDO_BIT0.
Note that the tdo_pin keyword has to be specified prior to the tdi_pin keyword for a
segment in the IOSpecList.
embedded_bidir_enable_net sys_use=ENABLE bc_inst=PRE_BC_BIDIR
tdo_pin=TDO_BIT0
DLX_CHIPTOP_DATA[0] bc_inst=PRE_BC_BIDIR
DLX_CHIPTOP_DATA[1] bc_inst=PRE_BC_BIDIR tdi_pin=TDI_BIT0
USER RESPONSE:
Review the IOSpecList and ensure the keywords are properly specified to identify the
segments and then rerun.
ERROR (TSY-262): Cannot find default tdo_pin TDO on instance bc_inst for
bc_segment bc_segment. When a tdo_pin and tdi_pin keyword pair are not specified
for a certain segment, the default pin names are TDO and TDI. Review the connection file and
ensure the pin name TDO is specified.
EXPLANATION:
If the tdo_pin and tdi_pin keywords are not explicitly specified for the embedded bc
segment, the program default is to search for a pin with the name TDI or TDO to be the
embedded bc chains head and tail. These two pins must be specified on the embedded
bc instance in the connection file as shown in the following example.
PRE_BC_IN: PRE_BC_IN_MOD port map (
TDI <= OPEN,
TDO => OPEN,
MODE_A <= OPEN,
SHIFTDR <= OPEN,
CLOCKDR <= OPEN,
RDI <= rdi_net,
RDO => I_CORE_READY_net
);
USER RESPONSE:
Review the connection file to ensure the pin exists and then rerun.

ERROR (TSY-263): Cannot find default tdi_pin TDI on instance bc_inst for
bc_segment bc_segment. When a tdo_pin and tdi_pin keyword pair are not specified
for a certain segment, the default pin names are TDO and TDI. Review the connection file to
ensure the pin name TDI is specified.
EXPLANATION:
If the tdo_pin and tdi_pin keywords are not explicitly specified for the embedded bc
segment, the program default is to search for a pin with the name TDI or TDO to be the
embedded bc chains head and tail. These two pins must be specified on the embedded
bc instance in the connection file as shown in the following example.
PRE_BC_IN: PRE_BC_IN_MOD port map (
TDI <= OPEN,
TDO => OPEN,
MODE_A <= OPEN,
SHIFTDR <= OPEN,
CLOCKDR <= OPEN,
RDI <= rdi_net,
RDO => I_CORE_READY_net
);
USER RESPONSE:
Review the connection file to ensure the pin exists and then rerun.
ERROR (TSY-264): OUTPUT3 or BIDIR Port port has an embedded data boundary cell.
Its enable boundary cell controlled by sys_enable must be embedded in the same block
as indicated by the same bc_inst keyword value.
EXPLANATION:
The data boundary cell and its enable boundary cell must both be embedded in the same
macro or both not embedded as shown in the following example.
Output3_Port sys_use=OUTPUT3 sys_out=dataout sys_enable=O_CORE_BIDIR_ENABLE
bc_inst=EMBEDDED_BC_MACRO
...
O_CORE_BIDIR_ENABLE bc_inst=EMBEDDED_BC_MACRO.
USER RESPONSE:
Review and correct the inconsistency of the data pin and enable signal in the IOSpecList
and then rerun.
ERROR (TSY-265): The tdi_pin keyword tdi_pin on port port is specified without the
corresponding tdo_pin specified before it. The program is unable to determine the head and
tail of a particular segment. Refer to the temporary IOSpecList
topmodule.speclist.bts.temp.
EXPLANATION:

The program failed to collect the head and tail pair for one particular segment. Mostly
likely the tdo_pin keyword is missing as in the following example.
embedded_bidir_enable_net sys_use=ENABLE bc_inst=PRE_BC_BIDIR
#tdo_pin=TDO_BIT0DLX_CHIPTOP_DATA[0] bc_inst=PRE_BC_BIDIR
DLX_CHIPTOP_DATA[1] bc_inst=PRE_BC_BIDIR tdi_pin=TDI_BIT0
USER RESPONSE:
Review the IOSpecList and ensure the keywords tdo_pin and tdi_pin both appear in
the right order and then rerun.
WARNING (TSY-266): Connection file signal con_signal is specified as a multi-source

net. The program will tolerate this illegal logic because the environment variable
DFTS_ALLOW_MULTISOURCE_NET is specified to be YES.
EXPLANATION:
A multi-source net is specified in the connection file. The setting for the environment
variable DFTS_ALLOW_MULTISOURCE_NET indicates that this illegal logic should be
tolerated.
USER RESPONSE:
Ensure the environment variable is specified as intended and rerun if necessary.

ERROR (TSY-300): Unable to obtain license.
EXPLANATION:
The program was unable to obtain the license required for Encounter Test Architect.
USER RESPONSE:
Ensure the availability of the necessary license and rerun.
WARNING (TSY-315): Memory element pinName is not in a scan chain and is corruptible
during the scan operation. The memory element may be clocked through
memoryElementName during the scan sequence scanSectionName.
EXPLANATION:
Note: If there are multiple scan sections then the scan section name appears in the
message test.

If there is only a single scan section, the scan section name is blank. If this is not the
design intent, correct and rerun.
If this is the design intent, then it violates design guidelines in that the non-scan memory
element may be clocked during the scan operation.
Guideline TG.8 - Section Scan State point 7 states that clocks to RAMs should be held
off and clocks to non-scan latches and flip-flops should be held stable. The clocks to
stable latches should be held to constant zero and the the clocks to flush latches should
be held to constant one.
The occurrence of this message generally indicates one or the other of two possible
problems:
The identified memory element is a latch that is part of an intended scan chain, but
this scan chain was not properly identified. One possible cause is that an SI test
function attribute is missing from the scan-in primary input pin.
The identified latch may be part of a scan chain, but this latch is neither controllable
nor measurable, due to having one or more clock inputs that are not at logic 0 in the
Test Inhibit and Clocks off state.
Intent
The intent of this check is to ease test generation and improve its performance by not
requiring simulation of the scan sequence.
USER RESPONSE:
Select the specific message from the Specific Message List. The block is displayed
and the pin with the incorrect value is identified by a unique color. The default is red.
The simulation state shown for the circuit is the scan state except the scan clocks
are at logic X.
Use the mouse pointer to verify the displayed block. The Information Window
Trace backward from the highlighted pin to identify the source of the incorrect
value. For more information, refer to Carries Clock in the "Encounter Test:
Reference: GUI"


memory element is meant to be scannable, then trace the scan path to see if it
is broken and in need of repair. If the scan path is unbroken then make certain
that it is correct for your design that this latch have a clock input which is not at
logic 0 in the Test Inhibit and Clocks off state.
ERROR (TSY-320): The insert_embedded_test command could not read file

file_name specified for keyword keyword.
EXPLANATION:
insert_embedded_test attempted to open the file listed, but was unable to. The
insert_embedded_test command will terminate.
USER RESPONSE:
Ensure the file exists and is readable, then rerun insert_embedded_test.
ERROR (TSY-360): Incorrect number of arguments have been specified for the proc
proc_name.
EXPLANATION:
The specified number of arguments for the proc is incorrect. The valid arguments for the
referenced proc are -statement and -line_number.
USER RESPONSE:
Correct the arguments to this proc and rerun.
ERROR (TSY-361): The option -statement is missing from the arguments for the proc
proc_name.
EXPLANATION:
This referenced proc requires that a connection file statement is specified as an
argument using the -statement option.
USER RESPONSE:
Specify a connection file statement as an argument for rhe referenced proc using the
-statement statement and rerun.
ERROR (TSY-362): The option -line_number is missing from the arguments to the proc
proc_name.
EXPLANATION:

This referenced proc requires that the line number for the connection file statement is
specified as an argument using the -line_number option.
USER RESPONSE:
Specify the line number of the connection file statement as an argument for the
referenced proc using the -line_number option and rerun.
ERROR (TSY-363): Incorrect number of arguments specified for the command

::confile::read_confile.
EXPLANATION:
Thespecified number of arguments for ::confile::read_confile is incorrect.
USER RESPONSE:
Correct the arguments specified for ::confile::read_confile and rerun. Use
::confile::read_confile with the -h option for help on its usage.
ERROR (TSY-364): The file filename specified as an argument for

::confile::read_confile does not exist.
EXPLANATION:
The file specified as one of the arguments for ::confile::read_confile does not
exist.
USER RESPONSE:
Specify an existing file as the argument for ::confile::read_confile and rerun.
ERROR (TSY-365): The IOcell on the TDO TAP port must be either BIDIR or OUTPUT3.
EXPLANATION:
The IOcell on the TDO TAP port must be either BIDIR or OUTPUT3.
USER RESPONSE:
Specify a BIDIR or OUTPUT3 iocell on the TDO TAP port in the IOSpecList, and then
rerun.
ERROR (TSY-366): An IOcell has not been found on the TDO TAP port. One must exist and
must be either BIDIR or OUTPUT3.
EXPLANATION:
There must be either a BIDIR or OUTPUT3 IOcell on the TDO TAP port.

USER RESPONSE:
Specify a BIDIR or OUTPUT3 iocell on the TDO TAP port in the IOSpecList, and then
rerun.
ERROR (TSY-367): Unable to determine the polarity of the enable pin on iocell iocell on
port port.
EXPLANATION:
The program is unable to determine the polarity of the enable pin on an iocell.
USER RESPONSE:
Use the IOSpecList keyword iocell_enable to specify the polarity of the enable pin
on BIDIR or OUTPUT3 cells Prefix the keyword value with the ! character to specify
active low logic.
ERROR (TSY-368): Enable elem has polarity polarity for a previous port. It cannot
have polarity tmp_polarity for port port. Ensure that all the ports controlled by enable
elem2 have the same enable polarity.
EXPLANATION:
All ports controlled by the enable port have the same enable polarity.
USER RESPONSE:
Ensure that all ports controlled by the enable port have the same enable polarity nd then
rerun.
ERROR (TSY-369): Unable to determine hookup pin for pinname pin on the JTAG_MACRO.
EXPLANATION:
The specified pin on the JTAG_MACRO must be connected to a top level port. Either the
top level port does not have an iocell, or it is a complex iocell whose pins must be defined
in the IOSpecList using the IOCELL_INPUT, IOCELL_OUTPUT, (and so on) keywords.
USER RESPONSE:
Ensure that the top level port exists, has an iocell on it, that the iocell is understood by
the command, and then rerun.
ERROR (TSY-370): Port port_name in the IOSpecList has the keyword keyword, but
does not have condition. Cannot make connection to the pinname pin on the
JTAG_MACRO.
EXPLANATION:

The specified pin on the JTAG_MACRO must be connected to a top level port. Although
the top level port has the specified keyword, it also must satisfy the specified condition.
The connection will not be made because the condition is not satisfied.
USER RESPONSE:
Ensure that the top level port exists, has the specified keyword. and satisfies the
specified condition; then rerun.
ERROR (TSY-371): Port port_name in the IOSpecList has the keyword keyword, but
does not have condition. Cannot make connection to the pinname pin on the
JTAG_MACRO.
EXPLANATION:
The specified pin on the JTAG_MACRO must be connected to a top level port. Although
the top level port has the specified keyword, it also must satisfy the specified condition.
The connection will not be made because the condition is not satisfied.
USER RESPONSE:
Ensure that the top level port exists, has the specified keyword. and satisfies the
specified condition; then rerun.
ERROR (TSY-372): Unable to determine core side iocell hookup pin for port port_name
that needs to be connected to the pin pinname on the JTAG_MACRO. JTAG_MACRO I/O
connections will be incomplete.
EXPLANATION:
The specified pin on the JTAG_MACRO must be connected to the referenced port name.
Either the top level port does not have an iocell, or it is a complex iocell whose pins must
be defined in the IOSpecList using the IOCELL_INPUT, IOCELL_OUTPUT, (and so on)
keywords.
USER RESPONSE:
Ensure that the top level port has an iocell on it, that the iocell is understood by the
command, and then rerun.
ERROR (TSY-373): Could not locate port port_name on the design. Without this port,
unable to determine hookup pin for pinname pin on the JTAG_MACRO.
EXPLANATION:
The specified pin on the JTAG_MACRO must be connected to the referenced top level
port. The connection is not made because no port exists in the IOSpecList.

USER RESPONSE:
Ensure that the port exists in the IOSpecList for the connection to be made and then
rerun.
ERROR (TSY-374): Unable to determine core side iocell_pin_type pin for

tap_port_type TAP port port_name that needs to be connected to the pin pinname
on the JTAG_MACRO. TAP I/O connections will be incomplete
EXPLANATION:
The specified pin on the JTAG_MACRO must be connected to the specified
iocell_pin_type on the TAP port. The command is unable to trace through the
design and identify the correct pin on the iocell. A possible cause is that the iocell is not
present in the design or it is a complex iocell whose pins must be identified using the
IOCELL_INPUT, IOCELL_OUTPUT (an so on) global keywords in the IOSpecList.
USER RESPONSE:
Ensure that the iocell exists in the design and its pins are specified in the IOSpecList if
necessary and then rerun.
ERROR (TSY-375): A mandatory pin pinname was not found on the JTAG_MODULE
instance.
EXPLANATION:
The specified pin must be present on every JTAG_MACRO used/recognized by this
command. This pin will be present on the JTAG_MACRO inserted by the command and
also must be present on a pre-instantiated JTAG_MACRO. The pin is missing from the
specified JTAG_MACRO instance. Refer to the Customer-Specific User Guide for the
list of pins on the JTAG_MACRO that the command expects to find.
USER RESPONSE:
Ensure that the pin exists on the JTAG_MACRO and rerun the command.
ERROR (TSY-376): Pin pinname on JTAG_MACRO instance instance does not exist on
the actual module definition of the JTAG_MACRO. The instance cannot have more pins than
the actual module.
EXPLANATION:
The specified pin must be present on the actual module statement of the JTAG_MACRO
as well, otherwise there will be a pin mismatch between the module definition and its
instantiation.
USER RESPONSE:

Ensure that the correct pins are present on the JTAG_MACRO instantiation and rerun the
command.
ERROR (TSY-377): A mandatory pin pinname was not found on the boundary cell
cell_name.
EXPLANATION:
The specified pin must be present on the specified boundary cell. Refer to the
Customer-Specific User Guide for a list of pins that need to be present on the
specified boundary cell. Note that the boundary cell can have more pins on it than
needed.
USER RESPONSE:
Update the verilog for the boundary cell to ensure that the pin exists on the boundary cell
and then rerun.
ERROR (TSY-378): There was an error while elaborating the boundary cell cell_name.
EXPLANATION:
Errors were encountered while loading the specified boundary cell. Refer to previous
messages in the log to see the error messages.
USER RESPONSE:
If needed, fix the errors by updating the Verilog for the boundary cell and rerun the
command.
ERROR (TSY-379): Processing terminates since the program is unable to locate the Verilog
file for the boundary cell cell_name in the custom boundary cell directory.
EXPLANATION:
The specified boundary cell could not be located in the custom boundary cell directory.
USER RESPONSE:
Ensure the Verilog file for the boundary cell is present in the custom boundary cell
directory and then rerun.
ERROR (TSY-380): Processing terminates since dedicated test port port_name does not
have a compliance enable value. The COMPLIANCE_PATTERNS attribute in the generated
BSDL file may be incorrect.
EXPLANATION:

The specified port is a dedicated test port and therefore must have a compliance enable
value specified for it so that the value can be put in the BSDL file.
USER RESPONSE:
Add the compliance enable value to the port in the IOSpecList and rerun the command.
ERROR (TSY-381): When IOWRAP=YES, there must be a port with test_use=EXTEST and
it must have comp_enab=0.
EXPLANATION:
For Reduced Pin Count Test (RPCT) there must be a port in the IOSpecList that has
test_use=EXTEST and this port must have comp_enab=0.
USER RESPONSE:
Ensure a port exists in the IOSpecList with with test_use=EXTEST and comp_enab=0.
ERROR (TSY-382): The user-specified value cmdline_topmodule for the command

option module does not match the value iospec_topmodule of the global keyword
TOP_MODULE_NAME in the IOSpecList. Rerun this command after resolving this mismatch.
EXPLANATION:
There is a mismatch between the top module name specified on the command line and
the specified top module in the IOSpecList.
USER RESPONSE:
Ensure the same topmodule is used and rerun this command.
ERROR (TSY-383): Unable to locate module topmodule within the loaded design. Ensure
the correct module name has been passed to the command.
EXPLANATION:
The specified top level module name does not exist in the loaded netlist
USER RESPONSE:
Ensure the correct top module name is used and rerun this command.
ERROR (TSY-384): Neither the EDO nor EDON pin was not found on the custom enable
boundary cell cell.
EXPLANATION:
One of the two output enable pins EDO and EDON is required on the custom boundary
cell. Ensure the polarity of this pin is consistent with the iocell enable polarity.

USER RESPONSE:
Ensure the proper enable pin is added to the custom enable boundary cell and then
rerun.
ERROR (TSY-385): The variable IMPLICIT_SI_MACRO_TEST_CONNECTIONS is set.

Macro Test net names (using keywords MT0_IN and MT1_IN) are not specified for every
Scan-In port. Remove the dft_signal_box_name pins connected to all Scan-In Macro
Test nets so that implicit SI MT insertion can take place.
EXPLANATION:
Macro Test net names have been specified for some but not all Scan-In test ports. No
dft_signal_box pins connected to these SI MT nets should be present for the implicit
SI Macro Test insertion to take place.
USER RESPONSE:
Remove these dft_signal_box pins conected to Scan-In Macro Test nets from the
connection file and then rerun.
ERROR (TSY-386): The variable IMPLICIT_SI_MACRO_TEST_CONNECTIONS is set.

Either specify dft_signal_box_name pins connected to all Scan-In Macro Test nets (the
Macro Test net names are specified by IOspeclist keywords MT0_IN and MT1_IN) or remove
all such dft_signal_box_name pins so that implicit SI MT insertion can take place.
EXPLANATION:
Some, but not all Scan-In Macro Test nets have been connected to the referenced
dft_signal_box pins in the conection file. They must be specified for all Scan-In
Macro Test nets.
USER RESPONSE:
Either remove the connections to these Scan-In Macro Test nets from the connection file
or specify connections to all the Macro Test nets for Scan-In ports and then rerun.
ERROR (TSY-387): The variable IMPLICIT_SI_MACRO_TEST_CONNECTIONS is set. The

connection file dft_signal_box_name pins connected to Scan-Input Macro Test nets
are not in order. These should start from start_pin and should be in order from 00, 01, 02 to
nn.
EXPLANATION:
The referenced dft_signal_box pins that are connected to Scan-In Macro Test nets
are not in order.
USER RESPONSE:

Either specify all the dft_signal_box pins connected to Scan-In Macro Test nets in
order or remove all these pins connected to Scan-In Macro Test nets and then rerun.
ERROR (TSY-388): The variable IMPLICIT_SI_MACRO_TEST_CONNECTIONS is set,

however the global keyword/environment variable DFT_SIGNAL_BOX_NAME is not defined.
EXPLANATION:
DFT_SIGNAL_BOX_NAME must also be specified when the global keyword/environment
variable IMPLICIT_SI_MACRO_TEST_CONNECTIONS is set,
USER RESPONSE:
Either specify the value for DFT_SIGNAL_BOX_NAME environment variable or the
IOSpeclist global keyword and then rerun
ERROR (TSY-389): The variable IMPLICIT_SI_MACRO_TEST_CONNECTIONS is set. The

connection file dft_signal_box_name pin pin_name is connected to a signal that is
not a Scan-Input Macro Test net. Rename this pin to be greater than max_pin_name or
remove this pin.
EXPLANATION:
The referenced pin already exists on the referenced dft_signal_box. This pin must
be connected to a Scan-In Macro Test net because pins from CE0_MTIN_00/
CE1_MTIN_00 to CE0_MTIN_nn/CE1_MTIN_nn (where nn is the number of Scan-In
ports) must be connected to Scan-In Macro Test nets.
USER RESPONSE:
Either rename this pin greater than CE0_MTIN_nn/CE1_MTIN_nn or remove this pin
and then rerun.
Either specify the value for DFT_SIGNAL_BOX_NAME environment variable or the
IOSpeclist global keyword and then rerun
WARNING (TSY-390): Some ports on which tdi_index is specified which will not exactly
match and will be relatively placed.
EXPLANATION:
The program places the BSRs relative to their tdi_index in situtations where the
tdi_index cannot be exactly honored.
USER RESPONSE:

No response is required if this condition is intentional. If it is not intentional, review the

the maximum tdi_index warnings and/or dummy_bsr positions, ensure they are
correctly specified, and then rerun.

WARNING (TSY-400): command completed with warning level messages.
EXPLANATION:
The referenced command completed with WARNING level messages.
USER RESPONSE:
Examine the warning level messages issued by Encounter Test Synthesis and respond
accordingly.
ERROR (TSY-401): command completed with error messages.

EXPLANATION:
The Encounter Test Synthesis processing required by the command issued error
messages.
USER RESPONSE:
accordingly.
WARNING (TSY-402): [Severe] command completed with severe warning messages.

EXPLANATION:
The Encounter Test Synthesis processing required by the command issued severe level
warning messages.
USER RESPONSE:
Examine the WARNING [Severe] messages issued by Encounter Test Synthesis and
respond accordingly.
WARNING (TSY-403): command_name processing completed with warning level

messages. Review the preceding messages.
EXPLANATION:
Warnings have occurred during the execution of the command. Netlist generation may
have been unsuccessful or incomplete.

USER RESPONSE:
Examine the warning messages and respond accordingly.
WARNING (TSY-404): Encounter Test Synthesis processing completed with warning level
messages.
EXPLANATION:
The Encounter Test Synthesis processing required by the command issued warning level
messages.
USER RESPONSE:
accordingly.
WARNING (TSY-405): Encounter Test Synthesis processing completed with error

messages.
EXPLANATION:
The Encounter Test Synthesis processing required by the command issued error
messages.
USER RESPONSE:
accordingly.
WARNING (TSY-406): [Severe] Encounter Test Synthesis processing completed with

severe error messages.
EXPLANATION:
The Encounter Test Synthesis processing required by the command issued severe level
error messages.
USER RESPONSE:
accordingly.
ERROR (TSY-407): command processing completed with error messages. Review the
messages.
EXPLANATION:

Errors have occurred during the execution of the command. Netlist generation may have
been unsuccessful or incomplete.
USER RESPONSE:
Examine the error messages and respond accordingly.
WARNING (TSY-408): Port port_name appears to be an direction port, expecting an

direction port. Skipping this port.
EXPLANATION:
The port direction defined in the IOSpecList does not match the netlist.
USER RESPONSE:
Correct the IOSpecList definition for this port and rerun if necessary.
WARNING (TSY-410): Global Data will not be written. File filename was not found.
EXPLANATION:
A file required for the determination of data to be written to global data could not be
located. No global data will be written by this command.
USER RESPONSE:
Examine preceding messages and attempt to resolve. If unsuccessful, contact
Encounter Test Customer Support (see Contacting Customer Service on page 23).
WARNING (TSY-411): Global Data will not be written. Could not establish topname.
EXPLANATION:
The value for topname is obtained from .globalData.dft. However, there was a
USER RESPONSE:
Examine preceding messages and attempt to resolve. If unsuccessful, contact
Encounter Test Customer Support (see Contacting Customer Service on page 23).
WARNING (TSY-412): Global Data will not be written. Could not establish output netlistfile.
EXPLANATION:
The value for the netlistfile is obtained from .globalData.dft. However, there was a
USER RESPONSE:

accordingly. If the problem remains unresolved, contact Encounter Test Customer
WARNING (TSY-413): command script generation completed with warning level

EXPLANATION:
The generation of the BuildGates or RTL Compiler script by Encounter Test Synthesis
issued warning level messages.
USER RESPONSE:
accordingly. If the problem remains unresolved, contact Encounter Test Customer
WARNING (TSY-414): [Severe] command script generation completed with severe

warning messages. Consult filename for more information.
EXPLANATION:
Severe warnings have occurred during the generation of the BuildGates or RTL Compiler
script.
USER RESPONSE:
Examine the messages issued by Encounter Test Synthesis and respond accordingly. If
the problem remains unresolved, contact Encounter Test Customer Support (see
WARNING (TSY-415): When outformat is not verilog, techmap=rc is not supported,

switching techmap to yes.
EXPLANATION:
Only verilog output is supported with RTL Compiler.
USER RESPONSE:
WARNING (TSY-416): The numchannels keyword is not divisible by numchains, the

FULLSCAN mode scan chains will not be balanced.
EXPLANATION:

For balanced FULLSCAN scan chains, the specified value for the numchannels keyword
must be divisible by the specified value for the numchains keyword when an XOR
Compression macro is used.
USER RESPONSE:
Modify the keyword values to make the numchannels value divisible by the numchains
value if FULLSCAN scan chains are required and rerun if necessary.
WARNING (TSY-417): The liboverride keyword is no longer supported when using RC

to build a top shell. Specify overrides for iocell pins in the input IOSpecList using the
IOCELL_* global keywords. The liboverride keyword will be ignored.
EXPLANATION:
The specified liboverride keyword is only supported when also specifying
run31flow=yes.
USER RESPONSE:
No response is required if it is acceptable to ignore the liboverride keyword;
otherwise specify run31flow=yes and rerun.
WARNING (TSY-418): The synsrule keyword is no longer supported. Srules should no

longer be needed when using RC to build the top shell, however, if you need to specify
overrides for iocell pins, use the IOCELL_* global keywords in the input IOSpecList. The
synsrule keyword will be ignored.
EXPLANATION:
The specified synsrule keyword is only supported when also specifying
run31flow=yes.
USER RESPONSE:
No response is required if it is acceptable to ignore the synsrule keyword; otherwise
specify run31flow=yes and rerun.
WARNING (TSY-419): The file filename.srule has been specified in the synlibs
keyword. Srules should no longer be needed when using RC to build the top shell, however,
if you need to specify overrides for iocell pins, use the IOCELL_* global keywords in the input
IOSpecList. The srule file will be ignored.
EXPLANATION:
Srules files specified with the synsrule keyword is only supported when also specifying
run31flow=yes.

USER RESPONSE:
No response is required if it is acceptable to ignore the srule file; otherwise also specify
run31flow=yes and rerun.
WARNING (TSY-420): Ignoring the fixtestmode keyword for port port. This port does
not have test_use=TE.
EXPLANATION:
The fixtestmode keyword must be specified only on TEST_ENABLE ports (that is,
ports with test_use=TE).
USER RESPONSE:
Place the fixtestmode keyword on a port with test_use=TE and rerun if necessary.
WARNING (TSY-421): Skipping selection of port port as the fixtestmode signal. This
ports core_test_in keyword has not been specified.
EXPLANATION:
The fixtestmode keyword must be specified only on ports that have a core_test_in
keyword. The value of the this keyword is used as the name of the port.
USER RESPONSE:
Add the core_test_in keyword or place the fixtestmode keyword on a different port
WARNING (TSY-422): Skipping selection of clock port to fix internal clock violations. It
does not have required_keywords.
EXPLANATION:
The clock port cannot be used to fix clock violations because it is missing the data
mentioned in the IOSpecList.
USER RESPONSE:
Add the missing data or select a different port for fixing clock violations and rerun if
necessary.
WARNING (TSY-423): No test_signal ports were found. If DFT internal clock violations
are found, they will not be fixed.
EXPLANATION:

A port needed for fixing internal clock violations could not be found. The generated
insert_scan script will not include the clock violation fixing.
USER RESPONSE:
If the design has no clock violations or if they do not need to be fixed, no action is needed.
To fix violations, add a suitable port to the design and rerun.
WARNING (TSY-424): Unable to determine the fix clock pin for clock port port. If DFT
internal clock violations are found, they will not be fixed.
EXPLANATION:
The selected clock for fixing clock violations does not specify the sys_in or test_in
keywords used to determine the signal to use.
USER RESPONSE:
No response is required, however to fix these violations, add the sys_in or test_in
keywords for the clock and then rerun.
WARNING (TSY-425): Skipping selection of test signal port port. It does not have
test_use=TCLKASY or TCLKASYNEG.
EXPLANATION:
The requested async clock for fixing violations does not specify test_use=TCLKASY or
TCLKASYNEG.
USER RESPONSE:
Specify the fixasyncset/reset keyword on a port with test_use=TCLKASY or
TCLKASYNEG and then rerun.
WARNING (TSY-426): Skipping selection of test signal port port. It does not have a
test_in keyword.
EXPLANATION:
The requested async clock for fixing violations does not specify the test_in keyword.
USER RESPONSE:
Specify the fixasyncset/reset keyword on a port with test_use=TCLKASY or
TCLKASYNEG and then rerun.
WARNING (TSY-427): No port available to fix async set/reset violations. If present in the
design, they will not be fixed.

EXPLANATION:
A suitable port for fixing async set/reset DFT violations could not be found.
USER RESPONSE:
Specify a port with test_use=TCLKASY or TCLKASYNEG to automatically fix set/reset
violations.
WARNING (TSY-428): Both misrsize and numchains specified - but are not consistent,
ignoring misrsize and using numchains.
EXPLANATION:
Either but not both numchains and misrsize must be specified; the other will derived.
USER RESPONSE:
Rerun with modified keyword specifications if necessary.
WARNING (TSY-429): Not all DFT rule violations have been fixed.
EXPLANATION:
One or more of the flops in the design are breaking a DFT rule violation. This violation
means the flop cannot be properly controlled for scan and therefore will not be included
in the connected scan chains.
USER RESPONSE:
Examine the preceding message to determine why the DFT rules were not automatically
fixed. If the defaultviolation fixing option was set to no, setting it to yes may allow
the violations to be fixed.
WARNING (TSY-430): Port_type port port_name appears to have a share IO macro

(instance macro_name), however the hookup keyword has not been provided. Ensure the
IOSpecList used by insert_scan includes these hookup keywords. See the extended help
for this message for more information about how this problem can be resolved.
EXPLANATION:
The build_top_shell command adds test_in_hookup and test_out_hookup
keywords to the IOSpecList it produces. These keywords are needed by insert_scan
to create the proper connections for test signals when share IO logic is used on these
ports. Share IO logic is inserted by build_top_shell on many ports where both a
sys_use and test_use is specified. The insert_scan command verifies connections by
searching for share IO macro instances names (SIOM*portname) that

build_top_shell may insert and issues this warning if the appropriate hookup
keyword is not present.
The following are possible reasons:
build_top_shell ran first, but a user-generated IOSpecList was specified
on the insert_scan command-line. While processing, build_top_shell
generates an IOSpecList file that includes the required hookup keywords. This
is the IOSpecList that should be used when insert_scan is run.
Remove the specified IOSpecList from the insert_scan command and it will
default to the one produced by build_top_shell. If the IOSpecList produced
by build_top_shell cannot be used directly used for insert_scan,
ensure the test_in_hookup and test_out_hookup keyowrds are present
in the IOSpecList used for insert_scan.
There is no IOSpecList specified on the insert_scan command however,
build_top_shell and insert_boundary_scan were run separately.
Instead of running these commands separately, the recommended flow is to run
boundary scan insertion as part of build_top_shell. If this is not possible,
then the hookup keywords that are present in the IOspecList produced by
build_top_shell, must be included in the IOSpecList used by
insert_boundary_scan. The hookup keywords will then be automatically
picked up by insert_scan through the IOSpecList produced by
insert_boundary_scan.
The design includes instance names that match SIOM*portname, where
portname is one of the ports on the design, however, this instance was not
added by build_top_shell. In this case, it should be possible to safely
ignore this message.
USER RESPONSE:
Follow the recommendations listed in the EXPLANATION to ensure the
test_in_hookup and test_out_hookup keywords required by insert_scan are
present when insert_scan is run.
WARNING (TSY-431): Port port_name specifies the keyword keyword, but it does not
appear to be a type port, ignoring the keyword.
EXPLANATION:
The referenced keyword is present on a port that does not appear to be a matching type.
USER RESPONSE:

Remove the keyword from the port or place it on a different port and then rerun if
necessary.
WARNING (TSY-432): Ignoring the keyword keyword on port port_name because port
type has already been choosen.
EXPLANATION:
The referenced keyword is present on more than one port in the IOSpecList. This
keyword must only be specified for one port.
USER RESPONSE:
Ensure the keyword is only specified for one port in the IOSpecList and rerun if
necessary.
WARNING (TSY-433): Ignoring the keyword keyword on port port_name because the
corresponding input port could not be determined.
IEXPLANATION:
The referenced keyword is present on a port for which the corresponding netlist port
cannot be determined.
USER RESPONSE:
Ensure the corresponding netlist port is specified in the IOSpecList using the
core_test_in, test_in, or sys_in keywords and then rerun if necessary.
WARNING (TSY-440): Using default synthesis library filename. Rerun with keyword
synlibs to identify specific synthesis libraries to use.
EXPLANATION:
The referenced default synthesis library was used during execution, possibility because
no other synthesis libraries were detected.
USER RESPONSE:
Specify synthesis libraries and rerun.
ERROR (TSY-441): Could not locate the rc (RTL Compiler) executable in the PATH.
Exiting...
EXPLANATION:
A version of RTL Compiler is included with Encounter Test and is required for scan
insertion. This message indicates a potential installation problem.

USER RESPONSE:
Ensure the rc executable is located in the PATH and rerun.
WARNING (TSY-442): BuildGates scan insertion is no longer supported, switching the

scanengine option to RC.
EXPLANATION:
Only RTL Compiler scan insertion is now supported.
USER RESPONSE:
Remove the scanengine keyword from the command string; it is no longer required.
WARNING (TSY-443): Switching scanengine to bg (BuildGates).

EXPLANATION:
If opmisr=no is specified and RC is not detected in the PATH, , the scanengine is
automatically to be set to BuildGates.
USER RESPONSE:
If the RC engine is desired, Install RC and make sure the rc executable is located in the
PATH, then rerun.
WARNING (TSY-450): Unsupported keyword, keyword_name, used to specify the

reg_name register information in the section_name section in the IOSpecList. This
keyword is ignored. Remove this keyword from the IOSpecList and specify a different keyword
if necessary.
EXPLANATION:
The keyword used to provide information about the specified register is not a supported
keyword. It is ignored.
USER RESPONSE:
Remove this unsupported keyword from the IOSpecList. Refer to the Customer-
Specific User Guide for the supported keywords and rerun this command.

WARNING (TSY-451): Incorrect values specified for keyword keyword_name. Values
specified for this keyword must only contain 0s, 1s, xs or Xs. For this keyword to be used,
ensure it contains only the allowed characters.

EXPLANATION:
Values for this keyword must only contain 0s, 1s, xs or Xs. Default values are generated
if incorrect values are specified.
USER RESPONSE:
Correct the keyword value and rerun. Refer to the Customer-Specific User Guide for
the correct syntax and allowed keyword values.
WARNING (TSY-452): Line in the JTAG_Inline section starting with reserved word
INSTRUCTION does not have the keyword keyword_name. For this line in the
JTAG_Inline section to be processed, ensure the keyword keyword_name is specified.
EXPLANATION:
It is mandatory to reference the specified keyword while describing an instruction in the
JTAG_Inline section using the reserved word INSTRUCTION.
USER RESPONSE:
Add the specified keyword and its value and rerun this command.
WARNING (TSY-453): The opcodes specified for instruction instruction_name are of

inconsistent length. The opcode opcode_value is ignored.
EXPLANATION:
All specified opcode values must have the same number of bits. Mismatched opcodes
will be ignored.
USER RESPONSE:
Ensure all specified opcodes have the same length and are specified using the correct
syntax. Refer to the Customer-Specific User Guide.
WARNING (TSY-454): The number of capture bits, num_capture_bits , in the capture

pattern, capture_data, does not match the length, register_length, of the register
in which the specified values will be captured. The LENGTH keyword is ignored. For the
LENGTH keyword to be used, ensure the register length and the capture pattern length match
each other.
EXPLANATION:
There is a mismatch between the number of bits to be captured into the Wrapper Bypass
Register (WBY) versus the specified length of the WBY. The length of the WBY is
adjusted to match the number of bits to be captured in the WBY.
USER RESPONSE:

Ensure the WBY length matches the number of WBY capture bits and rerun.
WARNING (TSY-455): Unsupported keyword, keyword_name, used to specify

information about instruction instruction_name in the IOSpecList. This keyword is
ignored. Remove this keyword and specify a different keyword if necessary.
EXPLANATION:
The keyword used to describe information about the specified instruction is not a
supported keyword. It is ignored.
USER RESPONSE:
Remove this unsupported keyword from the IOSpecList. Refer to the Customer-
Specific User Guide for the keywords supported for INSTRUCTION and rerun this
command.
WARNING (TSY-456): Incorrect value, value, was specified for keyword

keyword_name on instruction instruction_name. The specified keyword is ignored.
To ensure this keyword is used, specify a supported value for this keyword and rerun.
EXPLANATION:
The specified value specified for the referenced keyword is not supported. The program
ignores this keyword.
USER RESPONSE:
Refer to the Customer-Specific User Guide for the supported values and rerun.
WARNING (TSY-457): The value specified for keyword keyword_name on instruction

instruction_name must not contain commas or braces. For this value to be used during
processing, remove any commas or braces in the value and rerun.
EXPLANATION:
The specified value must not contain commas or braces. This value is ignored.
USER RESPONSE:
Remove all commas or braces in the keyword value and rerun.
WARNING (TSY-458): Unknown reserved word word_name specified in the IOSpecList.

Line in the section_name section starting with the specified reserved word is ignored.
Ensure the correct reserved word is used and rerun.
EXPLANATION:

An unsupported reserved word was used in the specified section. The line starting with
this reserved word is ignored.
USER RESPONSE:
Refer to the Customer-Specific User Guide for the list of supported reserved words
for the specified section.
WARNING (TSY-459): Port port in the IOSpecList has a mismatched number of keyword
and value pairs. This port is ignored. To enable processing of this port, ensure an equal
number of keywords and values and rerun.
EXPLANATION:
The program ignores the referenced port due to mismatched keywords and values on it.
USER RESPONSE:
Ensure an equal number of keywords and values is specified and rerun.
WARNING (TSY-460): IO IOSpecList of type $iospec2::type is empty. Not writing.

EXPLANATION:
If a IOSpecList of the active or specified type does not exist, a warning is issued stating
that nothing has been written to a file.
USER RESPONSE:
Ensure a IOSpecList of the specified type exists in memory and rerun.
WARNING (TSY-462): [Severe] For bussed ports where the keyword

current_keyword is used, the keyword value must be separated and the
field_length must match the port bus length. The keyword current_keyword on
port port_name will not be added.
EXPLANATION:
iospec2::add_port requires that specific keywords with slash-separated or bussed
values must have the same number of fields as port bus.
USER RESPONSE:
Ensure that specific keywords on bussed ports have the same number of fields (either
slash-separated or in a bus) as the port bus and rerun.
WARNING (TSY-463): [Severe] For ports where the keyword current_keyword is

used, the keyword value must not be bussed. The keyword current_keyword on port
port_name will not be added.

EXPLANATION:
iospec2::add_port requires specific keywords to not be bussed.
USER RESPONSE:
Ensure that specific keywords that are not to bussed are not bussed and rerun.
WARNING (TSY-464): [Severe] The entered global value_or_keyword keyword or

value_name does not have a value_or_keyword specified. It will not be added to the
IOSpecList.
EXPLANATION:
A global keyword must have both a keyword and a value specified and they must be
separated by an = sign.
USER RESPONSE:
Ensure that all globals have both a keyword and a value separated by an = sign and
rerun.
WARNING (TSY-465): [Severe] The entered IOSpecList line line is in an incorrect

format. It must have keyword and value pairs separated by = signs. It will not be added to
the IOSpecList.
EXPLANATION:
A IOSpecList must consist of either ports, global variables or
BSDL_INLINE|JTAG_INLINE|WRAPPER_INLINE sections.
USER RESPONSE:
Ensure that all globals, ports and BSDL_INLINE|JTAG_INLINE|WRAPPER_INLINE
sections are specified in the appropriate formats and rerun.
Refer to the Customer-Specific User Guide.
WARNING (TSY-466): The TOP_MODULE_NAME global keyword must be specified to

generate valid BSDL. Default TOP_MODULE_NAME=topmodule will be used.
EXPLANATION:
The TOP_MODULE_NAME global keyword must be specified to generate valid BSDL.
USER RESPONSE:
Specify the TOP_MODULE_NAME global keyword and rerun if necessary.

WARNING (TSY-467): Line count in the pinmap file does not match the required syntax.
Each line must have the port name and the package pin name, followed by any comments
starting with the pound sign (#).
EXPLANATION:
The referenced line in the pinmap file does not match the required syntax. Each line must
have the port name and the package pin name, followed by any comments indicated with
a pound sign. (#) in the first character of a line.
USER RESPONSE:
Correct the referenced line in the pinmap file to match the required syntax and rerun if
necessary.
WARNING (TSY-468): Pinmap file file will be ignored because a corresponding input
IOSpecList was not provided.
EXPLANATION:
The line in the pinmap file does not match the required syntax. Each line must have the
port name and the package pin name, followed by any comments indicated with a pound
sign. (#) in the first character of a line.
USER RESPONSE:
Correct the line in the pinmap file to match the required syntax and rerun if necessary.
WARNING (TSY-469): Unable to determine pintype pin of iocell cellname from the list
of possible pins pinlist. If necessary, use the keyword global keyword in the IOSpecList
to specify the pintype pin on this iocell. Port port is ignored during processing.
EXPLANATION:
None of the pins on the interface for the referenced iocell with cellname match any of the
pin names in the list pinlist. The program is searching for an input/output/enable pintype
on the interface of the iocell. Without identification of the referenced pintype, the
boundary scan connections cannot be complete and the referenced port will be ignored
during boundary scan processing.
USER RESPONSE:
Ensure the correct information regarding the I/O cell pins is provided in the input
IOSpecList using the global keywords IOCELL_INPUT, IOCELL_OUTPUT, and
IOCELL_ENABLE and rerun if necessary.

WARNING (TSY-470): Unable to determine iocell type from cellname on port port. Port
port will be ignored during boundary scan processing.
EXPLANATION:
The type of I/O cell could not be determined based on the specified I/O cell cellname
present on the referenced port. Every I/O cell must be one of INPUT/OUTPUT2/
OUTPUT3/BIDIR types.
USER RESPONSE:
Review preceding messages to ensure that no related errors were generated. Correct
WARNING (TSY-471): No PAD or PINMAP information has been provided for the design
ports through either the IOSpecList or Pinmap files. The PINMAP attribute in the generated
BSDL file will be left unassigned.
EXPLANATION:
The PIN_MAP_STRING attribute in the BSDL file maps a design port to its physical
package pin. This information needs to be provided through either the PAD or PINMAP
keywords in the IOSpecList file or through the Pinmap file. Since this information was not
provided, the specified attribute in the BSDL file will be left unassigned.
USER RESPONSE:
Specify the PAD or PINMAP information if the PIN_MAP_STRING attribute must be
assigned in the BSDL and rerun.
WARNING (TSY-472): Unable to determine the list of possible pintype pins on iocell
cellname. Ensure the keyword global keyword in the input IOSpecList contains the
possible pintype pin names using correct syntax. Port port is ignored during processing.
EXPLANATION:
For each pintype, the program searches a list of possible pin names on an iocell that can
be specified with a global keyword. In this case, the list was empty, since the global
keyword was specified in the IOSpecList but most likely either had syntax errors or
contained an empty value.
By default, the list contains some default values, but the default values are overridden by
the values specified for the global keyword.
USER RESPONSE:
Ensure values are specified for the global keyword using the correct syntax and rerun.

Refer to the Customer-Specific User Guide for the correct syntax for these global
keywords.
WARNING (TSY-473): IEEE 1149.1 TRST port not found. Assuming a power-on reset signal
is resetting the Tap Controller. For a pre-instantiated TAP Controller, its TRST pin must be
connected to the power-on reset signal or else it will be tied to its inactive value of logic 1. If
the TAP Controller is to be instantiated during boundary scan insertion, its TRST pin will be
tied to logic 1. Modify this connection and connect the pin to a power-on reset signal. The
modifications to the netlist should occur prior to running boundary scan verification.
EXPLANATION:
The TRST port is not a mandatory TAP port however this port is necessary to ensure that
the TAP controller starts in a known state during the power-on reset,. If this port is not
present, connect the JTAG_TRST pin on the TAP controller to a power-on reset signal to
ensure predictable behavior.
USER RESPONSE:
If the TRST port was intentionally ommitted, then no response is needed. If this was not
the intention, specify the TRST port and rerun.
WARNING (TSY-474): Port portname is not present on the design and is also not a TAP
port. If a port specified in the IOSpecList or Pinmap file is not a TAP port, then it must already
be present on the design. The referenced port is ignored during Boundary Scan processing.
EXPLANATION:
A port must already be present in the design an hooked up to its iocell. The only
exception to this is TAP ports. The TAP ports and their corresponding iocells can be
provided in the IOSpecList and not exist on the design.
USER RESPONSE:
Ensure the referenced port exists on the design and is connected to its iocell and rerun
if necessary.
WARNING (TSY-475): Unable to determine the top-level pin connected to pin pinname on
iocell instance iocellinstance. There must be a uni-directional path from the pin on the
possibly embedded iocell to the top level of the design and there must be a net connected to
the pin at the top-level. Port portname is ignored during processing since either the
functional connections are incomplete or the sys_use of sysuse is incorrect.
EXPLANATION:

A boundary cell will only be inserted on a functional net existing at the top-level of the
design and the functional pin on an iocell must have a net attached to it. This net must
be present and connected to the top-level of the design.
USER RESPONSE:
Ensure the iocell pin is connected to the functional logic in the design, and the functional
net connected to this pin exists at the top-level of the design and rerun if necessary.
WARNING (TSY-476): Port portname has SYS_USE=OUTPUT2, but the iocell on this port
is of type iocelltype. For the HIGHZ instruction to be correctly implemented, the iocell on
this port must be of type OUTPUT3 or BIDIR. This port is ignored during boundary scan
processing.
EXPLANATION:
When the HIGHZ instruction is active, all output ports must be in high-impedance state.
Therefore, even if a port is functionally an OUTPUT2, it must be possible to drive this port
to a high-impedance state. The iocell on this port must be of type OUTPUT3 or BIDIR.
USER RESPONSE:
Ensure the proper iocell pin is connected to this port if the HIGHZ instruction must be
implemented. If not, then remove the HIGHZ instruction from the IOSpecList and rerun.
WARNING (TSY-477): Unable to determine the functional use (SYS_USE keyword) of

design port portname. Ensure that the functional pins of the iocell instance
iocellinsgtance on this port have nets attached to them and that these nets are present
at the top level of the design. This port is ignored during boundary scan insertion.
EXPLANATION:
A boundary cell will only be inserted on a functional net existing at the top level of the
design. All the functional pins on an iocell instance must have nets attached to them and
these nets must be present and connected at the top-level of the design.
USER RESPONSE:
Ensure the iocell is functionally connected to the core logic and the functional nets
connected to the iocell must be present in the top-level of the design and rerun if
necessary.
WARNING (TSY-478): Unable to determine iocell connected to port portname on the

design. The specified port is ignored during processing.
EXPLANATION:

Every functional port on the design must have an iocell connected to it and this iocell
must then be connected to the functional logic. The referenced port either does not have
an iocell connected to it, or else the connected iocell was not recognized. The port must
be connected to a pin on the iocell that has the liberty attribute is_pad=true.
USER RESPONSE:
connected to the iocell must be present in the top-level of the design and rerun if
necessary.
WARNING (TSY-479): Port portname connects to non-PAD pin iocellpin on the

iocell. Ensure the iocell PAD pin has the is_pad=true attribute on it in the liberty file. The
referenced port is ignored during processing.
EXPLANATION:
must then be connected to the functional logic. The specified port has an iocell
connected to it, but it must be connected to a pin on the iocell that has the liberty attribute
is_pad=true.
USER RESPONSE:
Ensure the following and rerun if necessary:
An iocell is functionally connected to the port and the core logic.
The iocell pin connected to the port has the liberty attribute is_pad=true on it.
WARNING (TSY-480): The value cellvalue has been specified for keyword CELL on
port portname. An iocell must exist for the boundary cell to be inserted on a port. This port
is ignored during boundary scan insertion.
EXPLANATION:
must then be connected to the functional logic. Port portname has the value NONE
specified for the CELL keyword in the IOSpecList.
USER RESPONSE:
No response is required if this is intentional. Otherwise, ensure that the port has iocell
functionally connected between the port and the core logic and rerun if necessary.
WARNING (TSY-481): Unsupported value value specified for keyword BDY_USE on port
portname in the IOSpecList. This port is ignored during boundary scan processing.

EXPLANATION:
The referenced value for the BDY_USE keyword is not supported and is therefore ignored
during processing.
USER RESPONSE:
Specify a supported value for the BDY_USE keyword if the referenced port is to be
processed and rerun if necessary. Refer to the Customer-Specific User Guide.
WARNING (TSY-482): Unable to determine functional use (sys_use keyword) of iocell

instance iocellinstance due to unconnected direction pin pinname.
EXPLANATION:
All the functional pins on an iocell instance must have nets attached to them and these
nets must be present and connected at the top-level of the design. A boundary cell will
only be inserted on a functional net existing at the top-level of the design.
USER RESPONSE:
connected to the iocell are present in the top-level of the design and rerun if necessary.
WARNING (TSY-483): JTAG_TRST pin on the JTAG_MACRO is unconnected and no TRST

port has been specified either on the design or in the IOSpecList. Connected the pin to its
inactive value: logic value 1.
EXPLANATION:
The JTAG_TRST pin on the JTAG_MACRO must ideally be connected either to a top-level
TRST port, or to a power-on reset signal. If neither of these options are available, the
JTAG_TRST pin will be tied to its inactive value of logic-1.
USER RESPONSE:
No response is required if the intent is to tie the JTAG_TRST pin to logic-1 value, no
response is required. If this is not the intention, then either specify a top-level TRST port
or ensure a power-on reset signal is connected to the JTAG_TRST pin, and rerun if
necessary.
WARNING (TSY-484): The core side pin corepin on the iocell connected to the TAP port
portname is already connected and will remain connected since the specification was
madeo to preserve the connection. The jtagpin is currently unconnected and therefore
must be manually connected to the specified pin on the TDO iocell.
EXPLANATION:

The core side pin of the iocell on the specified TAP port is already connected to some
net. The program assumes that the specified TAP port is already connected either to a
JTAG_MACRO pin or to some other controlling logic and no additional connections will be
made.
USER RESPONSE:
No response is required If the existing connection is correct. If not, ensure that there is
no net connected to the core side pin of the iocell on the specified port and rerun if
necessary.
WARNING (TSY-485): Port portname has value bdyuse for the BDY_USE keyword.
Since this port is ignored during Boundary Scan processing, the BDY_USE keyword will be
overwritten with a value of NONE.
EXPLANATION:
The program ignores the specified port during boundary scan processing and adds
BDY_USE=NONE keyword for that port. If the port is already specified with the BDY_USE
keyword on it, it will be overwritten with BDY_USE=NONE.
USER RESPONSE:
If the port is not to be ignored, correct the preceding warnings related to that port and
rerun the command.
WARNING (TSY-486): The pin pin pinname of the iocell on TDO TAP port portname is
currently connected and will remain connected since the preservetdoconnection
keyword is set (or defaulted) to yes. If the pintype pin on the JTAG_MACRO is unconnected,
manuall connect the the specified iocell pin2 pin to it.
EXPLANATION:
The core side pin of the iocell on the specified TAP port is already connected to some
net. Therefore, the prrogram assumes that the specified TAP port is already connected
either to a JTAG_MACRO pin or to some other controlling logic. No additional connections
will be made.
USER RESPONSE:
Ensure that the existing connection is correct. If necessary, manually connect the
specified iocell pin to the JTAG_MACRO and rerun.
WARNING (TSY-487): The pin pin pinname of the iocell on TDO TAP port portname is
currently connected. Since it was not specified to preserve this connection, the connection
will be broken and the specified iocell pin2 pin will be connected to the pintype pin on the
JTAG_MACRO.

EXPLANATION:
The core pin of the iocell on the TDO TAP port is currently connected to the core or some
other logic. The preserve_tdo_connection command option was not specified and
therefore the existing connection will be broken and the iocell pin will be connected to the
JTAG_MACRO.
USER RESPONSE:
Ensure that the existing connection is correct and rerun if necessary
WARNING (TSY-488): The pin pinname was not found on the custom boundary cell
cell.
EXPLANATION:
The referenced pin is required for the standard boundary cell but is not required for the
custom boundary cell. Ensure the custom boundary cell will correctly function by hooking
up those pins in other means.
USER RESPONSE:
Ensure the custom boundary cell is correctly implemented and rerun if necessary.
WARNING (TSY-500): Unable to determine functionality of port_type port

port_name. The port is ignored. Use keyword keyword_type to specify the functionality
of the port and rerun to include this port.
EXPLANATION:
Every port specified in the CoreSpecList must have a keyword describing the
functionality of that port. For example, a functional port should have the CORE_SYS_USE
keyword specified, and a test port should have the CORE_TEST_USE keyword specified.
Without this information, it is impossible to understand the functionality of the port. The
program will ignore the specified port in the CoreSpecList because these requirements
are not met.
USER RESPONSE:
Specify, for the port identified in the message, the appropriate keyword describing the
type of this port and rerun. Refer to Creating IEEE 1500 Core Wrapping Logic in the
Encounter Test: Guide 1: Models for related information.


WARNING (TSY-501): An unsupported Wrapper Boundary Cell, cell_type, was used
for port port_name. If the default is not acceptable, replace the cell with one of the
supported cells and rerun.
EXPLANATION:
Every specified port in the CoreSpecList must use one of the supported Wrapper
Boundary Cells. If the user-specified cell is not one of the supported types, a default cell
type is used in its place.
USER RESPONSE:
Specify one of the supported Wrapper Boundary Cells and rerun. Refer to the
Customer-Specific User Guide.
WARNING (TSY-502): An unsupported instruction, instruction_name, has been

used. This instruction is ignored. Specify one of the supported instructions and rerun
EXPLANATION:
Every instruction specified in the CoreSpecList must be a supported instruction. The
instruction identified in the message is ignored.
USER RESPONSE:
Specify one of the supported instructions and rerun. Refer to Wrapper Instruction
Register (WIR) in the Encounter Test: Guide 1: Models for a list of supported
instructions.
WARNING (TSY-503): Keyword keyword_name was specified without a value. Every

keyword specified in the CoreSpecList must have a value. The keyword is ignored. To include
the keyword, assign an appropriate value and rerun.
EXPLANATION:
Every keyword specified in the CoreSpecList must have a non-null value. Since there is
no default for these keywords, the referenced keyword is ignored during processing of
the CoreSpecList information.
This error may also be caused due to incorrect syntax.
USER RESPONSE:
Specify a correct, non-null value for the keyword and rerun.

WARNING (TSY-504): Unable to obtain the OPCODE value. A null value was specified for
this keyword. The default opcode is used. If the default is not appropriate, specify the OPCODE
keyword with a non-null value and rerun.
EXPLANATION:
A non-null OPCODE value is required. If unspecified, a default opcode is generated and
used for this instruction.
USER RESPONSE:
If a specific opcode value is required, specify it using the OPCODE keyword. Refer to
Components of IEEE 1500 Wrapper Circuitry in the Encounter Test: Guide 1:
Models for the syntax to be used while specifying instruction opcodes.
WARNING (TSY-505): Incorrect values were specified for the OPCODE keyword for
instruction instruction_name. The opcode bits are only allowed the values 0, 1, x, or X.
To specify multiple opcodes, use a comma separated list of
OPCODE={opcode1,opcode2,opcode3}.
EXPLANATION:
An instruction opcode must consist of 0, 1, x, or Xs. Specify multiple opcodes for an
instruction by using a comma-separated list enclosed within braces. A default opcode is
generated and used in lieu of the specified opcode.
USER RESPONSE:
Refer to Components of IEEE 1500 Wrapper Circuitry in the Encounter Test: Guide
1: Models for information on instruction opcode syntax.
WARNING (TSY-506): The specified opcodes are of inconsistent length. All specified
opcode values must have the same number of bits. The opcodes are padded with default
values to make them the same length for this run. Ensure all the specified opcodes have the
same length and rerun.
EXPLANATION:
Specified opcodes must be of equal length. Mismatched opcode lengths cause some
opcodes to be padded with default values.
USER RESPONSE:
Ensure all specified opcodes have the same length and are specified using the correct
syntax.
WARNING (TSY-507): Incorrect values specified for keyword keyword_name. Supported

values for this keyword are 0s and 1s. Correct the keyword values and rerun.

EXPLANATION:
Allowable values for this keyword are 0s and 1s. Default values are generated if
incorrect values are specified.
USER RESPONSE:
Correct the keyword value and rerun. Refer to the Customer-Specific User Guide for
the correct syntax and allowed values for these keywords.
WARNING (TSY-508): Unable to implement instruction WS_SAFE. This instruction is

ignored. The WS_SAFE instruction requires that all Wrapper Boundary Cells on core outputs
support provision of hard-wired safe values. Ensure the correct Wrapper Boundary Cells are
used on all core outputs.
EXPLANATION:
For the WS_SAFE instruction to comply with the IEEE 1500 standard, all the Wrapper
Boundary Cells placed on the core outputs must support providing hard-wired safe
values. Only certain boundary cells are currently supported that can provide safe values.
The instruction is ignored to attain compliance with the standard.
USER RESPONSE:
Specify the correct Wrapper Boundary Cells on the cores output ports and rerun. Refer
to the Customer-Specific User Guide for a list of cell types that support the provision
of safe values.
WARNING (TSY-509): Parallel instruction instruction_name cannot be implemented.

This instruction is ignored because a non-zero number of Wrapper Parallel In (WPI) and
Wrapper Parallel Out (WPO) ports are not detected in the CoreSpecList. Ensure both the WPI
and WPO ports are specified in the CoreSpecList file.
EXPLANATION:
The width of the Parallel Port must be defined in order to implement instructions that use
the Wrapper Parallel Port. It is mandatory to specify Wrapper Parallel In and Wrapper
Parallel Out ports in the CoreSpecList since the width cannot be determined otherwise.
Instructions that use the parallel port are not implemented due to incomplete Parallel Port
information.
USER RESPONSE:
Ensure the Wrapper Parallel In and Wrapper Parallel Out ports are correctly specified in
the CoreSpecList file. Refer to the Customer-Specific User Guide.
WARNING (TSY-510): Unable to implement instruction WS_PRELOAD. This instruction is

ignored. The WS_PRELOAD instruction requires that all Wrapper Boundary Cells on core

outputs have a dedicated update storage element. Make sure the correct Wrapper Boundary
Cells are used on all core outputs.
EXPLANATION:
To attain IEEE 1500 compliance for the WS_PRELOAD instruction, all the Wrapper
Boundary Cells placed on core outputs must contain a dedicated storage element that
supports the update functionality. Only certain boundary cells are currently supported
that contain dedicated update storage elements. This instruction is ignored in order to
attain compliance with the standard.
USER RESPONSE:
Specify the correct Wrapper Boundary Cell types on the cores output ports and rerun.
Refer to Components of IEEE 1500 Wrapper Circuitry in the Encounter Test: Guide
1: Models for cell types that contain an update storage element.
WARNING (TSY-511): Invalid combination of keywords specified for port port_name. The
port is ignored. A non-clock port cannot have both the CORE_SYS_USE and CORE_TEST_USE
keywords since sharing of functional and test I/Os is not allowed. Specify only one of these
two keywords for this port.
EXPLANATION:
Currently there is no support for allowing ports to have both a functional and test use.
Only clock ports are exempt from this condition. This core port is ignored while building
the wrapper.
USER RESPONSE:
Make the port a dedicated functional or test port and rerun this command.
WARNING (TSY-512): Unable to determine functionality of port port_name. The port is

ignored. To include this port specify at least one of the following keywords: CORE_SYS_USE,
CORE_TEST_USE, WPR_USE, and rerun.
EXPLANATION:
Every port in the CoreSpecList requires specification of at least one of the keywords
CORE_SYS_USE, CORE_TEST_USE, or WPR_USE specified on it. Presence of these
keywords determines the actual functionality of this port. Absence of all three keywords
causes this core port to be ignored during wrapper creation.
USER RESPONSE:
Ensure the port has at least one of the listed keywords specified, and rerun this
command.

WARNING (TSY-513): Unable to determine port name on the core. For test ports, the
CORE_IN or CORE_OUT keywords must be used to specify the core port name. To include this
core port, specify the CORE_IN or CORE_OUT keyword for this port and rerun this command.
EXPLANATION:
The CORE_IN/CORE_OUT keywords are used to explicitly specify the port name on the
core. Since the wrapper port name for core test ports must be a reserved word, the
CORE_IN/CORE_OUT keywords are the only way to know the core ports to which
connections are to be made. Due to lack of this information, this core port is ignored
during wrapper creation.
USER RESPONSE:
Ensure the core test port has a correct (CORE_IN or CORE_OUT) keyword specified and
rerun.
WARNING (TSY-514): Invalid combination of keywords has been specified for port
port_name. The port is ignored. Port port_name cannot use the WPR_USE keyword in
combination with either CORE_TEST_USE or CORE_SYS_USE. Ensure this port either has
only the WPR_USE keyword, or some combination of the CORE_SYS_USE and
CORE_TEST_USE keywords.
EXPLANATION:
Every port in the CoreSpecList requires specification of at least one the keywords
CORE_SYS_USE, CORE_TEST_USE, or WPR_USE. The presence of these keywords
determines the actual functionality of this port. A port cannot use the WPR_USE keyword
in combination with any of the previously mentioned keywords.
Because ports needed to operate the Wrapper do not play a role in the operation of core,
they must not have either the CORE_SYS_USE or CORE_TEST_USE keywords specified
on them.
USER RESPONSE:
Ensure the port identified in this message is specified with correct keywords and rerun.
WARNING (TSY-515): Non-numeric value specified for keyword LENGTH. The run
continues using a default numeric value. If the default is not acceptable, specify an allowed
numeric value and rerun.
EXPLANATION:
The LENGTH of a register must be a numeric value. A default value will be assigned.
USER RESPONSE:

Specify a numeric value for the LENGTH keyword and rerun.
WARNING (TSY-516): No INTEST instructions have been specified in the CoreSpecList. To

attain compliance with the IEEE 1500 standard the instruction, WS_INTEST_SCAN, is
implemented in the wrapper. If this is not acceptable, specify an INTEST instruction in the
Wrapper_Inline section of the CoreSpecList and rerun.
EXPLANATION:
A wrapper must contain at least one instruction that tests the core to comply with the
IEEE 1500 standard. If no INTEST instructions have been specified, the
WS_INTEST_SCAN instruction is implemented by default.
USER RESPONSE:
If the WS_INTEST_SCAN instruction is not acceptable, specify at least one INTEST
instruction in the CoreSpecList and rerun.
WARNING (TSY-517): Unsupported keyword, keyword_name was used for port

port_name. This keyword is ignored. Remove this keyword from the CoreSpecList and
specify a different keyword if necessary.
EXPLANATION:
An unsupported keyword was used for the specified port and is ignored.
USER RESPONSE:
Refer to the Customer-Specific User Guide and if necessary, specify a supported
keyword and rerun.
WARNING (TSY-518): Incorrect syntax used to specify the value of keyword

keyword_name on port port_name. This keyword is ignored. Enclose the keyword value
between { and } braces and rerun.
EXPLANATION:
The syntax for the specified keyword requires that the value be enclosed between
matching braces; otherwise, this keyword is ignored.
USER RESPONSE:
Refer to the Customer-Specific User Guide, specify corrected syntax and rerun.
WARNING (TSY-519): Incorrect segment number segment_number specified for

instruction instruction_name using the keyword keyword_name on port
port_name. The value for the specified keyword should only be a positive integer greater

than 0. Ensure the correct value for the segment number and rerun; otherwise the specified
keyword is ignored.
EXPLANATION:
The segment number specified using the specified keyword should be an integer greater
than 0; otherwise, the keyword is ignored.
USER RESPONSE:
Ensure the keyword has the correct value and rerun.
WARNING (TSY-520): Incorrect syntax used to specify the value of keyword

keyword_name on port port_name. The required syntax is {a1:b1,a2:b2,a3:b3},
whereas the value specified was value. Ensure the value matches the required syntax;
otherwise the specified keyword is ignored.
EXPLANATION:
The value specified for the keyword is ignored since it does not match the required syntax
and the keyword is ignored. The syntax value is correctly specified as
{a1:b1,a2:b2,a3:b3}.
USER RESPONSE:
Refer to the Customer-Specific User Guide, specify a corrected keyword value and
rerun.
WARNING (TSY-521): Incorrect value, value, was specified for keyword

keyword_name on port port_name. The specified keyword is ignored. To ensure this
keyword is used during processing, specify a supported value for this keyword and rerun.
EXPLANATION:
An unsupported value was specified for the referenced keyword and caused the keyword
to be ignored.
USER RESPONSE:
Refer to the Customer-Specific User Guide, specify a supported keyword value and
rerun.
WARNING (TSY-522): Keyword keyword_name has been specified more than once on
the line in the Wrapper_Inline section beginning with the reserved word
keyword_word. Either remove the redundant keyword and rerun, or else only the first
occurrence is used.
EXPLANATION:

The same keyword has been specified multiple times on the same line in the
Wrapper_Inline section. Only the first occurrence is used.
USER RESPONSE:
If necessary, remove the incorrect instance of the referenced keyword and rerun.
WARNING (TSY-523): Unsupported keyword keyword_name used to specify the

Wrapper Instruction Register (WIR) information in the Wrapper_Inline section in the
CoreSpecList. This keyword is ignored. Remove this keyword from the CoreSpecList and
EXPLANATION:
The keyword used for specifying the Wrapper Instruction Register (WIR) information is
not a supported keyword and is ignored.
USER RESPONSE:
Remove the unsupported keyword from the CoreSpecList and rerun if necessary. Refer
to the Customer-Specific User Guide for supported keywords.
WARNING (TSY-524): Unsupported keyword keyword_name used to specify the

Wrapper Bypass Register (WBY) information in the Wrapper_Inline section in the
EXPLANATION:
An unsupported keyword was used to specify Wrapper Bypass Register (WBY)
information and is ignored.
USER RESPONSE:
to the Customer-Specific User Guide for supported keywords.
WARNING (TSY-525): Unsupported keyword keyword_name used to specify information

about instruction instruction_name in the Wrapper_Inline section in the
EXPLANATION:
An unsupported keyword was used to specify information for the referenced instruction
and is ignored.
USER RESPONSE:

to the Customer-Specific User Guide for supported INSTRUCTION keywords.
WARNING (TSY-526): Port port_name has CORE_SYS_USE of CLOCK so it must have

CORE_TEST_USE of TCLK or TCLKNEG or SCLK or SCLKNEG. The default value,
CORE_TEST_USE=TCLK is used. If the default is not appropriate, specify the appropriate
value and rerun.
EXPLANATION:
When specifying a clock port in the CoreSpecList, both the CORE_SYS_USE and
CORE_TEST_USE keywords must be specified. Whenever CORE_SYS_USE=CLOCK is
specified, the CORE_TEST_USE keyword requires of the following values: TCLK or
TCLKNEG or SCLK or SCLKNEG. If the CORE_TEST_USE keyword is not specified, or if the
keyword has an unsupported value, the value TCL is used by default.
USER RESPONSE:
Refer to theCustomer-Specific User Guide for the combination of values to be used
while specifying clocks in the CoreSpecList.
WARNING (TSY-527): Port port_name has CORE_TEST_USE of core_test_use so it

must have CORE_SYS_USE of CLOCK or NONE. The default value CORE_SYS_USE=CLOCK is
used. If the default is not appropriate, specify the appropriate value and rerun.
EXPLANATION:
When specifying a clock port in the CoreSpecList, both the CORE_SYS_USE and
CORE_TEST_USE keywords must be specified. Whenever a CORE_TEST_USE keyword
has one of the values TCLK or TCLKNEG, the CORE_SYS_USE keyword must have the
value CLOCK or NONE. If the CORE_SYS_USE keyword is not specified, or if the keyword
has an unsupported value, the value CLOCk is used by default.
USER RESPONSE:
Refer to the Customer-Specific User Guide for the combination of values to be used
while specifying clocks in the CoreSpecList.
WARNING (TSY-528): Incorrect values specified for keyword keyword_name on port

port_name. The specified keyword is ignored, and the run continues. For this keyword to
be used during processing, ensure the value assigned is a test inhibit (+TI or -TI) or a scan
enable (+SE or -SE) and rerun.
EXPLANATION:
An unsupported value was assigned to the referenced keyword and caused the keyword
to be ignored during processing.

USER RESPONSE:
Refer to the Customer-Specific User Guide for supported keyword values and rerun.
WARNING (TSY-529): Missing scan-in port for scan chain chain_name. This scan chain
is ignored. To ensure this chain is used during processing, specify
SCAN_CHAIN=chain_name value on the scan-in port of this chain and rerun.
EXPLANATION:
The specified scan chain is missing a scan input port. This chain is ignored during
processing.
USER RESPONSE:
Ensure the SCAN_CHAIN keyword is specified on the scan chains input port in the
CoreSpecList and rerun. The value of this keyword must be the name of the specified
scan chain.
WARNING (TSY-530): Missing scan-out port for scan chain chain_name. This scan chain
is ignored. To ensure this chain is used during processing, specify
SCAN_CHAIN=chain_name value on the scan-out port of this chain and rerun.
EXPLANATION:
The specified scan chain is missing a scan output port. This chain is ignored during
processing.
USER RESPONSE:
Ensure the SCAN_CHAIN keyword is specified on the scan chains output port in the
CoreSpecList and rerun. The value of this keyword must be the name of the specified
scan chain.
WARNING (TSY-531): Duplicate scan input port port_name1 found for scan chain
chain_name. The specified scan chain already has a scan input port port_name2. Port
port_name1 is ignored. For the correct scan input port to be used, ensure that the
SCAN_CHAIN=chain_name value is specified for only one input port in the CoreSpecList,
and then rerun.
EXPLANATION:
Multiple scan input ports have been specified for the scan chain with the name
chain_name. Only the first instance is used. The other input ports are ignored.
USER RESPONSE:

For the correct scan input port to be used, ensure there is only one input port in the
CoreSpecList that has the specified scan chain as the value of the SCAN_CHAIN
keyword and rerun.
WARNING (TSY-532): Duplicate scan output port port_name1 found for scan chain
chain_name. The specified scan chain already has a scan output port port_name2. Port
port_name1 is ignored. For the correct scan output port to be used, ensure that the
SCAN_CHAIN=chain_name value is specified for only one output port in the CoreSpecList,
and then rerun.
EXPLANATION:
Multiple scan output ports have been specified for the scan chain with the name
chain_name. Only the first instance is used. The other output ports are ignored.
USER RESPONSE:
For the correct scan output port to be used, ensure there is only one output port in the
CoreSpecList that has the specified scan chain as the value of the SCAN_CHAIN
keyword and rerun.
WARNING (TSY-533): Missing SCAN_CHAIN keyword on port port_name having

CORE_TEST_USE of core_test_use. The port is ignored. For the specified port to be
used, the scan chain to which this port is related must be specified in the CoreSpecList using
the SCAN_CHAIN keyword.
EXPLANATION:
Ports that have a CORE_TEST_USE of scan_in or scan_out are scan input or output
ports. These ports require the SCAN_CHAIN keyword specified so that the input and
output ports of a scan chain can be identified.
USER RESPONSE:
Refer to the Customer-Specific User Guide for a description of the SCAN_CHAIN
keyword, use it on the referenced port and rerun.
WARNING (TSY-534): The opcode opcode_value of instruction instruction_name

is not a unique opcode. It is ignored and a default opcode is assigned. If the default is not
acceptable, specify a unique opcode for instruction instruction_name and rerun.
EXPLANATION:
Each instruction in the wrapper requires a unique opcode. Since the specified opcode is
already in use for another instruction, a default opcode is assigned for the specified
instruction. Note that if multiple opcodes have been provided in the CoreSpecList for the
specified instruction, then a default opcode will not be assigned.

USER RESPONSE:
If the default behavior is not acceptable, specify a unique opcode for the referenced
instruction and rerun.
WARNING (TSY-535): Mismatch between the length wby_length specified for the
Wrapper Bypass Register (WBY) and the number of bits num_capture_bits supposed
to be captured in the WBY. The WBY length is adjusted to match the number of capture bits.
If this default behavior is not acceptable, ensure the WBY length matches the number of WBY
capture bits.
EXPLANATION:
There is a mismatch between the number of bits to be captured into the Wrapper Bypass
Register (WBY) versus the specified length of the WBY. The length of the WBY is
adjusted to match the number of bits to be captured in the WBY.
USER RESPONSE:
Ensure the WBY length matches the number of WBY capture bits and rerun.
WARNING (TSY-536): Mismatch between the length wir_length specified for the
Wrapper Instruction Register (WIR) and the number of bits num_capture_bits supposed
to be captured in the WIR. The number of WIR length capture bits is adjusted to match the
WIR length. If this default behavior is not acceptable, ensure the WIR length matches the
number of WIR capture bits.
EXPLANATION:
There is a mismatch between the number of bits to be captured into the Wrapper
Instruction Register (WIR) versus the length of the WIR. Since the length of the WIR can
be obtained either directly from the keyword LENGTH, or derived from the instructions
and opcodes that have been specified in the CoreSpecList, the number of bits to be
captured in the WIR is adjusted accordingly.
USER RESPONSE:
Ensure the WIR length matches the number of WIR capture bits and rerun.
WARNING (TSY-537): Duplicate declaration of INSTRUCTION instruction_name

found in the Wrapper_Inline section of the CoreSpecList. Only the first instance of the
instruction declaration is used. If this default behavior is not acceptable, remove the incorrect
instances of the instruction declaration and rerun.
EXPLANATION:
Multiple declarations of the same wrapper instruction have been found. The first instance
is used.

USER RESPONSE:
Remove the incorrect instances from the CoreSpecList and rerun.
WARNING (TSY-538): Opcode opcode specified for instruction instruction_name

does not match the length wir_length of the Wrapper Instruction Register (WIR). The
specified opcode is ignored, and a default opcode is assigned to this instruction. If a default
opcode is not acceptable, specify the correct opcode for the specified instruction and rerun.
EXPLANATION:
The length of the opcode specified for a wrapper instruction must match the length of the
Wrapper Instruction Register (WIR). Opcodes whose length do not match the length of
the WIR are ignored, and a default opcode is assigned to the corresponding instructions.
USER RESPONSE:
If a default opcode is not acceptable, specify an opcode whose length matches the length
of the WIR and rerun.
WARNING (TSY-539): Opcode opcodespecified for instruction instruction_name is

smaller than the Wrapper Instruction Register (WIR) length needed to implement all the
specified instructions. The specified opcode is padded with 0s to match the WIR length. If
this is not acceptable, ensure that the opcode for instruction instruction_name matches
the length of the WIR that is implemented.
EXPLANATION:
The length of the opcode specified for a wrapper instruction must match the length of the
Wrapper Instruction Register (WIR). Opcodes whose length do not match the length of
the WIR are padded with 0s if needed.
USER RESPONSE:
If the default behavior is not acceptable, specify an opcode whose length matches the
length of the WIR and rerun.
WARNING (TSY-540): The value,segment_value of the SEGMENT_ID keyword on port

port_name for instruction instruction_name is already in use by another wrapper
parallel input port. A unique number is assigned by default. If this is not acceptable, ensure a
unique number is assigned to the SEGMENT_ID keyword on the specified port.
EXPLANATION:
For each instruction, every wrapper parallel input port should be assigned a unique
SEGMENT_ID number. Not doing so would mean using two wrapper parallel input ports
to drive one boundary cell, which is not possible. A default unique number is assigned to
the SEGMENT_ID keyword on the specified port.

USER RESPONSE:
If the default assignment is not acceptable, for each instruction, assign unique
SEGMENT_ID numbers to each Wrapper Parallel Input port and rerun.
WARNING (TSY-541): Incorrect syntax when specifying multiple values for keyword
keyword_name in the Wrapper_Inline section. This keyword is ignored. For this
keyword to be used during processing, ensure the value specified matches the syntax
{val1,val2,val3}.
EXPLANATION:
When specifying multiple values using the referenced keyword, the syntax to be used is
{val1,val2,val3}. Since incorrect syntax was used in this case, the keyword was
ignored during processing.
USER RESPONSE:
Refer to the Customer-Specific User Guide, correct the syntax and rerun.
WARNING (TSY-542): Incorrect value while specifying global keyword keyword_name.

The value of a global keyword cannot contain the # character. The specified keyword is
ignored. For this keyword to be used during processing, ensure it does not contain the #
character in its value.
EXPLANATION:
The presence of comments (starting with #) on the same line as the global keyword
causes parsing problems. If necessary, place comments on the line above. Since the
specified global keyword had a # character in its value, it was ignored.
USER RESPONSE:
Remove the comments from the same line as the global keyword and rerun.
WARNING (TSY-543): Unable to locate port port_name specified in keyword

keyword_name for instruction instruction_name. Either the port does not exist, or
this port is being ignored due to a previous error. This port name in keyword keyword_name
is ignored. For this port to be used while processing the specified keyword, ensure the port
port_name exists and has no associated errors or warnings.
EXPLANATION:
The referenced port either does not exist, or has been ignored because of previous
errors relating to that port. The port is removed from the list of ports provided to the
specified keyword.
USER RESPONSE:

To include the port during processing, ensure the port exists, the name has been spelled
correctly, and the port has no associated errors/warnings, and then rerun.
WARNING (TSY-544): Unable to locate clock port_name1 specified using keyword

keyword_name on core port port_name2. The port port_name1 is not a clock port on the
core. This keyword is ignored. For this keyword to be used, ensure the core clock port exists
and has no associated errors or warnings.
EXPLANATION:
The referenced port either does not exist, or has been ignored because of previous
errors relating to that port. The port is removed from the list of ports provided to the
specified keyword.
USER RESPONSE:
To include the port during processing, ensure the port exists, the name has been spelled
correctly, and the port has no associated errors/warnings, and then rerun.
WARNING (TSY-545): Missing keyword on test port with keyword

SCAN_CHAIN=chain_name. This port does not have either CORE_IN or CORE_OUT
specified, and is ignored. For the scan chain to be connected properly, ensure that either the
CORE_IN or CORE_OUT keywords are specified on this test port.
EXPLANATION:
The CORE_IN and CORE_OUT keywords are used to explicitly specify the port name on
the core. Since the wrapper port name for core test ports is not specified (a reserved
word is used instead), the CORE_IN/CORE_OUT keywords are the only means to
determine how to connect the core ports. Due to lack of this information, this ports
information in the CoreSpecList is ignored.
USER RESPONSE:
Ensure the test port is specified with the correct (CORE_IN or CORE_OUT) keyword and
rerun.
WARNING (TSY-546): An unsupported Wrapper Boundary Cell, cell_type, was used

for global keyword DEFAULT_WRAPPER_BOUNDARY_CELL. The run continues using
supported cell default_cell_type. If the default is not acceptable, replace the cell with
one of the supported cells and rerun.
EXPLANATION:
The global keyword DEFAULT_WRAPPER_BOUNDARY_CELL is used to specify the
default boundary cell type for every port in the CoreSpecList. If the cell type specified

using this global keyword is not one of the supported types, a supported default cell type
is used in its place.
USER RESPONSE:
Specify one of the supported Wrapper Boundary Cells and rerun. Refer to "Creating
IEEE 1500 Core Wrapping Logic" in the Encounter Test: Guide 1: Models for a list of
supported cell types.
WARNING (TSY-547): Unable to insert Wrapper Boundary Cell on core pin core_pin.
The specified location is ignored. Ensure this pin exists on the core and the direction of this
core pin is specified correctly in the CoreSpecList file.
EXPLANATION:
The program was unable to insert Wrapper Boundary Cell on the specified core pin since
the pin was not found on the core. The core pin will be ignored during boundary cell
insertion.
USER RESPONSE:
To insert a boundary cell next to the specified core pin, ensure the pin exists and is
specified correctly, and then rerun.
WARNING (TSY-548): Input pin, core_pin, of core instance, core_instance, is not

connected within the wrapper. This pin is ignored during processing. Ensure this pin has been
specified correctly in the CoreSpecList file, resolve any and there are no preceding warnings
related to this pin.
EXPLANATION:
The referenced input pin on the core instance is unconnected. Possible causes are an
incorrect specification in the CoreSpecList file or there are other warnings associated
with this pin.
USER RESPONSE:
To connect the pin, ensure the pin is correctly specified in the CoreSpecList file, resolve
any preceding warnings related to this pin, and then rerun.
WARNING (TSY-549): Output pin, core_pin, of core instance, core_instance, is not

connected within the wrapper. This pin is ignored during processing. Ensure this pin has been
specified correctly in the CoreSpecList file and there are no preceding warnings related to this
pin.
EXPLANATION:

The referenced output pin on the core instance is unconnected. Possible causes are an
incorrect specification in the CoreSpecList file or there are other warnings associated
with this pin.
USER RESPONSE:
To connect the pin, ensure the pin is correctly specified in the CoreSpecList file, resolve
any preceding warnings related to this pin, and then rerun.
WARNING (TSY-550): Port portname already has the keyword kwdprev specified and
it will be overwritten with kwdnew, which was inferred from the option option on the
command line.
EXPLANATION:
The keyword value specified in the IOSpecList will be overwritten with a new value
obtained from information inferred from the command line.
USER RESPONSE:
Ensure that the information in the IOSpecList properly matches the options specified on
the command line and rerun if necessary.

WARNING (TSY-551): Unable to obtain any information from the input pinmap file
pinmapfile. Either the file was empty, or there were warnings generated while processing
the contents of the file. Processing will continue without the pinmap file.
EXPLANATION:
Either the file was empty, or there were warnings generated while processing the
contents of the file.
USER RESPONSE:
Ensure that the pinmap file is in the correct format and rerun if necessary.
WARNING (TSY-552): Port portname in the pinmap file pinmapfile does not have the
corresponding package pin name specified.
EXPLANATION:
The ports in the pinmap file must have a corresponding package pin specified on the
same line.
USER RESPONSE:

Ensure the pinmap file is in the correct format and that a corresponding package pin is
specified for each port and rerun if necessary.
WARNING (TSY-553): Port portname already has the keyword pad specified and
therefore the pinmap keyword obtained from the pinmap file will be ignored.
EXPLANATION:
If both a pad and pinmap keyword are specified, the package pin will be obtained from
the pad keyword and the pinmap keyword will be ignored. The recommended method is
to consistently use only pad or pinmap keywords in a IOSpecList and not both.
USER RESPONSE:
Ensure only pad or pinmap keywords are used in the IOSpecList and rerun if necessary.
WARNING (TSY-554): Port portname in the IOSpecList has keyword CELL=cell that
does not match the library cell libcell inferred from the design. The inferred cell infcell
will be used.
EXPLANATION:
There is a mismatch between the cell specified in the IOSpecList and the one inferred
from the design. The cell from the design is used.
USER RESPONSE:
Ensure consistency between the cell specified in the IOSpecList and the one inferred
from the design and rerun if necessary.
WARNING (TSY-580): Unknown option option to generate_files and will be ignored.

EXPLANATION:
An invalid option has been specified.
USER RESPONSE:
Specify a valid option to the command to prevent this warning and rerun if necessary.
WARNING (TSY-581): OPMISR_PLUS_FANOUT missing in the IOSpeclist. The

OPMISR_PLUS assignfile will not contain MISR statements.
EXPLANATION:
The OPMISR_PLUS_FANOUT value is not specified in the IOSpeclist however
OPMISR_PLUS is specified in the IOSpeclist.
USER RESPONSE:

Include the value of OPMISR_PLUS_FANOUT in the IOSpeclist or specify the value of the
keyword OPMISR_PLUS as NO and rerun if necessary.
WARNING (TSY-582): The MISR size misr_size is not valid, setting 16 as the default
MISR size.
EXPLANATION:
The specified MISR size is invalid.
USER RESPONSE:
Correct the number of scan-in and scan-out ports so that size of the MISR is valid and
rerun if necessary.
WARNING (TSY-583): The tf_list value in the IOspeclist for the pin pinname has a
missing character =. The tf_list value will be ignored for this pin.
EXPLANATION:
The character = is missing in the tf_list value for the referenced pin in the IOSpeclist.
USER RESPONSE:
Correct the value in the tf_list for the referenced pin in the IOSpeclist and rerun if
necessary.
WARNING (TSY-584): Missing pair of brackets in the tf_list value in the IOspeclist for
the pin pinname. The tf_list value will be ignored for this pin.
EXPLANATION:
The tf_list specification for the referenced pin in the IOSpeclist does not include the
opening-closing pair of brackets.
USER RESPONSE:
Correct the value in the tf_list for the referenced pin in the IOSpeclist to avoid this
message and rerun if necessary.
WARNING (TSY-585): The flag flag in tf_list in the IOspeclist for the pin pinname
contains space character(s). The tf_list value will be ignored for this pin.
EXPLANATION:
The referenced flag in the tf_list for the referenced pin in the IOSpeclist contains one
or mre space characters.
USER RESPONSE:

Correct the referenced flag in the tf_list for the referenced pin in the IOSpeclist to
avoid this warning and rerun if necessary.
WARNING (TSY-586): The flag value flag_value in tf_list in the IOspeclist for the
pin pinname contains invalid character(s). The tf_list value will be ignored for this pin.
EXPLANATION:
The specified flag value in the tf_list for the referenced pin in the IOSpeclist contains
one or more invalid characters.
USER RESPONSE:
Correct the flag value in the tf_list for the mentioned pin in the IOSpeclist to suppress
this warning and rerun if necessary.
WARNING (TSY-587): Did not find SYS_ENAB port port even though port port had a
SYS_ENAB keyword specified with a value of value.
EXPLANATION:
If a BIDIR or OUTPUT3 port has a sys_enab keyword specified, a port with the same
name as the sys_enab keyword value must exist.
USER RESPONSE:
Ensure that if BIDIR or OUTPUT3 port has a sys_enab keyword specified, a port with
the same name as the sys_enab keyword value exists. This port controls the enable pin
on the iocell connected to the sys_enab port. Rerun if necesary.
WARNING (TSY-588): Port controlport has a BDY_USE of NONE and therefore will not
control port port. This is a violation of the 1149.1 standard because every tri-state output
having a data boundary cell must have an ENABLE boundary cell on it.
EXPLANATION:
Every tri-state output having a data boundary cell must have an ENABLE boundary cell
on it. Since the controlling port in this case has a BDY_USE of NONE, a boundary cell will
not be placed on it. This is a violation of the 1149.1 standard.
USER RESPONSE:
Remove the BDY_USE=NONE line for the controlling port in the iospeclist and rerun.
WARNING (TSY-589): Port port must have a keyword keyword and one has not been
specified.
EXPLANATION:

BIDIR and OUTPUT3 ports must have a SYS_ENAB kwd specified in the IOSpecList.
USER RESPONSE:
Ensure that the port in question has either a BIDIR or OUTPUT3 SYS_USE value and if
so, add the SYS_ENAB kwd to specify the port that controls the enable pin of the
connected iocell. Rerun if necessary.
WARNING (TSY-590): TOP_MODULE_SCAN is not set. DFT_SIGNAL_BOX will not be

inserted.
EXPLANATION:
The value of global keyword TOP_MODULE_SCAN is not set in the IOSpeclist.
USER RESPONSE:
Specify TOP_MODULE_SCAN=yes in the IOSpeList to enable insertion of
DFT_SIGNAL_BOX and rerun if necessary.
WARNING (TSY-591): The keyword TOP_MODULE_SCAN in the IOSpeclist is set to an

invalid value. The default value of NO will be used.
EXPLANATION:
Global keyword TOP_MODULE_SCAN is set to an invalid value in the IOSpeclist.
USER RESPONSE:
Specify TOP_MODULE_SCAN=yes in the IOSpeList to insert top module scan and rerun
if necessary.
WARNING (TSY-592): The keyword JTAG_SCAN in the IOSpeclist is set to an invalid value.
Its value will be set to the value of TOP_MODULE_SCAN keyword instead.
EXPLANATION:
Global keyword JTAG_SCAN is set to an invalid value in the IOSpeclist.
USER RESPONSE:
Specify JTAG_SCAN=yes|no to override the default value and then rerun.
WARNING (TSY-593): The current RC version used is is prior to version 6.1. The
dft_pin_function attribute will be ignored.
EXPLANATION:
This RC version does not support the dft_pin_function attribute.

USER RESPONSE:
Use an RC version of 6.1 or higher to use this attribute.
WARNING (TSY-594): RC_message. Problem encountered while setting the attribute in

the line: line. This line, in the file file_name, will be ignored
EXPLANATION:
The referenced RC_message was generated while setting the required attribute in the
RC environment. The corresponding line in the referenced file will be ignored.
USER RESPONSE:
Whether the attribute is set on the correct object
Whether the object exists.
If necessary, correct the line and rerun.
ERROR (TSY-600): Error while parsing the Wrapper_Inline section in the CoreSpecList
file. Keywords and values should be separated only by an = sign. Make sure there are no
spaces between keywords and their values.
EXPLANATION:
Keywords and values must be separated only by an = sign, with no spaces in between.
USER RESPONSE:
Ensure only an = sign with no additionalspaces separate a keyword and its value and
rerun.

ERROR (TSY-601): Error while parsing the CoreSpecList file. No ports were found while
parsing the CoreSpecList file. Ensure that at least one port is specified in the CoreSpecList
file.
EXPLANATION:
The CoreSpecList must list at least one port on the core being wrapped.
USER RESPONSE:
Ensure the CoreSpecList file describes at least one core port and rerun.

ERROR (TSY-602): Error while parsing the Wrapper_Inline section in the CoreSpecList file.
There is an INSTRUCTION line in the Wrapper_Inline section without the keyword NAME
associated with it. Ensure that every line in the Wrapper_Inline section that describes an
instruction has a name associated with it.
EXPLANATION:
It is mandatory to reference the instruction name while describing an instruction in the
Wrapper_Inline section using the reserved word INSTRUCTION. Use the keyword
NAME to specify the name of the described instruction.
USER RESPONSE:
Add the instruction name using the keyword NAME and rerun.
ERROR (TSY-603): Error(s) encountered while processing the CoreSpecList file. Refer to
previous messages for more details.
EXPLANATION:
One or more errors were encountered while parsing the information in the CoreSpecList
file.
USER RESPONSE:
Correct the errors described in the preceding messages and rerun.
ERROR (TSY-604): Incorrect version of RTL Compiler. The command_name command

requires RTL Compiler version version_number or later. Ensure a valid version of RTL
Compiler is available and specified in the PATH environment variable and rerun.
EXPLANATION:
The referenced command requires a compatible RTL Compiler
USER RESPONSE:
Ensure that a valid version of RTL Compiler is available and the location of its executable
is included in the PATH environment variable, and then rerun the command.
ERROR (TSY-605): The COMPRESSION macro has not been generated since the command
option SPACECOMPACTOR equals no. The WP_INTEST_COMPRESSION instruction cannot be
implemented. Either remove the WP_INTEST_COMPRESSION instruction from the SpecList or
use the correct command options when running this command.
EXPLANATION:
To implement the WP_INTEST_COMPRESSION instruction, specify the keywords
spacecompactor, numchains, and numchannels.

USER RESPONSE:
To implement the WP_INTEST_COMPRESSION instruction, use the correct command
options and rerun.
ERROR (TSY-606): Unable to locate file, filename, containing the RTL for the
COMPRESSION macro. The WP_INTEST_COMPRESSION instruction cannot be implemented.
Ensure the proper command-line options for compression macro generation have been used
when running this command and no errors/warnings encountered during generation of the
COMPRESSION macro.
EXPLANATION:
The program expected that file filename would contain the COMPRESSION macro but
the specified file was not found.
USER RESPONSE:
Ensure that proper command options have been specified and there are no preceding
errors or warnings and rerun.
ERROR (TSY-607): The number, numwpi, of Wrapper Parallel Input or Output terminals
specified in the input SpecList must match the value, numchains, of the numchains
option on the command line.
EXPLANATION:
The number of WPI/WPO terminals should match the number of scan chains on the
COMPRESSION macro. The number of scan chains on the COMPRESSION macro are
specified using the numchains command. Currently all the WPI/WPO terminals must be
used for the instruction during which the COMPRESSION macro is active.
USER RESPONSE:
Ensure the number of WPI/WPO terminals match the value of the numchains
command-line option and rerun.
ERROR (TSY-608): Command-line options have been specified for generation of the
COMPRESSION macro, but the input SpecList needs to contain the
WP_INTEST_COMPRESSION instruction for the COMPRESSION macro to be connected.
EXPLANATION:
The COMPRESSION macro will be inserted and stitched into the wrapper shell only if the
WP_INTEST_COMPRESSION instruction is specified in the Wrapper_Inline section in
the input CoreSpecList.
USER RESPONSE:

Ensure that the specified instruction is present in the SpecList and rerun.
ERROR (TSY-609): Number of scan chains, numscanchains, within the core and
specified in the SpecList must match the value, numchannels, of the numchannels option
on the command line.
EXPLANATION:
The number of scan chains within the core are the channels for the COMPRESSION
macro. Therefore, the number of core scan chains specified in the input SpecList must
match the value of the numchannels option used to build the COMPRESSION macro.
USER RESPONSE:
Ensure the number of core scan chains match the value of the numchannels command-
line option and rerun.
ERROR (TSY-610): Number of core scan chains must be greater than 0 for the
instructionname instruction to be implemented.
EXPLANATION:
Since the specified instruction is used to test the core scan chains as well, there must be
non-zero number of core scan chains present in the core and defined in the SpecList.
USER RESPONSE:
Ensure the core has non-zero number of scan chains or remove this instruction name
from the Wrapper_Inline section of the SpecList and rerun.
ERROR (TSY-650): [Internal] An unexpected condition occurred in the Encounter Test

CoreSpecList processing code. Contact customer support to report this error and provide the
following information: error occurred on line 3943 of source file
process_corespeclist.tcl. Unknown option option_name was used while invoking
process_corespeclist.
EXPLANATION:
USER RESPONSE:

customer support.

CoreSpecList processing code. Specify a unique opcode for instruction
instruction_name and rerun. Contact customer support to report this error and provide
the following information: error occurred on line 1722 of source file
process_corespeclist.tcl. Unable to generate a unique opcode for instruction
instruction_name.
EXPLANATION:
USER RESPONSE:
customer support.

CoreSpecList processing code. Specify instruction instruction_name and the
appropriate testmode flag in the TESTMODE_ACTIVESTATE keyword list of port
port_name. Contact customer support to report this error and provide the following
information: error occurred on line 6379 of source file process_corespeclist.tcl. Did
not find instruction instruction_name in the TESTMODE_ACTIVESTATE keyword list of
port port_name.
EXPLANATION:
USER RESPONSE:

customer support.

process_corespeclist.tcl. Encountered unknown non-core control signal
signal_name.
EXPLANATION:
USER RESPONSE:
customer support.

process_corespeclist.tcl. Scan chain input input_port should have been found
in the list port_list.
EXPLANATION:
USER RESPONSE:

customer support.

CoreSpecList processing code. Remove the keyword keyword_name on register
register_name in the Wrapper_Inline section and rerun this command. Contact
customer support to report this error and provide the following information: error occurred on
line 961 of source file process_corespeclist.tcl. Have encountered keyword
keyword_name on register register_name for which no processing is done in the code.
EXPLANATION:
USER RESPONSE:
customer support.

CoreSpecList processing code. Use the CORE_TEST_USE keyword to specify the scan output
port for scan input port port_name during instruction instruction_name and rerun this
command. Contact customer support to report this error and provide the following
information: error occurred on line 2331 of source file process_corespeclist.tcl. No
corresponding scan output port for scan input port port_name during instruction
instruction_name.
EXPLANATION:

USER RESPONSE:
customer support.

following information: error_info
EXPLANATION:
USER RESPONSE:
customer support.
ERROR (TSY-659): The port port_name has an invalid value for the keyword
keyword_name.
EXPLANATION:
When the value of dft_processing is linkage or image_unwired, a port cannot
have a value of the specified keyword keyword_name other than NONE.
USER RESPONSE:

Either do not specify this keyword for this port or assign it a value of NONE in the
IOSpeclist and then rerun.

boundary scan processing code. Contact customer support to report this error and provide
the following information: error_info
EXPLANATION:
USER RESPONSE:
customer support.
WARNING (TSY-670): The command option option is not a recognized option for the
Connection File Parser API proc_name and will be ignored.
EXPLANATION:
The specified command option for the referenced Connection File Parser API is invalid.
The program will ignore the option while executing the command.
USER RESPONSE:
Specify the correct option for the API and rerun.
WARNING (TSY-671): Parse error at line line_number in the connection file. The
attribute statement is invalid and will be ignored.
EXPLANATION:
The attribute statement at the referenced line number in the connection file does not
follow the correct syntax. The program will ignore the specified attribute statement while
executing the command.
USER RESPONSE:
Use correct syntax for the attribute statement and rerun.

WARNING (TSY-672): Parse error in statement starting at line line_number in the

connection file. The attribute name is invalid and the statement will be ignored.
EXPLANATION:
The attribute statement at the referenced line number in the connection file does not
USER RESPONSE:
WARNING (TSY-673): Parse error in attribute statement starting at line line_number in

the connection file. The word o is missing and the statement will be ignored.
EXPLANATION:
The word of is missing from the required position in the specified attribute statement in
the connection file. The program will ignore the specified attribute statement while
USER RESPONSE:
Use correct syntax for the port name in the attribute statement and rerun.

the connection file. The port name is invalid and the statement will be ignored.
EXPLANATION:
The port name in the specified attribute statement in the connection file does not follow
the correct syntax. The program will ignore the specified attribute statement while
USER RESPONSE:
Use correct syntax for the port name in the attribute statement and rerun.

the connection file. The instance name is invalid and the statement will be ignored.
EXPLANATION:
The instance name in the specified attribute statement in the connection file does not
USER RESPONSE:

Use correct syntax for the instance name in the attribute statement and rerun.

the connection file. The word is is missing and the statement will be ignored.
EXPLANATION:
The word is is missing from the required position in the specified attribute statement in
the connection file. The program will ignore the specified attribute statement while
USER RESPONSE:

connection file. The port attribute attribute_name for the facility facility_name and
instance instance_name already exists in the database. The statement will be ignored.
EXPLANATION:
The referenced port attribute, facility and instance name combination already exists in
the connection file database. The program will ignore the specified attribute statement
while executing the command.
USER RESPONSE:
Check the connection file for duplicate attribution of the same object with a different value

connection file. The top level port attribute attribute_name for the facility
facility_name already exists in the database. The statement will be ignored
EXPLANATION:
This top level port attribute and facility name pair already exists in the connection file
database.The program will ignore the specified attribute statement while executing the
command.
USER RESPONSE:

connection file. The attribute expression is invalid and the statement will be ignored.
EXPLANATION:

The attribute expression for the specified attribute statement is invalid.The program will
ignore the specified attribute statement while executing the command.
USER RESPONSE:
Use correct syntax for the attribute expression and rerun.

connection file. The instance attribute attribute_name for the instance
instance_name already exists in the database. The statement will be ignored
EXPLANATION:
The referenced instance attribute and instance name pair already exists in the
connection file database.The program will ignore the specified attribute statement while
USER RESPONSE:
WARNING (TSY-681): Parse error in statement starting at line line_number. The top
level attribute attribute_name already exists in the database. The statement will be
ignored.
EXPLANATION:
The referenced top level attribute already exists in the connection file database. The
program will ignore the specified attribute statement while executing the command.
USER RESPONSE:
Use another attribute in the statement and rerun.

connection file. The statement is invalid and will be ignored.
EXPLANATION:
The specified statement located at the referenced line number is not valid.The program
will ignore the specified attribute statement while executing the command.
USER RESPONSE:
Use correct syntax for the statment and rerun.
WARNING (TSY-683): Parse error in connection file in statement starting at line

line_number near the end of the statement. The statement will be ignored

EXPLANATION:
A syntax error was detected near the end of the specified statement. The program will
ignore the statement while executing the command.
USER RESPONSE:

line_number around error_token. The statement will be ignored.
EXPLANATION:
A syntax error was detected in this statement near the referenced token of the statement.
The program will ignore the statement while executing the command.
USER RESPONSE:
WARNING (TSY-685): Parse error in connection file at line line_number. The module
name module_name is invalid. The statement will be ignored.
EXPLANATION:
The referenced module name in the specified attribute statement in the connection file
does not follow the correct syntax.The program will ignore the statement while executing
the command.
USER RESPONSE:
Use correct syntax for the module name and rerun.
WARNING (TSY-686): A second port map for instance instance_name used with a
different module module_name found on line line_number while processing the
connection file. The statement will be ignored.
EXPLANATION:
The referenced instance name in the specified statement is already in the connection file
database with a different module name. The program will ignore the port map statement
while executing the command.
USER RESPONSE:
Use a different instance in the statement or use the existing instance and module pair
from the connection file database and then rerun.

WARNING (TSY-687): A second port map for instance instance_name found on line
line_number while processing the connection file. Will continue processing the ports in
the second port map as if they were part of the first port map statement.
EXPLANATION:
The instance and module pair used in this port map statement already exists in the
connection file database. The program will process the ports in this statement as if they
were part of the first port map statement.
USER RESPONSE:
No response is required if this is the intent. If this is not the intent, consider the following
scenarios
If the ports must be processed as part of some other instance, change the
instance name and rerun.
It is also possible that the -noclear option was used with the command
::confile::read_confile and the connection file database already
contains the data for this instance. Rerunning without specifying this option may
remove this warning.
WARNING (TSY-688): Parse error in connection file at line line_number. The instance
name instance_name is invalid. The statement will be ignored
EXPLANATION:
The referenced instance name in the specified port map statement does not follow the
correct syntax. The program will ignore this statement while executing the command.
USER RESPONSE:
Use correct syntax for the instance name in the statement and rerun.
WARNING (TSY-689): Parse error in connection file at line line_number. Port

association list is missing from the port map statement for instance instance_name. The
EXPLANATION:
Port association list is missing from the specified port map statement. The program will
ignore this statement while executing the command.
USER RESPONSE:
Add the port association list to the port map statement and rerun.


line_number. The port association around error_token in the port map statement for
instance instance_name is invalid. This port asociation will be ignored.
EXPLANATION:
This port association for the specified statement does not follow the correct syntax. The
program will ignore this port association in the statement while executing the command.
USER RESPONSE:
Use correct syntax for the port association in the statement and rerun.

line_number. The port name port_name in the port map statement for instance
instance_name is invalid. This port association will be ignored.
EXPLANATION:
The referenced port name in this statement does not follow the correct syntax.The
USER RESPONSE:
Use correct syntax for the port name in the statement and rerun.

line_number.The port name port_name in the port map statement for instance
instance_name is invalid. This port association will be ignored.
EXPLANATION:
The referenced port name in this statement does not follow the correct syntax.The
USER RESPONSE:
Use correct syntax for the port name in the statement and rerun.

line_number for instance instance_name around module_pin_name. A port
association cannot connect module_pin_name to a top level pin and will be ignored
EXPLANATION:
The port association in the specified statement connects OPEN/VDD/GND/ZERO/ONE to
a top level pin. This is not allowed.The program will ignore this port association in the
statement while executing the command.

USER RESPONSE:
Use a valid module pin name in the statement and rerun.

line_number for instance instance_name. top_level_pin cannot have an index.
This port association will be ignored.
EXPLANATION:
OPEN/VDD/GND/ZERO/ONE cannot have an index. The program will ignore this port
association in the statement while executing the command.
USER RESPONSE:
Remove the index from OPEN/VDD/GND/ZERO/ONE and rerun.

line_number for instance instance_name. The module pin pin_name has already
been used and will be ignored.
EXPLANATION:
The referenced module pin name in the specified statement has already been used for
the same instance. The program will ignore this pin in the statement while executing the
command.
USER RESPONSE:
Replace the module pin in the statement and rerun.

line_number. Busses bus_name1 and bus_name2 in instance instance_name are
of unequal sizes. This port association will be ignored.
EXPLANATION:
These busses in the specified statement are of different sizes. The program will ignore
this port association in the statement while executing the command.
USER RESPONSE:
Use the same size top level bus and module bus in the statement and rerun.
WARNING (TSY-696): Unknown option option to ::confile::read_confile. The

option will be ignored.
EXPLANATION:

The specified command option for ::confile::read_confile is invalid. The

program will ignore the option while executing the command.
USER RESPONSE:
Specify a correct command and rerun.
WARNING (TSY-700): Input pin iocell_in_full for port port_name is connected to

driver by iopinin. The program has determined it should be connected to constant 1.
EXPLANATION:
The program has determined the connection after detecting an inconsistency between
the specified iopinin value and the specified iocell pin connection.
USER RESPONSE:

WARNING (TSY-701): Iocell iocell_instance output pin iocell_out is already
connected by iopinout.
EXPLANATION:
The specified value for the iopinin keyword in the IOSpecList has driven the program
to connect the referenced pin.
USER RESPONSE:
WARNING (TSY-702): Enable pin iocell_enable_full for port port_name is

connected to driver by the iopinin keyword. The program has determined it should be
connected to constant 0.
EXPLANATION:
USER RESPONSE:

WARNING (TSY-703): Enable pin iocell_enable_full for port port_name is

connected to driver by the iopinin keyword. The program has determined it should be
connected to constant 1.
EXPLANATION:
USER RESPONSE:
WARNING (TSY-704): Connection file processing can not connect inst_pin_full and
CFB_pin_full.
EXPLANATION:
The referenced pins cannot be connected.
USER RESPONSE:
WARNING (TSY-705): Functional port port_name does not have the cell or bdy_use
keyword. Adding bdy_use=NONE; a boundary cell will not be inserted for this port
EXPLANATION:
The program is taking the actions described in the message text.
USER RESPONSE:
WARNING (TSY-706): Cannot find the hookup pin in the model for
test_in_hookup=test_in_hookup of port port_name.
EXPLANATION:
The program is unable to find the referenced pin in the model for the referenced port
name.
USER RESPONSE:
WARNING (TSY-707): Port port_name iopinin has two different signals:

existing_signal signal_name for one pin pin_name, honoring the first signal
existing_signal.

EXPLANATION:
The program has detected differing signals for the referenced port and is using the first
signal.
USER RESPONSE:
WARNING (TSY-708): iopinin does not find signal signal_name to connect.

EXPLANATION:
A signal must be created in order for the iopinin detect it.
USER RESPONSE:
WARNING (TSY-709): iopinin does not find pin pin_name on iocell instance
iocell_instance.
EXPLANATION:
The program is unable to find the referenced pin on the referenced iocell instance.
USER RESPONSE:
WARNING (TSY-710): Will overwrite command line specified core instance name
core_instance with connection file core instance name this_core_instance.
EXPLANATION:
The core instance name specified in the connection file supercedes the core instance
name specified on the command line.
USER RESPONSE:
WARNING (TSY-711): IO Cell Input pin iocell_in_full for port port_name is

already connected to driver by iopinin processing.
EXPLANATION:
The warning is issued because the iopinin statement is same as the code default
behavior..

USER RESPONSE:
Ensure the iopinin statement is correctly specified and rerun if necessary.
WARNING (TSY-712): Signal net in the connection file does not have a sink and will be
deleted from the model.
EXPLANATION:
A sinkless net is specified in the connection file.
USER RESPONSE:
No response is required if this is the expected result. If unexpected, ensure the content
of connection file and/or the IoSpecList are complete and rerun if necessary.
WARNING (TSY-713): The port port_name has an invalid value for the keyword
dft_processing. Valid values are ignore, linkage and image_unwired.
EXPLANATION:
An invalid value for the keyword dft_processing has been specified in the IOSpeclist
for the reference portname.
USER RESPONSE:
Correct the keyword value in the IOSpeclist and rerun.
WARNING (TSY-714): The port port_name has an invalid value for the keyword
keyword_name. .
EXPLANATION:
When the value of dft_processing is linkage or image_unwired, a port cannot
have a value other than NONE for of the referenced keyword.
USER RESPONSE:
Either do not specify this keyword for this port or assign it a value of NONE in the
IOSpeclist and then rerun.
WARNING (TSY-715): The port port_name must have a valid library cell as the value for
keyword cell in the IOSpeclist.
EXPLANATION:
When the value of keyword iopinin or iopinout is specified for a port, the keyword
cell must have a valid cell name as its value.
USER RESPONSE:

Specify a valid cell for the referenced port in the IOSpeclist and rerun.
WARNING (TSY-716): The cell cell_name is not a valid cell. The port port_name must
have a valid library cell as the value for keyword cell in the IOSpeclist.
EXPLANATION:
The specified cell name in the IOSpeclist for this port is not a valid cell.
USER RESPONSE:
Specify a valid cell for the referenced port in the IOSpeclist and rerun.
WARNING (TSY-717): The pin pin_name specified in the value for keyword
keyword_name in port port_name is not a valid pin for cell cell_name.
EXPLANATION:
The pin name specified in the iopinin/iopinout keyword of this port in the IOSpeclist
does not exist on the cell for this port.
USER RESPONSE:
Specify a valid pin for the referenced cell name and rerun.
WARNING (TSY-718): The pin pin_name specified in the value for keyword
keyword_name in port port_name is not an direction pin.
EXPLANATION:
The direction of the specified pin is incorrect. In the IOSpeclist, the direction of pins
specified by iopinin keyword must be input and by iopinout keyword must be
output.
USER RESPONSE:
Use an appropriate pin with the correct direction and rerun.
WARNING (TSY-719): The variable IMPLICIT_SI_MACRO_TEST_CONNECTIONS is set.

The connection file dft_signal_box_name pin pin_name connected to net
mt_net_name does not conform to the standard name. An additional pin on
dft_signal_box_name named new_pin_name is being connected to this net.
EXPLANATION:
The referenced pin is connected to a Scan-In Macro Test net and it does not conform to
the standard name. A new pin on the referenced dft_signal_box is being connected
to this Macro Test net while also preserving the connection to the specified pin.

USER RESPONSE:
To avoid this warning message, use a pin with a standard name and rerun. Otherwise,
no response is required.
WARNING (TSY-720): Unmatched double quote in tf_list value for pin pin_name. The
tf_list value will be ignored for ths pin.
EXPLANATION:
The program detected an unmatched double quote instead of a pair of quotes in the
value of keyword tf_list for the referenced pin. The value for tf_list will be ignored
for this pin.
USER RESPONSE:
Correct the tf_list value for the referenced pin in the IOSpecList and rerun.
WARNING (TSY-721): Extra characters are present between a double quote and the next
comma in tf_list value for pin pin_name. The tf_list value will be ignored for this pin.
EXPLANATION:
The tf_list value for the referenced pin contains some invalid characters between the
end of a double quote and the next comma.
USER RESPONSE:
WARNING (TSY-722): Extra characters are present after a double quote before the end of
value of keyword tf_list for pin pin_name. The tf_list value will be ignored for this
pin.
EXPLANATION:
The tf_list value for the specified pin contains some invalid characters between the
end of a double quote and the end of tf_list value.
USER RESPONSE:
WARNING (TSY-723): The flag flag_name in tf_list value for the pin pin_name
contains invalid character(s). The tf_list value will be ignored for this pin.
EXPLANATION:

The referenced flag in tf_list value for the referenced pin contains some invalid
characters.
USER RESPONSE:
INFO (TSY-800): Creating file_description file_name

EXPLANATION:
The command will attempt to create the file/directory named in the message.
USER RESPONSE:
INFO (TSY-801): Generating a script for command_name.

EXPLANATION:
The insert_scan command is automatically generating a BuildGates or RTL COmpiler
script file based on the provided inputs. The script file is intended to be used as input to
BuildGates or RTL Compiler for scan insertion.
USER RESPONSE:
INFO (TSY-802): command completed successfully.

EXPLANATION:
The insert_scan command successfully created a BuildGates or RTL Compiler script.
USER RESPONSE:
INFO (TSY-803): Edif format requires the design to be mapped to the library before being
saved. A simple mapping will be performed.
EXPLANATION:
The Edif format cannot be used without tech-mapping the design. The techmap will be
set to 1 and processing will continue.
INFO (TSY-804): Launching command_name processing.

EXPLANATION:

The command is forking an instance of the indicated program.

USER RESPONSE:
INFO (TSY-805): command_name processing completed successfully.

EXPLANATION:
This message indicates that scan insertion processing completed without errors.
USER RESPONSE:
INFO (TSY-806): Launching process_name processing.

EXPLANATION:
The command is forking an instance of the program referenced in the message.
USER RESPONSE:
INFO (TSY-807): Encounter Test Synthesis processing completed successfully.

EXPLANATION:
The Encounter Test Synthesis processing required by the command was successful.
USER RESPONSE:
INFO (TSY-808): The command command is using IOSpecList file filename for
processing.
EXPLANATION:
Names the file command is using as the IOSpecList.
USER RESPONSE:
INFO (TSY-809): command script generation completed successfully.

EXPLANATION:

Script generation for the specified command (BuildGates or RTL Compiler ) completed
successfully.
USER RESPONSE:
INFO (TSY-810): Both executescript and exemode=script were specified. Overriding

exemode to be batch. Specify exemode=batch (the default) to suppress this message.
EXPLANATION:
The exemode=script option normally exits insert_scan after script generation but
before it is executed. Specifying both executescript and exemode=script would
cause the insert_scan command to exit before executing the script, that is, to nothing.
Since this is not useful, the exemode=batch option is set.
USER RESPONSE:
INFO (TSY-811): Using existing OPMISR RTL macro: file.

EXPLANATION:
Normally insert_scan will generate RTL verilog for the OPMISR+ macro. If the RTL
file already exists it will reuse that file instead of overwriting it. This allows customized
OPMISR+ macros to be used.
USER RESPONSE:
INFO (TSY-812): IO SpecList data of type $iospec2::type is erased from the memory.
EXPLANATION:
IO IOSpecList of the specified type was successfully erased from the memory.
USER RESPONSE:
INFO (TSY-813): IO SpecList file $filename1 is read into memory.

EXPLANATION:
IO IOSpecList of the specified type was successfully read into memory.
USER RESPONSE:

INFO (TSY-814): IO SpecList of type $type_temp is written to : $filename2.

EXPLANATION:
IO IOSpecList of the specified type was successfully written to the specified file.
USER RESPONSE:
INFO (TSY-815): A bsdl file will be written to directory.

EXPLANATION:
Either a dummy or a normal BSDL file was successfully written.
USER RESPONSE:
INFO (TSY-816): The numchains, scanins, or misrsize option has been specified.
Command options will be used to control the scan insertion process.
EXPLANATION:
If an IOSpecList has been specified, it will be ignored and scan configuration will be taken
from specified keyword values.
USER RESPONSE:
To drive scan configuration from the IOSpecList, exclude keyword specifications for
numchains, scanins, or misrsize and rerun. If the specified keyword values are
acceptable, no response is required.
INFO (TSY-817): An IOSpecList was specified either via command or in global data. It will
be ignored.
EXPLANATION:
If an IOSpecList has been specified, it will be ignored and scan configuration will be taken
from specified keyword values.
USER RESPONSE:
To drive scan configuration from the IOSpecList, exclude keyword specifications for
numchains, scanins, or misrsize and rerun. If the specified keyword values are
acceptable, no response is required.

INFO (TSY-818): An output filetype file has been generated and written to filename.
EXPLANATION:
A file of the reference type and name has been generated.
USER RESPONSE:
INFO (TSY-819): Global Data has been updated as if the generated scan insertion script
was run.
EXPLANATION:
The scriptonly option was specified for insert_scan. This option generates a scan
insertion script but does not execute it. Encounter Test makes the assumption that you
will run the script before proceeding to the next step. If you do not run the script, the scan
inserted netlist may not exist and may cause subsequent steps to fail.
USER RESPONSE:
Run the scan insertion script to completion before proceeding.
INFO (TSY-820): Port port_name appears to be a test_signal, however the keywords

are not defined. Skipping defining this port as a test_signal for scan insertion.
EXPLANATION:
When TOP_MODULE_SCAN=NO, test_use=SE and TE ports need either the
core_test_in or sys_in keywords to specify the name of the core port. For other test
signals, one of core_test_in, test_in, or sys_in is used to specify the name of the
core port.
RC cannot define the test signal without the name of the port, .
USER RESPONSE:
If this signal must be defined as a test signal in the RC session, specify the required
keywords in the IOSpecList and rerun.
INFO (TSY-821): Using test signal port to fix internal clock DFT violations.
EXPLANATION:
This test signal will be used to automatically fix internal clocking DFT violations found by
RC.
USER RESPONSE:

If you do not want such violations fixed, set the defaultviolationfixing keyword
option to no, remove any fixtestmode and fixclock keywords from the IOSpecList,
and then rerun.
INFO (TSY-822): Using port port to fix uncontrolled asynchronous violation_type

DFT violations.
EXPLANATION:
This test signal will be used to automatically fix uncontrolled asynchronous set/reset DFT
violations found by RC.
USER RESPONSE:
If you do not want such violations fixed, set the defaultviolationfixing keyword
option to no, remove any fixasyncset and fixasyncreset keywords from the
IOSpecList, and then rerun.
INFO (TSY-823): Inserting scan on module module, design design.

EXPLANATION:
This module is targeted for scan insertion.
USER RESPONSE:
If desired, specify the module keyword to target a different top level module for scan
insertion and then rerun.
INFO (TSY-824): Selecting port port test_signal.

EXPLANATION:
This port is selected for the specified purpose.
USER RESPONSE:
INFO (TSY-840): The netlist is written out in the default format (Verilog).
EXPLANATION:
The netlist will be written using the Verilog HDL format.
USER RESPONSE:

INFO (TSY-841): A Macro Isolation Control (MIC) file used for Test Data Migration will not
be generated.
EXPLANATION:
The command will NOT write out a Macro Isolation Control (MIC) file. The MIC file is
useful only if planning to use Encounter Tests Test Data Migration features. Write a MIC
file by specifying the writemic keyword of the build_1500_wrapper command.
USER RESPONSE:
INFO (TSY-842): A Data Sheet is generated.

EXPLANATION:
The command will write out a Data Sheet file. This file is useful when instantiating this
wrapped core inside an SoC.
USER RESPONSE:
INFO (TSY-843): The wrapper netlist is generated.

EXPLANATION:
The wrapper is created around the design and the netlist is written out with the
appropriate wrapper logic. If scriptonly=yes is specified, only the wrapper
configuration is displayed; the wrapper logic will not be generated.
USER RESPONSE:
INFO (TSY-844): No Technology Libraries have been specified.

EXPLANATION:
There were no specified Technology Libraries
to which the wrapper logic can be mapped. The wrapper logic will not be tech-mapped.
USER RESPONSE:
INFO (TSY-845): The wrapper logic will not be technology mapped.

EXPLANATION:
The wrapper logic that has been inserted will NOT be mapped to any Technology Library
due to one of the following conditions:
Technology Libraries are not provided
The keyword value techmap=no was specified.
If the synlibs=tech_lib keyword is specified, the default behavior is to map the
wrapper logic to the specified tech_lib library.
USER RESPONSE:
INFO (TSY-846): The wrapper logic will be tech mapped.

EXPLANATION:
The inserted wrapper logic will be mapped to the Technology Library specified by
synlibs=tech_lib keyword.
USER RESPONSE:
INFO (TSY-847): The command command is using CoreSpecList file file_name for
processing.
EXPLANATION:
The referenced command is using the referenced file as the CoreSpecList.
USER RESPONSE:
INFO (TSY-848): The wrapper netlist is be generated.

EXPLANATION:
The configuration of the wrapper is displayed; the wrapper logic is not inserted. This
enables verification that the desired wrapper is generated without actually modifying the
design netlist.
USER RESPONSE:
View the wrapper configuration to verify that the desired wrapper will be generated
without actually modifying the design netlist.

INFO (TSY-849): Setting misrsize to misr_size based on numchains

numchains_value and scanio scanio_value.
EXPLANATION:
The program determines the setting for the misrsize based on the specified values for
numchains and scanio.
USER RESPONSE:
INFO (TSY-850): Setting numchains to numchains_value based on misrsize

misrsize_value and scanio scanio_value.
EXPLANATION:
The program determines the setting for numchains based on the specified values for
misrsize and scanio.
USER RESPONSE:
INFO (TSY-851): An IOSpecList with TOP_MODULE_SCAN=YES has been specified. The

DFT_SIGNAL_BOX (instance name name) will be used to control the scan insertion process.
EXPLANATION:
The nets connected to the DFT_SIGNAL_BOX instance will be used as scan chain begin
and end points. Other connected nets specify the scan enable signal and signals used
to fix DFT rules violations.
USER RESPONSE:
INFO (TSY-852): The IOSpecList filename has been specified or was set in global data.
It will be used to control the scan insertion process.
EXPLANATION:
The scan chain configuration will be extracted from the IOSpecList. Based on test_use
values, some ports will be used as scan chain begin and end points. Other ports specify
the scan enable signal and signals used to fix DFT rules violations.
USER RESPONSE:

INFO (TSY-853): Using existing space compactor RTL macro: filename.

EXPLANATION:
An existing space compactor macro was detected in the specified output directory for the
netlist and will be used in place of the one that would normally be generated.
USER RESPONSE:
INFO (TSY-870): Generating the assignfile filename.

EXPLANATION:
The program is attempting to the referenced assign file.
USER RESPONSE:
INFO (TSY-875): Connection file filename is read into memory.

EXPLANATION:
The connection file specified as an argument for ::confile::read_confile is
parsed and read into memory.
USER RESPONSE:
INFO (TSY-900): Total number of functional ports on the wrapper is num_ports.

EXPLANATION:
The number of functional ports on the wrapper is displayed.
USER RESPONSE:
INFO (TSY-901): The wrapper netlist file is filename.

EXPLANATION:
The name of the file containing the wrapper netlist is identified.
USER RESPONSE:

INFO (TSY-902): The name of the core being wrapped is module_name.

EXPLANATION:
The name of the core being wrapped is identified.
USER RESPONSE:
INFO (TSY-903): The name of the wrapper module is module_name.

EXPLANATION:
The name of the module that contains the wrapper logic and that instantiates the core is
identified.
USER RESPONSE:
INFO (TSY-904): The default wrapper boundary cell is module_name.

EXPLANATION:
The default wrapper boundary cell type is identified.
USER RESPONSE:
INFO (TSY-905): Total number of valid port declarations in the CoreSpecList file is
num_ports.
EXPLANATION:
The number of valid ports descriptions present in the CoreSpecList file is stated.
USER RESPONSE:
INFO (TSY-906): Test clock port_name must be controlled to a safe value during
instructions that do not test the core. This should be done while instantiating this wrapped
core.
EXPLANATION:
Test clocks must be controlled to a safe value during functional mode.
USER RESPONSE:

INFO (TSY-907): The number of instructions that are implemented is

num_instructions.
EXPLANATION:
The number of instructions that are implemented is stated. Note that this may be less or
more than the number of instructions specified in the CoreSpecList. Some of the
specified instructions may have been ignored. If so, some of the earlier messages may
provide related information. Also, additional instructions mandated by the standard may
have been implemented.
USER RESPONSE:
INFO (TSY-908): The number of parallel instructions is num_instructions.

EXPLANATION:
The number of wrapper parallel instructions that will finally be implemented is stated.
Note that this may be less or more than the number of specified parallel instructions in
the CoreSpecList. Some of the specified parallel instructions may have been ignored. If
so, some of the earlier messages may provide related information.
USER RESPONSE:
INFO (TSY-909): The length of the Wrapper Instruction Register is number bits.
EXPLANATION:
The length of the Wrapper Instruction Register (WIR) is the same as the length of the
instruction opcodes.
USER RESPONSE:
INFO (TSY-910): The number of core scan chains specified in the CoreSpecList is
num_chains.
EXPLANATION:
The number of scan chains described in the CoreSpecList is stated.
USER RESPONSE:

INFO (TSY-911): Writing the DataSheet file file_name.

EXPLANATION:
The DataSheet file is identified. The DataSheet file contains useful information about the
wrapped core.
USER RESPONSE:
INFO (TSY-912): Writing the Macro Isolation Control (MIC) data for the test_boundary
boundary to file file_name.
EXPLANATION:
The MIC file is written for the desired test boundary, that is, the boundary for which the
test vectors are generated. The test boundary can be either the core or the wrapper
boundary.
USER RESPONSE:
INFO (TSY-913): Finished processing the CoreSpecList information.

EXPLANATION:
The information in the CoreSpecList file has been read and parsed.
USER RESPONSE:
INFO (TSY-914): CoreSpecList file file_name does not contain a Wrapper_Inline

section. Default instructions and opcodes are implemented.
EXPLANATION:
The CoreSpecList file does not contain a Wrapper_Inline section. Default instructions
is implemented, and default opcodes are generated for those instructions. Refer to the
Customer-Specific User Guide for default instructions that are implemented.
USER RESPONSE:

INFO (TSY-915): The environment variable DFT_SIGNAL_BOX_NAME has been set to value
dft_signal_box.
EXPLANATION:
The value of environment variable DFT_SIGNAL_BOX_NAME is specified and a
DFT_SIGNAL_BOX will be created with the specified name.
USER RESPONSE:
INFO (TSY-916): The keyword DFT_SIGNAL_BOX_NAME has been set to value

dft_signal_box.
EXPLANATION:
The value of global keyword DFT_SIGNAL_BOX_NAME is specified and a
DFT_SIGNAL_BOX will be created with the specified name.
USER RESPONSE:
INFO (TSY-917): The keyword DFT_SIGNAL_BOX_NAME is not set. The default value of
DFT_SIGNAL_BOX will be used for test signal connections.
EXPLANATION:
Neither the keyword DFT_SIGNAL_BOX_NAME is specified in the IOSpeclist nor is the
environment variable DFT_SIGNAL_BOX_NAME set. The default value
DFT_SIGNAL_BOX will be used for test signal connections.
USER RESPONSE:
INFO (TSY-918): The gate dft_signal_box already exists.

EXPLANATION:
The gate with the specified name already exists in the design. The existing gate will be
used for test signal connections.
USER RESPONSE:
INFO (TSY-919): Creating DFT_SIGNAL_BOX with name dft_signal_box.

EXPLANATION:
The DFT_SIGNAL_BOX is being created with the referenced name.
USER RESPONSE:
INFO (TSY-920): Inserting the BSR Lockup Latches after the boundary cells.
EXPLANATION:
The BSR Lockup Latches are being inserted between neighboring boundary cells per the
specification of the IOspeclist global keyword DFT_BSR_LOCKUP_INSERTION.
USER RESPONSE:
INFO (TSY-921): Keyword dft_processing has been specified with the value ignore for
the ports ignored_ports. These ports have been ignored.
EXPLANATION:
The IOSpeclist statements for the referenced ports contain dft_processing=ignore.
The ports will be ignored.
USER RESPONSE:

73
TTA - Testability Measurements
Messages
TTA-001 through TTA-038 on page 2335
TTA-001 through TTA-038

WARNING (TTA-001): Unrecognized simulation function.
EXPLANATION:
A simulation function was not recognized. This particular block will be treated as an X
source. A logic primitive not supported by sequential test generation was specified.
USER RESPONSE:
Ensure that logic primitives used are supported by Encounter Test and rerun.
WARNING (TTA-002): The fault type of faultID faultindex is currently not supported by
this application.
EXPLANATION:
A fault type not supported by the application was encountered. Processing of this
particular fault will be skipped.
USER RESPONSE:
Ensure that fault types are supported by this application and rerun.
WARNING (TTA-004): Unable to get design context

EXPLANATION:
A call related to the logic model failed.
USER RESPONSE:

TTA - Testability Measurements Messages
Ensure that the Encounter Test logic model files exist.
WARNING (TTA-005): Unable to load design model

EXPLANATION:
The program was unable to load the logic model.
USER RESPONSE:
Ensure that the Encounter Test logic model files exist. If not, import the design and
continue processing. See Performing Import New Circuit in the Encounter Test:
Guide 1: Models for related information.
WARNING (TTA-006): Unable to set the test mode

EXPLANATION:
The test pattern generator was unable to set the test mode.
USER RESPONSE:
Ensure that the test mode has been defined and rerun
WARNING (TTA-007): Unable to load design access methods

EXPLANATION:
USER RESPONSE:
WARNING (TTA-012): Unable to access the fault model for faultID faultindex
EXPLANATION:
Unable to access the fault model for the specified fault.
USER RESPONSE:
WARNING (TTA-013): A program internal calculation limit was exceeded: flat nodeID
nodeID
EXPLANATION:
The specified flat node has exceeded an program internal calculation limit. This may
indicate unbroken feedback loops. As a result, computed data may not be accurate.

USER RESPONSE:
WARNING (TTA-014): Memory allocation error

EXPLANATION:
The program function failed to allocate the required memory. Try killing unnecessary
processes or running the program on a machine with more memory.
USER RESPONSE:
assistance.
EXPLANATION:
Error while accessing program parameters.
USER RESPONSE:
assistance.
WARNING (TTA-020): Unable to retrieve line hold information

EXPLANATION:
USER RESPONSE:
Ensure that a linehold file exists or that it is created correctly and rerun.
INFO (TTA-024): Open tableName model

EXPLANATION:
Allocating the storage for a program function.
USER RESPONSE:
INFO (TTA-025): Close tableName model

EXPLANATION:
Releasing the storage used by a program function.

USER RESPONSE:
INFO (TTA-026): Processing of subroutineName is started

EXPLANATION:
A program function processing is started.
USER RESPONSE:
INFO (TTA-027): Processing of subroutineName is completed

EXPLANATION:
A program function processing is completed.
USER RESPONSE:
No response required,
WARNING (TTA-028): Unsupported netType value

EXPLANATION:
A symbolic value was not recognized. This particular symbolic value will be treated as an
X. A symbolic value not supported by this program function was specified.
USER RESPONSE:
Ensure that symbolic values used are supported by Encounter Test and rerun.
INFO (TTA-030): Processing CPU time = cpuTime

EXPLANATION:
Reporting CPU time for a specified processing function.
USER RESPONSE:
INFO (TTA-031): Processing elapse time = elapsedTime

EXPLANATION:
Reporting elapse time for a specified processing function.

USER RESPONSE:
WARNING (TTA-032): Hier index object hierIndex and flat nodeID flatIndex failed
the TI stability check.
EXPLANATION:
The specified hier index object and flat nodes state is in the opposite of the stability state
during the TI Stability Check.
USER RESPONSE:
Ensure that the test mode specifications are correct and rerun.
the TG stability check.
EXPLANATION:
during the TG Stability Check.
USER RESPONSE:
Ensure that the test mode specifications are correct and rerun.
the TG state check.
EXPLANATION:
during the TG State Check.
USER RESPONSE:
Ensure that the test mode specifications are correct and then rerun.
WARNING (TTA-035): Forced hier index object hierIndex and flat nodeID flatIndex
has a transition to non-forced event value.
EXPLANATION:
The specified forced hier index object and flat node has a transition to a non-forced event
value during PVS simulation.
USER RESPONSE:

WARNING (TTA-036): Release hier index object hierIndex and flat nodeID
flatIndex is not justified to the forced value.
EXPLANATION:
The specified release hier index object and flat node is not justified to a previously forced
event value during PVS simulation.
USER RESPONSE:
WARNING (TTA-037): Trying to load faultID faultID while a previously loaded faultID
faultID has not been unloaded.
EXPLANATION:
Calculations for the previous fault have not been reset, which may cause error in
calculations for the fault to be processed.
USER RESPONSE:
Ensure that the previous fault is unloaded prior to loading a new fault.
INFO (TTA-038): Trying to unload a fault which has not been loaded.
EXPLANATION:
The unload cannot take place because no fault has been loaded for processing. The
unload process is skipped.
USER RESPONSE:
Ensure that the fault load/unload APIs are used in proper order.

74
TTC - Test Generation Controller
Messages
TTC-001 through TTC-050 on page 2341

TTC-001 through TTC-050

ERROR (TTC-001): WORKDIR was not specified and is a required parameter.
EXPLANATION:
The WORKDIR name was not specified. The run terminates.
USER RESPONSE:
Specify WORKDIR, either by exporting or on the command line, and rerun.
ERROR (TTC-003): TESTMODE was not specified and is a required parameter.

EXPLANATION:
The TESTMODE was not specified. The run terminates.
USER RESPONSE:
Specify TESTMODE, either by exporting or on the command line, and rerun.
ERROR (TTC-004): The committed fault model file fileName does not exist and is
required for the generation of testType tests. Execute build_faultmodel to assign the
desired faults.
EXPLANATION:

TTC - Test Generation Controller Messages
Stored Pattern Test generation requires a fault model. The run terminates.
USER RESPONSE:
Build a fault model, then rerun test generation.
ERROR (TTC-005): Could not open|restart from the uncommitted file fileName.
EXPLANATION:
Some condition exists which prevents access to the indicated uncommitted file. This
could be a permissions problem, a locking problem (that is, some other job is running on
this experiment), or a DASD problem. The run terminates.
USER RESPONSE:
Examine the accompanying messages and correct the problem.
ERROR (TTC-006): Value error for parameter parameter: value is not recognized.
EXPLANATION:
This message is issued whenever an error is encountered during the processing of the
command line. The parameter is ignored and the remainder of the command line is
checked for errors. The Stored Pattern Test Generation run will be terminated
immediately after command line checking is completed.
USER RESPONSE:
Either omit the parameter, or specify an allowed value and rerun.
WARNING (TTC-007): Parameter value is not supported.

EXPLANATION:
This message is issued for parameters that either have been discontinued, or are not yet
supported. The parameter is ignored and the run proceeds.
USER RESPONSE:
Either ignore this message, or omit the parameter and rerun.
ERROR (TTC-008): Unable to obtain shared use of the hierModel.

EXPLANATION:
During initialization, the Stored Pattern Test Generation attempts to obtain a shared lock
on the hierModel file, to ensure that no other applications try to rebuild the hierModel
during the run. If this fails, it means that some other application has already obtained an
exclusive use lock on this file. The run terminates.

USER RESPONSE:
Wait until the other application is complete and rerun. If there is no other application
running requiring exclusive use of the hierModel, this may be a program error. If possible,
start over by rebuilding the model.
ERROR (TTC-009): Unable to obtain exclusive use of experiment experiment.

EXPLANATION:
Stored Pattern Test generation requires exclusive use of the specified experiment since
it will be creating uncommitted files for that experiment. The run terminates.
USER RESPONSE:
Another application may be using this experiment. Either wait until the other application
is complete, or select another experiment name and rerun.
INFO (TTC-010): Stored Pattern Test Generation has been successfully restarted from
checkpoint ID = time/date stamp.
EXPLANATION:
This is an informational message indicating the Stored Pattern Test Generation
application has been successfully restarted from the indicated checkpoint. The run will
proceed according to RESTART option specified.
USER RESPONSE:
ERROR (TTC-011): Attempt to restart Stored Pattern Test Generation failed - no checkpoint
data detected.
EXPLANATION:
A restart option was specified however no checkpoint data was detected to use for a
restart. The run terminates.
USER RESPONSE:
Remove the restart option and rerun.
ERROR (TTC-012): Attempt to restart Stored Pattern Test Generation failed - the following
parameter(s) were changed: changed_keywords.
EXPLANATION:

A restart option was specified however the indicated parameters were changed and are
not permitted to be changed on a restart. The run terminates.
USER RESPONSE:
Remove the restart option or restore the original settings of the indicated parameters and
rerun.
ERROR (TTC-013): [Internal] Unable to register object objectName.

EXPLANATION:
USER RESPONSE:
Rebuild the model and rerun. If this does not fix the problem, contact customer support
ERROR (TTC-014): [Internal] Unable to establish|remove dependency for object

objectName.
EXPLANATION:
This is program error. The run terminates.
USER RESPONSE:
This indicates a problem with the globalData file. Rebuild the model and rerun. If this
on page 23).
ERROR (TTC-015): Unable to establish shared lock on name.

EXPLANATION:
This is a generic message indicating that Stored Pattern Test Generation was unable to
obtain a shared lock on an object. This is probably caused by another application having
an exclusive lock. The run terminates.
USER RESPONSE:
Wait until the other application is complete and rerun. If no other application is running
which requires an exclusive lock, there may be a program or system error.
WARNING (TTC-016): [Severe] verify_test_structures for Stored Pattern tests

has not been run | has not run all applicable checks. Poor test
coverage and/or invalid test data may result.

EXPLANATION:
Audit information indicates that either verify_test_structures has not been run or
not all Stored Pattern checks were performed.. Information normally provided by
verify_test_structuresto guide test generation is not available. Invalid design
structures can cause test coverage and performance to degrade.
Run continues.
USER RESPONSE:
Run verify_test_structures prior to Stored Pattern Test Generation to ensure that
the design does not contain severe errors which will impact testability.
ERROR (TTC-017): Cannot append to experiment experiment_name because

checkpoint data exists. The run terminates.
EXPLANATION:
The indicated experiment has Stored Pattern Test Generation checkpoint data
associated with it (a checkpoint having been taken in a previous run). Since an
experiment cannot be appended to while in a checkpointed state, and an attempt was
made to do so in this case (append=yes), the run terminates.
USER RESPONSE:
Specify append=no and rerun. The fate of the checkpoint data must be addressed via
the restart option. If restart=end is specified, the run will simply restore the
uncommitted files based on the checkpoint data, and leave the experiment in a state
conducive to future appends.
WARNING (TTC-018): [Severe]|Blank verify_test_structures issued

Warning|Severe messages related to Stored Pattern Test checks. Poor test
coverage and/or invalid test data may result.
EXPLANATION:
Audit information indicates that verify_test_structures detected errors of the
indicated severity. These could have the indicated effect on Stored Pattern Test
Generation. The run continues.
USER RESPONSE:
Correct the design conditions which are in deviation and rerun
verify_test_structures and Stored Pattern Test Generation.
ERROR (TTC-019): A delay model name was not specified for the testType test and is
required to produce a Timed vector format.

EXPLANATION:
The indicated tests are to be generated with timings, thus requiring the specification of a
delay model. A delay model name was not specified however. The run terminates.
USER RESPONSE:
Specify the name of a delay model to be used in the generation of the indicated tests or
specify a test format other than timed (e.g., dynamic) and rerun.
ERROR (TTC-020): An experiment name of TFA is not allowed.

EXPLANATION:
TFA is a reserved experiment name for use during fault analysis. The run terminates.
USER RESPONSE:
Respecify the experiment name and rerun.
ERROR (TTC-021): Unable to establish a shared lock on mode modeName.

EXPLANATION:
The mode modeName is unavailable at this time. The run terminates.
USER RESPONSE:
Another application may be running which has established an exclusive lock on the
mode. If this is the case, wait until the other application completes and rerun.
ERROR (TTC-022): EXPERIMENT was not specified and is a required parameter.

EXPLANATION:
The EXPERIMENT name was not specified. The run terminates.
USER RESPONSE:
Specify EXPERIMENT, either by exporting or on the command line, and rerun.
ERROR (TTC-023): Pseudo primary inputs were found in the design model, but no user
sequences were provided and timed tests were requested. The run terminates.
EXPLANATION:
only with the help of user-supplied sequences. Test generation could proceed on an
uncommitted basis using automatic sequences to exercise the pseudo primary inputs,
but timing generation is not supported in this situation.

USER RESPONSE:
Change some options and resubmit the run. You may either:
Specify one or more user-generated test sequences. The test sequences must
first be coded and imported using Read Sequences from the Tools-
Sequences-Read Definition pull-down unless this has already been done. If
you are not familiar with this process, see "Coding Test Sequences" in the
Request static or dynamic (not timed) tests.
ERROR (TTC-024): {parm1=parm1value} may not be specified in combination with

{parm1=parm1value}.
EXPLANATION:
The combination of {parm1=parm1value} and {parm2=parm2value} is
unacceptable. This is true whether specified on the command line or via the Graphical
User Interface. The parameter is ignored and the remainder of the command line is
checked for errors. The Stored Pattern Test Generation run will be terminated
immediately after command line checking is completed.
USER RESPONSE:
Modify the command line or change the selections made for the program via the
Graphical User Interface so that these parameters and values are not specified in this
combination and rerun.
ERROR (TTC-025): A Stored Pattern Test Generation run may not append|overwrite
an MTG experiment.
EXPLANATION:
Stored Pattern Test Generation was invoked with an EXPERIMENT name which
corresponds to an existing Macro Test Generation (MTG) experiment. Stored Pattern
Test Generation is not permitted to append or overwrite an MTG experiment. The run
terminates.
USER RESPONSE:
Specify an alternate EXPERIMENT name and rerun.
ERROR (TTC-026): Logic model file fileName does not exist.

EXPLANATION:

Stored Pattern Test Generation attempted to load the indicated model file but determined
the file does not exist. The run terminates.
USER RESPONSE:
Ensure the necessary pre-requisite steps have been performed (model import, test
mode define etc.), prior to rerunning Stored Pattern Test Generation.
ERROR (TTC-027): Test mode of modeName does not exist.

EXPLANATION:
Stored Pattern Test Generation was invoked with a TESTMODE name which does not
exist. The run terminates.
USER RESPONSE:
Specify the name of an existing test mode and rerun.
ERROR (TTC-028): Delay model name does not exist.

EXPLANATION:
Stored Pattern Test Generation was invoked with a delay model name which does not
exist. The run terminates.
USER RESPONSE:
Specify the name of an existing delay model file and rerun.
ERROR (TTC-029): The General Purpose Simulator does not support the creation of IDDq
tests.
EXPLANATION:
Stored Pattern Test Generation was invoked (in part), to create IDDq tests. However, the
General Purpose Simulator has been selected (simulation=gp), and does not support
the creation of IDDq tests. The run terminates.
USER RESPONSE:
The High Speed Scan Based Simulator must be used for the creation of IDDq tests.
Either differ the creation of IDDq tests (test=iddq=no), or specify
simulation=hsscan and rerun.
INFO (TTC-030): Processing of dynamic logic faults has been deselected because the
vector format is Static.
EXPLANATION:

Stored Pattern Test Generation was invoked to create tests for logic faults using a vector
format of Static. This format does not contain release and capture sections as a
Dynamic format, and therefore is not suited for the detection of dynamic faults.
Processing of dynamic logic faults has therefore been deselected. Processing continues.
USER RESPONSE:
If processing of dynamic logic faults is desired, change the vector format of these tests
(e.g., test=logic=dynamic), and rerun. Otherwise, disregard this message.
ERROR (TTC-031): A delay model was specified for the testType test but the vector
format is not Timed.
EXPLANATION:
Stored Pattern Test Generation was invoked to create non-timed (e.g., static, dynamic)
tests of indicated type (e.g., logic, I/O Wrap), however a delay model was also specified
for the indicated tests. This is an inconsistency which causes the run to terminate.
USER RESPONSE:
If non-timed tests are desired for the indicated test type, remove the appropriate
delaymodel=file specification and rerun. If timed tests are desired, ensure this is
appropriately specified and rerun.
ERROR (TTC-032): Failed to obtain a license to run productName.

EXPLANATION:
Stored Pattern Test Generation was invoked to run the indicated product, but was unable
to obtain the necessary license. The run terminates.
USER RESPONSE:
Ensure the availability of the necessary license or modify the invocation of Stored Pattern
Test Generation so the indicated product is not required, and rerun.
ERROR (TTC-033): A test vector format of Static was detected, but static logic faults have
not been selected for processing or there are no static faults defined by the test mode.
EXPLANATION:
Stored Pattern Test Generation was invoked to create static logic tests, however static
logic faults are not selected for test generation or there are no static faults for this test
mode. This is an inconsistency which causes the run to terminate.
USER RESPONSE:

If static logic tests are desired, ensure static logic faults are defined for the testmode, and
are selected for test generation and rerun. If static logic tests are not desired, select an
alternative vector format (e.g., dynamic or timed), and rerun.
ERROR | WARNING |(TTC-034): The option nonscanlatch=flush|buffer has been

specified, but a nonscanflush sequence is not defined for test mode modename.
Processing terminates|Test coverage may be affected.
EXPLANATION:
When nonscanlatch=flush is specified, Stored Pattern Test Generation requires the
existence of a nonscanflush sequence to identify how to initialize data pipelines. The
nonscanflush sequence is used by the test generator to properly exercise the data
pipeline. THIS IS THE RECOMMENDED APPROACH FOR DESIGNS CONTAINING
DATA PIPELINES.
Since the nonscanflush sequence does not exist for the test mode, processing
terminates.
When nonscanlatch=buffer is specified, any single active port non-scan latch is
assumed to be in a data pipeline.
When nonscanlatch=singleportbuffer is specified, any single port non-scan
latch is assumed to be in a data pipeline.
Using nonscanlatch=buffer or nonscanlatch=singleportbuffer may affect
test coverage, as Stored Pattern Test Generation will treat data pipelines as buffers and
does not require the existence of a nonscanflush sequence.
Define a nonscanflush sequence for the test mode to properly exercise the data pipeline.
If the nonscanflush sequence does not exist, the data pipelines will not be properly
exercised and test coverage will be affected.
USER RESPONSE:
If you intended to use the nonscanlatch=flush or nonscanlatch=buffer option,
analyze your logic to determine how to initialize the data pipeline while holding the
scannable latches constant (at their scanned in states).
Code a pattern sequence to do this and import the sequence by selecting Tools -
Vectors - Read or run read_vectors. After importing the sequence, run
analyze_sequences to create the data pipeline information. Then rerun the test
generation job.
WARNING (TTC-035): [Severe] Pseudo primary inputs were found in the design model,
but no user sequences were provided. The run continues with automatically generated
sequences, but these tests can not be used on the hardware.

EXPLANATION:
only with the help of user-supplied sequences. Test generation will proceed on an
uncommitted basis using automatic sequences to exercise the pseudo primary inputs.
An audit bit is set to alert downstream (manufacturing) processes that the test data does
not include all the primary input stimuli required to run the generated tests on a hardware
tester.
USER RESPONSE:
A pseudo primary input is an internal point in the design that Encounter Test treats like
a physical primary input. User-defined test sequences must be coded to exercise the
hardware so it provides the stimulus required at the pseudo primary input that is
consistent with the logical definition of the pseudo primary input.
If you are not familiar with this process, see "Coding Test Sequences" in the Automatic
Test Pattern Generation User Guide.
ERROR (TTC-036): Static logic faults cannot be targeted when producing dynamic tests due
to the presence of custom scan sequence.
EXPLANATION:
A custom scan sequence has been provided for this test mode. Stored Pattern Test
Generation cannot convert the static tests generated when targeting static logic faults
into dynamic tests under a custom scan sequence.
USER RESPONSE:
If targeting static logic faults is not required, deselect this option and rerun. Otherwise,
specify that static tests are to be generated and rerun.
ERROR (TTC-037): The option nonscanlatch=flush has been specified, but the data
pipeline information is not defined for test mode modename. Processing terminates. Run
prepare_pipeline_sequence to create this information for test generation.
EXPLANATION:
When nonscanlatch=flush is specified, Stored Pattern Test Generation requires
analysis of the nonscanflush sequence to identify which non-scan latch ports are in the
data pipeline. This data is used by the test generator to properly exercise the data
pipeline.
USER RESPONSE:

If you intended to use the nonscanlatch=flush, run

prepare_pipeline_sequence to have the data pipeline information added to the test
mode. Then rerun Stored Pattern Test Generation.
Alternatively, use nonscanlatch=buffer or nonscanlatch=singlebuffer and
Stored Pattern Test Generation will treat pipelines as buffers. Any single-port non-scan
latch is assumed to be in a data pipeline, however this option may affect test coverage.
WARNING (TTC-038): There are no tests selected, therefore the run terminates.
EXPLANATION:
There are no tests (e.g., scan chain, logic, etc.), selected for the run. This may be due to
tests being previously deselected for various reasons (see preceding messages), or
because no tests were specified through the mode definition or user options (via GUI or
command line).
USER RESPONSE:
No response is required unless after looking at the log, it is expected that certain test(s)
be generated. In this case, ensure the correct user options are specified to generate the
test(s) desired prior to rerunning Stored Pattern Test Generation.
INFO (TTC-039): Pseudo primary inputs were found in the design model, but no user
sequences were provided. Random simulation can not be performed. Random simulation is
deselected and the run continues.
EXPLANATION:
User-defined sequences are required for random simulation when a testmode defines
pseudo primary inputs for On-Product Clock Generation logic.
USER RESPONSE:
If random simulation is desired:
A pseudo primary input is an internal point in the design that Encounter Test
treats like a physical primary input. User-defined test sequences must be coded
to exercise the hardware so it provides the stimulus required at the pseudo
primary input that is consistent with the logical definition of the pseudo primary
input.
If random simulation is not desired:
Ignore this message ; or,
Deselect Simulate pseudo-random patterns prior to test generation
algorithm on the Test Generation tab on the Create Logic Tests Advanced

Test Generation option screen; or, specify simrandom=no on the command

line.
INFO (TTC-040): Input experiment experiment is a fault subset. Reverse simulation is

deselected.
EXPLANATION:
Reverse simulation does not support fault subsets and would erase the existence of the
fault subset. Therefore, to preserve the fault subset for the experiment, reverse
simulation is deselected.
USER RESPONSE:
concern.
ERROR (TTC-041): Experiment experiment is a fault subset. Since append is no,

continuing the run would create a new experiment and eliminate the existence of the fault
subset. Rerun with append=yes to use the fault subset, or remove the experiment and rerun.
EXPLANATION:
Existing experimental faultStatus file was created as a Fault Subset. Fault subsets are
normally created for appending Test Generation runs to the fault subset experiment.
USER RESPONSE:
If fault subset processing is desired, rerun with append=yes specified. Otherwise,
remove the experiment and rerun.
INFO (TTC-042): Existing experiment experiment is unable to be opened. See preceding

TFM message(s). Since append is no, this failure is ignored and the run continues.
EXPLANATION:
Test Generation is unable to open the uncommitted faultStatus to perform the TTC-041
fault subset check.
USER RESPONSE:
concern.
WARNING (TTC-043): [Severe] Test mode testmode has SCAN_TYPE of 1149.1 and
TAP_TG_STATE of Capture_DR, but no user sequences were provided. The run continues
with automatically generated sequences, but these tests should not be used to test the circuit.
EXPLANATION:

A TAP_TG_STATE of Capture_DR requires user-supplied test sequences. Test

generation will proceed on an uncommitted basis using automatic sequences. Automatic
sequences are likely to pulse clocks in an order that is not compatible with Capture_DR
operation and would fail at the tester. Specifically, any automatically generated test which
does not pulse TCK exactly one time is likely to fail at the tester.
USER RESPONSE:
User-supplied test sequences must be specified for the generated tests to be used on
the hardware.
INFO (TTC-044): Scan Chain Test | Processing of dynamic logic

faults | Path Test is deselected because test mode name has SCAN_TYPE of
1149.1 and TAP_TG_STATE of Capture_DR.
EXPLANATION:
Encounter Test does not support creation of a scan chain test or Dynamic Test
Generation when a test mode is 1149.1 with a TAP_TG_STATE of Capture_DR.
USER RESPONSE:
concern.
ERROR (TTC-045): Dynamic tests for static logic faults can not be created because test
mode name has SCAN_TYPE of 1149.1 and TAP_TG_STATE of Capture_DR.
EXPLANATION:
Encounter Test does not support creation of dynamic tests for static logic faults when a
test mode is 1149.1 with a TAP_TG_STATE of Capture_DR.
USER RESPONSE:
If targeting static logic faults is not required, deselect this option and rerun. Otherwise,
specify that static tests are to be generated and rerun.
INFO (TTC-046): Test Sequence Modification is deselected due to the existence of user
sequences.
EXPLANATION:
The presence of user sequences overrides the support for Multi-clock Compaction
(keyword multiclockcompaction) and Test Sequence Modification Latch Cutoff
(keyword seqmodlatchcutoff).
USER RESPONSE:

concern.
ERROR (TTC-047): Parallel processing does not support creation of ECID | Iddq | I/O Wrap
| Interconnect | Path tests. The run terminates.
EXPLANATION:
Parallel processing does not support the subject test. Ensure proper methodology is
being followed.
USER RESPONSE:
concern.
WARNING (TTC-048): Unable to access verify_test_structures Test Status on the

globalData file. LSSD flush test cannot be generated.
EXPLANATION:
Generation of the LSSD flush test is dependent on information supplied by
verify_test_structures but verify_test_structures has not been run.
USER RESPONSE:
Run verify_test_structures before attempting to generate an LSSD flush test.
WARNING (TTC-049): Flush Observable scan chains do not exist. An LSSD flush test
cannot be generated.
EXPLANATION:
Generation of an LSSD flush test is dependent on the existence of flush observable scan
chains.
USER RESPONSE:
concern.
ERROR (TTC-050): LSSD flush test generation failed.

EXPLANATION:
An error condition was encountered processing the scan chain LSSD flush test patterns
Processing of the scan chain tests terminates.
USER RESPONSE:

Refer to previous messages to determine necessary action.

ERROR (TTC-051): Scan chain test generation failed.
EXPLANATION:
An error condition was encountered processing the scan chain test patterns. Processing
of the scan chain tests terminates.
USER RESPONSE:
Refer to previous messages to determine necessary action.
ERROR (TTC-052): The committed objectiveModel | objectiveStatus |

alternate faultModel.##TB_SDT does not exist and is required for the generation
of Interconnect | I/O Wrap tests.
EXPLANATION:
Stored Pattern Test Generation requires an objective model file, an objective model
status file, and an alternate fault model when performing Interconnect or I/O Wrap test
generation. The run terminates.
USER RESPONSE:
Run build_faultmodel to build the objective model, the objective status file, and the
alternate fault model. Then rerun Stored Pattern Test Generation.
INFO (TTC-053): Unable to access Maximum SDT Objective ID | Maximum SNT

Objective ID statistic from the globalData file. Range checking for Stuck Driver
Tests | Shorted Nets Tests is not done.
EXPLANATION:
One, or more, of the following have been specified: firstsdtobj, lastsdtobj, firstsntobj,
lastsntobj. Stored Pattern Test Generation is unable to access a statistic from the
globalData file to verify the parameters are valid for the range of Objective IDs.
USER RESPONSE:
Rerun build_faultmodel to get the statistic created in the globalData file and then
rerun Stored Pattern Test Generation. Contact customer support (see Contacting
Customer Service on page 23) if there is a concern.

ERROR (TTC-054): The index n specified for the firstsdtobj | lastsdtobj |

firstsntobj | lastsntobj option is out of range of defined Stuck Driver Test
| Shorted Nets Test objectives (range is min to max).
EXPLANATION:
The value specified is out of the range of objectives defined for the circuit.
USER RESPONSE:
Use report_sdtsnt_objective_statistics - View Objective Model List to view
the objectives and their indexes. Ensure specified values are in the range.
ERROR (TTC-055): The index n specified for the firstsdtobj | firstsntobj

option is greater than index m specified for the lastsdtobj | lastsntobj option. The
firstsdtobj | firstsntobj index must be less than or equal to the lastsdtobj
| lastsntobj index.
EXPLANATION:
The first objective index must be less than or equal to the last objective index.
USER RESPONSE:
Use report_sdtsnt_objective_statistics - View Objective Model List to view
the objectives and their indexes. Ensure specified values are in the range.
ERROR (TTC-056): Use of the General Purpose Simulator (simulation=gp) is not

supported for I/O Wrap | Interconnect test generation.
EXPLANATION:
The General Purpose Simulator is no longer supported for the subject test generation.
The run terminates.
USER RESPONSE:
Remove specification of the simulation option or specify simulation=hsscan.
concern.
WARNING (TTC-057): Stuck Driver Test has been deselected. There are no active static
| dynamic SDT Objectives for test mode testmode.
EXPLANATION:
Either Stuck Driver Test Objectives have not been defined for this test mode, or Create a
Test Mode has not identified any of the SDT Objectives as active for the test mode.

USER RESPONSE:
If acceptable, no response is required. If Create a Test Mode was run after Create a Fault
Model, verify results of Create a Test Mode. Otherwise, verify results of Create a Fault
Model.
concern.
ERROR (TTC-058): Parameter parameter name is not supported as a separate

parameter. It must be specified within option option name.
EXPLANATION:
Parameter can not be specified as a standalone parameter on the command line. Its
proper use is within the option identified.
USER RESPONSE:
Move parameter to the identified option using the proper syntax. Contact customer
support (see Contacting Customer Service on page 23) if there is a concern.
INFO (TTC-059): Processing of path faults has been deselected because the vector format
is Static.
EXPLANATION:
Stored Pattern Test Generation was invoked to create tests for logic faults using a vector
format of Static. This format does not contain release and capture sections as a Path
format, and therefore is not suited for the detection of path faults. Processing of path logic
faults has therefore been deselected. Processing continues.
USER RESPONSE:
If processing of path faults is desired, change the vector format of these tests (e.g.,
test=path), and rerun. Otherwise, disregard this message.
ERROR (TTC-061): Parameter altfault=alternate fault model name has

been specified, but alternate fault model file fileName does not exist.
Logic | Driver and Receiver | IDDq | Path Test Generation terminates.
EXPLANATION:
Stored Pattern Test Generation requires a fault model. The run terminates.
USER RESPONSE:

Re-specify the altfault parameter to correctly identify an input alternate fault model
previously created, or remove the altfault parameter if the standard fault model is to be
used as input.
WARNING (TTC-062): Scan Chain LSSD flush test is deselected due to the existence of a
PRPG and/or MISR.
EXPLANATION:
The LSSD flush test turns on all A and B shift clocks simultaneously. This would likely
cause oscillations and excessive noise in a PRPG or MISR that is controlled by A and B
shift clocks.
USER RESPONSE:
WARNING (TTC-064): testoption is deselected because test mode testmode

explanation.
EXPLANATION:
The indicated test will not be generated in this run. Refer to reason given. The run
continues.
USER RESPONSE:
No response is required. Contact customer support (see Contacting Customer Service
on page 23) if there is a concern.
WARNING (TTC-065): The test mode testmode defines an On-Product MISR for
signature collection. globalterm=none is specified (from the command line or defaulted
from the TDR) which may cause an X to propagate through internal logic and invalidate
signatures.
EXPLANATION:
If the global tester termination value is set to none, then any three-state high impedance
value that is not terminated by the product will propagate through internal logic as
unknown (X). If the global tester termination is set to 1 or 0, then 1 or 0 value will
propagate to internal logic. Since unknown values can corrupt the signatures,
termination of none should be avoided for signature-based testing.
USER RESPONSE:
If TWT036 messages were also issued for this run, incomplete On-Product MISR test
data exists. If the globalterm specification came from your command line, change it to a
valid value and rerun. If the globalterm specification came from the TDR, you can

override it on the command line with the globalterm keyword or use the Tester Override
screen if using the graphical user interface (GUI).
concern.
ERROR (TTC-066): Option simictnets=pkgio | nonpkgio is specified or has

defaulted from processictnets=pkgio | nonpkgio, but the faultModel does not
contain information to enable fault simulating only Package I/O Nets | Non-Package
I/O Nets.
EXPLANATION:
Only faults on Package I/O nets (simictnets=pkgio) or Non-Package I/O nets
(simictnets=nonpkgio) were requested to be fault simulated. The simictnets
keyword has either been explicitly specified or has had its value defaulted from the
specification of the processictnets keyword.
The alternate fault model ##TB_SDT, which is used by the fault simulator, was built with
a prior release of Encounter Test, and does not contain the information required to
distinguish between Package I/O and Non-Package I/O nets.
Therefore, the run terminates.
USER RESPONSE:
Run build_faultmodel overwrite=yes sdtsnt=only with the current release
of Encounter Test to have the alternate fault model rebuilt with the correct data to support
this use of simictnets, OR, modify the command line so simictnets=all will be
used. Then rerun Interconnect Test Generation.
WARNING (TTC-067): A product MISR is being used but verify_test_structures

Analyze X-sources was not run. Poor test efficiency and lower test coverage may result.
EXPLANATION:
The use of an on-product MISR requires the collection of signatures. It is important that
no unknown or unpredictable values be captured when signatures are to be created.
Encounter Tests verify_test_structures X-source checking should be run to
verify that there are no sources of unpredictable values that can be captured into a
signature. If this occurs, Encounter Test will not be able to compute a signature for such
tests.
Encounter Test may be able to create signatures if ATPG Xprevent support is used. This
support is dependent on application data from verify_test_structures that is used
by ATPG to aid in the prevention of Xs being captured, allowing signatures to be created.

Encounter Test may also be able to create signatures if channel masking has been
implemented in the design .
USER RESPONSE:
Please run verify_test_structures X-source checking.
WARNING (TTC-068): A product MISR is being used and verify_test_structures

Analyze X-sources found potential problems. Unknown values could be produced resulting in
unpredictable signatures.
EXPLANATION:
The use of an on-product MISR requires the collection of signatures. It is important that
no unknown or unpredictable values be captured when signatures are to be created.
Encounter Tests verify_test_structures X-source checking indicates that one or
more sources of unpredictable values may be captured into a signature. If this occurs,
Encounter Test will not be able to compute a signature for such tests.
USER RESPONSE:
If you get no additional error messages indicating that an X was in fact observed during
simulation, then no action is necessary, although it is possible that future test generation
runs could encounter this problem. On the other hand, if some X source was reported
during simulation you should modify the design and obtain a clean
verify_test_structures run before attempting any additional test generation. The
design must be modified to either remove the source of X, or block the X from
propagating to an observable latch.
INFO (TTC-069): A linehold file has been specified or Linehold Test Function pins exist. For
the Scan Chain Test, any hold statements will be treated as default.
EXPLANATION:
The scan chain test is automatically generated from the predefined scan operation
sequences. Inputs such as scan enables, which are specified in the scan operation
sequences, can not be overridden by lineholds.
The lineholds will be applied only to pins which are left as dont care by the scan
operation sequences and the scan chain test generator.
USER RESPONSE:
No response is necessary. If you want to be sure that you are getting the intended result,
verify that you did not specify linehold information for any pin that is used (set to a value)
by the scan operation. This includes any pin that is a CLOCK, SCAN_ENABLE (+/-SE),
CLOCK_ISOLATION (+/-CI), SCAN_DATA_INPUT (SI), OUTPUT_INHIBIT (+/-OI), or is
set to a known value in the scan state. If you expected a hold for any of these pins to be

honored during the scan chain test, then reexamine what it is that you were attempting
to do.
WARNING (TTC-070): The option removeXlatch is specified/defaulted to no but

Test Mode modename has defined SIGNATURES TYPE=RUNNING|FINAL. Option
removeXlatch is overridden from no to yes to ensure all test patterns will have valid
signatures.
EXPLANATION:
When signatures are being accumulated across tests, it must be possible to compute a
signature for every test. If an unknown value is observed (in a scan chain) and is not
masked from entering the signature, the signature becomes unpredictable, so the test
must be discarded.
USER RESPONSE:
If the design includes channel masking logic, ensure that the xMask option is set to yes
to mask out the unknown values before they get into the signature. As long as this
masking is occurring, no tests should be removed even though removeXlatch is set to
yes.
WARNING (TTC-071): Pseudo primary inputs were found in the design model, but no user
sequences were provided and timed tests were requested. Because they were flagged as
TIs the run will continue, but the test data will be suspect if the mode initialization sequence
does not set their values.
EXPLANATION:
This test mode contains some pseudo primary inputs, which Encounter Test can
generally exercise only with the help of user-supplied sequences. In the case of TIs, Test
generation will proceed using automatic sequences with the assumption that the mode
initialization sequence will properly initialize the pseudo primary inputs.
USER RESPONSE:
No response is required if it is acceptible to create timed tests without a user sequence.
If a user sequence is required, create one. Refer to Coding Test Sequences in the
INFO (TTC-072): This test mode contains nonlinear decompression, All test generation
other than random pattern simulation has been deselected
EXPLANATION:
This test mode contains nonlinear decompression. Test generation cannot be done
unless the decompression is linear. If selected, random pattern simulation will occur.

USER RESPONSE:
ERROR (TTC-073): This test mode contains decompression linear compression or

embedded pipelines. A latchfill value of X cannot be specified.
EXPLANATION:
This test mode contains decompression, linear compression or embedded pipelines.
latchfill and latchfill2 cannot have a value of X.
USER RESPONSE:
Either accept the default for these keywords default or specify one of the other values
and then rerun.
INFO (TTC-074): The specified user test sequence is too complex to direct the test
generator. The test generator will create its default sequence(s) and the resulting stimulus
values will be mapped to the user sequence before simulation.
EXPLANATION:
The user test sequences can only direct the test generator if they are not too complex.
Test generation will now create test sequences as if there was no user test sequence.
These sequences will be converted to the user-specified format before simulation,
assuring that the final patterns are in the desired format. It is possible that this conversion
may prevent the targeted faults from being detected.
USER RESPONSE:
If desired, specify a simpler user sequence or hide the complexity from test generation
with ignore attributes. Refer to TG=keyed data in the Automatic Test Pattern
ERROR (TTC-075): Retention Test generation failed.

EXPLANATION:
An error condition was encountered while trying to generate the retention test patterns.
USER RESPONSE:
Refer to previous messages to determine necessary action, resolve problems, and then
re-run.
WARNING (TTC-076): Fault index fault, specified in the tgfaultlist is invalid. It will be
ignored and the run will continue if other valid faults are specified.

EXPLANATION:
The fault index specified in the tgfaultlist is out of range for this circuit and will be ignored.
USER RESPONSE :
Check the fault index and make sure it is in range for this circuit. If other valid faults are
specifed the run will continue.
ERROR (TTC-077): This test mode contains decompression and the keyword
maxscanswitching is specified. There is currently very limited support for decompression
testmodes which may result in high pattern count and low test coverage. The run will
continue.
EXPLANATION:
This test mode contains decompression and the keyword maxscanswitching is
specified. There is currently very limited support for decompression testmodes which
may result in high pattern count and low testcoverage
USER RESPONSE:
The run continues.
INFO (TTC-100): A test was generated for fault.

EXPLANATION:
If requested (report=tested), a message will be issued each time a pattern is created
by the test generator. As this could happen a large number of times for a typical run,
reporting for tested faults should be left off. The fault portion of the message will include
the full name of the pin (or block, for pattern faults), as well as the fault index and whether
the fault is a pattern fault or a simple fault. The run continues.
USER RESPONSE:

INFO | WARNING (TTC-102): fault is status and reason.
EXPLANATION:
A limitation of the currently selected test generator was encountered which prevents a
test from being created. This does not mean that the fault is redundant, just that the test
generator could not create a test. Reasons include

scan conflicts: different values required in three adjacent latches

globalterm: algorithmic limitations prevent complete processing around three-
states
multi-time: algorithmic limitations prevent complete processing for faults which
require many time images for a test Run continues.
ignoremeasures or channel masking: observe latch for target fault is unusable
due to specification in an ignoremeasures file is unusable due to channel
masking
The run continues.
USER RESPONSE:
INFO (TTC-103): Test generation aborted while processing fault.

EXPLANATION:
The test generator terminated processing due to a pre-specified limit. Effort and time per
fault are examples of these limits. Run continues.
USER RESPONSE:
If there are excessive numbers of aborted faults, rerun with a higher effort level.
WARNING (TTC-104): testType tests have been deselected because no user specified
test sequences are of static|dynamic|IDDq format.
EXPLANATION:
The indicated tests will not be generated in this run due to an incompatibility between the
format (i.e., static, dynamic, or IDDq) of the indicated tests, and the user specified test
sequences supplied for the run. The run continues.
USER RESPONSE:
No response is required if it is acceptable that the indicated tests not be generated by
this run. Otherwise, steps will need to be taken to either ensure compatible formats
between the indicated tests and the user supplied test sequences, or to discontinue use
of user supplied sequences altogether, permitting use of automatically generated
sequences.
INFO (TTC-105): fault is Redundant.

EXPLANATION:

The test generator has determined that the specified fault is redundant. Run continues.
USER RESPONSE:
No response required. Excessive numbers of these faults will increase test generator
runtime.
INFO (TTC-106): Reverse simulation is selected, but output patterns are not being written.
Reverse simulation is deselected.
EXPLANATION:
This is an informational message. Run continues.
USER RESPONSE:
INFO (TTC-107): There are no scan chains in this circuit, therefore no scan chain tests will
be generated.
EXPLANATION:
The test mode and/or the user have specified that scan chain tests are to be generated;
however, no scan chains exist in the circuit. The run continues, but no scan chain tests
will be generated.
USER RESPONSE:
INFO (TTC-108): Generation of the scan chain testType test has been deselected
because it already exists.
EXPLANATION:
The scan chain tests have already been generated and either committed or saved in the
existing experiment in the case of an append run.
The run continues but additional scan chain tests will not be generated.
USER RESPONSE:
No response required if no additional scan chain tests are desired. Otherwise, rerun
explicitly specifying that scan chain tests are to be generated.
INFO (TTC-109): fault is status and reason.

EXPLANATION:

The test generator determined that the indicated fault is untestable due to the indicated
reason. The reason can be one of the following, listed with their definitions.
undetermined - classified as untestable but the cause was not determined.
linehold conflict - the test generator encountered logic value(s) originating from
linehold(s) (.LH flagged test function pin, or specified via a user file), which are
inconsistent with logic value(s) required to test the fault.
SOS conflict - (Simultaneous Output Switching) - the test generator
encountered at least one situation where it needed to pulse a clock (ON), while
an OI (Output Inhibit) pin is stimmed away from stability.
This situation is considered an illegal test under Simultaneous Output Switching
constraints due to the potential for excessive noise which could result.
clocking constraint - the test generator encountered at least one situation where
it needed to stim (not pulse), a clock to its ON value. The test generator is not
permitted to generate such a test when the STIMCLOCK=no user override is in
effect.
PMU conflict - (Parametric Measuring Units) - When running Stored Pattern
Test Generation on a test mode with pins not contacted by the tester, if the tests
being generated permit the use of PMUs, the test generator must observe
special constraints when the number of PMUs is less than the number of
primary I/O pins on the circuit.
The test generator in this case is permitted to stim or measure no more than
one non-test pin for each test.
The number of PMUs available for use is specified in the Tester Description
Rule, and incorporated into Encounter Test at Mode Definition time.
three-state contention - the test generator encountered at least one situation
where logic values consistent with generating a test create a three-state
contention condition in the good machine. The test generator does not generate
tests which cause three-state contention.
multi-clock conflict - the test generator encountered at least one situation where
in order to achieve logic values consistent with generating a test, multiple clock
pins where required to be away from stability simultaneously.
This is usually an indication of the presence of clock ANDing, and is not
considered a legal test in Encounter Test.
TG state (TI flags, etc..) - the test generator encountered logic value(s)
originating from Test Generation design state which are inconsistent with logic
value(s) required to test the fault.

clock-not-chopped fault - the test generator determined that a clock-not-

chopped fault (within a clock chopper network), is not observable at a Primary
Output.
non-terminated three-state (X source) - the test generator encountered at least
one situation where an X originating at a non-terminated (or terminated to X),
internal three-state device prevents successful generation of a test.
clock stuck off (X source) - the test generator determined that a fault on a clock
line feeds only single port memory elements and that the fault effect is the clock
stuck off. Since the memory elements clock is stuck off, the element cannot be
brought to a known state in the presence of the fault (always X).
X sources - the test generator encountered at least one situation where an X
originating from an X source prevents successful generation of a test. The
following are considered X sources in this context:
- TIEX
- sourceless logic
- feedback loop (not broken by a latch)
- single port memory element with clock tied OFF
- ROM with unknown contents
correlated pins - a test for this fault cannot be produced due to the existence of
correlated pins.
non-contacted pins - a test for this fault cannot be produced because required
input pins will not be contacted at the tester. This status occurs when using
reduced pin count test (RPCT) where the number of tester pins is less than the
number of product pins.
TG constraint - a test for this fault produces a conflict with pattern constraints
specified in the design source with the constraint attribute.
global termination - this can one of the following:
- global term 0 - a test for this fault requires termination on some three-state
primary output, but the test-supplied termination of 0 does not permit
termination to the state required by the test.
- global term 1 - a test for this fault requires termination on some three-state
primary output, but the test-supplied termination of 1 does not permit
termination to the state required by the test.

- global term none - a test for this fault cannot be produced without using global
tester termination, but globalterm=none has been specified.
clock required at Z - a test for this fault cannot be produced because the clock
is required a high impedance.
AC test constraint - a test for this fault cannot be produced due to conflicts with
dynamic/timed test constraints.
unreachable state - sequential conflict. This fault was discovered to be
untestable during sequential test generation.
feedback - a test for this fault cannot be produced due to asynchronous
feedback loops in the design.
nonscanlatch=flush - a test for this fault cannot be produced due to non-
scannable latches that are flushing.
USER RESPONSE:
Besides changing the circuit, there is no user response for faults which are untestable for
reasons relating to the logical topology of the design (for example, X sources, three-state
contention, etc.).
Faults untestable due to constraints not directly related to the design (e.g., STIMCLOCK,
SOS, etc.), MIGHT be tested with the removal of the constraint.
Note: There is no guarantee that a particular fault identified as untestable due to a
specific constraint will be tested when the constraint is removed. This is the case
because there may be other (yet unknown) reasons why the fault is untestable.
It is possible for the test generator to encounter a variety of conditions (reasons), when
attempting to find a test for a fault. When multiple reasons are detected, a priority scheme
is used to assign the final reason. This scheme is weighted toward user controllable
parameters which may be influencing test coverage.
INFO (TTC-110): text.

EXPLANATION:
This is a general informational message. Run continues.
USER RESPONSE:
WARNING (TTC-111): All fault_type faults are resolved or have not been defined for
this test mode, thus they will not be targeted.

EXPLANATION:
The indicated faults were selected for processing, however no unresolved faults of this
type currently exist for this test mode. The run continues without the indicated faults
processed.
USER RESPONSE:
No response required, unless processing of the indicated faults is desired. In that case,
rebuild the fault model with appropriate options and rerun.
INFO (TTC-112): The limit limit of value has been reached.

EXPLANATION:
This message is issued when a run limit is reached. The limits are:
CPU Time
Elapsed Time
Maximum Patterns - When the specified number of patterns is reached,
pattern resimulation, if selected (or required), will be run.
This can result in fewer patterns being generated than
that specified.
Maximum Untestable - When the number of untestable faults
reaches the percentage specified, the run will end.
Maximum Coverage - When the number of tested faults reaches
the percentage specified, the run will end.
Faults Processed - When the number of faults processed
reaches the specified limit, the run will end.
Run completes.
USER RESPONSE:
INFO (TTC-115): Reverse simulation is selected, but all patterns, including ineffective
patterns are being written. Reverse simulation is deselected.
EXPLANATION:
Stored Pattern Test Generation was invoked in a manner which stores all fault simulated
patterns including those that detect no faults, in the output Vectors file. Reverse
simulation is deselected whenever ineffective patterns are to be saved.
USER RESPONSE:
No response is necessary if Reverse simulation is not desired. Otherwise, remove the
option (writepatterns=all) which results in saving of ineffective patterns and
rerun.
INFO (TTC-116): Reverse simulation is deselected because reason.

EXPLANATION:
The message states why reverse simulation is being deselected. The reason is one of
the following:
compactioneffort=none is in effect
Neither Driver Receiver, Logic, I/O Wrap, Interconnect, nor Iddq tests are
requested
Either I/O Wrap or Interconnect is the only test requested and gmonly=yes is
specified
The run continues.
USER RESPONSE:
No response is necessary if reverse simulation is not desired. Otherwise, modify input
options and rerun.
ERROR (TTC-117): Cannot create dynamic tests for a mode which includes force B clock
support.
EXPLANATION:
The mode definition force B clock option imposes restrictions on the format of all test
sequences generated for a mode. These restrictions preclude the generation of dynamic
(or timed) tests. The run terminates.
USER RESPONSE:
If dynamic or timed tests are desired for the mode, redefine the mode without the force
B clock option in effect and then rerun Stored Pattern Test Generation. Otherwise, rerun
Stored Pattern Test Generation without dynamic or timed tests specified.
WARNING (TTC-118): Not a sufficient number of fault_type faults where found to

process. The run will terminate. Possible causes could be your input clock constraint file,
testsequence, setupsequence, or linehold file.
EXPLANATION:
Any unresolved faults left to process may be filter out by a clock constraint file, $ input
testSequence, setupsequence, or linehold file. There is not a sufficient number of faults
available to processes and therefore the run terminates.
USER RESPONSE:

No response required unless there are more faults left to be processed. Modify or
remove your clock constraint file, input testsequence, setupsequence or linehold
file and re-run.
WARNING (TTC-119): The scan chain testType test has already been generated, but will
be regenerated in this run.
EXPLANATION:
The indicated scan chain test has already been generated either in another exper (and
committed), or in this experiment in the case of an append run. The run continues and
the additional scan chain test will be generated.
USER RESPONSE:
WARNING (TTC-120): Fault simulation of the testType tests has been deselected
because reason. Good machine only simulation of the testType tests will be performed.
EXPLANATION:
The tests generated for the indicated test type (e.g., I/O Wrap), will be good machine only
simulated due to the indicated reason (e.g., no fault model exists).
USER RESPONSE:
If good machine only simulation is acceptable for the indicated test type, no action is
required. Otherwise, perform the steps required to ensure untested faults exist for the
test mode and rerun.
INFO (TTC-123): Checkpoint elapsed time of checkpoint_time minutes reached at

time_of_day. A checkpoint is now being taken.
EXPLANATION:
This is an informational message indicating that a Stored Pattern Test Generation
checkpoint is being taken at the indicated time. The run continues.
USER RESPONSE:
INFO (TTC-124): Checkpoint completed successfully. Checkpoint ID = time/date

stamp.
EXPLANATION:

This is an informational message indicating that a Stored Pattern Test Generation

checkpoint completed successfully. The run continues.
USER RESPONSE:
WARNING (TTC-125): Checkpoint of the name file failed. The run continues.
EXPLANATION:
A checkpoint of the indicated file failed. This message should be preceded by additional
messages which indicate why the checkpoint failed.
USER RESPONSE:
See preceding messages and take the appropriate corrective action to ensure success
of either the next checkpoint or completion of the run.
INFO (TTC-126): Switching from Scan Based to Sequential Test Generation Algorithm.
EXPLANATION:
Based on the parameter setting of tgalgorithm=both and internal heuristics, the
Stored Pattern Test Generation Controller is switching test generation algorithms as
indicated. The run continues.
USER RESPONSE:
INFO (TTC-127): Random simulation is deselected, reason why.

EXPLANATION:
Random simulation is deselected if:
all of the requested logic faults are resolved, or
a logic test section already exists in the committed test mode committed data,
or
a logic test section already exists for this experiment, or
no user specified test sequence satisfies the requested format (see previous
TTC-104 message).
The Test Generation Controller assumes the generation of random patterns has
previously occurred if a logic test section already exists for the test mode committed data
or the current experiment. The other reasons should be self-explanatory.

USER RESPONSE:
Rerun with effort=minimum and test=logic to force the creation of random
patterns or specify the proper user test sequence with the testsequence keyword. No
response is required if both of the preceding responses are not applicable.
INFO (TTC-128): Generation of the ECID test has been deselected because it already
exists.
EXPLANATION:
The ECID test has already been generated and either committed or saved in the existing
experiment (in the case of an append run). The run continues but an additional ECID test
will not be generated.
USER RESPONSE:
ERROR (TTC-129): Command line parameter contentionremove=no has been

specified indicating that test sequences for which 3-state contention was reported should be
written to the output Vectors file. Parallel simulation requires that you specify that all test
sequences, including those that are ineffective, be written (command line parameter
writepatterns=all).
EXPLANATION:
By specifying that patterns with 3-state contention should not be removed the user is
requesting that test sequences for which 3-state contention was reported be written to
the output Vectors file. When this option is specified, parallel simulation also requires that
all sequences, including those that are ineffective, be written to the output Vectors file.
USER RESPONSE:
If it is required that test sequences for which 3-state contention has been reported get
written to the output Vectors file, rerun specifying that ineffective patterns should be
included in the output (command line parameter writepatterns=all). Otherwise,
specify that these sequences should be removed (command line parameter
contentionremove=yes).
INFO (TTC-130): The default setting of multi-clock compaction,

(multiclockcompaction=yes) has been turned off because of unsafe three-state devices
on the part.
EXPLANATION:

Multi-clock compaction has been defaulted on, (multiclockcompaction=yes). Using

multi-clock compaction may be causing burnout during simulation. It has been turned off
to reduce the risk of creating tests that cause burnout.
USER RESPONSE:
No response required. If multi-clock compaction is still desired, add
multiclockcompaction=yes to the command line and rerun.
WARNING (TTC-132): Unable to switch from Scan-Based to Sequential test generation

algorithm. License for Sequential test generation is unavailable. Run continues using Scan-
Based test generation algorithm.
EXPLANATION:
Based on the parameter setting of tgalgorithm=both and internal heuristics, the
Stored Pattern Test Generation Controller is attempting to switch test generation
algorithms from Scan-Based to Sequential. Licenses for sequential test generation exist,
but none are currently available. Run continues using the Scan-Based algorithm.
USER RESPONSE:
No response required. The run completed using the Scan-Based test generation
algorithm (tgalgorithm=scan).
INFO (TTC-133): maxcarebits cannot be higher than the number of scan-in pins. The
specified value is ignored and maxcarebits will remain at the default value.
EXPLANATION:
The specified value for the maxcarebits keyword cannot be higher than the number of
scan-ins on the part.
USER RESPONSE:
Specify a correct value or let this keyword default.
INFO (TTC-134): The keyword maxcarebits is not valid with a test mode that does not have
linear decompression. The keyword specification is ignored and the run will continue.
EXPLANATION:
Use of the keyword maxcarebits is intended for test modes with linear decompression.
USER RESPONSE:
Remove this keyword from the command string or add linear decompression to your test
mode. Refer to the definition of ScanData for the SCAN mode defintion statement in the
Encounter Test: Guide 2: Testmodes.

INFO (TTC-135): The pattern file (TBDbin) is empty. No patterns have been saved for this
experiment.
EXPLANATION:
The pattern file (TBDbin) is empty. No patterns have been saved for this experiment.
USER RESPONSE:
ERROR (TTC-145): Cannot append to experiment experiment name because it

contains Scan Control Pipeline patterns that have already been manipulated. Run
terminates.
EXPLANATION:
Pattern audit information indicates the input experiment has already had its patterns
manipulated for Scan Control Pipelines. Encounter Test is unable to append to this
experiment under these conditions.
USER RESPONSE:
Specify a different input experiment name to create an additional experiment, OR
commit_tests the experiment and continue your methodology, OR remove
append=yes to overwrite the current experiment and patterns.

WARNING (TTC-151): Simulation detected fault fault which was marked redundant by
test generation.
EXPLANATION:
A fault determined to be redundant was marked detected by fault simulation. Run
continues.
USER RESPONSE:
No response required. If significant numbers occur, contact customer support (see
WARNING (TTC-153): Simulation detected patterns which cause three-state contention.

EXPLANATION:

Fault simulation detected pattern(s) which cause a three-state contention condition in the
good machine. The run continues.
USER RESPONSE:
WARNING (TTC-154): Possibly detected fault fault was marked redundant by test
generation.
EXPLANATION:
Fault simulation marked a fault as possibly detected which test generation determined to
be redundant. The run continues.
USER RESPONSE:
None. If significant numbers occur, contact customer support (see Contacting Customer
WARNING (TTC-156): The following TDR specification has been overridden:

specification.
EXPLANATION:
This is a warning message indicating a Test Description Rule (TDR) specification which
has been overridden by the user. The run continues.
USER RESPONSE:
No response is required if it is acceptable that the specification be overridden. Otherwise,
the run which issued this message should be terminated and Stored Pattern Test
Generation rerun without the override.
WARNING (TTC-157): Simulation detected fault fault which was resolved as ATPG
Untestable - reason.
EXPLANATION:
Fault simulation marked a fault as detected which test generation determined to be
untestable. The run continues.
USER RESPONSE:
No response required. If significant numbers occur, contact customer support (see
WARNING (TTC-158): Fault simulation detected stuck driver objective objective which
was previously determined to be untestable.

EXPLANATION:
Fault simulation detected that the Stuck Driver objective pattern fault was tested even
though the test generation was unable to generate a test for it. This may indicate an
limitation with test generation or fault simulation. The run continues.
USER RESPONSE:
WARNING (TTC-159): Fault simulation detected stuck driver objective objective which
was previously determined to be incomplete. See previous TTC-102 message.
EXPLANATION:
TTC-102 messages indicate objectives that are not detected by their respective test
pattern. Fault simulation of subsequent test patterns has serendipitiously detected this
objective. The run continues.
USER RESPONSE:
WARNING (TTC-160): [Severe] An error occurred while trying to analyze the sequence
definition seqDefName as specified on the keyword= command line parameter. Ensure
this sequence has been defined and can be found in the TBDseq file for this Test Mode.The
run will continue and will not use this sequence.
EXPLANATION:
The program was unable to find the test sequence <seqDefName> as specified by the
testsequence= or setupsequence= commandline parameter.
USER RESPONSE:
Ensure that the specified sequence can be found in the TBDseq file.
ERROR (TTC-162): The keyword setupsequence= setupsequenceName specifies a

sequence that is not found in the TBDseq file. The run will terminate.
EXPLANATION:
The setup sequence specified by the setupsequence keyword may be found in the
TBDseq file.
USER RESPONSE:

Make sure the setupsequence keyword is specified correctly or the setup sequence
exists in your TBDseq file. If the setupsequence keyword is not required, remove it
from the command line.
WARNING (TTC-163): [Severe] An error occurred while trying to analyze the sequence
definition sequenceName as specified on the testsequence keyword. error
conditionThis sequence will be ignored and the run will continue if other testsequences
are specified.
EXPLANATION:
The sequence specified by the testsequence keyword cannot be used due to the error
specified sequences specifed in the testsequence keyword.
USER RESPONSE:
Correct the error identifed for this testsequence. This sequence will be skipped and
other sequences specifed in the testsequence keyword will be processed.
ERROR (TTC-164): Small Delay Test Generation cannot continue. Either a

clockconstraints file must be provided or prepare_timed_sequences must be run to
provide the required release/capture timing.
EXPLANATION:
When smalldelay=yes is specified, release/capture timing information must be
provided either in a clockconstraints file, or in the testsequences created by
USER RESPONSE:
If prepare_timed_sequences command has been run and you would like to use
those sequences in create_logic_delay_tests, make sure useprep=no is not
specified on the create_logic_delay_tests command. If you would like to provide
release/capture timing directly to create_logic_delay_tests without using
sequences created by prepare_timed_sequences, you must specify a
clockconstraints file. Or remove smalldelay=yes from the command line. Then
rerun create_logic_delay_tests.
WARNING (TTC-165): No faults were found which can be tested with test sequence
sequenceName. This sequence will be ignored and the run will continue if other
testsequences are specified.
EXPLANATION:
No faults were identified which could be tested by the test sequence specified.
USER RESPONSE:

If faults should be tested by this sequence, analyze this sequence for possible problems.
This sequence will be ignored and other sequences specifed in the testsequence=
keyword will be processed. If other sequences are specified or this is a append run the
faults targeted by this sequence may already have been detected.
INFO (TTC-166): testsequence seqDefName has more clockType clocks defined than
the max allowed of maxClocks. Clock clockName will be ignored.
EXPLANATION:
The testsequence has more launch or capture clocks defined than the program allows.
Thie clocks will be ignored.
USER RESPONSE:
The run continues but this clocks will not be used.
WARNING (TTC-167): The current low power support, running with maxscanswitching
and/or maxcaptureswitching, only support one testsequence at at time. The run will
terminate.
EXPLANATION:
The testsequence= keyword was found on the command line to contain more than
one testsequence. The current low power support, running with maxscanswitching
and/or maxcaptureswithing only supports one testsequence at a time. The run will
terminate.
USER RESPONSE:
If multiple sequences are required please rerun with only one testsequence specified at
a time.
ERROR (TTC-198): The specified maxscanswitching | maxcaptureswitching

| maxscanswitching and maxcaptureswitching value(s) cannot be achieved.
EXPLANATION:
The specified maxscanswitching and/or maxcaptureswitching value(s)
cannot be used to generate effective patterns. Too much scanswitching is occuring and/
or a sufficient number of flops cannot be gated off to reach the user specified
USER RESPONSE:
For maxscanswitching, raise the maxscanswitching limit. For
maxcaptureswitching, raise the maxcaptureswitching limit or add additional
clock gating to the design.

ERROR (TTC-199): Terminating error received from Test Generation | Fault

Simulation process pid.
Message received: message received from child.
EXPLANATION:
USER RESPONSE:
Note the reason given in this message and contact customer support (see Contacting
Customer Service on page 23) if necessary.
ERROR (TTC-200): application terminating due to reason.

EXPLANATION:
USER RESPONSE:
Examine the log for a preceding message which may offer additional information relating
to why the run terminated. If such a message exists, refer to the corresp explanation/
response. Otherwise, note the reason given in this message and contact customer
support (see Contacting Customer Service on page 23) if necessary.
ERROR (TTC-201): [Internal] Program error - error.

EXPLANATION:
A program error has occurred. The run will continue if possible.
USER RESPONSE:
Note the error and contact customer support (see Contacting Customer Service on
page 23).
ERROR (TTC-202): Less than percentage% of the attempted faults were tested during
the test generation learning phase. This may be due to a testability problem with the design,
a problem with a user-supplied test sequence, a large number of timing constraints, or a
conflict between keywords specified on the command line and the sequences produced by
Check the verify_test_structures log for testability problems, and verify that any
user-defined sequences and timings are appropriate for the design. If
create_logic_delay_tests is being run after prepare_timed_sequences has been
run, look for keywords in this run that may cause create_logic_delay_tests to create
sequences that could conflict with those created by prepare_timed_sequences.

EXPLANATION:
The test generator was unable to generate enough tests during the learning phase. This
can occur if there is a testability problem with the design, if one or more of the inputs to
the command conflict with each other, or if the constraints on ATPG are too severe.
USER RESPONSE:
Take the following actions, correct where appropriate, and then rerun:
Verify a testability problem with the design by reviewing the
verify_test_structures command log.
Conflicting inputs to the command may occur if you are using a test sequence
(either user-specifed or created by prepare_timed_sequences) that is
inconsistent with the dynseqfilter, dynpomeasures, allowedpistims,
or dynonly2clks keywords. If a test sequence is specified or
prepare_timed_sequences has been run, omit these keywords from the
create_logic_delay_tests command line.
ERROR (TTC-203): Using the dynseqfilter=dynseqfilter, the test generator was

not able to identify the release and capture events (stims, pulses and/or measures) required
to generate tests. This can happen for instance if dynseqfilter=norepeat (default for
LSSD designs) is specified and there is only one clock in the design, or if
dynseqfilter=repeat (default for non-LSSD) is specified and there are no clocks in the
design. Ensure that the dynseqfilter is set correctly, or provide a user test sequence or
clock constraints file.
EXPLANATION:
create_logic_delay_tests or prepare_timed_sequences was unable to
identify release and capture events to be used during ATPG. This can occur if the
dynseqfilter is inconsistent with the clocks in the design.
USER RESPONSE:
Either change the dynseqfilter to match the clocks available in the design or provide
a user test sequence or clock constraints file, and then rerun.
WARNING (TTC-204): Clock domains selected for testing by either the dynseqfilter,
clockconstraints or testsequence keywords are different than the domains checked
during read_sdf. Processing continues.
EXPLANATION:
When the SDF is read, the domains to be checked are identified by the dynseqfilter,
clockconstraints or testsequence parameters. Similarily, the faults are selected for test
generation in same way. If domains selected for test generation are different than those

checked by read_sdf, then some domains were not checked to determine if the delays
are valid. This may result in incorrectly timed patterns. The dynseqfilter defaults to
repeat for non-LSSD testmodes and norepeat for LSSD testmodes.
USER RESPONSE:
Rerunning read_sdf or build_delaymodel using the same settings as this
command is recommended. To check the delays for the entire circuit, specify
dynseqfilter=any on the read_sdf or build_delaymodel commands.
ERROR (TTC-205): The option faultype=dynamic is required for

create_logic_delay_tests. Processing ends
EXPLANATION:
The faulttype keyword specification be dynamic when running
create_logic_delay_tests so that dynamic faults will be simulated. The following
are valid specifications:
faulttype=dynamic to simulate dynamic faults only
faulttype=static,dynamic to simulate both static and dynamic faults
USER RESPONSE:
Add the option dynamic to the faulttype keyword and then rerun
create_logic_delay_tests.
ERROR (TTC-206): All of the patterns created by the test generator are failing simulation.
Processing ends. This may be due to three-state contention. Check to see whether there are
TSV-093 or TSV-193 messages issued by the verify_test_structures command
indicating possible three-state contention. Make sure you are running with
contentionprevent=yes to protect three-state devices and specify the
contentionreport setting that will tolerate contention in the test patterns.
EXPLANATION:
Contention can occur if three-state devices are not protected during ATPG. The
verify_test_structures command issues messages TSV-093 and TSV-193 to
identify possible three-state contention. If contention is not supposed to be possible, use
the verify_test_structures message analysis to verify that the testmode has
been built correctly. If possible contention exists, specify contentionprevent=yes
during ATPG so that the test generator will protect the three-state devices. You may also
specify contentionreport=hard to ignore soft contention, or
contentionreport=none to ignore all contention.
USER RESPONSE:

Correct the testmode definition or rerun ATPG using the contentionprevent and/or
contentionreport keywords.
ERROR (TTC-207): The file specified by testsequence=filename contains no

sequences , or invalid sequence names. Processing ends.
EXPLANATION:
A file was specified on the testsequence keyword but it contains no sequences , or
invalid sequence names, so processing did not continue.
USER RESPONSE:
Please review the sequence file. This could be because a previous command was unable
to create any.
ERROR (TTC-210): Unable to open pattern file from parallel experiment

experimentName of task taskNum. The patterns simulated by this process will not be
included in the final pattern set from this parallel run.
EXPLANATION:
An error occurred trying to open the pattern file (TBDbin) generated by the parallel
process using the experiment name experimentName, which was also known as task
number taskNum. We are unable to include those patterns in the final set of patterns
output from this parallel experiment.
USER RESPONSE:
Try to resolve the problem and rerun or contact customer support (see Contacting
ERROR (TTC-211): LSF services are ending with an error condition. Examine the log for a
preceding message which may offer additional information relating to why there is an error
condition. If such a message exists, try to resolve the problem. Otherwise, note the reason
given in this message and if necessary contact customer support.
EXPLANATION:
An error occured with the LSF services, the run may terminate.
USER RESPONSE:
Try to resolve the problem and rerun or contact customer support (see Contacting
Customer Service on page 23) for more assistance.
INFO (TTC-212): Running with gcovdebug, all output will be suppressed.

EXPLANATION:

Running with a special gcov debug option. All output will be suppressed.
USER RESPONSE:
The run continues.
WARNING (TTC-300): The Test Generator was unsuccessful in a preliminary attempt to

protect the three-state devices from contention. The run continues, but there is a possibility
that tests will not be generated.
EXPLANATION:
The keyword value contentionprevent=yes has been specified. During initialization
of the test generator, a preliminary fault-independent attempt is made to protect all
unsafe three-state devices from contention. This attempt was not successful. If the run
continues without creating any tests, it is likely there is a problem with the design which
does not allow for safe tests.
USER RESPONSE:
If safe tests are generated, ignore this message. If no safe tests are generated it may be
possible to relax the contentionreport option to allow soft or allx contentions to
occur. Otherwise, analyze the design to deternine why contention is unavoidable.
WARNING (TTC-301): Test generation failed to create a test sequence which matches the
user specified test sequence. The run continues if other test sequences are specified.
EXPLANATION:
The test generator was unable to generate a test that matches the user specified test
sequence. The run will continue if other sequences are specified.
USER RESPONSE:
If there are no warning messages about the user test sequence, try running the test
generator with reportsequence and examine the sequences generated by the test
generator that do not match the user specified test sequence.
WARNING (TTC-400): The testmode definition requests true time flush and/or scan tests.
This application only creates static tests. The run continues, creating static scan/flush tests.
Use create_scanchain_timed_delay_tests to create the tests requested by the
testmode.
EXPLANATION:
create_tests creates static scan/flush and logic tests. To create the True-Time
versions of these tests, use the timed_delay versions of the scanchain tests
commands. To create other types of tests, use other create_*tests commands.

Enter help create to obtain a list of create commands.

USER RESPONSE:
Ignore this message if the intent is to create static flush and/or scanchain tests; the static
test generation will continue.
If True-Time tests are desired, use the timed_delay version of the command(s).
If the testmode definition is incorrect, perform the following to modify it for future
processing:
Change the test_types statement in the mode definition file
Rebuild the testmode
Rerun create_tests to create static scan/flush/logic tests.
WARNING (TTC-401): The testmode definition does not request scan or flush tests. The run
continues without creating the scanchain or lssd_flush tests. Use
create_logic_tests to create the logic tests without scanchain and/or lssd_flush
tests.
EXPLANATION:
create_tests creates static scan/flush and logic tests. The testmode did not request
scan/flush tests. To create just logic tests, use create_logic_tests.
USER RESPONSE:
Ignore this message if the intent is to create static flush and/or scanchain tests; the static
test generation will continue.
If just logic tests are desired, run create_logic_tests with the same experiment
used on this command to overwrite the results with only logic tests.
WARNING (TTC-402): The testmode definition requests true time logic tests. This
application only creates static tests. The run continues, creating static logic tests. Use
create_logic_delay_tests to create the logic tests requested by the testmode.
EXPLANATION:
create_tests creates static scan/flush and logic tests. To create the True-Time
versions of these tests, use the timeyd_delay versions of the scanchain,
lssd_flush of logic tests commands. To create other types of tests, use other
create commands.
Enter help create to obtain a list of create commands.

USER RESPONSE:
Ignore this message if the intent is to create static logic tests; the static test generation
will continue.
If True-Time tests are desired, use create_logic_delay_tests.


75
TTM - Test Mode Messages
TTM-001 through TTM-050 on page 2389

TTM-001 through TTM-050

ERROR (TTM-001): Missing TESTMODE keyword.
EXPLANATION:
The TESTMODE keyword is required.
USER RESPONSE:
Use TESTMODE=modename when invoking this application.
Refer to "build_testmode in the Encounter Test: Reference: Commands for

ERROR (TTM-002): Missing or invalid MODEDEF keyword.

EXPLANATION:
The MODEDEF keyword is required.
USER RESPONSE:
Use MODEDEF=modedef filename when invoking this application.
Refer to "build_testmode in the Encounter Test: Reference: Commands for
ERROR (TTM-003): Unable to resolve file filename from path keyword.

EXPLANATION:
The filename specified cannot be found.
USER RESPONSE:
Check that the filename resides in the proper path.
ERROR (TTM-004): Error loading Hierarchical Model.

EXPLANATION:
The hierarchical model is created during Build Model. The application could not open the
file. It is either non-existent or the file permissions do not allow access.
USER RESPONSE:
Ensure the file permissions allow you to build a model. Check for previous error
messages.
ERROR (TTM-005): Error in Flat Model access, application.

EXPLANATION:
The flat model is created during Build Model. The application could not open the file. It is
either non-existent or the file permissions do
not allow access.
USER RESPONSE:
Ensure the file permissions allow you to build a model. Check for previous error
messages.
ERROR (TTM-006): Error in TBD access, application.

EXPLANATION:
TBD accesses the Mode Initialization Sequences.
USER RESPONSE:
Check for previous messages regarding read_vectors on this file.
ERROR (TTM-007): Error saving globalData file.

EXPLANATION:
The globalData file holds the new Mode Definition data.
USER RESPONSE:
Ensure your file system has enough space for new data. Check that you have the proper
file access permissions.
ERROR (TTM-008): Error registering recordname on GlobalData file.

EXPLANATION:
The globalData file holds the new Mode Definition data.
USER RESPONSE:
Ensure your file system has enough space for new data. Ensure you have the proper file
access permissions.
ERROR (TTM-009): [Internal] Programmer error. Invalid Comet Name passed to

function. This comet name is not listed in the modeDef stats. Check the spelling and
check that it is not NULL.
EXPLANATION:
USER RESPONSE:
assistance.
ERROR (TTM-010): [Internal] Programmer error. Invalid TTMdataList passed to

function. You must do TTMopenDataList before sending this parameter to a method.
EXPLANATION:

USER RESPONSE:
assistance.
ERROR (TTM-011): [Internal] Programmer error. Invalid TTMvalueList passed to

function. You must do TTMopenValueList before sending this parameter to a method.
EXPLANATION:
USER RESPONSE:
assistance.
WARNING (TTM-012): Error reading recordnamestatistics record from globalData.

extraInfo
EXPLANATION:
The globalData file holds the new Mode Definition data. A problem occurred accessing
or accommodating the globalData information. This could ultimately be terminating.
USER RESPONSE:
Ensure you have the proper file access permissions. Verify that the mode exists for the
WORKDIR provided.
ERROR (TTM-013): [Internal] Programmer error. Invalid TTMhandle passed to

TTMsetMode of mode modename. You must do TTMsetMode before sending this parameter
to a method.
EXPLANATION:
USER RESPONSE:
assistance.
ERROR (TTM-014): Error writing recordname statistics record to globalData.

EXPLANATION:
The statistics record was not written to the globalData file correctly.
USER RESPONSE:

access permissions.
ERROR (TTM-015): [Internal] Programmer error. Invalid TTMhandle passed to

TTMfreeMode. Check to see if the TTMhandle has already been through TTMfreeMode.
EXPLANATION:
USER RESPONSE:
assistance.
ERROR (TTM-016): [Internal] message

EXPLANATION:
USER RESPONSE:
assistance.
ERROR (TTM-017): Mismatch detected on recordname statistics record. Version

version1 is the current release. Your data has version version2. This design must be rebuilt
and new modes created at the current level.
EXPLANATION:
You have a design with an old level of modeDef statistics.
USER RESPONSE:
Rebuild this mode at the latest level.
ERROR (TTM-018): Unable to obtain locktype lock on filename.

EXPLANATION:
One of the following is possible:
The file permissions do not allow you access to the file.
The Build Model process failed.
The file is already in use.

USER RESPONSE:
Perform the following:
Ensure you have the proper file access permissions.
Ensure that the hierModel exists.
Determine whether the file is already in use.
ERROR (TTM-019): Unable to register dependencytype dependency for object1

against object2.
EXPLANATION:
A dependency could not be created between two objects on the globalData file.
USER RESPONSE:
Ensure that you have the proper file access permissions.
ERROR (TTM-020): Tester Description Rule mandatory for mode definition.

EXPLANATION:
The mode definition file is missing the TESTER_DESCRIPTION_RULE statement.
USER RESPONSE:
Add the TESTER_DESCRIPTION_RULE (TDR) statement to your mode definition file.
Ensure the TDR name is valid.
ERROR (TTM-021): Scan information mandatory for mode definition.

EXPLANATION:
The SCAN statement is required in the mode definition file. It specifies the type of scan
design to be used for the design.
USER RESPONSE:
Add the SCAN statement to your mode definition file.
ERROR (TTM-022): Syntax Error: Scan Type specified is not supported. Supported Scan
Types are: NONE, LSSD, GSD, 1149.1, and ASSUMED.
EXPLANATION:
The mode definition file specifies an invalid scan type.
USER RESPONSE:

Specify a valid SCAN TYPE in your mode definition file.
ERROR (TTM-023): Syntax Error: Test Type IOWRAP may not be selected when Scan Type
is 1149.1.
EXPLANATION:
The mode definition file specifies an invalid test type for SCAN TYPE = 1149.1.
USER RESPONSE:
Specify SCAN TYPE = LSSD or GSD if you want TEST_TYPE = IOWRAP.
ERROR (TTM-024): Test Type mandatory for mode definition.

EXPLANATION:
The TEST_TYPE statement is required in the mode definition file. It specifies what type
of tests are to be generated.
USER RESPONSE:
Add the TEST_TYPE statement to your mode definition file.
ERROR (TTM-025): Syntax Error: Test Type specified is not supported. Supported Test
Types are: NONE, STATIC LOGIC SIGNATURES NO, DYNAMIC LOGIC SIGNATURES NO,
SCAN CHAIN, IDDQ, DRIVER RECEIVER, INTERCONNECT, ECID and OPCBIST.
EXPLANATION:
The mode definition file specifies an invalid test type.
USER RESPONSE:
Specify a valid TEST_TYPE in your mode definition file.
ERROR (TTM-026): Syntax Error: Test Type Interconnect may only be selected when Scan
Type is 1149.1.
EXPLANATION:
The mode definition file specifies an invalid test type when SCAN TYPE = LSSD or GSD.
USER RESPONSE:
Specify SCAN TYPE = 1149.1 if you want TEST_TYPE = Interconnect.
ERROR (TTM-027): Faults specified as DYNAMIC require a DYNAMIC Test Type.

EXPLANATION:

The test type specified in the mode definition file is invalid for dynamic faults.
USER RESPONSE:
Specify TEST_TYPE DYNAMIC when you have FAULTS DYNAMIC in your mode
definition file.
ERROR (TTM-028): Test Mode name of modename reserved for system use.
EXPLANATION:
The mode name you selected is reserved for system use and may not be used to create
a new mode.
USER RESPONSE:
You must specify a different MODENAME.
ERROR (TTM-029): Syntax Error: Symbolic substitution not supported.

EXPLANATION:
Invalid syntax was specified in the mode definition file.
USER RESPONSE:
Refer to Mode Definition Statements in the Encounter Test: Guide 2: Testmodes for
correct mode definition file syntax.
ERROR (TTM-030): Pin name pinname not found on design.

EXPLANATION:
The specified pin name does not exist on the hierModel.
USER RESPONSE:
Ensure you are using the correct mode definition file for this design. Ensure the pin name
spelling is correct. You may need to specify the name in double quotes.
WARNING (TTM-031): Net name netname not found on design.

EXPLANATION:
The specified net name does not exist on the hierModel.
USER RESPONSE:
Ensure you are using the correct mode definition file for this design. Ensure the net name

WARNING (TTM-032): modename is not registered in the GlobalData file.

EXPLANATION:
The specified mode name does not exist on the globalData.
USER RESPONSE:
Ensure the mode name specified is spelled correctly.
WARNING (TTM-033): Unable to locate mode modename in recordname statistics

record.
EXPLANATION:
The specified mode name that does not exist in the mode def statistics.
USER RESPONSE:
Check that the mode name specified is spelled correctly.
ERROR (TTM-034): Storage allocation failure in application.

EXPLANATION:
There is not enough free memory for the application to continue running.
USER RESPONSE:
Ensure you have enough free memory to run the application.
ERROR (TTM-035): Sequence Definition file, filename, does not contain a MODE INIT
sequence.
EXPLANATION:
The sequence definition file must contain a MODE INIT sequence in order to continue
running mode definition with the SEQDEF parameter specified on the
build_testmode command line.
USER RESPONSE:
Specify a MODE INIT sequence in the sequence definition file. Refer to Sequence
Definition Application Objects in the Encounter Test: Reference: Test Pattern
Formats for information on sequence definition files.
ERROR (TTM-036): The initialization sequence specifies Begin_Test_Mode modename

(mode number number) but that test mode does not exist. Test Mode Define cannot proceed.

EXPLANATION:
The Begin_Test_Mode statement from the sequence definition file specifies a Parent
Mode name to be used in setting up this Child mode. A Parent Mode must be defined
before building a Child mode. A Parent mode does not exist for this child mode.
USER RESPONSE:
Remove the Begin_Test_Mode statement from the sequence definition file in order to
continue running mode definition; or first run build_testmode for the Parent mode
specified in the Begin_Test_Mode statement from the sequence definition file.
ERROR (TTM-037): A TBD BEGIN_TEST_MODE event was found in the middle of the
initialization sequence. The BEGIN_TEST_MODE event is only allowed as the first event in
the initialization sequence. Processing is terminated.
EXPLANATION:
The Begin_Test_Mode statement from the sequence definition file specifies a Parent
Mode name to be used in setting up this Child mode.
It must be the first statement in the sequence definition file.
USER RESPONSE:
Ensure the Begin_Test_Mode statement is listed first in the sequence definition file.
ERROR (TTM-038): Stim Latch events are not allowed when a Parent Mode is not defined.
EXPLANATION:
A Begin_Test_Mode statement has not been defined in the sequence definition file, thus,
no Parent mode exists. Stim Latch events are only allowed when a Parent Mode is
specified in the sequence definition file. The Stim Latch event depends on a controllable
scan chain being defined to load the latches. Controllable scan chains are only defined
in the context of a test mode, and you cannot use the target test mode to define itself.
You must use the parent test mode to initialize the target test mode.
USER RESPONSE:
If you have a stim latch event, ensure that a Parent Mode has been specified in the
sequence definition file. Otherwise, remove the stim latch events.
ERROR (TTM-039): A valid Net Name must be used in PRPG/MISR definitions. The
specified net name: netname does not exist on the hierModel. Processing Terminates.
EXPLANATION:

The specified net name does not exist on the hierModel.

USER RESPONSE:
Ensure you are using the correct mode definition file for this design. Ensure the net name
ERROR (TTM-040): TDR tdrname is invalid. Processing Terminates.

EXPLANATION:
The TDR could not be processed.
USER RESPONSE:
Check for previous messages regarding TDR processing.
ERROR (TTM-041): LSSD FORCE_B_CLOCK option cannot be used with TEST_TYPE

DYNAMIC. Processing Terminates.
EXPLANATION:
You cannot use the LSSD FORCE_B_CLOCK option when you use TEST_TYPE DYNAMIC
in your mode definition file.
USER RESPONSE:
Remove the LSSD FORCE_B_CLOCK option or remove the statement TEST_TYPE
DYNAMIC and then rerun.
ERROR (TTM-042): Skewed_Scan_Load events are not allowed when a Parent Mode is
defined. Processing Terminates.
EXPLANATION:
A Begin_Test_Mode statement has been defined in the sequence definition file, thus
a Parent mode exists. Skewed_Scan_Load events are used to specify a skewed scan
chain load, causing the correlation of values in adjacent latches to be offset from the
correlation resulting from a normal scan chain load. Encounter Test does not support
the added complexity of figuring out the correct LFSR states that would result from a
skewed load occurring in the parent test mode.
USER RESPONSE:
Remove the Skewed_Scan_Load events and use only Scan_Load events.
ERROR (TTM-043): An Apply event was found in the initialization sequence which starts
with a Begin_Test_Mode event. When using a parent test mode, the initialization sequence
must be self-contained. Processing Terminates.

EXPLANATION:
It requires extra work in test generation to process the initialization sequence when there
is a parent test mode involved and the initialization sequence is broken up into sequence
subroutines invoked by the Apply event. The Apply event can be used in the initialization
sequence only if there is no parent test mode.
USER RESPONSE:
Remove the Apply event(s).
ERROR (TTM-044): The initialization sequence specifies Begin_Test_Mode modename but

that test mode does not exist. Test Mode Define cannot proceed. Processing Terminates.
EXPLANATION:
The test mode initialization sequence contained a Begin_Test_Mode event referring to a
test mode that was not yet built. It is therefore impossible to switch to that test mode to
process the initialization sequence.
USER RESPONSE:
Create the parent test mode before processing this child mode.
ERROR (TTM-045): During mode redefine, delete_testmode failed. Check for previous
messages. Processing Terminates.
EXPLANATION:
The old test mode data must be removed from the global data before the mode can be
redefined. There was a problem removing the old data.
USER RESPONSE:
Check for previous error messages to determine the failure.
ERROR (TTM-046): TDR processing failed on TDR tdrname. Check for previous
EXPLANATION:
The TDR parsing utility failed. It should print a reason for the failure.
USER RESPONSE:
ERROR (TTM-047): build_testmode LBIST processing failed. Check for preceding


EXPLANATION:
There was an error processing the initialization sequences.
USER RESPONSE:
ERROR (TTM-048): Illegal or missing statement_type statement terminator:

terminator.
EXPLANATION:
There was an error processing the MODEDEF file. Each statement must end with a
semicolon.
USER RESPONSE:
Check the MODEDEF file for missing semicolons or for an invalid keyword in the middle
of a statement. This may be interpreted as a missing statement terminator.
ERROR (TTM-049): Conflicting statement_type statement value: value.

EXPLANATION:
There was an error processing the MODEDEF file. The statement value conflicts with a
previously set value.
USER RESPONSE:
Check the MODEDEF file for conflicting statement values. Refer to Mode Definition
Statements in the Encounter Test: Guide 2: Testmodes for proper MODEDEF values.
ERROR (TTM-050): Illegal statement_type statement text: statement_text.

EXPLANATION:
There was an error processing the MODEDEF file. The text for the given statement is not
correct.
USER RESPONSE:
Check the MODEDEF file for illegal statements. Refer to Mode Definition Statements in
the Encounter Test: Guide 2: Testmodes for proper MODEDEF values.

ERROR (TTM-051): Illegal statement_type statement value: statement_value.

EXPLANATION:
There was an error processing the MODEDEF file. The value for the given statement is
not correct.
USER RESPONSE:
Check the MODEDEF file for illegal statements. Refer to Mode Definition Statements
in the Encounter Test: Guide 2: Testmodes for proper MODEDEF values.
ERROR (TTM-052): Missing statement_type statement text.

EXPLANATION:
There was an error processing the MODEDEF file. The given statement is missing the
required text.
USER RESPONSE:
Check the MODEDEF file for incomplete statements. Refer to Mode Definition
Statements in the Encounter Test: Guide 2: Testmodes for proper MODEDEF
syntax.
ERROR (TTM-053): Missing or invalid statement_type statement value:

statement_value
EXPLANATION:
There was an error processing the MODEDEF file. The given statement is missing a
required value.
USER RESPONSE:
Check the MODEDEF file for incomplete statements. Refer to Mode Definition
syntax.
ERROR (TTM-054): Missing test_function_type test function polarity value.

EXPLANATION:
There was an error processing the MODEDEF file. The given test function requires a
polarity value.
USER RESPONSE:
Check the MODEDEF file for incorrect ASSIGN statement flags. Refer to Mode
Definition Statements in the Encounter Test: Guide 2: Testmodes for proper
MODEDEF syntax.

ERROR (TTM-055): Invalid test_function_type test function polarity value.

EXPLANATION:
There was an error processing the MODEDEF file. The given test function was assigned
an invalid test function polarity value.
USER RESPONSE:
MODEDEF syntax.
ERROR (TTM-056): Conflicting test_function_type test function polarity value.

EXPLANATION:
There was an error processing the MODEDEF file. The assigned test function polarity
conflicts with a previously set value.
USER RESPONSE:
MODEDEF syntax.
ERROR (TTM-057): Incomplete statement_type statement - missing

statement_value statement value.
EXPLANATION:
There was an error processing the MODEDEF file. The given statement is missing a
required value.
USER RESPONSE:
Check the MODEDEF file for an incorrect statement. Refer to Mode Definition
syntax.
ERROR (TTM-058): build_testmode assign file processing. Statement statement is

not allowed. Processing Terminates.
EXPLANATION:
There was an error processing the MODEDEF assignfile. The given statement is not
allowed.
USER RESPONSE:

Check the MODEDEF assignfile for an invalid statement. Refer to Mode Definition
syntax.
ERROR (TTM-059): Unable to open MODEDEF assignfile=assignfilename.

EXPLANATION:
There was an error in opening the MODEDEF assignfile.
USER RESPONSE:
Check the directory permissions for this file.
ERROR (TTM-060): Unable to process command line option option. There are
number modes requested and number parameters were specified for this option.
EXPLANATION:
There were multiple modes specified with the TESTMODE option for build_testmode.
The number of parameters specified for the referenced option did not match the number
of modes specified. The parameters for the referenced option must be separated by
commas; no blanks are allowed.
USER RESPONSE:
Review your command line options and verify the number of parameters for each option.
Refer to "build_testmode in the Encounter Test: Reference: Commands for proper
syntax.
ERROR (TTM-061): 1149.1 test mode contains SCAN TYPE=scanType IN=inValue

OUT=outValue. This mode is assumed to be for the purpose of doing stored pattern test
generation. SCAN IN must be specified as PI and OUT must be specified as PO. Processing
terminates.
EXPLANATION:
A test mode containing 1149.1 test function pins (TCK, TMS, TDI, TDO and optional TRST)
and a SCAN TYPE of LSSD, GSD or ASSUMED is for the purpose of doing stored pattern
test generation. The SCAN IN and OUT specifications must be IN and OUT respectively.
The value ONBOARD is for the purpose of doing LBIST test generation.
USER RESPONSE:
If the test mode is to be used for stored pattern test generation, specify IN=PI and
OUT=PO on the SCAN statement in the MODEDEF file. If the test mode is to be used for
LBIST, remove the 1149.1 test function from the MODEDEF file, or override the design

source with an ASSIGN PIN=pinname TEST FUNCTION=NIL statement. Then rerun

build_testmode.
ERROR (TTM-062): SCAN TYPE specified as 1149.1 but the test mode is missing pins with
the following test function pins:tflist. Processing terminates.
Update the BSDL, modedef, or assignfile ito nclude those attributes on the applicable primary
pins.
EXPLANATION:
A SCAN TYPE of 1149.1 implies that the non-TAP, non-IR latches and flip-flops are
configured into one or more scan chains, each of which is scannable via the TAP when
the appropriate instruction is loaded into the IR. This test mode is to be used for the
purpose of Boundary Scan Verification (BSV), interconnect test generation, or for stored
pattern test generation using the TAP controller for scanning.
If the test mode is meant to be used for these purposes, Encounter Test also requires
that test function pin attributes (TCK, TMS, TDI, TDO and an optional TRST) be placed
on the primary input pins to identify the pins of the TAP controller. The test function pin
attributes can be specified in the design source, via an ASSIGN PIN statement in the
MODEDEF file, or can be derived from BSDL if it is specified as input to Build Test Mode.
USER RESPONSE:
If the test mode is to be used for TAP-scan stored pattern test generation, interconnect
test generation or Boundary Scan Verification, specify the appropriate test function pin
attributes. If the test mode is to be used for some other purpose, specify a SCAN TYPE
other than 1149.1. Then rerun Build Test Mode.
ERROR (TTM-063): Test Mode assumed to be for TAP-scan stored pattern test generation,
but TAP_TG_STATE is not specified. Processing terminates.
EXPLANATION:
This test mode is assumed to be for the purpose of doing TAP-scan stored pattern test
generation, due to the specification of SCAN TYPE=1149.1 and the value specified in
the TEST TYPES statement. In order to determine the state of the TAP controller during
test generation, you must also specify the TAP_TG_STATE option on the SCAN
statement.
USER RESPONSE:
If the test mode is to be used for TAP-scan stored pattern test generation, specify the
TAP_TG_STATE option on the SCAN statement.

If the test mode is to be used for Boundary Scan Verification, specify TEST
TYPES=NONE. If the mode is to be used for interconnect test generation, specify
INTERCONNECT in the TEST TYPES statement. Then rerun Build Test Mode.
ERROR (TTM-064): Pseudo primary input ppi_name was defined multiple times in the
hierarchical model with conflicting test function pin attributes.
EXPLANATION:
Two or more cells contained PPI keywords defining this pseudo primary input. In
addition, test function pin attributes were found in these multiple definitions which
conflict. Encounter Test does not know the correct test function pin attribute to place on
this pseudo PI, so it cannot build the test mode.
USER RESPONSE:
Find all occurrences of this pseudo primary input name in your cell library and design
source and verify that they are all the same logical signal. If they are, then one of the test
function pin attributes was specified incorrectly; remove or correct it. If it is more than one
interdependent logical signal that is being referred to, then it is a name conflict, and you
will have to change the name of one of them, and change the corresponding
CUTPOINTS accordingly. These corrections can be made either by editing the design
source and re-importing the design or by adding CUTPOINTS statements in the test
mode definition file and rerunning Build Test Mode.
ERROR (TTM-065): Instruction instruction was not found in the BSDL. Processing
terminates.
EXPLANATION:
The INSTRUCTION option on the SCAN statement identifies which instruction(s) must
be loaded into the IR in order to allow scanning through the TAP port during stored
pattern test generation. The instruction name specified could not be found in the
accompanying BSDL to allow conversion to the appropriate op code.
USER RESPONSE:
If the instruction name specified is incorrect on the SCAN statement, or if the BSDL is
incorrect, specify the correct instruction name. If you have user specified mode
initialization and scan sequences, the INSTRUCTION option is not required. Remove it
from the SCAN statement. Then rerun Build Test Mode.
ERROR (TTM-066): Net netname was identified as a cut point, but is fed by a Primary
Input. Cut points may not be placed on Primary Inputs. Processing terminates.

EXPLANATION:
Cut points are used to determine which logic signals within the design are OPCG
outputs. This allows Encounter Test applications which cannot handle OPCG logic to
ignore it and treat the rest of the package as though the OPCG logic were not present.
The net specified was identified as a cut point, but is fed directly by a primary input, so it
cannot be the output of OPCG logic.
USER RESPONSE:
If you are attempting to assign a test function to the logic signal, use the ASSIGN PI test
mode definition statement, instead of the CUTPOINTS and ASSIGN PPI statements.
Otherwise, you may have specified an incorrect net name in a CUTPOINTS statement.
Correct the net name, and rerun Build Test Mode.
ERROR (TTM-067): Error in CUTPOINT or PPI attribute: attribute on cell cellname.

Reason: reason. Processing terminates.
EXPLANATION:
An error was detected in the logic model attribute describing a cutpoint or pseudo
primary input (PPI). A description of the error is also given.
USER RESPONSE:
Correct the error in the attribute and rerun build_testmode.
ERROR (TTM-068): Cutpoint cutpoint specified in source is not correlated to a flat

model node. Processing terminates.
EXPLANATION:
The specified cutpoint cannot be correlated to a flat model node. There is either a
programming error, or the cutpoint is specified on a sourceless, sinkless net.
USER RESPONSE:
Correct the definition of the cutpoint and rerun build_testmode, or contact customer
WARNING (TTM-069): [Severe] A cutpoint was placed on net netName on statement

number stmtNumber that contained fanout and was subject to model reduction As a result
from the reduction, the cutpoint was placed on a feeding gate that may not accurately
represent the desired cutpoint result.
EXPLANATION:

As a result of model reduction, the cutpoint specification has changed. The node feeding
the reduced buffer or inverter will now be the cutpoint location. This may yield
undesirable results when stimming the PPI.
USER RESPONSE:
Choose among the following actions:
Override the model reduction on the buffer or inverter by placing a
TB_REDUCE=NO attribute on instances of hierarchical blocks. If
TB_REDUCE=NO is specified, all buffers and inverters within the usage of the
level of hierarchy will not be reduced.
Move the cutpoint to a more desirable net.
Override the model reduction by specifying reducemodel=no on the
WARNING (TTM-070): Error writing recordname statistics record to globalData.

EXPLANATION:
The statistics record was not written to the globalData file correctly.
USER RESPONSE:
access permissions.
WARNING (TTM-071): The questionable value value was passed into method
methodName.
EXPLANATION:
An internal programming error may have occurred. The value identified is suspicious in
that it was not expected. There may be other errors associated with this message
indicating that a programming error has occurred.
USER RESPONSE:
If the problem reoccurs, contact customer support (see Contacting Customer Service
on page 23).
ERROR (TTM-072): Invalid Test Type TYPE value. br The Test Type TYPE value of
TEST_RESET is not valid for OPMISR test modes (when the SCAN OUT value in the Scan
statement = TO_MISR).
EXPLANATION:

Either the Test Type TYPE value is invalid OR the SCAN OUT value in the Scan
statement is invalid. The TEST_RESET Test Type TYPE is only valid for modes that are
OPMISR.
USER RESPONSE:
Ensure that the TEST_TYPE TYPE value specified is valid. Refer to TEST_TYPES in
the Encounter Test: Guide 2: Testmodes. Correct the Scan Out value to TO_MISR to
specify an OPMISR test mode.
ERROR (TTM-073): A PIPELINE_DEPTH value cannot be specified with PIs that have test
function definition of badtest_testfunctions in compression testmodes. Only test
function values of SI, SO, CMI, or CME are allowed. A test function value of BDY, CTL or OLI
may also be specified inconjunction with the previous values.
EXPLANATION:
The PIPELINE DEPTH value can only be specified for Scan_Ins, Scan_Outs,
Channel_Mask_Enables, and Channel_Mask_Inputs for compression testmodes.
A test function value of BDY, CTL, or OLI may also be specified inconjunction with the
previous values.
USER RESPONSE:
If the testmode is intended to be a compression testmode use a mode definition file
which specifies in=pi and out=compactor on the SCAN statement of that file.
If the testmode is not intended to be a compression testmode remove the PIPELINE
keyword from the Assign statements of all Scan_Ins, Scan_Outs,
Channel_Mask_Enables, and Channel_Mask_Inputs. Rerun after making the
required corrections.
ERROR (TTM-074): Error finding core instance coreInstanceName in the chip model.
EXPLANATION:
Cannot fine the specified core instance in the chip model.
USER RESPONSE:
Ensure that the assign file has the right core instance name.
ERROR (TTM-077): Clock Domain clockDomainName is listed more than once in

PARENT_DOMAIN_NAME statements. Every clock domain used in
PARENT_DOMAIN_NAME statements must be unique.
EXPLANATION:

Each shadow clock domain must behave identically to its parent. If a shadow clock
domain is also a parent domain or same clock domain have two parent domains or the
same parent domain is listed in two separate PARENT_DOMAIN_NAME statements,
then the statements can be reorganized so that every clock domain used in any
PARENT_DOMAIN_NAME statements is unique.
USER RESPONSE:
Detemine why any clock domain is listed more than once in PARENT_DOMAIN_NAME
statements. Reorganize the PARENT_DOMAIN_NAME statements to ensure that no
clock domain appears more than once in the PARENT_DOMAIN_NAME statements. If
appropriate, you may combine two PARENT_DOMAIN_NAME statements into a single
statement (with a single parent domain). Edit the modedef or assign file accordingly and
rerun the job.
ERROR (TTM-082): A shadow domain and its parent are not identical. Domain
clockDomainName has a different number of registers than Domain
clockDomainName.
EXPLANATION:
The two clock domains identified in the message are related as parent and shadow by
the testmode definition statement PARENT_DOMAIN_NAME=<domain name>. Each
shadow clock domain must behave identically to its parent, but these two domains have
different programming registers. Since they have different registers, we do not know how
to program the domains identically.
USER RESPONSE:
Determine whether these two clock domains should be related. If so, they must have
identical OPCG registers defined. The registers must have identical names, and be the
same length. Change the netlist and reprocess the circuit. If the domains should not be
related, then change the PARENT_DOMAIN_NAME statement in the testmode definition
or assign file and rerun this job.
ERROR (TTM-083): A shadow domain and its parent are not identical. Domain
clockDomainName has a register registerName which is not defined for Domain
clockDomainName.
EXPLANATION:
The two clock domains identified in the message are related as parent and shadow by
the testmode definition statement PARENT_DOMAIN_NAME=<domain name>. Each
shadow clock domain must behave identically to its parent, but these two domains have
different programming registers. Since they have different registers, we do not know how
to program the domains identically.

USER RESPONSE:
Determine whether these two clock domains should be related. If so, they must have
identical OPCG registers defined. The registers must have identical names, and be the
same length. Change the netlist and reprocess the circuit. If the domains should not be
related, then change the PARENT_DOMAIN_NAME statement in the testmode definition
or assign file and rerun this job.
ERROR (TTM-088): Domain clockDomainName or its DOMAIN_GO_REF signal is not

sourced by a PLL. Every clock domain listed as a parent or shadow in the
PARENT_DOMAIN_NAME statement must be source by a PLL and so should be its
DOMAIN_GO_REF signal.
EXPLANATION:
The clock domain identified in the message is listed as a parent or shadow by the
testmode definition statement PARENT_DOMAIN_NAME=<domain name>. Such a
clock domain and its DOMAIN_GO_REF signal must be sourced by a PLL.
USER RESPONSE:
Determine whether the clock domain should be listed in testmode definition statement
PARENT_DOMAIN_NAME=<domain name>. If it should, then the domain and its
DOMAIN_GO_REF signal must be sourced by a PLL. If necessary, change the netlist
and reprocess the circuit. If this domain should not be a parent or shadow to another
domain, then change the PARENT_DOMAIN_NAME statement in the testmode
definition or assign file and rerun the job.
ERROR (TTM-090): FLH latches cannot be used for testmodes for Hierarchical Test.
EXPLANATION:
FLH latches cannot be used for testmodes for Hierarchical Test.
USER RESPONSE:
Remove FLH test function from latches to be able to use Hierarchical Test for this
testmode.
ERROR (TTM-091): PRPG registers cannot be used for testmodes for Hierarchical Test.
EXPLANATION:
PRPG registers cannot be used for testmodes for Hierarchical Test.
USER RESPONSE:

Remove PRPG registers from the design to be able to use Hierarchical Test for this
testmode.
ERROR (TTM-092): Command line argument noncontactedbidiatz was assigned a

value of yes for this testmode. This testmode is used for Hierarchical Test.
EXPLANATION:
noncontactedbidiatz = yes can not be specified for testmodes for Hierarchical
Test.
USER RESPONSE:
Remove noncontactedbidiatz statement from your command line.
ERROR (TTM-093): Scan Fill values can not be specified for bypass testmodes for
Hierarchical Test.
EXPLANATION:
Scan Fill values can not be specified for bypass testmodes for Hierarchical Test.
USER RESPONSE:
Remove the SCAN_FILL statement from your mode definition file.
ERROR (TTM-094): Test Type Interconnect can not be specified for testmodes for
Hierarchical Test.
EXPLANATION:
Test Type Interconnect can not be specified for testmodes for Hierarchical Test.
USER RESPONSE:
Change the TEST_TYPES statement in your mode definition file to remove Interconnect
TEST_TYPES.
ERROR (TTM-095): Test Type 'MACRO' can not be specified for testmodes for Hierarchical
Test.
EXPLANATION:
Test Type MACRO can not be specified for testmodes for Hierarchical Test.
USER RESPONSE:
Change the TEST_TYPES statement in your mode definition file to remove MACRO
TEST_TYPES.

ERROR (TTM-096): A partition file is specified. This is not supported for Hierarchical Test.
EXPLANATION:
A partition file is specified. This is not supported in Hierarchical Test.
USER RESPONSE:
Build testmode without the use of partition file.
ERROR (TTM-097): Scan Type '1149.1' can not be specified for testmodes for Hierarchical
Test.
EXPLANATION:
Scan Type 1149.1 cannot be specified for testmodes for Hierarchical Test.
USER RESPONSE:
Change the Type keyword of the Scan statement in your mode definition file to GSD.
ERROR (TTM-098): Scan Type ASSUMED can not be specified for testmodes for Hierarchical
Test.
EXPLANATION:
Scan Type ASSUMED can not be specified for testmodes for Hierarchical Test.
USER RESPONSE:
ERROR (TTM-099): Scan Type NONE can not be specified for testmodes for Hierarchical
Test.
EXPLANATION:
Scan Type NONE can not be specified for testmodes for Hierarchical Test.
USER RESPONSE:
ERROR (TTM-100): Scan Type LSSD can not be specified for testmodes for Hierarchical
Test.
EXPLANATION:
Scan Type LSSD can not be specified for testmodes for Hierarchical Test.
USER RESPONSE:

ERROR (TTM-101): [Internal] Program error Test Structure Identification.

Error Analysis Information = error_info
EXPLANATION:
There was a severe problem during Test Structure Identification.
USER RESPONSE:
Save the error analysis information and contact customer support (see Contacting
INFO (TTM-102): Test Structure Identification processing complete.

EXPLANATION:
The Test Structure Identification process, which does some preprocessing of the design
for Test Structure Verification, is complete.
USER RESPONSE:
INFO (TTM-103): Test Structure Identification processing has started.

EXPLANATION:
The Test Structure Identification process, which does some preprocessing of the design
for Test Structure Verification, has started.
USER RESPONSE:
No response is necessary.
WARNING (TTM-104): The current stack size (bytes1 bytes) may be insufficient. Raise
the system stack limit to at least bytes2 bytes to avoid stack problems when processing this
design.
EXPLANATION:
If the test mode definition completes successfully, you may disregard this message. If the
test mode definition had trouble due to stack overflow (a process was terminated or a
core file was produced), the problem is likely to be caused by insufficient stack space
based upon a system set limit. The problem (and message) can be avoided by raising
the stack limit of the system (or for the specific user) to the amount shown in the
message.

USER RESPONSE:
If the test mode definition completes successfully, you may disregard this message. If the
test mode definition encounters difficulty due to stack overflow (a process terminated or
core file produced), the problem is likely caused by insufficient stack space based upon
a system-set limit. The problem (and message) can be avoided by raising the stack limit
of the system (or for the specific user) to the amount shown in the message. You can
check the current stack limit by using the ulimit -a Unix command. Unix commands
ulimit -Sd unlimited, ulimit -Sm unlimited and ulimit -Ss unlimited can be used to
maximize the system stack resources.
WARNING (TTM-105): [Severe] The mode definition SCAN_TYPE statement specifies

LENGTH = m, which is less than the length of the longest scan chain for this test mode, n.
The LENGTH parameter specified will be ignored, and the length of the longest scan chain,
n, will be used for the length of the scan sequence.
EXPLANATION:
The LENGTH parameter of the mode definition SCAN_TYPE statement was used to
override the default scan sequence length, but the LENGTH specified was smaller than
the longest scan chain in this test mode. The LENGTH specification will therefore be
ignored and the length of the longest scan chain in this test mode will determine the
length of the scan sequence.
USER RESPONSE:
If you wish to control the length of the scan sequence then you must change the
LENGTH specification in the mode definition statement to be at least as large as the
length of the longest scan chain in this test mode, and then rerun Build Test Mode.
INFO (TTM-106): The mode definition SCAN_TYPE statement specifies LENGTH = m, which
is greater than the length of the longest scan chain for this test mode, n. The LENGTH
specified, m, will be used for the length of the scan sequence.
EXPLANATION:
The LENGTH parameter of the mode definition SCAN_TYPE statement was used to
override the default scan sequence length. All scan operations will use the specified
LENGTH.
USER RESPONSE:
Verify that the specified LENGTH satisfies your needs. If so, then no further response is
required. If the specified LENGTH is incorrect, respecify it in the mode definition
SCAN_TYPE statement and rerun Build Test Mode.

ERROR (TTM-107): There are clockNumber clocks defined for the current testmode
which exceeds Encounter Test limit clockLimit.
EXPLANATION:
Encounter Test supports up to 450 clocks in a testmode. Exceeding this limit will cause
build_testmode to terminate.
USER RESPONSE:
Reduce total clock number below Encounter Test limit --- 450.
ERROR (TTM-108): Sequence definition file, filename, could not be found in the
sequence definition path. Correct the sequence definition file name and/or sequence
definition path to identify an existing sequence definition file.
EXPLANATION:
When a sequence definition file has been defined in the mode definition file or is
specified to the build_testmode command by the SEQDEF keyword , it must exist in
the sequence definition path as specified by the SEQPATH keyword
USER RESPONSE:
Correct the filename and/or SEQPATH and then rerun.
INFO (TTM-112): Error reading recordname statistics record from globalData.

EXPLANATION:
The globalData file contains the new Mode Definition data.
USER RESPONSE:
Ensure proper file access permissions, verify that the mode exists for the specified
WORKDIR, and rerun if necessary.
ERROR (TTM-113): The PARENT_DOMAIN_NAME statement for domain

clockDomainName identifies domain clockDomainName as a shadow. These two
domains are not identical because one is an internal domain (INTERNAL_DOMAIN_NAME)
and the other is not. You must redefine one of the domains or remove this one as a shadow
of this parent.
EXPLANATION:
Each shadow domain must behave identically to its parent, but internal (static) domains
are assumed to behave differently from at-speed (dynamic) domains.
USER RESPONSE:

Determine whether the identified domain should be a shadow of this parent. If not,
change the PARENT_DOMAIN_NAME statement by removing this one from the shadow
list. If it should be shadowing this parent, then you will have to change the definition of
one of the domains so that they match (both defined in DOMAIN_NAME statements or
both defined in INTERNAL_DOMAIN_NAME statements).
ERROR (TTM-114): Domain clockDomainName is identified as a parent or a shadow

domain in a PARENT_DOMAIN_NAME statement. But one of its registers,
domainRegName, has a name which does not have the format of
<domainName>.<localRegisterName>. Thus, the registers in the parent and shadow
cannot be correlated, so it is not possible to copy register values from one domain to the other.
EXPLANATION:
To shadow a domain, it is necessary to copy the programming values of the parent's
registers to the corresponding shadow domain registers. Without having the naming
convention of <domainName>.<localRegisterName>, we do not know how to
map the parent domain programming into the shadow domain.
USER RESPONSE:
Rename the domain registers to follow the convention
<domainName>.<localRegisterName> and rerun the job. Make sure the
<localRegisterName> portion of all the domain register names match between
parent and shadow domains.
ERROR (TTM-120): Assign/ModeDef file had an unclosed block comment when an EOF
was encountered.
EXPLANATION:
The Assign or Mode Definition file contains an unclosed block comment when the End-
Of-File was reached. All text following the opening of the block comment is ignored.
Processing terminates with a bad token indication since the end of the block comment
could not be determined.
USER RESPONSE:
Ensure the block comment is closed with a corresponding */ and rerun if necessary.
ERROR (TTM-121): Both scan control pipeline and compression pipeline are found in the
current testmode.
EXPLANATION:
Encounter Test does not support scan control pipeline and compression pipeline in one
single testmode. Scan control pipeline and compression pipeline are mutually exclusive.

USER RESPONSE:
Ensure that only one type of pipeline compression is defined in the current testmode and
then rerun.
WARNING (TTM-122): [Severe] Pin pin_name was assigned pipeline depth value1.
However, the pipeline depth found by Encounter Test is value2.
EXPLANATION:
The detected pipeline depth on the referenced pin is shorter than the specified value.
This indicates that the compression pipeline may not properly work.
USER RESPONSE:
Review and correct the compression pipeline design and specification, and then rerun.
ERROR (TTM-123): The length of Channel Mask Enable Pipeline and Internal Scan Data
Length, length of CME pipeline + ISDL, is greater than the length of the
Compressed_Input_Stream event, length of Compressed Input Stream
Event.
EXPLANATION:
Encounter Test detects the existing Channel Masking Enable Pipelines length + Internal
Scan Data length is greater than the length of the Compressed_Input_Stream event.
USER RESPONSE:
Review and correct the compression pipeline design and specification, and then rerun..
ERROR (TTM-124): Channel Masking Enable pipelines have different defined depth.
EXPLANATION:
Encounter Test requires all Channel Masking Enable (CME) pipelines, if they exist, to
have the same length.
USER RESPONSE:
Ensure all Channel Masking Enable (CME) pipelines have the same length, and then
rerun.
ERROR (TTM-126): Pin pinname has a test function of TC pin in addtion to one or more
of the following test functions; SI, TDI, OLI, or CMI. Testmodes which are identified as migrate
testmodes do not allow this combination.
EXPLANATION:

For testmodes which have boundary=migrate specified in the Scan statement of the
mode definition file the pins used for scan data cannot also be specified as Test
Constraint pins as the insertion of pipelines for those pins at the chip level cannot support
the required TC value and the required pipeline priming.
USER RESPONSE:
Remove the TC test functiion from the pin.
ERROR (TTM-250): The sequence definition file contains a misrobserve sequence and
the test modes SIGNATURE=YES keyword, of the TEST_TYPES statement, specified a type
of TEST_SERIAL_RESET.
EXPLANATION:
Encounter Test supports the observation and reset of a MISR by either the use of
misrobserve and misrobserve sequences or by the use of sigobs and sigobsrtn
sequences. When TYPE TEST_SERIAL_RESET is specified a misrobserve
sequence cannot be used.
USER RESPONSE:
If the MISRs are to be observed via the misrobserve sequence remove the
TEST_SERIAL_RESET specification from the TEST_TYPES statement. If the MISRs are
to be observed via the sigobs sequence, remove the misrobserve sequence from the
sequence definition file.
ERROR (TTM-251): The sequence definition file contains a misrreset sequence and the
test modes SIGNATURE=YES keyword, of the TEST_TYPES statement, specified a type of
TEST_SERIAL_RESET.
EXPLANATION:
Encounter Test supports the observation and reset of a MISR by either the use of
misrobserve and misrreset sequences or by the use of sigobs and sigobsrtn
sequences. When TYPE=YES TEST_SERIAL_RESET is specified a misrreset sequence
cannot be used.
USER RESPONSE:
If the MISRs are to be reset via the misrreset sequence remove the
TEST_SERIAL_RESET specification from the TEST_TYPES statement. If the MISRs are
to be reset via the sigobsrtn sequence remove the misrreset sequence from the
sequence definition file.


WARNING (TTM-267): Latch blockname was designated as TB_STABILITY=value1
but the scan sequence does not force it to this state. It will be treated as scan-corruptible to
value2. There are a total of n latches in this category.
EXPLANATION:
Encounter Test was told via the TB_STABILITY attribute to assume that the identified
latch is at the specified value when the design is in the test constraint and clocks off state.
If the scan operation does not leave the latch at this specified value, invalid tests may
result. Encounter Test was unable to verify this scan-corrupted state.
USER RESPONSE:
Make sure the TB_STABILITY attribute was specified on the correct latch, and with the
correct value. If so, then you should verify that the tests are valid by resimulating at least
a sample of the tests in a test mode where the TB_STABILITY attribute was not used,
after expanding the test data to unravel the BIST loops and the scan sequences
WARNING (TTM-268): [Severe] Latch blockname was designated as

TB_STABILITY=value but it is scan corrupted to the opposite state.
EXPLANATION:
Encounter Test was told via the TB_STABILITY attribute to assume that the identified
latch is at the specified value when the design is in the test constraint and clocks off state.
If the scan operation does not leave the latch at this specified value, invalid tests may
result.
Encounter Test found that the scan operation does not leave the latch at the specified
value, so the exposure to invalid test data is high.
USER RESPONSE:
Make sure the TB_STABILITY attribute was specified on the correct latch, and with the
correct value. If so, then you should verify that the tests are valid by resimulating at least
a sample of the tests in a test mode where the TB_STABILITY attribute was not used,
after expanding the test data to unravel the BIST loops and the scan sequences
WARNING (TTM-269): [Severe] Block blockname was designated as

TB_STABILITY=value1 but it is set to value2 by the mode initialization sequence.
EXPLANATION:

Any pins or nets that have a defined stability value must be left at that value after applying
the modes initialization sequence. The identified block failed to be at its stability value at
the end of the mode initialization sequence.
USER RESPONSE:
Make sure the TB_STABILITY value is correct. If it is not, change it in the model source
and re-import the design. Otherwise, correct the mode initialization sequence so that the
identified block is forced to its TB_STABILITY value and rerun Create a Test Mode.
ERROR (TTM-270): On-Board LFSRs were detected and the primary input test functions
indicate that multiple scan sections are required.
EXPLANATION
Encounter Test currently does not support the use of multiple scan sections in a test
mode which uses PRPGs or MISRs.
Intent:
This is a basic Encounter Test limitation that is being enforced.
USER RESPONSE:
If you want to use an on-board LFSR, you will need to perform all scan operations within
a single scan section.
WARNING (TTM-271): The user specified Diagnostic Mode name, testmode name does
not exist.
EXPLANATION:
In order to be able to perform diagnostic scan out operations for a scan to MISR test
mode, it is required that a valid test mode be identified that can be switched to for this
purpose.
Intent:
If you need to allow diagnostic scan out operations, the Diagnostic Mode Name must
specify the name of a valid test mode. This mode must perform scan operations such
that scan chains are scanned out through chip I/O pins.
USER RESPONSE:

If the ability to perform diagnostics for a Scan to MISR test mode is important, specify,
on the Diagnostic_Mode statement, the name of a test mode which has already been
defined for the purpose of scanning out internal latch contents for diagnostics. This test
mode should be a traditional full scan (through the chip pins) test mode.
WARNING (TTM-272): The user supplied Diagnostic_Observe_Sequence,

sequence_name, does not contain a Going_To_Mode object.
EXPLANATION:
It is not required to supply the Diagnostic_Observe_Sequence and
Diagnostic_Return_Sequence in a Scan_To_MISR mode. If provided, the following
criteria must be met:
Both the Diagnostic_Observe_Sequence and
Diagnostic_Return_Sequence must be supplied.
Both sequences must contain a Going_To_Mode object and an
In_Test_Mode object.
The specified modes in the Going_To_Mode object and the In_Test_Mode
objects must be identical.
The names for the Going_To_Mode and In_Test_Mode objects must be the
same as the specified diagnostic mode name.
USER RESPONSE:
Ensure the user supplied diagnostic sequences comply with the requirements stated in
the explanation of this message and rerun if necessary.
WARNING (TTM-273): In the user supplied Diagnostic_Observe_Sequence,

sequence_name, the mode specified in the Going_To_Mode object does not match the
mode specified in the In_Test_Mode object.
EXPLANATION:
Both sequences must contain Going_To_Mode and In_Test_Mode objects.
objects must match.

The names of the Going_To_Mode and In_Test_Mode objects must be the

USER RESPONSE:
Ensure the supplied diagnostic sequences comply with the requirements stated in the
explanation of this message and rerun if necessary.
WARNING (TTM-274):The user supplied Diagnostic_Observe_Sequence,

sequence_name, specifies a Going_To_Mode testmode_name which is differs from the
user specified diagnostic mode name, diagmode_name.
EXPLANATION:
objects must match.
USER RESPONSE:

sequence_name, does not contain an In_Test_Mode object.
EXPLANATION:


objects must match.
USER RESPONSE:
the explanation of this message.
WARNING (TTM-276): The user supplied Diagnostic_Return_Sequence,

sequence_name, the mode specified in the Going_To_Mode object does not match the
mode specified in the In_Test_Mode object.
EXPLANATION:
objects must match.
USER RESPONSE:

sequence_name, specifies an In_Test_Mode testmode_name which differs from the
user specified Diagnostic Mode name, diagmode_name.
EXPLANATION:


objects must match.
USER RESPONSE:

sequence_name, does not contain a Going_To_Mode object.
EXPLANATION:
objects must match.
USER RESPONSE:
WARNING (TTM-279): On-Board PRPG, identified by netname does not feed into any
channel latches.
EXPLANATION:
None of the PRPGs cells feed to a Channel Latch.
USER RESPONSE:
If you intended that the PRPG connect to channels, correct the design to establish this
connection and then rerun.


sequence_name, specifies a Going_To_Mode testmode_name which differs from the
target mode name, diagmode_name.
EXPLANATION:
objects must match.
USER RESPONSE:

sequence_name, does not contain an In_Test_Mode object.
EXPLANATION:
objects must match.
USER RESPONSE:

WARNING (TTM-283): The user-supplied Diagnostic_Return_Sequence,

sequence_name, specifies an In_Test_Mode testmode_name, which is different than
the target mode name, diagmode_name.
EXPLANATION:
objects must match.
USER RESPONSE:
Ensure the user-supplied diagnostic sequences comply with the requirements stated in
WARNING (TTM-284): Either a Diagnostic_Observe_Sequence or a

Diagnostic_Return_Sequence sequence_name were specified, but not both.
EXPLANATION:
objects must match.

USER RESPONSE:
Ensure the user-supplied diagnostic sequences comply with the requirements stated in
WARNING (TTM-285): No diagnostic sequences were specified and the Diagnostic Mode
was not specified. Diagnosis of OPMISR tests will not be possible.
EXPLANATION:
OPMISR and OPMISR+ test modes require the use of a diagnostic mode to scan out the
states of all internal scan elements for diagnosis. All required sequences must be
specified for custom scan sequences, including diagnostic observe (diagobserve) and
diagnostic return (diagreturn) sequences. If these are not defined, the program
attempts to create default sequences, but only if the diagnostic test mode is specified.
USER RESPONSE:
Specify a diagnostic test mode when defining an OPMISR or OPMISR+ test mode, which
is normally a full-scan mode. For example, DIAGNOSTIC_MODE=FULLSCAN; might be
appropriate in the mode definition file. When custom scan sequences are being defined
for an OPMISR mode, include sequences of type diagobserve and diagreturn that
will move the design from the OPMISR mode to the diagnostic mode and back so that
diagnostics can be performed.
WARNING (TTM-286): [Severe] No MISR_Observe (MO) pins are defined in this OPMISR
test mode and there is no signature observation sequence defined. Signatures cannot be
observed. Define the MO pins in the assign file and rebuild the test mode.
EXPLANATION:
For OPMISR or OPMISR+ test modes, the MISR signatures must be read out in one of the
following ways:
In parallel through a space compactor at device output pins that are identified
as MISR_Observe (MO) test function pins.
Serially through use of a signature observation mode. Normally MISR
signatures are read in parallel at MISR_Observe (MO) test function pins.
No MO pins are defined for this test mode and there was no signature observation test
mode defined to indicate serial observation using the scan chains defined in another
mode. There is no means defined to observe the signatures for this mode.
USER RESPONSE:
For most cases a set of MISR Observe (MO) test function pins should be defined in the
mode definition file or the assign file. If serial unloading of the signatures is intended,

specify the SIGNATURE_OBSERVATION_MODE statement in the mode definition file or

assign file. Refer to SIGNATURE_OBSERVATION_MODE in the Encounter Test:
Guide 2: Testmodes.
Note that it is possible to use both MO pins for parallel observation and a signature
observation mode for serial observation of signatures. You may be able to continue on to
create tests in this mode, but this will only give an indication of the fault coverage that
may be attainable since the signatures are observable.
It is required that you eventually rebuild this test mode with the MO pins defined or a
signature observation mode defined.
WARNING (TTM-287): [Severe] There is no MISR_Observe sequence. MISR signatures

cannot be observed. Either define MISR_Observe (MO) test pins and let Encounter Test
generate the scan sequences, or add a misrobserve sequence type to your custom scan
sequence definitions.
EXPLANATION:
For OPMISR and OPMISR+ test modes, unless the MISR signatures are expected to be
serially unloaded, the MISR states are read in parallel at MISR_Observe (MO) test
function pins.This is accomplished by a special sequence of type=misrobserve that
is applied after the response data had been scanned out into the MISRs but before the
MISRs are reset. Encounter Test will normally generate such a sequence, but not if
custom scan sequences have been defined in which case this special sequence must be
supplied with all other scan-related sequences when the test mode is being defined.
USER RESPONSE:
When defining custom scan sequences for an OPMISR or OPMISR+ test mode, a
sequence definition of type=misrobserve must be defined and applied within the
scansequence after the scansection but before the misrreset sequence is
applied (using Apply events). However, if the intent is to only perform serial MISR
observation by serially scanning out the final signature using a separate test mode, then
a SIGNATURE_OBSERVATION_MODE statement must be used in the mode definition file
or assign file when defining the test mode. If custom scan sequences are being defined,
a sequence type of sigobs should be defined.
It is required that you eventually rebuild this test mode such that a misrobserve
sequence is defined or a sigobs sequence is defined.
WARNING (TTM-288): [Severe] The misrobserve sequence does not contain a single
Measure_MISR_Data event. MISR signature observation will not work without such events.
This should be fixed before continuing.
EXPLANATION:

MISR observation is done in OPMISR and OPMISR+ test modes by viewing the MISR
bits at MISR_Observe (MO) test function pins. The sequence of events that enable the
paths from the MISRs to the MO pins and then actually indicate that the MISR values
should be observed at these pins is denoted within a sequence definition of type
misrobserve.
A misrobserve sequence should designate what pins to observe and when to do it by
including a Measure_MISR_Data event that lists which pins (all the MO pins) should be
being observed at the time of the event. This event is missing from the misrobserve
sequence and as such cannot actually measure the MISR signatures.
USER RESPONSE:
Presumably the misrobserve sequence was manually written. Update the sequence
to include the use of the Measure_MISR_Data event and then rebuild the test mode.
WARNING (TTM-289): [Severe] The sequence sequence is missing. Both

misrobserve and misrreset sequence types should be defined for an OPMISR or
OPMISR+ test mode. This should be fixed before continuing.
EXPLANATION:
For OPMISR and OPMISR+ test modes, there should be a sequence defined for
observing the MISR bits and for resetting the MISR states.
At least one of these special sequences was not found. The undefined sequence type is
indicated in the message text.
USER RESPONSE:
Define both a misrobserve and a misrreset sequence when defining custom scan
sequences for OPMISR or OPMISR+ test modes.
The only condition where a misrobserve sequence is not required is for a signature
observation test mode since the MISRs will be observed by serially unloading them using
the scan chains of the signature observation test mode.
ERROR (TTM-290): Multiple scan sections are defined for a testmode with on-board LFSRs
or compression. This is not supported. This must be fixed before continuing.
EXPLANATION:
Encounter Test currently limits the use of multiple scan sections to test modes that use
basic scan chains only. When any kind of compression or LBIST functionality, such as
PRPGs, MISRs or space compactors are used in a test mode, then that test mode is not
permitted to use more than a single scan section. Note that multiple scan sections are
typically used for scanning multiple IEEE 1149.1 scan chains that use separate

instructions to enable each chain to shift; these different "scan shift states" are what
require the use of multiple scan sections.
USER RESPONSE:
Ensure that only one scan section is used for any test modes that use any kind of
compression or LBIST and rerun.
WARNING (TTM-291): pinName is not set to the Diagnostic Mode stability value by the
Diagnostic_Observe sequence.
EXPLANATION:
When switching from the base test mode to the diagnostic observation test mode,
Encounter Test requires that the sequence used to perform the switching must correctly
set all signals required to establish the diagnostic mode. The referenced signal,
(pinName), is expected to be at a specific value when in the diagnostic mode, but
analysis of the Diagnostic_Observe sequence shows that this pin is not at its
required value.
USER RESPONSE:
The identified signal or pin is required to be at a value in order to be considered to have
successfully switched to the diagnostic mode. Update the Diagnostic_Observe
sequence to ensure this signal is set to the required value.
WARNING (TTM-292): The Diagnostic_Observe sequence cannot be simulated.

EXPLANATION:
The Diagnostic_Observe sequence cannot be simulated due to one of following
conditions:
The specified Diagnostic Mode name does not exist.
The supplied Diagnostic_Observe_Sequence does not contain a
Going_To_Mode object.
The supplied Diagnostic_Observe_Sequence specifies a
Going_To_Mode which differs with the specified Diagnostic Mode name.
The supplied Diagnostic_Observe_Sequence does not contain an
The supplied Diagnostic_Observe_Sequence specifies an
In_Test_Mode that differs from the specified Diagnostic Mode name.

In the supplied Diagnostic_Observe_Sequence, the mode in the

Going_To_Mode object does not match the mode in the In_Test_Mode
object.
In the supplied Diagnostic_Return_Sequence, the mode specified in the
Going_To_Mode object does not match the mode specified in the
A Diagnostic_Observe_Sequence or a
Diagnostic_Return_Sequence were supplied. Both are required.
No diagnostic sequences were supplied the Diagnostic Mode was not specified.
USER RESPONSE:
Use the conditions described in the preceding explanation to correct the diagnostic
sequence.
WARNING (TTM-293): Simulation of the Diagnostic_Return sequence does not result

in the stability state of the Scan to MISR mode. It will be replaced with the modeinit sequence.
The pin pinName is not at its required value.
EXPLANATION:
When switching from the base test mode to the diagnostic return test mode, Encounter
Test requires that the sequence used to perform the switching must correctly set all
signals required to establish the diagnostic mode. The referenced signal, (pinName), is
expected to be at a specific value when in the diagnostic mode, but analysis of the
Diagnostic_Return sequence shows that this pin is not at its required value.
USER RESPONSE:
successfully switched to the diagnostic mode. Update the Diagnostic_Return
successfully switched to the diagnostic mode. Update the Diagnostic_Observe
WARNING (TTM-294): The Diagnostic_Return sequence cannot be simulated.

EXPLANATION:
The Diagnostic_Return sequence cannot be simulated due to one of following
conditions:
The specified Diagnostic Mode name does not exist.

The supplied Diagnostic_Observe_Sequence does not contain a

Going_To_Mode object.
The supplied Diagnostic_Observe_Sequence specifies a
Going_To_Mode that differs with the specified Diagnostic Mode name.
The supplied Diagnostic_Observe_Sequence does not contain an
The supplied Diagnostic_Observe_Sequence specifies an
In_Test_Mode which differs from the specified Diagnostic Mode name.
In the supplied Diagnostic_Observe_Sequence, the mode in the
Going_To_Mode object does not match the mode in the In_Test_Mode
object.
In the supplied Diagnostic_Return_Sequence, the mode specified in the
Going_To_Mode object does not match the mode specified in the
A Diagnostic_Observe_Sequence or a
Diagnostic_Return_Sequence were supplied. Both are required.
No diagnostic sequences were supplied the Diagnostic Mode was not specified.
USER RESPONSE:
Use the conditions described in the preceding explanation to correct the diagnostic
sequence.
WARNING (TTM-295): Latch/Flop blockname is corrupted by simulation of the

Diagnostic_Observe sequence.
EXPLANATION:
The latch/flop identified in this message is found to be corrupted while switching to the
diagnostic mode when the diagnostic observe sequence is applied in order to switch to
the diagnostic test mode for scanning out values for diagnostic observation. This
condition causes observation of this latch/flop in the diagnostic mode to become
unreliable.
USER RESPONSE:
Encounter Test does not currently account for such corruption so as to ignore the values
held in such latches/flops. It is an important DFT guideline that all latches/flops
considered observable in the target test mode not be corrupted when switching to the
diagnostic mode.

Although Encounter Test allows proceeding beyond this point, the problem should be
corrected or diagnostic measures must mask for all such corrupted latches/flops and
diagnostic resolution will suffer.
Note: Encounter Test does not automatically perform masking for these corrupted
latches/flops during diagnostics.
ERROR (TTM-296): Invalid test functions have been defined on PIs/PPIs for an 1149.1 test
mode. 1149.1 test modes are not allowed to use compression or related test functions.
EXPLANATION:
Since Encounter Test currently limits use of compression to test modes that do not use
1149.1 tap controller for scanning, 1149.1 test mode are not allowed to define test
function pins associated with compression use. This means test functions SIG, SOG, MO,
MRD, MRST, MRE, CME, CMLE are not legal for use in test modes with scan type = 1149.1.
USER RESPONSE:
If on-product compression is required, change the test mode so that it does not require
use of the 1149.1 TAP controller to do scan. Note that it is acceptable to use an 1149.1
TAP controller to initialize the design to enter into a compression test mode if you define
a custom mode initialization sequence. Rebuild the test mode after making these
changes.
ERROR (TTM-297): The target mode modename references a parent mode modename
which is an assumed scan chain test mode.
EXPLANATION:
An assumed scan chain testmode cannot be used as a parent testmode.
USER RESPONSE:
Redefine the target testmode such that the user of the parent is not required or redefine
the parent testmode so it does not use assumed scan.
WARNING (TTM-298): [Severe] PO pinname from Measure_MISR_Data event of the

MISR_Observe sequence seqname is not fed by a MISR RCL.
EXPLANATION:
The MISR signatures are expected to be verified by observing them via the
MISR_Observe (MO) pins during the misrobserve sequence referenced by the
message. The referenced MO pin being observed does not appear to be fed from a set of
MISR bits through a linear space compactor function. This is not expected and typically
indicates the MISR observation design state is not correctly established.

USER RESPONSE:
If all MISR bits are validly observed at other pins, then it may be that the reference pin is
not truly a MISR_Observe pin and it should have its test function definition changed to
reflect this. If the referenced sequence is a custom-defined sequence, then it should
remove reference to pin pinname. If not all MISR bits are being observed, then most
likely the MISR Observation design state is not being established correctly to ensure the
state of all MISR bits can be seen through linear (XOR) space compactors to a set of
MISR_Observe (MO) pins.
Ensure that any primary inputs required to be at a specific value when observing the
MISRs are defined as +MRD (for pins that need to be 1) or -MRD (for pins needing to be
0) and then rerun.
WARNING (TTM-300): [Severe] The sequence name pulses PI/PPI during the
sequence type. The pulse occurred in a second pulse event. Encounter Test does not
support multiple pulse events for user specified skewed load or skewed unload sequences.
EXPLANATION:
Encounter Test allows only one pulse event for clock primary inputs or pseudo-primary
inputs for the skewed load and skewed unload sequences when they are provided by the
user. If multiple pulse events occur the test data may not correctly predict the responses
and may result in zero yield.
USER RESPONSE:
Correct the skewed load or unload sequence so that it contains only one pulse event for
the clock primary inputs and one pulse event for the clock pseudo-primary inputs.

WARNING (TTM-301): [Severe] The sequence name pulses PI/PPI during the
sequence type. PI/PPI is not a(n) clock type. Encounter Test does not support
pulsing of clock types during user specified sequence type sequences.
EXPLANATION:
Encounter Test requires the pulsing of A clocks during user specified skewed load
sequence and the pulsing of B clocks during user specified skewed unload sequence. If
the inappropriate clock type is pulsed the test data may not correctly predict the
responses and may result in zero yield.
USER RESPONSE:

the appropriate clock primary inputs and one pulse event for the appropriate clock
pseudo-primary inputs.
WARNING (TTM-302): [Severe] The sequence name contained too many events or an
illegal event for a sequence type. Encounter Test allows only one pulse event for clock
primary inputs, one pulse event for pseudo-primary inputs, and one set scan data event for
user specified skewed load or skewed unload sequences.
EXPLANATION:
Encounter Test allows only one pulse event for clock primary inputs, one pulse event for
pseudo-primary inputs, and one set scan data event for the skewed load and skewed
unload sequences when they are provided by the user. If multiple pulse events occur the
test data may not correctly predict the responses and may result in zero yield.
USER RESPONSE:
the clock primary inputs and one pulse event for the clock pseudo-primary inputs.
WARNING (TTM-303): [Severe] The sequence name does not pulse PI/PPI during
the sequence type. PI/PPI is a(n) clock type. Encounter Test requires the pulsing of all
clock types during user specified sequence type sequences.
EXPLANATION:
Encounter Test requires the pulsing of all A clocks during user specified skewed load
sequence and the pulsing of all B clocks during user specified skewed unload sequence.
If the all the appropriate clocks are not pulsed the test data may not correctly predict the
responses and may result in zero yield.
USER RESPONSE:
the appropriate clock primary inputs and one pulse event for the appropriate clock
pseudo-primary inputs.
INFO (TTM-304): number FSM candidate latches have been found. The threshold for
reasonable performance is number.
EXPLANATION:
Encounter Test automatically determines the 1149.1 finite state machine latches when
they are not identified by user attribute. The candidate latches are found via tracing.
Through simulation the FSM latches are found from the list of candidates. Reasonable
performance for FSM latch identification can be maintained when the number candidate

latches is low (less than the specified threshold). If the threshold of candidate FSM
latches is exceeded performance may suffer.
USER RESPONSE:
If the threshold of candidate FSM latches is exceeded, accept the additional run time or
add the FSM attribute to the finite state machine latches.
WARNING (TTM-305): [Severe] Primary input pinname identified as an OSC pin is not in
the On-Product Clock logic.
EXPLANATION:
Encounter Test requires that all primary inputs identified by an OSC attribute must be
part of the On-Product Clock logic.
USER RESPONSE:
Either remove the OSC attribute from the specified primary input or modify the design
such that this pin is part of the On-Product Clock logic.
WARNING (TTM-306): A sequence_type sequence exists, but it is not possible for

Encounter Test to use it. It will be ignored.
EXPLANATION:
Encounter Test requires that the application of the skewed load/unload sequence result
in a one-half bit shift of the scan chains. Test Mode Define has determined that this does
not hold for this design. The most likely reason for this is that a clock pulsed in the
sequence causes one or more scan bits to shift an entire bit position.
USER RESPONSE:
Correct the skewed load/unload sequence or the design such that the application of the
sequence results in a one-half bit shift of the scan chains. One possible cause for this
condition is that an edge-triggered scan clock (ES or EC) was accidentally defined as an
LSSD scan A clock (AS or AC) or scan B clock (BS or BC). If this is the case, correct the
clock type specification and rebuild the test mode. Alternatively, run Test Structure
Verification and correct any clocking problems or broken scan chains, and then rerun
build_testmode.
WARNING (TTM-307): [Severe] PO pinname from Measure_MISR_Data event of the

MISR_Observe sequence, seqname, is not fed by a valid XOR/XORN network.
EXPLANATION:
The MISR signatures are expected to be verified by observing them via the
MISR_Observe (MO) pins during the referenced misrobserve sequence. The referenced

MO pin being observed does not appear to be fed from a set of MISR bits through a linear
space compactor function. This is not expected and typically indicates the MISR
observation circuit state is not correctly established.
USER RESPONSE:
If all MISR bits are validly observed at other pins, then it may be that the
referenced pin name is not truly a MISR_Observe pin. Change the test function
definition accordingly.
If the referenced sequence is a custom-defined sequence, remove referenced
pin name.
If not all MISR bits are being observed, then most likely the MISR Observation
circuit state is not correctly established to ensure the state of all MISR bits can
be seen through linear (XOR) space compactors to a set of MISR Observe
(MO) pins.
Ensure that any primary inputs that need to be at a specific value when
observing the MISRs are defined as +MRD (for pins need to be 1) or -MRD (for
pins needing to be 0).
Rerun after evaluating and correcting any of the preceding conditions.
WARNING (TTM-308): A sequence_type sequence exists, but it is not possible for

Encounter Test to use it. It will be ignored.
EXPLANATION:
Encounter Test requires that the application of the skewed unload sequence result in a
one-half bit shift of the scan chains. Test Mode Define has determined that this does not
hold for this design. The most likely reason for this is that a clock pulsed in the sequence
causes one or more scan bits to shift an entire bit position.
USER RESPONSE:
Correct the skewed unload sequence or the design such that the application of the
LSSD scan A clock (AS or AC) or scan B clock (BS or BC). If this is the case, correct the
clock type specification and re-build the test mode. Alternatively, run Test Structure
Verification and correct any clocking problems or broken scan chains, and rerun
build_testmode.
INFO (TTM-314): count out of total pins active for percent active%, percent
inactive% inactive. Constraints comprise percent constraints% of the pins.
EXPLANATION:

This message identifies the number of active pins in the Logic Model. A pin is active if
caused by constraints or by real logic that, for some reason, cant be observed.
USER RESPONSE:
INFO (TTM-315): count out of total nets active for percent active%, percent
constraints% inactive. Constraints comprise percent inactive% of the nets.
EXPLANATION:
This message identifies the number of active nets in the Logic Model. A net is active if
caused by constraints or by real logic that, for some reason, cant be observed.
USER RESPONSE:
ERROR (TTM-316): Channel masking was detected and the primary input flags indicate that
multiple scan sections are required.
EXPLANATION:
Encounter Test currently does not support the use of multiple scan sections in a test
mode which uses channel masking.
Intent:
This is a basic limitation that is being enforced.
USER RESPONSE:
Perform all scan operations within a single scan section in order to use channel masking.
WARNING (TTM-320): Error in Backtracing for boundary Scan External: block blockid
RAM or ROM found!
EXPLANATION:
A RAM or ROM was found in tracing back from a primary output to find its associated
boundary scan latch. This deviates from boundary scan design guidelines and will
degrade testability for this test mode as well as interconnect test generation on the higher
level package.

USER RESPONSE:
Ensure the external boundary scan chain test configuration controls are specified, using
TI test function pin attributes, to direct the primary output backtrace to its associated
boundary scan latch rather than into the system logic.
WARNING (TTM-322): Latch blockid2, which is non-scanable in the boundary scan

external test mode, gates the system clock path to boundary scan receiver latch blockid1.
This condition will cause faults into this receiver latch to be untestable in this test mode.
EXPLANATION:
clock input to include all the logic necessary to ensure controllability from the primary
USER RESPONSE:
WARNING (TTM-323): Non-boundary scan latch blockid was found in backtracing from
Primary Output pinid. blockid is not included in the boundary model.
EXPLANATION:
USER RESPONSE:
scan latch.
WARNING (TTM-324): No boundary scan latches were found forward tracing from PI
pinid.
EXPLANATION:

external test mode. No scannable latch was found in tracing forward from this primary
input. This will degrade testability for this test mode as well as interconnect test
USER RESPONSE:
attribute) are specified to direct the primary input forward trace to its associated
WARNING (TTM-325): No boundary scan latches or PIs were found back tracing from PO
PO name.
EXPLANATION:
external test mode. No scannable latch was found in tracing backward from this primary
output. This will degrade testability for this test mode as well as interconnect test
USER RESPONSE:
attribute) are specified to direct the primary output backward trace to its associated
WARNING (TTM-326): Primary Input Pin pinid is unused.

EXPLANATION:
No net is connected to this primary input pin.
USER RESPONSE:
Verify that the logic is correct.
WARNING (TTM-330): Forward trace on PI pinid included n boundary scan latches. This
PI was not picked up in the backtrace on the latches.
EXPLANATION:
The number of boundary scan external scannable latches that were found in tracing
forward from this PI is displayed. In backtracing from these latches, with TI values
enforced, this same PI was not found.
USER RESPONSE:

Make certain that there is no primary input with the TI attribute that is blocking the path
from this primary input to its associated boundary scan latch.
WARNING (TTM-331): PO, po name, backtraced into Latch Block blockid. This latch
was used as a boundary scan latch for PO po name.
EXPLANATION:
The indicated latch is used as a boundary scan latch to the data input of a three-state
driver that feeds more than one primary output. It will not be possible to independently
control these primary output nets, thus limiting the ability to perform a complete
interconnect test on the next higher level package.
USER RESPONSE:
Make certain that this multiple usage of the same boundary scan data latch is as
INFO (TTM-332): PO, po name, backtraced into Latch Block blockid. This latch was
used as a boundary scan latch for PO po name.
EXPLANATION:
The indicated latch is used as a boundary scan latch to the enable input of a three-state
driver that feeds more than one primary output.
USER RESPONSE:
Make certain that this multiple usage of the same boundary scan enable latch is as
WARNING (TTM-333): RAM/ROM block blockid2 gates the system clock path to
boundary scan receiver latch blockid1. This condition will cause faults into this receiver
latch to be untestable in this test mode.
EXPLANATION:
The identified receiver latch was associated with a primary input, but backtracing from it
to include all the logic necessary to ensure controllability from the primary input to this
latch found a RAM or ROM block. This block will be replaced by a source of x for test
generation and fault simulation, and will degrade testability for this test mode as well as
the ability to do a complete interconnect test on the higher level package.
USER RESPONSE:

latch are not gated by any RAM or ROM.
WARNING (TTM-334): RAM or ROM block blockid1 was found in backtracing from
Primary Output blockid2. blockid1 is not included in the boundary model.
EXPLANATION:
boundary scan external mode. The identified RAM/ROM block will be replaced by a
source of x for test generation and fault simulation, and will degrade testability for this test
mode as well as the ability to do a complete interconnect test on the higher level
package.
USER RESPONSE:
scan latch.
WARNING (TTM-335): Latch blockid1, which is non-scannable in the boundary scan

external test mode, gates the data path to boundary scan receiver latch blockid2. This
EXPLANATION:
USER RESPONSE:
associated boundary scan latch. Further, ensure that data paths to this boundary scan
WARNING (TTM-336): RAM/ROM block blockid1 gates the data path to boundary scan
receiver latch blockid2. This condition will cause faults into this receiver latch to be
untestable in this test mode.
EXPLANATION:

input to this latch found a RAM or ROM block. This block will be replaced by a source of
x for test generation and fault simulation, and will degrade testability for this test mode as
well as the ability to perform a complete interconnect test on the higher level package.
USER RESPONSE:
boundary scan latch. Further, ensure that data paths to this boundary scan latch are not
gated by any RAM or ROM.
WARNING (TTM-337): PO pinid data path has n boundary scan latches and m non-
EXPLANATION:
The backtrace along the data path of the TSD associated with this primary output
USER RESPONSE:
boundary scan latch is associated with this primary outputs data back-trace.
WARNING (TTM-338): PO pinid enable path has n boundary scan latches and m non-
EXPLANATION:
The backtrace along the enable path of the TSD associated with this primary output
USER RESPONSE:

Modify the boundary scan design so that only one boundary scan latch and no non-
boundary scan latch is associated with this primary outputs enable back-trace.
WARNING (TTM-340): At event event of the scan operation, CME pipeline element
block name is corrupted. This condition may prevents the creation of a single Load
Channel Mask event for use by multiple test sequences.
EXPLANATION:
The application of the identified event of the scan opeation, corrupts the CME pipeline
element. This message states that at the identified event, the value which was loaded
into the latch or flop of the CME pipeline may be overwritten. Since the value loaded into
the CME pipeline may be compromised the mask enable valued load in one test
sequence cannot be used by any subsequent test sequence. This requires that each test
sequence requiring masking contains its own Load Channel Mask event.
USER RESPONSE:
Change the logic or sequences to prevent the corruption of the CME pipeline or accept
the possible reloading of identical mask data.
WARNING (TTM-341): At event event of the scan operation, channel mask shift register
element block name is corrupted. This condition may prevents the creation of a single
Load Channel Mask event for use by multiple test sequences.$ event
EXPLANATION:
The application of the identified event of the scan operation, corrupts the channel mask
shift register element. This message states that at the identified event, the value which
was loaded into the latch or flop of the Channel Mask Shift Register may be overwritten.
Since the value loaded by the Channel Mask Load sequence may be compromised the
mask values loaded in one test sequence cannot be used by any subsequent test
sequence. This requires that each test sequence requiring masking contains its own
Load Channel Mask event.
USER RESPONSE:
Change the logic or sequences to prevent the corruption of the Channel Mask Shift
Register or accept the possible reloading of identical mask data.
ERROR (TTM-342): Failure to specify exactly one instruction when no user-defined custom
scan sequence is supplied and the UPDATE_DR=yes option is specified.
EXPLANATION:
When a test mode uses scan type of 1149.1 and specifies UPDATE_DR=yes, either a full
custom scan sequence must be defined that correctly traverses the 1149.1 TAP

controller state machine and which includes use of a loadsuffix sequence, or a single
INSTRUCTION should be specified on the SCAN TYPE statement of the mode definition
or assign file so that the scan sequence can be automatically generated.
USER RESPONSE:
When defining a test mode that uses the 1149.1 TAP controller and which actually
updates the scan chain update stages during the UPDATE_DR state, ensure that you use
only a single scan section by specifying a single INSTRUCTION to be loaded into the TAP
controller.
Alternatively, it is possible to manually define the very complex sequence of events
needed to traverse the TAP states to move from scan through UPDATE_DR, with the
UPDATE_DR state needing to be applied using a loadsuffix scan sequence type.
Note: We do not recommend using UPDATE_DR for scan loading except for the
boundary scan chain.If you choose to utilize UPDATE_DR, we highly recommend letting
the tool automatically generate the complex scan sequences.
WARNING (TTM-344): [Severe] At event event of the scanop sequence, channel mask
shift register element block_name is corrupted. This condition may prevent the masking of
the observable register masked by this channel mask shift register element.
EXPLANATION:
The application of the identified event of the scan sequence, corrupts the channel mask
shift register element. This message states that at the identified event, the value which
was loaded into the latch or flop of the Channel Mask Shift Register may be overwritten.
Since the value loaded by the Channel Mask Load sequence may be compromised
masking may not work properly.
USER RESPONSE:
Change the logic or sequences to eliminate the corrupt of the channel mask shift
registers.
WARNING (TTM-345): There is more than 20 percent active logic in this boundary scan
external test mode. There may be more scan chains defined than are required to scan all
boundary scan chains.
EXPLANATION:
In a boundary scan external test mode, only a small percentage of the logic (less than
20%) should be active. This test mode contains more than 20% active logic. This is most
likely due to the fact that there are scan chains defined in this mode other than those
required to scan the boundary scan chain(s). When creating boundary (skin) models, it
is important to try to keep the percentage of active logic to a minimum.

USER RESPONSE:
Analyze the scan chains defined for this mode using View Circuit Statistics. If the scan
chains defined for this mode include only the boundary scan chains, contact customer
support (see Contacting Customer Service on page 23) to see if perhaps there is a
program error. If the active logic is determined to be correct, this message may be
ignored. Otherwise, remove the unnecessary Scanin and Scanout test functions from the
mode and rerun Build Test Mode.
INFO (TTM-346): There is more than 20 percent active logic in this boundary scan external
test mode.
EXPLANATION:
In a boundary scan external test mode, only a small percentage of the logic (less than
20%) should be active. This test mode contains more than 20% active logic. This is most
likely due to the fact that there are scan chains defined in this mode other than those
required to scan the boundary scan chain(s). While having too much active logic in a
boundary external mode is inefficient, this is not considered a problem unless you intend
to create a boundary (skin) model for MCM interconnect testing.
USER RESPONSE:
WARNING (TTM-347): There is less than 96 percent active logic in this test mode. Global
fault coverage is impacted when too little of the logic is visible.
EXPLANATION:
In a boundary scan internal or boundary=no test mode, only a small percentage of the
logic (less than 4%) should be inactive. This test mode contains more than 4% inactive
logic. This is most likely caused by either the use of Test Inhibit (TI) test function pins that
block some logic from being observed, or from the use of blackboxes, which leaves the
logic feeding them unobservable. Fault coverage may suffer if too much logic cannot be
observed.
USER RESPONSE:
If you intended to have more than 4% inactive logic, then there is no user action required.
Otherwise, find the inactive logic (you can list inactive latches as a starting point and
trace backward from there, or you can list inactive faults) and try to understand why it is
inactive by tracing forward to find possible observe paths. Note that inactive logic is
displayed in dark grey to make it easier to tell the inactive logic from the active logic.

WARNING (TTM-348): [Severe] This test mode will not function correctly as an 1149.1
design since the mode initialization sequence does not reset the finite state machine latches
to the Test-Logic-Reset state.
EXPLANATION:
The test mode being processed has TCK, TMS, TDI and TDO pins, thus identifying it as
1149.1. It must therefore contain a TAP controller having at least four finite state machine
(FSM) latches. build_testmode identified the finite state machine latches but the
mode initialization sequence does not reset them to the Test-Logic-Reset state. Any
attempt to proceed with further Encounter Test processing steps is likely to encounter
serious difficulties due to the fact that the TAP controller, fundamental to all 1149.1
operations, is not properly initialized.
USER RESPONSE:
There are two possible causes for this problem.
The TAP controller logic is not correctly implemented. Make the necessary
corrections and rerun build_testmode.
The mode initialization sequence is incorrect. Make the necessary corrections and
rerun build_testmode.
WARNING (TTM-349): [Severe] The mode initialization sequence contains loop events
which are not allowed for 1149.1 test modes.
EXPLANATION:
(FSM) latches. build_testmode identified the finite state machine latches but the
mode initialization sequence contains loop events. Encounter Test requires all loops be
removed from the mode initialization sequence when to allow build_testmode to
properly locate a force event within that sequence.
USER RESPONSE:
Remove all loops from the mode initialization sequence and rerun build_testmode.
INFO (TTM-350): There are pscCount Permanently Scan Corrupted Latches.

EXPLANATION:
Permanently Scan Corrupted Latches are non-scan latches which are set to a
permanent, known, fixed value following the completion of the scan operation. Prior to
the first scan operation these latches are at an unknown value but once a scan operation

is completed, they become functionally equivalent to fixed value latches set at a known
(i.e. 0 or 1) value that will never change.
USER RESPONSE:
If it is known that a scan operation will be done at the beginning of a test, it is possible to
have the build_testmode process identify them as fixed value latches which improves
the results of many Encounter Test applications. To have build_testmode identify
permanently scan corrupted latches as fixed value latches, add this option to the
build_testmode command line:
assumeTestStartsWithScan=yes (the default is no)
If this option is used, message, TTM-351 is printed indicating that all permanently scan
corrupted latches have been converted to Fixed Value Latches.

INFO (TTM-351): There are pscCount Permanently Scan Corrupted Latches that have
been converted to Fixed Value Latches.
EXPLANATION:
Permanently Scan Corrupted Latches are non-scan latches which are set to a
permanent, known, fixed value following the completion of the scan operation. Prior to
the first scan operation these latches are at an unknown value but once a scan operation
is completed, they become functionally equivalent to fixed value latches set at a known
(i.e. 0 or 1) value that will never change.
This message indicates that assumeTestStartsWithScan=yes has been specified
on the build testmode command line which causes all permanently scan corrupted
latches to be converted to fixed value latches.
USER RESPONSE:
This conversion is valid only if tests are known to begin with a scan operation. If this
conversion is not desired, then either omit the assumeTestStartsWithScan option or
specify assumeTestStartsWithScan=no.
WARNING (TTM-352): [Severe] PRPG Spreader Pipeline Depth mismatch found! Longest
Depth = number and the Shortest Depth = number.
EXPLANATION:
The PRPG Spreader network pipeline must provide a uniform pipeline depth so that all
PRPG data arrives at all Scan Chains (i.e. Channels) simultaneously. This design has
unequal pipeline depths therefore no random patterns will be generated.

If the Shortest Depth is zero, this indicates that none of the Channels received known
data values from the PRPG Spreader Pipeline flops even when the maximum allowed
depth was tried. In this case, the Longest Depth indicated the longest PRPG Spreader
Pipeline depth allowed by the product.
USER RESPONSE:
Correct the design so the PRPG Spreader Network pipelines have the same depth.
WARNING (TTM-353): [Severe] PRPG Spreader Pipeline Flop/Latch

memoryElementName changed value outside of the Scan State.
EXPLANATION:
The PRPG Spreader network pipeline flops/latches must retain their state outside of the
scan state to prevent the downstream Scan Chains (i.e. Channels) from being loaded
with corrupted data. Random patterns are not generated due to this error.
USER RESPONSE:
Correct the design so that the pipeline flops/latches cannot change value outside of the
scan state.

memoryElementName is a stableFlushType and is incompatible with the PRPG that
feeds it.
EXPLANATION:
The PRPG bit that drives this PRPG Spreader network pipeline flop/latch has an
opposite stable/flush relationship. For example, this error is generated if the driving
PRPG bit was a flush master/stable slave latch pair and the referenced pipeline flop/latch
is stable master/flush slave latch pair. The other possible case is that the PRPG is a
stable master/flush slave and the pipeline is a flush master/stable slave flop latch pair.
Random patterns are not generated due to this error.
USER RESPONSE:
Correct the design so that the PRPG and pipeline flops/latches have a compatible stable/
flush relationship.
WARNING (TTM-355): [Severe] PRPG Spreader Pipeline Flops/Latches are fed by

multiple clocks. Flop/Latch memoryElement1 is fed by Clock PI clockPi1 and Flop/Latch
memoryElement2 is fed by clock PI clockPi2.
EXPLANATION:

The PRPG Spreader network pipeline flops/latches must be controlled by a single scan
clock primary input. Since the pipeline flops/latches require multiple clocks to control
them, no random patterns will be generated.
USER RESPONSE:
Correct the design so that the pipeline flops/latches are controlled by a single scan clock.

memoryElementName is not controlled by any scan clock PIs.
EXPLANATION:
The PRPG Spreader network pipeline flops/latches must be controlled by a single scan
clock primary input. No scan clocks were found that control this pipeline flop/latch.
Random patterns are not generated due to this error.
USER RESPONSE:
Correct the design so that the pipeline flops/latches are controlled by a single scan clock.
INFO (TTM-357): There are number scan chains which are controllable and observable.
EXPLANATION:
The message states the number of controllable and observable scan chains.
USER RESPONSE:
WARNING (TTM-358): There are number scan chains which are only controllable.
EXPLANATION:
The message states the number of controllable scan chains.
USER RESPONSE:
Encounter Test supports the use of scan chains which are only controllable. If you
intended for all the scan chains to be both controllable and observable, run
verify_test_structures and address the TSV messages related to the scan
chains.
WARNING (TTM-359): There are number scan chains which are only observable.
EXPLANATION:
The message states the number of observable scan chains.

USER RESPONSE:
Encounter Test supports the use of scan chains which are only observable. If you
intended for all the scan chains to be both controllable and observable, run
verify_test_structures and address the TSV messages related to the scan
chains.
WARNING (TTM-360): A sequence_type sequence exists, but it will be ignored.

reason
Explanantion:
Encounter Test detected that the skewed load/unload sequence cannot be applied
USER RESPONSE:
LSSD scan A clock (AS orAC) or scan B clock (BS or BC). If this is the case, correct the
build_testmode.
WARNING (TTM-361): A sequence type sequence exists, but it will be ignored.

reason.
EXPLANATION:
Encounter Test detected that the skewed load/unload sequence cannot be applied.
USER RESPONSE:
LSSD scan A clock (AS orAC) or scan B clock (BS or BC). If this is the case, correct the
build_testmode.
WARNING (TTM-362): At event event of the scanop sequence, observable scan element
block_name is corrupted. Since the value captured by this scan element may have been
overwritten, the latch is removed from the scan chain as a valid measure point. This condition
may increase the difficulty of testing some faults.
EXPLANATION:

The application of the identified event, which occurs prior to the scan sequence, corrupts
an observable element of the scan chain before it has had a chance to be shifted out.
This message states that at the identified event the value which was captured in the latch
or flop may be overwritten. Since the captured value may be compromised the identified
latch or flop is removed from the Encounter Test observable scan chain. Since this
reduces the number of available capture elements reduced fault coverage, increased
pattern count, and increased test time may result.
USER RESPONSE:
In most cases, eliminating the scan corruption will require a change in the logic, the test
function pin definitions, or the scanop sequence to allow the normal scan latches to
remain stable until the scan sequence is reached.
WARNING (TTM-363): At event event of the scanop sequence, controllable scan element
block_name is corrupted. Since the value loaded into this scan element by the scan
sequence may have been overwritten, the scan element is removed as a valid, correlated
controllable element. This condition may increase the difficulty of testing some faults.
EXPLANATION:
The application of the identified event, which occurs following the scan sequence,
corrupts a scan loaded latch or flop. This message states that at the identified event the
value which was loaded into the scan element by the scan sequence may be overwritten.
Since the scan loaded value may be compromised, the identified scan element is
removed from the Encounter Test controllable scan chain as a correlated latch/flop.
Since this reduces the number of scan elements that will be available to ATPG as known
stimulus points at the end of scan, reduced fault coverage, increased pattern count, and
increased test time may result.
USER RESPONSE:
WARNING (TTM-364): At event event of the scanop sequence, controllable scan element
block_name is being removed from the controllable scan chain as the representative
controllable element is corrupted. This condition may increase the difficulty of testing some
faults.
EXPLANATION:
corrupts the scan element representing a bit position in the controllable scan chain. This
message states that at the identified event, the value which was loaded into the latch or
flop chosen as the representative for that bit position may be overwritten. Since the scan

loaded value of the representative scan element may be compromised, any latch or flop
whose value is correlated to that representative scan element at the end of scan must be
removed from the Encounter Test controllable scan chain. The removal of the
representative scan element will be identified by a separate message (TTM-365). Since
this reduces the number of scan elements which will be available to ATPG known
stimulus points at the end of scan, reduced fault coverage, increased pattern count, and
increased test time may result.
USER RESPONSE:
WARNING (TTM-365): At event event of the scanop sequence, the controllable scan
element block_name is corrupted. Since the value loaded into this scan element by the
scan sequence may have been overwritten, the scan element is removed as a valid
controllable element. This element was the representative for a bit of the controllable scan
chain therefore all latches and flops correlated to this representative element will also be
removed. This condition may increase the difficulty of testing some faults.
EXPLANATION:
corrupts the representative controllable element. This message states that at the
identified event the value which was loaded into the element chosen as the
representative element may be overwritten. Since the scan loaded value of the
representative element may be compromised, any latch or flop whose value is correlated
to the representative element at the end of scan must be removed from the Encounter
Test controllable scan chain. The removal of the correlated elements will be identified by
a separate message (TTM-364). Since this reduces the number of scan elements which
will be available to ATPG known stimulus points at the end of scan, reduced fault
coverage, increased pattern count, and increased test time may result.
USER RESPONSE:
WARNING (TTM-366): Inconsistent scan corruption found. Application of the optional

sequence_name sequence causes the scan-corrupted value of PI/PPI/Latch_name
to change from val1 to val2.The sequence_name sequence is considered invalid and
will not be used.

EXPLANATION:
The optional scan sequence, sequence_name, appears to cause a different scan
corruption for PI/PPI/Latch_name depending on whether it is applied (val1) or
skipped (val2). Since Encounter Test does not support changes in scan corruption that
are dependent on whether optional scan sequences are applied, this sequence is
considered invalid and will not be used.
USER RESPONSE:
Change the sequence definition so that it does not cause a different scan corruption to
occur, possibly by making the sequence block the clocking of any affected latches or
flops. If the scan corrupt difference appears at a PI or PPI, most likely before the
sequence exists, it should be resetting the value for this PI or PPI back to the value it had
prior to the sequence.
WARNING (TTM-367): [Severe] An oscillator was suddenly started or stopped during the
scan operation without the use of a Start_Osc or Stop_Osc event.
EXPLANATION:
When an oscillator is started (by means of the Start_Osc event), all patterns up to the
Stop_Osc event must be synchronized with the oscillator by means of Wait_Osc events
in each pattern. There are exceptions to this rule: patterns containing Scan_Load,
Scan_Unload, Channel_Scan, or Apply events should not contain Wait_Osc
events. In brief, any pattern containing a "macro" event which is not executed directly by
the tester should not contain Wait_Osc events. The appearance of this message is
indicative of a pattern which should contain a Wait_Osc event but does not or a pattern
that should not contain a Wait_Osc event but does.
USER RESPONSE:
Examine preceding TBD messages that should have been issued by the checking
program to identify the problem.
WARNING (TTM-368): [Severe] The scan operation ends with a different set of oscillators
running from the set of oscillators presumed running at the start of the scan operation.
EXPLANATION:
The same set of oscillators should be running at the beginning and end of the scan
operation. If the scan operation starts an oscillator, it should stop that oscillator before
the end of the scan operation, and similarly if it turns off (stops) an oscillator, it should
restart that oscillator before the end of the scan operation. This message indicates that
within the set of sequences that define the scan operation, there is a mismatch between
Start_Osc and Stop_Osc events.

USER RESPONSE:
You must have been using custom scan sequence if the scan operation is using oscillator
events. Examine your scan sequence definitions and make sure that for each Start_Osc
there is a corresponding Stop_Osc. After you have matched these events so that the
same set of oscillators is running at the beginning and end of the scan operation, rebuild
the test mode.
WARNING (TTM-369): [Severe] A pin, pinID, not identified as an Oscillator test function
(oTI or OSC) is used in an oscillator event in the modeinit sequence. Identify this pin as either
an oTI or OSC test function pin or the test data is likely to fail.
EXPLANATION:
Oscillator events are to be used only for test function pins defined to be oscillators. An
oTI identifies a pin that is expected to be oscillating once started in the modeinit
sequence and does not designate an OFF state. An OSC test function includes
specification of an OFF state for the oscillator (-OSC or +OSC to denote an OFF state of
0 or 1 respectively) and the oscillator must be started within the mode initialization
sequence.
USER RESPONSE:
Start an oscillator within the mode initialization sequence by specifing an oscillator test
function for the oscillator pin.
Define the pin as a -OSC or +OSC test function and rerun.
ERROR (TTM-370): User must specify exactly one instruction when no user-defined custom
scan sequence is supplied and the TAP_TG_STATE is SDR or CDR.
EXPLANATION:
When scan type=11491 and no user-defined scan protocol sequence is defined there
must be exactly one instruction specified when TAP_TG_STATE is Shift DR or Capture
DR.
USER RESPONSE:
Do one of the following:
Define a scan protocol sequence.
Specify exactly one instruction.
Change the TAP_TG_STATE.

WARNING (TTM-371): [Severe] Invalid user specified FORCE event. The correct FORCE
event specification follows:
EXPLANATION:
The user specified FORCE event of the modeinit does not coincide with the Encounter
Test calculated FORCE event that is required to insure correct simulation of 1149.1 TAP
controller.
USER RESPONSE:
Correct the FORCE event so that correct simulation of 1149.1 TAP controller is insured.
WARNING (TTM-372): [Severe] Event event of the Scanop sequence produced a

hard/soft contention on 3-state I/O net: netName.
The contention is partly due to 3-state Primary Input: pinName
being at logic value v.
EXPLANATION:
The specified event of the Scanop Sequence produced a contention condition on the
specified internal 3-state net.
USER RESPONSE:
Correct the event so that it does not cause a contention on the 3-state net, and rerun
Build Test Mode.
WARNING (TTM-373): Test Constraint Test Function PI, pinID, is not modified during the
Scanop sequence. It is acting as a Test Inhibit but is not treated as such.
EXPLANATION:
A Test Constraint pin is not modified during the Scanop sequence and functionally
behaves as a Test Inhibit pin.
USER RESPONSE:
Verify the referenced pins definition. No response is required if it is intended to be a Test
Contraint pin. Otherwise, consider changing the pin to a Test Inhibit pin to potentially
improve active logic identification and test coverage.
WARNING (TTM-374): [Severe] Scan last bit sequence, sequence name, does not scan
chain 1 bit.
EXPLANATION:
The scanlastbit sequence exists for those cases where the scansequence is suited for
scanning only the first N-1 bits of a scan chain, and a special sequence, scanlastbit, is

necessary to scan the Nth bit. This happens, for instance, with an 1149.1 scan protocol.
When the scanlastbit sequence is used it must scan just exactly one bit, no more, no less.
USER RESPONSE:
Modify the scan last bit sequence so the register is shifted exactly 1 bit.
WARNING (TTM-376): [Severe] Oscillator test function pin, pinID, is manipulated

following its Start_Osc in the modeinit sequence. Modify the modeinit sequence so that any
pulsing or other manipulation of the oscillator pin is done before the Start_Osc event.
EXPLANATION:
Once an oscillator pin has an oscillating signal applied, the pin should not be referenced
in another event until the oscillating input is stopped by use of a Stop_Osc event.
USER RESPONSE:
Explicit pulsing of an OSC pin must be done prior to the Start_Osc event. Correct this
error in the mode initialization sequence definition and rerun.
WARNING (TTM-377): The sequence name is unusable since its application causes the
scan-corrupted value of PI/PPI Latch name to change from val1 to val2. Encounter
Test does not support variation in scan corruption depending on whether a normal unload or
skewed unload is done.
EXPLANATION:
Application of the skewed_unload sequence followed by the scansequence causes a
difference in scan-corrupted values from those resulting from application of the scan
sequence alone. Encounter Test is capable of keeping track of only one set of scan-
corrupted values; therefore the skewunload sequence will not be used. This means that
there will never be any Skewed_Scan_Unload or Channel_Scan (skewed_unload)
events written to the output vectors file. One possible cause for this is a broken scan
chain which can be determined by TSV analysis.
USER RESPONSE:
Either correct the skewed_unload sequence so that it does not cause this discrepancy,
or else, if a changed latch is at fault, block the skewed_unload sequence from changing
the value of the indicated latch and then rerun.
WARNING (TTM-378): The sequence name is unusable since its application causes the
scan-corrupted value of PI/PPI Latch name to change from val1 to val2. Encounter
Test does not support variation in scan corruption depending on whether a normal load or
skewed load is done.
EXPLANATION:

Application of the scansequence followed by the skewload sequence causes a difference

in scan-corrupted values from those resulting from application of the scansequence
alone. Encounter Test is capable of keeping track of only one set of scan-corrupted
values; therefore the skewload sequence will not be used. This means that there will
never be any Skewed_Scan_Load or Channel_Scan (skewed_load) events written to
the output Vectors file. One possible cause for this is a broken scan chain which can be
determined by TSV analysis.
USER RESPONSE:
Either correct the skewload sequence so that it does not cause this discrepancy, or else,
if a changed latch is at fault, block the skewload sequence from changing the value of the
latch indicated.
WARNING (TTM-379): Application of the sequence name causes the scan-corrupted

value of PI/PPI/Latch name to change from val1 to val2.
EXPLANATION:
Application of the scanop followed by the loadsuffix sequence causes a difference in
scan-corrupted values from those resulting from application of the scanop alone. This
may destroy some test stimulus values derived by the test generator and could result in
sim rejects and loss of test coverage.
USER RESPONSE:
Either correct the loadsuffix sequence so that it does not cause this discrepancy, or else,
if a changed latch is at fault, block the loadsuffix sequence from changing the value of
the latch indicated.
ERROR (TTM-380): Pin pinid is stimmed or observed during the Scanop, but it has no
test function pin attribute.
EXPLANATION:
Any pin stimmed or observed by a CSP must have some test function pin attribute, in
order to indicate tester contact.
USER RESPONSE:
Correct the error by affixing a test function pin attribute to the specified pin.
WARNING (TTM-381): [Severe] Test Function PI, pinid, in mode modename, is not at
its defined stability value (value) for this mode after simulation of sequenceid sequence
event eventid, pattern patternid. Test Data produced may be invalid.
EXPLANATION:

The scan operation caused the specified pin to change from its defined stability value.
This can cause illegal design states to be entered that are not subject to analysis by Test
Structure Verification. The exposure exists that any test data produced using this scan
protocol could fail to verify at the tester.
USER RESPONSE:
Modify the identified sequence so the identified test function PI is at its stability value
after simulation of the sequence.
ERROR (TTM-382): Invalid SCAN SECTION structure.

detailmsg
EXPLANATION:
One of the following conditions have been found.
The scan section limit of 16 has been exceeded.
An event type other than "apply" was found.
More than one "scanprecond," "skewunload," "scansequence," "scanlastbit,"
"skewload," or "scansectionexit" sequence was found.
A "scanprecond" sequence was not the first sequence in the scan section.
A "skewunload" sequence was found before a "scanprecond" sequence or after
a "scansequence" sequence.
A "scansequence" sequence does not exist.
A "scanlastbit" sequence was found before a "scansequence" sequence.
A "skewload" sequence was found before a "scansequence" or "scanlastbit"
sequence, if it exists.
A "scansectionexit" sequence was not the last sequence in the scan section.
USER RESPONSE:
Correct the ordering of the scan section sequences. Refer to "Scan Operation" in the
Encounter Test: Reference: Test Pattern Formats and "Custom Scan Sequences"
in the Encounter Test: Guide 2: Testmodes for scan operation details.
ERROR (TTM-383): Invalid SCANOP structure.

EXPLANATION:
One of the following conditions has been found during the processing of a user defined
scan sequence scan operation (scanop).

More than one "scanentry" or "scanexit" sequence was found

A "scanentry" sequence was not the first sequence in the scan operation
A "scanexit" sequence was not the last sequence in the scan operation
USER RESPONSE:
Correct the ordering of the scan operation sequences. Refer to "Scan Operation" in the
Encounter Test: Reference: Test Pattern Formats and "Custom Scan Sequences"
in the Encounter Test: Guide 2: Testmodes for scan operation details.
ERROR (TTM-384): Unrecognized Event In Scanop.

EXPLANATION:
An invalid event was found during the processing of a user defined scan operation. Only
"apply" events which reference defined scan sequences are allowed.
USER RESPONSE:
Correct the scan operation sequence by removing the invalid events. Refer to "Scan
Operation" in the Encounter Test: Reference: Test Pattern Formats and "Custom
Scan Sequences" in the Encounter Test: Guide 2: Testmodes for scan operation
details.
WARNING (TTM-385): User FSM blockname not a real FSM.

EXPLANATION:
A finite state machine (FSM) latch is required to reach a definite logic 1 or logic 0 state
through application of the modeinit sequence. The identified FSM latch failed to do so.
This failure may cause serious difficulties with test generation, either in coverage or
performance.
USER RESPONSE:
Modify the logic or modeinit sequence so the identified latch reaches a definite logic 1 or
logic 0 after application of the modeinit sequence.
WARNING (TTM-386): This test mode will not function correctly as an 1149.1 part since
only number finite state machine latches could be identified in the TAP controller.
EXPLANATION:
(FSM) latches. Create a Test Mode failed in its attempt to identify these latches through
application of a synchronous reset to the Test-Logic-Reset state. Any attempt to proceed

with further Encounter Test processing steps is likely to encounter serious difficulties due
to the fact that the TAP controller, fundamental to all 1149.1 operations, could not be
adequately identified.
USER RESPONSE:
There are two possible causes for this problem.
The TAP controller logic is not correctly implemented. Make the necessary
corrections and rerun Create a Test Mode.
1149.1 compliance enable stimuli are needed to prime the design to respond
correctly to the synchronous TAP reset. Modify your BSDL to contain the
necessary compliance enable patterns and rerun Create a Test Mode.
INFO (TTM-387): A default scanop sequence will be generated.

EXPLANATION:
In the absence of a user-specified custom scan sequence (scanop) Encounter Test
automatically generates one on the basis of the test function pin attributes you have
assigned to your design. This automatically generated default scanop consists of exactly
one scan section, having a scanprecond sequence which sets all CI, SE and OI pins to
value and a scansequence which pulses clocks in A-E-B order.
USER RESPONSE:
No action is necessary if it is determined that this default scanop is adequate to scan all
the scannable memory elements of your design.
Otherwise, if it is not adequate for this purpose, then you must generate a scanop and
rerun Build Test Mode, specifying the Sequence Definition Path and File Name required
to access your custom scanop.
INFO (TTM-388): User defined custom scan sequence scanop sequence name is being
used.
EXPLANATION:
The custom scan sequence found in the file using the Sequence Definition Path and file
name is being used by Encounter Test to determine the scan state, and the scan chains.
USER RESPONSE:
WARNING (TTM-389): User defined custom scan sequence scanop sequence name is
ignored, only the first scanop will be used.

EXPLANATION:
More than one scan protocol sequence was found in the sequence file. Encounter Test
will use only the first scanop found.
USER RESPONSE:
INFO (TTM-390): User specified modeinit sequence sequence name from input
sequence is being used.
EXPLANATION:
The custom modeinit sequence found in file using the Sequence Definition Path and file
name is being used by Encounter Test to define the Test Constraint and clocks off state.
USER RESPONSE:
INFO (TTM-391): A default modeinit sequence will be generated.

EXPLANATION:
In the absence of a user-specified nodeinit sequence Encounter Test automatically
generates one on the basis of the test function pin attributes you have assigned to your
design. This automatically generated sequence consists of patterns which set up the
following:
Sets all three-state input pins to high-Z
Sets all non-three-state TI and TC test function pins to their stability values
Sets all three-state TI test function pins to their stability values.
Sets all clock test function pins to their stability values.
Sets TMS to 1 if an 1149 test mode.
USER RESPONSE:
No action is necessary if it is determined that this default modeinit is adequate to set the
design to the Test Constraint and clocks off state. Otherwise, if it is not adequate for this
purpose, then you must generate a modeinit, as described in Requirements of
Initialization Sequences in the Encounter Test: Guide 2: Testmodes and rerun
Create a Test Mode, specifying the Sequence Definition Path and File Name required to
access your custom modeinit.
WARNING (TTM-392): [Severe] Start_Osc event not allowed on a Pseudo PI name.

EXPLANATION:
Encounter Test can not handle a Start_Osc event on a Pseudo PI.
USER RESPONSE:
Remove the Start_Osc event on the Pseudo PI identified in the message.
WARNING (TTM-393): The automatically generated sequencetype sequence requires

stimming/pulsing pseudo PI ppiname. This may not work in the hardware.
EXPLANATION:
No user-defined sequencetype sequence was found, so this sequence is being
generated automatically. The ppiname pseudo primary input is being exercised, but
Encounter Test does not know how to manipulate pseudo primary inputs in the absence
of a user-specified sequence. Therefore, this sequence may work fine in all Encounter
Test applications, but fail in the hardware.
USER RESPONSE:
Create the sequence, specifying all required primary input stimuli as well as the pseudo
primary input stimuli. Then rebuild the test mode, specifying the name of the input file
that contains the sequence definition.
ERROR (TTM-394): User must specify one or more instructions when no user-defined
custom scan sequence and modeinit sequence is defined.
EXPLANATION:
When scan type=11491 and no user defined modeinit or scan protocol sequence is
defined there must be one or more instructions along with a valid TAP_TG_STATE
specified in order for Encounter Test to continue.
USER RESPONSE:
Do one of the following:
Define a modeinit or scan protocol sequence.
Specify one or more instructions along with a valid TAP_TG_STATE.
ERROR (TTM-395): User must specify a valid TAP_TG_STATE when no user-defined

custom scan sequence and modeinit sequence defined.
EXPLANATION:

It is required that Create a Test Mode know the TAP_TG_STATE in which stored pattern
test generation is to be done in order that it be able to automatically generate the
necessary modeinit and scanop sequences.
USER RESPONSE:
There are two options: Either,
Redefine your test mode to specify a TAP_TG_STATE in the SCAN TYPE
statement and rerun Create a Test Mode.
Define a custom modeinit and custom scan sequence and rerun Build Test
Mode, specifying the location of these two sequences via the Sequence
Definition Path and Sequence Definition File Name.
ERROR (TTM-396): User-defined custom scan sequence but no modeinit sequence

defined.
EXPLANATION:
User-defined custom scan sequence requires the presence of a modeinit sequence.
USER RESPONSE:
Remove the user-defined scan protocol sequence or define a modeinit sequence.
ERROR (TTM-397): User-defined modeinit sequence but no custom scan sequence

defined.
EXPLANATION:
For scan types of 11491, if a custom modeinit sequence is defined, there must also be a
user defined scan protocol sequence.
USER RESPONSE:
Remove the user-defined modeinit sequence or define a scan protocol sequence.
WARNING (TTM-398): User-defined custom scan sequence is ignored.

EXPLANATION:
The user-defined custom scan sequence is ignored for scan types of 11491 with a test
type = none, or static interconnect test.
USER RESPONSE:
Ignore the message, or remove the user-defined custom scan sequence from the input
sequence file.

WARNING (TTM-399): Pin pinId is set to high impedance (Z) during the Scanop, but this
pin is not being contacted by the tester.
EXPLANATION:
The identified pin is not being contacted by the tester, so any activity on this pin is viewed
by the test data supply system as an error. In this case, you are in effect asking the tester
to disconnect from a pin that it is not connected to. There is nothing inherently wrong with
that, but it will cause a hiccup in downstream processing.
USER RESPONSE:
Make sure you really intended the test mode to be boundary scan internal. If so, remove
the redundant stim Z on this pin, and rebuild the test mode.
WARNING (TTM-400): Illegal TTM switch flag(s) flags. Valid flags are: -h -t
EXPLANATION:
Illegal flags were specified for Build Test Mode either from the Graphical User Interface,
or from the command line.
USER RESPONSE:
If you were running from the Graphical User Interface, contact customer support (see
Contacting Customer Service on page 23) for assistance. There may be a
programming error. If you were running from the command line, you may only specify the
flags -h and -t.

WARNING (TTM-401): Unable to open file filename.
EXPLANATION:
The filename specified cannot be found or it cannot be opened.
USER RESPONSE:
Check that this filename exists then check the directory permissions for this file.
WARNING (TTM-403): Parent Mode keyword is not recognized. Parent Mode must be
specified in the Sequence Definition file.
EXPLANATION:

The current test mode only needs to be associated with a parent test mode when you
are providing an externally specified initialization sequence to preinitialize RAMs or
latches, before beginning operations in the current test mode. Therefore, the parent
mode should be specified in the initialization sequence file and not in the mode definition
file.
USER RESPONSE:
Remove the PARENT MODE statement from the mode definition file, and ensure that the
initialization sequence file specifies the appropriate parent mode via the
Begin_Test_Mode construct. For more information on externally specified initialization
sequences, refer to the "Coding an Externally Specified Initialization Sequence" in the
Encounter Test: Guide 2: Testmodes.
WARNING (TTM-404): [Severe] Latch latchID does not appear to be scannable in the
parent test mode testmode_name.
EXPLANATION:
The mode initialization sequence for the Child test mode included a Scan_Load event
(applied in the parent test mode) that included the LBIST_flush parameter. THE
LBIST_flush parameter is and optional request for Encounter Test to automatically
establish the initial state of the channel latches which accounts for any inversions
between each channel latch and its corresponding channel start. In this case, the scan
chain identified above was not scannable in the parent mode and therefore cannot be
automatically initialized by the parent mode scan.
USER RESPONSE:
Bring up the GUI design display and using the TOOLS pulldown, set the mode
initialization state. Check the latch given above along with its correlated latches (those
belonging to the same scan chain bit) to determine what they have been initialized to. If
their initialization states are not what was intended, correct the modeinit sequence and
rebuild the test mode.
WARNING (TTM-405): BIST_flush was specified, but is not supported at this time. It will be
ignored.
EXPLANATION:
Support for the BIST_flush option has been suspended due to technical problems.
Encounter Test results are not reliable when this option is used, so it has been disabled
for this release.
USER RESPONSE:

If the initial value of the channel latches is critical for your BIST methodology, then you
must specify the values individually in the Scan_Load event of the mode initialization
sequence instead of relying on the BIST_flush option. If it was not imperative for you to
use the BIST_flush option, then this message can safely be ignored.
WARNING (TTM-406): Syntax Error: Internal Pin test function not supported.
EXPLANATION:
An attempt was made to assign a test function to an internal pin or net in the Encounter
Test model. Test functions may only be assigned to primary I/O pins or latches.
USER RESPONSE:
Correct or remove the ASSIGN statement so that it does not refer to an internal pin or
net. For more information on the ASSIGN statement, refer to ASSIGN in the Encounter
WARNING (TTM-407): Implicit SE generation on pin pinid (Pin index index)

unsuccessful.
EXPLANATION:
This pin is a BIDI/CIO and it has an SO test function. Thus it requires a flag and
build_testmode will try to add an SE test function. This process was unsuccessful
finding a pin polarity or there is no logic connected to this pin. A SE (Scan Enable) test
function was not added for this pin.
USER RESPONSE:
WARNING (TTM-408): [Severe] Number of test function pins (pins) exceeds the TDR pin
limit.
EXPLANATION:
The number of pins that have test function attributes exceeds the number of tester
contacted pins defined in the TDR.
USER RESPONSE:
Change your pin attributes or specify a different TDR.
WARNING (TTM-409): Number of data pins exceeds number of TDR data inputs.
EXPLANATION:

The number of pins with test function defined exceeds the number of tester contact pins
defined in the TDR.
USER RESPONSE:
Specify a different TDR or reduce the test function pin count.
WARNING (TTM-410): [Severe] Number of scan-in pins exceeds number of TDR scan
inputs.
EXPLANATION:
The number of pins with scan-in test functions exceeds the number of scan-in pins
defined in the TDR. For OPMISR modes, the number of scan-in test functions includes
the number of channel mask enable (CME) pins.
USER RESPONSE:
Modify the pin test functions or specify a different TDR.
WARNING (TTM-411): [Severe] Number of clock pins exceeds number of TDR clock
inputs.
EXPLANATION:
The number of pins with clocking test functions exceeds the number of clock pins defined
in the TDR.
USER RESPONSE:
WARNING (TTM-412): Number of scan-in pins does not equal number of scan-out pins.
EXPLANATION:
The number of pins with scan-in test functions does not equal the number of pins with
scan-out pins. These must be equal for LSSD.
USER RESPONSE:
Modify the pin test functions.
WARNING (TTM-413): Unrecognized attribute value on hier pin pinid not applied.
EXPLANATION:
The attribute specified in the message is not recognized as a valid pin test function
attribute.

USER RESPONSE:
Refer to the Encounter Test: Guide 2: Testmodes for Mode Definition Syntax.
information.
WARNING (TTM-414): Unable to process attribute value on hier pin pinid.

EXPLANATION:
The attribute specified in the message is not recognized as a valid pin test function
attribute.
USER RESPONSE:
Refer to the Encounter Test: Guide 2: Testmodes for Mode Definition Syntax.
information.
WARNING (TTM-415): Unable to build Fault Model data - see preceding TFM message(s)
for details.
EXPLANATION:
A problem has been detected resulting in failure to build Fault Model data.
USER RESPONSE:
Refer to "TFM - Fault Model Messages" documentation for previous TFM messages.
WARNING (TTM-416): The number of clock isolation pins is greater than one. Only one is
allowed. TSV will choose just one and continue. This may give unpredictable test results.
EXPLANATION:
The number of pins with clock Isolation test functions is greater than one. Only one is
allowed.
USER RESPONSE:
Modify the pin test functions.
WARNING (TTM-417): Unable to build Hier Model active/inactive logic - see preceding THM
message(s) for details.
EXPLANATION:
A problem has been detected resulting in failure to build Hier Model active/inactive logic.
USER RESPONSE:

Refer to "THM - Encounter Test Hierarchical Model Messages" documentation for

previous THM messages.
WARNING (TTM-418): COMET TYPE mismatch for COMET comet_name1. It will be

changed to comet_name2 to match previous mode definitions.
EXPLANATION:
The COMET name given has already been defined in a previous mode. It can not be
redefined in this mode with a different TYPE. The previously defined TYPE will be used
in this mode.
USER RESPONSE:
Check previous mode definitions to verify the COMET TYPEs used.
WARNING (TTM-419): Test Type DRIVER_RECEIVER is not allowed with BOUNDARY_SCAN

= INTERNAL.
EXPLANATION:
Test Type DRIVER_RECEIVER is only allowed with BOUNDARY_SCAN EXTERNAL or NO.
The internal boundary scan mode does not contain all the logic necessary for
DRIVER_RECEIVER processing.
USER RESPONSE:
proper values. Change the boundary scan value and rerun if necessary.
WARNING (TTM-420): Attribute attributeName is missing an attribute value on hier pin

pinId.
EXPLANATION:
The referenced attribute has no right hand side attribute value (for example,
"TB_OFLAG="). The attribute is ignored and processing continues.
USER RESPONSE:
Correct the attribute specification and rerun if necessary. Refer to Specifying Test
Function Pin Attributes in Design Source in the Encounter Test: Guide 2: Testmodes
WARNING (TTM-422): Test Type Interconnect should be run with Boundary Scan External.
EXPLANATION:

Test Type Interconnect is only valid with BOUNDARY_SCAN EXTERNAL. The external
mode contains the active logic used in Interconnect testing.
USER RESPONSE:
proper MODEDEF values.
WARNING (TTM-423): BSDL file filename was not specified. It is a required file for Scan
Type 1149.1.
EXPLANATION:
1149.1 processing requires a BSDL file as input.
USER RESPONSE:
proper MODEDEF values.
WARNING (TTM-424): ASSIGN specifications will be ignored when Scan Type is 1149.1.
EXPLANATION:
1149.1 processing receives all pin flag data from the BSDL file. ASSIGN statements will
be ignored when processing this mode.
USER RESPONSE:
Refer to "Test Function Pins for an 1149.1 Mode" in the Encounter Test: Guide 2:
Testmodes for proper BSDL specification of pin flag data.
WARNING (TTM-425): Error opening the BSDL pin flag data.

EXPLANATION:
1149.1 processing receives all pin flag data from the BSDL file. There was a problem
accessing the pin flag data.
USER RESPONSE:
Refer to "Test Function Pins for an 1149.1 Mode" in the Encounter Test: Guide 2:
Testmodes for proper BSDL specification of pin flag data. Verify the BSDL file has been
properly specified.
WARNING (TTM-426): Number of MISR overflow pins exceeds number of TDR MISR
overflows.
EXPLANATION:

The number of pins with MISR OVERFLOW test functions exceeds the number of MISR
OVERFLOW pins defined in the TDR.
USER RESPONSE:
WARNING (TTM-427): IDDQ test type requires TDR Measure Current greater than zero.
EXPLANATION:
When TEST TYPE IDDQ is specified in the modedef file, the TDR requested in the
modedef file must have a Measure Current specified that is greater than zero.
USER RESPONSE:
Change your TEST TYPE or specify a different TDR.
WARNING (TTM-428): PRPG_NET attribute, value, found but there is no corresponding

PRPG polynomial specified.
EXPLANATION:
A PRPG_NET attribute was found in the hierModel but there was no PRPG attribute
found in the hierModel giving the polynomial values. This PRPG_NET attribute will be
ignored.
USER RESPONSE:
Specify a PRPG polynomial or remove the PRPG_NET statement in the model source
file and re-import the design.
WARNING (TTM-429): MISR_NET attribute, value, found but there is no corresponding

MISR polynomial specified.
EXPLANATION:
A MISR_NET attribute was found in the hierModel but there was no MISR attribute found
in the hierModel giving the polynomial values. This MISR_NET attribute will be ignored.
USER RESPONSE:
Specify a MISR polynomial or remove the MISR_NET statement in the model source file
and re-import the design.
WARNING (TTM-430): Invalid hierNetName, netname, in modedef file. PRPG definition

will be skipped.
EXPLANATION:

ON_BOARD_PRPG statement referenced an invalid hierModel net name. This PRPG

USER RESPONSE:
Correct the ON_BOARD_PRPG statement using a valid net name.
WARNING (TTM-431): Invalid hierNetName, netname, in modedef file. MISR definition will
be skipped.
EXPLANATION:
ON_BOARD_MISR statement referenced an invalid hierModel net name. This MISR
USER RESPONSE:
Correct the ON_BOARD_MISR statement using a valid net name.
WARNING (TTM-432): The maximum number of comet definitions allowed for a design is
64. No more Comets may be defined.
EXPLANATION:
The maximum number of comets has been defined. No more new comet definitions are
allowed. This statement is ignored.
USER RESPONSE:
Remove unused modes to free up comet definition space.
WARNING (TTM-433): The ON_BOARD_PRPG statement found in the testmode definition

is ignored because ON_BOARD was NOT specified in the IN portion of the Scan statement.
EXPLANATION:
ON_BOARD is required within the IN portion of the Scan statement for on-board PRPG.
The ON_BOARD_PRPG statement is ignored.
USER RESPONSE:
For PRPG data to be considered, the Mode Definition file must be enhanced to have
ON_BOARD specified within the Scan In statement. Refer to SCAN in the Encounter
WARNING (TTM-434): The ON_BOARD_MISR statement found in the testmode definition

is ignored because SCAN OUT=PO was specified.
EXPLANATION:

SCAN OUT=PO stipulates that all scan chains must feed primary outputs. This conflicts
with the use of an on-board MISR. The ON_BOARD_MISR statement is ignored.
USER RESPONSE:
ERROR (TTM-435): Unable to do Sequence Definition processing. Check previous

messages.
EXPLANATION:
Sequence definition processing has not completed successfully.
USER RESPONSE:
Refer to Encounter Test documentation for previous TTM messages.
WARNING (TTM-436): Test Function PI, pinid, in mode modename, is not at its defined
stability value (value) for this mode after simulation of Test mode initialization sequence
event eventid, pattern patternid. Test Data produced may be invalid.
EXPLANATION:
Encounter Test requires that no primary input stimuli occur when a clock or test inhibit
(TI) pin is not at its defined stability value (other than those necessary for returning to
stability). The referenced PI was not at its stability value at the end of simulation of the
referenced PI stim event. This violates assumptions made by Verify Test Structures and
may render the test data to be invalid.
USER RESPONSE:
Correct the Test Mode Initialization Sequences so that the test function pins are at
stability after applying the referenced stim event.
WARNING (TTM-437): Fixed Value latch, latchid, in test mode modename changed
state at event eventid, pattern patternid. Test Data produced may be invalid.
EXPLANATION:
When initializing a test mode by using a parent test mode, the normal restrictions (such
as overriding TI pins) are relaxed to allow the possibility of conflict between the parent
modes and the target modes stability states. In such a case, the burden is upon the user
to ensure that the condition does not cause invalid test data. In this case, a parent modes
fixed value latch is not holding its value; possibly this latch has no effect on the target
modes initialization, or it no longer needs to be fixed value from this point in the
initialization sequence.

USER RESPONSE:
Correct your Test Mode Initialization Sequences so that the fixed value latches remain
fixed after applying the given latch stim event. If this is not possible, then you must verify
that the fixed value is no longer required for purposes of the target test mode initialization
process.
ERROR (TTM-438): Test function pin name, in mode name is not at its defined stability
value (value) for this mode after simulation of the sequence name.
EXPLANATION:
Encounter Test requires that any test function pins that have a defined stability value
(Clock and Test-Inhibit pins) must be left at that value after applying the test modes
initialization and scanop sequences. The referenced PI or pseudo PI failed to be at its
stability value at the end of simulation of the sequence. This may cause inaccurate test
structure identification and invalid circuit states which prevent downstream applications
from properly functioning.
USER RESPONSE:
Correct your sequences so that the test function pins are at stability after applying the
sequence.
ERROR (TTM-439): TSImain did not complete successfully. Check preceding messages.
EXPLANATION:
A problem was detected preventing TSImain completion.
USER RESPONSE:
Refer to Chapter 75, TTM - Test Mode Messages for previous messages.
WARNING (TTM-440): A Sequence Definition file is required when MISR is defined without
specifying MRST (MISR Reset) test function on any pin.
EXPLANATION:
A MRST pin is required by build_testmode to generate MISR reset sequence. Either
specify a MRST test function on a pin or provide a user defined MISR reset sequence
USER RESPONSE:
Provide a user defined MISR reset sequence or specify MRST test function on an input
pin.

WARNING (TTM-441): PRPG FAST_FORWARD option was requested by at least one but
not ALL PRPG definitions. This option can only be used by ALL or NONE of the PRPG
definitions. FAST_FORWARD option will be ignored.
EXPLANATION:
The modedef On Board PRPG statement requested the FAST_FORWARD option. There
exists at least one other PRPG statement that does not request the FAST_FORWARD
option. In order to use this option, it must be requested on all the PRPG statements.
USER RESPONSE:
Refer to Encounter Test: Guide 2: Testmodes for correct Mode Definition Syntax..
Select FAST_FORWARD on all the PRPG statements or on none of them.
WARNING (TTM-442): hier pin pinid has value attribute. A BDY or CTL attribute is also
needed in a boundary scan internal mode if this pin is to be used for non-scan function or
random patterns testing (WRP or LBIST).
EXPLANATION:
All scan out and scan in pins require a BDY or CTL attribute when BOUNDARY SCAN
INTERNAL has been specified in order for this logic to be active in the mode.
USER RESPONSE:
Refer to Encounter Test: Guide 2: Testmodes for correct Mode Definition Syntax..
WARNING (TTM-443): Test Type IOWRAP is not allowed with BOUNDARY_SCAN =

INTERNAL.
EXPLANATION:
Test Type IOWRAP is only allowed with BOUNDARY_SCAN EXTERNAL or NO. The
internal boundary scan mode does not contain all the logic necessary for IOWRAP
processing.
USER RESPONSE:
proper MODEDEF values. Change your boundary scan value.
WARNING (TTM-444): Test Type STATIC INTERCONNECT is not allowed with

BOUNDARY_SCAN = INTERNAL.
EXPLANATION:

Test Type STATIC INTERCONNECT is only allowed with BOUNDARY_SCAN

EXTERNAL or NO. The internal boundary scan mode does not contain all the logic
necessary for STATIC INTERCONNECT processing.
USER RESPONSE:
WARNING (TTM-445): Number of design pins exceeds TDR pin limit.

EXPLANATION:
The number of pins on this design exceeds the number of tester contact pins defined in
the TDR.
USER RESPONSE:
Specify a different TDR.
WARNING (TTM-446): COMET TYPE mismatch for COMET comet. This user defined
comet uses the tdr name. It must have type STATS_ONLY. The COMET TYPE will be
changed to STATS_ONLY.
EXPLANATION:
The COMET named for the TDR must always have type STATS_ONLY. This COMET
definition will be ignored.
USER RESPONSE:
Remove this COMET statement from the modedef file and let the system setup the
default TDR COMET name with the proper type.
WARNING (TTM-447): The no_interconnect (NIC) pin test functions should not be specified
when SCAN BOUNDARY EXTERNAL MODEL has not been specified. The NIC pin test
functions will be ignored.
EXPLANATION:
NIC test functions affect Encounter Test processing only for a test mode defined as
SCAN BOUNDARY EXTERNAL MODEL. In such a test mode any logic that connects
only to a NIC- test function will be considered inactive. For any other kind of test mode
the NIC test function is ignored.
USER RESPONSE:
To observe the NIC test functions, change the test mode to SCAN BOUNDARY EXTERNAL
MODEL. Otherwise, ignore this message.

WARNING (TTM-448): Scan Boundary Model is not allowed with BOUNDARY_SCAN =

value.
EXPLANATION:
The MODEL option is only allowed with BOUNDARY_SCAN = EXTERNAL. This option
flags the mode to be used during Boundary Model Build
USER RESPONSE:
WARNING (TTM-449): Scan Boundary MCM is not allowed with BOUNDARY_SCAN =

value.
EXPLANATION:
The MCM option is only allowed with BOUNDARY_SCAN = EXTERNAL. This option
flags the mode to be used during Boundary Model Build. It also informs the active node
map builder to build an MCM external model. The default is to build a chip external
model.
USER RESPONSE:
WARNING (TTM-450): Pin name pinid given by the CORRELATE model attribute is not
found in the hierModel. This attribute will be ignored.
EXPLANATION:
The Pin name specified is not found in the hierModel. Correlate attributes are found in
the hierModel source.
USER RESPONSE:
Refer to "TEST_FUNCTION_PIN_ATTRIBUTES " in the Encounter Test: Guide 2:
Testmodes for information on proper model attributing. Check that the pin name is
spelled correctly on the CORRELATE attribute in the model source.

WARNING (TTM-451): Pin name pinid is a correlated pin and is not allowed to have test
function defined on it. The test function flags will be ignored.

EXPLANATION:
The Pin name specified has a test function attribute either in the hierModel or in the
modedef file. A correlated pin is not allowed to have a test function assigned. It received
its test function value from the Primary Pin test function value.
USER RESPONSE:
proper MODEDEF values. Check the modedef file and the model source for test function
attributes on this pin and remove them.
WARNING (TTM-452): Pin name pinid1 is a correlated pin and is not allowed to also be
a Primary Pin. The CORRELATE attribute on pin pinid2 is ignored.
EXPLANATION:
The pin name specified has been named the Primary Pin for the second pin specified
using a CORRELATE attribute in the hierModel. A correlated pin is not allowed to be a
Primary Pin.
USER RESPONSE:
Refer to "TEST_FUNCTION_PIN_ATTRIBUTES " in the Encounter Test: Guide 2:
Testmodes for information on proper model attributing. Check that the pin name is
spelled correctly on the CORRELATE attribute in the model source.
WARNING (TTM-453): [Severe] The tester can not contact all the pins (n) needed for static
tests in this test mode.
EXPLANATION:
The test mode definition specifies static logic tests and not internal boundary scan, but
the number of active primary inputs and outputs exceeds both the TDR Full Function Pin
Limit parameter and the TDR PMU Capacity parameter. When you run test generation,
only the primary I/Os that have test function attributes will be used.
USER RESPONSE:
Make sure the specifications in your test mode definition rule (TDR, test types, boundary
scan) are correct. Make sure you are accessing the correct version of the TDR. If you
must run logic tests on a tester with fewer pins than your product, and you are not using
boundary scan, then your test coverage will suffer.
WARNING (TTM-454): This test mode specifies one or more test types that require full-
function tester pins, but there are not enough of them to contact all the pins (n) used in the
test mode.

EXPLANATION:
The test mode definition does not specify internal boundary scan, but the number of
active primary inputs and outputs exceeds the TDR Full Function Pin Limit. The test
mode also specifies some test type(s) that cannot use parametric measure units. When
you run test generation, only the primary I/Os that have test function attributes will be
used.
USER RESPONSE:
Make sure the specifications in your test mode definition rule (TDR, test types, boundary
scan) are correct. Make sure you are accessing the correct version of the TDR. If you
must run the specified test type(s) on a tester with fewer pins than your product, and you
are not using boundary scan, then your test coverage will suffer.
WARNING (TTM-455): [Severe] This test mode specifies driver and receiver testing, but
the tester does not have enough PMU-serviceable pins to handle all the pins (n).
EXPLANATION:
Driver and receiver testing is supported for the specific purpose of applying parametric
tests to the primary I/O pins of the product. Since the product has more pins than are
supported by the testers parametric measuring units, and Encounter Test will assume
that only the pins having test function pin attributes can be measured parametrically. This
will seriously limit the test coverage attainable for driver and receiver faults.
USER RESPONSE:
Make sure the specifications in your test mode definition rule (TDR and
TEST_TYPE=DRIVER_RECEIVER) are correct. Make sure you are accessing the
correct version of the TDR. If you must run driver and receiver tests on a tester with fewer
pins than your product, then you may want to find out exactly which pins can be
measured parametrically by the tester, and block off the immeasurable primary inputs
with a TI (test inhibit) signal. If you have primary outputs or bidirectional pins that cannot
be accessed by PMUs, then you are stuck because Encounter Test has no way to specify
which pins they are.
WARNING (TTM-456): [Severe] Build NodeIsActive data did not complete successfully.
Check preceding messages.
EXPLANATION:
The mode definition function Build NodeIsActive failed. There should be previously
specified THM numbered messages. If there are no previous messages, there may have
been an abnormal termination of the Build NodeIsActive process.
USER RESPONSE:

Refer to the previously specified THM - Hierarchical Model Messages on page 1209. If
there are no THM numbered messages, check for a "core" file. Save the core file and call
WARNING (TTM-457): [Severe] Invalid ASSIGN statement hierNetName, netname, in

modeDef file. This net has greater than one internal output pin, only one is allowed. This
ASSIGN statement will be ignored.
EXPLANATION:
The netname used in the ASSIGN statement had more than one internal output pin on
the net. A latch ASSIGN statement net can have only one internal output pin.
USER RESPONSE:
Remove the ASSIGN statement.
ERROR (TTM-458): Net name, netname, is not found in the hierModel. This ASSIGN
EXPLANATION:
The ASSIGN statement referenced an invalid hierModel net name. This ASSIGN
USER RESPONSE:
Correct the ASSIGN statement using a valid net name.
ERROR (TTM-459): Pin name, pinname, is not found in the hierModel. This ASSIGN
EXPLANATION:
The ASSIGN statement contained a pin name that could not be found in the hierarchical
model.
USER RESPONSE:
Check for a typographical error. If you believe the pin name was spelled correctly, make
sure you have all the right qualifiers included. As a last resort, you can build a dummy
test mode to display the design, and check the pin name in the information window when
it is displayed. When you find the correct name, edit the test mode definition and run Build
Test Mode again.
WARNING (TTM-460): Test Function attribute on pin pinname1 will override the attribute
specified on pin pinname2 for latch block blockname.
EXPLANATION:

These attributes were specified on two different usage blocks that trace back to the same
latch, and thus are in conflict with each other. Pin pinname1 is at a higher level in the
structure, so this is interpreted as an intentional override, and its test function will be
placed on the latch primitive blockname.
USER RESPONSE:
Make sure the override was intentional. If it was not intentional, then edit the test mode
definition by either removing the ASSIGN statement for pinname1 or changing it to
PIN pinname, TEST_FUNCTION=NIL
if the specification originated in the model source. In the latter case, you may prefer to
edit the model source and re-import the design. Then rerun Build Test Mode.
WARNING (TTM-461): Test Function attribute on pin pinname1 conflicts with the attribute
specified on pin pinname2 for latch block blockname. Neither of these attributes will be
used.
EXPLANATION:
These attributes were specified on two different usage blocks that trace back to the same
latch, and thus are in conflict with each other.
Build Test Mode has no criterion by which to judge one of these to be more likely correct,
so the specification is treated as being invalid.
USER RESPONSE:
Find out which of the specifications is correct. Then remove the other one by either
removing the ASSIGN statement for it in the test mode definition file or, if the specification
originated in the model source, setting it to NIL. In the latter case, you may prefer to edit
the model source and re-import the design. Then rerun Build Test Mode.
WARNING (TTM-462): Invalid test function polarity value v on internal pin pinname. This
attribute will be ignored.
EXPLANATION:
This is a syntax error. The polarity must be + or 1 (positive) or 0 (negative).
USER RESPONSE:
Correct the polarity in the model source or in the test mode definition file statement. Then
re-import the design if the error was in the model source or rerun Build Test Mode if the
error was in the test mode definition file.
WARNING (TTM-463): Invalid test function tf on internal pin pinname in model source.
This attribute will be ignored.

EXPLANATION:
This is a syntax error. The only test functions allowed on internal pins are for latches,
namely: TI, TEST_INHIBIT, FLH, and LINEHOLD, FSM and FINITE_STATE_MACHINE.
Only certain combinations are allowed as well. An incorrect combination of valid test
functions will also cause this message to print.
USER RESPONSE:
Correct the test function in the model source or in the test mode definition file statement.
Then re-import the design if the error was in the model source or rerun Build Test Mode
if the error was in the test mode definition file.
WARNING (TTM-464): The back trace on internal pin pinname encountered more than
one latch block. This test function specification is invalid and will be ignored.
EXPLANATION:
Encounter Test must identify which latch primitive is associated with the specified test
function. In this case the designation is ambiguous because more than one latch
primitive feeds the specified pin (pinname). Since Encounter Test cannot ascertain which
latch is supposed to carry the specified test function, the test function specification is
ignored.
USER RESPONSE:
Ensure that the logic structure is correct. If it is, then make sure that all TI signals were
correctly specified which would block paths from some of the latches to the designated
pin. If more than one latch does truly feed the designated pin in this test mode, and the
test function specification for the target latch cannot be defaulted, then it will have to be
specified at a lower level in the hierarchy. If this specification is in the model source, you
can edit it and re-import the design or you can override it with the assign statement
PIN pinname, TEST_FUNCTION=NIL
in the test mode definition. In either case, move the test function specification to a lower
level block either in the model source or in the test mode definition. Then rerun Build Test
Mode.
WARNING (TTM-465): The back trace on internal pin pinname did not encounter any latch
blocks. This test function specification is invalid and will be ignored.
EXPLANATION:
The usage block that contains the specified pin (pinname) does not have any latch
primitives inside it. The usage block may have an incorrect cell specified. More likely, the
test function specification is superfluous or was placed on the wrong usage block.

USER RESPONSE:
Make sure the usage blocks cell specification is correct. If it is, then determine which
usage block contains the latch that the test function was intended for. Edit the test
function source or the test mode definition to either remove the test function (if it is
superfluous) or place it on a pin on the correct usage block.
WARNING (TTM-466): The linehold attribute specified on pin pinname is ignored because
the associated latch, blockname, is not scannable in the parent test mode.
EXPLANATION:
The reason for using a linehold (FLH) attribute on a fixed value latch instead of
test_inhibit (TI) is to allow the value to be overridden at test generation run time. But
Encounter Test does not know how to override the value in this latch because it is not
scannable.
USER RESPONSE:
Modify the logic so that this latch is scannable in the parent mode, or change the FLH
attribute to TI. Note that if the logic is modified, you will have to re-import the design;
otherwise, you should be able to resume processing with Build Test Mode for the parent
test mode or the target mode.
WARNING (TTM-467): The test function attributes on pins pinname1 and pinname2
conflict. These latches are constrained by their correlation in the parent mode scan
configuration. The linehold attribute on pinname will be changed to Test Inhibit.
EXPLANATION:
One of the latches was specified as TI and the other as linehold. The latches cannot be
loaded via the parent scan operation to independent values, and therefore, the lineheld
latch must always be initialized to the same value to agree with the TI specification on
the other latch. Therefore, the linehold specification is dropped and both latches will be
treated as TI.
USER RESPONSE:
If there is a need to override the linehold value on the one latch, then the design will have
to be changed to make the two latches independent in the parent scan mode. Then re-
import the design. If you do not have to override the linehold value on this latch, then no
action is necessary in response to this message.
WARNING (TTM-468): The test function attributes on pins pinname1 and pinname2
have conflicting polarity. These latches are constrained by their correlation in the parent
mode. The initialized value will be used for these latches.

EXPLANATION:
The two latches listed in the message text are specified to be overrideable (linehold) fixed
value latches. The linehold value that they may be overridden to will be set by modifying
the mode initialization sequence so as to scan in the value using the parent mode scan
operation.
Because of the way these latches are interconnected in the parent mode scan chain,
they cannot be initialized to independent states. The particular states specified in the test
functions conflict, as they cannot be simultaneously reached using the parent modes
scan operation.
USER RESPONSE:
Assuming the parent mode was defined correctly, one of these two latches will have to
be given a different test function so that they are in agreement. Modify the logic source
or the test mode definition to change the test function specification. Then resume by re-
importing the design or rerunning Build Test Mode respectively.
WARNING (TTM-469): Latch block blockname has a test function of vTI but its initial
value is e. Its effective test function is eTI.
EXPLANATION:
One purpose of the test mode initialization sequence is to set all fixed value latches to
their designated states. In this case, the initial value, determined by the mode
initialization sequence, is different from the state designated by the test function
specification. Encounter Test uses the value determined by mode initialization sequence.
USER RESPONSE:
Change the mode initialization sequence to put the correct initial value into the latch,
which agrees with the test function specified. Then rerun Build Test Mode.
WARNING (TTM-470): Latch blockname has a test function specified as v2FLH, but this
latch block does not hold its value. The test function is ignored.
EXPLANATION:
This is not a fixed value latch, as evidenced by the fact that it does not hold its value. The
test function FLH is valid only for fixed value latches.
USER RESPONSE:
Determine whether the latch in question is supposed to be a fixed value latch or a
scannable latch. If it is supposed to be fixed value, then the logic must be changed to
either gate off its clock(s) or gate in its current value when a clock is pulsed. If it is a

scannable latch, then remove the FLH test function specification and supply the linehold
information through the linehold file input to the test generation application.
WARNING (TTM-471): 3-State Primary Input pin, pinname, in mode testmode is not at
high-Z after simulation of the sequence_type Sequence.
EXPLANATION:
Encounter Test requires that any 3-state Primary Inputs that do not have a defined
stability value must be at high-Z after applying the test modes initialization and PRPG
Save/Restore sequences. The specified 3-state Primary Input is not a test function pin
with a defined stability value, and it is not at high-Z at the end of the simulation of the
sequence.
USER RESPONSE:
Correct your Test Mode Initialization and PRPG Save/Restore Sequences so that the 3-
state Primary Inputs (which are not test function pins) are at high-Z at the end of the
sequences.
WARNING (TTM-472): Test Function attributes were assigned for some latches, but no test
mode initialization sequence was specified. All latch test function attributes are ignored.
EXPLANATION:
Encounter Test does not support test function attributes on any latches except fixed value
latches. Fixed value latches must be initialized in some other test mode (the parent),
which is specified through the user-supplied mode initialization sequence. Since you did
not specify a mode initialization sequence, there can be no fixed value latches (other
than ones that are uninitialized), so the latch test functions would not be valid.
USER RESPONSE:
Write a test mode initialization sequence which sets all fixed value latches to the
appropriate states and specify the name of the file containing this sequence in the test
mode definition. Rerun Build Test Mode.
WARNING (TTM-473): Latch blockname has test function specified as v1FLH. The mode
initialization sequence sets the value v2 in this latch. The test function will be treated as
v2FLH.
EXPLANATION:
The value of this latch as specified by the test function disagrees with the initial value of
the latch. The initial value is taken as the default linehold value, so the test function as
seen by the Encounter Test applications is changed to reflect the initial value.
USER RESPONSE:

Realize that for any test generation run where you do not override the linehold value for
this latch, the initial value will be used, and not the value specified by the test function. If
you want to avoid this confusion, then either change the latch state in the mode
initialization sequence or its state specified in the test function and rerun Build Test
Mode.
WARNING (TTM-474): Latch block blockname has test function vtfFLH. The mode
initialization sequence did not initialize this latch. The test function is ignored.
EXPLANATION:
The initial value of a latch (as determined by the test mode initialization sequence) is
taken as its default linehold value, so it is important that this be the same as the value
specified in the test function. Since this latch does not have a predictable initial value, it
cannot be processed as a fixed value latch, and its test function is therefore invalid. The
latch will be treated as floating, and for purposes of the x-state propagation check, as an
X-generator.
USER RESPONSE:
Specify a value for this latch in the test mode initialization sequence. Rerun Build Test
Mode.
WARNING (TTM-475): Latch blockname has test function specified as vTI, but this latch
did not hold its value. The test function is ignored.
EXPLANATION:
This is not a fixed value latch, as evidenced by the fact that it does not hold its value. The
test function TI is valid only for fixed value latches.
USER RESPONSE:
Either modify the logic to make this a fixed value latch or remove the test function
specification. To make it a fixed value latch, you must either gate off its clock(s) or gate
in its current value when a clock is pulsed. Rerun Build Test Mode.
WARNING (TTM-476): Pin pinName has test function of SI, but there is no tester PRPG
defined for scan. The TEST_TYPES statement specified LOGIC SIGNATURES, but both
LBIST and WRP test generation will fail.
EXPLANATION:
The only test methods in Encounter Test that support signature generation are LBIST
and WRP. Both LBIST and WRP tests depend upon a tester PRPG to drive any scan
chains whose data is from a primary input (as opposed to an on-product PRPG in the
case of LBIST).

According to the TDR, no tester PRPG is defined, so neither LBIST nor WRP can be run
in this test mode.
USER RESPONSE:
There are several possible sources of error that could have caused this message, or it
may not be a problem at all. If you do not intend to generate WRP or LBIST tests in this
test mode, then you can ignore this message. Removing the SIGNATURES keyword
from the TEST_TYPES statement in the mode definition will suppress this message if
the test mode is built again. If you do intend to generate WRP or LBIST tests in this test
mode, then you must change one of the following:
Change the test mode definition to point to the correct TDR that has PRPGs
defined.
Get the latest version of the TDR that has the PRPGs defined.
If it is LBIST, you may want to change the logic by connecting this scan chain
input to an on-product PRPG output.
WARNING (TTM-477): FIXED_VALUE_DEFAULT = FLH has been specified but no parent

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Encounter Test: Reference: Messages

Product Version 15.12

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THT-600 through THT-999 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1205

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TMT-051 through TMT-306 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1664

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TSV-151 through TSV-194 .............................................. 2093

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Troubleshooting TSV-014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2814

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Typographic and Syntax Conventions

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Encounter Test Documentation Roadmap

Command GUI Expert

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Getting Help for Encounter Test and Diagnostics

Contacting Customer Service

October 2015 23 Product Version 15.12

Encounter Test And Diagnostics Licenses

Using Encounter Test Contrib Scripts

What We Changed for This Edition

Revisions for Version 15.10

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Revisions for Version 15.11

Revisions for Version 15.12

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Interactive and Background Messages

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Chapter 16, TCW - Stand Alone Random Pattern Simulation Messages

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Chapter 48, TLM - Logic Model Messages

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Chapter 82, TWC - Command Script Messages

Message Severity Codes

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Message Return Codes

Severity Code Return Code

Extended Message Help

displays interactive help information for messages TSV-001 and TSV-314.

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C5CCS-001 through C5CCS-003 on page 37

C5CCS-001 through C5CCS-003

WARNING (C5CCS-003): [Severe] Invalid mode specified mode.

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