TND352 D

DC-DC Converters Feedback
and Control
Agenda
Feedback generalities
Conditions for stability
Poles and zeros
Phase margin and quality coefficient
Undershoot and crossover frequency
Compensating the converter
Compensating with a TL431
Watch the optocoupler!
Compensating a DCM flyback
Compensating a CCM flyback
Simulation and bench results
Conclusion
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Agenda
Poles and zeros
Conclusion
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3
What is Feedback?
A target is assigned to one or several state-variables, e.g. Vout
= 12 V.
A circuitry monitors Vout deviations related to Vin, Iout, T° etc.
If Vout deviates from its target, an error is created and fed-back
to the power stage for action.
The action is a change in the control variable: duty-cycle (VM),
peak current (CM) or the switching frequency.
Compensating for the converter shortcomings!
Input voltage Output voltage

Vin DC-DC Vout Input voltage
Rth
Vth Vout
Vin
action
control
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The Feedback Implementation
Vout is permanently compared to a reference voltage Vref.
The reference voltage Vref is precise and stable over temperature.
The error,ε = Vref − αVout, is amplified and sent to the control input.
The power stage reacts to reduce ε as much as it can.
Power stage - H
Vout
Control
variable d
Error amplifier - G
Rupper
+
-
Vin
α
-
+
Vp
Modulator - GPWM Vref Rlower
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Agenda
Poles and zeros
Conclusion
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Positive or Negative Feedback?
Do we want to build an oscillator?
The « Plant »
Vin(s) + ε Vout(s)
Error voltage H(s)
−
G(s)
Vout ( s ) H (s)
=
Vin ( s ) 1+ H (s)G (s) Open-loop gain T(s)
⎡ H (s) ⎤
Vout ( s ) = lim ⎢ Vin ( s ) ⎥ To sustain self-oscillations, as Vin(s)
Vin ( s ) → 0 1 + G ( s ) H ( s ) goes to zero, quotient must go infinite
⎣⎢ ⎦⎥
Sign is neg for:
ϕ = -180° =1
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Conditions for Oscillations
when the open-loop gain equals 1 (0 dB) – cross over point
total rotation is -360°: -180° for H(s) and -180° for G(s)
¾ we have self-sustaining oscillating conditions
Total phase delay at fc:
180
Loop gain |H(s)| -180° H(s) power stage

Gain is 1 -180° G(s) opamp
90.0 at fc
total = -360°
0
0 dB
Loop phase arg H(s)
-90.0 ϕ = -180°
-180 21
22 -180°
1 10 100 1k 10k 100k

frequency in hertz
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The Need for Phase Margin
we need phase margin when T(s) = 0 dB
we need gain margin when arg T(s) = -360°
180 80.0 T(s) phase phase

Phase margin:
margin The margin before the loop
gain phase rotation arg T(s)
arg T(s)
90.0 40.0
= -360° reaches -360° at T(s) = 0 dB
ph_vout in degrees
vdbout in db(volts)
0° 2
Plot1
0 0
0 dB
gain
margin
-90.0 -40.0
Crossover
1
frequency fc
T(s) = 0 dB Gain margin:
The margin before the loop
-180 -80.0
gain T(s) reaches 0 dB at a

10 100 1k 10k 100k freq. where arg T(s) = -360°
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Agenda
Poles and zeros
Conclusion
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Poles and Zeros
A plant (power stage) loop gain is defined by:
N (s)
H (s) =
numerator
D (s) denominator
solving for N(s) = 0, the roots are called the zeros
solving for D(s) = 0, the roots are called the poles
5k
Two zeros f z1 = = 796 Hz
sz1 = −5k 2π
H (s) =
( s + 5k )( s + 30k )
sz2 = −30k f z2 =
30k
= 4.77 kHz
s + 1k 2π
s p1 = −1k 1k
f p1 = = 159 Hz
One pole
2π
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Poles and Zeros
A pole lags the phase by -45°at its cutoff frequency
0
Vin Vout 20.0

Cutoff frequency
R2 0
-3 dB
1k
-20.0
V1 C1
-40.0
AC = 1 10nF -60.0 |Vout(s)| -1 slope

-20 dB/decade
1
-20.0
Vout ( s ) 1 1 -45° at
= =
-40.0
cutoff
Vin ( s ) 1 + sRC 1 + s -60.0
ω0 -80.0 argVout(s) 2
10 100 1k 10k 100k 1Meg 10Meg
1
ω0 =
RC -90° delay
for f = ∞
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Poles and Zeros
A zero boosts the phase by +45°at its cutoff frequency
0 0
40.0 1 20.0
+1 slope |Vout(s)|
+1 slope
0 +20 dB/decade 1
vdbout in db(volts)
30.0
+20 dB/decade
vdb2 in db(volts)
plot1
Plot1
-20.0
20.0
-40.0
10.0 Cutoff frequency
0 |Vout(s)| -60.0
-3 dB
10 100 1k 10k 100k 1Meg 10Meg
frequency in hertz
90.0
Cutoff frequency 2
90.0
argVout(s)
70.0 -3 dB 90° 90°
ph_v2 in degrees
ph_vout in degrees
70.0
Plot2
50.0
+45° at +45° at
plot2
50.0
30.0 cutoff 30.0 cutoff

10.0
0° argVout(s) 10.0 0°
2
10 100 1k 10k 100k 10 100 1k 10k 100k 1Meg 10Meg
frequency in hertz frequency in hertz
Vin Vout
The general form of a zero:
C1 s
10nF
s Vout ( s ) sRC ω0
G (s) = 1 + = =
ω0 V1 R2 Vin ( s ) 1 + sRC 1 + s
AC = 1 1k
ω0
1
ω0 =
RC
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The Right Half-Plane Zero
In a CCM boost, Iout is delivered during the off time: I out = I d = I L (1 − D )
Id(t) Id(t)
IL0 IL1
Vin Vin
L L
IL(t) IL(t)
Id0
Id1
d̂
t t
D0Tsw D1Tsw
Tsw Tsw
If D brutally increases, D' reduces and Iout drops!
d VL ( t )
What matters is the inductor current slew-rate dt
Occurs in flybacks, buck-boost, Cuk etc.
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The Right-Half-Plane-Zero
With a RHPZ we have a boost in gain but a lag in phase!
1
40.0
|Vout(s)|
20.0 +1 slope
vdbout in db(volts)
+20 dB/decade LHPZ

Plot1
-20.0
s
G (s) = 1 +
-40.0
ω0
180 RHPZ
argVout(s)
90.0
ph_vout in degrees
s
Plot2
G (s) = 1 −
0
-90.0 -90° 2
ω0
-180
1 10 100 1k 10k 100k 1Meg

frequency in hertz
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Agenda
Poles and zeros
Conclusion
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How much Margin? The RLC Filter
let us study an RLC low-pass filter, a 2nd order system
R1 L1
1
T (s) =
{R} {L}
3 2 1 Vout
LCs 2 + RCs + 1
C1
1 1
Vin {C}
T (s) = =
s2 s s2 s
+ 2ζ +1 + +1
ωr 2 ωr ωr 2 ωr Q
1
parameters ωr =
LC
f0=235k
L=10u 1
C Q=
C=1/(4*3.14159^2*f0^2*L) ζ =R
w0=({L}*{C})^-0.5 4L 2ζ
Q=10 zeta
R=1/((({C}/(4*{L}))^0.5)*2*{Q}) ωr resonant freq.
ζ damping factor
Q quality coeff.
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The RLC Response to an Input Step
changing Q affects the transient response
Q=5 Q < 0.5 over damping

1.80
Q=1 Q = 0.5 critical damping

Q > 0.5 under damping
Q = 0.707
vout#6, vout#5, vout#4, vout#3, vout in volts
1.40
Overshoot = 65%
Plot1
1.00 11
9
10
8
7
Asymptotically stable
600m
Q = 0.5 Fast response and no overshoot!
200m Q = 0.1
5.00u 15.0u 25.0u 35.0u 45.0u

ti i d
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Where is the Analogy with T(s)?
in the vicinity of the crossover point, T(s) combines:
one pole at the origin, ω0 and one high frequency pole, ω2
9 Link the closed-loop response to the open-loop phase margin:
1
T(s) T (s) = (OL)
180 80.0
⎛ s ⎞⎛ s ⎞
phase
⎜ ⎟⎜ 1 + ⎟
gain ω
⎝ 0 ⎠⎝ ω 2 ⎠
90.0 40.0 Close the

loop
T (s) 1
in degrees
vdbout in db(volts)
0° = (CL)
1+ T (s)
2
s2
0 0
0 dB s
+ +1
ph_vout
ω0ω2 ω0
-90.0 -40.0
1
-1
T (s)
Link open-loop ϕm -2 =
1
-180 -80.0
1+ T (s) s2 s
with closed-loop Q + +1
10 100 1k 10k 100k
ωr 2 ωr Q
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Closed-Loop Q Versus Open-Loop ϕm
a Q factor of 0.5 (critical response) implies a ϕm of 76°
a 45° ϕm corresponds to a Q of 1.2: oscillatory response!
10
Q
7.5
1
( 1+ tan( φ) ) 2
4
5
ϕm
tan( φ)
2.5
0.5
0
0 25 50 75 100
76°
360
φ⋅
2⋅ π
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Summary on the Design Criteria
compensate the open-loop gain for a phase margin of 70°
make sure the open-loop gain margin is better than 15 dB
never accept a phase margin lower than 45° in worst case
5.12
PM = 10°
PM = 25°
PM = 45°
5.06
PM = 76°
vout2#a, vout2, vout2#b, vout2#d in volts
Plot2
5.00 5
1
3
2
f ( Cout , f c , ΔI out ) 4.94
4.88
f ( PM )
300u 900u 1.50m 2.10m 2.70m
time in seconds
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Agenda
Poles and zeros
Conclusion
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DC-DC Output Impedance
A DC-DC conv. combines an inductor and a capacitor

As f is swept, different elements dominate Zout,OL
Open-loop model 2 f0
Lout Rlf 20.0
Z02
⎛ Rlf ⎞
1+ ⎜ ⎟
100u 10m Zout (dBΩ)
4 1 2 Vout Rlf ⎝ Z0 ⎠
0
Resr
1m I1 Lout f (Hz)
vdbout in db(volts)
AC = 1
plot1
-20.0
3 Cout
Cout
1000uF -40.0
RLf Resr
-60.0 2
Crossover region
A buck equivalent circuit 1 10 100 1k
frequency in hertz
10k 100k 1Meg
⎛ 1 ⎞
Z out = ( sLout + RLf ) || ⎜ Resr + ⎟ To avoid stability issues,
⎝ sCout ⎠
fc >> f0
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Closing the Loop…
At the crossover frequency Zout,CL ≈ Zout,OL
100
|T(s)|
50.0
fc
vdbout#b, vdbout, vdberr in db(volts)
Plot1
|Zout,OL| 2
-50.0
5
3
|Zout,CL|≈| Zout,OL|
|Zout,CL|
-100
1 10 100 1k 10k 100k

frequency in hertz
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Calculating the Output Impedance
the closed-loop output impedance is dominated by Cout

1 1 1 1
Z out ,CL ≈ ≈
2π f c Cout 1 + T ( s ) 2π f cCout 2 − 2 cos (ϕm )
2
Zout Zout
degrades improves
Open-loop phase
margin affects the
1 1 closed-loop output
1 + T ( fc ) impedance
ϕm °
0
20 40 60 80
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An Example with a Buck
Let’s assume an output capacitor of 1 mF

The spec states a 80 mV undershoot for a 2 A step
How to select the crossover frequency?
ΔI out ΔI out
ΔVout ≈ fc ≈
2π f c Cout ΔVout Cout 2π
2 1
fc ≈ = 4 kHz Z Cout @ 4 kHz = = 40 mΩ
80m ×1m × 2π 2π × 4k ×1m
Select a 1000-µF capacitor featuring less than a 40-mΩ ESR
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Setting the Right Crossover Frequency
Compensate the converter for a 4 kHz fc
Compensated open-loop gain

180 80.0
Buck operated in voltage-mode
90.0 40.0
phase
ϕm = 70°
ph_verr in degrees
vdberr in db(volts)
Plot1
0 0 4
fc
-90.0 -40.0 3
gain
-180 -80.0
10 100 1k 10k 100k

frequency in hertz
4 kHz
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Step Load the Output
rLf L1
10m 100u vout
a c Vout
7 3
d
the load varies
11
R10
PWM switch VM p 1m
Vin
X3 I1
10
PWMVM 16
L = 100u
Fs = 100k C5
1mF
from 100 mA to 2.1 A
H(s)
12 vout
GAIN
X1 C2
GAIN {C2}
K = 0.5 PWM R7
{R3}
C1
gain {C1}
R2
{R2}
Rupper
10k 8
13 C3
5 {C3}
Verr Rlower
X2 V2 10k
AMPSIMP 2.5
G(s)
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Measure the Obtained Undershoot
5.00
5
ΔI
ΔV ≈ 40m
4.98
2 − 2 cos (ϕm )
vout in volts
Plot1
4.96
2
ΔV ≈ 40m × = 70 mV
1.14
4.94
70 mV
4.92
1.61m 2.42m 3.23m 4.05m 4.86m

time in seconds
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Agenda
Poles and zeros
Conclusion
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How do we Stabilize the Converter?
1. Select the crossover frequency fc (assume 4 kHz)
2. Provide a high dc gain for a low static error and good input rejection
3. Shoot for a 70° phase margin at fc
4. Evaluate the needed phase boost at fc to meet (3)
5. Shape the G(s) path to comply with 1, 2 and 3
Open-loop Bode plot of the power stage, H(s) Asc ,OL ( s )

40.0 180
Asc ,CL ( s ) =
1+ T ( s)
20.0 90.0 Gain
ph_voutin degrees
vdboutin db(volts)
Plot1
0 0
Phase Arg H(s) @ fc
-20.0 -90.0
-40.0 -180
|H(s)| @ fc
1
10 100 1k 10k 100k
frequency in hertz
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First, Provide Mid-Band Gain at Crossover
1. Adjust G(s) to boost the gain by +21 dB at crossover
¾ Create the so-called mid-band gain
40.0 180
Push the
gain up. 0 dB@fc
20.0 90.0 Gain
ph_voutin degrees
vdboutin db(volts)
Plot1
0 0
Phase Tailor G(s) to

exhibit a gain
|H(s)|= -21 dB of +21 dB@ fc.
-20.0 -90.0
Arg H(s)= -175°
-40.0 -180
10 100 1k 10k 100k

frequency in hertz 4 kHz
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Second, Provide High Gain in DC
2. An integrator provides a high dc gain but rotates by -270°
¾ This is the origin pole
C1
100n
60.0 360
60 dB 1 2
E1
R1 1k
10k
4 Vout
-20 dB per decade V1

AC = 1
30.0 180
slope -1
vdbout in db(volts)
p in unknown
Plot1
0 0
-180° by inverting
op amp
-30.0 -180
-90° by pole 8
at the origin 10 -270°
-60.0 -360
100m 1 10 100 1k 10k 100k

frequency in hertz
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Third, Evaluate the Phase Boost at fc
0
ph_vout#a in degrees
-40.0
arg H(s) at 4 kHz
Plot1
-80.0
arg H(s)
-120
arg H(s) -175° 18
-160
+
0
-113° arg G(s)
-90.0
arg G(s)
p in unknown
Plot3
-180
+155° 11
-270
-360 Phase boost at fc
ϕm = 70°
0
-90.0 arg H(s)G(s)

p in unknown
Plot2
-180
-270
ϕm
-360 1
10 100 1k 10k 100k

frequency in hertz
arg H ( f c ) − 270° + BOOST − ϕm = −360°

BOOST = ϕm − arg H ( f c ) − 90° = 70° + 175 − 90 = 155°
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How do We Boost the Phase at fc?
The phase boost is created by combining zeros and poles
⎛ ω ⎞ ⎛ ω ⎞
⎜1 + j ⎟ ⎜1 + j ⎟
ω z1 ⎠ ω z1 ⎠
G ( jω ) = ⎝ arg G ( jω ) = boost = arg ⎝
⎛ ω ⎞ ⎛ ω ⎞
⎜⎜1 + j ⎟ ⎜⎜1 + j ⎟
⎝ ω p1 ⎟⎠ ⎝ ω p1 ⎟⎠
⎛ fc ⎞ ⎛ fc ⎞
arg G ( f c ) = arctan ⎜ ⎟ − arctan ⎜⎜ ⎟⎟
⎝ z1 ⎠
f f
⎝ p1 ⎠
Assume 1 zero placed at 705 Hz, 1 pole at 22 kHz and a 4-kHz crossover frequency:
⎛ 4k ⎞ ⎛ 4k ⎞
arg G ( 4 kHz ) = arctan ⎜ ⎟ − arctan ⎜ ⎟ = 80 − 10.3 ≈ 70°
⎝ 705 ⎠ ⎝ 22k ⎠
If poles and zeros are coincident, no phase boost!
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G100 Hz = 38 dB
Gain
40.0 360
|G(s)|
20.0 180
Gain at
fc = 21 dB 33
vdbout in db(volts)
p in unknown
plot1
0 0
fz = 705 Hz fp = 22 kHz
-20.0 -180
-270° 32
Phase boost
-40.0 -360
at fc = 71°
Phase
Arg G(s)
10 100 1k 10k 100k
frequency in hertz 4 kHz Type 2
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The type 1 configuration

No phase boost, pure integral term
Permanent phase lag of -270°
Ok if argH(fc) < -45° for a ϕm of 45°
C1
10n
1 2
Vout ( s ) 1 1
G (s) = = =
Vin ( s )
E1
R1 10k sR1C1 s
10k
1 ω0
4 Vout
ω p1 =
V1
R1C1
AC = 1
1 pole at the origin
Type 1
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Phase boost up to 90°
Ok if argH(fc) < -90°
C2
1 + sR2C1
G (s) = −
62pF
⎛ ⎡ C1C2 ⎤ ⎞
sR1 ( C1 + C2 ) ⎜⎜1 + sR2 ⎢
C1
⎥ ⎟⎟
R2
2nF
+
116k
1 2 4 ⎝ ⎣ 1
C C 2 ⎦⎠
E1
R1 10k If C2 << C1
10k
1 1 1
3 Vout
ω po = ω p1 = ω z1 =
V1
R1C1 R2C2 R2C1
AC = 1
1 zero
1 pole
Type 2
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Phase boost up to 180°
Ok if argH(fc) < -180°
sR2C1 + 1 sC3 ( R1 + R3 ) + 1
G (s) = −
⎛ C C ⎞ ( sR3C3 + 1)
C2
350pF sR1 ( C1 + C2 ) ⎜1 + sR2 1 2 ⎟
⎝ C1 + C2 ⎠
C1 R2
11nF 20k
1 2 4
If C2 << C1 and R3 << R1
C3 R3 E1 1 1 1
22nF 321 10k ω z1 = ωz2 = ω po =
5 R2C1 R1C3 R1C1
Vout
3
1 1
R1
10k ω p1 = ω p2 =
V1 R3C3 R2C2
AC = 1

2 zeros
2 poles
Type 3
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Finally, We Test the Open-Loop Gain
5. Given the necessary boost of 155°, we select a type-3 amplifier
6. A SPICE simulation can give us the whole picture!
rLf L1
10m 100u vout
a c Vout
7 3
d R10
11
PWM switch VM p 1m
Vin R11
10 X3
PWMVM 16 1
L = 100u
Fs = 100k C5
1mF
Buck stage
12 vout
GAIN
X1 C2
GAIN
K = 0.5
{C2}
R7 1 pole at the origin
{R3}
2
C1
{C1}
R2
{R2}
Rupper
10k 8
2 zeros at 500 Hz
13
5
C3
{C3} 2 poles at 50 kHz
LoL
1kH
1
Verr Rlower
CoL X2 10k
1kF V2
AMPSIMP 2.5
9
Vstim
AC = 1
Type 3
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Finally, We Test the Open-Loop Gain
An ac simulation gives us the open-loop Bode plot
Gain
80.0 360
T(s)
40.0 180
fc = 4 kHz
vdberr in db(volts)
p in unknown
plot1
0 0
-40.0 -180 15
ϕm = 70°
-80.0 -360 Phase 14
Arg T(s)
10 100 1k 10k 100k
frequency in hertz
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Agenda
Poles and zeros
Conclusion
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Type 2 with a TL431
Litterature examples use op amps to close the loop.
Reality differs as the TL431 is widely implemented.
How to convert a type 2 to a TL431 circuit?
K
R
K
TL431A R
A
2.5V
R
A A shunt regulator! A
K
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43
Type 2 with a TL431
A TL431 implements a two-loop configuration
FB signal
Rpullup FB D2
L1
MBR20100CT
2.2u
Vout
solution A Vdd
Rbias RLED Rupper
Gnd
fast slow
lane lane
C2 C3
1mF Czero 100uF
Vcc
X1
solution B TL431A
FB Rlower
FB signal
Rpulldown
Gnd
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Adding a Pole for a Type 2 Circuit
The pole is a simple capacitor on the collector
Rpullup
Vdd FB Vdd
FB
Rpulldown
Cpole Cpole Or on the
emitter
VFB ( s ) ⎛ sRupper C zero + 1 ⎞ ⎛ 1 ⎞ R pullup

G (s) = = −⎜
⎜ sRupper C zero ⎟⎟ ⎜⎜ 1 + sR pullup C pole ⎟⎟ CTR
Vout ( s ) ⎝ ⎠⎝ ⎠ RLED
1 1 R pullup 1
f po = fz = G= CTR fp =
2π Rupper Czero 2π Rupper Czero RLED 2π R pullup C pole
Pole at the origin Low frequency zero Mid-band gain High frequency pole
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The Type 2 Final Implementation
The LED resistor fixes the mid-band gain

Vout
RLED
Rupper
Vdd
1 3
U2A
Rpullup Czero
2
Cpole U2B X1 Rlower

TL431
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What TL431?
The TL431 is available under several grades
TL431AI, 2.495 V, ± 2.2% TA = -25 °C to +85 °C
TL431AC, 2.495 V, ± 1.6% TA = -25 °C to +85 °C
TL431BI, 2.495 V, ± 0.8% TA = -25 °C to +85 °C
• BV = 37 V, IK,max = 100 mA and IK,min = 1 mA
The TLV431 can regulate to a lower output

TLV431A, 1.24 V, ± 2% TA = -25 °C to +85 °C
TLV431B, 1.24 V, ± 1% TA = -25 °C to +85 °C
• BV = 18 V, IK,max = 20 mA and IK,min = 100 µA
NCP100 down to 0.9 V
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Agenda
Poles and zeros
Conclusion
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The Optocoupler is the Treator Here!
You need galvanic isolation between the prim. and the sec.
An optocoupler transmits light only, no electrical link
Creepage path
Silicone
LED dome
c a
Detector
Ic IF
500 µm
Clearance
Detector LED Luigi Galvani, 1737-1798
Italian physician and physicist
e k
Ic
CTR = × 100
IF
French
Current Transfer Ratio specimen
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49
The Internal Pole should be Known
The photons are collected by a collector-base area.

This area offers a large parasitic capacitance: opto pole!
Vdd
Vdd Vout
Rpullup RLED
Rpullup RLED
VFB
CTR C
VFB ( s ) R pullup CTR 1

=− If fp is above 5 times fc, its effect is negligible
Vout ( s ) RLED 1 + sR pullup C If fp is close to fc, phase margin degradation
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50
Assess the CTR Variations
CTR changes with the operating current!
Try to select collector bias currents around 2-5 mA
CTR between 0.63 and 1.25

Normalized to 1 (0 dB) Watch out for
0.63 gives –4 dB fc
crossover frequency
1.25 gives +2 dB
changes and phase margin
at CTR extremes!
SFH-615
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51
Changing the Pullup Affects the Pole Position
A low pullup resistor offers better bandwidth!
30 kHz 10 kHz
Rpullup = 1 kΩ Rpullup = 4.7 kΩ
Changing the bias point affects the CTR

CTR 5 kHz VFB ( s ) R pullup
=− CTR
Vout ( s ) RLED
Rpullup = 15 kΩ
If Rpullup = RLED, then |G0| = 0 dB…?
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52
Agenda
Poles and zeros
Conclusion
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53
Stabilizing a DCM Flyback Converter
We want to stabilize a 20 W DCM adapter
Vin = 85 to 265 Vrms
Vout = 12 V/1.7 A
Fsw = 60 kHz
Selected controller: NCP1216
1. Obtain a power stage open-loop Bode plot, H(s)

2. Look for gain and phase values at cross over
3. Compensate gain and build phase at cross over, G(s)
4. Run a loop gain analysis to check for margins, T(s)
5. Test transient responses in various conditions
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54
Capture a SPICE schematic with an averaged model
839mV
vc
a
PWM switch CM
389mV
duty-cycle
DC 6
X2x
XFMR D1A
RATIO = -166m mbr20200ctp vout
90.0V 12.0V
vout
2 3 4
Vin p -76.1V 12.6V
c
90
AC = 0 R10
0V
13 20m
X9
Rload
PWMCM L1 12.0V
V(errP)/3 > 1 ? 1 7.2
L = Lp {Lp}
Fs = 65k 1 : V(errP)/3 C5
8
Ri = 0.7 3mF
Se = Se B1
Voltage
Coming from FB
Look for the bias points values: Vout = 12 V, ok
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The feedback portion includes the optocoupler pole
parameters
Vdd
5
Vout=12
errP 5.00V
vout Ibridge=250u
2.52V
5
Rlower=2.5/Ibridge
X4 Rled
Rupper=(Vout-2.5)/Ibridge
Rpullup
POLE
{Rpullup} {Rled} Lp=450u
FP = pole
S+A
Se=100m
K
K=1 2.52V 11.7V

fc=1k
2.52V Verr pm=60 from
Rupper2
LoL {Rupper} Gfc=-24 Bode
1kH
err
18 11
pfc=-77
X7 G=10^(-Gfc/20)
Optocoupler
Cpole = 1/(6.28*pole*pullup) boost=pm-(pfc)-90
CTR = CTR pi=3.14159
9
K=tan((boost/2+45)*pi/180)
2.52V
14 Cpole2 Fzero=fc/k
CoL {Cpole}
10
Fpole=k*fc
1kF 10.7V Czero1 Rpullup=20k
0V
{Czero}
15 RLED=CTR*Rpullup/G
Vstim Czero=1/(2*pi*Fzero*Rupper)
2.49V
AC = 1 X10
TL431_G
Rlower2 Cpole=1/(2*pi*Fpole*Rpullup)
{Rlower} CTR=1.5
Pole=6k
Automated compensation
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Get the open-loop power stage transfer function, H(s)
60.0
30.0
Gain at 1 kHz
-22.7 dB
0
-30.0
1
-60.0
|H(s)|
180
Phase at 1 kHz
90.0
-79 °
0
-90.0
-180 argH(s) 2
10 100 1k 10k 100k
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57
Boost the gain by +22 dB, boost the phase at fc
4
80.0
GM
40.0
35 dB
0
-40.0
-80.0 |T(s)| Cross over

180
1 kHz
90.0
4
-90.0
Margin at 1 kHz
-180 argT(s) 60°
10 100 1k 10k 100k
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Test the response at both input levels, 90 and 265 Vrms
Sweep ESR values and check margins again
12.04 Vout(t)
Hi
12.00
line
6
4
11.96
11.92
100 Low
mV
line
11.88
200 mA to 2 A in 1 A/µs
3.00m 9.00m 15.0m 21.0m 27.0m
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59
Agenda
Poles and zeros
Conclusion
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60
Stabilizing a CCM Flyback Converter
We want to stabilize a 90 W CCM adapter
Vin = 85 to 265 Vrms
Vout = 19 V/4.8 A
Fsw = 60 kHz
Selected controller: NCP1230
1. Obtain a power stage open-loop Bode plot, H(s)

2. Look for gain and phase values at cross over
3. Compensate gain and build phase at cross over, G(s)
4. Run a loop gain analysis to check for margins, T(s)
5. Test transient responses in various conditions
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PWM switch CM
vc
467mV
a
duty-cycle
DC 6
X2x
XFMR D1A
RATIO = -0.25 mbr20200ctp vout
90.0V
vout
2 3 4 19.0V
-78.8V
p
Vin 19.7V
c
90
AC = 0 0V R10
13 14.4m
X9
19.0V Rload
PWMCM L1
1 4
L = Lp {Lp} 786mV V(errP)/3 > 1 ?
Fs = 65k 1 : V(errP)/3 C5
8
Ri = 0.25 6600u
Se = 0 B1
Voltage
Look for the bias points values: Vout = 19 V, ok

Vsetpoint < 1 V, enough margin on current sense
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parameters
Vdd
5
5.00V Vout=19
errP
2.36V vout Ibridge=250u
5
Rlower=2.5/Ibridge
X4 Rled Rupper=(Vout-2.5)/Ibridge
Rpullup
POLE {Rled} Lp=350u
{Rpullup}
FP = pole
S+A
Se=20k
K
K=1 2.36V 18.7V

fc=1k
2.36V Verr pm=60 from
Rupper2
LoL {Rupper} Gfc=-22 Bode
1kH
err pfc=-71
18 11
X8 G=10^(-Gfc/20)
Optocoupler
Fp = Pole
boost=pm-(pfc)-90
R7 CTR = CTR pi=3.14159
1 K=tan((boost/2+45)*pi/180)
2.36V
Fzero=fc/k
14 Cpole2
CoL {Cpole} 17.7V
Fpole=k*fc
9 10
0V
1kF Czero1 Rpullup=20k
15 2.49V
{Czero} RLED=CTR*Rpullup/G
Vstim Czero=1/(2*pi*Fzero*Rupper)
AC = 1 X10 Cpole=1/(2*pi*Fpole*Rpullup)
Rlower2
TL431_G CTR=1.5
{Rlower}
Pole=6k
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32.0
16.0
Gain at 1 kHz
-22 dB Sub harmonic
0
poles
-16.0
|H(s)|
ramp
-32.0
180
Phase at 1 kHz
90.0
-71 ° Inject ramp
compensation
0
-90.0
-180 argH(s)
6
10 100 1k 10k 100k
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64
The easiest way to damp the poles:
¾ Calculate the equivalent quality coefficient at Fsw/2
¾ Calculate the external ramp to make Q less than 1
1 1
Q= = =8
⎛ Se 1 ⎞ 3.14 × ( 0.5 − 0.46 )
π ⎜D' + − D⎟
⎝ Sn 2 ⎠
Sn ⎛ 1 ⎞ Vin Ri ⎛ 1 ⎞ 90 × 0.25 ⎛ 1 ⎞
Se = ⎜ − 0.5 + D ⎟ = ⎜ − 0.5 + D ⎟ = ⎜ − 0.5 + 0.46 ⎟ = 36 kV s
D'⎝π ⎠ Lp D ' ⎝ π ⎠ 320u × (1 − 0.46 ) ⎝ 3.14 ⎠
2.3 Vpp Se 36k

Mr = = = 51% Vin Ri
Rramp
S n 70k On-time slope
Lp
2.3
18 kΩ DRV
Rcurrent
S ramp = = 153 kV s
15u
CS Ri M S R 0.51× 70k × 18k
Rcurrent = r n ramp = = 4.1 k Ω
NCP1230 S ramp 153k
internal
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65
Boost the gain by +22 dB, boost the phase at fc
11
80.0
Cross over
40.0 1 kHz GM
20 dB
0
-40.0
10
-80.0
|T(s)|
180
90.0
-90.0
Margin at 1 kHz
-180 argT(s) 60° 11
10 100 1k 10k 100k
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Test the response at both input levels, 90 and 265 Vrms
Sweep ESR values and check margins again
19.11 Vout(t)
19.03
Hi
line
18.95 12
11
18.87
112 mV
Low
18.79
line
1.80m 5.40m 9.00m 12.6m 16.2m
time in seconds
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67
Agenda
Poles and zeros
Conclusion
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68
Testing a UC3843 Converter
A 19 V/3 A converter is built around an UC3843
The converter operates in CCM or DCM
T1
86H-6232
0.18 : 1 : 0.25
HV-bulk
R19 R3 R13
47k 47k 47k C2
10n D5
400V MBR20100 L2
2.2u
+
. . C5a C5b C7
IC4 Vout
KBU4K
D2 . 1.2mF
25V
1.2mF
25V
220uF
25V
MUR160
C11 R6
100p
Vref C13
6k Gnd
R17 2.2nF
IN
47k Type = Y1
1 CMP Ref 8 R1 D8 R8 R14

R7 330 1N4937 1k 4.7k
C4 10k
2 x 10mH 100uF
2 FB Vcc 7
L1
Schaffner RN122-1.5/02 400V M1

R12
3 CS DRV 6
SPP11N60S5 10k
Vref R16
R11 4 Rt GND 5 10 R18
10k 47k
C10
U1
470n X2
UC3843
U3B R10
56k
R23 R24
1Meg 1Meg
U3A C6
R5 100n
1k
R15 R6a R6b

85-260 Vac 4.7k 1 1
C12 C16 C15 C3 IC2 R9

220p 4.7nF 10nF 220uF TL431 10k
Gnd
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69
Full Load Leads to CCM Operation
simulated
CCM operation, Rload = 6.3 Ω
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70
Reduce the Load to Enter in DCM
simulated
DCM operation, Rload = 20 Ω
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71
From the Open-Loop Bode Plot, Compensate
The TL431 is tailored to pass a 1 kHz bandwidth
Vref Vout Calculate mid-band gain: +18 dB

R pullup CTR 4.7 k × 0.45
RLed Rupper RLED = 18
= = 266 Ω
66 kΩ 20
7.94
10
1 kΩ We place a zero at 300 Hz:
CTR
= 45% Czero 1 1
C zero = = = 8 nF
2π f zero Rupper 6.28 × 300 × 66k
Cpole Rpulldown
Rlower We place a pole at 3.3 kHz:
10 kΩ
1 1
C pole = = = 10 nF
2π f pole R pulldown 6.28 × 3.3k × 4.7 k
k factor method
“Switch-Mode Power Supplies: SPICE Simulations and Practical Designs”, McGraw-Hill
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72
Verify in the Lab. the Open-Loop Gain
Sweep extreme voltages and loads as well!
Simulated
CCM operation, Rload = 6.3 Ω, Vin = 150 Vdc
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Simulated
0 100 1k 10k 100
CCM operation, Rload = 6.3 Ω, Vin = 330 Vdc
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74
Simulated
DCM operation, Rload = 20 Ω, Vin = 330 Vdc
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75
As a Final Test, Step Load the Output
Good agreement between curves!
Vin = 150 V
Simulated CCM
2 to 3 A
1 A/µs
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76
As a final test, Step Load the Output
DCM operation at high line is also stable
Vin = 330 V
Simulated DCM
0.5 to 1 A
1 A/µs
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77
Conclusion
DC-DC loop compensation cannot be overlooked
It is important to understand the impact of phase margin
The crossover frequency affects the output impedance
Current mode CCM or DCM is ok with a TL431-based type 2
Make sure the optocoupler is characterized, watch the pole!
Use SPICE before going to the bench: NO trial and error!
Once the simulation is stable, build the prototype
Simulations and laboratory debug: the success recipe!
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For More Information
• View the extensive portfolio of power management products from ON

Semiconductor at www.onsemi.com
• View reference designs, design notes, and other material supporting

the design of highly efficient power supplies at
www.onsemi.com/powersupplies
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DC-DC Converters Feedback

Compensating for the converter shortcomings!

Input voltage Output voltage

Modulator - GPWM Vref Rlower

Loop gain |H(s)| -180° H(s) power stage

1 10 100 1k 10k 100k

180 80.0 T(s) phase phase

gain T(s) reaches 0 dB at a

 solving for N(s) = 0, the roots are called the zeros

 solving for D(s) = 0, the roots are called the poles

Vin Vout 20.0

AC = 1 10nF -60.0 |Vout(s)| -1 slope

30.0 cutoff 30.0 cutoff

+20 dB/decade LHPZ

1 10 100 1k 10k 100k 1Meg

Q=5 Q < 0.5 over damping

Q=1 Q = 0.5 critical damping

Q = 0.5 Fast response and no overshoot!

5.00u 15.0u 25.0u 35.0u 45.0u

90.0 40.0 Close the

f ( Cout , f c , ΔI out ) 4.94

 A DC-DC conv. combines an inductor and a capacitor

1 10 100 1k 10k 100k

 the closed-loop output impedance is dominated by Cout

 Let’s assume an output capacitor of 1 mF

Select a 1000-µF capacitor featuring less than a 40-mΩ ESR

 Compensate the converter for a 4 kHz fc

Compensated open-loop gain

10 100 1k 10k 100k

1.61m 2.42m 3.23m 4.05m 4.86m

Open-loop Bode plot of the power stage, H(s) Asc ,OL ( s )

Phase Arg H(s) @ fc

Phase Tailor G(s) to

10 100 1k 10k 100k

-20 dB per decade V1

at the origin 10 -270°

100m 1 10 100 1k 10k 100k

-360 Phase boost at fc

-90.0 arg H(s)G(s)

10 100 1k 10k 100k

arg H ( f c ) − 270° + BOOST − ϕm = −360°

 The type 1 configuration

1 pole at the origin

 The type 2 configuration

 The type 3 configuration

1 pole at the origin

VFB ( s ) ⎛ sRupper C zero + 1 ⎞ ⎛ 1 ⎞ R pullup

 The LED resistor fixes the mid-band gain

Cpole U2B X1 Rlower

 The TLV431 can regulate to a lower output

 The photons are collected by a collector-base area.

VFB ( s ) R pullup CTR 1

CTR between 0.63 and 1.25

Rpullup = 1 kΩ Rpullup = 4.7 kΩ

 Changing the bias point affects the CTR

1. Obtain a power stage open-loop Bode plot, H(s)

 Look for the bias points values: Vout = 12 V, ok

K=1 2.52V 11.7V

10 100 1k 10k 100k

-80.0 |T(s)| Cross over

1. Obtain a power stage open-loop Bode plot, H(s)

 Look for the bias points values: Vout = 19 V, ok

K=1 2.36V 18.7V

solving for N(s) = 0, the roots are called the zeros

solving for D(s) = 0, the roots are called the poles

A DC-DC conv. combines an inductor and a capacitor

the closed-loop output impedance is dominated by Cout

Let’s assume an output capacitor of 1 mF

Compensate the converter for a 4 kHz fc

The type 1 configuration

The type 2 configuration

The type 3 configuration

The LED resistor fixes the mid-band gain

The TLV431 can regulate to a lower output

The photons are collected by a collector-base area.

Changing the bias point affects the CTR

Look for the bias points values: Vout = 12 V, ok

Look for the bias points values: Vout = 19 V, ok

DCM operation at high line is also stable