M.tech I Sem Vlsi Technoly I Lab Record

PART-A
Front-end Environment
Block Diagram:
Page | 1
Logic Diagram:
Timing waveform:
EXPERIMENT-1
Page | 2
LOGIC GATES
AIM: To develop the source code for LOGIC GATES by using VHDL/VERILOG and
obtain the simulation, synthesis.
VHDL CODE FOR AND GATE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity andgate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
Cout : out STD_LOGIC);
end andgate;
architecture Behavioral of andgate is
begin
Cout<=a and b;
end Behavioral;
VERILOG CODE FOR AND GATE:

module and1(a,b,c);
input a,b;
output c;
assign c= a & b;
endmodule
Page | 3
Block Diagram:
Logic Diagram:
Timing waveform:
OR GATE
Page | 4
VHDL CODE FOR OR GATE:
library IEEE;
entity orgate is
b : in STD_LOGIC;
end orgate;
architecture Behavioral of orgate is
begin
Cout <= a or b;
end Behavioral;
VERILOG CODE FOR OR GATE:

module or2(a,b, c);
input a,b;
output c;
assign c = a | b;
endmodule
Block Diagram:
Page | 5
Logic Diagram:
Timing waveform:
NOT GATE
VHDL CODE FOR NOT GATE:

Page | 6
library IEEE;
entity notgate is
end notgate;
architecture Behavioral of notgate is
begin
Cout <= not a;
end Behavioral;
VERILOG CODE FOR NOT GATE:
module notga(a, b);

input a;
output b;
assign b = ~ a;
endmodule
Block Diagram:
Page | 7
Logic Diagram:
Timing waveform:
NAND GATE
Page | 8
VHDL CODE FOR NAND GATE:
library IEEE;
entity nandgate is
b : in STD_LOGIC;
end nandgate;
architecture Behavioral of nandgate is
begin
Cout <= a nand b;
end Behavioral;
VERILOG CODE FOR NAND GATE:
module nand2 (a,b,c);

input a,b;
output c;
wire p;
assign p=a&b;
assign c=~p;
endmodule
Block Diagram:
Page | 9
Logic Diagram:
Inputs Outpu Truth table

t
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
Timing waveform:
NOR GATE
Page | 10
VHDL CODE FOR NOR GATE:
library IEEE;
entity norgate is
b : in STD_LOGIC;
end norgate;
architecture Behavioral of norgate is
begin
Cout<= a nor b;
end Behavioral;
VERILOG CODE FOR NOR GATE:
module nor2(a,b, c);

input a,b;
output c;
wire p;
assign p=a|b;
assign c=~p;
endmodule
Block Diagram:
Page | 11
Logic Diagram:
Timing waveform:
XOR GATE
VHDL CODE FOR XOR GATE:
Page | 12
library IEEE;
entity xorgate is
b : in STD_LOGIC;
end xorgate;
architecture Behavioral of xorgate is
begin
Cout<= a xor b;
end Behavioral;
VERILOG CODE FOR XOR GATE:
module exorg(a,b,c);
input a,b;
output c;
wire s1,s2,s3,s4;
assign
s1=~a,
s2=~b,
s3= s1 & b,
s4= s2 & a, c= s3| s4;
endmodule
Block Diagram:
Page | 13
Logic Diagram:
Truth table:
Inputs Output
A B Y
0 0 1
0 1 0
1 0 0
1 1 1
Timing waveform:
XNOR GATE
Page | 14
VHDL CODE FOR XNOR GATE:
library IEEE;
entity xnorgate is
b : in STD_LOGIC;
end xnorgate;
architecture Behavioral of xnorgate is
begin
Cout<=a xnor b;
end Behavioral;
VERILOG CODE FOR XNOR GATE:
module exorg(a,b,c);
input a,b;
output c;
wire s1,s2,s3,s4;
assign
s1=~a,
s2=~b,
s3= s1 & b,
s4= s2 & a,
c= ~(s3| s4);
endmodule
SYNTHESIS REPORT:
Started : "Check Syntax for andgate".
Page | 15
==================================================================
==== ==
* HDL Compilation
==================================================================
=======
Compiling vhdl file "C:/Xilinx91i/andgate/andgate.vhd" in Library work.
Entity <andgate> compiled.
Entity <andgate> (Architecture <Behavioral>) compiled.
Process "Check Syntax" completed successfully
Reading design: andgate.prj
==================================================================
=======
* HDL Compilation *
==================================================================
=======
Compiling vhdl file "C:/Xilinx91i/andgate/andgate.vhd" in Library work.
Architecture behavioral of Entity andgate is up to date.
==================================================================
=======
* Design Hierarchy Analysis *
==================================================================
=======
Analyzing hierarchy for entity <andgate> in library <work> (architecture <behavioral>).
==================================================================
=======
* HDL Analysis *
==================================================================
=======
Analyzing Entity <andgate> in library <work> (Architecture <behavioral>).
Entity <andgate> analyzed. Unit <andgate> generated.
==================================================================
=======
Page | 16
* HDL Synthesis *
==================================================================
=======
Performing bidirectional port resolution...
Synthesizing Unit <andgate>.
Related source file is "C:/Xilinx91i/andgate/andgate.vhd".
Unit <andgate> synthesized.
HDL Synthesis Report
Found no macro
==================================================================
=======
* Advanced HDL Synthesis *
==================================================================
=======
Loading device for application Rf_Device from file '3s250e.nph' in environment C:\Xilinx91i.
==================================================================
=======
Advanced HDL Synthesis Report
Found no macro
==================================================================
=======
* Low Level Synthesis *
==================================================================
=======
Optimizing unit <andgate> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block andgate, actual ratio is 0.
Final Macro Processing ...
==================================================================
=======
Page | 17
Final Register Report
Found no macro
==================================================================
=======
* Partition Report *
==================================================================
=======
Partition Implementation Status
No Partitions were found in this design.
==================================================================
=======
* Final Report *
==================================================================
=======
Clock Information:
No clock signals found in this design
Asynchronous Control Signals Information:
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -4
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 6.209ns
==================================================================
=======
WARNING:ProjectMgmt - "C:/Xilinx91i/andgate/andgate.ngc" line 0 duplicate design unit:

'Module|andgate'
Process "Synthesize" completed successfully
Reading design: ma.prj

Page | 18
==================================================================
=======
* HDL Compilation *
==================================================================
=======
Compiling vhdl file "C:/Xilinx91i/sri/ma.vhd" in Library work.
Architecture behavioral of Entity ma is up to date.
==================================================================
=======
==================================================================
=======
Analyzing hierarchy for entity <ma> in library <work> (architecture <behavioral>).
==================================================================
=======
* HDL Analysis *
==================================================================
=======
Analyzing Entity <ma> in library <work> (Architecture <behavioral>).
Entity <ma> analyzed. Unit <ma> generated.
==================================================================
=======
* HDL Synthesis *
==================================================================
=======
Synthesizing Unit <ma>.
Related source file is "C:/Xilinx91i/sri/ma.vhd".
Found 1-bit xor2 for signal <c>.
Unit <ma> synthesized.
==================================================================
=======
Page | 19
Macro Statistics
# Xors :1
1-bit xor2 :1
==================================================================
=======
==================================================================
=======
Loading device for application Rf_Device from file '3s50.nph' in environment C:\Xilinx91i.
==================================================================
=======
Macro Statistics
# Xors :1
1-bit xor2 :1
==================================================================
=======
==================================================================
=======
Optimizing unit <ma> ...
Found area constraint ratio of 100 (+ 5) on block ma, actual ratio is 0.
==================================================================
=======
Found no macro
Page | 20
==================================================================
=======
==================================================================
=======
==================================================================
=======
* Final Report *
==================================================================
=======
Clock Information:
Timing Summary:
Speed Grade: -4
Started : "Creating Tbw file".
Entity <ma> compiled.
Entity <ma> (Architecture <behavioral>) compiled.
running Fuse ...
Page | 21
Compiling vhdl file "C:/Xilinx91i/sri/m.vhw" in Library work.
Entity <m> compiled.
Entity <m> (Architecture <testbench_arch>) compiled.
Parsing "m_beh.prj": 0.23
Codegen work/ma: 0.00
Codegen work/ma/Behavioral: 0.97
Codegen work/m: 0.00
Codegen work/m/testbench_arch: 1.13
Building m_isim_beh.exe
Running ISim simulation engine ...
This is a Full version of ISE Simulator.
Simulator is doing circuit initialization process.
Finished circuit initialization process.
RESULT: Simulated the VHDL and VERILOG codes for LOGIC GATES and
obtained the timing diagrams.
Logic Diagram:
Page | 22
Block Diagram:
Timing Waveform:
EXPERIMENT-2
COUNTERS
Page | 23
AIM: To develop the source code for COUNTERS by using VHDL/VERILOG and
VHDL CODE FOR SYNCHRONOUS COUNTER:
library IEEE;
entity syncount is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
e : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (3 downto 0));
end syncount;
architecture Behavioral of syncount is
signal count : std_logic_vector(3 downto 0);
begin
process(clk,rst)
begin
if rst='0' then
count <="1111";
elsif(clk'event and clk='1') then
if(e='1') then
count <= count-1;
else
count<=count;
end if;
Page | 24
end if;
end process;
q<=count;
end Behavioral;
VERILOG CODE FOR SYNCHRONOUS COUNTER:
module counter (out,clk);
output [4:1] out;
input clk;
reg [4:1] out;
initial
begin
out=1'd14;
end
always @(posedge clk)
out <= out -1;
endmodule
SYNTHESIS REPORT:
Started : "Check Syntax for syncount".
==================================================================
=======
* HDL Compilation *
==================================================================
=======
Compiling vhdl file "C:/Xilinx91i/syncount/syncount.vhd" in Library work.
Entity <syncount> compiled.
Entity <syncount> (Architecture <behavioral>) compiled.
Page | 25
Reading design: syncount.prj
==================================================================
=======
* HDL Compilation *
==================================================================
=======
Compiling vhdl file "C:/Xilinx91i/syncount/syncount.vhd" in Library work.
Architecture behavioral of Entity syncount is up to date.
==================================================================
=======
==================================================================
=======
Analyzing hierarchy for entity <syncount> in library <work> (architecture <behavioral>).
==================================================================
=======
* HDL Analysis *
==================================================================
=======
Analyzing Entity <syncount> in library <work> (Architecture <behavioral>).
Entity <syncount> analyzed. Unit <syncount> generated.
==================================================================
=======
* HDL Synthesis *
==================================================================
=======
Synthesizing Unit <syncount>.
Related source file is "C:/Xilinx91i/syncount/syncount.vhd".
Found 4-bit down counter for signal <count>.
Summary:
Page | 26
inferred 1 Counter(s).
Unit <syncount> synthesized.
==================================================================
=======
Macro Statistics
# Counters :1
4-bit down counter :1
==================================================================
=======
==================================================================
=======
Loading device for application Rf_Device from file '3s250e.nph' in environment C:\Xilinx91i.
==================================================================
=======
Macro Statistics
# Counters :1
4-bit down counter :1
==================================================================
=======
Optimizing unit <syncount> ...
Found area constraint ratio of 100 (+ 5) on block syncount, actual ratio is 0.
==================================================================
=======

Page | 27
Macro Statistics
# Registers :4
Flip-Flops :4
==================================================================
=======
==================================================================
==================================================================
=======
* Final Report *
==================================================================
=======
Clock Information:
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP |4 |
-----------------------------------+------------------------+-------+
-----------------------------------+------------------------+-------+
Control Signal | Buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
rst_inv(rst_inv1_INV_0:O) | NONE(count_3) |4 |
-----------------------------------+------------------------+-------+
Timing Summary:
Speed Grade: -4
Minimum period: 2.656ns (Maximum Frequency: 376.506MHz)
Minimum input arrival time before clock: 2.360ns

Page | 28
Maximum output required time after clock: 4.496ns
Maximum combinational path delay: No path found
==================================================================
=======
running Fuse ...
Logic Diagram:
Page | 29
Block Diagram:
Timing Waveforms:
ASYNCHRONOUS COUNTER
Page | 30
VHDL CODE FOR ASYNCHRONOUS COUNTER :
library IEEE;
entity asycount is
rst : in STD_LOGIC;
e : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (3 downto 0));
end asycount;
architecture Behavioral of asycount is
signal count:std_logic_vector(3 downto 0);
begin
process(clk,rst)
begin
if(e='1') then
count <= count+1;
else
count <= count;
end if;
end process;
q <= count;
end Behavioral;
VERILOG CODE:
module counter (out,clk);
output [4:1] out;

Page | 31
input clk;
reg [4:1] out;
initial
begin
out=0'd0;
end
always @(posedge clk)
out <= out -1;
endmodule
SYNTHESIS REPORT:
Started : "Check Syntax for asycount".
=============================================================
============
* HDL Compilation *
=============================================================
============
Compiling vhdl file "C:/Xilinx91i/asycount/asycount.vhd" in Library work.
Entity <asycount> compiled.
Entity <asycount> (Architecture <Behavioral>) compiled.
Reading design: asycount.prj
=============================================================
============
* HDL Compilation *
=============================================================
============
Compiling vhdl file "C:/Xilinx91i/asycount/asycount.vhd" in Library work.
Architecture behavioral of Entity asycount is up to date.

Page | 32
=============================================================
============
=============================================================
============
Analyzing hierarchy for entity <asycount> in library <work> (architecture

<behavioral>).
=============================================================
============
* HDL Analysis *
=============================================================
============
Analyzing Entity <asycount> in library <work> (Architecture <behavioral>).
Entity <asycount> analyzed. Unit <asycount> generated.
=============================================================
============
* HDL Synthesis *
=============================================================
============
Synthesizing Unit <asycount>.
Related source file is "C:/Xilinx91i/asycount/asycount.vhd".
Found 4-bit adder for signal <count$add0000> created at line 43.
Summary:
inferred 1 Adder/Subtractor(s).
Unit <asycount> synthesized.
=============================================================
============
Macro Statistics
Page | 33
# Adders/Subtractors :1
4-bit adder :1
# Latches :1
4-bit latch :1
=============================================================
============
=============================================================
============
Loading device for application Rf_Device from file '3s250e.nph' in environment

C:\Xilinx91i.
=============================================================
============
Macro Statistics
4-bit adder :1
# Latches :1
4-bit latch :1
=============================================================
============
=============================================================
============
Optimizing unit <asycount> ...
Found area constraint ratio of 100 (+ 5) on block asycount, actual ratio is 0.
Page | 34
=============================================================
============
Found no macro
=============================================================
============
=============================================================
============
=============================================================
============
* Final Report *
=============================================================
============
Clock Information:
-----------------------------------+------------------------+-------+
-----------------------------------+------------------------+-------+
e | BUFGP |4 |
-----------------------------------+------------------------+-------+
Timing Summary:
Speed Grade: -4
Minimum period: 2.741ns (Maximum Frequency: 364.830MHz)

Page | 35
=============================================================
============
running Fuse ...
RESULT: Simulated the VHDL and VERILOG codes for COUNTERS and obtained
the timing diagrams.
Page | 36
Block Diagram:
State Diagram:
Page | 37
Timing Waveform:
EXPERIMENT-3
MOORE FSM
AIM: To develop the source code for MOORE FSM by using VHDL/VERILOG
and obtain the simulation, synthesis.
VHDL CODE FOR MOORE FSM:
library IEEE;
Page | 38
entity moore is
Port ( x : in STD_LOGIC;
rst : in STD_LOGIC;
clk : in STD_LOGIC;
z : out STD_LOGIC);
end moore;
architecture Behavioral of moore is
type state is (s0,s1,s2,s3);
signal y:state:= s0;
begin
process(clk)
begin
if (rst='1')then
y<=s0;
else
case y is
when s0=>
if (x='1')then
y<=s1;
else y<=s0;
end if;
when s1=>
if(x='0')then
y<=s2;
Page | 39
else
y<=s1;
end if;
when s2=>
if(x='1')then
y<=s3;
else
y<=s0;
end if;
when s3=>
if(x='1')then
y<=s1;
else
y<=s2;
end if;
when others=>
y<=s0;
end case;
end if;
end if;
end process;
z<=1 when y=s3 else 0;
end Behavioral;
VERILOG CODE FOR MOORE FSM:
module vmo1(clk, x, z);
input clk;
Page | 40
input x;
output z;
reg [1:0] state;
parameter [1:0] zero =2'b00,
one=2'b01,
two=2'b10,
three=2'b11;
assign z=state[1] & state[0];
always@(posedge clk)
case(state)
zero:if(x==0)
state<=zero;
else
state<=one;
one:if(x==0)
state<=two;
else
state<=one;
two:if(x==0)
state<=zero;
else
state<=three;
three:if(x==0)
state<=two;
else
state<=one;
default:state<=zero;
Page | 41
endcase
endmodule
SYNTHESIS REPORT:
Started : "Check Syntax for moore".
=============================================================
============
* HDL Compilation *
=============================================================
============
Compiling vhdl file "C:/Xilinx91i/moore/moore.vhd" in Library work.
Entity <moore> compiled.
Entity <moore> (Architecture <behavioral>) compiled.
Reading design: moore.prj
=============================================================
============
* HDL Compilation *
=============================================================
============
Compiling vhdl file "C:/Xilinx91i/moore/moore.vhd" in Library work.
Architecture behavioral of Entity moore is up to date.
=============================================================
============
=============================================================
============
Analyzing hierarchy for entity <moore> in library <work> (architecture

<behavioral>).
Page | 42
=============================================================
============
* HDL Analysis *
=============================================================
============
Analyzing Entity <moore> in library <work> (Architecture <behavioral>).
rst, y, x.
Entity <moore> analyzed. Unit <moore> generated.
=============================================================
============
* HDL Synthesis *
=============================================================
============
Synthesizing Unit <moore>.
Related source file is "C:/Xilinx91i/moore/moore.vhd".
Using one-hot encoding for signal <y>.
Unit <moore> synthesized.
=============================================================
============
Found no macro
=============================================================
============
=============================================================
============

C:\Xilinx91i.
Page | 43
=============================================================
============
Found no macro
=============================================================
============
=============================================================
============
Optimizing unit <moore> ...
Found area constraint ratio of 100 (+ 5) on block moore, actual ratio is 0.
=============================================================
============
Found no macro
=============================================================
============
=============================================================
============
=============================================================
============
* Final Report *
=============================================================
============
Page | 44
Clock Information:
Timing Summary:
Speed Grade: -4
=============================================================
============
running Fuse ...
Page | 45
RESULT: Simulated the VHDL and VERILOG codes for MOORE FSM and
Block Diagram:
State Diagram:
Page | 46
Timing Waveforms:
EXPERIMENT-4
FINITE STATE MACHINE
AIM: To develop the source code for MEALY FSM by using VHDL/VERILOG and
VHDL CODE FOR MEALY FSM:
library IEEE;
Page | 47
entity mealy is
Port ( x : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
z : out STD_LOGIC);
end mealy;
architecture Behavioral of mealy is
type state is (s0,s1,s2);
signal y: state:=s0;
begin
process(clk,rst)
begin
if(rst='1') then
y<=s0;
elsif(clk='1' and clk'event) then
case y is
when s0=>
if (x='1') then
y<=s1;
else
y<=s0;
end if;
when s1=>
if (x='1') then
Page | 48
y<=s1;
else
y<=s2;
end if;
when s2=>
if (x='1') then
y<=s1;
else
y<=s0;
end if;
when others =>y<=s0;
end case;
end if ;
end process;
z<=1 when(y=s2 and x=1)else0;
end Behavioral;
VERILOG CODE FOR MEALY FSM:
module vmealy1(clk, x, z);
input clk;
input x;
output z;
reg [1:0] state;
parameter [1:0] zero=2'b00,
one=2'b01,
two=2'b10;
Page | 49
assign z=x&state[1];
always@(posedge clk)
case(state)
zero:if(x==0)
state<=zero;
else
state<=one;
one:if(x==0)
state<=two;
else
state<=one;
two:if(x==0)
state<=zero;
else
state<=one;
default:state<=zero;
endcase
endmodule
SYNTHESIS REPORT:
Started : "Check Syntax for mealy".
=============================================================
============
* HDL Compilation *
=============================================================
============
Compiling vhdl file "C:/Xilinx91i/mealy/mealy.vhd" in Library work.
Entity <mealy> compiled.

Page | 50
Entity <mealy> (Architecture <behavioral>) compiled.
Reading design: mealy.prj
=============================================================
============
* HDL Compilation *
=============================================================
============
Compiling vhdl file "C:/Xilinx91i/mealy/mealy.vhd" in Library work.
Architecture behavioral of Entity mealy is up to date.
=============================================================
============
=============================================================
============
Analyzing hierarchy for entity <mealy> in library <work> (architecture

<behavioral>).
=============================================================
============
* HDL Analysis *
=============================================================
============
Analyzing Entity <mealy> in library <work> (Architecture <behavioral>).
Entity <mealy> analyzed. Unit <mealy> generated.
=============================================================
============
* HDL Synthesis *
=============================================================
============
Page | 51
Synthesizing Unit <mealy>.
Related source file is "C:/Xilinx91i/mealy/mealy.vhd".
INFO:Xst:2117 - HDL ADVISOR - Mux Selector <y> of Case statement line 46 was
re-encoded using one-hot encoding. The case statement will be optimized (default
statement optimization), but this optimization may lead to design initialization
problems. To ensure the design works safely, you can:
- add an 'INIT' attribute on signal <y> (optimization is then done without any
risk)
- use the attribute 'signal_encoding user' to avoid onehot optimization
- use the attribute 'safe_implementation yes' to force XST to perform a safe

(but less efficient) optimization
Using one-hot encoding for signal <y>.
Found 3-bit register for signal <y>.
Unit <mealy> synthesized.
=============================================================
============
Macro Statistics
# Registers :1
3-bit register :1
=============================================================
============
=============================================================
============

C:\Xilinx91i.
=============================================================
============
Macro Statistics
Page | 52
# Registers :3
Flip-Flops :3
=============================================================
============
=============================================================
============
Optimizing unit <mealy> ...
Found area constraint ratio of 100 (+ 5) on block mealy, actual ratio is 0.
=============================================================
============
Found no macro
=============================================================
============
=============================================================
============
=============================================================
============
* Final Report *
=============================================================
============
Clock Information:

Page | 53
Timing Summary:
Speed Grade: -4
=============================================================
============
running Fuse ...
Page | 54
RESULT: Simulated the VHDL and VERILOG codes for MEALY FSM and
Block Diagram:
Timing Waveform:
Page | 55
EXPERIMENT-5
MEMORIES
AIM: To develop the source code for MEMORIES by using VHDL/VERILOG and
VHDL CODE FOR RAM:
library IEEE;
Page | 56
entity ram is
we : in STD_LOGIC;
a : in STD_LOGIC_VECTOR (4 downto 0);
di : in STD_LOGIC_VECTOR (3 downto 0);
do : out STD_LOGIC_VECTOR (3 downto 0));
end ram;
architecture Behavioral of ram is
type ram_type is array(31 downto 0) of std_logic_vector(3 downto 0);
signal RAM:ram_type;
begin
process (clk)
begin
if(clk'event and clk='1') then
if(we='1')then
RAM(conv_integer(a))<=di;
end if;
end if;
end process;
do<=RAM(conv_integer(a));
end Behavioral;
VERILOG CODE FOR RAM:
module vram1(clk, we, a, di, do);
input clk;
input we;
Page | 57
input [4:0] a;
input [3:0] di;
output [3:0] do;
reg [3:0] ram [31:0];
always @ (posedge clk)
begin
if (we)
ram[a] <= di;
end
assign do= ram[a];
endmodule
SYNTHESIS REPORT:
Started : "Check Syntax for ram".
=============================================================
============
* HDL Compilation *
=============================================================
============
Compiling vhdl file "C:/Xilinx91i/ram/ram.vhd" in Library work.
Entity <ram> compiled.
Entity <ram> (Architecture <behavioral>) compiled.
Reading design: ram.prj
=============================================================
============
* HDL Compilation *
Page | 58
=============================================================
============
Compiling vhdl file "C:/Xilinx91i/ram/ram.vhd" in Library work.
Architecture behavioral of Entity ram is up to date.
=============================================================
============
=============================================================
============
Analyzing hierarchy for entity <ram> in library <work> (architecture <behavioral>).
=============================================================
============
* HDL Analysis *
=============================================================
============
Analyzing Entity <ram> in library <work> (Architecture <behavioral>).
Entity <ram> analyzed. Unit <ram> generated.
=============================================================
============
* HDL Synthesis *
=============================================================
============
Synthesizing Unit <ram>.
Related source file is "C:/Xilinx91i/ram/ram.vhd".
Found 32x4-bit single-port RAM <Mram_RAM> for signal <RAM>.
Summary:
inferred 1 RAM(s).
Unit <ram> synthesized.
Page | 59
=============================================================
============
Macro Statistics
# RAMs :1
32x4-bit single-port RAM :1
=============================================================
============
=============================================================
============

C:\Xilinx91i.
INFO:Xst:2452 - Unit <ram> : The small RAM <Mram_RAM> will be implemented

on LUTs in order to maximize performance and save block RAM resources. If you
want to force its implementation on block, use option/constraint ram_style.
-----------------------------------------------------------------------
| ram_type | Distributed | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 32-word x 4-bit | |
| clkA | connected to signal <clk> | rise |
| weA | connected to signal <we> | high |
| addrA | connected to signal <a> | |
| diA | connected to signal <di> | |
| doA | connected to signal <do> | |
-----------------------------------------------------------------------
=============================================================
============

Page | 60
Macro Statistics
# RAMs :1
32x4-bit single-port distributed RAM :1
=============================================================
============
=============================================================
============
Optimizing unit <ram> ...
Found area constraint ratio of 100 (+ 5) on block ram, actual ratio is 0.
=============================================================
============
=============================================================
============
=============================================================
============
=============================================================
============
* Final Report *
=============================================================
============
Clock Information:
-----------------------------------+------------------------+-------+

Page | 61
-----------------------------------+------------------------+-------+
clk | BUFGP |4 |
Timing Summary:
Speed Grade: -4
=============================================================
============
running Fuse ...
Page | 62
RESULT: Simulated the VHDL and VERILOG codes for RAM and obtained the
timing diagrams.
Block Diagram:
Timing Waveforms:
Page | 63
EXPERIMENT-6
ARITHMETIC AND LOGIC UNIT
AIM: To develop the source code for ALU by using VHDL/VERILOG and obtain
the simulation, synthesis.
VHDL CODE FOR 16-BIT ALU:
library IEEE;
entity alu is
Port ( a : in STD_LOGIC_VECTOR (15 downto 0);
b : in STD_LOGIC_VECTOR (15 downto 0);
Page | 64
sel : in STD_LOGIC_VECTOR (3 downto 0);
cin : in STD_LOGIC;
y : out STD_LOGIC_VECTOR (15 downto 0));
end alu;
architecture Behavioral of alu is
signal arith,logic:std_logic_vector(15 downto 0);
begin
with sel(2 downto 0) select
arith<= a when "000",
a+1 when "001",
a-1 when"010",
b when "011",
b+1 when "100",
b-1 when "101",
Page | 65
Page | 66
a+b when "110",
a+b+cin when others;
with sel (2 downto 0) select
logic<= not a when "000",
not b when "001",
a and b when"010",
a or b when "011",
a nand b when "100",
a nor b when "101",
a xor b when "110",
not(a xor b) when others;
with sel(3) select
y<= arith when'0' ,
logic when others;
end Behavioral;
VERILOG CODE FOR 16-BIT ALU:
module valu1(a, b, sel, f);
input [15:0] a;
input [15:0] b;
input [2:0] sel;
output [15:0] f;
reg[15:0]f;
always @ (sel or a or b)
case(sel)
3'b000:f=5'b00000;
Page | 67
3'b00:f=b-a;
2:f=a-b;
3:f=a+b;
4:f=a^b;
5:f=a|b;
6:f=a&b;
7:f=15'b11111;
endcase
endmodule
SYNTHESIS REPORT:
Started : "Check Syntax for alu".
=============================================================
============
* HDL Compilation *
=============================================================
============
Compiling vhdl file "C:/Xilinx91i/balu/alu.vhd" in Library work.
Entity <alu> compiled.
Entity <alu> (Architecture <Behavioral>) compiled.
Reading design: alu.prj
=============================================================
============
* HDL Compilation *
=============================================================
============
Compiling vhdl file "C:/Xilinx91i/balu/alu.vhd" in Library work.
Architecture behavioral of Entity alu is up to date.

Page | 68
=============================================================
============
=============================================================
============
Analyzing hierarchy for entity <alu> in library <work> (architecture <behavioral>).
=============================================================
============
* HDL Analysis *
=============================================================
============
Analyzing Entity <alu> in library <work> (Architecture <behavioral>).
Entity <alu> analyzed. Unit <alu> generated.
=============================================================
============
* HDL Synthesis *
=============================================================
============
Synthesizing Unit <alu>.
Related source file is "C:/Xilinx91i/balu/alu.vhd".
WARNING:Xst - Property "use_dsp48" is not applicable for this technology.
Found 8-bit 8-to-1 multiplexer for signal <arith>.
Found 8-bit adder for signal <arith$addsub0000> created at line 41.
Found 8-bit subtractor for signal <arith$addsub0001> created at line 41.
Page | 69
Found 8-bit subtractor for signal <arith$addsub0003> created at line 41.
Found 8-bit adder carry in for signal <arith$addsub0005> created at line 41.
Found 8-bit 8-to-1 multiplexer for signal <logic>.
Found 8-bit xor2 for signal <logic$xor0000> created at line 50.
Summary:
inferred 6 Adder/Subtractor(s).
inferred 16 Multiplexer(s).
Unit <alu> synthesized.
=============================================================
============
Macro Statistics
8-bit adder :3
8-bit adder carry in :1
8-bit subtractor :2
# Multiplexers :2
8-bit 8-to-1 multiplexer :2
# Xors :1
8-bit xor2 :1
=============================================================
============
=============================================================
============

C:\Xilinx91i.
Page | 70
=============================================================
============
Macro Statistics
8-bit adder :3
8-bit adder carry in :1
8-bit subtractor :2
# Multiplexers :2
8-bit 8-to-1 multiplexer :2
# Xors :1
8-bit xor2 :1
=============================================================
============
=============================================================
============
Optimizing unit <alu> ...
Found area constraint ratio of 100 (+ 5) on block alu, actual ratio is 4.
=============================================================
============
Found no macro
=============================================================
============
Page | 71
=============================================================
============
=============================================================
============
* Final Report *
=============================================================
============
Clock Information:
Timing Summary:
Speed Grade: -4
=============================================================
============
running Fuse ...
Page | 72
RESULT: Simulated the VHDL and VERILOG codes for ARTHIMETIC AND
LOGIC UNIT and obtained the timing diagrams.
Block Diagram:
Page | 73
Logic Diagram:
Timing Waveforms:
EXPERIMENT-7
PRIORITY ENCODER
Page | 74
AIM: To develop the source code for PRIORITY ENCODER by using VHDL/
VERILOG and obtain the simulation, synthesis.
VHDL CODE FOR PRIORITY ENCODER:
library IEEE;
entity encode1 is
Port ( din : in STD_LOGIC_VECTOR (7 downto 0);
dout : out STD_LOGIC_VECTOR (2 downto 0));
end encode1;
architecture Behavioral of encode1 is
begin
pri_enc : process (din) is
begin
if (din(7)='1') then
dout <= "000";
elsif (din(6)='1') then
dout <= "001";
dout <= "010";
dout <= "011";
dout <= "100";
dout <= "101";
Page | 75
dout <= "110";
dout <= "111";
end if;
end process pri_enc;
end Behavioral;
VERILOG CODE FOR PRIORITY ENCODER:
module pri_enc(dout, din);
output [2:0] dout;
input [7:0] din ;
assign dout = (din[7] ==1'b1 ) ? 3'b111:
(din[6] ==1'b1 ) ? 3'b110:
(din[5] ==1'b1 ) ? 3'b101:
(din[4] ==1'b1) ? 3'b100:
(din[3] ==1'b1) ? 3'b011:
(din[2] ==1'b1) ? 3'b010:
(din[1] ==1'b1) ? 3'b001: 3'b000;
endmodule
SYNTHESIS REPORT:
Started : "Check Syntax for encode1".
==================================================================
=======
* HDL Compilation *
==================================================================
=======
Compiling vhdl file "C:/Documents and
Settings/Student/Desktop/lavanya/priority/encode1.vhd" in Library work.
Entity <encode1> compiled.
Page | 76
Entity <encode1> (Architecture <behavioral>) compiled.
Reading design: encode1.prj
==================================================================
=======
* HDL Compilation *
==================================================================
=======
Architecture behavioral of Entity encode1 is up to date.
==================================================================
=======
==================================================================
=======
Analyzing hierarchy for entity <encode1> in library <work> (architecture <behavioral>).
==================================================================
=======
* HDL Analysis *
==================================================================
=======
Analyzing Entity <encode1> in library <work> (Architecture <behavioral>).
Entity <encode1> analyzed. Unit <encode1> generated.
==================================================================
=======
* HDL Synthesis *
==================================================================
=======
Synthesizing Unit <encode1>.

Related source file is "C:/Documents and
Settings/Student/Desktop/lavanya/priority/encode1.vhd".
WARNING:Xst:737 - Found 3-bit latch for signal <dout>. Latches may be generated from
incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD
designs, as they may lead to timing problems.
Page | 77
Unit <encode1> synthesized.
==================================================================
=======
Macro Statistics
# Latches :1
3-bit latch :1
==================================================================
=======
==================================================================
=======
==================================================================
=======
Loading device for application Rf_Device from file '3s200.nph' in environment

C:\Xilinx\10.1\ISE.
==================================================================
=======
Macro Statistics
# Latches :1
3-bit latch :1
==================================================================
=======
==================================================================
=======
==================================================================
=======
Optimizing unit <encode1> ...

Found area constraint ratio of 100 (+ 5) on block enco1, actual ratio is 0.
Page | 78
==================================================================
=======
Found no macro
==================================================================
=======
==================================================================
=======
==================================================================
=======

-------------------------------
-------------------------------
==================================================================
=======
* Final Report *
==================================================================
=======
Clock Information:
------------------
-----------------------------------+------------------------+-------+
-----------------------------------+------------------------+-------+
din<0> | BUFGP |3 |
-----------------------------------+------------------------+-------+

----------------------------------------
-----------------------------------+------------------------+-------+
-----------------------------------+------------------------+-------+
dout_0__or0000(dout_0__or0000:O) | NONE(dout_0) |1 |
dout_0__or0001(dout_0__or0001_f5:O)| NONE(dout_0) |1 |
dout_1__and0000(dout_1__and00001:O)| NONE(dout_1) |1 |
Page | 79
-----------------------------------+------------------------+-------+
Timing Summary:
---------------
Speed Grade: -4

==================================================================
=======
Process "Synthesis" completed successfully
Started : "Launching RTL Schematic Viewer for encode1.ngr".

This is a Full version of ISE Simulator(ISim).
Started : "Check Syntax for encode1".
==================================================================
=======
* HDL Compilation *
==================================================================
=======
Entity <encode1> compiled.
Entity <encode1> (Architecture <behavioral>) compiled.
Reading design: encode1.prj
==================================================================
=======
* HDL Compilation *
==================================================================
=======
Architecture behavioral of Entity encode1 is up to date.
Page | 80
==================================================================
=======
==================================================================
=======
Analyzing hierarchy for entity <encode1> in library <work> (architecture <behavioral>).
==================================================================
=======
* HDL Analysis *
==================================================================
=======
Analyzing Entity <encode1> in library <work> (Architecture <behavioral>).
Entity <encode1> analyzed. Unit <encode1> generated.
==================================================================
=======
* HDL Synthesis *
==================================================================
=======
Synthesizing Unit <encode1>.

Related source file is "C:/Documents and
Settings/Student/Desktop/lavanya/priority/encode1.vhd".
WARNING:Xst:737 - Found 3-bit latch for signal <dout>. Latches may be generated from
incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD
designs, as they may lead to timing problems.
Unit <encode1> synthesized.
==================================================================
=======
Macro Statistics
# Latches :1
3-bit latch :1
==================================================================
=======
Page | 81
==================================================================
=======
==================================================================
=======
Loading device for application Rf_Device from file '3s200.nph' in environment

C:\Xilinx\10.1\ISE.
==================================================================
=======
Macro Statistics
# Latches :1
3-bit latch :1
==================================================================
=======
==================================================================
=======
==================================================================
=======
Optimizing unit <encode1> ...

Found area constraint ratio of 100 (+ 5) on block enco1, actual ratio is 0.
==================================================================
=======
Found no macro
==================================================================
=======
==================================================================
=======
Page | 82
==================================================================
=======
-------------------------------
==================================================================
=======
* Final Report *
==================================================================
=======
Clock Information:
------------------
-----------------------------------+------------------------+-------+
-----------------------------------+------------------------+-------+
din<0> | BUFGP |3 |
-----------------------------------+------------------------+-------+

----------------------------------------
-----------------------------------+------------------------+-------+
-----------------------------------+------------------------+-------+
dout_0__or0001(dout_0__or0001_f5:O)| NONE(dout_0) |1 |
-----------------------------------+------------------------+-------+
Timing Summary:
---------------
Speed Grade: -4

Page | 83
==================================================================
=======
Process "Synthesis" completed successfully
Started : "Launching RTL Schematic Viewer for encode1.ngr".

This is a Full version of ISE Simulator(ISim).
RESULT: Simulated the VHDL and VERILOG codes for PRIORITY ENCODER
and obtained the timing diagrams.
Page | 84
PART-B
Back-end Environment
Schematic diagram:
Page | 85
Truth table:
Input Output
0 1
1 0
EXPERIMENT-8
INVERTER
Page | 86
AIM: Using Tanner tools obtain a NOT gate, and to perform the DRC, extraction,
LVS, and simulation of the NOT gate.
APPARATUS: Tanner EDA tools 13.0V
PROCEDURE:
Schematic of Inverter Using S-EDIT:
1. Creating a New Design using S-EDIT and open file with name not. Tanner.
2. Browse the tools and devices from tanner eda tools.
3. Drag the components of PMOS and NMOS transistors and connect them
appropriately.
4. Check for loose connections using design rules and design checks in tools.
5. Provide the values to the circuit and simulate the result.
6. After simulation is successful extracts the net list from the circuit.
7. Use T-spice to for simulation.
Layout using L-EDIT:
1. Create the layout for a NOT gate. Start the layout in a new tanner tools file
not.tan and use your guide either your own layout stick diagram from the
presentation or the layout provided.
2. Re-use parts of the layout of the NOT gate, but make sure you use the correct
transistor sizes.
3. If dots appear in some areas in your layout, this is an indication that a design
rule (or rules) has been violated. To check which rule was violated, place the
box around the error area and type Shift-y or choose Explain DRC under
Box from the Misc menu. Look for the list of DRC errors in the tanner
Timing Waveforms:
Page | 87
Layout:
command window (the window from which you started tanner). You must fix all
DRC errors.
4. Make sure that you have drawn all necessary contacts between layers.
Page | 88
5. Label all input, output and supply voltage terminals by selecting the
corresponding layers and typing t. The power supply and ground labels must
be global (Vdd! and GND! respectively).
Expected Results:
Layout plot of the NOT gate.
Extract & LVS the Layout:

1. Doing extraction means obtaining the net list of an electrical circuit from the
layout images.
This is done in order to perform circuit level simulation (for Ex: using Spice)
parasitic capacitance between layout layers should be included in the extracted
circuit.
2. Once the layout is finished, do the extraction by clicking on extract it under
the local menu. Observe the local messages in the TANNER command
window, make sure we dont gat get any error messages. If the extraction is
successful, you will see the following message: DONE.
3. Extraction may fail if there is any error in the layout (Ex: The Drawn image
doesnt form a transistor).
4. The extractor will report errors and warnings by including the area of their
occurrence.
5. LVS stands for Layout-Verses-Schematic, which is used to compare the net list
of your extracted layout to the schematic. This check is used to make sure you
have no mistakes in your layout, and it actually corresponds to your schematic.
To LVS your extracted layout you have to create a schematic for the NOT gate
with the same transistor dimensions.
Simulate your design:
1. Run T- Spice and simulate your NOT gate. Apply Vdd to input b and apply a
pulse to input a with a height 2.5 volts with the rise and fall time of 200 ps, a
Page | 89
delay time of 0 ns, a pulse width of 3 ns, and a period of 6 ns. Plot the input
and output waveforms.
Spice netlist:
MNMOS_1 Out In Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_1 Out In Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
Vv1 Vdd Gnd PULSE(0 5 0 5n 5n 95n 200n)
Vv2 In Gnd BIT({0100101111} )
.PRINT TRAN V(Out)
.PRINT TRAN V(In)
.tran 5ns 100ns
.end
EXTRACTED RESULTS:
Provide a printout of the circuit diagram with parasitic capacitors, and a print
out of the required input and output waveforms.
Schematic diagram:
Page | 90
Tabular form:
wol bl blb q qbar operation

0 X X 0/1 1/0 Hold
1 1 1 0/1 1/0 Read
1 1 0 1 0 Write 1
1 0 1 0 1 Write 0
EXPERIMENT-9
Static RAM
Page | 91
AIM: Using Tanner tools obtain an SRAM cell, and to perform the DRC, extraction,
LVS, and simulation of the Static RAM.
PROCEDURE:
Schematic Using S-EDIT:
1. Creating a New Design using S-EDIT and open file with name sram. Tanner.
2. Browse the tools and devices from tanner EDA tools.
appropriately.

1. Create the layout for a six transistor sram cell. Start the layout in a new tanner
tools file sram.tan and use your guide either your own layout stick diagram
from the presentation or the layout provided.
2. Re-use parts of the layout of the SRAM cell, but make sure you use the correct
transistor sizes.
command window (the window from which you started tanner). You must fix
all DRC errors.
Timing Waveforms:
Page | 92
Layout:
5. Label all
input,
output and
supply
voltage
terminals by
Page | 93
selecting the corresponding layers and typing t. The power supply and
ground labels must be global (Vdd! and GND! respectively).
Expected Results:
Layout plot of the SRAM cell.

layout images.This is done in order to perform circuit level simulation (for Ex:
using Spice) parasitic capacitance between layout layers should be included in
the extracted circuit.
occurrence.
To LVS your extracted layout you have to create a schematic for the SRAM
cell with the same transistor dimensions.
1. Run T- Spice and simulate your SRAM cell. Apply Vdd to input b and apply
a pulse to input a with a height 2.5 volts with the rise and fall time of 200 ps,
a delay time of 0 ns, a pulse width of 3 ns, and a period of 6 ns. Plot the input
Spice netlist:
Cc1 q Gnd 10f

Cc2 qb Gnd 10f
Page | 94
MNMOS_3 bl wol q Gnd NMOS W=1.2u L=250n AS=1.08p PS=4.2u AD=1.08p
PD=4.2u
MNMOS_4 qb wol blb Gnd NMOS W=1.2u L=250n AS=1.08p PS=4.2u AD=1.08p
PD=4.2u
MNMOS_5 N_1 wol Gnd Gnd NMOS W=1.4u L=250n AS=1.26p PS=4.6u
AD=1.26p PD=4.6u
MNMOS_1 q qb N_1 N_1 NMOS W=2.4u L=250n AS=2.16p PS=6.6u AD=2.16p
PD=6.6u
MNMOS_2 qb q N_1 N_1 NMOS W=2.4u L=250n AS=2.16p PS=6.6u AD=2.16p
PD=6.6u
MPMOS_1 qb q Vdd Vdd PMOS W=600n L=250n AS=540f PS=3u AD=540f PD=3u
MPMOS_2 q qb Vdd Vdd PMOS W=600n L=250n AS=540f PS=3u AD=540f PD=3u
Vv1 Vdd Gnd DC 2.5
V(((_25 Pos_NC_0 Neg_NC_1 DC 2.5
Vv2 wol Gnd BIT({0111} ON=2.5 )
Vv3 bl Gnd BIT({1110} ON=2.5 )
Vv4 blb Gnd BIT({0101} ON=2.5 )
.PRINT TRAN V(qb)
.PRINT TRAN V(q)
.PRINT TRAN V(blb)
.PRINT TRAN V(bl)
.PRINT TRAN V(wol)
.tran 5ns 200ns
.end
EXTRACTED RESULTS:
Schematic diagram:
Page | 95
Tabular form:
A B Cin SUM Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
EXPERIMENT-10
FULL ADDER
AIM: Using Tanner tools obtain a FULL ADDER, and to perform the DRC,
extraction, LVS, and simulation of the Full Adder.
Page | 96
PROCEDURE:
1. Creating a New Design using S-EDIT and open file with name fulladd. Tanner.
appropriately.

1. Create the layout for a Full Adder. Start the layout in a new tanner tools file
not.tan and use your guide either your own layout stick diagram from the
2. Re-use parts of the layout of the Full adder, but make sure you use the correct
transistor sizes.
all DRC errors.
Timing Waveforms:
Page | 97
Layout:
be global (Vdd! and GND! respectively)
Page | 98
Expected Results:
Layout plot of the Full adder.

occurrence.
To LVS your extracted layout you have to create a schematic for the Full Adder
1. Run T- Spice and simulate your Full adder. Apply Vdd to input b and apply a
Spice Netlist:
Cc1 Cout Gnd 1f
Cc2 SUM Gnd 1f
MNMOS_1 N_34 Cin N_38 Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
Page | 99
MNMOS_2 N_36 A N_40 Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_3 N_38 B Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_4 N_38 A Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
PD=6.8u
MNMOS_6 N_26 N_34 N_42 Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_7 Cout N_34 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_8 N_42 A Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
PD=6.8u
MNMOS_10 N_42 Cin Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_11 N_26 A N_1 Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_12 N_1 B N_2 Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_13 N_2 Cin Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_14 SUM N_26 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_10 N_26 N_34 N_13 Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_11 N_13 Cin Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_12 N_34 Cin N_3 Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_13 N_36 A N_7 Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_14 SUM N_26 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_1 N_3 A Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
Page | 100
MPMOS_2 N_3 B Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_3 N_7 B Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_4 Cout N_34 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_5 N_13 A Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_6 N_13 B Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_7 N_4 Cin Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_8 N_5 B N_4 Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_9 N_26 A N_5 Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
Vv1 Vdd Gnd DC 2.5
Vv2 A Gnd BIT({00001111} ON=2.5 )
Vv3 B Gnd BIT({00110011} ON=2.5 )
Vv4 Cin Gnd BIT({01010101} ON=2.5 )
.PRINT TRAN V(Cout)
.PRINT TRAN V(SUM)
.PRINT TRAN V(Cin)
.PRINT TRAN V(B)
.PRINT TRAN V(A)
********* Simulation Settings - Analysis section *********
.tran 5ns 200ns
********* Simulation Settings - Additional SPICE commands *********

.end
EXTRACTED RESULTS:
Page | 101
Schematic Diagram:
Page | 102
Tabular form:
A B Output
0 0 0
0 1 0
1 0 0
1 1 1
EXPERIMENT-11
Page | 103
AND GATE
AIM: Using Tanner tools obtain an AND gate, and to perform the DRC, extraction,
LVS, and simulation of the AND gate.
PROCEDURE:
1. Creating a New Design using S-EDIT and open file with name andgt. Tanner.
appropriately.

1. Create the layout for a AND gate. Start the layout in a new tanner tools file
andgt.tan and use your guide either your own layout stick diagram from the
2. Re-use parts of the layout of the AND gate, but make sure you use the correct
transistor sizes.
all DRC errors.
Timing Waveforms:
Page | 104
Layout:
Expected Results:
Layout plot of the AND gate.
Page | 105
layout images. This is done in order to perform circuit level simulation (for Ex:
occurrence.
To LVS your extracted layout you have to create a schematic for the AND gate
1. Run T- Spice and simulate your AND gate. Apply Vdd to input b and apply a
Spice Netlist:
model nmos nmos level=1
.model pmos pmos level=1
MMOSFET_N_1 N_1 b N_2 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
MMOSFET_N_2 N_2 a Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
MMOSFET_N_3 c N_1 Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
MMOSFET_P_1 N_1 a Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
Page | 106
MMOSFET_P_2 N_1 b Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
MMOSFET_P_3 c N_1 Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
v1 vdd gnd 5
v2 a gnd PULSE (0 5 0 10p 10p 5n 15n)
v3 b gnd PULSE (0 5 0 10p 10p 5n 10n)
.tran .5n 100n
.print tran v(c,gnd) v(a) v(b)
.end
EXTRACTED RESULTS:
Schematic Diagram:
Page | 107
Truth Table:
A Output
0 0
1 1
EXPERIMENT-12
TWO STAGE BUFFER
Page | 108
AIM: Using Tanner tools obtain TWO STAGE BUFFER , and to perform the DRC,
extraction, LVS, and simulation of the TWO STAGE BUFFER.
PROCEDURE:

1. Creating a New Design using S-EDIT and open file with name buffer1.
Tanner.
appropriately.

1. Create the layout for a two stage buffer. Start the layout in a new tanner tools
file andgt.tan and use your guide either your own layout stick diagram from
the presentation or the layout provided.
2. Re-use parts of the layout of the two stage buffer, but make sure you use the
correct transistor sizes.
all DRC errors.
Timing Waveforms:
Page | 109
Layout:
Page | 110
Expected Results:
Layout plot of the Two stage buffer.

occurrence.
To LVS your extracted layout you have to create a schematic for the Full Adder
1. Run T- Spice and simulate your Two stage buffer. Apply Vdd to input b and
apply a pulse to input a with a height 2.5 volts with the rise and fall time of
200 ps, a delay time of 0 ns, a pulse width of 3 ns, and a period of 6 ns. Plot the
input and output waveforms.
SPICE NETLIST:
.model nmos nmos level=1
Page | 111
.model pmos pmos level=1
MMOSFET_N_1 N_1 a Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
MMOSFET_N_2 N_1 b Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
MMOSFET_P_1 N_1 b N_2 N_2 PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
MMOSFET_N_3 c N_1 Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
MMOSFET_P_2 N_2 a Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
MMOSFET_P_3 c N_1 Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
v1 vdd gnd 5
v2 a gnd PULSE (0 5 0 10p 10p 5n 15n)
v3 b gnd PULSE (0 5 0 10p 10p 5n 10n)
.tran .5n 100n
.print tran v(c,gnd) v(a) v(b)
.end
EXTRACTED RESULTS:
Page | 112

M.tech I Sem Vlsi Technoly I Lab Record

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

M.tech I Sem Vlsi Technoly I Lab Record

Uploaded by

Copyright:

Available Formats

PART-A

VHDL CODE FOR AND GATE:

Cout : out STD_LOGIC);

architecture Behavioral of andgate is

VERILOG CODE FOR AND GATE:

Cout : out STD_LOGIC);

architecture Behavioral of orgate is

VERILOG CODE FOR OR GATE:

VHDL CODE FOR NOT GATE:

Cout : out STD_LOGIC);

architecture Behavioral of notgate is

Cout <= not a;

VERILOG CODE FOR NOT GATE:

module notga(a, b);

Cout : out STD_LOGIC);

architecture Behavioral of nandgate is

Cout <= a nand b;

VERILOG CODE FOR NAND GATE:

module nand2 (a,b,c);

Inputs Outpu Truth table

Cout : out STD_LOGIC);

architecture Behavioral of norgate is

VERILOG CODE FOR NOR GATE:

module nor2(a,b, c);

VHDL CODE FOR XOR GATE:

Cout : out STD_LOGIC);

architecture Behavioral of xorgate is

VERILOG CODE FOR XOR GATE:

Cout : out STD_LOGIC);

architecture Behavioral of xnorgate is

VERILOG CODE FOR XNOR GATE:

Compiling vhdl file "C:/Xilinx91i/andgate/andgate.vhd" in Library work.

Entity <andgate> compiled.

Entity <andgate> (Architecture <Behavioral>) compiled.

Process "Check Syntax" completed successfully

Reading design: andgate.prj

Compiling vhdl file "C:/Xilinx91i/andgate/andgate.vhd" in Library work.

Architecture behavioral of Entity andgate is up to date.

* Design Hierarchy Analysis *

Analyzing hierarchy for entity <andgate> in library <work> (architecture <behavioral>).

Analyzing Entity <andgate> in library <work> (Architecture <behavioral>).

Entity <andgate> analyzed. Unit <andgate> generated.

Performing bidirectional port resolution...

Synthesizing Unit <andgate>.

Related source file is "C:/Xilinx91i/andgate/andgate.vhd".

Unit <andgate> synthesized.

HDL Synthesis Report

* Advanced HDL Synthesis *

Advanced HDL Synthesis Report

* Low Level Synthesis *

Optimizing unit <andgate> ...

Mapping all equations...

Building and optimizing final netlist ...

Found area constraint ratio of 100 (+ 5) on block andgate, actual ratio is 0.

Final Macro Processing ...

Partition Implementation Status

No Partitions were found in this design.

No clock signals found in this design

Asynchronous Control Signals Information:

No asynchronous control signals found in this design

Minimum period: No path found

Minimum input arrival time before clock: No path found

Maximum output required time after clock: No path found