How Computers Work

Lecture 5

Memory Implementation

How Computers Work Lecture 5 Page 1

A Top-Down View of the Beta Architecture

PC
With st(ra,C,rc) : Mem[C+<rc>] <- <ra>
Q

XADDR
RA1
Memory
RD1 JMP(R31,XADDR,XP)

ISEL 0 1

31:26 25:21 20:5 9:5 4:0

OPCODE RA C RB RC

+1 0 1

OPCODE RA1 RA2

Register File SEXT Register File
RD1 RD2

ASEL BSEL
0 1 2 1 0

A B
ALUFN ALU
A op B
Z

RA2
Memory
RD2

PCSEL 0 1 0 1 2 WDSEL

D WD WA WD WA RC
PC Memory Register File
WE WEMEM WE WERF

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1
 Todays Lecture:
How do we build these?
RA1
Memory
RD1

RA1 RA2
Register File Register File
RD1 RD2

RA2
Memory
RD2

WD WA WD WA
Memory Register File
WE WE

How Computers Work Lecture 5 Page 3

Recall the Enable-Controlled Register

D
Q
32
E 32

CLK

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2
How do we select 1 of 31 registers to read?
D
Q
E

D
Q
E

.
.
.
D
Q
E

How Computers Work Lecture 5 Page 5

A: Add an output selector.

D
Q
E

D
Q
E

RD1 = <RA1>
.
.
.
D
Q
E

RA1
How Computers Work Lecture 5 Page 6

3
Q: How do we add a second port?
D
Q
E

D
Q
E

RD1 = <RA1>
.
.
.
D
Q
E

RA1
How Computers Work Lecture 5 Page 7

A: Add a second multiplexor

D
Q
E

D
Q
E

RD1 = <RA1> RD2 = <RA2>

.
.
.
D
Q
E
0
0

RA1 RA2
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4
Q: How do we write selectively?
D
Q
E

D
Q
E

RD1 = <RA1> RD2 = <RA2>

.
.
.
D
Q
E
0
0

RA1 RA2
How Computers Work Lecture 5 Page 9

A: Use a decoder on the Enables

WD
D
Q 0
0 E 0

D
Q 1
1 E 1

RD1 = <RA1> RD2 = <RA2>

WERF .
.
.
D
Q 30
30 E 30
31 31 0 31
0

RA1 RA2
WA
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 The Decoder / Demultiplexor

How Computers Work Lecture 5 Page 11

To minimize wires:
WD WD
D D
Q 0 Q
0 E 0 E 0

D D
Q 1 Q
1 E 1 E 1

RD1
WERF . . RD2

. .
. .
D D
Q 30 Q
30 E 30 E 30
31 31 31
0 31
0
RA1
WA RA2
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 Q: What about the clocks?
WD
D
Q 0
0 E 0

D
Q 1
1 E 1

RD1 = <RA1> RD2 = <RA2>

WERF .
.
.
D
Q 30
30 E 30
31 0
31 0 31

RA1 RA2
WA
How Computers Work Lecture 5 Page 13

A: Connect them all together.

WD
D
Q 0
0 E 0

D
Q 1
1 E 1

RD1 = <RA1> RD2 = <RA2>

WERF .
.
.
D
Q 30
30 E 30
31 31 0 31
0

RA1 RA2
WA Clock
How Computers Work Lecture 5 Page 14

7
Q: Is it practical to do the big
Memory this way?

A: NO
How Computers Work Lecture 5 Page 15

Minimize per-bit circuitry

.
. ...
.

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8
 1 Bit Cell

How Computers Work Lecture 5 Page 17

Minimizing per-bit circuitry

.
. ...
.

Sense Amplifiers

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 How about ROMs?

How Computers Work Lecture 5 Page 19

Q: What can we use for a switch?

A: The Field-Effect Transistor

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10
The N-Channel FET (NFET)

How Computers Work Lecture 5 Page 21

The P-Channel FET (PFET)

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 How do we implement multiple ports?

2 Read and 1 Write Ports

For now, LD and ST instructions are mutually
exclusive.
1 RD + 1 RD/WR port needed
LD and ST are dont happen that often
Most of the time only 1RD port necessary
Easy answer : Do them sequentially
Need a way to stall machine waiting for Mem
How Computers Work Lecture 5 Page 23

Q: How do we stall this machine?

PC
Q

XADDR
RA1
Memory
RD1 JMP(R31,XADDR,XP)

ISEL 0 1

31:26 25:21 20:5 9:5 4:0

OPCODE RA C RB RC

+1 0 1

OPCODE RA1 RA2

Register File SEXT Register File
RD1 RD2

ASEL BSEL
0 1 2 1 0

A B
ALUFN ALU
A op B
Z

RA2
Memory
RD2

PCSEL 0 1 0 1 2 WDSEL

D WD WA WD WA RC
PC Memory Register File
WE WEMEM WE WERF

How Computers Work Lecture 5 Page 24

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 A: Stalls are done by:
Disabling WERF
Disabling Memory Write
Disabling PC write

How Computers Work Lecture 5 Page 25

Another Approach - Increasing

Memory Bandwidth

Make memory twice as wide

64 Bits Instead of 32
Should work out in the long run, as 2 words are read per
machine cycle, but
Words read are next to each other in address space
Need a place to stash the extra word
Sometimes, the stashed word isnt used.
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 Summary
What Did we learn today?
How to Implement Registers + Big Memory
Multi-Port Big Memories arent easy
Sequential Access (stalls + extra logic)
Wide Access + Some sort of cache + extra logic
Recitation
Review of todays lecture

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