MATHA COLLEGE OF TECHNOLOGY

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

SYLLABUS

Subject Name: EC010 404 Digital Electronics Class: S4 - ECE

Module I (12hours)
Positional Number System: Binary, Octal, Decimal, Hexadecimal number system, Number
base conversions, complements - signed magnitude binary numbers - Binary Arithmetic-
addition, subtraction - Binary codes- Weighted, BCD, 8421, Gray code, Excess 3 code,
ASCII, Error detecting and correcting code, parity, hamming code. Boolean postulates and
laws with proof, De-Morgans Theorems, Principle of Duality, Minimization of Boolean
expressions, Sum of Products (SOP), Product of Sums (POS), Canonical forms, Karnaugh
map Minimization, Dont care conditions

Module II (12 hours)

Digital Circuits: Positive and Negative logic, Transistor transistor logic, TTL with totem
pole, open collector and tri state output, Emitter coupled logic basic ECL inverter, NMOS
NOR gate, CMOS inverter, NAND and NOR, Gate performance parameters fan in, fan
out, propagation delay, noise margin, power dissipation for each logic, characteristics of
TTL and CMOS, subfamilies of TTL and CMOS.
.
Module III (12 hours)
Introduction to Combinational Circuits: Basic logic gates, Universal gates, Realization of
Boolean functions using universal gates, Realization of combinational functions: addition
half and full adder n bit adder carry look ahead adder, subtraction, comparison, code
conversion, and decoder, encoder, multiplexer, demultiplexer, parity checkers, and parity
generator.
Introduction to Sequential Circuits: latches, timing, Flip Flops, types, characteristic
equations, excitation tables, Realization of one flip flop using other flip flops.

Module IV (12 hours)

Application of flip flops as bounce elimination switch, register, counter and RAM, Binary
ripple counter, synchronous binary counter, Design of modulo n synchronous counter,
up/down counters,
Shift registers SISO, SIPO, PISO, PIPO, bidirectional shift register and universal register,
counters based on shift registers

Module V (12 hours)

Hazards in combinational circuits: Static hazard, dynamic hazard, essential hazards, hazard
free combinational circuits.
Introduction to programmable logic devices: PLA- block diagram, PAL block diagram,
registered PAL, Configurable PAL, GAL - architecture, CPLD classification internal
architecture, FPGA - architecture, ASIC categories , full custom and semi custom.

1
Reference Books

1. Donald D Givone, Digital Principles and Design, Tata McGraw Hill, 2003.
2. G K Kharate, Digital Electronics, Oxford university press, 2010
3. Ronald J Tocci, Digital Systems, Pearson Education, 10th edition 2009.
4. Thomas L Floyd, Digital Fundamentals, Pearson Education, 8th edition, 2003.
5. Donald P Leach, Albert Paul Malvino, Digital Principles and Applications, Tata
McGraw Hill 6th edition, 2006.
6. Charles H.Roth, Fundamentals of Logic Design, Thomson Publication Company 5th
edition, 2004.
7. Milos Ercegovac, Introduction to Digital Systems, Wiley India, 2010
8. Moris mano, Digital Design, PHI, 3rd edition, 2002.
9. Anada kumar, Fundamentals of Digital Circuits, PHI, 2008.
10. Brain Holdesworth, Digital Logic Design, Elsevier, 4th edition, 2002.

2
 MATHA COLLEGE OF TECHNOLOGY
DEPARTMENT OF ELECTRONICS AND COMMUNICATION

LESSON PLAN

Subject Name: EC010 404 Digital Electronics Class: S4 A - BATCH

Name of the Teacher: Krishnachandran R. Total Expected: - 47hrs.

Module Topics Date Hours Remarks

Positional Number System: Binary,

Octal, Decimal, Hexadecimal number 18-01-12 2
system, Number base conversions,

complements - signed magnitude binary

numbers - Binary Arithmetic- addition, 19-01-12,
2
subtraction , Binary codes- Weighted, 20-01-12
BCD, 8421, Gray code,

Excess 3 codes, ASCII, Error detecting

and correcting code, parity, and hamming 20-01-12 1
code.
Module I
Boolean postulates and laws with proof,
De-Morgans Theorems, Principle of
25-01-12 1
Duality, Minimization of Boolean
expressions

Sum of Products (SOP), Product of Sums

25-01-12 1
(POS), Canonical forms

Karnaugh map Minimization, Dont care 27-01-12,

2
conditions 01-02-12

Class Test 03-02-12 1

Digital Circuits: Positive and Negative

01-02-12,
logic, Transistor transistor logic, TTL 2
with totem pole, open collector and tri 02-02-12
state output, characteristics of TTL
Module II 03-02-12 ,
Emitter coupled logic basic ECL 2
inverter, NMOS NOR gate 08-02-12

08-02-12,
CMOS inverter, NAND and NOR, 2
characteristics of CMOS 09-02-12

3
 Gate performance parameters fan in,
fan out, propagation delay, noise margin,
10/02/12 2
power dissipation for each logic,
subfamilies of TTL and CMOS

Module II Class Test 16-01-12 1

Introduction to Combinational Circuits:

Basic logic gates, Universal gates,
Realization of Boolean functions using 17/02/12 2
universal gates, Realization of
combinational functions:
addition half and full adder n bit
adder carry look ahead adder, 22-02-12 2
subtraction,
Comparison, code conversion, and
decoder, encoder, multiplexer, 29-02-12,
Module III 3
demultiplexer, parity checkers, and parity 01-03-12
generator.

Introduction to Sequential Circuits:

latches, timing, Flip Flops, types,
characteristic equations, excitation tables, 02-03-12,
3
Realization of one flip flop using other 07-03-12
flip flops.

Class Test 14-03-12 1

Application of flip flops as bounce 07-03-12,

elimination switch, register, counter and 2
14-03-12
RAM, Binary ripple counter,
Synchronous binary counter, Design of
16-03-12,
modulo n synchronous counter, 3
up/down counters, 21-03-12
Module IV
Shift registers SISO, SIPO, PISO, 21-03-12,
PIPO, bidirectional shift register and 2
22-03-12
universal register
Counters based on shift registers 23-03-12 1

Class Test 29-03-12 1

Hazards in combinational circuits: Static

Module V hazard, dynamic hazard, essential 23-03-12 1
hazards, hazard free combinational
circuits.
Introduction to programmable logic 30-03-12 1
devices: PLA- block diagram,

4
 30-03-12,
PAL block diagram, registered PAL, 2
Configurable PAL, GAL - architecture, 04-04-12

CPLD classification internal 04-04-12 1

architecture

Module V FPGA - architecture 12-04-12 1

ASIC categories, full custom and semi

custom. 13-04-12 1

Class Test 13-04-12 1

5
 MATHA COLLEGE OF TECHNOLOGY
DEPARTMENT OF ELECTRONICS AND COMMUNICATION

LESSON PLAN

Subject Name: EC010 404 Digital Electronics Class: S4 B - BATCH

Name of the Teacher: Krishnachandran R. Total Expected: - 48hrs.

Module Topics Date Hours Remarks

Positional Number System: Binary,

18-01-12,
Octal, Decimal, Hexadecimal number 2
19-01-12
system, Number base conversions,

complements - signed magnitude binary

numbers - Binary Arithmetic- addition, 21-01-12,
2
subtraction , Binary codes- Weighted, 23-01-12
BCD, 8421, Gray code,

Excess 3 codes, ASCII, Error detecting

and correcting code, parity, and hamming 24-01-12 1
code.
Module I
Boolean postulates and laws with proof,
De-Morgans Theorems, Principle of
25-01-12 1
Duality, Minimization of Boolean
expressions

Sum of Products (SOP), Product of Sums

28-01-12 1
(POS), Canonical forms

Karnaugh map Minimization, Dont care 30-01-12,

2
conditions 31-01-12

Class Test 04-02-12 1

Digital Circuits: Positive and Negative

01-02-12,
logic, Transistor transistor logic, TTL 2
with totem pole, open collector and tri 02-02-12
state output, characteristics of TTL
06-02-12 ,
Emitter coupled logic basic ECL 2
Module II 07-02-12
inverter, NMOS NOR gate
08-02-12,
CMOS inverter, NAND and NOR, 2
characteristics of CMOS 09-02-12

Gate performance parameters fan in, 16-02-12, 2

6
 fan out, propagation delay, noise margin, 17-02-12
power dissipation for each logic,
subfamilies of TTL and CMOS

Module II Class Test 17-01-12 1

Introduction to Combinational Circuits:

Basic logic gates, Universal gates, 18-02-12,
Realization of Boolean functions using 2
21-02-12
universal gates, Realization of
combinational functions:
addition half and full adder n bit 22-02-12,
2
adder carry look ahead adder, 25-02-12
subtraction,
Comparison, code conversion, and
decoder, encoder, multiplexer, 27-02-12,
Module III 3
demultiplexer, parity checkers, and parity 29-03-12
generator.

Introduction to Sequential Circuits:

latches, timing, Flip Flops, types,
characteristic equations, excitation tables, 01-03-12,
3
Realization of one flip flop using other 05-03-12
flip flops.

Class Test 07-03-12 1

Application of flip flops as bounce 06-03-12,

2
elimination switch, register, counter and 12-03-12
RAM, Binary ripple counter,
Synchronous binary counter, Design of
13-03-12,
modulo n synchronous counter, 3
up/down counters, 17-03-12
Module IV
Shift registers SISO, SIPO, PISO, 19-03-12,
PIPO, bidirectional shift register and 2
20-03-12
universal register
Counters based on shift registers 21-03-12 1

24-03-12 1
Class Test
Hazards in combinational circuits: Static
hazard, dynamic hazard, essential 22-03-12 1
Module V hazards, hazard free combinational
circuits.
Introduction to programmable logic 29-03-12 1
devices: PLA- block diagram,
PAL block diagram, registered PAL, 3
30-04-12,
Configurable PAL, GAL - architecture,

7
 02-04-12

CPLD classification internal 03-04-12 1

architecture
04-04-12 1
Module V FPGA - architecture
ASIC categories, full custom and semi
custom. 10-04-12 1

Class Test 12-04-12 1

8
 MATHA COLLEGE OF TECHNOLOGY
DEPARTMENT OF ELECTRONICS AND COMMUNICATION

CLASS NOTES

Subject Name: EC010 404 Digital Electronics Class: S4 - ECE

Name of the Teacher: Krishnachandran R.

Page
Module Topics Reference
No.s
Positional Number System: Binary,
Digital Fundamentals- 42-47,
Octal, Decimal, Hexadecimal
Thomas L. Floyd 69-78
number system
47-50,
Number base conversions -do- 70-71,
76-78
complements - signed magnitude
binary numbers, Binary Arithmetic- -do- 54-62
addition, subtraction
Binary codes- Weighted, BCD,
8421, Gray code, Excess 3 code,
Fundamentals of Digital
Module I ASCII, Error detecting and 70-95
Circuits A. Anand Kumar
correcting code, parity, hamming
code
Boolean postulates and laws with
-do- 139-149
proof, De-Morgans Theorems,
Principle of Duality -do- 151-152
Minimization of Boolean
expressions, Sum of Products (SOP),
-do- 157-162
Product of Sums (POS), Canonical
forms
Karnaugh map Minimization, Dont
-do- 195-223
care conditions
Digital Electronics and
Digital Circuits: Positive and
Logic Design Somanathan 212-216
Negative logic,
Nair
Transistor transistor logic, TTL with
Fundamentals of Digital
totem pole, open collector and tri 733-742
Circuits A. Anand Kumar
state output

Emitter coupled logic basic ECL

Module II -do- 747-752
inverter,

NMOS NOR gate, -do- 753-756

CMOS inverter, NAND and NOR -do- 756-760
Module II Gate performance parameters fan -do- 729-733

9
 in, fan out, propagation delay, noise
margin, power dissipation for each
logic,
Digital Electronics and 224-
Characteristics of TTL and CMOS Logic Design Somanathan 228,
Nair 244-246
Subfamilies of TTL and CMOS. Fundamentals of Digital
742-744
Circuits A. Anand Kumar
Introduction to Combinational
Circuits: Basic logic gates, Universal
gates -do- 108-120
Realization of Boolean functions
using universal gates,
Realization of combinational
functions: addition half and full -do- 282-287
adder
Module III n bit adder carry look ahead adder -do- 291-295
Subtractor -do- 287-291
Comparators -do- 326-328
Code Convertors -do- 305-314
330-
decoder, encoder -do- 332,
337-341
multiplexer, demultiplexer, -do- 337-357
parity checkers, and parity generator.
-do- 322-325
Introduction to Sequential Circuits:
latches, timing, Flip Flops, types,
characteristic equations, excitation
Module III -do- 459-492
tables, Realization of one flip flop
using other flip flops.

Digital Electronics and

Application of flip flops as bounce
Logic Design Somanathan 113-114
elimination switch
Nair
Counter , Binary ripple counter, Fundamentals of Digital
527-532
synchronous binary counter Circuits A. Anand Kumar
Design of modulo n synchronous
Module IV -do- 538-551
counter, up/down counters,
Shift registers SISO, SIPO, PISO,
PIPO, bidirectional shift register and -do- 513-517
universal register,
Counters based on shift registers
-do- 561-563
Hazards in combinational circuits:
Static hazard, dynamic hazard,
Module V -do- 361-364
essential hazards, hazard free
combinational circuits.

10
 Introduction to programmable logic Modern Digital Electronics-
451-458
devices: PLA- block diagram R. P. Jain
PAL block diagram, registered
PAL, Configurable PAL, GAL - -do- 465-475
architecture
CPLD classification internal
-do- 478-480
architecture,
FPGA - architecture -do- 483-489
ASIC categories , full custom and
Internet
semi custom

Text Books Referred

1. Digital Fundamentals- Thomas L. Floyd

2. Fundamentals of Digital Circuits A. Anand Kumar
3. Digital Electronics and Logic Design Somanathan Nair
4. Modern Digital Electronics- R. P. Jain

11
 QUESTION BANK
EC010 404: DIGITAL ELECTRONICS

Module I
Part A

1. What are the properties of Gray code? Write all gray codes
2. Convert the following decimal numbers into its equivalent binary 1) 625.05 2)
0.003901
3. Perform subtraction of binary number 10010 from 11001 using ones compliment and
twos compliment method.
4. Using ones compliment and twos compliment method subtract 100110 -1101
5. Write the values of the following binary numbers in decimal system by considering it
as both signed and unsigned number(use ones compliment for signed number): (1)
111011; (2) 010111
6. Perform binary subtraction using 2s complement and 1s complement methods100-
110000.
7. Explain how a function containing max. terms can be simplified using K-map.
8. State and explain Demorgans laws.

Part B

9. What are signed binary numbers? Explain with examples.

10. Subtract using 1s complement and 2s complement method: 101011-10110.
11. Simplify + + ( + )
12. Simplify the expression = + + + + + +
13. Express the Boolean expression = + in product of max. Terms.
14. Construct Karnaugh Map and simplify 1) = + + 2) = + +
+
15. Prove that + + + = + ( + )
16. Using Boolean algebra simplify the expressions 1) + + 2) + +
+

Part C

17. Find the minimal sop and POS for f=M0,2,4,10,11,13+dc(1,3,6)

18. Implement the following functions using 8:1 MUX 1) f=
m(0,3,4,6,8,10,12,13)+dc(2,7) 2) f = M(0,3,5,6,7,10,11,13,14 )
19. Apply De Morgans theorems to the following expressions and prove that 1)
A+B+C=AC+BC 2) A+B+CD=ABC+ABD. 3) + + + = +
+

12
 20. What are error detecting and correcting codes? Give examples and explain the
processes. What are excess three codes? Write the excess-3 codes corresponding to
the decimal 1 to 16.
21. Encode the following decimal numbers to BCD code 1) 640 2)372.98 3)20.301.
Encode these numbers to Gray code.
22. A stair case light is controlled by two switches one at the top of the stairs and another
at the bottom of the stairs 1) make the truth table for the system. 2) Write the logic
equation in SOP form. 3) Realize the circuit using AND-OR gates 4) neither realize
the circuit using only NOR gates.
23. Explain the even and odd parity schemes bringing out their Merits and demerits.
Attach proper even parity bit to the following bytes of Date 1) 10100100 2)
00001001 3) 11111110 4) 10101010
24. Explain the features of excess-3 codes giving examples. What are its uses? Bring out
the special features of hamming codes and their applications.

Module II
Part A

25. What do you mean by Positive and negative Logic.

26. Draw the circuit of a TTL NAND gate?
27. Explain briefly a CMOS NOT gate.
28. What do you mean by Active and Passive Pull up?
29. List out Various TTL sub families
30. Why ECL family is able to provide high speed.
31. Define Fan-in and Fan-Out and give typical values for TTL family.

Part B

32. Explain wire-AND ing in TTL circuits and its applications.

33. Define noise margin, giving value for TTL.
34. Define Propagation delay of a logic gate. Compare the same for TTL and CMOS.
35. What are the advantages and disadvantages of totem pole Output?
36. Compare the power dissipation of various logic families.
37. Draw and explain the circuit diagram of CMOS NAND gate.
38. Draw and explain tri-state inverter.
39. How the use of Schotkey transistors improves the performance of TTL.
40. Describe the sourcing and sinking characteristics of a gate?

Part C

41. Sketch and Explain the circuit diagrams and working of 1) non-inverting CMOS tri-
state driver with active high control and inverting CMOS tri-state driver with active
low control. What are its applications?
42. Draw the circuit diagram of a 2-input NAND gate in TTL family and explain the
working with the help of its truth table.

13
 43. Giving typical values, define and explain the following standard TTL NAND gate(i)
Fan-in(ii)Fan-out(iii)noise margin(iv)Propagation delay(v)VoH(vi)VIH
44. Draw the circuit of an open collector AND gate and explain. What are its
applications?
45. Draw the circuit of a CMOS NOR gate and explain its working. Compare CMOS
and TTL gates
46. With a neat circuit diagram, Explain the working of a two input OR gate of CMOS
logic family.
47. Discuss the various TTL sub families in Detail.
48. With the help of a neat diagram explain the working of an ECL NOT gate.
49. Compare any four properties of TTL and CMOS logic families. Explain a CMOS
NAND gate.
50. Explain an ECL NOR/OR gate with help of a neat diagram.
51. Explain TTL Tristate inverter in detail.

Module III
Part A

52. Draw the symbol and truth table of NOR gate.

53. Design and draw a half adder using NAND gates only.
54. Explain the differences between a Latch and a flip-flop?
55. What is the principle of edge triggering? Why is it used?
56. Using 4:1 MUX, realize AND and OR functions.
57. Realize a Half adder using minimum number of NOR gates.
58. Why negative edge triggering is used in flip-flops?
59. Which are the universal gates? Why they are called so?
60. Realise a NAND gate using a 4:1 multiplexer.
61. Draw a full adder using half adders. Explain the working using truth tables.

Part B

62. Explain what a level triggered flip flop is and for what purposes can it be used.
Compare their operations with the edge triggered flip flops.
63. Distinguish between truth table and excitation table with reference to the JK flip
flop. What are their uses?
64. State and explain any two practical applications of XOR gate.
65. Draw a NOR and OR gate functions using only NAND gates.
66. Draw the block diagram of a de-multiplexer and explain. What are its applications?
67. Draw the circuit of a half adder using NAND gates only.
68. Clearly explain race around problem.
69. Draw the excitation table of JK flip flop and explain the same.
70. What are the applications of XOR gates?
71. What are D-latches? What are its applications
72. Convert a RS flip flop to a T flip-flop

14
 73. With logic diagrams show how a JK flip-flop can be converted into (i) D flip-flop (ii)
T flip-flop?

Part C

74. Draw the truth table for a full adder. Design the minimal circuit using NAND gates
only.
75. Draw the circuit diagram of a clocked master slave JK flip flop with preset and clear
inputs and explain its working.
76. With logic diagram and table explain the working of an 8:1 multiplier. Distinguish
between a multiplexer and encoder.
77. Sketch and explain the complete circuit of a negative edge triggered master slave JK
flip flop with synchronous, asynchronous inputs. Use only fundamental logic gates.
78. Explain encoders and decoders with examples. What are their applications?
79. Draw the circuit of a parallel binary adder cum subtractor and explain its working.
80. Draw the circuit of a twos compliment adder cum subtractor and explain its working.
81. Draw the truth table of an MS JK flip-flop using NOR gates only and explain.
Explain how racing can be avoided by MSJK.
82. What is a multiplexer? Explain 4 to 1 MUX with neat diagram. Implement the
following function using 4 to 1 MUX = (0,1,3,5,8,9,12,14,15)
83. Design a full subtractor circuit using NAND gates only. Realise the above using a
decoder.
84. With neat circuit diagram, explain the working of a carry propagation adder. Mention
its merits and disadvantages.
85. Draw the truth table for a positive edge triggered JK flip-flop with waveforms and
explain. Compare with RS flip flop.

Module IV
Part A

86. Compare and contrast Synchronous and Asynchronous counters.

87. Explain a 4-bit serial shift register.
88. What is a ring counter? What are its practical applications?
89. Explain any two distinct applications of shift registers.
90. Bring out the advantages and disadvantages of ripple counter compared to a
synchronous counter.
91. Explain the principle and applications buffer registers.

Part B

92. Explain how JK flip-flop act as bounce elimination switch.

93. Distinguish between latches and flip flops.

15
 94. Draw the circuit diagram, output sequence and timing diagram of a four bit Johnson
counter.
95. Draw and explain the application of the ring counter with its timing diagram.
96. What are the differences between shift register and counter? Give one application
each.
97. Explain a for bit serial shift register.

Part C

98. Design a counter with irregular binary count sequence 1,4,3,2,5,0,6,1. Use T flip
flops draw the wave forms.
99. Explain with diagrams 1) 4-bit bidirectional shift register and 2)4-bit ring counter.
100.Using T-flip flops, Design a counter with the following repeated binary sequence 0,
1, 3,7,6,4.
101. Draw the circuit of a ring counter and explain the working with the help of timing
diagram. Show how you can make a four stage ring counter work as a divide by two
counters and divide by four pulse divider.
102. What is a shift register? Write a neat circuit explain a 4 bit parallel in serial out ,
parallel out shift registers for different combination of inputs.
103. Design a mod-16 up counter using positive edge triggered JK flip-flops with
minimal combinational logic circuits. Explain the circuit diagram with help of its
timing diagrams.
104. Draw the circuit of a 4 bit shift-left and shift right register with mode control and
explain its working.
105. With a neat circuit diagram, explain the working of a 4 bit universal shift register.
106. Design and develop a decade counter using JK master slave flip flops? What are the
merits and demerits of a ripple counter over a synchronous counter?
107. Draw the circuit of a mod controlled up-down counter of a 4 bit using JK flip flops.
Draw the timing diagrams and explain.

Module V
Part A

108. Distinguish between PLA and PAL.

109. What is meant by static hazards? Draw the circuit with a static 1 hazard and static1
hazard free circuit.
110. Write a note on VHDL.
111. Explain how hazards can occur in Logic gates.

Part B

112. Write a brief note on FPGA.

113. Explain static and dynamic hazards
114. Discuss about ASIC
115. Write brief note on Programmable Logic devices

16
 116. Explain Dynamic and Essential Hazard.
117. What are registered and configurable PAL

Part C

118.With the help of neat diagrams, explain the working of 1) FPGA and 2) CPLD.
119.Discuss various hazards in digital circuits. And what do you mean by hazard free
combinational circuits.
120.Explain with neat diagrams , the architecture of GAL
121.Discuss PLAs and PAL.
122.Discuss how a logic function can be implemented using PLAs with an example.
123.Design an XS-3 to BCD converter using PLA and PAL.
124.Implement the following Boolean functions using PLA 1) (, , ) = (0,1,3,5)
2) (, , ) = (0,3,5,7)
125.Implement a full adder using PLA.

17