Seminar Report -2010 High K Metal Solution

(1) INTRODUCTION
The type of transistor that is chained together by the hundreds of millions to make up
today's microprocessors, memory, and other chips is called a metal-oxide-
semiconductor field effect transistor, or MOSFET. Basically, it is a switch. A voltage
on one terminal, known as the gate, turns on or off a flow of current between the two
other terminals, the source and the drain.

Although the basic features and materials of the MOS transistor have stayed pretty
much the same since the late 1960s, the dimensions have scaled dramatically. The
transistor's minimum layout dimensions were about 10 micrometers 40 years ago, and
are less than 50 nm now, smaller by a factor of more than 200. Suppose a 1960s
transistor was as big as a three- bedroom house and that it shrank by the same factor.

We could hold the house in the palm of our hand today. The rapid progress of CMOS
integrated circuit technology, since late 1980‘s, has enabled the Si-based
microelectronic industry to simultaneously meet several technological requirements to
fuel market expansion. These requirements include performance (or speed),low static
(off-state) power and a wide range of power supply and input-output voltages. This
has been accomplished by a calculated reduction of the dimensions of the
fundamental active device in the circuit. This device is the Metal Oxide
Semiconductor Field Effect Transistor (MOSFET).And this practice is called Scaling.

The thickness of the SiO 2 insulation on the transistor's gate has scaled from about 100
nm down to 1.2 nm on state-of-the-art microprocessors. The rate at which the
thickness decreased was steady for years but started to slow at the 90-nm generation,
which went into production in 2003. It was then that the oxide hit its five-atom limit.
The insulator thickness shrank no further from the 90-nm to the 65-nm generation still
common today. The reason the gate oxide was shrunk no further is that it began to
leak current, resulting in increased heating of processing core.

The leakage arises from quantum effects. At 1.2 nm, the quantum nature of particles
starts to play a big role. In terms of classical physics, an electron is like a ball and the
insulation as a tall and narrow hill. The height of the hill represents how much energy

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 Seminar Report -2010 High K Metal Solution

the electron needs to get it to the other side. Once given sufficient energy—sure
enough—it could get over the hill, busting through the insulation in the process. But
when the hill (the oxide layer) is so narrow (individual atoms of thickness), the
electron looks less like a ball and more like a wave. Specifically, it's a wave that
defines the probability of finding the electron in a particular location. The trouble is
that the wave is actually broader than the hill, extending all the way to the other side
and beyond. That means there is a distinct probability that an electron that should be
on the gate side of the oxide can simply appear on the channel side, having ‗tunneled‘
through the energy barrier posed by the insulation rather than going over it.Many
material systems are currently under consideration as potential replacements for SiO 2
as gate dielectric material for sub-0.1 micrometer complementary metal oxide
semiconductor (CMOS) technology. Considering the required properties of gate
dielectric the key guidelines for selecting an alternative gate dielectric are
permittivity, band gap and band alignment to silicon, thermodynamic stability, film
morphology, interface quality, compatibility with the current or expected materials to
be used in processing for CMOS devices, process compatibility and reliability. Many
dielectrics appear favorable in some of these areas, but very few materials are
promising with respect to all of these guidelines.

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 Seminar Report -2010 High K Metal Solution

(2)MOSFETS-AN OVERVIEW
MOSFETs come in two varieties: N (for n-type) MOS and P (for p-type) MOS. The
difference is in the chemical makeup of the source, drain, and gate. Integrated circuits
contain both NMOS and PMOS transistors. The transistors are formed on single-
crystal silicon wafers; the source and drain are built by doping the silicon with
impurities such as arsenic, phosphorus, or boron. Doping with boron adds positive
charge carriers, called holes, to the silicon crystal, making it p-type, while doping
with arsenic or phosphorus adds electrons, making it n-type.

Fig (1):- THE TRANSISTOR STRUCTURE : A positive voltage on the gate of an NMOS
transistor drives positive charge in the channel away from the insulating gate oxide and
attracts electrons, forming a path for electrons to flow.

Taking an NMOS transistor as an example, the shallow source and drain regions are
made of highly doped n-type silicon. Between them lies a lightly doped p-type region,
called the transistor channel—where current flows. On top of the channel lies that thin
layer of SiO 2 insulation, usually just called the gate oxide, which is the cause of the
chip industry's most recent technological headaches.

Overlying that oxide layer is the gate electrode, which is made of partially ordered, or
polycrystalline, silicon. In the case of an NMOS device it is also n-type. (The silicon
gates replaced aluminum gates—the metal in ‗metal-oxide semi conductor‘— But the
‗MOS‘ acronym has nevertheless lived on.)

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 Seminar Report -2010 High K Metal Solution

The NMOS transistor works like this: a positive voltage on the gate sets up an electric
field across the oxide layer. The electric field repels the holes and attracts electrons to
form an -electron-conducting channel between the source and the drain.

A PMOS transistor is just the complement of NMOS. The source and drain are p-
type; the channel, n-type; and the gate, p-type. It works in the opposite manner as
well: a positive voltage on the gate (as measured between the gate and source) cuts off
the flow of current.

In logic devices, PMOS and NMOS transistors are arranged so that their actions
complement each other, hence the term CMOS for complementary metal-oxide
semiconductor. The arrangement of CMOS circuits is such that they are designed to
draw power only when the transistors are switching on or off.

From an electrical stand point of view the MOS structure is equivalent to a parallel
plate capacitor. When a voltage is applied between the gate and source terminals, the
resulting electric field penetrates through the oxide, creating an inversion channel
within the channel underneath. The inversion channel is of the same type of as the
source and drain of the transistor, providing a conduit through which current passes.
The capacitance C of this parallel plate capacitor is

Where
A=capacitor area
K=relative dielectric constant of the material
EO= permittivity of free space
t=thickness of dielectric

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 Seminar Report -2010 High K Metal Solution

(3)MOORE’S LAW
Moore‘s Law– A prediction (not really a law) made by Intel co-founder Gordon
Moore that the number of transistors on a chip double every two years. Intel‘s
microprocessors have followed this ‗law‘ very closely, beginning with the 4004 in
1971, with just over 2000 transistors, and leading up to today‘s Itanium® 2 processor
which has 410 million transistors. In general, transistor density is roughly doubled
with each new process generation, which occurs every two years.

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 Seminar Report -2010 High K Metal Solution

(4)SCALING
Scaling of a device deals with reduction in the size of device as a whole. To enhance
circuit performance, the circuit density must be increased, i.e. no of transistors/chip.
For this device dimensions must be decreased, which implies reduction in gate length
(which is also called minimum feature size L).To maintain the capacitance of MOS
junction, the gate thickness must also be scaled accordingly.
4.1 What to Scale ?
1) Lithographic dimensions known as critical dimension (CD)
a. Gate length and Gate width
b. Contact sizes
2) Oxide thickness
3) Junction depth
4) Supply voltage
4.2 Why to Scale?
1) Improve device performance
- Switching speed increases with shrinking dimensions
a. Shorter transit time
b. Lower capacitance
2) Make smaller chip with same number of transistors
a. Increase in number of chips/wafer
b. number chips/wafer = f(chip area)
c. Increase in chip yield
Y=Y0 exp(-AD0)
where A=chip area and D0= process defect density/cm2
4.3 Improvement in Performance
The drive current Id of a MOSFET can be written using gradual channel
approximation as follows:

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 Seminar Report -2010 High K Metal Solution

 W=width of the channel

 L=channel length
 µ=channel carrier mobility
 COX =capacitance density associated with gate dielectric when the underlying
channel is in the inverted state
 Vg=gate voltage
 Vd=drain voltage
 Vt=threshold voltage
Thus even in this simplified approximation, a reduction in channel length or an
increase in gate dielectric capacitance will result in an increased Id sat .
This implies higher performance.

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 Seminar Report -2010 High K Metal Solution

4.4 Scaling Of Gate Oxide

The key element enabling the scaling of conventional MOSFETS is the excellent
materials and electrical properties of SiO2.Since 1957; SiO2 is being used as the
conventional gate dielectric.

Fig(2 ):- Scaling of physical thickness of SiO2 gate oxide across technology generations.

4.5 Advantages of SiO2 as gate dielectric include:

 SiO 2 is robust, amorphous and thermally grown.
 SiO 2 has good thermodynamic and electrical stability.
 SiO 2 forms a high quality Si-SiO2 interface.
 SiO2 is highly compatible.

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 Seminar Report -2010 High K Metal Solution

(5)SCALING LIMITS AND NEED FOR

ALTERNATE GATE DIELECTRICS
As scaling is done, the gate oxide thickness is made thinner and thinner to maintain
adequate capacitance across it. Scaling limit of SiO 2 is reached when the gate oxide
thickness<20 Å .i.e. less than 2nm.
Need of alternate dielectrics arises due to the following factors:
 Increased leakage current
 Ultra thin SiO2 films
 Penetration of Boron
 Reliability issues
5.1 Increased Leakage Current
As the thickness of gate oxide becomes very small, electrons can tunnel across the
thin gate .The tunneling phenomenon can be explained by the wave nature of electron,
as is described in quantum mechanics. So as the barrier width decreases to a small
value, the Electrons can move across it, even if they do not have the sufficient energy.
Hence, in effect, the leakage current across the gate increases.
5.2 Ultra Thin SiO2 Films
The film is made of two or three monolayer of atoms. The SiO 2 band gap or band
offsets to Si change with decreasing film thickness.
Electron Energy loss spectroscopy is a technique in which a material is exposed to a
beam of electrons with a known range of kinetic energies. Some of the electrons
undergo inelastic scattering which means that they loose energy and have their paths
slightly and randomly deflected. The amount of energy can be measured using an
electron potentiometer and interpreted in terms of what caused the energy loss.
Inelastic interaction include photon reactions, inter and intra band transitions, plasmon
excitations and inner shell ionizations. The inner shell ionizations are particularly
useful for detecting the elemental components of a material. E.g. one may find that a
larger no of electrons comes through the material with a 2 to 5 eV less energy than
what they had entered the material. It so happened that this is about

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 Seminar Report -2010 High K Metal Solution

the amount of energy needed to remove an inner shell electrons from a carbon atom.
This can be taken as the evidence that a significant amount of carbon is present in that
part of the material being hit by the electron beams. Using the wide range of energy
losses one can determine the type of atoms and the no of atoms struck by the beam.
Thickness measurements EELS allow quick and reliable measurement of local
thickness in transmission electron microscope. The most efficient procedure is the
following
 Measure the energy loss spectrum in the energy range about 5 to 200eV (wider
better).Such measurement is quick (milliseconds) and thus can be applied to
materials normally unstable under electron beam.
 Analyze the spectrum :
(1) Extract Zero Loss Peak (ZLP) using standard routines:
(2) Calculate integrals under ZLP (I0) and under whole spectrum (I)
 The thickness t = mfp* ln(I/I0). Here mfp is the mean free path of electron
inelastic scattering, which has recently been tabulated for most elemental
solids and oxides.
The spatial resolution of this procedure is limited by the Plasmon localization and
is about 1 nm, meaning that spatial thickness maps can be measured in scanning
transmission electron microscope with ~1nm resolution
When the electron energy loss spectroscopy (EELS) was carried out on 7-15 Å SiO2
layers on Si, it was indicated that full band gap of SiO2 is obtained after only about
two monolayer of Si channel interface oxygen neighbors and so cannot form the full
band gap that exists within the bulk of SiO2 film. The thickness at each interface
required for the full band gap for SiO2 is therefore 3.5-4 Å. Counting both interfaces;
the total thickness of 7-8 Å is required. These results set an absolute thickness limit of
SiO2 of 7 Å. Below this thickness, an effective short is caused through the dielectric,
rendering it useless as an insulator.
5.3 Penetration Of Boron:
On annealing, Boron diffuses and concentration increases in channel region. This
alters device properties like threshold voltage Vt.This effect is seen in PMOSFETS
only, where in the gate electrode is doped with Boron atoms.

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 Seminar Report -2010 High K Metal Solution

5.4 Reliability Issues:

Thin films under constant stress do not last long. A 15 Å film lasts 10 years under
operating voltage of 1.5 V. Oxide breakdown may occur due to build-up of many
defects in the SiO 2 layer. To overcome these issues, it is high time conventional SiO 2
is replaced by other materials having higher dielectric constants.

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 Seminar Report -2010 High K Metal Solution

(6)HIGH-k DIELECTRICS
Dielectric constant is a term that refers to a material's ability to concentrate an electric
field. Having a higher dielectric constant means the insulator can provide increased
capacitance between two conducting plates—storing more charge—for the same
thickness of insulator. Or it can provide the same capacitance with a thicker insulator
The term high-k dielectrics refer to materials with a high dielectric constant (k) which
may be used in the next generation semiconductor components to replace the SiO 2
gate dielectric, especially for the low standby power (LSTP) applications.

With the continued scaling of thee gate oxide to below 2 nm, leakage currents due to
tunneling and out-diffusion of Boron are very high,so the thickness must be increased
without reducing the associated capacitance.A thick layer can be used with the high–
k material to prevent top-to-bottom metal shortage. So the challenge was to identify a
gate dielectric material as a replacement for SiO 2 .ie a gate insulator that was thick
enough to keep electrons from tunneling through it and yet permeable enough to let
the gate's electric field into the channel so that it could turn on the transistor. In other
words, the material had to be physically thick but electrically thin
There are three types of high-k dielectrics:
Those with 4<k<10 such as SiNx
Those with10<k<100 such as Ta2 O5 , TiO2, Al2 O3
Those with 100<k such as PZT
6.1 Role Of High K
We know the capacitance at the MOS junction is given by:

From the equation decreasing the thickness t will increase the capacitance of the
structure and thereby increase the capacitance of the structure and thereby increased
the number of charges in the channel and the drive current for a fixed value of gate
voltage. However the SiO 2 layer thickness is reaching the limits of scaling. The
alternative way of increasing capacitance is to use an insulator with a higher dielectric
constant than SiO 2

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 Seminar Report -2010 High K Metal Solution

Fig(3 ):- THE HIGH-K WAY: The dielectric constant, k, is a measure of an insulator’s ability
to concentrate an electric field. If one gate oxide has twice the dielectric constant of another,
a given voltage will draw twice as much charge into the transistor channel. Or, the same
amount of charge will accumulate, if the higher-k dielectric is made twice as thick.

6.2 Concept Of EOT

EOT stands for Equivalent Oxide Thickness. It may be defined as the theoretic
thickness of SiO2 required to achieve the same capacitance as the dielectric, ignoring
issues such as leakage and reliability. For example EOT=10 Å implies high- k
dielectric of thickness t has same capacitance as SiO 2 of thickness 10 Å.

Given the EOT as teq the dielectric constant of high-k material as K and the dielectric
constant of SiO 2 as Kox=3.9, as the physical thickness T high-k of the alternative
dielectric can be calculated.

Since K high-k > K ox, we have t high-k > t eq. Thus the physical thickness of the
high-k dielectric is greater than the equivalent oxide thickness. Hence, when the EOT
is small(less than 10 Å), the actual thickness can be higher and hence tunneling etc
can be overcome.

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 Seminar Report -2010 High K Metal Solution

6.2 Advantages Of High-k

In short, the main advantages of these materials may be listed vas follows:
1. Allows greater physical thickness of oxide layer.
2. Improves gate capacitance
3. Reduces leakage, along with present drive current level
4. Overcomes the problems of reliability, boron diffusion etc
6.3 High-K Dielectric candidates,
Aluminum oxide (Al2 O3 ), Titanium dioxide (TiO 2 ), Tantalum pent oxide (Ta2 O5 ),
Hafnium dioxide (HfO 2 ), Hafnium silicate (HfSiO 4 ), Zirconium oxide (ZrO 2 ),
Zirconium silicate (ZrSiO 4 ) , and Lanthanum oxide (La2 O 3 ).
Following current research, compounds of Zirconium and Hafnium hold the most
promise and hafnium silicon oxy nitride (HfSiON) to be more specific

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 Seminar Report -2010 High K Metal Solution

(7)MATERIAL CONSIDERATIONS
The alternate material chosen must satisfy a set of criteria to perform as successful
gate dielectric. Based on the criteria; a number of above mentioned compounds can be
eliminated. Some of the key guidelines are briefed here. They include
1) Permittivity and barrier height
2) Thermodynamic Stability
3) Interface Quality
4) Film Morphology
5) Process compatibility
6) Reliability
7.1 Permittivity & Barrier Height
Selecting a material, with higher permittivity than SiO 2 is clearly essential. The
required permittivity must be balanced, however against the barrier height for the
tunneling process. This is because leakage current density increases exponentially
with decreasing barrier height and thickness according to the equation below'

The following figure gives the band offset calculations for potential high-k materials

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 Seminar Report -2010 High K Metal Solution

Fig(4 ):- Band offset Calculations for High-k Materials

We find that the band gap of SrTiO 3 , Ta2 O5 <0.5 eV, hence they cannot be used. On
the other hand band gaps of Al2 O3 , Y2 O 3 are nearly 2.6 eV and of ZrO 2 , ZrSiO 4 are
around 1.5 eV. Hence they satisfy this requirement.
7.2 Thermodynamic Stability
Most of the high-k metal oxide systems investigated thus far have unstable interfaces
with Si, i.e. they react with Si under equilibrium conditions to form an undesirable
interfacial layer. These materials therefore require an interfacial reaction barrier. Any
ultra thin interfacial reaction barrier with teq, 20 Å will have the same interface
quality,uniformity and reliability concerns as SiO 2 does in this thickness regime. This
is especially true when the interface plays a determining role in the resulting electrical
properties. It is important to understand the thermodynamics of these systems, and
thereby attempt to control the interface with Si. The material should remain stable on
contact with Si even at high temperatures (during annealing).

Eg: Ta2 O 5 on Si forms a layer of SiO 2

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 Seminar Report -2010 High K Metal Solution

Ta2 O 5 , TiO 2 are unstable thermodynamically and hence cannot be used. On the other
hand ZrO2, ZrSiO 4 are stable and HfO 2 , HfSiO 4 are stable and preferable in this
aspect.

7.3 Interface Quality

A clear goal of any potential high-k gate dielectric is to attain a sufficiently high
quality interface with the Si channel, as close as that possible to that of SiO 2 . It is
difficult to imagine any material creating better interface than that of SiO 2 .Interface
state density of SiO 2 is 2×1010 states /cm2 whereas that of most high-k dielectrics is
1012 states/cm2.Hence, it is crucial to understand the origin of the interface properties
of any high-k gate dielectric, so that an optimal high-k- Si interface may be obtained.
The bonding constraints must also be considered at the Si dielectric interface. If the
average no of bonds per atom N avg=3, the interface defect density increases
proportionally, with a corresponding degradation in device performance. Metal oxides
which contain elements with a high coordination such as Ta and Ti will have high
Navg, and forms an over constrained interface with Si. Degradation in leakage current
and electron channel mobility is therefore expected. Similarly, cations with low
coordination e.g. Ba, Ca compared to that of Si lead to under constrained systems in
the corresponding metal oxides. These lead to formation of a high density of electrical
defects near the Si dielectric interface resulting in poor electrical properties. Presence
of unsatisfied bonding locations give rise to dangling bonds that act as oxygen
vacancies and electron trap sites. This degrades electron mobility and effects
threshold voltage etc. Al2 O3 , Y2 O 3 , and La2 O3 have high defect densities and are
consequently undesirable.

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 Seminar Report -2010 High K Metal Solution

7.4 Film Morphology

Most of the advanced gate dielectrics studied to date is either polycrystalline or single
crystal films, but it is desirable to select a material which remains in glassy phase
(amorphous) throughout the necessary processing treatments. Polycrystalline gate
dielectrics may be problematic because grain boundaries serve as high leakage paths,
and this may lead to the need for an amorphous interfacial layer to reduce leakage
current.
In addition, grain size and orientation changes through out a polycrystalline film can
cause significant variations in k, leading to irreproducible properties. Single crystal
oxides grown by MBE methods can avoid grain boundaries while providing a good
interface, but these materials also require a sub monolayer deposition control, which
may only be obtained by MBE. Given the concerns regarding polycrystalline and
single crystal films, it appears that an amorphous film structure is the ideal one for the
gate dielectric, like HfSiO 4 , ZrSiO 4 .
7.5 Process Compatibility
A crucial factor in determining the final film quality and properties is the method by
which the dielectrics are deposited in a fabrication process. The deposition process for
the dielectric must be compatible with the current or expected CMOS processing,
cost, and throughput. The method in use includes Physical Vapor Deposition (PVD),
Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD) and Molecular
Beam Epitaxy (MBE).
Physical Vapor Deposition (PVD):
Used to deposit thin films-one atom at a time on to various surface. Coating surface is
physical rather than chemical as in CVD.
Chemical vapor deposition (CVD):
Here wafer is exposed to one or more precursors which react or decompose on a
surface to produce desired deposit. The various reaction steps involved are:
1) Vaporization and transport of the precursor molecules into the reactor.
2) Diffusion of precursor molecules on the surface
3) Adsorption of precursor molecules to surface
4) Decomposition of precursor molecules to the surface and incorporation to solid
films
5) Recombination of molecular byproducts and desorption to gas phase.

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 Seminar Report -2010 High K Metal Solution

Atomic Layer Deposition (ALD):

It takes place at about 200-400 Celsius. It is similar to CVD except it breaks CVD
into two half reactions keeping precursor materials separate throughout coating
process atomic layer control or film grown can be obtained as fine as 0.1 Å.
Advantages of ALD are that it produces conformal, pinhole free layer chemically
bonded to the substrate.
Molecular Beam Epitaxy (MBE):
It takes place in high vacuum. Substrate is held high in vacuum. It has slow deposition
rate. In Solid beam Epitaxy ultra pure elements like Ga and As is heated in separate
cells until they slowly begin to evaporate. Evaporated elements condense on water
where they may react with each other. The term beam simply means that evaporated
atoms do not react with one another or any other vacuum chamber gases until they
reach wafer long free path of beams.
During operation RHEED (Reflection High Energy Electron Diffraction) used for
monitoring growth of crystal layers. A computer controls shutters in front of each
furnace, allowing precise control of thickness of each layer to single layer of atoms.
Thus the rate at which atomic beam strikes surface can be closely controlled and
growth of high quality crystal result. Sample is held at relatively lower temperature
7.6 Reliability
The electrical reliability of a new gate dielectric must also be considered critical for
application in CMOS technology. The determination of whether or not a high-k
dielectric satisfies the strict reliability criteria requires a well characterized materials
system. We have to consider the dependence of voltage acceleration extrapolation on
dielectric thickness and the improvement of reliability projection arising from
improved oxide thickness uniformity.
The material must be stable in contact with the gate electrode. In this aspect, HfO 2 ,
Al2 O 3 are very reliable where as ZrO 2 is unreliable

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 Seminar Report -2010 High K Metal Solution

(8)NEW CHALLENGES ASSOCIATED WITH

HIGH K SOLUTION

The different challenges include:

1) Method of deposition
2) Availability of precursors
3) Formation of interfacial layers
4) Phonon Scattering & low charge-carrier mobility
8.1 Method Of Deposition
A major uncertainty facing material suppliers is whether the semiconductor industry
will adopt CVD or ALD as its high-k deposition method of choice. ALD (Atomic
Layer Deposition) is a newer technology that is intriguing to chip fabricators because
it uses a pulsing technique to deposit incredibly thin layers one at a time. It is different
from CVD in the fact that CVD is more temperature sensitive In this technique, the
compound layer is formed through layer by layer deposition of the precursor atoms in
short pulses. This results in a highly uniform and well-controlled deposition process.
Fig shows a schematic representation of this ALD process

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 Seminar Report -2010 High K Metal Solution

The different steps in ALD in include (as an e.g. consider deposition of ZrO 2 ):
1) Vapor such as MCl4 is introduced into a process chamber.
2) Vapor forms an absorbed monolayer on the surface of the wafer.
3) Water vapor is introduced into the chamber.
4) Water vapor and MCl4 produce one monolayer of MO 2 .
But ALD process is very slow and has a very small throughput. This challenge posed
by the deposition process is yet in consideration. Considering CVD (Chemical Vapor
Deposition), it consists of a group of wafers placed in vacuum chamber where
chemical vapors are thermally reacted at lower pressure to deposit film on the wafer.
Deposition process is continuous. Vapor flows continuously into chamber during the
deposition cycle. Deposited film thickness depends on temperature, pressure, gas flow
etc. While in ALD deposited film thickness depends only on the no of deposition
cycles. More recently ATMI developed a unique solid Hafnium precursor delivery
system called ProE Vap that is designed to help deposit hafnium tetrachloride, a
leading candidate to be used with the ALD technique.

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8.2 Availability Of Precursors

Chemical companies have the added challenge of appropriate precursor molecules.
For Hafnium oxide, candidate precursors include tetrakis (dimethylamino) hafnium,
tetrakis (diethylamino) hafnium, tetrakis (ethylmethylamino) hafnium, and hafnium
tetrachloride. These precursors are placed in a CVD or an ALD chamber, where they
are heated, vaporized,and uniformly deposited as hafnium oxide or silicate on a
silicon surface.
To be a successful a precursor, a compound must be able to survive the heating
process but then be able to breakdown on command on the silicon substrate. It must
also interact properly with the substrate so an amorphous rather than a crystalline film
is formed. Precursor must be volatile and thermally stable to ensure efficient
transportation so that reactions will not precursor transport controlled. Vapor pressure
of precursor should be high enough to completely fill the deposition chamber so that
monolayer deposition takes place within a reasonable length of time. Precursors must
chemosorb onto surface or rapidly react with surface gaps and aggressively with each
other to keep deposition time short.
8.3 Formation of Interfacial Layer
High-k dielectric has high density of interface states even if they are
thermodynamically stable. Almost all materials form these interfacial layers which
have a finite thickness and a solution to this problem or at least the minimization of its
effects is essential. This is one of the major challenges, as a result of which SiO2 is
yet to be replaced completely.
When the interfacial layer is formed, this layer will have a different dielectric constant
and as a result the overall capacitance of the junction maybe compromised, because
the actual physical thickness of the pure high-k dielectric is lesser then.

8.4 Phonon Scattering & Low Charge Carrier Mobility

When high K NMOS and PMOS transistors were made. Then came the next snag.
These transistors, pretty much identical to our existing transistors except for the
different dielectric,

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had a few problems. For one thing, it took more voltage to turn them on than it should
have—what's called Fermi-level pinning. For another, once the transistors were ON,
the charges moved sluggishly through them—slowing the device's switching speed.
This problem is known as low charge-carrier mobility.
The source of the trouble is the interaction between the polysilicon gate electrode and
the new high-k dielectrics.

The dielectric layer is made up of dipoles—objects with a positive pole and a negative
one. This is the very aspect that gives the high-k dielectric such a high dielectric
constant. These dipoles vibrate like a taut rubber band and lead to strong vibrations in
a semiconductor's crystal lattice, called phonons. These phonons knock around
passing electrons, slowing them down and reducing the speed at which the transistor
can switch.
Solution :- The simulations indicated that the influence of dipole vibrations on the
channel electrons can be screened out by significantly increasing the density of
electrons in the gate electrode. One way to do that would be to switch from a
polysilicon gate to a metal one. As a conductor, metal can pack in hundreds of times
more electrons than silicon. Experiments and further computer simulations confirmed
that metal gates would do the trick, screening out the phonons and letting current flow
smoothly through the transistor channel. What's more, the bond between the high-k
dielectric and the metal gate would be so much better than that between the dielectric
and the silicon gate that other problem, Fermi-level pinning, would be solved by a
metal gate as well.

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 Seminar Report -2010 High K Metal Solution

(9) NEW CHALLENGES ASSOCIATED

WITH HIGH K METAL SOLUTION
9.1 Finding a metal that could be used for the gate electrode that
would combine well with the new high-k dielectric .
Just as standard MOS transistors use n-type and p-type polysilicon gates for NMOS
and PMOS transistors, high-k transistors would need metal gate electrode materials
with a key property similar to polysilicon's. This key property is known as the work
function. In this context, work function refers to the energy of an electron in the gate
electrode relative to that of an electron in the lightly doped silicon channel. The
energy difference sets up an electric field that can modulate to the amount of voltage
needed to begin to turn the transistor on, the threshold voltage. Unless the gate's work
function is chosen well, the threshold voltage will be too high, and the transistor will
not turn on easily enough.

Gate electrodes with the ―right‖ work function are required for high-performance
CMOS applications

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 Seminar Report -2010 High K Metal Solution

9.2 Adopting New Fabrication Method

The normal fabrication method is known as ―gate first.‖ As the name implies, the gate
dielectric and gate electrodes are constructed first. Then the dopants for the source
and drain are implanted into the silicon on either side of the gate. Finally, the silicon
is annealed to repair the damage from the implantation process. That procedure
requires that the gate electrode material be able to withstand the high temperatures
used in the annealing step—not a problem for polycrystalline silicon but potentially a
big one for some metals. Another transistor process sequence, dubbed ―gate last,‖
circumvents the thermal annealing requirement by depositing the gate electrode
materials after the source and drain are formed. However, the gate-last process was
ultimately adopted by the chip industry but it was too challenging. A third approach
called fully silicided gates, follow the normal gate-first process and then turn the
polysilicon gate into a metal-silicide gate, essentially replacing every other silicon
atom with metal (usually nickel). Then, by doping the nickel silicide, you can alter its
work function for use in either an NMOS device or a PMOS one. By late 2006,
though, nearly everyone had given up on the fully silicided gates approach due to
difficulty in controlling silicide's work function quite close enough to where it needed
to be.

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 Seminar Report -2010 High K Metal Solution

(10) PROBLEM SOLVED

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 Seminar Report -2010 High K Metal Solution

(11) CONCLUSION
In the current CMOS industry, high-k dielectrics have a significant role to play in
further miniaturization. Hence very soon SiO 2 will be completely replaced by these
materials as gate oxides in MOSFETS. This significantly reduces tunneling and other
issues related to ultra thin SiO 2 films. Various material considerations having been
taken into consideration, Hafnium based compounds hold the most promise as the
next generation gate oxide, HfSiON in particular.
Intel made the first working 45-nm microprocessors using these revolutionary high-k
plus metal gate transistors. One was the Penryn dual-core microprocessor, which has
410 million transistors. The quad-core version of this product will have 820 million
transistors. Penryn was followed a few months later by Silverthorne, a single-core
microprocessor with 47 million transistors that is designed for low-power
applications, including mobile Internet devices and ultramobile PCs. There are more
than 15 new chips under development at Intelusing our new technology.
The invention of high-k plus metal gate transistors was an important breakthrough.
Although the Chip industry could have continued to shrink transistors to fit the
dimensions needed for the 45-nm generation without this breakthrough, those
transistors would not have worked much better than their predecessors, and they
certainly would have expended more watts. This new transistor can be scaled further,
and development is already well under way on our next-generation 32-nm transistors
using an improved version of high-k plus metal gate technology. Whether this type of
transistor structure will continue to scale to the next two generations—22 nm and 16
nm—is a question for the future. Will we need new materials and new structures
again?

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 Seminar Report -2010 High K Metal Solution

(12) REFERENCES
(1) Mark T Bohr,Robert S Chau,Tahir Ghani & Kaizad Mistry ― The High K
Solution‖,IEEE SPECRTUM December 2007
(2) Robert Chau ―Gate Dielectric Scaling for High Performance CMOS from
SiO2/Poly Silicon to High K/Metal Gate ‖, Intel Fellow Technology and
Manufacturing Group November 2003
(3) Robert Chau, Suman Datta, Mark Doczy, Jack Kavalieros and Matthew Metz
Gate Dielectric Scaling for High-Performance CMOS: from SiO2 to High-K, Intel
Corporation
(4) Jeffrey Hicks, Daniel Bergstrom, Mike Hattendorf, Jason Jopling, Jose
MaizSangwoo Pae, Chetan Prasad, Jami Wiedemer, Logic Technology
Development, Intel Corporation ―45nm Transistor Reliability‖, Intel® Technology
Journal Vol 12 Issue 2, June 17 2008
(5) Robert Chau, Senior Member, IEEE, Suman Datta, Member, IEEE, Mark Doczy,
Brian Doyle, Jack Kavalieros, and Matthew Metz , ―High-_/Metal–Gate Stack
andIts MOSFET Characteristics‖IEEE ELECTRON DEVICE LETTERS, VOL. 25,
NO. 6, JUNE 2004
(6) ―Intel‘s Breakthrough in High-K Gate Dielectric Drives Moore‘s Law Well into
the Future‖ Technology@Intel Magazine January 2004
(7) K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M. Brazier, M
Buehler, A. Cappellani, R. Chau*, C.-H. Choi, G. Ding, K. Fischer, T. Ghani, R.
Grover, W. Han, D. Hanken, M. Hattendorf, J. He#, J. Hicks#, R. Heussner, D. L.
Pipes, M. Prince, P. Ranade, T. Reynolds,J. Sandford, L. Shifren%, J. Sebastian, J.
Seiple, D. Simon, S. Sivakumar,P. Smith, C. Thomas, T. Troeger, P. Vandervoorn, S.
Williams, K. Zawadzki ―45nm Logic Technology with High-k + Metal Gate
Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and
100% Pb-free Packaging‖ Portland Technology Development, *CR, #QRE, %PTM
Intel Corporation
(8) W. Haensch,E. J. Nowak,R. H. Dennard,P. M. Solomon,A. Bryant,O. H.
Dokumaci,A. Kumar,X. Wang,J. B. Johnson,and M. V. Fischetti ―Silicon CMOS
devices beyond scaling‖. IBM Journel Of Research and Development Advanced
Silicon Technology Volume 50,
Number 4/5, 2006

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GEC Kozhikkode 29 Department of AE&I