International Journal of Research in Advanced Technology - IJORAT

Vol. 1, Issue 8, SEPTEMBER 2016

Implementation of 8-Port Adaptive Network

On-Chip Architecture Using VLSI Technique
K. Karthika1, C.Kohila2
Assistant Professor, ECE, PSNACET, Dindigul, India 1
Assistant Professor, ECE, PSNACET, Dindigul, India 2
Abstract: Networks-on-chip have emerged as a promising on-chip interconnect for future multi/many-core
architectures as Networks-on-chip area unit ready to scale communication links with the growing variety of cores.
Progressive Networks-on-chip styles rely in the main on a static network configuration using fastened routing
algorithms and buffer placements. This approach does not seem to be effective in coping with hard-to-predict
system behaviour. This drawback is solved by using runtime adaptational network-on-chip. Adaptational route
allocation rule that provides a needed level of quality of services in addition to associate adaptational buffer
assignment theme that reassigns buffer blocks on-demand. The area overhead is additionally reduced by resource
multiplexing because of the on-demand buffer assignment at every output port. This project proposes a brand new
router topology that is employed to scale back the network size and routing time, An appropriate alternate to
network style and implementation and a brand new adaptational routing rule for 8-port router design. The
mathematician Network-On-Chip is simulated using VLSI Technique.
I. INTRODUCTION
In this paper, we tend to provide a technique to design
extremely adaptive
routing algorithms for NOC
architectures that don't need the utilization of any VCs. the
essential plan behind the projected approach is summarized
as follows: historically, within the general domain, a routing
algorithmic program is intended based mostly only on the
constellation. As there's no data regarding the applying
which will be mapped on the system, the routing algorithmic
program should guardedly guarantee any two network nodes
to speak.
On the contrary, within the embedded system domain,
the designer typically has associate in-depth information of
the applying which will be mapped on the system. If we tend
to contemplate the canonical design flow of associate NoCbased embedded system[2], when the task mapping section,
we have got the knowledge regarding the set of pairs of
cores that communicate and alternative pairs that never
communicate. When the task programming section of
system development, we will able to even have data
regarding the set of communication transactions that are
coincidental and others that are no concurrent. We tend to
benefit of those characteristics to extract adaptivity free.
II. CARTESIAN NETWORKS
Cartesian routing could be a quick
packet routing
mechanism supposed for geographic addresses and might
effectively accelerate the packet routing method among an
area or metropolitan surroundings[3]. The wide space
Cartesian routing represented in this paper is associate
degree extension of the Cartesian routing algorithms

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designed to form the exchange of net work packets between

nation-states potential. It additionally introduces a
replacement hierarchical data structure for the complete
web. The projected web is viewed as a hierarchy of networks
consisting of routers. At the best level of this hierarchy,
major routers exchange packets between large geopolitical
areas like countries, states. There area unit solely four layers
during this structure and at every layer Cartesian routing is
employed to send packets from the supply router to the
destination. The wide-area Cartesian Routing rule
overcomes these issues by making a stratified network
consisting of two or a lot of layers. Every network at a given
layer encompasses one or a lot of networks[4]. two
extensions to the first Cartesian Routing rule area unit
required, each network needs a web work router which will
direct packets destined for different networks up to the
encircling network. The address structure reflects the
network structure, with specific fields within the address
related to every layer.
A. Cartesian Network Initialization
In Cartesian routing, every arterial problems arterial this
manner (ATW) management packets throughout its format
method. Associate degree ATW tells the receiving collector
router if associate degree arterial is accessible through the
incoming port. Associate degree ATW additionally specifies
what reasonably association is accessible via the incoming
port: north, south, north and south or neither[6]. Upon
receiving associate degree ATW, every collector router
updates its blood vessel Direction Indicator (ADI) and
forwards the ATW to the other port. ATWs also are used to
establish Virtual Arterials, made in things wherever it is

International Journal of Research in Advanced Technology - IJORAT

Vol. 1, Issue 8, SEPTEMBER 2016

physically not possible for associate degree arterial to span

two collectors. The ADI points within the direction of the
blood vessel router (i.e., east or west) and indicates whether
or not the arterial router features a association to the north,
the south, or both.
B. Cartesian Routing
Packets will arrive on either a west or east port of a
collector router. Packets intended for a distinct latitude area
unit forwarded out the other port from that they are received.
The ADI determines the packets initial direction on the
collector router once a packet arrives on the bottom port of a
collector router[5]. When deciding a packets initial
direction, the router initially compares the packets
destination address with its own address[7]. The packet are
going to be forwarded within the direction of the destination
if the destination latitude is that the same as the collectors.
The packet is forwarded within the direction of the ADI if
the destination is on totally different latitude.

A. Architecture
The modified Weighted XY-routing (WXY-routing)
algorithmic rule given assigns every output port a weight
supported offered bandwidth and therefore the coordinate
(columns) distance or the coordinate (rows) distance
between this and therefore the destination node. This ideally
provides the packet a most variety of wise routing selections
on its route because it enable the packet to be routed toward
its destination in each the directions. The weight is
additionally proportional to the offered bandwidth. If the
output port is chosen with the very best associated offered
bandwidth, the used bandwidth is distributed as equally as
possible among the output ports. Thus, the opposite output
ports are additional possible to be able to accommodate
future transactions. By permitting each value to contribute to
the weight, the weight becomes a trade-off between these
two issues.

III. ROUTER STRUCTURE

Signal arrives

Packet passed

Incoming packet
warning

Signal leaves

Packet from
ipsaY

signal

Signal from
ipsY

Pass packet to opsX

Fig.1. Router Structure

IV. MODIFIED WXY ROUTING ALGORITHM

In WXY routing algorithm route is checked in only four
possible directions where as in case of modified WXY
routing algorithm route is checked in eight possible
directions. Instead of using 4-port here we are using 8-port
so we can reduce traffic density. So that we can reduce
latency. The incoming packet structure consists of start of
packet (SOP), end of packet (EOP), both the SOP and EOP
should be 6 bits wide and all the 6 bits should be one if it is
not the packet will be discarded. DLAT and DLONG is
nothing but destination latitude and destination longitude
both should be 5 bits wide and this should be assigned by
OSI layer protocol. NODE LAT and NODE LONG is
nothing but node latitude and node longitude it is assigned to
the router. Then the packet structure consists of DATA

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Fig.2. Architecture of Modified WXY routing Algorithm for 8-port.

B. Algorithm
Step 1: The packet is send from west direction, if
destination latitude equal to node latitude and destination
longitude equal to node longitude means the packet will be
holded.

International Journal of Research in Advanced Technology - IJORAT

Vol. 1, Issue 8, SEPTEMBER 2016

Fig.3. Flow Chart of Modified WXY routing Algorithm for 8-Port

Structure

Step 2: If destination latitude greater than node latitude

and destination longitude is equal to node longitude means
the packet will send into North direction.
Step 3: If destination latitude is less than node latitude and
destination longitude is less than node longitude means the
packet will be send in southwest direction.
Step 4: If destination latitude is greater than node latitude
and destination longitude is less than node longitude means
the packet will be send in northwest direction.
Step 5: If destination latitude is greater than node latitude
and destination longitude is greater than node longitude
means the packet will send in northeast direction.
Step 6: If destination latitude is less than node latitude and
destination longitude equal to node longitude means the
packet will send in south direction.
Step 7: If destination latitude is equal to node latitude and
destination longitude is less than node longitude means the
will be holded.
Step 8: If destination latitude equal to node latitude and
destination longitude is greater than node longitude means
the packet will be send in east direction.
Step 9: If destination latitude is less than node latitude and
destination longitude is greater than node longitude means
the will send in southeast direction.

Fig.4. Simulation Result of Modified WXY Routing Algorithm for

Southwestport.

Fig.5. Simulation Result of Modified WXY Routing Algorithm for

Northeast direction

V. RESULT
In modified WXY routing algorithm I have designed one
router it consists of 8-ports and the delay introduced is
6.13sec and the Device utilization summary is Number of
Slices:72 out of 4656, Number of Slice Flip Flops:102 out
of 9312, Number of 4 input LUTs: 40 out of 9312,
Number of IOs:291,Number of bonded IOBs:291 out of 158,
IOB Flip Flops:144,Number of GCLKs:5 out of 24

Fig.6. RTL schematic view of 8-port router

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International Journal of Research in Advanced Technology - IJORAT

Vol. 1, Issue 8, SEPTEMBER 2016

III. CONCLUSION
AdNoC architecture is the first approach of
adaptive on-chip communication architecture. It provides an
adaptive route allocation algorithm to meet changing
bandwidth guarantees an on-demand buffer block
assignment scheme for runtime connection establishment
between a data producer and a data consumer. AdNoC
architecture is complimented by a monitoring component for
providing runtime observability. It is hardly intrusive, Due
to our runtime observability scheme, AdNoC increases the
connection success rate compared with state-of-the-art
approaches. Furthermore, we have provided the first
prototype of the AdNoC architecture in FPGA that can
efficiently cope with hard-to-predict system behavior at
runtime.Our proposed modified WXY routing algorithm
scheme increases the on-chip resource utilization and
decreases the overall buffer use, compared to fixed number
of buffer blocks is tied to the output port. The entire area
overhead is traded off against the flexibility to select
available route and the latency is reduced.

Fig.7. Technology schematic view of 8-port router

HDL Synthesis Report
Macro Statistics
# Latches
10-bit latch
36-bit latch
5-bit latch
# Comparators
36-bit comparator not equal
5-bit comparator greater
5-bit comparator less

: 14
:2
: 10
:2
:6
:3
:1
:2

REFERENCES

Device utilization summary

Selected Device: 3s500epq208-4
Number of Slices
Number of Slice Flip Flops
Number of 4 input LUTs
Number of IOs
Number of bonded IOBs
IOB Flip Flops
Number of GCLKs

:
:
:
:
:
:
:

72 out of 4656
102 out of 9312
40 out of 9312
291
291 out of 158
144
5 out of 24

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Fig.8. Timing Report of 8-port router

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