Ref: AC108/ST/WP0/DR-P/104b.

Project Number: AC108

Project Title: DVBird
(Digital Video Broadcasting integrated receiver decoder)
Deliverable Type: P (Public)

CEC Deliverable Number: D19

Contractual Date of Delivery to the CEC: December 1997

Actual Date of Delivery To the CEC: July 1998

Title of Deliverable:
Final Project Report

Workpackage contributing to the deliverable: WP0

Nature of Deliverable: R (= report)

Authors: F. Scalise

Abstract:

At the end of the DVBird project this report summarizes the results and the
achievements gathered during the whole project duration. The current large
discussion on Digital Terrestrial TV in Europe and all over the world in the
consumer market allows to place particular emphasis on exploitation of the project
results and success stories.

Keyword list:

Digital terrestrials TV, DVB-T, silicon solutions, VLSI, lab tests, demonstrations,
COFDM, demodulation, channel estimation, channel decoding.
Contents

ABSTRACT: .......................................................................................................................................... 1

KEYWORD LIST:................................................................................................................................. 1

CONTENTS ........................................................................................................................................... 2

1 INTRODUCTION .......................................................................................................................... 3

2 BACKGROUND AND PLAN OF THE DVBIRD PROJECT....................................................... 5

3 DIGITAL TERRESTRIAL TV TODAY ....................................................................................... 8

3.1 DTTV IN EUROPE ...................................................................................................................... 8
3.1.1 France............................................................................................................................... 8
3.1.2 The Netherlands ................................................................................................................ 8
3.1.3 United Kingdom ................................................................................................................ 9
3.1.4 Sweden.............................................................................................................................. 9
3.1.5 Finland ............................................................................................................................. 9
3.1.6 Spain................................................................................................................................. 9
3.1.7 Italy................................................................................................................................... 9
3.1.8 Portugal .......................................................................................................................... 10
3.1.9 Germany ......................................................................................................................... 10
3.2 DTTV OUTSIDE E UROPE .......................................................................................................... 10
3.2.1 Australia ......................................................................................................................... 10
3.2.2 China .............................................................................................................................. 11
3.2.3 Japan .............................................................................................................................. 11
3.2.4 New Zeland ..................................................................................................................... 11
3.2.5 Singapore ........................................................................................................................ 11
3.3 THE ROLE OF THE SILICON TECHNOLOGY ................................................................................... 11
4 PROJECT ACHIEVEMENTS..................................................................................................... 13
4.1 TECHNICAL ACHIEVEMENTS ..................................................................................................... 13
4.2 DVBIRD CHIP SET FEATURES ................................................................................................... 17
4.2.1 IC1: I/Q Generation and OFDM Demodulation ............................................................... 17
4.2.2 IC2: Channel Estimation and Correction ......................................................................... 18
4.2.3 IC3: Channel Decoding ................................................................................................... 19
4.2.4 IC4: Synchronisation and Control.................................................................................... 20
4.3 HARDWARE DEMONSTRATOR AND PRACTICAL EXPERIMENTATION ............................................. 21
5 DVBIRD SUCCESS STORY........................................................................................................ 22
5.1 1996: THE FIRST EFFORT .......................................................................................................... 22
5.2 1997: THE DVB-T CHIP SET IS HERE!........................................................................................ 22
5.3 1998: DVBIRD IS TOUCHING THE SOUTHERN HEMISPHERE ......................................................... 23
6 CONCLUSIONS........................................................................................................................... 25

7 REFERENCES ............................................................................................................................. 26

8 ANNEX 1 ...................................................................................................................................... 29

2
1 Introduction

Digital TV is currently the main topic of technical discussion in the field of

consumer electronics. A lot of work has been carried out in all the fields of consumer
applications that have been recently affected by digital techniques; such process has
been called “digitalization” or “digital revolution” in newspapers and magazines,
describing the advantages of digital techniques over analog existing ones. To support
this process, relevant results have been obtained in video compression techniques
and standards (MPEG), audio and video processing, video recording, format
conversion, etc. Moreover, traditional techniques of the information theory have
been well exploited, both from the algorithmic point of view and from the
architectural hardware implementation. The key point of the introduction of digital
techniques in consumer electronics is that digital data are just made of a suitable
combination of binary information (0,1). Therefore, powerful methods are now
needed to protect your digital data from errors during storage, transmission and
processing (channel coding and forward error correction).

To take advantage of this revolution, most of the European consumer

electronic companies and research centers have placed a huge effort trying to meet
both the continuously increasing user requirements and the flexibility and
programmability issues. The problem is to choose the best solution for an acceptable
tradeoff in the short term as well as in the long one. Particular stress was put on the
exploitation of an efficient technique for channel coding and modulation for all the
three main transmission media, i.e. terrestrial, cable and satellite.

In this field several results have been obtained within the European
Programmes (EUREKA, RACE), with several projects that have been launched in
the last five years. Up to now, the three types of transmission (cable, satellite,
terrestrial, UHF/VHF) have been studied and implemented separately, since the
characteristics of the transmission channel are quite different in the three cases. This
is surely the best solution for the short-term market, since there is a lot of pressure
for an early introduction of digital TV services by satellite and cable and now even
terrestrial broadcasting.

As far as the terrestrial transmission is concerned, specific problems had to be

solved, such as multipath propagation and co-channel interference, thus requiring the
introduction of a specific algorithmic solution for signal modulation (Orthogonal
Frequency Division Multiplex, OFDM). This additional effort somewhat delayed,
comparing to satellite, the introduction of an efficient terrestrial digital service to
replace the current analog TV transmission. For this reason, the European solution
(DVB-T standard) has been fixed and standardized only in early 1996.

3
 After this investigation period, the key challenge was to arrive to an
integrated receiver, based on the current silicon CMOS technology, with the aim of
providing the market with a digital terrestrial TV terminal at reasonable cost. For this
reason, the DVBird project has been started in early 1996.

DVBird

Digital
Video
Broadcasting
integrated
receiver
decoder

4
2 Background and plan of the DVBird project

Up to the end of 1995, the main framework for the technical investigations on
Digital Terrestrial TV Broadcasting was the RACE 2082 dTTb project (digital
Terrestrial TV broadcasting, 1992-1995) [1]. Such project was sponsored by the
European Commission, with the aim of contributing to the establishment of an
European standard and corresponding technologies for a Terrestrial Digital TV
Broadcasting Service. Other projects (e.g. Scandinavian HD-DIVINE and German
HDTVT) started a parallel activity on these topics on a regional basis with a tight link
with the dTTb project. More that 40 partners were part of dTTb and the most of the
project duration was spend in investigating the different algorithmic proposal for the
DTTV system, as well as in prototyping a hardware module to perform lab tests and
field trials all over Europe. The result of this long work was the definition of the first
draft of the system specification and the manufacturing of a hardware demonstrator
(in two subsequent releases) including both the transmitter and the receiver part. The
2nd dTTb demonstrator [2] (with some slight modifications) is still circulating among
former dTTb lab partners and broadcasters, to witness how relevant was the result of
that project

In parallel to the dTTb project, the European Digital Video Broadcasting

(DVB) consortium has been established to coordinate all the work carried out in
Europe in the field of Digital TV. The primary aim of DVB is, among other tasks, to
finalizing and assessing the specification of a Baseline System for Terrestrial (DVB-
T), satellite (DVB-S) and cable (DVB-C) Digital TV Broadcasting and to prepare the
submission to ETSI for standardization. In particular, the DVB-T [3] standard has
been agreed by the DVB members and submitted to ETSI in early 1996 to provide a
reference specification for the development of prototype integrated receivers beyond
the dTTb work.

After the DVB-T finalization, the effort has been concentrated on the next
step towards the finalization of the work, that is, in view of the introduction of a
Digital terrestrial TV service in Europe; the target date is now the end of 1998. Once
the paper specification was agreed in the framework of DVB, it was necessary to
demonstrate that the proposed system is feasible and that consumer receivers can be
manufactured at a reasonable price. This step is critical to implement a real service
(not a pilot service or a field trial).

Therefore, in accordance with the ACTS program, the DVBird project was
started in January 1996 comprising most of the dTTb partners originally involved in
complexity estimation of a VLSI solution (Module 7 of dTTb). According to the
above mentioned requirement, the main aim of DVBird project was agreed as to
develop an optimized an integrated chip set for Digital terrestrial TV receiver,

5
according to the DVB-T standard. To reach this goal, the intermediate objectives of
DVBird project were:

1. Starting from the specification of the second dTTb demonstrator and from the
final DVB-T specification of baseline system, taking into account user
requirements and complexity issues, the definition of the receiver architecture
for Digital Terrestrial TV Broadcasting was finalized. The main result of this
preliminary work has been the specification, design and prototyping of a first
generation chip set for Digital terrestrial TV Broadcasting to support the early
introduction of such a service in the market. To achieve this, the consortium
took great benefit from the results of dTTb, being compliant to DVB-T
specification.
2. After that, the development of a first hardware demonstrator for Terrestrial
Digital TV Broadcasting (receiver part only) was carried out, from the
specification mentioned in point 1, based on the ICs of the new chip set
developed inside the DVBird project. This demonstrator was also intended to
be delivered to other ACTS projects, e.g. VALIDATE, to carry out field trials
for service planning and design validation purposes. Such a demonstrator was
also intended to be an effective way to broadcast the knowledge among DVB
and other European companies to develop future market-oriented products
(receivers, TV sets) related to Terrestrial Broadcasting of Digital TV signals.
3. Starting from the result of the tests on the DVBird demonstrator, a further
algorithmic and architectural study was planned with the purpose of defining
the specification of an improved second-generation receiver for Digital
terrestrial TV Broadcasting. Key issues like better channel equalization or
synchronization algorithms are some of the open issues covered in this phase
of the project

To reach the above-mentioned goals the project partners made extensive use
of state-of-the-art foundry facilities and sub-micron CMOS technology within
Europe, in order to stress the VLSI complexity of the receiver. Such issue is strategic
because in the real market the trend is towards the integration of more and more
large system on a single chip to cut down the cost of the final terminal for the user. In
view of this, the development of more optimized algorithms featuring efficient
hardware architectures is a key issue.

The last phase of the project is meant as the natural continuation of the work
performed within the first phase, in view of establishing, assessing and validating the
system and architectural knowledge towards the definition of more reliable products
and services.

Moreover, the case of DTTV in Europe is even more complex. The “1998”
target date for the introduction of the first regular service of terrestrial digital TV in

6
Europe (UK and Sweden) has considerably increased the amount of field trials and
lab tests to be performed on the available DVB-T equipment, including integrated
receivers like the one developed within DVBird. As a consequence, to meet the
actual market perspectives, the amount of work of the DVBird partners dedicated to
the specification, development, simulation and testing of the DVBird VLSI solution
has been increased, comparing to the first commitments decided during the
preparation of the DVBird proposal in autumn 1995.

Such consideration is important to understand the problems encountered

during the project period. To be ready for the market within 1998, the silicon
manufacturers inside the project Decided to start the real consumer production plans
even before the end of the DVBird project, that was meant to be a preliminary
prototyping phase. This increases the problems of confidentiality among the DVBird
partners.

Therefore, the importance of the work performed within the DVBird project
goes beyond a pure system research and a lab prototyping; such project has been a
real “market driver” for DVB-T standard, rather than a pure Research &
Development project.

7
3 Digital Terrestrial TV today

To understand the importance of the work performed within the DVBird

project, it is worth to briefly review the status of the introduction of Digital
terrestrial TV in Europe and outside Europe as part of the global “digitalization”
process of consumer electronics. It is very important to understand the volume of
the potential market and the heavy problems involved in the transition from analog
to digital services (e.g. simulcasting, frequency planning, interference, receiver
costs, interoperability of standards).

3.1 DTTV in Europe

After the huge amount of technical investigations during the last five years,
the DTTV in Europe is now moving quickly towards the introduction of the real
service, as a consequence of the dramatic improvements in silicon technology.
Two countries are on the leading edge, UK and Sweden, and they plan to
introduce a real DVB-T service around the end of 1998 or early 1999 at the latest.
Thanks to the work made in these two countries and the exchange of information
in the framework of the European Commission and the DVB organization, all
major European countries are now coming out with detailed plans to set up a
DVB-T service in the next future. In the rest of this chapter some considerations
recently issued [4] on the status of this process in the major European countries
and in some other countries worldwide will be given, with special focus on those
countries that are oriented to DVB-T.

3.1.1 France

In January 1998 the French Prime Minister announced measures designed to

promote the digital information society, featuring DTTV transmission in the
second half of 1998. Several different sites have been proposed (Brittany, for
instance). A regulatory framework is being prepared to handle the new service
once implemented in the real world. Some studies on frequency planning and the
requirements of future digital TV sets have been carried out to provide technical
data for the service implementation.

3.1.2 The Netherlands

The Ministry of Transport is developing a plan for the introduction of DVB-T to

be finalized within 1998. The DTTV service could start with a pilot project in the
area Hilversum/Utrecht in 1999 followed by an operational service in the
Randstad area in year 2000.

8
3.1.3 United Kingdom

Plans are already advanced for the launch of DTTV later in 1998. A target date of
November 1st is the current deadline. The multiplexes have been already assigned
to several UK TV operators (BBC, for instance). The plans of DTTV in UK have
been designed on the basis of interleaved coverage of six multiplexes.
Transmission will be operated with the 2K option of the DVB-T standard,
featuring an overall payload of approx. 24 Mbit/s.

3.1.4 Sweden

The Swedish government announced licenses in late 1997 for two multiplexes
with 4 TV channels each (to be awarded around mid 1998). Transmission will
begin in five areas of Sweden (50% coverage of the population). The launch is
expected at the beginning of 1999, being confident to have DTTV receiver in the
market at the end of 1998. More than 50 companies have applied for license to
transmit either regionally or nationally. Two more multiplexes are under
considerations.

3.1.5 Finland

YLE Television (Finnish Broadcasting Company) started DVB-T test transmission

in October 1997 in Helsinki in 8K mode. Such test bed will be used to assess
coverage, performances and quality of signal. The Finnish government has started
the discussion concerning DTTV. Some problems of frequency planning and
negotiation with neighboring countries (Russia, Estonia and Sweden) are still to be
solved.

3.1.6 Spain

Spanish government has prepared the “Digital TV National Technical Plan” for
DTTV. The policy is to subordinate the renewal of the license of the private TV
networks to digital system use, fixing a period for the transition from analog to
digital (simulcasting).

3.1.7 Italy

RAI has defined a DTTV experimentation project that will operate in two phases:
firstly a number of towns (Rom, Turin, Pisa, Livorno, Palermo, Aosta) will be
served with a DVB-T signal to assess coverage studies and performance
evaluation. This phase is supposed to be concluded by the end of 1999. A second
phase will achieve a wider coverage starting from the wider metropolitan areas.

9
3.1.8 Portugal

A DTTV demonstration will be arranged for the World EXPO’98. After that, an
experimental digital network is planned in the Lisbon area based in 8K mode and
transmission should be accommodated in channel 61.

3.1.9 Germany

Representatives of the public and private broadcasters are actually discussing the
scenario for the start up of DTTV in Germany. Regulatory aspects are also under
consideration. Such group of representatives (coming out from the so-called
TV2000 Forum) is responsible to prepare a detailed proposal. The forecasted
starting point for the launch of DTTV is at the beginning of year 2000 with a
simulcasting period of about 10 years (to be approved by the government). Four
field trial sites have been defined to carry out experimentation: Berlin, North
Germany, Nordrhein-Westfalen and Munich. The first one is already operating on
the air, while the other three are planned. A proposal is supposed to be issued mid
of 1998. Germany is also advanced in studying the roboustness of the DVB-T
standard in the mobile environment; field trials have been carried out in the Berlin
area.

3.2 DTTV outside Europe

3.2.1 Australia

Australia is on the leading edge of DTTV experimentation. Extensive field trials

of both the European DVB-T system and the US ATSC system have been carried
out in 1997 and early 1998 to gather experimental data on coverage, quality, etc.
of both proposed system. After a long decision process and several discussions,
the Federation of Australian Commercial TV stations (FACTS) has recommended
the Federal Australian Government to adopt DVB-T for DTTV service in
Australia (see Annex 1). This recommendation has been issued end of June, after a
demonstration of COFDM HDTV performed with the chip set designed within the
DVBird project (COFDM part) and with commercial silicon products for the
MPEG2 demux/decoding functions. Such demonstration has been held in June 10th
in Sydney and in June 12th in Canberra. The plan for the introduction of the DTTV
service in Australia envisages to commence DTTV (now DVB-T!) service in
metropolitan areas by the end of year 2000 and in regional areas before the end of
year 2003. The duration of the simulcasting period has still to be defined,
according to the future market of digital set top boxes. The target quality for the
program material has been required to be HDTV, while in Europe SDTV has been
proposed. 7 MHz channel spacing has been also envisaged, while in Europe 8
MHz is the rule.

10
3.2.2 China

The Ministry of Radio Films and Television in China is considering DTTV as a

high priority item and it is expected that China Central TV (CCTV) will evaluate
both DVB-T and ATSC systems before making a choice.

3.2.3 Japan

Japan is developing its own system for DTTV, that is COFDM based but not fully
compliant with the DVB-T European standard (ISDB-T or BST-OFDM). The
target date to launch the service should be year 2000, but with some questions still
pending. Extensive field trials in Japan are expected in fall 1998 to further
investigate the current version of the system specifications. The final draft
standard is to be submitted for approval at the Ministry of Post and
Telecommunications in spring 1999.

3.2.4 New Zeland

A strong preference has been indicated in favor of DVB-T system. Now that
Australia is going towards DVB-T, the choice seems to be clear.

3.2.5 Singapore

The Singapore Broadcasting Authority has granted a license to an independent

company (Advent Television) to set up a digital terrestrial trial service, based on
DVB-T specification. However, the final choice on the system is still not made; a
Digital TV Technical Committee has been established to make a recommendation.

3.3 The role of the silicon technology

The DVBird project was meant to “break the wall” of the DVB-T receiver,
demonstrating the feasibility of the implementation of the DVB-T receiver at a
reasonable cost.

In early 1996, several doubts were on the table, concerning the complexity of
a DVB-T receiver, particularly the 8K option of the COFDM technique; the need of
a parallel real-time FFT processor was seen as a problem for the silicon
implementation of the DVB-T standard. However, the DVBird partners have
demonstrated that the silicon technology for the year 1998 is already mature to carry
such system and to allow the manufacturing of the receiver for the volume
production.

11
 More in general, when developing a new system, like Digital Terrestrial TV,
the first step is to investigate the system requirements and to develop a set of
algorithms that meet the target performances needed for the expected service quality.
After that, the focus has to be placed on the implementation of such system in the
real world, taking into account that the cost of the new service for the target user is
one key point to achieve a successful implementation.

In consumer electronics silicon technology is a powerful method to cut down

the cost of a terminal, thanks to the integration capabilities, now really impressive
and not far from the physical limit. At the present time it is often used the concept of
“system on silicon”. It means that a single chip is now able to carry not only a very
complex hardware structure, like a demodulator, a microprocessor or a powerful
digital signal processing function (FFT), but also a combination of those functions.

These results in the integration on a chip allows the system designer to

develop algorithms with a very high computational requirements, while keeping low
the cost of the final components. Therefore, the key point for market penetration is
not only to optimize the algorithms and the architecture, but also to use a powerful
silicon technology to diffuse the system.

A good example of the integration potentiality, that is going to be possible by

the new silicon technology, is Digital TV. When DVBird started (early 1996),
Digital TV was studied heavily and detailed specifications were available for the
three different transmission chains, i.e. satellite, cable and terrestrial (UHF/VHF
band) in a quite independent manner. No doubt that this was the right approach to
allow an early introduction of a Digital TV service in Europe in the three different
media, since the technical problems to be solved were quite different, especially
for the terrestrial chain with respect to the other two.

However, the future of Digital TV in the medium and long term is based on
the possibility for the industrial and consumer companies to provide the market with
low-cost solutions with more and more advanced features and services, taking
advantage of the integration capabilities of the new silicon technology.

At the present time, the concept of a "common" or “universal” receiver, able

to deal with the three different transmission chains, is no more a pure dream. The
envisaged scenario for the end of the century will be the co-existence of the three
transmission chains. It will require the capability to efficiently and rapidly convert
each service from one source to the others (interoperability) and, therefore, the
availability of an efficient implementation on silicon of this “common” receiver. This
concept is now going to be feasible thanks to the latest silicon technologies.

12
4 Project Achievements

In the following chapters the main technical achievements of the DVBird

project are described. Special focus is placed on the features of the DVBird VLSI
chip set that is the first one in the world compliant to the full DVB-T standard.

4.1 Technical achievements

According to the original plan, the work in the first year has been
concentrated in Workpackage 1 (system specs, receiver architecture, and models
validation) with the aim of assessing the receiver specification (according to the
DVB-T standard) and the hardware architecture (including chip partitioning of the
receiver). On the other hand, the work of the second year has been specifically
carried out in Workpackage 2 (IC design and manufacturing) and 3 (demonstrator
design and manufacturing), while Workpackage 1 was in charge of a crucial task,
mainly concentrated in the cross-validation of the models of the different chips.

The first main achievement of the DVBird project is the prototyping of the
chip set to implement the digital terrestrial TV receiver, according to the European
DVB-T standard. This chip set comprises four chips to implement the full
functionality of the DVB-T receiver. The functional block diagram of the DVBird
receiver, with the partitioning into chips is shown below [5], [6].
CHANNEL
DECODING

chip 1 chip 2 MAPPING

I,Q COFDM
ANALOG I&Q
FRONT A/D
GEN.
DEMODUL. channel chip 3
END (2K/8KFFT) correction
FREQUENCY
Fs DEINTERLEAVING
AGC REFERENCE
FFT window SYMBOLS
amplitude EXTRACTION VITERBI
DECODER
frequency
FRAME & TIME
correction CHANNEL BYTE
SYNCHRONISATION
ESTIMATION DEINTERLEAVING
FREQUENCY
SYNCHRONISATION REED-SOLOMON
DECODER
video chip 4 SERIAL BUS
MPEG2 VIDEO
audio TRANSPORT
DECODER MPEG2 AUDIO max Bit Rate
DEMUX (MPEG2)
DECODER
~30 MBit/s

General block diagram of the DVBird receiver

13
Starting from the antenna, the RF signal is passed into the Analog Front End
module, where it is first down-converted to and intermediate frequency IF1, then
to e second intermediate frequency IF2 and finally to baseband. The analog signal
is then passed through an ADC (Analog to Digital Converter) to obtain a dataflow
of 18 Msamples/s. The data stream is made of modulation components I and Q
multiplexed, thus supporting a rate of modulation points (I+Q) of approx. 9 MHz.

The 18 MHz digital sample rate is then passed into the first chip (IC1) [7]
that performs the filtering to separate the I and Q components and to perform the
OFDM demodulation. This last function is achieved through a FFT on a window
that can be either 2048 samples or 8192 samples (2K and 8K mode respectively).
Both modes are part of the DVB-T standard. The real-time FFT is performed
through a hardware parallel processor, in order to achieve the needed processing
speed.

The data stream after FFT is then passed to the second chip (IC2) [8] to
estimate the distortion in amplitude and phase of the constellation points. Such
distortion is generated by the terrestrial channel, due to its characteristics, such as
multipath propagation, frequency selective fading, etc. The estimation of the
distortion is measured on a set of pilot carriers, that are inserted in the OFDM
frame. Such reference symbols are used to compute the correction factor for a
given information sample, through the use of combined frequency and time
interpolation. Once the correction factors are computed, the given sample is
corrected and the output data stream is passed to the following stage (IC3).

In parallel to the main processing path, the fourth chip of the set (IC4) [9] is
in charge of all the synchronisation tasks that are needed to recover the start of the
current frame and of the current OFDM symbol (2048 or 8192 samples
respectively). Typical tasks are frequency synchronisation, time synchronisation,
sampling clock recovery, FFT window adjusting. In addition, IC4 acts as master of
the full chip set, since it is able to extract form the data stream the TPS parameters
(Transmission Parameter Signalling), that carry the control information and the
parameters of the chosen transmission mode, according to the options of the DVB-
T standard:
1. Inner code rate: (1/2, 2/3, ¾, 5/6, 7/8)
2. Guard interval duration: (1/4, 1/8, 1/16, 1/32 of the active period of the OFDM symbol)
3. Modulation type: (QPSK, 16QAM, 64QAM)
4. FFT size: (2K, 8K)

14
 Such parameters are decoded within IC4 and then passed to the other three
chips through a dedicated serial bus interface. Each chip has a set of state registers,
where this information is stored for the current OFDM frame. The processing of
each of the other three chips is driven by the value of these parameters. For this
reason, IC4 is the master of the whole set.

IC3 [10] is the final component of the main processing chain

(IC1+IC2+IC3). The I and Q samples, once corrected in IC2, are then delivered to
a first block of deinterleaving (Symbol Deinterleaving) to restore the original
order of the modulation samples, that were interleaved in the transmission part to
enhance the performances of the error correction algorithms. The samples are then
combined (I+Q) to retrieve the constellation point and to obtain the associated bit
word (2, 4 or 6 bits depending on the type of constellation). The bit stream
generated by this process (Demapping) is then again deinterleaved (Bit
Deinterleaver) and sent to the FEC stage (Forward Error Correction) for channel
decoding. The adopted coding schema (according to DVB-T standard) is a
concatenation of a punctured convolutional code (Inner Code) and a Reed-
Solomon block code (Outer Code) separated by another interleving stage.
Therefore, on the receiver side a Viterbi Decoder, a Byte Deinterleaver and a
Reed-Solomon Decoder are used to correct the transmission errors and to achieve
the QEF condition (Quasi Error Free) at the output of the receiver.

The output interface is a standard MPEG2 Transport Stream interface. A

smoothing buffer is placed on the output interface to allow complying with any
type of source demux and decoder chips, according to the MPEG standard,
without any special buffering requirements.

After the first engineering samples, some bugs have been found that
required additional work to achieve full functional samples and in some cases a
new silicon was necessary, as in the usual manufacturing procedure.

A considerable delay to perform the diffusion on silicon of the chip set has
been necessary, comparing to the original DVBird plan; it can be justified looking
at the block diagram of the receiver. IC1, IC2 and IC3 are part of a unique
processing chain and the final testing of IC3, for instance, (on the test patterns
generated at the output of IC2) can be performed only when the previous chips are
fully operational. In addition, the DVBird designers have spent a lot of effort in
the cross-validation of the different chips, because each chip was designed and
manufactured by a different partner, with several constraints on the exchange of
information, due to confidentiality reasons.

15
 The second achievement of the DVBird project is the specification, design
and manufacturing of the Digital Board [11], that is devoted to carry the ADC and
the four chips (IC1, IC2, IC3, IC4), that will implement the Digital Part of the
receiver. The receiver demonstrator is completed by the Analog Front End module
[12] that perform the down conversion from the RF to the baseband, through the
IF, as well as the tuning to the selected UHF channel.

The Digital Board is the core of the DVBird receiver demonstrator, where
the main processing is performed and where the most of the design effort of the
project partners has been placed, to achieve a highly integrated chip set. The
schematic of the board mostly reflects the block diagram of the DVBird receiver,
with the four chips. In addition some standard market components have been used
to complete the receiver board, as following:

♦ The commercial ADC (Analog to Digital Converter) Harris HI5703 has been
selected to support the requirements of data rate and conversion precision.

♦ A standard EEPROM has been used to contain the software to be loaded into
IC4 at the boot of the system

♦ A 36 MHz VCXO has been used to generate the master clock for the four chips

Once the Digital Board has been manufactured and a first assembly and
testing of the four chips on the board has been performed, the lab tests helped to
detect some bugs in the four chips during the assembly and integration of the
whole demonstrator. This last task has been completed in June 1998.

The third achievement within Workpackage 3 was the definition of the so-
called Man-Machine Interface (MMI) or Graphical User Interface (GUI) [13].
This software program has been written for the Windows operating system to run
on a usual PC and to allow the user to operate with the DVBird demonstrator. A
graphical interface allows the operator to communicate with the digital board
(through the I2C interface of IC4) and to perform the following functionality:

♦ To select the frequency channel in the tuner

♦ To monitor the transmission parameters (TPS)

♦ To load a specific transmission mode into the hardware (set of TPS value)

♦ To monitor the content of the state registers of the different chips

♦ To monitor the BER value (for measurement purpose)

16
4.2 DVBird Chip Set features

4.2.1 IC1: I/Q Generation and OFDM Demodulation

♦ Compliant to DVB-T Standard. All Modes supported

♦ 2K and 8K options
♦ Variable Guard Interval (1/4, 1/8, 1/16, 1/32 of Useful Symbol Duration)
♦ Digital Generation of I (In phase) & Q (Quadrature) components
♦ Digital Frequency Correction of Local Oscillator’s drift (in the range -/+ 70
kHz)
♦ Direct FFT Computation (2K & 8K)
♦ Digital Time Shift
♦ Digital Automatic Gain Control (AGC) with Delta-Sigma Output
♦ Coarse Time Synchronisation through correlation on Guard Interval
♦ Digital Input/Output Data in Multiplexed Way. Outputs in Bit-Reversed
Order
♦ External control through dedicated serial bus
♦ Packaging : PGA120 / PQFP 128
♦ Power : 3.3 Volt

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General block diagram of DVBird IC1

17
4.2.2 IC2: Channel Estimation and Correction

♦ Complete channel estimation through time and frequency interpolation

♦ Common phase error correction
♦ Fine frequency errors estimation on scattered pilots
♦ Partial channel estimation
♦ Confidence calculation
♦ Data correction (division by channel response)
♦ TPS differencial demodulation
♦ 2K and 8K options
♦ Bit reverse re-ordering
♦ 3-symbols built-in delay line
♦ External control through dedicated serial bus
♦ Packaging : PGA120 / PQFP 128
♦ Power : 3.3 Volt

C 2_BIT_TPS

C 1_DA TA_STAR T bit 2 symbols delay-line 1 symbol demod C 2_TPS _V AL

reverse delay-line TPS C 2_FSTAR T

C 1_D ATA C 2_DATA_S TA RT

C 2_RS_STAR T
C 4_C LK18

partial Time Channel

R ESETB C 2_DATA
channel interpolation FIR correction
CPE
estimation C 2_D_V AL

C4_FSD A
C 2_CNF D
Serial interface Confidence calculation
C 4_S EN

General block diagram of DVBird IC2

18
4.2.3 IC3: Channel Decoding

♦ Digital multiplexed IQ inputs

♦ Digital confidence input
♦ Digital MPEG2 transport stream output (8-bits) parallel and serial
♦ 2K and 8K options
♦ Variable guard interval (GI: 1/4, 1/8, 1/32 of useful period)
♦ Hierarchical and not hierarchical modes supported
♦ QPSK, 16QAM, 64QAM (WITH alfa=1,2,4) demodulation options
♦ Inner symbol deinterleaving, inner bit deinterleaving
♦ Soft Viterbi decoding of inner convolutional code
♦ Depuncturing for different code rates (R=1/2, 2/3, 3/4, 5/6, 7/8)
♦ Outer deinterleaving (I=12)
♦ Decoding of outer RS(204,188) Reed-Solomon code
♦ External control through dedicated serial bus
♦ Compliant to DVB-T standard (all modes supported)

c2_data(7:0)

c2_cnfd SYMBOL DEINTERL.

(3:0)
resetb INNER DECODER
DEMAPPER
c2_data _start

OUTER DEINTERL.
c4_clk18 BIT DEINTERL.

c4_clk36 OUTER DECODER

DEPUNCTURER
c2_d_val
alfa(2:0) EN. DISP. REMOVAL
ofdmode constype(1:0)
c2_fstart
dep_rate(2:0)
c4_fsda priority
SERIAL BUS MPEG2 INTERFACE
c4_sen INTERFACE

c3_d_val c3_byte_clk c3_rs_fail c3_pack_clk c3_data(7:0)

General block diagram of DVBird IC3

19
4.2.4 IC4: Synchronisation and Control

♦ Internal fast I2C bus mastering

♦ Clocks and reset signal for the chipset
♦ Frequency error estimation
♦ Time error estimation
♦ Sampling frequency error estimation
♦ Transmission Parameter Signalling recovery and decoding
♦ 2K and 8K options
♦ External control and interface through standard I2C bus
♦ Packaging : CQFP 64
♦ Power : 3.3 Volt

CHIP4
DSP - Philips Epics11
Debug
Controller
YMEM DCB
1K*16 bits RAM
12
4K*4 ROM EPICS 11
C1_DATA
Input 1K*12 ROM DSP core
C1_DATA_START
Carrier (16*16)35bit ALU
Computation SR-AXU ZMEM
XMEM
EMPI 2K*32 RAM
5k256*14RAM 32*32 ROM

dwn_scl DIO space

dwn_sda Master 18 registers
C4_scl IIC
C4_sda 18.28 MHz

CLK36 Clock Fast Serial Time Synchro Sampling Frequency

C4_CLK18_IN divider Bus Flag Handler delta-sigma Modulator

resetb 2

C4_CLK18 FIN C4_FSDA C4_SEN

C1_SYMB_DET C4_FFT_WIN C4_FSAMP

General block diagram of DVBird IC4

20
4.3 Hardware Demonstrator and practical experimentation

The original plan of the DVBird project did not comprise any field trials.
The reason for this is that another ACTS project (VALIDATE) was started in the
same time frame to deal with field trials and frequency planning for the DVB-T
standard. DVBird and VALIDATE agreed to cooperate and to avoid duplication of
work. Some preliminary information have been published by VALIDATE partners
including coverage studies and implementation margin. Such information has been
obtained from lab test and field trials based on prototype discrete hardware
receivers, like the second dTTb demonstrator. However, the final step was to
establish practical experiments by operating an integrated receiver, like the one
scheduled within DVBird. The connection with VALIDATE project, therefore,
was of primary importance to finalize the design of the chip set and to have a
feedback from lab test and field trials on the DVB-T standard.

Unfortunately, due to the delay in the prototyping of the DVBird chip set,
no real joint activity has been carried out during the project duration, except the
testing of the Analog Front End module by VALIDATE partners and the exchange
of general information material (deliverables).

The short time available for the finalization of the DVBird demonstrator
before the end the project (May 1998) allowed, until now, only internal lab tests
on the DVBird chip set performed by the DVBird partners involved in the
demonstrator manufacturing (SGS-THOMSON and Philips). The target of this lab
test was to finalize the demonstrator to set up a show of the complete
demonstration chain, based on the DVBird technology, in front of the
representatives of the Federation of the Australian Commercial TV Stations
(FACTS) in mid June 1998. Such demonstration has been performed successfully.

21
5 DVBird Success Story
The story of the DVBird project started in January 1996 and lasted two years
and a half; each year can be identified with a different main task and achievement,
according to the development process of the DVBird chip set. The first year has
been devoted to the assessment of the specification of the DVB-T receiver and the
partitioning of the overall architecture into four chips. The second year has been
used to design the chip set and to start the manufacturing of the demonstrator
boards, while the rest of the project period has been devoted to finalize the
demonstrator software and hardware and to fix some bugs in the chip set. The
closing event is the final demonstration in Australia in June this year.

5.1 1996: The first effort

At the beginning of the project in January 1996 the DVB-T specification
were not yet frozen. In December 1995 heavy changes were agreed in the
framework of DVB; in particular the deletion of the NULL symbol and the
CAZAC sequences obliged the DVBird partners to an additional work to track the
final version of the specification, comparing to the investigations performed
within the previous dTTb project. The DVB-T specs have been finalized only in
spring 1996, with delay, with respect to the original work plan of DVBird.
However, the first project year has been successfully spent on the definition of the
specs of the DVBird receiver on the basis of the DVB-T standard. The result is
described in the deliverable D06 [5].

In parallel, a suitable chip partitioning has been agreed, with four chips
implementing the full receiver form the output of the ADC up to the MPEG2
Transport Stream interface. Such specification was adopted as the basis for the
design of the chip set [6].

The modeling of the chips was started using VHDL language and a high
level model of the complete transmitter/receiver chain was developed to provide a
reference for the validation of the VHDL models and the generation of suitable
test patterns in different parts of the receiver [14].

The promotional activity of the project was concentrated on articles on

magazines and two papers written for ECMAST96 [15] and the HDTV Workshop
in Los Angeles [16]. Particularly the Los Angeles presentation of the project
generated a lot of discussion in the US, where COFDM was not yet fully exploited
for DTTV applications.

5.2 1997: The DVB-T chip set is here!

The second project year was the most critical one, because a very huge effort
have been placed on the design activity of the four chips. The different chips have

22
been finalized and diffused on silicon at different dates, because three chips are
conceptually organized in a chain in the receiver block diagram (IC1, IC2, IC3).
The testing of the last chip could be finished only after the testing of the previous
two and so on. This situation added a lot of delay in the freezing of the designs for
the diffusion on silicon.

In addition, the confidentiality constraints among the partners required a lot

of effort for cross-validation of the whole chip set. Such activity has been
performed by suitable test files generated with the reference chain and, at the end,
by exchanging the real output files obtained by direct simulation of the VHDL
models. All this work has been made for all the possible operating modes and
configurations of the receiver.

At the end of the year engineering samples of the four chips were available
and a testing on the boards could be started to evaluate the design in the real
environment. The first DVB-T chip set (fully 8K/2K compatible) was born [7],
[8], [9], [10].

The promotion of the project continued with two more papers for
Montreaux Symposium [17] in June 1997 and for IBC in September 1997 [18].
The DVBird project was assigned a stand in the Technology Campus of IBC98,
where a lot of visitors get in touch with the consortium. A poster of the project
was also displayed in the TEKO stand at IFA98 in Berlin.

During this year the first contacts with representatives of the Australian
broadcasting community has been started, in order to support the process of choice
of the DTTV standard in that country. A delegation of DVBird project, with the
aim of promoting the DVBird chip set, attended a DVB demonstration in Sydney
in December 1997 [19]. During this demo the DVB-T system have been
demonstrated with HDTV quality by using professional equipment and a over-the-
air transmission of COFDM signal through a local broadcaster.

5.3 1998: DVBird is touching the southern hemisphere

The participation to the DVB demonstration in Sydney has increased the
connection between the DVBird consortium and the Australians. Further
discussion and information exchanges have been carried out weekly during the
first 6 months of 1998. The target was to arrive at a demonstration of the DVB-T
system by using the DVBird technology (chip set) as a real example of an
integrated receiver before the final decision was taken (June 1998).

During those 6 months all bugs in the engineering samples of the DVBird chip
set have been cleared and the digital board finalized.

23
 Due to the high pressure from the market of DTTV receivers, some partners of
the project started in parallel commercial developments based on the DVBird
technology. Below are some examples of market exploitations of the DVBird
results:

♦ STMicroelectronics and Philips signed in September 1997 a commercial

agreement to manufacture and sell jointly the DVBird chip set.
♦ CCETT started in early 1998 to develop an integrated receiver for
professional use, based on the DVBird technology [20].
♦ Comatlas is going to finalize a second source of the DVBird chip set with
some new features.

STMicroelctronics and Philips also continued to improve the digital board, in

order to arrive to a realistic design to be used for demonstrations and lab tests.
This work has been finalized in early June 1998, when the demonstration in
Australia was planned.

Such demonstration (held in Sydney and Canberra on June 10th and 12th in
front of all the key players of the Australian DTTV scenario) featured the
transmission of 1250/50 Hz interlaced HDTV DVB-T signal in 8K mode with a
channel spacing of 7 MHz. The modulation chain was built around professional
equipment available on the market, while the Digital Board from
STMicroelectronics and the DVBird chip set constituted the receiver chain.

The message behind that demonstration was that the DVB-T standard is
actually supported by a VLSI solution suitable for the production of DVB-T set-
top boxes and Digital TV sets for the consumer market.

As a result of this demonstration, a few days after that event, a meeting has
been held at the Federation of Australian Commercial TV Stations (FACTS).
FACTS was in charge to make a recommendation to the Australian Federal
Government concerning which system to choose for DTTV, either the DVB-T
from Europe or the ATSC from US. After that meeting, FACTS finally
recommended adopting the DVB-T standard as the future DTTV system in
Australia (see annex 1).

In parallel, some DVBird partners continued the algorithmic investigations to

improve the receiver performances. A paper has been recently presented at ICC98
in Chicago [21].

24
6 Conclusions

The advent of Digital Terrestrial TV is no more far in the future. UK and

Sweden are going to set up a real service over the air around the end of this
year and most of the other European countries are trying to fill the gap with
aggressive plans for a DTTV service. Digital Terrestrial TV is now a
European hot topic.

A similar process has been started all over the world and two main
proposals have been presented; the DVB-T standard from Europe and the
ATSC standard, promoted by US and based on single carrier 8-VSB
modulation technique. All major countries in the world, with Australia in pole
position, have taken part of this big discussion on the choice of the DTTV
system between the European system (COFDM) and the US system (8-VSB).

The role of DVBird project in this long process has been highly strategic
for the DVB-T standard, with the aim of “breaking the wall” of the complexity
of DVB-T receivers. In fact, after the DVB-T standardization (two years ago)
it was necessary to go from the system simulation and the first dTTb hardware
demonstrator (big racks and a lot of boards) to the real world of the consumer
product, by proposing a cost effective VLSI solution.

The prototyping of the DVB-T COFDM chip set has clearly demonstrated
the feasibility of the DVB-T standard, beyond its outstanding technical
performances in the terrestrial environment.

Furthermore, the first hardware demonstrator of a DVB-T receiver had

made possible to have a first reference design for the development of
consumer DVB-T receivers and to convince the key players in the DTTV field
to consider the DVB-T standard for their new digital service.

Australia has very recently chosen DVB-T and is only the first step of this
story outside Europe.

Also to be mentioned several papers published by the project partners in

well-known international conference (IBC, Montreax, HDTV Workshop, etc.)
during the project duration and a huge amount of articles in technical
magazines, press releases and brochures published and distributed in the last
two years in Europe and worldwide.

25
7 References

[1] B.Marti, D.Nasse, P.Bernard, B. Le Floch

“Problems and Perspectives of Digital Terrestrial television in Europe”
SMPTE Journal, August 1993

[2] dTTb project, Module 6 partners

“Hardware Specification of the second dTTb demonstrator”
dTTb deliverable H117 vs.3, February 1996

[3] prETS 300 744

“Digital Video Broadcasting (DVB); Framing Structure, channel coding and
modulation for digital terrestrial television (DVB-T)”
ETSI standard – Final Draft, November 1996

[4] European Broadcasting Union – DVB technical Assembly

“Digital TV in their countries: reports from the Members about developments”
DVB document TA064, April 1998

[5] DVBird partners

“Specification of the first generation receiver”
DVBird deliverable D07, July 1996

[6] DVBird partners

“Receiver architecture and ICs specification”
DVBird deliverable D01, July 1996

[7] C.del Toso

“IC samples and datasheet for Digital Front-end for DEM1”
DVBird deliverable D14, July 1997

[8] P.Penard
“IC samples and datasheet for Channel Estimation for DEM1”
DVBird deliverable D10.2, July 1997

[9] L.Soyer, L.Lauer

“IC samples and datasheet for Synchronization for DEM1”
DVBird deliverable D10.1, July 1997

[10] F.Scalise, J.Galbrun

“IC samples and datasheet for Channel Decoding for DEM1”
DVBird deliverable D11, December 1997

26
[11] V.Chowdhury
“Demonstrator DEM1 Specification and Architecture”
DVBird deliverable D09, July 1997

[12] A.Dener
“Receiver Front-end for demonstrator DEM1”
DVBird deliverable D12, March 1997

[13] F.Scalise, J.H.Waterman, J.E.Hutchinson

“MMI and Packaging”
DVBird deliverable D17, May 1998

[14] J.J.Ma
“Reference Chain for Global Validation of VHDL Models:
Dvbird deliverable D26, March 1997

[15] M.Balanza, N.Chauve, P.Combelles, C.Del Toso, D.Hepper, G.Masera,

J.M.Marczak, F.Nicolas, P.Pirat, P.Robertson, F.Scalise
“Prototyping an efficient silicon to promote the DVB-T standard”
Proc. of ECMAST96, ACTS Workshop, Louvain-La-Neuve, May 1996

[16] F.Scalise, M.Balanza, N.Chauve, P.Combelles, P.Penard, C.Del Toso,

D.Hepper, G.Masera, C.Hernandez, F.Nicolas, D.Le Goff, P.Robertson
“A Prototype VLSI Solution for Digital Terrestrial TV Receivers conforming to
the DVB-T Standard”
Proc. Of HDTV Workshop, Los Angeles CA, November 1996

[17] P.Combelles, F.Scalise, D.Hepper, L.Soyer, F.Nicolas

“Results from the DVBird project: a chip-set implementing the full DVB-T
specification”
Proc. of Montreaux Symposium, Montreaux, June 1997

[18] M.Tognin, L.Soyer, P.Combelles, C.Del Toso, D.Hepper, G.Piccinini, J.J.Ma,

F.Nicolas, P.Robertson, F.Scalise, A.Dener
“A VLSI solution for a digital terrestrial TV (DVB-T) receiver”
Proc. Of IBC97, Amsterdam, September 1997

[19] DVB Project Office

“DVB shows Australia off-the-shelf HDTV”
DVB press release, December 1997

[20] CCETT
“IRD-PRO. A full DVB-T Integrated Receiver Decoder for professional use and
early digital TV experimentations” – Preliminary Information
CCETT marketing brochure, January 1998

27
 [21] P.Combelles, C.Del Toso, D.Hepper, D.Le Goff, J.J.Ma,
P.Robertson, F.Scalise, L.Soyer, M.Zamboni
“A Receiver Architecture Conforming to the OFDM Based Digital Video
Broadcasting Standard for Terrestrial Transmission (DVB-T)”
Proc. Of ICC98, Chicago, June 1998

28
8 Annex 1

Press release from Australia about the DTTV standard

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