Professional Documents
Culture Documents
Pin Diagrams
PIC16F83
PIC16F84
PIC16CR83
PIC16CR84
Extended voltage range devices available
(PIC16LF8X, PIC16LCR8X)
PDIP, SOIC
Program
Memory
(words)
Data
Data
RAM
EEPROM
(bytes) (bytes)
Max.
Freq
(MHz)
PIC16F83
512 Flash
36
64
PIC16F84
1 K Flash
68
64
10
36
64
10
PIC16CR84 1 K ROM
68
64
10
10
Peripheral Features:
RA2
18
RA1
RA3
17
RA0
RA4/T0CKI
16
OSC1/CLKIN
MCLR
15
OSC2/CLKOUT
VSS
14
VDD
RB0/INT
13
RB7
RB1
12
RB6
RB2
11
RB5
RB3
10
RB4
PIC16F8X
PIC16CR8X
DS30430C-page 1
PIC16F8X
Table of Contents
1.0 General Description ...................................................................................................................................................................... 3
2.0 PIC16F8X Device Varieties .......................................................................................................................................................... 5
3.0 Architectural Overview.................................................................................................................................................................. 7
4.0 Memory Organization ................................................................................................................................................................. 11
5.0 I/O Ports...................................................................................................................................................................................... 21
6.0 Timer0 Module and TMR0 Register............................................................................................................................................ 27
7.0 Data EEPROM Memory.............................................................................................................................................................. 33
8.0 Special Features of the CPU ...................................................................................................................................................... 37
9.0 Instruction Set Summary ............................................................................................................................................................ 53
10.0 Development Support ................................................................................................................................................................. 69
11.0 Electrical Characteristics for PIC16F83 and PIC16F84.............................................................................................................. 73
12.0 Electrical Characteristics for PIC16CR83 and PIC16CR84........................................................................................................ 85
13.0 DC & AC Characteristics Graphs/Tables.................................................................................................................................... 97
14.0 Packaging Information .............................................................................................................................................................. 109
Appendix A: Feature Improvements - From PIC16C5X To PIC16F8X .......................................................................................... 113
Appendix B: Code Compatibility - from PIC16C5X to PIC16F8X.................................................................................................. 113
Appendix C: Whats New In This Data Sheet ................................................................................................................................. 114
Appendix D: Whats Changed In This Data Sheet ......................................................................................................................... 114
Appendix E: Conversion Considerations - PIC16C84 to PIC16F83/F84 And PIC16CR83/CR84.................................................. 115
Index ................................................................................................................................................................................................. 117
On-Line Support................................................................................................................................................................................. 119
Reader Response .............................................................................................................................................................................. 120
PIC16F8X Product Identification System ........................................................................................................................................... 121
Sales and Support.............................................................................................................................................................................. 121
DS30430C-page 2
PIC16F8X
1.0
GENERAL DESCRIPTION
PIC16F83
PIC16F84
PIC16CR83
PIC16CR84
Table 1-1 lists the features of the PIC16F8X. A simplified block diagram of the PIC16F8X is shown in
Figure 3-1.
The PIC16F8X fits perfectly in applications ranging
from high speed automotive and appliance motor
control to low-power remote sensors, electronic locks,
security devices and smart cards. The Flash/EEPROM
technology makes customization of application
programs (transmitter codes, motor speeds, receiver
frequencies, security codes, etc.) extremely fast and
convenient. The small footprint packages make this
microcontroller series perfect for all applications with
space limitations. Low-cost, low-power, high
performance, ease-of-use and I/O flexibility make the
PIC16F8X very versatile even in areas where no
microcontroller use has been considered before
(e.g., timer functions; serial communication; capture,
compare and PWM functions; and co-processor
applications).
The serial in-system programming feature (via two
pins) offers flexibility of customizing the product after
complete assembly and testing. This feature can be
used to serialize a product, store calibration data, or
program the device with the current firmware before
shipping.
1.1
1.2
Development Support
DS30430C-page 3
PIC16F8X
TABLE 1-1
Clock
Memory
Maximum Frequency
of Operation (MHz)
PIC16CR83
10
PIC16F84
10
PIC16CR84
10
512
1K
512
1K
36
36
68
68
64
64
64
64
TMR0
TMR0
TMR0
TMR0
Interrupt Sources
I/O Pins
13
13
13
13
2.0-6.0
2.0-6.0
2.0-6.0
2.0-6.0
Packages
18-pin DIP,
SOIC
18-pin DIP,
SOIC
18-pin DIP,
SOIC
18-pin DIP,
SOIC
Features
10
All PICmicro Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16F8X Family devices use serial programming with clock pin RB6 and data pin RB7.
DS30430C-page 4
PIC16F8X
2.0
2.
3.
4.
2.1
2.3
2.4
ROM Devices
Flash Devices
2.2
Quick-Turnaround-Production (QTP)
Devices
DS30430C-page 5
PIC16F8X
NOTES:
DS30430C-page 6
PIC16F8X
3.0
ARCHITECTURAL OVERVIEW
DS30430C-page 7
PIC16F8X
PIC16CXX devices contain an 8-bit ALU and working
register. The ALU is a general purpose arithmetic unit.
It performs arithmetic and Boolean functions between
data in the working register and any register file.
FIGURE 3-1:
13
Program Counter
Flash/ROM
Program
Memory
PIC16F83/CR83
512 x 14
PIC16F84/CR84
1K x 14
Program
Bus
8 Level Stack
(13-bit)
14
EEDATA
RAM Addr
EEPROM
Data Memory
64 x 8
EEADR
Addr Mux
Instruction reg
Direct Addr
TMR0
Indirect
Addr
FSR reg
RA4/T0CKI
STATUS reg
8
MUX
Power-up
Timer
Instruction
Decode &
Control
Timing
Generation
Oscillator
Start-up Timer
8
ALU
Power-on
Reset
Watchdog
Timer
I/O Ports
RA3:RA0
W reg
RB7:RB1
RB0/INT
OSC2/CLKOUT
OSC1/CLKIN
DS30430C-page 8
MCLR
VDD, VSS
PIC16F8X
TABLE 3-1
SOIC
No.
I/O/P
Type
OSC1/CLKIN
16
16
OSC2/CLKOUT
15
15
MCLR
I/P
ST
Pin Name
Buffer
Type
Description
17
17
I/O
TTL
RA1
18
18
I/O
TTL
RA2
I/O
TTL
RA3
I/O
TTL
RA4/T0CKI
I/O
ST
RB0/INT
I/O
TTL/ST (1)
RB1
I/O
TTL
RB2
I/O
TTL
RB3
I/O
TTL
RB4
10
10
I/O
TTL
RB5
11
11
I/O
TTL
RB6
12
12
I/O
TTL/ST (2)
(2)
TTL/ST
RB7
13
13
I/O
VSS
VDD
14
14
Legend: I= input
O = output
I/O = Input/Output
P = power
= Not used
TTL = TTL input
ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
DS30430C-page 9
PIC16F8X
3.1
3.2
Instruction Flow/Pipelining
FIGURE 3-2:
CLOCK/INSTRUCTION CYCLE
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Internal
phase
clock
Q3
Q4
PC
PC
OSC2/CLKOUT
(RC mode)
EXAMPLE 3-1:
PC+2
1. MOVLW 55h
2. MOVWF PORTB
3. CALL SUB_1
4. BSF
PC+1
PORTA, BIT3
Fetch 1
Execute 1
Fetch 2
Execute 2
Fetch 3
Execute 3
Fetch 4
Flush
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is flushed from the pipeline while the new instruction is being fetched and then executed.
DS30430C-page 10
PIC16F8X
MEMORY ORGANIZATION
4.1
FIGURE 4-1:
PC<12:0>
13
CALL, RETURN
RETFIE, RETLW
Stack Level 1
Stack Level 8
User Memory
Space
4.0
Reset Vector
0000h
0004h
1FFh
1FFFh
FIGURE 4-2:
PC<12:0>
13
CALL, RETURN
RETFIE, RETLW
Stack Level 1
Stack Level 8
Reset Vector
0000h
0004h
User Memory
Space
3FFh
1FFFh
DS30430C-page 11
PIC16F8X
4.2
4.2.1
4.2.2
DS30430C-page 12
PIC16F8X
FIGURE 4-1:
File Address
FIGURE 4-2:
File Address
File Address
80h
00h
Indirect addr.(1)
OPTION
81h
01h
TMR0
OPTION
81h
PCL
82h
02h
PCL
PCL
82h
STATUS
STATUS
83h
03h
STATUS
STATUS
83h
FSR
FSR
84h
04h
FSR
FSR
84h
05h
PORTA
TRISA
85h
05h
PORTA
TRISA
85h
06h
PORTB
TRISB
86h
06h
PORTB
TRISB
86h
87h
07h
08h
EEDATA
EECON1
88h
08h
EEDATA
EECON1
88h
09h
EEADR
EECON2(1)
89h
09h
EEADR
EECON2(1)
89h
0Ah
PCLATH
PCLATH
8Ah
0Ah
PCLATH
PCLATH
8Ah
0Bh
INTCON
INTCON
8Bh
0Bh
INTCON
INTCON
8Bh
8Ch
0Ch
00h
Indirect addr.(1)
01h
TMR0
02h
PCL
03h
04h
Indirect addr.(1)
07h
0Ch
36
General
Purpose
registers
(SRAM)
Mapped
(accesses)
in Bank 0
2Fh
30h
File Address
8Ch
Mapped
(accesses)
in Bank 0
4Fh
50h
7Fh
FFh
Bank 0
Bank 1
80h
87h
68
General
Purpose
registers
(SRAM)
AFh
B0h
Indirect addr.(1)
CFh
D0h
7Fh
FFh
Bank 0
Bank 1
DS30430C-page 13
PIC16F8X
TABLE 4-1
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on all
other resets
(Note3)
Bank 0
00h
INDF
---- ----
---- ----
01h
TMR0
xxxx xxxx
uuuu uuuu
02h
PCL
0000 0000
0000 0000
(2)
IRP
RP1
TO
RP0
PD
DC
03h
STATUS
04h
FSR
05h
PORTA
RA4/T0CKI
RA3
RA2
RA1
06h
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
07h
0001 1xxx
000q quuu
xxxx xxxx
uuuu uuuu
RA0
---x xxxx
---u uuuu
RB0/INT
xxxx xxxx
uuuu uuuu
---- ----
---- ----
08h
EEDATA
xxxx xxxx
uuuu uuuu
09h
EEADR
xxxx xxxx
uuuu uuuu
0Ah
PCLATH
---0 0000
---0 0000
0Bh
INTCON
GIE
EEIE
T0IE
0000 000x
0000 000u
---- ----
---- ----
1111 1111
1111 1111
0000 0000
0000 0000
RBIE
T0IF
INTF
RBIF
Bank 1
80h
INDF
81h
OPTION_
REG
82h
PCL
83h
STATUS (2)
84h
FSR
85h
TRISA
86h
TRISB
87h
88h
EECON1
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
RP1
RP0
TO
PD
DC
0001 1xxx
000q quuu
xxxx xxxx
uuuu uuuu
---1 1111
---1 1111
1111 1111
1111 1111
---- ----
---- ----
---0 x000
---0 q000
89h
EECON2
0Ah
PCLATH
0Bh
INTCON
GIE
EEIE
T0IE
EEIF
WRERR
WREN
WR
RD
RBIE
T0IF
INTF
RBIF
---- ----
---- ----
---0 0000
---0 0000
0000 000x
0000 000u
DS30430C-page 14
PIC16F8X
4.2.2.1
STATUS REGISTER
FIGURE 4-1:
R/W-0
IRP
R/W-0
RP1
R/W-0
RP0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
bit7
bit 7:
R/W-x
C
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as 0
- n = Value at POR reset
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)
00 = Bank 0 (00h - 7Fh)
01 = Bank 1 (80h - FFh)
10 = Bank 2 (100h - 17Fh)
11 = Bank 3 (180h - 1FFh)
Each bank is 128 bytes. Only bit RP0 is used by the PIC16F8X. RP1 should be maintained clear.
bit 4:
bit 3:
bit 2:
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1:
DC: Digit carry/borrow bit (for ADDWF and ADDLW instructions) (For borrow the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0:
DS30430C-page 15
PIC16F8X
4.2.2.2
OPTION_REG REGISTER
Note:
FIGURE 4-1:
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit7
bit0
bit 7:
bit 6:
bit 5:
bit 4:
bit 3:
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as 0
- n = Value at POR reset
DS30430C-page 16
TMR0 Rate
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
WDT Rate
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
PIC16F8X
4.2.2.3
INTCON REGISTER
Note:
FIGURE 4-1:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-x
GIE
EEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
bit7
bit 7:
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as 0
- n = Value at POR reset
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
DS30430C-page 17
PIC16F8X
4.3
FIGURE 4-1:
LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
12
PCL
8 7
0
INST with PCL
as dest
PC
8
PCLATH<4:0>
ALU result
4.4
Stack
PCLATH
Note:
PCH
12 11 10
PCL
0
8 7
PC
GOTO, CALL
2
PCLATH<4:3>
11
Opcode <10:0>
PCLATH
4.3.1
COMPUTED GOTO
The PIC16F83 and PIC16CR83 have 512 words of program memory. The PIC16F84 and PIC16CR84 have
1K of program memory. The CALL and GOTO instructions have an 11-bit address range. This 11-bit address
range allows a branch within a 2K program memory
page size. For future PIC16F8X program memory
expansion, there must be another two bits to specify
the program memory page. These paging bits come
from the PCLATH<4:3> bits (Figure 4-1). When doing a
CALL or a GOTO instruction, the user must ensure that
these page bits (PCLATH<4:3>) are programmed to
the desired program memory page. If a CALL instruction (or interrupt) is executed, the entire 13-bit PC is
pushed onto the stack (see next section). Therefore,
DS30430C-page 18
PIC16F8X
4.5
The INDF register is not a physical register. Addressing INDF actually addresses the register whose
address is contained in the FSR register (FSR is a
pointer). This is indirect addressing.
EXAMPLE 4-2:
EXAMPLE 4-1:
NEXT
INDIRECT ADDRESSING
movlw
movwf
clrf
incf
btfss
goto
0x20
FSR
INDF
FSR
FSR,4
NEXT
;initialize pointer
; to RAM
;clear INDF register
;inc pointer
;all done?
;NO, clear next
CONTINUE
:
;YES, continue
FIGURE 4-1:
DIRECT/INDIRECT ADDRESSING
Indirect Addressing
Direct Addressing
RP1 RP0
bank select
from opcode
IRP
location select
bank select
00
01
10
11
not used
not used
Bank 2
Bank 3
(FSR)
location select
00h
00h
0Bh
0Ch
Data
Memory (3)
Addresses
map back
to Bank 0
2Fh (1)
30h (1)
4Fh (2)
50h (2)
7Fh
7Fh
Bank 0
Bank 1
DS30430C-page 19
PIC16F8X
NOTES:
DS30430C-page 20
PIC16F8X
5.0
I/O PORTS
EXAMPLE 5-1:
INITIALIZING PORTA
CLRF
PORTA
BSF
MOVLW
STATUS, RP0
0x0F
MOVWF
TRISA
FIGURE 5-2:
5.1
;
;
;
;
;
;
;
;
;
;
;
Data
bus
WR
PORT
Initialize PORTA by
setting output
data latches
Select Bank 1
Value used to
initialize data
direction
Set RA<3:0> as inputs
RA4 as outputs
TRISA<7:5> are always
read as 0.
CK
N
Data Latch
VSS
WR
TRIS
CK
Schmitt
Trigger
input
buffer
TRIS Latch
FIGURE 5-1:
Data
bus
RD TRIS
D
WR
Port
RA4 pin
Q
Q
VDD
CK
D
EN
EN
P
RD PORT
Data Latch
N
D
WR
TRIS
I/O pin
Q
VSS
CK
TRIS Latch
TTL
input
buffer
RD TRIS
Q
EN
RD PORT
DS30430C-page 21
PIC16F8X
TABLE 5-1
PORTA FUNCTIONS
Name
Bit0
Buffer Type
RA0
RA1
RA2
RA3
RA4/T0CKI
bit0
bit1
bit2
bit3
bit4
TTL
TTL
TTL
TTL
ST
Function
Input/output
Input/output
Input/output
Input/output
Input/output or external clock input for TMR0.
Output is open drain type.
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 5-2
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
05h
PORTA
RA4/T0CKI
RA3
RA2
85h
TRISA
TRISA4
TRISA3
TRISA2
Bit 0
Value on
Power-on
Reset
Value on all
other resets
RA1
RA0
---x xxxx
---u uuuu
TRISA1
TRISA0
---1 1111
---1 1111
Bit 1
Legend: x = unknown, u = unchanged, - = unimplemented read as 0. Shaded cells are unimplemented, read as 0
DS30430C-page 22
PIC16F8X
5.2
FIGURE 5-3:
Read (or write) PORTB. This will end the mismatch condition.
Clear flag bit RBIF.
FIGURE 5-4:
RBPU(1)
VDD
RBPU(1)
Data bus
weak
P pull-up
Data Latch
D
WR Port
Q
I/O
pin(2)
CK
Data bus
WR Port
WR TRIS
WR TRIS
Data Latch
D
Q
I/O
pin(2)
CK
TRIS Latch
D
Q
TRIS Latch
D
weak
P pull-up
TTL
Input
Buffer
CK
TTL
Input
Buffer
CK
RD TRIS
Q
Latch
RD TRIS
Q
RD Port
RD Port
D
EN
EN
Set RBIF
RB0/INT
From other
RB7:RB4 pins
Schmitt Trigger
Buffer
RD Port
EN
DS30430C-page 23
PIC16F8X
EXAMPLE 5-1:
INITIALIZING PORTB
CLRF
PORTB
BSF
MOVLW
STATUS, RP0
0xCF
MOVWF
TRISB
TABLE 5-3
Name
RB0/INT
;
;
;
;
;
;
;
;
;
;
Initialize PORTB by
setting output
data latches
Select Bank 1
Value used to
initialize data
direction
Set RB<3:0> as inputs
RB<5:4> as outputs
RB<7:6> as inputs
PORTB FUNCTIONS
Bit
Buffer Type
bit0
TABLE 5-4
Address
Name
TTL/ST
(1)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on all
other resets
uuuu uuuu
06h
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
xxxx xxxx
86h
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
1111 1111
1111 1111
81h
OPTION_
REG
PS0
1111 1111
1111 1111
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
DS30430C-page 24
PIC16F8X
5.3
5.3.1
5.3.2
FIGURE 5-5:
EXAMPLE 5-1:
READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT
PC
Instruction
fetched
PC
PC + 1
Q1 Q2 Q3 Q4
PC + 2
PC + 3
NOP
NOP
RB7:RB0
Port pin
sampled here
TPD
Instruction
executed
NOP
MOVWF PORTB
write to
PORTB
Note:
MOVF PORTB,W
DS30430C-page 25
PIC16F8X
NOTES:
DS30430C-page 26
PIC16F8X
6.0
8-bit timer/counter
Readable and writable
8-bit software programmable prescaler
Internal or external clock select
Interrupt on overflow from FFh to 00h
Edge select for external clock
6.1
FIGURE 6-1:
TMR0 Interrupt
PSout
1
Sync with
Internal
clocks
1
RA4/T0CKI
pin
Programmable
Prescaler
TMR0 register
PSout
(2 cycle delay)
T0SE
3
PS2, PS1, PS0
PSA
T0CS
Note 1: Bits T0CS, T0SE, PS2, PS1, PS0 and PSA are located in the OPTION_REG register.
2: The prescaler is shared with the Watchdog Timer (Figure 6-6)
FIGURE 6-2:
PC
TMR0
PC
MOVWF TMR0
Instruction
Fetch
T0
T0+1
Instruction
Executed
PC+1
PC+2
PC+3
T0+2
NT0
NT0
Write TMR0
executed
Read TMR0
reads NT0
Read TMR0
reads NT0
PC+4
MOVF TMR0,W
NT0
Read TMR0
reads NT0
PC+5
PC+6
MOVF TMR0,W
NT0+1
Read TMR0
reads NT0 + 1
NT0+2
T0
Read TMR0
reads NT0 + 2
DS30430C-page 27
PIC16F8X
FIGURE 6-3:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC-1
PC
Instruction
Fetch
PC
PC+1
MOVWF TMR0
MOVF TMR0,W
PC+3
T0+1
T0
TMR0
PC+2
Instruction
Execute
PC+5
MOVF TMR0,W
PC+6
MOVF TMR0,W
NT0+1
NT0
Write TMR0
executed
FIGURE 6-4:
PC+4
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
CLKOUT(3)
TMR0 timer
FEh
T0IF bit 4
(INTCON<2>)
FFh
00h
01h
02h
GIE bit
(INTCON<7>)
Interrupt Latency(2)
INSTRUCTION FLOW
PC
PC
Instruction
fetched
Inst (PC)
Instruction
executed
Inst (PC-1)
PC +1
PC +1
Inst (PC+1)
Inst (PC)
Dummy cycle
0004h
0005h
Inst (0004h)
Inst (0005h)
Dummy cycle
Inst (0004h)
DS30430C-page 28
PIC16F8X
6.2
6.2.2
6.2.1
6.3
Prescaler
DS30430C-page 29
PIC16F8X
FIGURE 6-5:
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Ext. Clock/Prescaler
Output After Sampling
Increment TMR0 (Q4)
TMR0
T0
T0 + 1
T0 + 2
Note 1: Delay from clock input change to TMR0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).
Therefore, the error in measuring the interval between two edges on TMR0 input = 4Tosc max.
2: External clock if no prescaler selected, Prescaler output otherwise.
3: The arrows indicate where sampling occurs. A small clock pulse may be missed by sampling.
FIGURE 6-6:
CLKOUT (= Fosc/4)
0
RA4/T0CKI
pin
M
U
X
1
M
U
X
SYNC
2
Cycles
TMR0 register
T0SE
T0CS
Watchdog
Timer
M
U
X
PSA
8-bit Prescaler
8
8 - to - 1MUX
PS2:PS0
PSA
0
MUX
PSA
WDT
time-out
Note: T0CS, T0SE, PSA, PS2:PS0 are bits in the OPTION_REG register.
DS30430C-page 30
PIC16F8X
6.3.1
EXAMPLE 6-1:
TABLE 6-1
Address
CHANGING PRESCALER
(TIMER0WDT)
BCF
CLRF
STATUS, RP0
TMR0
BSF
CLRWDT
MOVLW
MOVWF
BCF
STATUS, RP0
bxxxx1xxx
OPTION_REG
STATUS, RP0
EXAMPLE 6-2:
;Bank 0
;Clear TMR0
; and Prescaler
;Bank 1
;Clears WDT
;Select new
; prescale value
;Bank 0
CHANGING PRESCALER
(WDTTIMER0)
CLRWDT
BSF
MOVLW
STATUS, RP0
bxxxx0xxx
MOVWF
BCF
OPTION_REG
STATUS, RP0
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on all
other resets
xxxx xxxx
uuuu uuuu
01h
TMR0
0Bh
INTCON
GIE
EEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 0000
81h
OPTION_
REG
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
85h
TRISA
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
---1 1111
---1 1111
Legend: x = unknown, u = unchanged. - = unimplemented read as 0. Shaded cells are not associated with Timer0.
DS30430C-page 31
PIC16F8X
NOTES:
DS30430C-page 32
PIC16F8X
7.0
EECON1
EECON2
EEDATA
EEADR
7.1
FIGURE 7-1:
EEADR
R/W-0
R/W-x
R/W-0
R/S-0
R/S-x
EEIF
WRERR
WREN
WR
RD
bit7
bit0
R
W
S
U
= Readable bit
= Writable bit
= Settable bit
= Unimplemented bit,
read as 0
- n = Value at POR reset
bit 7:5
Unimplemented: Read as 0
bit 4
bit 3
bit 2
bit 1
bit 0
DS30430C-page 33
PIC16F8X
EECON1 and EECON2 Registers
7.3
EXAMPLE 7-1:
BCF
MOVLW
MOVWF
BSF
BSF
BCF
MOVF
STATUS, RP0
CONFIG_ADDR
EEADR
STATUS, RP0
EECON1, RD
STATUS, RP0
EEDATA, W
DS30430C-page 34
;
;
;
;
;
;
;
Bank 0
7.4
EXAMPLE 7-1:
Required
Sequence
7.2
BSF
BCF
BSF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
STATUS, RP0
INTCON, GIE
EECON1, WREN
55h
EECON2
AAh
EECON2
EECON1,WR
BSF
INTCON, GIE
;
;
;
;
;
;
;
;
;
;
Bank 1
Disable INTs.
Enable Write
Write 55h
Write AAh
Set WR bit
begin write
Enable INTs.
Address to read
Bank 1
EE Read
Bank 0
W = EEDATA
PIC16F8X
7.5
Write Verify
SUBWF EEDATA, W
BTFSS STATUS, Z
GOTO WRITE_ERR
:
:
Depending on the application, good programming practice may dictate that the value written to the Data
EEPROM should be verified (Example 7-1) to the
desired value to be written. This should be used in
applications where an EEPROM bit will be stressed
near the specification limit. The Total Endurance disk
will help determine your comfort level.
7.6
WRITE VERIFY
BCF
:
:
MOVF
BSF
STATUS, RP0 ;
;
;
EEDATA, W
;
STATUS, RP0 ;
BSF
EECON1, RD
Bank 0
Any code can go here
7.7
Must be in Bank 0
Bank 1
BCF
;
; Is the value written (in W reg) and
;
read (in EEDATA) the same?
;
Address
READ
TABLE 7-1
Is difference 0?
NO, Write error
YES, Good write
Continue program
EXAMPLE 7-1:
;
;
;
;
;
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on all
other resets
08h
EEDATA
xxxx xxxx
uuuu uuuu
09h
EEADR
xxxx xxxx
uuuu uuuu
---0 x000
---0 q000
---- ----
---- ----
88h
EECON1
89h
EECON2
EEIF
WRERR
WREN
WR
RD
Legend: x = unknown, u = unchanged, - = unimplemented read as 0, q = value depends upon condition. Shaded cells are not
used by Data EEPROM.
DS30430C-page 35
PIC16F8X
NOTES:
DS30430C-page 36
PIC16F8X
8.0
DS30430C-page 37
PIC16F8X
8.1
Configuration Bits
FIGURE 8-1:
R-u
R-u
R-u
R-u
R-u
R-u
R/P-u
R-u
R-u
R-u
CP
CP
CP
CP
CP
CP
DP
CP
CP
CP
bit13
R-u
R-u
R-u
R-u
bit 6:4
bit 3
bit 2
bit 1:0
DS30430C-page 38
PIC16F8X
FIGURE 8-2:
CP
CP
CP
CP
CP
CP
CP
R/P-u
R/P-u
CP
CP
R/P-u
R/P-u
R/P-u
R/P-u
bit13
bit0
R = Readable bit
P = Programmable bit
- n = Value at POR reset
u = unchanged
bit 2
bit 1:0
8.2
Oscillator Configurations
8.2.1
OSCILLATOR TYPES
LP
XT
HS
RC
8.2.2
FIGURE 8-3:
CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS, XT OR LP OSC
CONFIGURATION)
C1(1)
OSC1
XTAL
RF(3)
OSC2
RS(2)
C2(1)
Note1:
2:
3:
To
internal
logic
SLEEP
PIC16FXX
DS30430C-page 39
PIC16F8X
FIGURE 8-4:
Clock from
ext. system
PIC16FXX
Open
TABLE 8-1
OSC2
Ranges Tested:
Mode
Freq
XT
455 kHz
2.0 MHz
4.0 MHz
8.0 MHz
10.0 MHz
HS
Note :
OSC1/C1
OSC2/C2
47 - 100 pF 47 - 100 pF
15 - 33 pF 15 - 33 pF
15 - 33 pF 15 - 33 pF
15 - 33 pF 15 - 33 pF
15 - 33 pF 15 - 33 pF
Crystals Tested:
32.768 kHz
100 kHz
200 kHz
1.0 MHz
2.0 MHz
4.0 MHz
10.0 MHz
8.2.3
Epson C-001R32.768K-A
Epson C-2 100.00 KC-P
STD XTL 200.000 KHz
ECS ECS-10-13-2
ECS ECS-20-S-2
ECS ECS-40-S-4
ECS ECS-100-S-4
20 PPM
20 PPM
20 PPM
50 PPM
50 PPM
50 PPM
50 PPM
Resonators Tested:
455 kHz
2.0 MHz
4.0 MHz
8.0 MHz
10.0 MHz
Panasonic EFO-A455K04B
Murata Erie CSA2.00MG
Murata Erie CSA4.00MG
Murata Erie CSA8.00MT
Murata Erie CSA10.00MTZ
0.3%
0.5%
0.5%
0.5%
0.5%
FIGURE 8-5:
EXTERNAL PARALLEL
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
+5V
To Other
Devices
10k
4.7k
TABLE 8-2
Mode
Freq
OSC1/C1
OSC2/C2
LP
32 kHz
200 kHz
100 kHz
2 MHz
4 MHz
4 MHz
10 MHz
68 - 100 pF
15 - 33 pF
100 - 150 pF
15 - 33 pF
15 - 33 pF
15 - 33 pF
15 - 33 pF
68 - 100 pF
15 - 33 pF
100 - 150 pF
15 - 33 pF
15 - 33 pF
15 - 33 pF
15 - 33 pF
XT
HS
Note :
PIC16FXX
74AS04
CLKIN
74AS04
10k
XTAL
10k
20 pF
20 pF
DS30430C-page 40
PIC16F8X
FIGURE 8-6:
EXTERNAL SERIES
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
FIGURE 8-7:
RC OSCILLATOR MODE
VDD
Rext
330 k
330 k
74AS04
74AS04
To Other
Devices
PIC16FXX
Cext
74AS04
CLKIN
Fosc/4
Recommended values:
XTAL
Note:
RC OSCILLATOR
PIC16FXX
VSS
0.1 F
8.2.4
Internal
clock
OSC1
8.3
OSC2/CLKOUT
5 k Rext 100 k
Cext > 20pF
Reset
DS30430C-page 41
PIC16F8X
FIGURE 8-8:
MCLR
WDT
Module
SLEEP
WDT
Time_Out
Reset
VDD rise
detect
Power_on_Reset
VDD
OST/PWRT
OST
Chip_Reset
Q
OSC1/
CLKIN
PWRT
On-chip
RC OSC(1)
Enable PWRT
DS30430C-page 42
PIC16F8X
TABLE 8-3
Condition
STATUS Register
Power-on Reset
000h
0001 1xxx
000h
000u uuuu
000h
0001 0uuu
000h
0000 1uuu
WDT Wake-up
PC + 1
PC + 1
uuu0 0uuu
(1)
uuu1 0uuu
TABLE 8-4
Register
Address
Power-on Reset
xxxx xxxx
uuuu uuuu
uuuu uuuu
INDF
00h
---- ----
---- ----
---- ----
TMR0
01h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PCL
02h
0000h
0000h
STATUS
03h
0001 1xxx
000q quuu(3)
uuuq quuu(3)
FSR
04h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTA
05h
---x xxxx
---u uuuu
---u uuuu
PORTB
06h
xxxx xxxx
uuuu uuuu
uuuu uuuu
EEDATA
08h
xxxx xxxx
uuuu uuuu
uuuu uuuu
EEADR
09h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PCLATH
0Ah
---0 0000
---0 0000
---u uuuu
INTCON
0Bh
0000 000x
0000 000u
uuuu uuuu(1)
INDF
80h
---- ----
---- ----
---- ----
OPTION_REG
81h
1111 1111
1111 1111
uuuu uuuu
PCL
82h
0000h
0000h
PC + 1(2)
PC + 1
(3)
uuuq quuu(3)
STATUS
83h
0001 1xxx
000q quuu
FSR
84h
xxxx xxxx
uuuu uuuu
uuuu uuuu
TRISA
85h
---1 1111
---1 1111
---u uuuu
TRISB
86h
1111 1111
1111 1111
uuuu uuuu
EECON1
88h
---0 x000
---0 q000
---0 uuuu
EECON2
89h
---- ----
---- ----
---- ----
PCLATH
8Ah
---0 0000
---0 0000
---u uuuu
INTCON
8Bh
0000 000x
0000 000u
uuuu uuuu(1)
DS30430C-page 43
PIC16F8X
8.4
8.5
FIGURE 8-9:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR SLOW
VDD POWER-UP)
VDD
VDD
D
R
R1
MCLR
C
PIC16FXX
8.6
DS30430C-page 44
PIC16F8X
FIGURE 8-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 8-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
DS30430C-page 45
PIC16F8X
FIGURE 8-12: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 8-13: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME
V1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
When VDD rises very slowly, it is possible that the TPWRT time-out and TOST time-out will expire before VDD
has reached its final value. In this example, the chip will reset properly if, and only if, V1 VDD min.
DS30430C-page 46
PIC16F8X
8.7
TABLE 8-5
Power-up
PWRT
Enabled
PWRT
Disabled
Wake-up
from
SLEEP
XT, HS, LP
72 ms +
1024TOSC
1024TOSC
1024TOSC
RC
72 ms
TO
PD
1
0
x
0
0
1
1
1
x
0
1
0
1
0
VDD
VDD
33k
10k
TABLE 8-6
Reset on Brown-Out
TIME-OUT IN VARIOUS
SITUATIONS
Oscillator
Configuration
8.8
40k
PIC16F8X
40k
PIC16F8X
VDD
MCLR
R1
R1 + R2
= 0.7V
DS30430C-page 47
PIC16F8X
8.9
Interrupts
T0IF
T0IE
INTF
INTE
Wake-up
(If in SLEEP mode)
Interrupt to CPU
RBIF
RBIE
EEIF
EEIE
GIE
DS30430C-page 48
PIC16F8X
FIGURE 8-17: INT PIN INTERRUPT TIMING
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
CLKOUT 3
4
INT pin
INTF flag
(INTCON<1>)
Interrupt Latency 2
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
PC
Instruction
fetched
Inst (PC)
Instruction
executed
Inst (PC-1)
PC+1
Inst (PC+1)
Inst (PC)
0004h
PC+1
Dummy Cycle
0005h
Inst (0004h)
Inst (0005h)
Dummy Cycle
Inst (0004h)
8.9.1
INT INTERRUPT
8.9.3
PORT RB INTERRUPT
TMR0 INTERRUPT
DS30430C-page 49
PIC16F8X
8.10
EXAMPLE 8-1:
PUSH
MOVWF
SWAPF
MOVWF
:
:
:
:
SWAPF
W_TEMP
STATUS, W
STATUS_TEMP
MOVWF
STATUS
SWAPF
SWAPF
W_TEMP, F
W_TEMP, W
ISR
POP
DS30430C-page 50
STATUS_TEMP, W
;
;
;
:
;
;
;
;
;
;
;
;
;
PIC16F8X
8.11
WDT PERIOD
0
WDT Timer
M
U
X
Postscaler
8
8 - to -1 MUX
PS2:PS0
PSA
WDT
Enable Bit
0
MUX
PSA
WDT
Time-out
TABLE 8-7
Address
Name
2007h
Config. bits
81h
OPTION_
REG
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
(2)
(2)
(2)
(2)
PWRTE(1)
WDTE
FOSC1
FOSC0
(2)
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
Value on all
other resets
1111 1111
DS30430C-page 51
PIC16F8X
8.12
8.12.2
SLEEP
Q1 Q2 Q3 Q4
Q1
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3
Q4
OSC1
TOST(2)
CLKOUT(4)
INT pin
INTF flag
(INTCON<1>)
Interrupt Latency
(Note 2)
GIE bit
(INTCON<7>)
Processor in
SLEEP
INSTRUCTION FLOW
PC
Instruction
fetched
Instruction
executed
Note
1:
2:
3:
4:
PC
Inst(PC) = SLEEP
Inst(PC - 1)
PC+1
Inst(PC + 1)
SLEEP
PC+2
PC+2
PC + 2
Inst(PC + 2)
Inst(PC + 1)
Dummy cycle
0004h
0005h
Inst(0004h)
Inst(0005h)
Dummy cycle
Inst(0004h)
DS30430C-page 52
PIC16F8X
8.12.3
8.13
8.14
ID Locations
8.15
PIC16F8X
microcontrollers
can
be
serially
programmed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for power, ground, and the programming
voltage. Customers can manufacture boards with
unprogrammed devices, and then program the
microcontroller just before shipping the product,
allowing the most recent firmware or custom firmware
to be programmed.
The device is placed into a program/verify mode by
holding the RB6 and RB7 pins low, while raising the
MCLR pin from VIL to VIHH (see programming
specification). RB6 becomes the programming clock
and RB7 becomes the programming data. Both RB6
and RB7 are Schmitt Trigger inputs in this mode.
After reset, to place the device into programming/verify
mode, the program counter (PC) points to location 00h.
A 6-bit command is then supplied to the device, 14-bits
of program data is then supplied to or from the device,
using load or read-type instructions. For complete
details of serial programming, please refer to the
PIC16CXX Programming Specifications (Literature
#DS30189).
External
Connector
Signals
To Normal
Connections
PIC16FXX
+5V
VDD
0V
VSS
VPP
MCLR/VPP
CLK
RB6
Data I/O
RB7
VDD
To Normal
Connections
DS30430C-page 53
PIC16F8X
DS30430C-page 54
PIC16F8X
9.0
TABLE 9-1
OPCODE FIELD
DESCRIPTIONS
Field
Description
Label name
TOS
Top of Stack
PC
Program Counter
PCLATH
GIE
WDT
Watchdog Timer/Counter
TO
Time-out bit
PD
Power-down bit
dest
[ ]
Options
italics
Byte-oriented operations
Bit-oriented operations
Literal and control operations
All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction.
In this case, the execution takes two instruction cycles
with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for
an oscillator frequency of 4 MHz, the normal instruction
execution time is 1 s. If a conditional test is true or the
program counter is changed as a result of an instruction, the instruction execution time is 2 s.
Table 9-2 lists the instructions recognized by the
MPASM assembler.
Figure 9-1 shows the general formats that the instructions can have.
Note:
FIGURE 9-1:
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
label
( )
<>
OPCODE
Contents
0
k (literal)
Assigned to
Register bit field
In the set of
User defined term (font is courier)
11
OPCODE
10
0
k (literal)
DS30430C-page 55
PIC16F8X
TABLE 9-2
Mnemonic,
Operands
Description
Cycles
14-Bit Opcode
MSb
LSb
Status
Affected
Notes
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
dfff
dfff
lfff
0xxx
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
xxxx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
C,DC,Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C,DC,Z
Z
1,2
1,2
2
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1 (2)
1 (2)
01
01
01
01
1,2
1,2
3
3
k
k
k
k
k
k
k
k
k
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
C,DC,Z
Z
TO,PD
Z
TO,PD
C,DC,Z
Z
Note 1:
When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is 1 for a pin configured as input and is driven low by an external
device, the data will be written back with a 0.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned
to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
DS30430C-page 56
PIC16F8X
9.1
Instruction Descriptions
ADDLW
ANDLW
Syntax:
[label] ADDLW
Syntax:
[label] ANDLW
Operands:
0 k 255
Operands:
0 k 255
Operation:
(W) + k (W)
Operation:
Status Affected:
C, DC, Z
Status Affected:
Encoding:
11
111x
kkkk
kkkk
Encoding:
11
1001
kkkk
kkkk
Description:
Description:
Words:
Words:
Cycles:
Cycles:
Q Cycle Activity:
Example:
Q1
Q2
Q3
Q4
Decode
Read
literal k
Process
data
Write to
W
ADDLW
0x15
Q Cycle Activity:
Example
=
=
ADDWF
Add W and f
Q3
Q4
Process
data
Write to
W
ANDLW
0x5F
W
0x10
0xA3
After Instruction
After Instruction
W
Q2
Read
literal "k"
Before Instruction
Before Instruction
W
Q1
Decode
0x25
ANDWF
AND W with f
0x03
Syntax:
[label] ADDWF
Syntax:
[label] ANDWF
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
Operation:
Status Affected:
C, DC, Z
Status Affected:
Encoding:
00
f,d
0111
dfff
ffff
Encoding:
00
f,d
0101
dfff
ffff
Description:
Description:
Words:
Words:
Cycles:
Cycles:
Q Cycle Activity:
Example
Q1
Q2
Q3
Q4
Decode
Read
register
f
Process
data
Write to
destination
ADDWF
FSR, 0
Before Instruction
W =
FSR =
Example
Q1
Q2
Q3
Q4
Decode
Read
register
f
Process
data
Write to
destination
ANDWF
FSR, 1
Before Instruction
0x17
0xC2
After Instruction
W =
FSR =
Q Cycle Activity:
W =
FSR =
0x17
0xC2
After Instruction
0xD9
0xC2
W =
FSR =
0x17
0x02
DS30430C-page 57
PIC16F8X
BCF
Bit Clear f
BTFSC
Syntax:
[label] BCF
Syntax:
Operands:
0 f 127
0b7
Operands:
0 f 127
0b7
Operation:
0 (f<b>)
Operation:
skip if (f<b>) = 0
Status Affected:
None
Status Affected:
None
Encoding:
01
f,b
00bb
bfff
ffff
Description:
Words:
Cycles:
Q Cycle Activity:
Example
Q1
Q2
Q3
Q4
Decode
Read
register
f
Process
data
Write
register f
BCF
Encoding:
10bb
bfff
ffff
Words:
Cycles:
1(2)
Q Cycle Activity:
FLAG_REG, 7
01
Description:
Before Instruction
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
data
No-Operat
ion
Q3
Q4
FLAG_REG = 0xC7
If Skip:
After Instruction
FLAG_REG = 0x47
(2nd Cycle)
Q1
Q2
No-Operat
ion
Example
HERE
FALSE
TRUE
BTFSC
GOTO
FLAG,1
PROCESS_CODE
Before Instruction
PC =
address HERE
After Instruction
BSF
Bit Set f
Syntax:
[label] BSF
Operands:
0 f 127
0b7
Operation:
1 (f<b>)
Status Affected:
None
Encoding:
Description:
01
Cycles:
Example
01bb
bfff
ffff
Words:
Q Cycle Activity:
if FLAG<1> = 0,
PC =
address TRUE
if FLAG<1>=1,
PC =
address FALSE
f,b
Q1
Q2
Q3
Q4
Decode
Read
register
f
Process
data
Write
register f
BSF
FLAG_REG,
Before Instruction
FLAG_REG = 0x0A
After Instruction
FLAG_REG = 0x8A
DS30430C-page 58
PIC16F8X
BTFSS
CALL
Call Subroutine
Syntax:
Syntax:
[ label ] CALL k
Operands:
0 f 127
0b<7
Operands:
0 k 2047
Operation:
(PC)+ 1 TOS,
k PC<10:0>,
(PCLATH<4:3>) PC<12:11>
Status Affected:
None
Operation:
skip if (f<b>) = 1
Status Affected:
None
Encoding:
Description:
01
Cycles:
1(2)
If Skip:
ffff
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
data
No-Operat
ion
(2nd Cycle)
Q1
Q2
No-Operat
ion
Example
bfff
Words:
Q Cycle Activity:
11bb
HERE
FALSE
TRUE
Q3
10
Words:
Cycles:
Q Cycle Activity:
FLAG,1
PROCESS_CODE
2nd Cycle
Example
0kkk
kkkk
kkkk
Q1
Q2
Q3
Q4
Decode
Read
literal k,
Push PC
to Stack
Process
data
Write to
PC
Q4
No-Opera
tion
HERE
CALL
THERE
Before Instruction
PC = Address HERE
After Instruction
Before Instruction
PC =
Description:
1st Cycle
BTFSC
GOTO
Encoding:
address HERE
PC = Address THERE
TOS = Address HERE+1
After Instruction
if FLAG<1> = 0,
PC =
address FALSE
if FLAG<1> = 1,
PC =
address TRUE
DS30430C-page 59
PIC16F8X
CLRF
Clear f
Syntax:
[label] CLRF
Operands:
0 f 127
Operation:
00h (f)
1Z
Status Affected:
Encoding:
00
0001
1fff
ffff
CLRW
Clear W
Syntax:
[ label ] CLRW
Operands:
None
Operation:
00h (W)
1Z
Status Affected:
Encoding:
00
0001
0xxx
xxxx
Description:
Description:
Words:
Words:
Cycles:
Cycles:
Q Cycle Activity:
Example
Q1
Q2
Q3
Q4
Decode
Read
register
f
Process
data
Write
register f
CLRF
Q Cycle Activity:
Example
FLAG_REG
=
0x5A
Q3
Q4
Process
data
Write to
W
CLRW
=
=
0x00
1
0x5A
After Instruction
After Instruction
FLAG_REG
Z
Q2
No-Opera
tion
Before Instruction
Before Instruction
FLAG_REG
Q1
Decode
W
Z
=
=
0x00
1
CLRWDT
Syntax:
[ label ] CLRWDT
Operands:
None
Operation:
00h WDT
0 WDT prescaler,
1 TO
1 PD
Status Affected:
TO, PD
Encoding:
00
0000
0110
0100
Description:
CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler
of the WDT. Status bits TO and PD are
set.
Words:
Cycles:
Q Cycle Activity:
Example
Q1
Q2
Q3
Q4
Decode
No-Opera
tion
Process
data
Clear
WDT
Counter
CLRWDT
Before Instruction
WDT counter =
After Instruction
WDT counter =
WDT prescaler=
TO
=
PD
=
DS30430C-page 60
0x00
0
1
1
PIC16F8X
COMF
Complement f
Syntax:
[ label ] COMF
Operands:
0 f 127
d [0,1]
Operation:
(f) (destination)
Status Affected:
Encoding:
Description:
00
f,d
1001
dfff
ffff
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register
f
Process
data
Write to
destination
DECFSZ
Decrement f, Skip if 0
Syntax:
Operands:
0 f 127
d [0,1]
Operation:
(f) - 1 (destination);
skip if result = 0
Status Affected:
None
Encoding:
COMF
0x13
Cycles:
1(2)
=
=
0x13
0xEC
If Skip:
After Instruction
REG1
W
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
data
Write to
destination
Q3
Q4
Decrement f
Syntax:
Operands:
0 f 127
d [0,1]
Operation:
(f) - 1 (destination)
Status Affected:
Example
DECFSZ
GOTO
CONTINUE
CNT, 1
LOOP
Before Instruction
00
0011
dfff
ffff
Description:
Words:
Cycles:
Example
HERE
PC
Encoding:
Q Cycle Activity:
(2nd Cycle)
Q1
Q2
No-Operat
ion
DECF
ffff
Words:
Before Instruction
=
dfff
REG1,0
REG1
1011
Description:
Q Cycle Activity:
Example
00
Q1
Q2
Q3
Q4
Decode
Read
register
f
Process
data
Write to
destination
DECF
address HERE
After Instruction
CNT
if CNT
PC
if CNT
PC
=
=
=
CNT - 1
0,
address CONTINUE
0,
address HERE+1
CNT, 1
Before Instruction
CNT
Z
=
=
0x01
0
=
=
0x00
1
After Instruction
CNT
Z
DS30430C-page 61
PIC16F8X
Unconditional Branch
INCF
Increment f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 k 2047
Operands:
Operation:
k PC<10:0>
PCLATH<4:3> PC<12:11>
0 f 127
d [0,1]
Operation:
(f) + 1 (destination)
None
Status Affected:
GOTO
Status Affected:
Encoding:
10
GOTO k
1kkk
kkkk
kkkk
Encoding:
00
INCF f,d
1010
dfff
ffff
Description:
Description:
Words:
Words:
Cycles:
Cycles:
Q Cycle Activity:
1st Cycle
2nd Cycle
Q1
Q2
Q3
Q4
Decode
Read
literal k
Process
data
Write to
PC
No-Operat
ion
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register
f
Process
data
Write to
destination
Example
INCF
CNT, 1
Before Instruction
Example
GOTO THERE
CNT
Z
After Instruction
PC =
DS30430C-page 62
Address THERE
=
=
0xFF
0
=
=
0x00
1
After Instruction
CNT
Z
PIC16F8X
INCFSZ
Increment f, Skip if 0
IORLW
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operands:
0 k 255
Operation:
(f) + 1 (destination),
skip if result = 0
Operation:
Status Affected:
Status Affected:
00
Cycles:
1(2)
If Skip:
dfff
ffff
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
data
Write to
destination
Q3
Q4
(2nd Cycle)
Q1
Q2
No-Operat
ion
Example
1111
Words:
Q Cycle Activity:
Encoding:
None
Encoding:
Description:
INCFSZ f,d
11
IORLW k
1000
kkkk
kkkk
Description:
Words:
Cycles:
Q Cycle Activity:
Example
Q1
Q2
Q3
Q4
Decode
Read
literal k
Process
data
Write to
W
IORLW
0x35
Before Instruction
W
0x9A
After Instruction
W
Z
=
=
0xBF
1
HERE
INCFSZ
GOTO
CONTINUE
CNT, 1
LOOP
Before Instruction
PC
address HERE
After Instruction
CNT =
if CNT=
PC
=
if CNT
PC
=
CNT + 1
0,
address CONTINUE
0,
address HERE +1
DS30430C-page 63
PIC16F8X
IORWF
Inclusive OR W with f
MOVLW
Move Literal to W
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operands:
0 k 255
Operation:
k (W)
Status Affected:
None
IORWF
f,d
Operation:
Status Affected:
Encoding:
Description:
00
0100
dfff
ffff
Words:
Cycles:
Q Cycle Activity:
Example
Encoding:
11
Q2
Q3
Q4
Decode
Read
register
f
Process
data
Write to
destination
IORWF
00xx
kkkk
kkkk
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
MOVLW k
Example
Q1
Q2
Q3
Q4
Decode
Read
literal k
Process
data
Write to
W
MOVLW
0x5A
After Instruction
RESULT, 0
0x5A
Before Instruction
RESULT =
W
=
0x13
0x91
After Instruction
RESULT =
W
=
Z
=
0x13
0x93
1
MOVWF
Move W to f
Syntax:
[ label ]
0 f 127
d [0,1]
Operands:
0 f 127
Operation:
(W) (f)
Operation:
(f) (destination)
Status Affected:
None
Status Affected:
Encoding:
MOVF
Move f
Syntax:
[ label ]
Operands:
Encoding:
Description:
00
1000
dfff
ffff
Words:
Cycles:
Q Cycle Activity:
MOVF f,d
Q1
Q2
Q3
Q4
Decode
Read
register
f
Process
data
Write to
destination
00
MOVWF
0000
1fff
ffff
Description:
Words:
Cycles:
Q Cycle Activity:
Example
Q1
Q2
Q3
Q4
Decode
Read
register
f
Process
data
Write
register f
MOVWF
OPTION_REG
Before Instruction
OPTION =
W
=
0xFF
0x4F
After Instruction
Example
MOVF
FSR, 0
After Instruction
OPTION =
W
=
0x4F
0x4F
DS30430C-page 64
PIC16F8X
NOP
No Operation
RETFIE
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
None
Operands:
None
Operation:
No operation
Operation:
Status Affected:
None
TOS PC,
1 GIE
Status Affected:
None
Encoding:
00
NOP
0000
Description:
No operation.
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Example
0xx0
0000
Encoding:
Q2
Q3
0000
0000
1001
Description:
Words:
Cycles:
Q4
NOP
00
RETFIE
Q Cycle Activity:
1st Cycle
2nd Cycle
Example
Q1
Q2
Q3
Q4
Decode
No-Opera
tion
Set the
GIE bit
Pop from
the Stack
No-Operat
ion
RETFIE
After Interrupt
PC =
GIE =
OPTION
Syntax:
[ label ]
Operands:
None
Operation:
(W) OPTION
TOS
1
OPTION
00
0000
0110
0010
Description:
Words:
Cycles:
Example
To maintain upward compatibility
with future PIC16CXX products,
do not use this instruction.
DS30430C-page 65
PIC16F8X
RETLW
RETURN
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 k 255
Operands:
None
Operation:
k (W);
TOS PC
Operation:
TOS PC
Status Affected:
None
Status Affected:
None
Encoding:
Encoding:
RETLW k
11
Description:
01xx
kkkk
kkkk
Words:
Cycles:
Q Cycle Activity:
1st Cycle
2nd Cycle
Q1
Q2
Q3
Q4
Read
literal k
No-Opera
tion
Write to
W, Pop
from the
Stack
No-Operat
ion
0000
Words:
Cycles:
2
1st Cycle
2nd Cycle
Example
Q1
Decode
No-Operat
ion
Q2
Q3
Q4
RETURN
After Interrupt
CALL TABLE
TOS
;W contains table
;offset value
;W now has table value
TABLE ADDWF PC
RETLW k1
RETLW k2
1000
PC =
Example
0000
Description:
Q Cycle Activity:
Decode
00
RETURN
;W = offset
;Begin table
;
RETLW kn
; End of table
Before Instruction
W
0x07
After Instruction
W
DS30430C-page 66
value of k8
PIC16F8X
RLF
RRF
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
Operation:
Status Affected:
Status Affected:
Encoding:
Description:
RLF
00
1101
f,d
dfff
ffff
Encoding:
Description:
00
Register f
Words:
Cycles:
Cycles:
Example
Q1
Q2
Q3
Q4
Decode
Read
register
f
Process
data
Write to
destination
RLF
REG1,0
dfff
ffff
Register f
Q1
Q2
Q3
Q4
Decode
Read
register
f
Process
data
Write to
destination
RRF
REG1,0
Before Instruction
=
=
1110 0110
0
=
=
=
1110 0110
1100 1100
1
After Instruction
REG1
W
C
Q Cycle Activity:
Example
Before Instruction
REG1
C
1100
Words:
Q Cycle Activity:
RRF f,d
REG1
C
=
=
1110 0110
0
=
=
=
1110 0110
0111 0011
0
After Instruction
REG1
W
C
DS30430C-page 67
PIC16F8X
SLEEP
SUBLW
Syntax:
[ label ]
SUBLW k
Syntax:
[ label ]
Operands:
None
Operands:
0 k 255
Operation:
00h WDT,
0 WDT prescaler,
1 TO,
0 PD
Operation:
k - (W) (W)
Status Affected:
C, DC, Z
SLEEP
Encoding:
11
110x
kkkk
kkkk
Description:
The W register is subtracted (2s complement method) from the eight bit literal 'k'.
The result is placed in the W register.
Words:
Cycles:
Words:
Example 1:
Cycles:
Status Affected:
TO, PD
Encoding:
Description:
Q Cycle Activity:
00
0000
0110
0011
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal k
Process
data
Write to W
SUBLW
0x02
Before Instruction
Q1
Decode
Q2
Q3
No-Opera No-Opera
tion
tion
Q4
W
C
Z
Go to
Sleep
=
=
=
1
?
?
After Instruction
Example:
SLEEP
W
C
Z
Example 2:
=
=
=
1
1; result is positive
0
Before Instruction
W
C
Z
=
=
=
2
?
?
After Instruction
W
C
Z
Example 3:
=
=
=
0
1; result is zero
1
Before Instruction
W
C
Z
=
=
=
3
?
?
After Instruction
W
C
Z
DS30430C-page 68
=
=
=
0xFF
0; result is negative
0
PIC16F8X
SUBWF
Subtract W from f
SWAPF
Swap Nibbles in f
Syntax:
[ label ]
Syntax:
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
Operation:
(f<3:0>) (destination<7:4>),
(f<7:4>) (destination<3:0>)
Status Affected:
None
SUBWF f,d
00
Cycles:
Example 1:
dfff
ffff
Subtract (2s complement method) W register from register 'f'. If 'd' is 0 the result is
stored in the W register. If 'd' is 1 the
result is stored back in register 'f'.
Words:
Q Cycle Activity:
0010
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
data
Write to
destination
SUBWF
00
Example 2:
=
=
=
=
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
data
Write to
destination
SWAPF REG,
=
=
=
=
=
=
=
=
Example 3:
=
=
=
=
REG1
=
=
=
=
REG1
W
=
=
=
=
0xA5
=
=
0xA5
0x5A
1
2
1; result is positive
0
2
2
?
?
TRIS
Syntax:
[label]
Operands:
5f7
Operation:
TRIS
1
2
?
?
After Instruction
REG1
W
C
Z
After Instruction
Encoding:
0xFF
2
0; result is negative
0
00
0000
0110
0fff
Description:
Words:
Cycles:
Before Instruction
REG1
W
C
Z
Before Instruction
3
2
?
?
After Instruction
REG1
W
C
Z
ffff
Example
Before Instruction
REG1
W
C
Z
dfff
Description:
After Instruction
REG1
W
C
Z
1110
REG1,1
Before Instruction
REG1
W
C
Z
Encoding:
Example
To maintain upward compatibility
with future PIC16CXX products,
do not use this instruction.
DS30430C-page 69
PIC16F8X
XORLW
XORWF
Exclusive OR W with f
Syntax:
[label]
Syntax:
[label]
Operands:
0 k 255
Operands:
Operation:
0 f 127
d [0,1]
Status Affected:
Operation:
Status Affected:
Encoding:
11
XORLW k
1010
kkkk
kkkk
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
Q1
Q2
Q3
Q4
Decode
Read
literal k
Process
data
Write to
W
XORLW
Encoding:
00
XORWF
0110
f,d
dfff
ffff
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register
f
Process
data
Write to
destination
0xAF
Before Instruction
W
Example
0xB5
After Instruction
W
0x1A
XORWF
REG
Before Instruction
REG
W
=
=
0xAF
0xB5
=
=
0x1A
0xB5
After Instruction
REG
W
DS30430C-page 70
PIC16F8X
10.0
DEVELOPMENT SUPPORT
10.1
Development Tools
10.2
10.3
10.4
The PRO MATE II Universal Programmer is a full-featured programmer capable of operating in stand-alone
mode as well as PC-hosted mode. PRO MATE II is CE
compliant.
The PRO MATE II has programmable VDD and VPP
supplies which allows it to verify programmed memory
at VDD min and VDD max for maximum reliability. It has
an LCD display for displaying error messages, keys to
enter commands and a modular detachable socket
assembly to support various package types. In standalone mode the PRO MATE II can read, verify or program
PIC12CXXX,
PIC14C000,
PIC16C5X,
PIC16CXXX and PIC17CXX devices. It can also set
configuration and code-protect bits in this mode.
10.5
DS30430C-page 71
PIC16F8X
10.6
10.7
10.8
DS30430C-page 72
an RS-232 interface, push-button switches, a potentiometer for simulated analog input, a thermistor and
separate headers for connection to an external LCD
module and a keypad. Also provided on the PICDEM-3
board is an LCD panel, with 4 commons and 12 segments, that is capable of displaying time, temperature
and day of the week. The PICDEM-3 provides an additional RS-232 interface and Windows 3.1 software for
showing the demultiplexed LCD signals on a PC. A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals.
10.9
10.10
Assembler (MPASM)
PIC16F8X
MPASM has the following features to assist in developing software for specific use applications.
Provides translation of Assembler source code to
object code for all Microchip microcontrollers.
Macro assembly capability.
Produces all the files (Object, Listing, Symbol,
and special) required for symbolic debug with
Microchips emulator systems.
Supports Hex (default), Decimal and Octal source
and listing formats.
MPASM provides a rich directive language to support
programming of the PICmicro. Directives are helpful in
making the development of your assemble source code
shorter and more maintainable.
10.11
10.12
C Compiler (MPLAB-C17)
10.14
MP-DriveWay is an easy-to-use Windows-based Application Code Generator. With MP-DriveWay you can
visually configure all the peripherals in a PICmicro
device and, with a click of the mouse, generate all the
initialization and many functional code modules in C
language. The output is fully compatible with Microchips MPLAB-C C compiler. The code produced is
highly modular and allows easy integration of your own
code. MP-DriveWay is intelligent enough to maintain
your code through subsequent code generation.
10.15
10.16
10.13
fuzzyTECH-MP fuzzy logic development tool is available in two versions - a low cost introductory version,
MP Explorer, for designers to gain a comprehensive
working knowledge of fuzzy logic system design; and a
full-featured version, fuzzyTECH-MP, Edition for implementing more complex systems.
Both versions include Microchips fuzzyLAB demonstration board for hands-on experience with fuzzy logic
systems implementation.
DS30430C-page 73
Emulator Products
Software Tools
PIC16CXXX
MPLAB C17
Compiler
fuzzyTECH-MP
Explorer/Edition
Fuzzy Logic
Dev. Tool
MP-DriveWay
Applications
Code Generator
PIC17C75X
Programmers
Total Endurance
Software Model
PICSTARTPlus
Low-Cost
Universal Dev. Kit
PRO MATE II
Universal
Programmer
KEELOQ
Programmer
Demo Boards
PICDEM-2
PICDEM-3
KEELOQ
Evaluation Kit
HCS200
HCS300
HCS301
SEEVAL
Designers Kit
PICDEM-1
24CXX
25CXX
93CXX
PIC16F8X
MPLAB
Integrated
Development
Environment
PIC16C5X
ICEPIC Low-Cost
In-Circuit Emulator
PIC14000
TABLE 10-1:
DS30430C-page 74
PICMASTER/
PICMASTER-CE
In-Circuit Emulator
PIC12C5XX
PIC16F83/84
11.0
PIC16F8X
DS30430C-page 75
PIC16F8X
TABLE 11-1
PIC16F83/84
OSC
PIC16F84-10
PIC16F83-10
PIC16LF84-04
PIC16LF83-04
RC
VDD:
IDD:
IPD:
Freq:
4.0V to 6.0V
4.5 mA max. at 5.5V
14 A max. at 4V WDT dis
4.0 MHz max.
VDD:
IDD:
IPD:
Freq:
4.5V to 5.5V
1.8 mA typ. at 5.5V
1.0 A typ. at 5.5V WDT dis
4..0 MHz max.
VDD:
IDD:
IPD:
Freq:
2.0V to 6.0V
4.5 mA max. at 5.5V
7.0 A max. at 2V WDT dis
2.0 MHz max.
XT
VDD:
IDD:
IPD:
Freq:
4.0V to 6.0V
4.5 mA max. at 5.5V
14 A max. at 4V WDT dis
4.0 MHz max.
VDD:
IDD:
IPD:
Freq:
4.5V to 5.5V
1.8 mA typ. at 5.5V
1.0 A typ. at 5.5V WDT dis
4.0 MHz max.
VDD:
IDD:
IPD:
Freq:
2.0V to 6.0V
4.5 mA max. at 5.5V
7.0 A max. at 2V WDT dis
2.0 MHz max.
HS
VDD:
4.5V to 5.5V
VDD:
4.5V to 5.5V
IDD:
IDD:
IPD:
IPD:
VDD:
IDD:
IPD:
Freq:
4.0V to 6.0V
48 A typ. at 32 kHz, 2.0V
0.6 A typ. at 3.0V WDT dis
200 kHz max.
VDD:
IDD:
IPD:
Freq:
2.0V to 6.0V
45 A max. at 32 kHz, 2.0V
7 A max. at 2.0V WDT dis
200 kHz max.
The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user select the device type that ensures the specifications required.
DS30430C-page 76
PIC16F83/84
11.1
DC CHARACTERISTICS:
DC Characteristics
Power Supply Pins
Parameter
No.
Sym
Characteristic
D001
D001A
D002
VDD
Supply Voltage
VDR
D003
VPOR
D004
SVDD
IDD
D010
D010A
PIC16F8X
6.0
5.5
V
V
V
VSS
0.05*
1.8
7.3
4.5
10
mA
mA
5
10
mA
D013
D020
IPD
Power-down Current(3)
7.0
28
A
D021
1.0
14
A
D021A
1.0
16
A
* These parameters are characterized but not tested.
Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1=external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, T0CKI = VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula IR = VDD/2Rext (mA) with Rext in kOhm.
DS30430C-page 77
PIC16F8X
11.2
DC CHARACTERISTICS:
PIC16F83/84
PIC16LF84, PIC16LF83 (Commercial, Industrial)
DC Characteristics
Power Supply Pins
Parameter
No.
Sym
D001
D002
VDD
VDR
D003
VPOR
D004
SVDD
IDD
Characteristic
Supply Voltage
RAM Data Retention
Voltage(1)
VDD start voltage to
ensure internal
Power-on Reset signal
VDD rise rate to ensure
internal Power-on
Reset signal
Supply Current(2)
6.0
V
V
VSS
0.05*
D010
D010A
1
7.3
4
10
mA
mA
D014
15
45
Power-down Current(3)
3.0
16
A
D020
IPD
0.4
7.0
A
D021
0.4
9.0
A
D021A
* These parameters are characterized but not tested.
Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1=external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, T0CKI = VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be
estimated by the formula IR = VDD/2Rext (mA) with Rext in kOhm.
DS30430C-page 78
PIC16F8X
PIC16F83/84
11.3
DC CHARACTERISTICS:
DC Characteristics
All Pins Except
Power Supply Pins
Parameter
No.
Sym
VIL
D030
D030A
D031
D032
D033
D034
VIH
D040
D040A
D041
D042
D043
D050
VHYS
D070
IPURB
D060
IIL
Characteristic
Input Low Voltage
I/O ports
with TTL buffer
with Schmitt Trigger buffer
MCLR, RA4/T0CKI
OSC1 (XT, HS and LP modes)(1)
OSC1 (RC mode)
Input High Voltage
I/O ports
with TTL buffer
Typ
Max
Units
VSS
VSS
VSS
Vss
Vss
Vss
0.8
0.16VDD
0.2VDD
0.2VDD
0.3VDD
0.1VDD
V
V
V
V
V
V
VDD
VDD
VDD
VDD
V
V
VDD
V
V
400*
5
5
A
A
Conditions
2.4
0.48VDD
Hysteresis of
TBD
Schmitt Trigger inputs
PORTB weak pull-up current
50*
250*
Input Leakage Current(2,3)
I/O ports
MCLR, RA4/T0CKI
OSC1
D061
D063
Min
I/O ports
0.6
V
IOL = 8.5 mA, VDD = 4.5V
OSC2/CLKOUT
0.6
V
IOL = 1.6 mA, VDD = 4.5V
Output High Voltage
D090
VOH
I/O ports(3)
VDD-0.7
V
IOH = -3.0 mA, VDD = 4.5V
D092
OSC2/CLKOUT
VDD-0.7
V
IOH = -1.3 mA, VDD = 4.5V
*
These parameters are characterized but not tested.
Data in Typ column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator configuration, the OSC1 pin is a Schmitt Trigger input. Do not drive the PIC16F8X with an
external clock while the device is in RC mode, or chip damage may result.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
4: The user may choose the better of the two specs.
D080
D083
VOL
DS30430C-page 79
PIC16F8X
11.4
PIC16F83/84
DC CHARACTERISTICS:
DC Characteristics
All Pins Except
Power Supply Pins
Sym
Characteristic
D100
COSC2
D101
CIO
Parameter
No.
D120
D121
ED
VDRW
D122
TDEW
D130
D131
EP
VPR
15
pF
50
pF
1M
VMIN
10M
6.0
E/W
V
10
20*
ms
100
VMIN
1000
6.0
E/W
V
25C at 5V
VMIN = Minimum operating
voltage
D132
VPEW VDD for erase/write
4.5
5.5
V
D133
TPEW Erase/Write cycle time
10
ms
*
These parameters are characterized but not tested.
Data in Typ column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only
and are not tested.
DS30430C-page 80
PIC16F8X
PIC16F83/84
TABLE 11-2
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase symbols (pp) and their meanings:
pp
2
to
ck
CLKOUT
cy
cycle time
io
I/O port
inp
INT pin
mc
MCLR
Uppercase symbols and their meanings:
S
F
Fall
H
High
I
Invalid (Hi-impedance)
L
Low
Time
os,osc
ost
pwrt
rbt
t0
wdt
OSC1
oscillator start-up timer
power-up timer
RBx pins
T0CKI
watchdog timer
P
R
V
Z
Period
Rise
Valid
High Impedance
Load Condition 2
VDD/2
RL
CL
Pin
CL
Pin
VSS
VSS
RL =
464
CL =
50 pF
15 pF
DS30430C-page 81
PIC16F8X
11.5
PIC16F83/84
Q1
Q3
Q2
Q4
Q1
OSC1
1
2
CLKOUT
TABLE 11-3
Parameter
No.
Tosc
Characteristic
Min
Typ
Max
Units
DC
DC
DC
DC
2
4
10
200
MHz
MHz
MHz
kHz
XT, RC osc
XT, RC osc
HS osc
LP osc
PIC16LF8X-04
PIC16F8X-04
PIC16F8X-10
PIC16LF8X-04
Oscillator Frequency(1)
DC
DC
0.1
0.1
1.0
DC
2
4
2
4
10
200
MHz
MHz
MHz
MHz
MHz
kHz
RC osc
RC osc
XT osc
XT osc
HS osc
LP osc
PIC16LF8X-04
PIC16F8X-04
PIC16LF8X-04
PIC16F8X-04
PIC16F8X-10
PIC16LF8X-04
500
250
100
5.0
ns
ns
ns
s
XT, RC osc
XT, RC osc
HS osc
LP osc
PIC16LF8X-04
PIC16F8X-04
PIC16F8X-10
PIC16LF8X-04
Oscillator Period(1)
500
250
500
250
100
5.0
10,000
10,000
1,000
ns
ns
ns
ns
ns
s
RC osc
RC osc
XT osc
XT osc
HS osc
LP osc
PIC16LF8X-04
PIC16F8X-04
PIC16LF8X-04
PIC16F8X-04
PIC16F8X-10
PIC16LF8X-04
0.4
60 *
50 *
2.0 *
35 *
25 *
50 *
15 *
4/Fosc
DC
s
ns
ns
s
ns
ns
ns
ns
XT osc
XT osc
LP osc
HS osc
XT osc
LP osc
HS osc
PIC16LF8X-04
PIC16F8X-04
PIC16LF8X-04
PIC16F8X-10
PIC16F8X-04
PIC16LF8X-04
PIC16F8X-10
2
3
TCY
TosL,
TosH
TosR,
TosF
Conditions
DS30430C-page 82
PIC16F8X
PIC16F83/84
FIGURE 11-4: CLKOUT AND I/O TIMING
Q1
Q4
Q2
Q3
OSC1
11
10
22
23
CLKOUT
13
19
14
12
18
16
I/O Pin
(input)
15
17
I/O Pin
(output)
new value
old value
20, 21
Note: All tests must be done with specified capacitive loads (Figure 11-2) 50 pF on I/O pins and CLKOUT.
TABLE 11-4
Parameter
No.
10
Characteristic
TosH2ckL
OSC1 to CLKOUT
TosH2ckH
OSC1 to CLKOUT
TckR
10A
11
11A
12
12A
13
Min
Typ
Max
PIC16F8X
15
30 *
ns
Note 1
PIC16LF8X
15
120 *
ns
Note 1
PIC16F8X
15
30 *
ns
Note 1
PIC16LF8X
15
120 *
ns
Note 1
PIC16F8X
15
30 *
ns
Note 1
PIC16LF8X
15
100 *
ns
Note 1
PIC16F8X
15
30 *
ns
Note 1
TckF
14
TckL2ioV
15
TioV2ckH
13A
PIC16LF8X
Units Conditions
15
100 *
ns
Note 1
0.5TCY +20 *
ns
Note 1
PIC16F8X
0.30TCY + 30 *
ns
Note 1
CLKOUT
PIC16LF8X
0.30TCY + 80 *
ns
Note 1
Note 1
16
TckH2ioI
0*
ns
17
TosH2ioV
PIC16F8X
125 *
ns
PIC16LF8X
250 *
ns
18
TosH2ioI
PIC16F8X
10 *
ns
PIC16LF8X
10 *
ns
PIC16F8X
-75 *
ns
PIC16LF8X
-175 *
ns
PIC16F8X
10
35 *
ns
PIC16LF8X
10
70 *
ns
10
35 *
ns
19
20
TioV2osH
TioR
20A
21
TioF
PIC16F8X
PIC16LF8X
10
70 *
ns
Tinp
PIC16F8X
20 *
ns
or low time
PIC16LF8X
55 *
ns
PIC16F8X
TOSC
ns
PIC16LF8X
TOSC
ns
21A
22
22A
23
23A
Trbp
DS30430C-page 83
PIC16F8X
PIC16F83/84
FIGURE 11-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O Pins
TABLE 11-5
Parameter
No.
Sym
30
TmcL
31
Twdt
32
Tost
33
Tpwrt
34
TIOZ
Characteristic
Min
Max
Units
Conditions
1000 *
ns
7*
18
33 *
ms
VDD = 5.0V
ms
28 *
72
132 *
ms
VDD = 5.0V
100 *
ns
Typ
1024TOSC
DS30430C-page 84
PIC16F8X
PIC16F83/84
FIGURE 11-6: TIMER0 CLOCK TIMINGS
RA4/T0CKI
40
41
42
TABLE 11-6
Parameter
No.
40
Characteristic
No Prescaler
With Prescaler
41
No Prescaler
With Prescaler
42
*
Min
0.5TCY + 20 *
ns
50 *
30 *
ns
ns
Conditions
0.5TCY + 20 *
ns
50 *
20 *
ns
ns
TCY + 40 *
N
ns
N = prescale value
(2, 4, ..., 256)
DS30430C-page 85
PIC16F8X
PIC16F83/84
NOTES:
DS30430C-page 86
PIC16CR83/84
12.0
PIC16F8X
DS30430C-page 87
PIC16F8X
TABLE 12-1
PIC16CR83/84
OSC
PIC16CR84-10
PIC16CR83-10
PIC16LCR84-04
PIC16LCR83-04
RC
VDD:
IDD:
IPD:
Freq:
4.0V to 6.0V
4.5 mA max. at 5.5V
14 A max. at 4V WDT dis
4.0 MHz max.
VDD:
IDD:
IPD:
Freq:
4.5V to 5.5V
1.8 mA typ. at 5.5V
1.0 A typ. at 5.5V WDT dis
4..0 MHz max.
VDD:
IDD:
IPD:
Freq:
2.0V to 6.0V
4.5 mA max. at 5.5V
5 A max. at 2V WDT dis
2.0 MHz max.
XT
VDD:
IDD:
IPD:
Freq:
4.0V to 6.0V
4.5 mA max. at 5.5V
14 A max. at 4V WDT dis
4.0 MHz max.
VDD:
IDD:
IPD:
Freq:
4.5V to 5.5V
1.8 mA typ. at 5.5V
1.0 A typ. at 5.5V WDT dis
4.0 MHz max.
VDD:
IDD:
IPD:
Freq:
2.0V to 6.0V
4.5 mA max. at 5.5V
5 A max. at 2V WDT dis
2.0 MHz max.
HS
IDD:
IPD:
IPD:
LP
VDD:
IDD:
IPD:
Freq:
4.0V to 6.0V
48 A typ. at 32 kHz, 2.0V
0.6 A typ. at 3.0V WDT dis
200 kHz max.
VDD:
IDD:
IPD:
Freq:
2.0V to 6.0V
45 A max. at 32 kHz, 2.0V
5 A max. at 2V WDT dis
200 kHz max.
The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user select the device type that ensures the specifications required.
DS30430C-page 88
PIC16CR83/84
12.1
DC CHARACTERISTICS:
DC Characteristics
Power Supply Pins
Parameter
No.
Sym
Characteristic
D001
D001A
D002
VDD
Supply Voltage
VDR
D003
VPOR
D004
SVDD
IDD
D010
D010A
PIC16F8X
6.0
5.5
0.05*
V
V
V
VSS
1.8
7.3
4.5
10
mA
mA
5
10
mA
D013
(3)
D020
IPD
Power-down Current
7.0
28
A
D021
1.0
14
A
D021A
1.0
16
A
* These parameters are characterized but not tested.
Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1=external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, T0CKI = VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula IR = VDD/2Rext (mA) with Rext in kOhm.
DS30430C-page 89
PIC16F8X
12.2
PIC16CR83/84
DC CHARACTERISTICS:
DC Characteristics
Power Supply Pins
Parameter
No.
Sym
D001
D002
VDD
VDR
D003
VPOR
D004
SVDD
IDD
Characteristic
Supply Voltage
RAM Data Retention
Voltage(1)
VDD start voltage to
ensure internal
Power-on Reset signal
VDD rise rate to ensure
internal Power-on
Reset signal
Supply Current(2)
6.0
V
V
VSS
0.05*
D010
D010A
1
7.3
4
10
mA
mA
D014
15
45
Power-down Current(3)
3.0
16
A
D020
IPD
0.4
5.0
A
D021
0.4
6.0
A
D021A
* These parameters are characterized but not tested.
Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1=external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, T0CKI = VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be
estimated by the formula IR = VDD/2Rext (mA) with Rext in kOhm.
DS30430C-page 90
PIC16F8X
PIC16CR83/84
12.3
DC CHARACTERISTICS:
DC Characteristics
All Pins Except
Power Supply Pins
Parameter
No.
Sym
Characteristic
Min
Typ
Max
Units Conditions
VSS
0.8
VSS
0.16VDD
entire range(4)
VSS
entire range
I/O ports
with TTL buffer
D030A
D031
0.2VDD
D032
MCLR, RA4/T0CKI
Vss
0.2VDD
D033
Vss
0.3VDD
D034
Vss
0.1VDD
V
V
I/O ports
2.4
0.48VDD
VDD
VDD
0.45VDD
VDD
0.85
VDD
VDD
D042
D043
VDD
D050
VHYS
Hysteresis of
Schmitt Trigger inputs
TBD
D070
IPURB
50*
250*
400*
I/O ports
D061
MCLR, RA4/T0CKI
D063
OSC1
I/O ports
0.6
OSC2/CLKOUT
0.6
I/O ports(3)
VDD-0.7
OSC2/CLKOUT
VDD-0.7
IIL
VOL
D083
VOH
DS30430C-page 91
PIC16F8X
12.4
PIC16CR83/84
DC CHARACTERISTICS:
DC Characteristics
All Pins Except
Power Supply Pins
Sym
Characteristic
D100
COSC2
D101
CIO
D120
D121
ED
VDRW
Parameter
No.
15
pF
50
pF
1M
VMIN
10M
6.0
E/W
V
25C at 5V
VMIN = Minimum operating
voltage
10
20*
ms
D122
TDEW Erase/Write cycle time
*
These parameters are characterized but not tested.
Data in Typ column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only
and are not tested.
DS30430C-page 92
PIC16F8X
PIC16CR83/84
TABLE 12-2
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase symbols (pp) and their meanings:
pp
2
to
ck
CLKOUT
cy
cycle time
io
I/O port
inp
INT pin
mc
MCLR
Uppercase symbols and their meanings:
S
F
Fall
H
High
I
Invalid (Hi-impedance)
L
Low
Time
os,osc
ost
pwrt
rbt
t0
wdt
OSC1
oscillator start-up timer
power-up timer
RBx pins
T0CKI
watchdog timer
P
R
V
Z
Period
Rise
Valid
High Impedance
Load Condition 2
VDD/2
RL
CL
Pin
CL
Pin
VSS
VSS
RL =
464
CL =
50 pF
15 pF
DS30430C-page 93
PIC16F8X
12.5
PIC16CR83/84
Q1
Q3
Q2
Q4
Q1
OSC1
1
2
CLKOUT
TABLE 12-3
Parameter
No.
Characteristic
External CLKIN Frequency(1)
Oscillator Frequency
Tosc
(1)
Oscillator Period
(1)
TCY
TosL,
TosH
TosR,
TosF
Min
Typ
Max
Units
Conditions
DC
MHz
XT, RC osc
PIC16LCR8X-04
DC
MHz
XT, RC osc
PIC16CR8X-04
DC
10
MHz
HS osc
PIC16CR8X-10
DC
200
kHz
LP osc
PIC16LCR8X-04
DC
MHz
RC osc
PIC16LCR8X-04
DC
MHz
RC osc
PIC16CR8X-04
0.1
MHz
XT osc
PIC16LCR8X-04
0.1
MHz
XT osc
PIC16CR8X-04
1.0
10
MHz
HS osc
PIC16CR8X-10
DC
200
kHz
LP osc
PIC16LCR8X-04
500
ns
XT, RC osc
PIC16LCR8X-04
250
ns
XT, RC osc
PIC16CR8X-04
100
ns
HS osc
PIC16CR8X-10
5.0
LP osc
PIC16LCR8X-04
500
ns
RC osc
PIC16LCR8X-04
250
ns
RC osc
PIC16CR8X-04
500
10,000
ns
XT osc
PIC16LCR8X-04
250
10,000
ns
XT osc
PIC16CR8X-04
100
1,000
ns
HS osc
PIC16CR8X-10
5.0
LP osc
PIC16LCR8X-04
0.4
4/Fosc
DC
60 *
ns
XT osc
PIC16LCR8X-04
50 *
ns
XT osc
PIC16CR8X-04
2.0 *
LP osc
PIC16LCR8X-04
35 *
ns
HS osc
PIC16CR8X-10
PIC16CR8X-04
25 *
ns
XT osc
50 *
ns
LP osc
PIC16LCR8X-04
15 *
ns
HS osc
PIC16CR8X-10
DS30430C-page 94
PIC16F8X
PIC16CR83/84
FIGURE 12-4: CLKOUT AND I/O TIMING
Q1
Q4
Q2
Q3
OSC1
11
10
22
23
CLKOUT
13
19
14
12
18
16
I/O Pin
(input)
15
17
I/O Pin
(output)
new value
old value
20, 21
Note: All tests must be done with specified capacitive loads (Figure 12-2) 50 pF on I/O pins and CLKOUT.
TABLE 12-4
Parameter
No.
10
Characteristic
TosH2ckL
OSC1 to CLKOUT
TosH2ckH
OSC1 to CLKOUT
TckR
10A
11
11A
12
12A
13
PIC16CR8X
Typ
Max
15
30 *
Units Conditions
ns
15
120 *
ns
Note 1
PIC16CR8X
15
30 *
ns
Note 1
PIC16LCR8X
15
120 *
ns
Note 1
PIC16CR8X
15
30 *
ns
Note 1
PIC16LCR8X
15
100 *
ns
Note 1
PIC16CR8X
15
30 *
ns
Note 1
PIC16LCR8X
15
100 *
ns
Note 1
0.5TCY +20 *
ns
Note 1
14
TckL2ioV
15
TioV2ckH
PIC16CR8X
0.30TCY + 30 *
ns
Note 1
CLKOUT
PIC16LCR8X
0.30TCY + 80 *
ns
Note 1
Note 1
16
TckH2ioI
0*
ns
17
TosH2ioV
PIC16CR8X
125 *
ns
PIC16LCR8X
250 *
ns
18
TosH2ioI
PIC16CR8X
10 *
ns
PIC16LCR8X
10 *
ns
PIC16CR8X
-75 *
ns
PIC16LCR8X
-175 *
ns
19
20
TioV2osH
TioR
20A
21
23A
10
35 *
ns
10
70 *
ns
10
35 *
ns
PIC16CR8X
PIC16LCR8X
10
70 *
ns
Tinp
PIC16CR8X
20 *
ns
or low time
PIC16LCR8X
55 *
ns
Trbp
PIC16CR8X
TOSC
ns
PIC16LCR8X
TOSC
ns
22A
23
PIC16CR8X
PIC16LCR8X
TioF
21A
22
Note 1
PIC16LCR8X
TckF
13A
Min
DS30430C-page 95
PIC16F8X
PIC16CR83/84
FIGURE 12-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O Pins
TABLE 12-5
Parameter
No.
Characteristic
30
TmcL
31
Twdt
32
Tost
33
Tpwrt
34
TIOZ
Min
Typ
Max
Units
Conditions
1000 *
ns
7*
18
33 *
ms
VDD = 5.0V
ms
28 *
72
132 *
ms
VDD = 5.0V
100 *
ns
1024TOSC
DS30430C-page 96
PIC16F8X
PIC16CR83/84
FIGURE 12-6: TIMER0 CLOCK TIMINGS
RA4/T0CKI
40
41
42
TABLE 12-6
Parameter
No.
40
Tt0H
Characteristic
T0CKI High Pulse Width
Min
No Prescaler
With Prescaler
41
Tt0L
No Prescaler
With Prescaler
42
*
Tt0P
T0CKI Period
0.5TCY + 20 *
ns
50 *
30 *
ns
ns
Conditions
0.5TCY + 20 *
ns
50 *
20 *
ns
ns
TCY + 40 *
N
ns
N = prescale value
(2, 4, ..., 256)
DS30430C-page 97
PIC16F8X
PIC16CR83/84
NOTES:
DS30430C-page 98
PIC16F8X
13.0
The graphs and tables provided in this section are for design guidance and are not tested or guaranteed.
In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD
range). This is for information only and devices are guaranteed to operate properly only within the specified range.
The data presented in this section is a statistical summary of data collected on units from different lots over a period
of time and matrix samples. Typical represents the mean of the distribution at 25C, while max or min represents
(mean + 3) and (mean - 3) respectively, where is standard deviation.
1.20
Rext = 10 k
Cext = 100 pF
1.16
1.12
1.08
1.04
1.00
VDD = 5.5 V
0.96
0.92
VDD = 3.5 V
0.88
0.84
-40
-20
20 25
40
60
70
80 85
100
T(C)
TABLE 13-1
RC OSCILLATOR FREQUENCIES*
Cext
Rext
Average
Fosc @ 5V, 25C
Part to Part Variation
5k
4.61 MHz
25%
10 k
2.66 MHz
24%
100 k
311 kHz
39%
100 pF
5k
1.34 MHz
21%
10 k
756 kHz
18%
100 k
82.8 kHz
28%
300 pF
5k
428 kHz
13%
10 k
243 kHz
13%
100 k
26.2 kHz
23%
* Measured on DIP packages. The percentage variation indicated here is part-to-part variation due to normal process
distribution. The variation indicated is 3 standard deviation from average value for full VDD range.
20 pF
DS30430C-page 99
PIC16F8X
FIGURE 13-2: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 20 PF
Measured on DIP Packages, T = 25C
5.5
5.0
R = 5k
4.5
4.0
Fosc (MHz)
3.5
R = 10k
3.0
2.5
2.0
1.5
1.0
R = 100k
0.5
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
DS30430C-page 100
PIC16F8X
FIGURE 13-3: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 100 PF
Measured on DIP Packages, T = 25C
1.8
R = 5k
1.6
1.4
Fosc (MHz)
1.2
1.0
R = 10k
0.8
0.6
0.4
0.2
R = 100k
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
0.6
R = 5k
FOSC (MHz)
0.5
0.4
R = 10k
0.3
0.2
0.1
R = 100k
0.0
2.0
2.5
3.0
5.0
5.5
6.0
DS30430C-page 101
PIC16F8X
FIGURE 13-5: TYPICAL IPD vs. VDD,
WATCHDOG DISABLED
6.0
10
9
5.0
8
T = 25C
T = 25C
7
6
IPD (A)
IPD (A)
4.0
3.0
5
4
3
2
2.0
1
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
1.0
VDD (Volts)
0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
FIGURE 13-7: VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS vs. VDD
1.40
VTH (Volts)
1.30
1.20
(
Typ
1.10
C
+25
1.00
0.90
0.80
0.70
2.0
2.5
3.0
3.5
4.0
VDD (Volts)
4.5
5.0
5.5
6.0
DS30430C-page 102
PIC16F8X
FIGURE 13-8: VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT
(IN XT, HS, AND LP MODES) vs. VDD
3.0
2.8
2.6
VTH (Volts)
2.4
2.2
2.0
(
Typ
1.8
C)
+25
1.6
1.4
1.2
1.0
0.8
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
5.5
6.0
VDD (Volts)
Note: This input pin is CMOS input.
FIGURE 13-9: VIH, VIL OF MCLR, T0CKI AND OSC1 (IN RC MODE) vs. VDD
5.0
4.5
4.0
3.5
3.0
V IH
ty p +
25C
2.5
2.0
1.5
1.0
0.5
0.0
2.0
2.5
3.0
3.5
4.0
VDD (Volts)
4.5
5.0
DS30430C-page 103
PIC16F8X
FIGURE 13-10: TYPICAL IDD vs. FREQUENCY (RC MODE @20PF, 25C)
TYPICAL IDD vs FREQ (RC MODE @20pF)
10000
1000
6.0V
5.5V
100
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
10
100000
1000000
10000000
FREQ (Hz)
DS30430C-page 104
PIC16F8X
FIGURE 13-11: TYPICAL IDD vs. FREQUENCY (RC MODE @100PF, 25C)
TYPICAL IDD vs FREQ (RC MODE @100 pF)
10000
1000
6.0V
5.5V
100
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
10
10000
100000
1000000
10000000
FREQ (Hz)
DS30430C-page 105
PIC16F8X
FIGURE 13-12: TYPICAL IDD vs. FREQUENCY (RC MODE @300PF, 25C)
TYPICAL IDD vs FREQ (RC MODE @300pF)
1000
6.0V
5.5V
100
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
10
10000
100000
1000000
FREQ (Hz)
DS30430C-page 106
PIC16F8X
FIGURE 13-14: TRANSCONDUCTANCE (gm)
OF HS OSCILLATOR vs. VDD
50
9000
45
8000
40
7000
35
6000
30
5000
gm (A/V)
Typ +25C
25
Typ +25C
4000
20
3000
15
2000
10
100
5
2.0
3.0
4.0
VDD (Volts)
5.0
6.0
0
2.0
3.0
4.0
5.0
VDD (Volts)
6.0
DS30430C-page 107
PIC16F8X
FIGURE 13-15: TRANSCONDUCTANCE (gm)
OF LP OSCILLATOR vs. VDD
45
40
2000
35
30
25
gm (A/V)
gm (A/V)
1500
20
Typ +25C
Typ +25C
1000
15
500
10
5
0
2.0
0
2.0
3.0
4.0
5.0
6.0
3.0
4.0
5.0
6.0
VDD (Volts)
VDD (Volts)
DS30430C-page 108
PIC16F8X
FIGURE 13-19: IOL vs. VOL, VDD = 3 V
45
40
5
35
30
10
IOL (mA)
IOH (mA)
Typ +25C
15
25
Typ +25C
20
15
20
10
5
25
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.0
VOH (Volts)
0.5
1.0
1.5
2.0
2.5
3.0
VOL (Volts)
0
80
70
10
60
20
Typ +25C
IOL (mA)
IOH (mA)
15
Typ +25C
50
40
25
30
30
20
35
10
40
1.5
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VOL (Volts)
DS30430C-page 109
PIC16F8X
FIGURE 13-21: TYPICAL DATA MEMORY ERASE/WRITE CYCLE TIME VS. VDD
10
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
VDD (Volts)
Shaded area is beyond recommended range.
TABLE 13-2
INPUT CAPACITANCE*
Typical Capacitance (pF)
Pin Name
18L PDIP
18L SOIC
PORTA
5.0
4.3
PORTB
5.0
4.3
MCLR
17.0
17.0
OSC1/CLKIN
4.0
3.5
OSC2/CLKOUT
4.3
3.5
T0CKI
3.2
2.8
* All capacitance values are typical at 25C. A part to part variation of 25% (three standard deviations) should
be taken into account.
DS30430C-page 110
PIC16F8X
14.0
PACKAGING INFORMATION
14.1
Example
18L PDIP
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
AABBCDE
18L SOIC
PIC16F84-04I/P
9632SAW
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
XXXXXXXXXXXX
AABBCDE
Legend: XX...X
AA
BB
C
D
E
PIC16F84-04
/SO
9648SAN
Note:
In the event the full Microchip part number cannot be marked on one line,
it will be carried over to the next line, thus limiting the number of available
characters for customer specific information.
Standard OTP marking consists of Microchip part number, year code, week
code, facility code, mask rev# and assembly code. For OTP marking beyond
this, certain price adders apply. Please check with your Microchip Sales Office.
For QTP devices, any special marking adders are included in QTP price.
DS30430C-page 111
PIC16F8X
Package Type:
2
n
1
E1
A1
A
R
c
A2
B1
B
eB
Units
Dimension Limits
PCB Row Spacing
Number of Pins
Pitch
Lower Lead Width
Upper Lead Width
Shoulder Radius
Lead Thickness
Top to Seating Plane
Top of Lead to Seating Plane
Base to Seating Plane
Tip to Seating Plane
Package Length
Molded Package Width
Radius to Radius Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
INCHES*
NOM
0.300
18
0.100
0.013
0.018
0.055
0.060
0.000
0.005
0.005
0.010
0.110
0.155
0.075
0.095
0.000
0.020
0.125
0.130
0.890
0.895
0.245
0.255
0.230
0.250
0.310
0.349
5
10
5
10
MIN
n
p
B
B1
R
c
A
A1
A2
L
D
E
E1
eB
MAX
0.023
0.065
0.010
0.015
0.155
0.115
0.020
0.135
0.900
0.265
0.270
0.387
15
15
MILLIMETERS
NOM
MAX
7.62
18
2.54
0.33
0.46
0.58
1.40
1.52
1.65
0.00
0.13
0.25
0.13
0.25
0.38
2.79
3.94
3.94
1.91
2.41
2.92
0.00
0.51
0.51
3.18
3.30
3.43
22.61
22.73
22.86
6.22
6.48
6.73
5.84
6.35
6.86
7.87
8.85
9.83
5
10
15
5
10
15
MIN
* Controlling Parameter.
Dimension B1 does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003
(0.076 mm) per side or 0.006 (0.152 mm) more than dimension B1.
Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010 (0.254 mm) per side or 0.020 (0.508 mm) more than dimensions D or E.
DS30430C-page 112
PIC16F8X
Package Type:
2
B
n
X
45
L
R2
c
A
R1
Units
Dimension Limits
Pitch
Number of Pins
Overall Pack. Height
Shoulder Height
Standoff
Molded Package Length
Molded Package Width
Outside Dimension
Chamfer Distance
Shoulder Radius
Gull Wing Radius
Foot Length
Foot Angle
Radius Centerline
Lead Thickness
Lower Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
L1
p
n
A
A1
A2
D
E
E1
X
R1
R2
L
L1
c
B
A2
INCHES*
NOM
0.050
18
0.093
0.099
0.048
0.058
0.004
0.008
0.450
0.456
0.292
0.296
0.394
0.407
0.010
0.020
0.005
0.005
0.005
0.005
0.011
0.016
0
4
0.010
0.015
0.009
0.011
0.014
0.017
0
12
0
12
MIN
A1
MAX
0.104
0.068
0.011
0.462
0.299
0.419
0.029
0.010
0.010
0.021
8
0.020
0.012
0.019
15
15
MILLIMETERS
NOM
MAX
1.27
18
2.36
2.64
2.50
1.22
1.73
1.47
0.10
0.28
0.19
11.43
11.73
11.58
7.42
7.59
7.51
10.01
10.64
10.33
0.74
0.25
0.50
0.13
0.25
0.13
0.13
0.13
0.25
0.28
0.53
0.41
0
4
8
0.25
0.38
0.51
0.23
0.27
0.30
0.36
0.48
0.42
0
12
15
0
12
15
MIN
Controlling Parameter.
Dimension B does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003
(0.076 mm) per side or 0.006 (0.152 mm) more than dimension B.
Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010 (0.254 mm) per side or 0.020 (0.508 mm) more than dimensions D or E.
DS30430C-page 113
PIC16F8X
NOTES:
DS30430C-page 114
PIC16F8X
APPENDIX A: FEATURE
IMPROVEMENTS FROM PIC16C5X TO
PIC16F8X
The following is the list of feature improvements over
the PIC16C5X microcontroller family:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
3.
4.
5.
DS30430C-page 115
PIC16F8X
APPENDIX C: WHATS NEW IN THIS
DATA SHEET
1.
1.
2.
2.
3.
4.
DS30430C-page 116
PIC16F8X
APPENDIX E: CONVERSION CONSIDERATIONS - PIC16C84 TO PIC16F83/F84 AND
PIC16CR83/CR84
Considerations for converting from the PIC16C84 to
the PIC16F84 are listed in the table below. These considerations apply to converting from the PIC16C84 to
the PIC16F83 (same as PIC16F84 except for program
Difference
PIC16C84
PIC16F84
PWRTE
PWRTE
RAM = 36 bytes
RAM = 68 bytes
N/A
RB0/INT pin
TTL
TTL/ST*
(* This buffer is a Schmitt Trigger
input when configured as the external interrupt.)
N/A
Code Protect
1 CP bit
9 CP bits
REXT = 3k - 100k
REXT = 5k - 100k
N/A
DS30430C-page 117
PIC16F8X
NOTES:
DS30430C-page 118
PIC16F8X
INDEX
Numerics
8.1 Configuration Bits ......................................................... 37
A
Absolute Maximum Ratings ......................................... 73, 85
ALU ...................................................................................... 7
Architectural Overview ......................................................... 7
Assembler
MPASM Assembler .................................................... 70
B
Block Diagram
Interrupt Logic ............................................................ 47
On-Chip Reset Circuit ................................................ 41
RA3:RA0 and RA5 Port Pins ..................................... 21
RA4 Pin ...................................................................... 21
RB7:RB4 Port Pins .................................................... 23
TMR0/WDT Prescaler ................................................ 30
Watchdog Timer ......................................................... 50
Brown-out Protection Circuit .............................................. 46
C
Carry .................................................................................... 7
CLKIN .................................................................................. 9
CLKOUT .............................................................................. 9
Code Protection ........................................................... 37, 52
Compatibility, upward ........................................................... 3
Computed GOTO ............................................................... 18
Configuration Bits ............................................................... 37
D
DC Characteristics ................... 75, 76, 77, 78, 87, 88, 89, 90
Development Support ........................................................ 69
Development Tools ............................................................ 69
Digit Carry ............................................................................ 7
CALL .......................................................................... 57
CLRF ......................................................................... 58
CLRW ........................................................................ 58
CLRWDT ................................................................... 58
COMF ........................................................................ 59
DECF ......................................................................... 59
DECFSZ .................................................................... 59
GOTO ........................................................................ 60
INCF .......................................................................... 60
INCFSZ ...................................................................... 61
IORLW ....................................................................... 61
IORWF ....................................................................... 62
MOVF ........................................................................ 62
MOVLW ..................................................................... 62
MOVWF ..................................................................... 62
NOP ........................................................................... 63
OPTION ..................................................................... 63
RETFIE ...................................................................... 63
RETLW ...................................................................... 64
RETURN .................................................................... 64
RLF ............................................................................ 65
RRF ........................................................................... 65
SLEEP ....................................................................... 66
SUBLW ...................................................................... 66
SUBWF ...................................................................... 67
SWAPF ...................................................................... 67
TRIS .......................................................................... 67
XORLW ..................................................................... 68
XORWF ..................................................................... 68
Section ....................................................................... 53
Summary Table ......................................................... 54
INT Interrupt ...................................................................... 48
INTCON ........................................................... 17, 42, 47, 48
INTEDG ............................................................................. 48
Interrupts
Flag ............................................................................ 47
Interrupt on Change Feature ..................................... 23
Interrupts ............................................................. 37, 47
Family of Devices
PIC16C8X .................................................................... 3
FSR .............................................................................. 19, 42
Fuzzy Logic Dev. System (fuzzyTECH-MP) ................... 71
Loading of PC .................................................................... 18
G
GIE ..................................................................................... 47
I
I/O Ports ............................................................................. 21
I/O Programming Considerations ....................................... 25
ICEPIC Low-Cost PIC16CXXX In-Circuit Emulator ........... 69
In-Circuit Serial Programming ...................................... 37, 52
INDF ................................................................................... 42
Instruction Format .............................................................. 53
Instruction Set
ADDLW ...................................................................... 55
ADDWF ...................................................................... 55
ANDLW ...................................................................... 55
ANDWF ...................................................................... 55
BCF ............................................................................ 56
BSF ............................................................................ 56
BTFSC ....................................................................... 56
BTFSS ....................................................................... 57
M
MCLR ...................................................................... 9, 41, 42
Memory Organization
Data Memory ............................................................. 12
Memory Organization ................................................ 11
Program Memory ....................................................... 11
MP-DriveWay - Application Code Generator ................. 71
MPLAB C ........................................................................... 71
MPLAB Integrated Development Environment Software ... 70
O
OPCODE ........................................................................... 53
OPTION ................................................................. 16, 42, 48
OSC selection .................................................................... 37
OSC1 ................................................................................... 9
OSC2 ................................................................................... 9
Oscillator
HS ........................................................................ 39, 46
LP ........................................................................ 39, 46
RC ....................................................................... 39, 40
XT .............................................................................. 39
Oscillator Configurations .................................................... 39
DS30430C-page 119
PIC16F8X
P
Paging, Program Memory .................................................. 18
PCL .............................................................................. 18, 42
PCLATH ....................................................................... 18, 42
PD .......................................................................... 15, 41, 46
PICDEM-1 Low-Cost PICmicro Demo Board ..................... 70
PICDEM-2 Low-Cost PIC16CXX Demo Board .................. 70
PICDEM-3 Low-Cost PIC16CXXX Demo Board ................ 70
PICMASTER In-Circuit Emulator ..................................... 69
PICSTART Plus Entry Level Development System ........ 69
Pinout Descriptions .............................................................. 9
POR ................................................................................... 43
Oscillator Start-up Timer (OST) ........................... 37, 43
Power-on Reset (POR) .................................. 37, 42, 43
Power-up Timer (PWRT) ..................................... 37, 43
Time-out Sequence .................................................... 46
Time-out Sequence on Power-up .............................. 44
TO .................................................................. 15, 41, 46
Port RB Interrupt ................................................................ 48
PORTA ..................................................................... 9, 21, 42
PORTB ..................................................................... 9, 23, 42
Power-down Mode (SLEEP) .............................................. 51
Prescaler ............................................................................ 29
PRO MATE II Universal Programmer .............................. 69
Product Identification System ........................................... 121
X
XT ...................................................................................... 46
Z
Zero bit ................................................................................. 7
R
RBIF bit ........................................................................ 23, 48
RC Oscillator ...................................................................... 46
Read-Modify-Write ............................................................. 25
Register File ....................................................................... 12
Reset ............................................................................ 37, 41
Reset on Brown-Out ........................................................... 46
S
Saving W Register and STATUS in RAM .......................... 49
SEEVAL Evaluation and Programming System .............. 71
SLEEP .................................................................... 37, 41, 51
Software Simulator (MPLAB-SIM) ...................................... 71
Special Features of the CPU .............................................. 37
Special Function Registers ................................................ 12
Stack .................................................................................. 18
Overflows ................................................................... 18
Underflows ................................................................. 18
STATUS ................................................................... 7, 15, 42
T
time-out .............................................................................. 42
Timer0
Switching Prescaler Assignment ................................ 31
T0IF ............................................................................ 48
Timer0 Module ........................................................... 27
TMR0 Interrupt ........................................................... 48
TMR0 with External Clock .......................................... 29
Timing Diagrams
Time-out Sequence .................................................... 44
Timing Diagrams and Specifications ............................ 80, 92
TRISA ................................................................................. 21
TRISB ........................................................................... 23, 42
W
W ........................................................................................ 42
Wake-up from SLEEP .................................................. 42, 51
Watchdog Timer (WDT) ................................... 37, 41, 42, 50
WDT ................................................................................... 42
Period ......................................................................... 50
DS30430C-page 120
PIC16F8X
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip
World Wide Web (WWW) site.
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape or Microsoft
Explorer. Files are also available for FTP download
from our FTP site.
DS30430C-page 121
PIC16F8X
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
To:
RE:
Reader Response
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
Application (optional):
Would you like a reply?
Device: PIC16F8X
N
Literature Number: DS30430C
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
8. How would you improve our software, systems, and silicon products?
DS30430C-page 122
PIC16F8X
PIC16F8X PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
Device
Frequency
Range
-XX
Frequency Temperature
Range
Range
/XX
XXX
Package
Pattern
PIC16F8X(2), PIC16F8XT(3)
PIC16LF8X(2), PIC16LF8XT(3)
PIC16F8XA(2), PIC16F8XAT(3)
PIC16LF8XA(2), PIC16LF8XAT(3)
PIC16CR8X(2), PIC16CR8XT(3)
PIC16LCR8X(2), PIC16LCR8XT(3)
04
10
20
(1)
= 4 MHz
= 10 MHz
= 20 MHz
= 0C to
= -40C to
+70C
+85C
(Commercial)
(Industrial)
Temperature
Range
b
I
Package
P
SO
SS
Pattern
= PDIP
= SOIC (Gull Wing, 300 mil body)
= SSOP
Examples:
a)
b)
c)
Note 1: b = blank
2: F
= Standard VDD range
LF = Extended VDD range
CR = ROM Version, Standard VDD
range
LCR = ROM Version, Extended VDD
range
3: T = in tape and reel - SOIC, SSOP
packages only.
2.
3.
The Microchips Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
For latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302.
DS30430C-page 123
Note the following details of the code protection feature on PICmicro MCUs.
The PICmicro family meets the specifications contained in the Microchip Data Sheet.
Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,
when used in the intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet.
The person doing so may be engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of
our product.
If you have any further questions about this matter, please contact the local sales office nearest to you.
Trademarks
The Microchip name and logo, the Microchip logo, FilterLab,
KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER,
PICSTART, PRO MATE, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode
and Total Endurance are trademarks of Microchip Technology
Incorporated in the U.S.A.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
2002, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
M
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
Japan
Corporate Office
Australia
Rocky Mountain
China - Beijing
Atlanta
500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Tel: 770-640-0034 Fax: 770-640-0307
Boston
2 Lan Drive, Suite 120
Westford, MA 01886
Tel: 978-692-3848 Fax: 978-692-3821
Chicago
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 630-285-0071 Fax: 630-285-0075
Dallas
4570 Westgrove Drive, Suite 160
Addison, TX 75001
Tel: 972-818-7423 Fax: 972-818-2924
Detroit
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: 248-538-2250 Fax: 248-538-2260
Kokomo
2767 S. Albright Road
Kokomo, Indiana 46902
Tel: 765-864-8360 Fax: 765-864-8387
Los Angeles
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: 949-263-1888 Fax: 949-263-1338
China - Chengdu
Microchip Technology Consulting (Shanghai)
Co., Ltd., Chengdu Liaison Office
Rm. 2401, 24th Floor,
Ming Xing Financial Tower
No. 88 TIDU Street
Chengdu 610016, China
Tel: 86-28-6766200 Fax: 86-28-6766599
China - Fuzhou
Microchip Technology Consulting (Shanghai)
Co., Ltd., Fuzhou Liaison Office
Unit 28F, World Trade Plaza
No. 71 Wusi Road
Fuzhou 350001, China
Tel: 86-591-7503506 Fax: 86-591-7503521
China - Shanghai
Microchip Technology Consulting (Shanghai)
Co., Ltd.
Room 701, Bldg. B
Far East International Plaza
No. 317 Xian Xia Road
Shanghai, 200051
Tel: 86-21-6275-5700 Fax: 86-21-6275-5060
China - Shenzhen
San Jose
Hong Kong
New York
Toronto
6285 Northam Drive, Suite 108
Mississauga, Ontario L4V 1X5, Canada
Tel: 905-673-0699 Fax: 905-673-6509
India
Microchip Technology Inc.
India Liaison Office
Divyasree Chambers
1 Floor, Wing A (A3/A4)
No. 11, OShaugnessey Road
Bangalore, 560 025, India
Tel: 91-80-2290061 Fax: 91-80-2290062
Korea
Microchip Technology Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea 135-882
Tel: 82-2-554-7200 Fax: 82-2-558-5934
Singapore
Microchip Technology Singapore Pte Ltd.
200 Middle Road
#07-02 Prime Centre
Singapore, 188980
Tel: 65-334-8870 Fax: 65-334-8850
Taiwan
Microchip Technology Taiwan
11F-3, No. 207
Tung Hua North Road
Taipei, 105, Taiwan
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
EUROPE
Denmark
Microchip Technology Nordic ApS
Regus Business Centre
Lautrup hoj 1-3
Ballerup DK-2750 Denmark
Tel: 45 4420 9895 Fax: 45 4420 9910
France
Microchip Technology SARL
Parc dActivite du Moulin de Massy
43 Rue du Saule Trapu
Batiment A - ler Etage
91300 Massy, France
Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Germany
Microchip Technology GmbH
Gustav-Heinemann Ring 125
D-81739 Munich, Germany
Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Italy
Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Milan, Italy
Tel: 39-039-65791-1 Fax: 39-039-6899883
United Kingdom
Arizona Microchip Technology Ltd.
505 Eskdale Road
Winnersh Triangle
Wokingham
Berkshire, England RG41 5TU
Tel: 44 118 921 5869 Fax: 44-118 921-5820
01/18/02