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Data Sheet
FEATURES
GENERAL DESCRIPTION
APPLICATIONS
Wireless infrastructure (W-CDMA, TD-SCDMA, WiMAX, GSM,
PCS, DCS, DECT)
Point to point/point to multipoint microwave links
Satellites/VSATs
Test equipment/instrumentation
Clock generation
AV DD
CE
REFIN A
REFIN B
CLK
DATA
LE
2
DOUBLER
10-BIT R
COUNTER
DVDD
RSET
VP
VVCO
VRF
AVDD
MULTIPLEXER
2
DIVIDER
MUXOUT
LOCK
DETECT
CREG 1
CREG 2
DATA REGISTER
FUNCTION
LATCH
CHARGE
PUMP
CPOUT
PHASE
COMPARATOR
INTEGER
REGISTER
FRACTION
REGISTER
VTUNE
VREF
VBIAS
VCO
CORE
MODULUS
REGISTER
VREGVCO
1/2/4/8
16/32/64
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
OUTPUT
STAGE
RFOUTA+
RFOUTA
PDBRF
MULTIPLEXER
AGND
CPGND
AGNDRF
SDGND
ADF4355
AGNDVCO
RFOUTB+
RFOUTB
12910-001
OUTPUT
STAGE
N COUNTER
Figure 1.
Rev. 0
Document Feedback
ADF4355
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Register 4 ..................................................................................... 22
Applications ....................................................................................... 1
Register 5 ..................................................................................... 23
Register 6 ..................................................................................... 24
Register 7 ..................................................................................... 26
Register 8 ..................................................................................... 27
Specifications..................................................................................... 3
Register 9 ..................................................................................... 27
Register 10 ................................................................................... 28
Register 11 ................................................................................... 28
Register 12 ................................................................................... 29
RF N Divider ............................................................................... 12
Optimizing Jitter......................................................................... 30
Lock Time.................................................................................... 31
VCO.............................................................................................. 14
Printed Circuit Board (PCB) Design Guidelines for a ChipScale Package .............................................................................. 33
Register 0 ..................................................................................... 18
Register 1 ..................................................................................... 19
Register 2 ..................................................................................... 20
Register 3 ..................................................................................... 21
REVISION HISTORY
4/15Revision 0: Initial Version
Rev. 0 | Page 2 of 35
Data Sheet
ADF4355
SPECIFICATIONS
AVDD = DVDD = VRF = 3.3 V 5%, 4.75 V VP = VVCO 5.25 V, AGND = CPGND = AGNDVCO = SDGND = AGNDRF = 0 V, RSET = 5.1 k,
dBm referred to 50 , TA = TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
REFINA/REFINB CHARACTERISTICS
Input Frequency
Single-Ended Mode
Differential Mode
Input Sensitivity
Single-Ended Mode
Symbol
Min
Typ
Max
Unit
10
10
250
600
MHz
MHz
0.4
AVDD
V p-p
0.4
1.8
V p-p
60
250
125
pF
pF
A
A
MHz
Differential Mode
Input Capacitance
Single-Ended Mode
Differential Mode
Input Current
Phase Detector Frequency
CHARGE PUMP (CP)
Charge Pump Current, Sink/Source
High Value
Low Value
RSET Range
Current Matching
ICP vs. VCP 1
ICP vs. Temperature
LOGIC INPUTS
Input High Voltage
Input Low Voltage
Input Current
Input Capacitance
LOGIC OUTPUTS
Output High Voltage
Output High Current
Output Low Voltage
POWER SUPPLIES
Analog Power
Digital Power and RF Supply Voltage
Charge Pump and VCO Voltage
Charge Pump Supply Power Current
Digital Power Supply Current +
Analog Power Supply Curent 3
Output Dividers
Supply Current
RFOUTA/RFOUTB Supply Current
Low Power Sleep Mode
Test Conditions/Comments
6.9
1.4
ICP
VINH
VINL
IINH/IINL
CIN
1.5
VOH
DVDD 0.4
1.5
mA
mA
k
%
%
%
0.6
1
3.0
3.15
4.75
AVDD
5.0
8
62
6 to 36
70
16/20/
42/55
500
1000
500
0.4
3.45
5.25
9
69
Rev. 0 | Page 3 of 35
85
20/35/
50/70
Fixed
0.5 V VCP1 VP 0.5 V
0.5 V VCP1 VP 0.5 V
VCP1 = 2.5 V
V
V
A
pF
V
V
A
V
1.8
IOH
VOL
IVCO
IRFOUT x
RSET = 5.1 k
4.8
0.3
5.1
3
3
1.5
AVDD
DVDD, VRF
VP, VVCO
IP
DIDD, AIDD
mA
mA
mA
mA
A
A
ADF4355
Parameter
RF OUTPUT CHARACTERISTICS
VCO Frequency Range
RF Output Frequency
VCO Sensitivity
Frequency Pushing (Open-Loop)
Frequency Pulling (Open-Loop)
Harmonic Content
Second
Third
RF Output Power 4
RF Output Power Variation
RF Output Power Variation (over
Frequency)
Level of Signal with RF Output
Disabled
Data Sheet
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
6800
6800
15
15
0.5
MHz
MHz
MHz/V
MHz/V
MHz
27
22
20
12
+8
+3
1
3
dBc
dBc
dBc
dBc
dBm
dBm
dB
dB
60
dBm
30
dBm
3400
53.125
KV
NOISE CHARACTERISTICS
Fundamental VCO Phase Noise
Performance
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
221
223
116
150
80
dBc/Hz
dBc/Hz
dBc/Hz
fs
dBc
Rev. 0 | Page 4 of 35
Data Sheet
ADF4355
TIMING CHARACTERISTICS
AVDD = DVDD =VRF = 3.3 V 5%, 4.75 V VP = VVCO 5.25 V, AGND = CPGND = AGNDVCO = SDGND = AGNDRF = 0 V, RSET = 5.1 k,
dBm referred to 50 , TA = TMIN to TMAX, unless otherwise noted.
Table 2. Write Timing
Parameter
t1
t2
t3
t4
t5
t6
t7
Limit
20
10
10
25
25
10
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Description
LE setup time
DATA to CLK setup time
DATA to CLK hold time
CLK high duration
CLK low duration
CLK to LE setup time
LE pulse width
t5
CLK
t3
t2
DATA
DB31 (MSB)
DB30
DB3
(CONTROL BIT C4)
DB2
(CONTROL BIT C3)
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t7
t1
t6
Rev. 0 | Page 5 of 35
12910-002
LE
ADF4355
Data Sheet
Rating
0.3 V to +3.6 V
0.3 V to +0.3 V
0.3 V to +5.8 V
0.3 V to AVDD + 2.5 V
0.3 V to VP + 0.3 V
0.3 V to DVDD + 0.3 V
0.3 V to AVDD + 0.3 V
0.3 V to AVDD + 0.3 V
2.1 V
40C to +85C
65C to +125C
150C
27.3C/W
TRANSISTOR COUNT
The transistor count for the ADF4355 is 103,665 (CMOS) and
3214 (bipolar).
ESD CAUTION
260C
40 sec
1000 V
2500 V
Rev. 0 | Page 6 of 35
Data Sheet
ADF4355
32
31
30
29
28
27
26
25
CREG 2
SDGND
MUXOUT
REFINA
REFINB
DVDD
PDBRF
CREG 1
1
2
3
4
5
6
7
8
ADF4355
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
VBIAS
VREF
RSET
AGNDVCO
VTUNE
VREGVCO
AGNDVCO
VVCO
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO AGND.
12910-003
AGND
VRF
RFOUTA+
RFOUTA
AGNDRF
RFOUTB+
RFOUTB
AV DD
9
10
11
12
13
14
15
16
CLK
DATA
LE
CE
AVDD
VP
CPOUT
CPGND
Mnemonic
CLK
DATA
LE
CE
5, 16
AVDD
VP
CPOUT
8
9
10
CPGND
AGND
VRF
11
RFOUTA+
12
RFOUTA
13
14
AGNDRF
RFOUTB+
15
RFOUTB
17
VVCO
18, 21
19
AGNDVCO
VREGVCO
20
VTUNE
Description
Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high
impedance CMOS input.
Serial Data Input. The serial data is loaded most significant bit (MSB) first with the four least significant bits (LSBs)
as the control bits. This input is a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into the register that
is selected by the four LSBs.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode. A
logic high (at levels equal to DVDD) on this pin powers up the device, depending on the status of the power-down bits.
Analog Power Supply. This pin ranges from 3.15 V to 3.45 V. Connect decoupling capacitors to the analog ground
plane as close to this pin as possible. AVDD must have the same value as DVDD.
Charge Pump Power Supply. VP must have the same value as VVCO. Connect decoupling capacitors to the ground
plane as close to this pin as possible.
Charge Pump Output. When enabled, this output provides ICP to the external loop filter. The output of the loop
filter is connected to VTUNE to drive the internal VCO.
Charge Pump Ground. This output is the ground return pin for CPOUT.
Analog Ground. Ground return pin for AVDD.
Power Supply for the RF Output. Connect decoupling capacitors to the analog ground plane as close to this pin
as possible. VRF must have the same value as AVDD.
VCO Output. The output level is programmable. The VCO fundamental output or a divided down version is
available.
Complementary VCO Output. The output level is programmable. The VCO fundamental output or a divided down
version is available.
RF Output Stage Ground. Ground return pins for the RF output stage.
Auxiliary VCO Output. The output level is programmable. The VCO fundamental output or a divided down version
is available.
Complementary Auxiliary VCO Output. The output level is programmable. The VCO fundamental output or a
divided down version is available.
Power Supply for the VCO. The voltage on this pin ranges from 4.75 V to 5.25 V. Connect decoupling capacitors to
the analog ground plane as close to this pin as possible.
VCO Ground. Ground return path for the VCO.
VCO Compensation Node. Connect decoupling capacitors to the ground plane as close to this pin as possible.
Connect this pin directly to VVCO.
Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CPOUT
output voltage.
Rev. 0 | Page 7 of 35
ADF4355
Pin No.
22
23
Mnemonic
RSET
VREF
24
25, 32
VBIAS
CREG1, CREG2
26
27
PDBRF
DVDD
28
29
30
REFINB
REFINA
MUXOUT
31
SDGND
EP
Data Sheet
Description
Bias Current Resistor. Connecting a resistor between this pin and ground sets the charge pump output current.
Internal Compensation Node. DC biased at half the tuning range. Connect decoupling capacitors to the ground
plane as close to this pin as possible.
Reference Voltage. Connect a 100 nF decoupling capacitor to the ground plane as close to this pin as possible.
Outputs from the LDO Regulator. Pin 25 and Pin 32 are the supply voltages to the digital circuits and have a
nominal voltage of 1.8 V. Decoupling capacitors of 100 nF connected to AGND are required for these pins.
RF Power-Down. A logic low on this pin mutes the RF outputs. This mute function is also software controllable.
Digital Power Supply. This pin must be at the same voltage as AVDD. Place decoupling capacitors to the ground
plane as close to this pin as possible.
Complementary Reference Input. If unused, ac-couple this pin to AGND.
Reference Input.
Multiplexer Output. The multiplexer output allows the digital lock detect, the analog lock detect, scaled RF, or the
scaled reference frequency to be externally accessible.
Digital - Modulator Ground. Pin 31 is the ground return path for the - modulator.
Exposed Pad. The exposed pad must be connected to AGND.
Rev. 0 | Page 8 of 35
Data Sheet
ADF4355
50
50
70
70
90
110
130
150
10k
100k
1M
10M
100M
130
170
1k
50
70
70
90
110
130
150
1M
10M
100M
1
2
4
8
16
32
64
90
110
130
10k
100k
1M
10M
100M
170
12910-005
1k
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
12910-008
150
FREQUENCY (Hz)
70
70
50
90
110
130
150
1
2
4
8
16
32
64
90
110
130
150
1k
10k
100k
1M
10M
FREQUENCY (Hz)
100M
170
12910-006
170
100k
50
170
10k
FREQUENCY (Hz)
110
12910-007
1k
FREQUENCY (Hz)
90
150
12910-004
170
1
2
4
8
16
32
64
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
12910-009
Rev. 0 | Page 9 of 35
ADF4355
1
2
70
90
110
130
170
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
12910-010
150
10
9
8
7
6
5
4
3
2
1
0
1
2
3
4
5
6
7
8
9
10
FREQUENCY (GHz)
1
2
SECOND HARMONIC
THIRD HARMONIC
70
10
15
90
POWER (dBc)
40C
+25C
+85C
12910-016
50
Data Sheet
110
130
20
25
30
35
40
150
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
50
12910-011
170
FREQUENCY (GHz)
1
2
70
6
4
90
POWER (dBm)
12910-017
45
110
130
2
0
2
4
6
150
10k
100k
1M
FREQUENCY (Hz)
10M
100M
12910-012
1k
10
FREQUENCY (GHz)
12910-018
8
170
Rev. 0 | Page 10 of 35
Data Sheet
0.40
100
110
0.30
0.25
120
0.20
130
0.15
140
0.10
150
0.05
1.8
2.8
3.8
4.8
5.8
6.8
Figure 16. RMS Jitter vs. Output Frequency, PFD Frequency = 61.44 MHz,
Loop Filter = 20 kHz
50
10k
100k
1M
10M
100M
FREQUENCY (Hz)
90
100
70
110
80
120
130
90
140
100
160
10k
100k
1M
10M
100M
FREQUENCY (Hz)
80
4.65
4.60
90
4.55
FREQUENCY (GHz)
100
110
120
130
140
4.50
4.45
1
4.40
4.35
4.30
4.25
150
4.20
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
4.15
1
12910-024
160
1k
12910-026
150
12910-022
110
1k
80
PFD = 15.36MHz
PFD = 30.72MHz
PFD = 61.44MHz
60
160
12910-021
0
0.8
TIME (ms)
12910-128
0.35
90
12910-025
0.45
80
0.50
ADF4355
Figure 21. Lock Time for 250 MHz Jump from 4150 MHz to 4400 MHz,
Loop Bandwidth = 20 kHz
Rev. 0 | Page 11 of 35
ADF4355
Data Sheet
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
BUFFER
SW1
SW3
MULTIPLEXER
TO
R COUNTER
AVDD
ECL TO CMOS
CONVERTER
REFINA
REFINB
2.5k
2.5k
12910-226
SW4
BIAS
GENERATOR
RF N DIVIDER
The RF N divider allows a division ratio in the PLL feedback
path. Determine the division ratio by the INT, FRAC1, FRAC2,
and MOD2 values that this divider comprises.
RF N COUNTER
FRAC1 +
N = INT +
MOD2
MOD1
TO PFD
N COUNTER
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
INT
REGISTER
FRAC1
REGISTER
FRAC2
VALUE
MOD2
VALUE
12910-027
FROM
VCO OUTPUT/
OUTPUT DIVIDERS
FRAC2
(5)
Data Sheet
ADF4355
DVDD
THREE-STATE OUTPUT
(6)
where:
fPFD is the frequency of the phase frequency detector.
GCD is a greatest common denominator function.
fCHSP is the desired channel spacing frequency.
DVDD
SDGND
R DIVIDER OUTPUT
N DIVIDER OUTPUT
MUX
CONTROL
SDGND
R Counter
The 10-bit R counter allows the input reference frequency
(REFIN) to be divided down to produce the reference clock to
the PFD. Division ratios from 1 to 1023 are allowed.
Q1
UP
U1
CLR1
DELAY
HIGH
U3
CHARGE
PUMP
CP
CLR2
DOWN
D2
Q2
U2
IN
12910-028
+IN
12910-029
RESERVED
INT N Mode
HIGH
MUXOUT
C3
0
0
0
0
1
1
1
1
0
0
0
0
1
Control Bits
C2
0
0
1
1
0
0
1
1
0
0
1
1
0
C1
0
1
0
1
0
1
0
1
0
1
0
1
0
Register
Register 0
Register 1
Register 2
Register 3
Register 4
Register 5
Register 6
Register 7
Register 8
Register 9
Register 10
Register 11
Register 12
PROGRAM MODES
Rev. 0 | Page 13 of 35
ADF4355
Data Sheet
VCO
The VCO core in the ADF4355 consists of four separate VCOs,
each of which uses 256 overlapping bands, which allows covering
a wide frequency range without a large VCO sensitivity (KV) and
without resultant poor phase noise and spurious performance.
The correct VCO and band are chosen automatically by the
VCO and band select logic when Register 0 is updated and autocalibration is enabled. The VCO VTUNE is disconnected from
the output of the loop filter and is connected to an internal
reference voltage.
The R counter output is used as the clock for the band select
logic. After band selection, normal PLL action resumes. The
nominal value of KV is 15 MHz/V when the N divider is driven
from the VCO output, or the KV value is divided by D. D is the
output divider value if the N divider is driven from the RF
output divider (chosen by programming Bits[D23:D21] in
Register 6).
The VCO shows variation of KV as the tuning voltage, VTUNE,
varies within the band and from band to band. For wideband
applications covering a wide frequency range (and changing
output dividers), a value of 15 MHz/V provides the most accurate
KV, because this value is closest to the average value. Figure 26
shows how KV varies with fundamental VCO frequency along with
an average value for the frequency band. Users may prefer this
figure when using narrow-band designs.
50
VCO
50
RFOUTA
BUFFER/
DIVIDE BY
1/2/4/8/
16/32/64
40
35
30
LINEAR
TREND LINE
AVERAGE
VCO SENSITIVITY
25
20
15
10
3.8
4.3
4.8
5.3
5.8
FREQUENCY (GHz)
6.3
6.8
12910-133
5
0
3.3
VRF
45
OUTPUT STAGE
12910-032
Rev. 0 | Page 14 of 35
Data Sheet
ADF4355
RFOUTA Off
78 mA
RFOUTA = 4 dBm
78 mA
RFOUTA = 1 dBm
78 mA
RFOUTA = +2 dBm
78 mA
RFOUTA = +5 dBm
78 mA
79.8 mA
87.8 mA
97.1 mA
104.9 mA
109.8 mA
113.6 mA
115.9 mA
101.3 mA
110.1 mA
119.3 mA
127.1 mA
131.8 mA
135.5 mA
137.8 mA
111.9 mA
120.6 mA
130.1 mA
137.8 mA
142.7 mA
146.5 mA
148.9 mA
122.7 mA
131.9 mA
141.6 mA
149.2 mA
154.1 mA
157.8 mA
160.1 mA
132.8 mA
141.9 mA
152.1 mA
159.7 mA
164.6 mA
168.4 mA
170.8 mA
Rev. 0 | Page 15 of 35
ADF4355
Data Sheet
REGISTER MAPS
AUTOCAL
PRESCALER
REGISTER 0
RESERVED
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
0
PR1
AC1
N15
N16
N14
N13
N12
N11
N10
N9
N8
N7
DB8
DB7
DB6
DB5
DB4
N5
N4
N3
N2
N1
N6
DB3
DB2
C4(0) C3(0)
DB1
DB0
C2(0) C1(0)
REGISTER 1
RESERVED
CONTROL
BITS
DBR 1
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
F24
F23
F22
F21
F20
F19
F18
F17
F16
F15
F14
F13
F12
F11
F10
F9
F8
F7
F6
DB7 DB6
F5
F4
F3
DB5 DB4
DB3
F2
F1
DB2
DB1
DB0
REGISTER 2
DBR 1
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
F14
F13
F11
F12
F10
F9
F8
F7
F6
F5
CONTROL
BITS
F4
F3
F2
M14
F1
M13
M12
M11
M10
M9
M8
M7
DB8
DB7
DB6
DB5
DB4
M5
M4
M3
M2
M1
M6
DB3
DB2
DB1
DB0
PHASE
ADJUST
PHASE
RESYNC
SD LOAD
RESET
RESERVED
REGISTER 3
CONTROL
BITS
DBR 1
P23
P22
P21
P20
P19
P18
P17
P16
P15
P14
P13
P12
P11
P10
P9
P8
P7
DB5 DB4
DB3
P6
P5
P4
P3
P2
P1
COUNTER
RESET
P24
CP THREESTATE
PA1
POWER-DOWN
PR1
PD
POLARIT Y
SD1
MUX LOGIC
REF MODE
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
DB7 DB6
DB2
DB1
DB0
CONTROL
BITS
DBR 1
DOUBLE BUFF
MUXOUT
RDIV2
RESERVED
REFERENCE
DOUBLER DBR 1
REGISTER 4
DBR 1
10-BIT R COUNTER
CURRENT
SETTING
DBR 1
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
M3
M2
M1
RD2
RD1
R10
R9
R8
R7
R6
R5
R4
R3
R2
D1
R1
CP4
CP3
CP2
CP1
U6
DB7 DB6
U5
U4
U3
DB5 DB4
DB3
U2
U1
DB2
DB1
DB0
REGISTER 5
CONTROL
BITS
DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
RF OUTPUT
ENABLE
RESERVED
RF
OUTPUT
POWER
DB3
DB2
DB1
DB0
AUX RF
OUTPUT
POWER
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
1DBR
2DBB
BL10
BL9
D13
D12
D11
D10
BL8
BL7
BL6
BL5
BL4
BL3
BL2
BL1
D8
D6
D5
D4
D3
D2
D1
DB2
DB1
DB0
AUX RF OUTPUT
ENABLE
RESERVED
RF DIVIDER
SELECT2
MTLD
RESERVED
RESERVED
FEEDBACK
SELECT
NEGATIVE
BLEED
RESERVED
GATED
BLEED
REGISTER 6
Data Sheet
ADF4355
LDO MODE
LD
CYCLE
COUNT
RESERVED
FRAC-N LD
PRECISION
RESERVED
LOL MODE
LE SYNC
REGISTER 7
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4
0
LE
LD4
LD5
LOL LD3
CONTROL
BITS
DB3
DB2
DB1
DB0
REGISTER 8
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
DB7 DB6
DB5 DB4
1
DB3
DB2
DB1
DB0
REGISTER 9
SYNTHESIZER
LOCK TIMEOUT
TIMEOUT
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
VC8
VC7
VC6
VC5
VC4
VC3
VC2
VC1
TL10
TL9
TL8
TL7
TL6
TL5
TL4
TL3
TL2
TL1
AL5
AL4
AL3
AL2
AL1
SL5
CONTROL
BITS
DB7 DB6
DB5 DB4
SL4
SL2
SL3
DB3
DB2
DB1
DB0
ADC
CLOCK DIVIDER
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
AD8
AD7
AD6
AD5
AD4
DB7 DB6
AD3 AD2
AD1
ADC ENABLE
ADC
CONVERSION
REGISTER 10
DB5 DB4
CONTROL
BITS
DB3
DB2
DB1
DB0
REGISTER 11
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
DB7 DB6
DB5 DB4
0
DB3
DB2
DB1
DB0
REGISTER 12
P15
P14
P13
P12
P11
P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
Rev. 0 | Page 17 of 35
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
12910-035
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
P16
CONTROL
BITS
RESERVED
RESYNC CLOCK
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
0
AC1
PR1
N16
N15
N14
N13
N12
N11
N10
N9
N8
N7
DB8
N6
N5
DB7
N4
DB6
N3
N2
PR1
PRESCALER
N16
N15
...
N5
N4
N3
N2
N1
4/5
...
NOT ALLOWED
8/9
...
NOT ALLOWED
...
NOT ALLOWED
...
...
...
NOT ALLOWED
23
DB4
N1
DB3
DB2
DB1
DB0
...
VCO
AUTOCAL
...
...
...
DISABLED
...
65533
ENABLED
...
65534
...
65535
AC1
DB5
24
12910-036
RESERVED
PRESCALER
Data Sheet
AUTOCAL
ADF4355
REGISTER 0
Prescaler
Control Bits
The dual modulus prescaler (P/P + 1), along with the INT,
FRACx, and MODx counters, determines the overall division
ratio from the VCO output to the PFD input. The PR1 bit
(Bit DB20) in Register 0 sets the prescaler value.
Reserved
Operating at CML levels, the prescaler takes the clock from the
VCO output and divides it down for the counters. It is based on
a synchronous 4/5 core. When the prescaler is set to 4/5, the
maximum RF frequency allowed is 7 GHz. The prescaler limits
the INT value; therefore, if P is 4/5, NMIN is 23, and if P is 8/9,
NMIN is 75.
Rev. 0 | Page 18 of 35
Data Sheet
ADF4355
CONTROL
BITS
DBR 1
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
F24
F23
F22
F21
F20
F19
F18
F17
F16
F15
F14
F13
F12
F11
F10
F9
F8
F7
F6
F24
F23
..........
F2
F1
..........
..........
..........
..........
..........
..........
..........
..........
16777212
..........
16777213
..........
16777214
.........
16777215
F5
F3
F2
F1
DB3
DB2
DB1
DB0
12910-037
RESERVED
REGISTER 1
Control Bits
Reserved
Bits[DB31:DB28] are reserved and must be set to 0.
Rev. 0 | Page 19 of 35
ADF4355
Data Sheet
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
F14
F13
F12
F11
F10
F9
F8
F7
F6
F5
F4
CONTROL
BITS
F3
F2
F1
M14
M13
M12
M11
M10
M9
M8
M7
M6
DB8
DB7
DB6
DB5
DB4
M5
M4
M3
M2
M1
DB3
DB2
DB1
DB0
F14
F13
..........
F2
F1
FRAC2 WORD
M14
M13
..........
M2
M1
..........
..........
NOT ALLOWED
..........
..........
NOT ALLOWED
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
16381
..........
16380
..........
16382
..........
16381
..........
16382
..........
16382
.........
16383
.........
16383
REGISTER 2
Control Bits
Rev. 0 | Page 20 of 35
12910-038
DBR 1
ADF4355
PHASE
ADJUST
PHASE
RESYNC
SD LOAD
RESET
RESERVED
Data Sheet
CONTROL
BITS
DBR 1
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
SD1
PR1
PA1
PA1
PR1
SD1
1DBR
P24
P23
P22
P21
P20
P19
PHASE
ADJUST
P18
P17
P16
P15
P14
P13
P12
P11
P10
P9
P8
P24
P23
..........
P2
P1
DISABLED
..........
ENABLED
..........
..........
..........
..........
..........
..........
..........
16777212
..........
16777213
..........
16777214
.........
16777215
PHASE
RESYNC
DISABLED
ENABLED
SD LOAD
RESET
ON REGISTER0 UPDATE
DISABLED
P7
P6
P5
P4
P3
P2
P1
DB3
DB2
DB1
DB0
12910-039
REGISTER 3
Control Bits
With Bits[C4:C1] set to 0011, Register 3 is programmed. Figure 33
shows the input data format for programming this register.
Reserved
Phase Adjust
SD Load Reset
When writing to Register 0, the - modulator resets. For
applications in which the phase is continually adjusted, this may
not be desirable; therefore, in these cases, the - reset can be
disabled by writing a 1 to the SD1 bit (Bit DB30).
Phase Resync
To use the phase resynchronization feature, the PR1 bit (Bit DB29)
must be set to 1. If unused, the bit can be programmed to 0. The
phase resync timer must also be used in Register 12 to ensure that
the resynchronization feature is applied after the PLL has settled
to the final frequency. If the PLL has not settled to the final frequency,
phase resync may not function correctly. Resynchronization is
useful in phased array and beam forming applications. It ensures
repeatability of output phase when programming the same
frequency. In phase critical applications that use frequencies
requiring the output divider (<3400 MHz), it is necessary to
feed the N divider with the divided VCO frequency as distinct
Rev. 0 | Page 21 of 35
COUNTER
RESET
CP THREESTATE
DBR 1
POWER-DOWN
CURRENT
SETTING
PD
POLARITY
DBR 1
10-BIT R COUNTER
REF MODE
DOUBLE BUFF
DBR 1
RDIV2
MUXOUT
RESERVED
MUX LOGIC
Data Sheet
REFERENCE
DOUBLER DBR 1
ADF4355
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4
0
M3
M2
M1
RD2
R10
RD2
REFERENCE
DOUBLER
DISABLED
R9
R8
R7
R6
R5
ENABLED
R4
R3
R2
R1
D1
CP4
CP3
COUNTER
RESET
DISABLED
ENABLED
DIFF
ENABLED
CP1
ICP (mA)
5.1k
ENABLED
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0.31
0.63
0.94
1.25
1.56
1.88
2.19
2.50
2.81
3.13
3.44
3.75
4.06
4.38
4.69
5.00
..........
..........
..........
..........
..........
1020
..........
1021
..........
1022
..........
1023
M3
M2
M1
OUTPUT
THREE-STATE OUTPUT
DVDD
SDGND
R DIVIDER OUTPUT
N DIVIDER OUTPUT
RESERVED
DB2
CP2
..........
DB3
DB1
U1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
U1
REFIN
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
U2
SINGLE
CP3
R DIVIDER (R)
U3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
R1
U4
U6
CP4
R2
U5
DISABLED
DISABLED
..........
U6
DOUBLE BUFFERED
REGISTER 6, BITS[DB23:DB21]
R9
CP1
REFERENCE DIVIDE BY 2
R10
CP2
D1
RD1
1
1DBR
RD1
U5
LDP
U2
CP
THREE-STATE
1.8V
DISABLED
3.3V
ENABLED
U4
PD POLARITY
U3
POWER DOWN
NEGATIVE
DISABLED
POSITIVE
ENABLED
DB0
C1(0)
12910-040
CONTROL
BITS
REGISTER 4
RDIV2
Control Bits
Reserved
10-Bit R Counter
MUXOUT
The on-chip multiplexer (MUXOUT) is controlled by
Bits[DB29:DB27]. For additional details, see Figure 34.
Double Buffer
Reference Doubler
Setting the RD2 bit (Bit DB26) to 0 feeds the REFIN signal directly
to the 10-bit R counter, disabling the doubler. Setting this bit to
1 multiplies the reference frequency by a factor of 2 before
feeding it into the 10-bit R counter. When the doubler is
disabled, the REFIN falling edge is the active edge at the PFD
input to the fractional synthesizer. When the doubler is enabled,
both the rising and falling edges of the reference frequency
become active edges at the PFD input.
Rev. 0 | Page 22 of 35
Data Sheet
ADF4355
Reference Mode
Level Select
Counter Reset
The U1 bit (Bit DB4) resets the R counter, N counter, and VCO
band select of the ADF4355. When DB4 is set to 1, the RF
synthesizer N counter and R counter, and the VCO band select,
are reset. For normal operation, set DB4 to 0. Toggling counter
reset (Bit DB4) is also required when changing frequency (see
the Frequency Update Sequence section for additional details).
Power-Down
The U3 bit (Bit DB6) sets the programmable power-down mode.
Setting DB6 to 1 performs a power-down. Setting DB6 to 0
returns the synthesizer to normal operation. In software powerdown mode, the ADF4355 retains all information in its registers.
The register contents are only lost if the supply voltages are
removed.
REGISTER 5
The bits in Register 5 are reserved and must be programmed as
described in Figure 35, using a hexadecimal word of 0x00800025.
DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
0
Rev. 0 | Page 23 of 35
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
12910-041
CONTROL
BITS
RESERVED
AUX RF
OUTPUT
POWER
RF OUTPUT
ENABLE
AUX RF OUTPUT
ENABLE
RESERVED
RF
OUTPUT
POWER
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
BL10
BL9
D13
D12
D11
D10
BL8
BL7
BL5
BL6
BL4
BL3
BL2
BL1
D8
D6
D5
D4
D3
FEEDBACK
D13 SELECT
0
1
DIVIDED
FUNDAMEN TAL
DISABLED
ENABLED
DISABLED
ENABLED
D12
D11
D10
RF DIVIDER SELECT
D8
MUTE TILL
LOCK DETECT
MUTE DISABLED
16
MUTE ENABLED
32
64
BL8
1BITS[DB23:DB21]
BL7
..........
BL2
BL1
..........
(3.75A)
..........
(7.5A)
..........
..........
..........
..........
252
(945A)
..........
253
(948.75A)
..........
254
(952.5A)
..........
255
(956.25A)
D2
D1
DB2
DB1
D2
D1
OUTPUT POWER
4dBm
1dBm
+2dBm
+5dBm
D3
RF OUT
DISABLED
ENABLED
D5
D4
4dBm
1dBm
+2dBm
+5dBm
D6
AUXILIARY OUT
DISABLED
ENABLED
DB0
BLEED CURRENT
ARE BUFFERED BY A WRITE TO REGISTER 0 WHEN THE DOUBLE BUFFER BIT IS ENABLED, BIT DB14 OF REGISTER 4.
12910-042
RF DIVIDER
SELECT1
MTLD
RESERVED
RESERVED
FEEDBACK
SELECT
Data Sheet
NEGATIVE
BLEED
GATED
BLEED
RESERVED
ADF4355
REGISTER 6
Reserved
Control Bits
Feedback Select
Reserved
Bit DB31 is reserved and must be set to 0.
Gated Bleed
Bleed currents can be used for improving phase noise and
spurs; however, due to a potential impact on lock time, the
gated bleed bit, BL10 (Bit DB30), if set to 1, ensures bleed
currents are not switched on until the digital lock detect asserts
logic high. Note that this function requires digital lock detect to
be enabled.
Negative Bleed
Use of constant negative bleed is recommended for most
applications because it improves the linearity of the charge
pump leading to lower noise and spurs than leaving negative
bleed off. To enable negative bleed, write 1 to BL9 (Bit DB29),
and to disable negative bleed, write 0 to BL9 (Bit DB29).
D13 (Bit DB24) selects the feedback from the output of the
VCO to the N counter. When D13 is set to 1, the signal is taken
directly from the VCO. When this bit is set to 0, the signal is
taken from the output of the output dividers. The dividers
enable coverage of the wide frequency band (54 MHz to
6800 MHz). When the divider is enabled and the feedback
signal is taken from the output, the RF output signals of two
separately configured PLLs are in phase. Divided feedback is
useful in some applications where the positive interference of
signals is required to increase the power.
RF Divider Select
D12 to D10 (Bits[DB23:DB21]) select the value of the RF output
divider (see Figure 36).
Rev. 0 | Page 24 of 35
Data Sheet
ADF4355
Reserved
Tests have shown that the optimal bleed set is the following:
4/N < IBLEED/ICP < 10/N
where:
IBLEED is the value of constant negative bleed applied to the
charge pump, which is set by the contents of Bits[BL8:BL1].
ICP is the value of charge pump current setting, Bits[DB13:DB10] of
Register 4.
N is the value of the feedback counter from the VCO to the PFD.
Reserved
Bit DB12 is reserved and must be set to 0.
RF Output Enable
Bit DB6 enables or disables the primary RF output (RFOUTA+/
RFOUTA). When DB6 is set to 0, the primary RF output is
disabled. When DB6 is set to 1, the primary RF output is
enabled.
Output Power
Bits[DB5:DB4] set the value of the primary RF output power
level (see Figure 36).
Rev. 0 | Page 25 of 35
LD MODE
LD
CYCLE
COUNT
RESERVED
LOL MODE
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4
0
LE
LD5
LD4
LOL LD3
LE SYNCHRONIZ ATION
DB3
DB2
DB1
DB0
LD1
LE
CONTROL
BITS
FRACTIONAL-N
INTEGER-N (2.9ns)
LD3
LD2
FRACTIONAL-N LD PRECISION
5.0ns
6.0ns
8.0ns
12.0ns
DISABLED
DISABLED
LE SYNCED TO REFIN
ENABLED
LD5
LD4
1024
2048
4096
8192
12910-043
RESERVED
FRAC-N LD
PRECISION
Data Sheet
LE SYNC
ADF4355
REGISTER 7
Control Bits
Reserved
Bits[DB31:DB29] are reserved and must be set to 0. Bit DB28 is
reserved and must be set to 1. Bits[DB27:DB26] are reserved
and must be set to 0.
LE Sync
When set to 1, Bit DB25 ensures that the load enable (LE) edge
is synchronized internally with the rising edge of reference
input frequency. This synchronization prevents the rare event of
reference and RF dividers loading at the same time as a falling
edge of reference frequency, which can lead to longer lock times.
Reserved
Bits[DB24:DB10] are reserved and must be set to 0.
Rev. 0 | Page 26 of 35
Data Sheet
ADF4355
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4
0
DB3
DB2
DB1
DB0
12910-044
CONTROL
BITS
RESERVED
SYNTHESIZER
LOCK TIMEOUT
TIMEOUT
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
VC8
VC7
VC6
VC5
VC4
VC3
VC2
VC1
TL10
TL9
TL8
TL7
TL6
TL5
TL4
TL3
TL2
TL1
AL5
AL4
AL3
AL2
TL9
..........
TL2
TL1
..........
..........
..........
..........
..........
..........
1020
..........
1021
..........
1022
..........
1023
TL10
VC8
VC7
..........
VC2
VC1
..........
..........
..........
..........
..........
..........
252
..........
253
..........
254
..........
255
TIMEOUT
AL5
SL5
DB7 DB6
DB5 DB4
SL4
SL2
SL3
DB3
SL4
..........
SL2
SL1
..........
..........
..........
..........
..........
..........
28
..........
29
..........
30
..........
31
ALC WAIT
AL4
..........
AL2
AL1
..........
..........
..........
..........
..........
..........
28
..........
29
..........
30
..........
31
DB2
DB1
DB0
SL5
AL1
CONTROL
BITS
SLC WAIT
12910-045
REGISTER 8
AL5 to AL1 (Bits[DB13:DB9]) set the timer value used for the
automatic level calibration of the VCO. This function combines
the PFD frequency, the timeout variable, and ALC wait variable.
Choose ALC such that the following equation is always greater
than 50 s.
REGISTER 9
Control Bits
With Bits[C4:C1] set to 1001, Register 9 is programmed. Figure 39
shows the input data format for programming this register.
Timeout
TL10 to TL1 (Bits[DB23:DB14]) set the timeout value for the
VCO band select. Use this value as a variable in the other VCO
calibration settings.
Rev. 0 | Page 27 of 35
ADC
CLOCK DIVIDER
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
AD8
AD7
AD6
AD5
AD4
DB7 DB6
AD3 AD2
AD7
..........
AD2
..........
..........
..........
..........
..........
..........
252
..........
253
..........
254
..........
255
AD8
DB5 DB4
AD1
CONTROL
BITS
DB3
DB2
DB1
DB0
AE1
ADC
DISABLED
ENABLED
AE2
ADC CONVERSION
DISABLED
ENABLED
12910-047
RESERVED
ADC ENABLE
Data Sheet
ADC
CONVERSION
ADF4355
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4
0
DB3
DB2
DB1
DB0
12910-048
CONTROL
BITS
RESERVED
REGISTER 10
Control Bits
With Bits[C4:C1] set to 1010, Register 10 is programmed.
Figure 40 shows the input data format for programming this
register.
Reserved
ADC Enable
AE1 (Bit DB4), when set to 1, powers up the ADC for the
temperature dependent VTUNE calibration. It is recommended to
always use this function.
REGISTER 11
The bits in this register are reserved and must be programmed
as described in Figure 41, using a hexadecimal word of
0x0061300B.
Rev. 0 | Page 28 of 35
Data Sheet
ADF4355
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
P15
P14
P13
P12
P11
P10
P8
P9
P7
P6
P5
P4
P3
P2
P16
P15
...
P5
P4
P3
P2
P1
RESYNC CLOCK
...
NOT ALLOWED
...
...
...
...
...
22
...
23
...
24
...
...
...
65533
...
65534
...
65535
P1
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
12910-049
P16
CONTROL
BITS
RESERVED
RESYNC CLOCK
REGISTER 12
Control Bits
1.
2.
3.
4.
5.
6.
Reserved
Bits[DB15:DB4] are reserved. Bit DB10 and Bit DB4 must be set
to 1, but all other bits in this range must be set to 0.
Register 12
Register 11
Register 10
Register 9
Register 8
Register 7
Register 6
Register 5
Register 4
Register 3
Register 2
Register 1
Register 0
Rev. 0 | Page 29 of 35
ADF4355
Data Sheet
FRAC2
FRAC1 +
MOD2 (fPFD)/RF Divider
RFOUT = INT +
MOD1
(7)
where:
RFOUT is the RF frequency output.
INT is the integer division factor.
FRAC1 is the fractionality.
FRAC2 is the auxiliary fractionality.
MOD2 is the auxiliary modulus.
MOD1 is the fixed 24-bit modulus.
RF Divider is the output divider that divides down the VCO
frequency.
fPFD = REFIN ((1 + D)/(R (1 + T)))
From Equation 8,
fPFD = (122.88 MHz (1 + 0)/2) = 61.44 MHz
(8)
where:
REFIN is the reference frequency input.
D is the RF REFIN doubler bit.
R is the RF reference division factor.
T is the reference divide by 2 bit (0 or 1).
For example, in a universal mobile telecommunication system
(UMTS) where 2112.8 MHz RF frequency output (RFOUT) is
required, a 122.88 MHz reference frequency input (REFIN) is
available. Note that the ADF4355 VCO operates in the frequency
range of 3.4 GHz to 6.8 GHz. Therefore, an RF divider of 2 must
be used (VCO frequency = 4225.6 MHz, RFOUT = VCO frequency/
RF divider = 4225.6 MHz/2 = 2112.8 MHz).
The feedback path is also important. In this example, the VCO
output is fed back before the output divider (see Figure 43).
In this example, divide the 122.88 MHz reference signal by 2 to
generate a fPFD of 61.44 MHz. The desired channel spacing is
200 kHz.
PFD
VCO
RFOUT
N
DIVIDER
12910-148
fPFD
(9)
(10)
where:
INT = 68
FRAC1 = 13,019,817
MOD2 = 1536
FRAC2 = 1024
RF Divider = 2
OPTIMIZING JITTER
For lowest jitter applications, use the highest possible PFD
frequency to minimize the contribution of in-band noise from
the PLL. Set the PLL filter bandwidth such that the in-band noise
of the PLL intersects with the open-loop noise of the VCO,
minimizing the contribution of both to the overall noise.
Use the ADIsimPLL design tool for this task.
Rev. 0 | Page 30 of 35
Data Sheet
ADF4355
SPUR MECHANISMS
Reference Spurs
Reference spurs are generally not a problem in fractional-N
synthesizers because the reference offset is far outside the loop
bandwidth. However, any reference feedthrough mechanism
that bypasses the loop may cause a problem. Feedthrough of
low levels of on-chip reference switching noise, through the
prescaler back to the VCO, can result in reference spur levels
as high as 80 dBc.
LOCK TIME
The PLL lock time divides into a number of settings. All of
these are modeled in the ADIsimPLL design tool. Faster lock
times than those detailed in this data sheet are possible; contact
your local Analog Devices, Inc., sales representative for more
information.
Rev. 0 | Page 31 of 35
ADF4355
Data Sheet
APPLICATIONS INFORMATION
DIRECT CONVERSION MODULATOR
51
REFIO
51
IOUTA
MODULATED
DIGITAL
DATA
AD9761
LOW-PASS
FILTER
IOUTB
TxDAC
QOUTA
LOW-PASS
FILTER
QOUTB
FSADJ
51
51
2k
FREF IN
FREF IN
VDD
1nF 1nF
100nF
100nF
LOCK
DETECT
25
30
CREG1 MUXOUT
17
10
26
32
5
4
27
6
16
VVCO VP AV DD DVDD AV DD CE PDB RF VRF CREG2
RFOUTB+ 14
1nF 1nF
RFOUTB 15
28 REF INB
IBBN
VOUT
7.5nH
1 CLK
7.5nH
1nF
2 DATA
RFOUTA+ 11
ADF4355
3 LE
LOIN
1nF
VTUNE 20
4.7k
1500pF
CPGND SDGND AGND AGNDRF AGNDVCO VREGVCO
31
13
18
21
10pF
VREF
VBIAS
23
24
19
0.1F
10pF
LPF
33nF
QUADRATURE
PHASE
SPLITTER
RFOUT
DSOP
3.3k
CPOUT 7
22 RSET
LOIP
LPF
RFOUTA 12
ADL5375
IBBP
29 REF A
IN
QBBN
390pF
QBBP
1k
0.1F 10pF
0.1F
Rev. 0 | Page 32 of 35
12910-138
VVCO
Data Sheet
ADF4355
POWER SUPPLIES
For the 3.3 V supply pins, use one or two ADM7150 regulators.
Figure 45 shows the recommended connections.
CIN
1F
ON
OFF
CBYP
1F
EN
VOUT
ADM7150
VOUT = 3.3V
COUT
1F
100nF
REF
BYP
VREG
CREG
10F
25
30
CREG1 MUXOUT
17
REF_SENSE
GND
FREF IN
FREF IN
1nF 1nF
LOCK
DETECT
100nF
10
26
4
27
6
32
16
VVCO VP DVDD AVDD CE PDB RF VRF CREG2
29 REF INA
RFOUTB+ 14
1nF 1nF
RFOUTB 15
28 REF INB
7.5nH
VIN
CIN
1F
ON
OFF
CBYP
1F
EN
VOUT
ADM7150
REF
BYP
VREG
CREG
10F
REF_SENSE
GND
VOUT = 5.0V
COUT
1F
1 CLK
VIN = 6.0V
VOUT
7.5nH
1nF
2 DATA
RFOUTA+ 11
ADF4355
3 LE
RFOUTA 12
1nF
VTUNE 20
3.3k
CPOUT 7
22 RSET
4.7k
AVDD 5
CPGND SDGND AGND AGNDRF AGNDVCO VREGVCO
8
31
13
18
21
10pF
Rev. 0 | Page 33 of 35
VREF
19
33nF
390pF
1k
VBIAS
23
0.1F
1500pF
24
10pF
0.1F 10pF
0.1F
12910-050
VIN = 6.0V
ADF4355
Data Sheet
OUTPUT MATCHING
The low frequency output can simply be ac-coupled to the next
circuit, if desired; however, if higher output power is required,
use a pull-up inductor to increase the output power level.
VRF
7.5nH
50
12910-051
100pF
RFOUTA+
Rev. 0 | Page 34 of 35
Data Sheet
ADF4355
OUTLINE DIMENSIONS
0.30
0.25
0.18
32
25
24
0.50
BSC
*3.75
3.60 SQ
3.55
EXPOSED
PAD
17
TOP VIEW
0.80
0.75
0.70
0.50
0.40
0.30
8
16
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
PIN 1
INDICATOR
BOTTOM VIEW
0.25 MIN
08-16-2010-B
PIN 1
INDICATOR
5.10
5.00 SQ
4.90
ORDERING GUIDE
Model1
ADF4355BCPZ
ADF4355BCPZ-RL7
EV-ADF4355SD1Z
1
Temperature Range
40C to +85C
40C to +85C
Package Description
32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Evaluation Board
Rev. 0 | Page 35 of 35
Package Option
CP-32-12
CP-32-12