Lecture Notes

Power MOSFETs
Outline
Construction of power MOSFETs
Physical operations of MOSFETs
Power MOSFET switching Characteristics
Factors limiting operating specfications of MOSFETs
COOLMOS
PSPICE and other simulation models for MOSFETs

Copyright by John Wiley & Sons 2003

MOSFETs - 1

Multi-cell Vertical Diffused Power MOSFET (VDMOS)

source
conductor

contact to source
diffusion

field
oxide

gate
oxide

+
P

+
P

gate
width

Ngate
conductor

N+

Copyright by John Wiley & Sons 2003

MOSFETs - 2

Important Structural Features of VDMOS

source

body-source
short

gate

conductor
field
gate

N+

N+
P (body)
N(drift

region)

oxide

oxide

N+

N+
P (body)
i

parasitic
BJT

channel
length

integral
diode

N+
drain

1. Parasitic BJT. Held in cutoff by body-source short

2. Integral anti-parallel diode. Formed from parasitic BJT.
3. Extension of gate metallization over drain drift region. Field plate and accumulation
layer functions.
4. Division of source into many small areas connected electrically in parallel.
Maximizes gate width-to-channel length ratio in order to increase gain.
5. Lightly doped drain drift region. Determines blocking voltage rating.
Copyright by John Wiley & Sons 2003

1.3x10^17
Breakdown Voltage= __________________
Drift Region Doping

MOSFETs - 3

Alternative Power MOSFET Geometries

Source
boddy-source short
Oxide
N+
P
Parasitic BJT

Gate
conductor

N+
Channel
P
length

N-

Integral
diode

ID

Trench-gate MOSFET
Newest geometry. Lowest
on-state resistance.

N+

Drain
gate

oxide

gate

source

N+

N+

N
i
N+

drain

V-groove MOSFET.
First practical power
MOSFET.
Higher on-state
resistance.

Copyright by John Wiley & Sons 2003

MOSFETs - 4

MOSFET I-V Characteristics and Circuit Symbols

i

[v
GS

ohmic

GS(th)

DS

i
V

GS5

active
V

actual

GS4

VG S 3

linearized

GS2

V
GS1

GS

<V

v
GS(th)

BV
DSS

v
GS

V
GS(th)

DS

G
G
N-channel
MOSFET

P-channel
MOSFET

Copyright by John Wiley & Sons 2003

MOSFETs - 5

The Field Effect - Basis of MOSFET Operation

VG G 1

SiO
2

V
GG3

SiO
2

+ +

+ +

+
ionized
depletion layer
acceptors
boundary

VG G 2

SiO
2

+ +

+ +

free

electrons

+ +

+ + + +

+ +

inversion layer
with free electrons

N
+

depletion layer
ionized
boundary
acceptors

ionized
acceptors

+ +

depletion layer boundary

Val ue deter mi ned by sever al factor s

1. Type of mater i al used for gate conductor
2. Dopi ng densi ty of body r egi on di r ectl y
beneath gate
3. I mpur i ti es/bound char ges i n ox i de
eox
4. Ox i de capaci tance per uni t ar ea Cox =
t ox
t ox = ox i de thi ck ness

Thr eshol d Vol tage V GS(th)

Adjust thr eshol d vol tage dur i ng devi ce

fabr i cati on vi a an i on i mpl antati on of
V GS wher e str ong i nv er si on l ayer has for med.
i mpur i ti es i nto body r egi on just beneath
Typi cal v al ues 2- 5 v ol ts i n power MOSFETs
gate ox i de.

Copyright by John Wiley & Sons 2003

MOSFETs - 6

Drift Velocity Saturation

electron
drift velocity

Mobility also decreases because large

values of VGS increase free electron

8 x 1 06
cm/sec

density.

1.5x10

At larger carrier densities, free carriers

collide with each other (carrier-carrier
scattering) more often than with lattice and
mobility decreases as a result.

electric
field

V/cm

In MOSFET channel, J = q n n E
= q n v n ; velocity v n = n E

Mobilty decreases, especially via carriercarrier scattering leead to linear transfer

curve in power devices instead of square
law transfer curve of logic level MOSFETs.

Velocity saturation means that the

mobility n inversely proportional to
electric field E.
Copyright by John Wiley & Sons 2003

MOSFETs - 7

Channel-to-Source Voltage Drop

VGS = VGG = Vox + VCS(x) ;

V

GG

V
DD1

Vo x(x)
N

VCS(x) = ID1RCS(x)

inversion

V (x)
CS
x

D1

Larger x value corresponds be being

closer to the drain and to a smaller
Vox .

depletion

Smaller Vox corresponds to a smaller

N
N+

channel thickness. Hence reduction in

channel thickness as drain is
approached from the source.

Copyright by John Wiley & Sons 2003

MOSFETs - 8

Channel Pinch-off at Large Drain Current

+
V

V D D 2+

D2

avoi ded.

Vo x(x)

GG

Appar ent di l emma of

channel di sappear i ng at
dr ai n end for l ar ge I D

1. Lar ge el ectr i c fi el d at dr ai n
end or i ented par al l el to
dr ai n cur r ent fl ow. Ar i ses
fr om l ar ge cur r ent fl ow i n
channel constr i cti on at
dr ai n.

inversion

V (x)
CS

depletion

velocity
saturation
region

P
N

N+

2. Thi s el ectr i c fi el d tak es

over mai ntenance of
mi ni mum i nver si on l ayer
thi ck ness at dr ai n end.

I D2 > I D1 so V CS2(x ) > V CS1(x ) and thus channel

nar r ower at an gi ven poi nt.

Lar ger gate- sour ce bi as

V GG postpones fl atteni ng

Total channel r esi stance fr om dr ai n to sour ce

i ncr easi ng and cur ve of I D vs V DS for a fi x ed V GS

of I D vs V DS unti l l ar ger
val ues of dr ai n cur r ent ar e
r eached.

fl attens out.
Copyright by John Wiley & Sons 2003

MOSFETs - 9

MOSFET Switching Models for Buck Converter

Vd

Io
D

DS(on)

RG

V
GG

Buck converter using power MOSFET.

gs

MOSFET equivalent circuit valid for

on-state (triode) region operation.

D
C

gd

gd
I

G
C

= f(V
)
GS
D

gs
S

MOSFET equivalent circuit valid for offstate (cutoff) and active region operation.

Copyright by John Wiley & Sons 2003

MOSFETs - 10

MOSFET Capacitances Determining Switching Speed

g at e

source

C gs
N

+
C

N+

gd

gd2

idealization

gd

Cd s
actual

N
C
drain-body
depletion layer

N+

gd1
v

drain

GS

= v

DS

200 V

DS

Gate-source capacitance Cgs approximately

constant and independent of applied voltages.
Gate-drain capacitance Cgd varies with applied
voltage. Variation due to growth of depletion layer
thickness until inversion layer is formed.
Copyright by John Wiley & Sons 2003
MOSFETs - 11

Internal Capacitances Vs Spec Sheet Capacitances

MOSFET internal capacitances

Reverse transfer or feedback capacitance

C

C gd
G

bridge

D
C gs

+V b

Cd s

C gd

Bridge balanced (Vb=0) Cbridge = Cgd = C rss

Input capacitance
G

Output capacitance
G

C iss
S

C iss = C gs + C gd

Copyright by John Wiley & Sons 2003

C oss
S

C oss = C gd + C d s
MOSFETs - 12

Turn-on Equivalent Circuits for MOSFET Buck Converter

V

Equi val ent ci r cui t

dur i ng td(on).

in

D
F

I o
C

+
V

GG

D
F

Equi val ent ci r cui t

dur i ng tfv1.

I o

DC

C gd1

Vi n

Equivalent cir cuit

dur ing tr i .

C gd1

+
V

gs

GG

in

R
Cg d 1

+
V

GG

GG

gs

Vi n

Equivalent cir cuit

dur ing tfv2.

I o

DC

I o

DS(on)

G
C

gs

C gd2

Copyright by John Wiley & Sons 2003

MOSFETs - 13

MOSFET-based Buck Converter Turn-on Waveforms

V

GG+

= R

(C
+ C
)
gs
G gd1
v

V
G S , Io
V

= R

GS

(t)

(C
+ C
)
gs
gd2

GS(th)
i

Charge on C

V in

gs

Charge on C
gd

+ Cg d

Free-wheeling diode
assumed to be ideal.
(no reverse recovery
i (t)
D
current).

fv2

(t)

(t)
DS

Io

t
d(on)

ri

t fv1

t
DS(on)

Copyright by John Wiley & Sons 2003

MOSFETs - 14

Turn-on Gate Charge Characteristic

Vgs,on
I
V + D1
t
g
mo

Vgs

V
d

V
V
d1 d2
V

I
Cgd

d3

Specified I

on

+
Vgs
-

D1

p
Vgs

T1

Vd

ds

V + I /gm
t
D1
t
V
gs,on

Vgs,off
I
d


Cgd(Vds)Vds dVds

+
V
ds
-

(V - V )
t
m gs

V
t

Vds,on

D1

V
ds

Vgs,on

[Cgs(Vgs)+Cgd(Vgs)]VgsdVgs

QT = Qon + Qp +

Q gate

(Vt+ID1/gm)

Qon =
[Cgs(Vgs)+Cgd(Vgs)]VgsdVgs
Vgs,off
Qp =

C
gs

D1

(Vt+ID1/gm)

V
ds,on

V
d

Copyright by John Wiley & Sons 2003

MOSFETs - 15

Turn-on Waveforms with Non-ideal Free-wheeling Diode

i

Io

Vi n

(t)

Io + I rr

I rr

I rr

i
t rr

(t)

GS,I

Cgs

Equivalent circuit for

estimating effect of freewheeling diode reverse
recovery.

o
t

Vin

GG

V
GS(th)

+
V

Io

ri

C gd1

(t)
DS
t

Copyright by John Wiley & Sons 2003

MOSFETs - 16

MOSFET-based Buck Converter Turn-off Waveforms

GS
V

t 2=

(t)

GG

R (C
+ C )
gs
G gd2

t1=
V

GS,I
o

R (C
+ C )
gs
G gd1
GS(th)

t
i

(t)

Essentially the
inver se of the tur n- on
pr ocess.

d(off)
v

Assume ideal fr eew heeling diode.

(t)
DS

(t)
V

I o

in

t
t

t rv1

rv2

t fi

Model quanitatively
using the same
equivalent cir cuits as
for tur n- on. Simply
use cor r ect dr iving
voltages and initial
conditions

Copyright by John Wiley & Sons 2003

MOSFETs - 17

dV/dt Limits to Prevent Parasitic BJT Turn-on

g at e

source

N+

Cg d

parasitic
BJT

Cg d

N
N

drain

Large positive Cgd

dVDS

dt
could turn on parasitic BJT.

D
L+
D

F+

T+

I o

T-

Turn-on of T+ and reverse recovery of Df- will

dv DS
in bridge circuit.
produce large positive Cgd
dt
Parasitic BJT in T- likely to have been in reverse
active mode when Df- was carrying current. Thus

L-

DF -

stored charge already in base which will increase

dv DS
is
likeyhood of BJT turn-on when positive Cgd
dt
generated.

Copyright by John Wiley & Sons 2003

MOSFETs - 18

Maximum Gate-Source Voltage

V GS(max) = maxi mum per mi ssi bl e gatesour ce vol tage.
I f V GS >V GS(max) r uptur e of gate oxi de by
l ar ge el ectr i c fi el ds possi bl e.
EBD(oxi de) 5- 10 mi l l i on V/cm
Gate oxi de ty pi cal l y 1000 anstr oms thi ck
V GS(max) < [5x106] [10- 5] = 50 V
Ty pi cal V GS(max) 20 - 30 V
Stati c char ge on gate conductor can r uptur e
gate oxi de
Handl e MOSFETs w i th car e (gr ound
y our sel f befor e handl i ng devi ce)
P l ace anti - par al l el connected Zener di odes
betw een gate and sour ce as a pr otecti ve
measur e

Copyright by John Wiley & Sons 2003

MOSFETs - 19

MOSFET Breakdown Voltage

depletion layer boundary
without field plate
action of gate electrode

depletion layer boundary

with field plate action
of gate electrode

BVDSS = drain-source breakdown

voltage with VGS = 0

2. Appropriate length of drain drift region

Caused by avalanche breakdown of

drain-body junction

3. Field plate action of gate conductor

overlap of drain region

Achieve large values by

1. Avoidance of drain-source reachthrough by heavy doping of body
and light doping of drain drift region

4. Prevent turn-on of parasitic BJT with

body-source short (otherwise BVDSS
= BVCEO instead of BVCBO)

Copyright by John Wiley & Sons 2003

MOSFETs - 20

MOSFET On-state Losses

gate

source

channel
resistance

accumulation
layer
resistance

N+
P
P
I

source region
resistance

drift region
resistance

drain region
resistance

+
drain

rDS(on) dominated by drain drift resistance

for BVDSS > few 100 V

On-state power dissipation Pon =

Io2 rDS(on)

Vd
rDS(on) =

ID

Large VGS minimizes accumulation

layer resistance and channel
resistance

3x10-7

BVDSS2
A

rDS(on) increases as temperature increases.

Due to decrease in carrier mobility with
increasing temperature.

Copyright by John Wiley & Sons 2003

MOSFETs - 21

Paralleling of MOSFETs
D

MOSFETs can be easily

paralleled because of
positive temperature
coefficient of rDS(on).

Rd
Q
1
G

Positive temperature coefficient leads to thermal

stabilization effect.
If rDS(on)1 > rDS(on)2 then more current and thus
higher power dissipation in Q2.
Temperature of Q2 thus increases more than
temperature of Q1 and rDS(on) values become
equalized.
Copyright by John Wiley & Sons 2003
MOSFETs - 22

MOSFET Safe Operating Area (SOA)

log ( i

No distinction betw een

FBSOA and RBSOA. SOA
is squar e.

DM
10

-5

sec

10 - 4 sec

FB = for w ar d bias.
V GS 0.

Tj , m a x
10

-3

sec

RB = r ever se bias.
V GS 0.

DC

BV

No second br eakdow n.

DSS
log ( v

DS

Copyright by John Wiley & Sons 2003

MOSFETs - 23

Structural Comparison: VDMOS Versus COOLMOS

source

N+

N+

N+

+
P

gate
cond

+
P

N+

Conventional
vertically oriented
power MOSFET

N-

N+
drain

source

N+

P
b

N+

gate
cond

N+

N+
b
P

N
b

N+

COOLMOS structure
(composite buffer structure,
super-junction MOSFET,
super multi-resurf
MOSFET)
Vertical P and N regions of
width b doped at same
density (Na = Nd)

drain

Copyright by John Wiley & Sons 2003

MOSFETs - 24

COOLMOS Operation in Blocking State

source
gate
cond

N+

N+

N+

COOLMOS structure partially

depleted.

N+
b

Arrows indicate direction of

depletion layer growth as device
turns off.

V
1

Note n-type drift region and

adjacent p-type stripes deplete
uniformly along entire vertical
length.

+
N+
drain

source
gate
cond

N+

N+

N+

N
Ec

Ec

COOLMOS structure at edge

of full depletion with applied
voltage Vc. Depletion layer
reaches to middle of vertical P
and N regions at b/2.

N+
b

Using step junction formalism,

Vc = (q b2 Nd)/(4 e) = b Ec,max/2

Vc
+

N+

Keep Ec,max EBD/2. Thus

Nd ( e EBD)/(q b)

drain

Copyright by John Wiley & Sons 2003

MOSFETs - 25

COOLMOS Operation in Blocking State (cont.)

source
gate
cond

N+

N+

N+
P

b
Ev

Ev

N+
b

Ev

P
Ec

Ec

N+
drain

V > Vc

For applied voltages V > Vc, vertically oriented electric field Ev begins to grow in depletion region.
Ev spatially uniform since space charge compensated for by Ec. Ev V/W for V >> Vc.
Doping level Nd in n-type drift region can be much greater than in drift region of conventional
VDMOS drift region of similar BVBD capability.
At breakdown Ev = EBD 300 kV/cm ; V = BVBD = EBDW
Copyright by John Wiley & Sons 2003
MOSFETs - 26

COOLMOS Operation in ON-State

source
gate
cond

N+

N+

N+

Ro n

On-state specific resistance ARon [-cm2]

much less than comparable VDMOS
because of higher drift region doping.

N+
b

V1

COOLMOS conduction losses much

less than comparable VDMOS.

N+
drain

ID

Ron A = W/(q nNd) ; Recall that Nd = (e EBD)/(q b)

Breakdown voltage requirements set W = BVBD/ EBD.

Substituting for W and Nd yields Ron A = (b BVBD)/(e n EBD2)
Copyright by John Wiley & Sons 2003
MOSFETs - 27

Ron A Comparison: VDMOS versus COOLMOS

COOLMOS at BVBD = 1000 V. Assume b 10 m. Use EBD = 300 kV/cm.
Ron A = (10-3 cm) (1000 V)/[ (9x10-14 F/cm)(12)(1500 cm2 -V-sec)(300 kV/cm)2]
Ron A = 0.014 -cm . Corresponds to Nd = 4x1015 cm-3
Typical VDMOS, Ron A = 3x10-7 (BVBD)2
Ron A = 3x10-7 (1000)2 = 0.3 -cm ; Corresponding Nd= 1014 cm3
Ratio COOLMOS to VDMOS specific resistance = 0.007/0.3 = 0.023 or approximately 1/40
At BVBD = 600 V, ratio = 1/26.
Experimentally at BVBD = 600 V, ratio is 1/5.
For more complete analysis see: Antonio G.M. Strollo and Ettore Napoli, Optimal ON-Resistance
Versus Breakdown Voltage Tradeoff in Superjunction Power Device: A Novel Analytical Model, IEEE
Trans. On Electron Devices,Vol. 48, No. 9, pp 2161-2167, (Sept., 2001)

Copyright by John Wiley & Sons 2003

MOSFETs - 28

COOLMOS Switching Behavior

Larger blocking voltages Vds > depletion
voltage Vc, COOLMOS has smaller Cgs, Cgd,
and Cds than comparable (same Ron and
BVDSS) VDMOS.

MOSFET witching waveforms for clamped inductive load.

v (t)
GS

Small blocking voltages Vds < depletion

voltage Vc, COOLMOS has larger Cgs, Cgd,
and Cds than comparable (same Ron and
BVDSS) VDMOS.

V GS,Io
V

GS(th)
t

Effect on COOLMOS switching times

relative to VDMOS switching times.
v (t)
DS

V
DS(on)

V
d

t
t

d(on)

(t)

t r i t fv1 t
fv2

d(off)

t rv1

tfi

Io

rv2

Turn-on delay time - shorter

Current rise time - shorter

Voltage fall time1 - shorter

Voltage fall time2 - longer

Turn-off delay time - longer

Voltage rise time1 - longer

Voltage rise time2 - shorter

Current fall time - shorter

Copyright by John Wiley & Sons 2003

MOSFETs - 29

PSPICE Built-in MOSFET Model

Circuit components
Drain
RD

Cgb

RG, RDS, RS, RB, and RD = parasitic

ohmic resistances

Cgs Cgd, and Cgb = constant voltageindependent capacitors

Cbs and Cbd = nonlinear voltagedependent capacitors (depletion layer

capacitances)

Idrain = f(Vgs, Vds) accounts for dc

characteristics of MOSFET

Model developed for lateral (signal level)

MOSFETs

Cbd

Cgd

RB

RG

Idrain

RDS

Bulk

Gate

Cgs

Cbs

RS
Source

Copyright by John Wiley & Sons 2003

MOSFETs - 30

Lateral (Signal level) MOSFET

Body-source short

Cgs

Cgd

Body-source short keeps Cbs constant.

S
N+

N+

C bg

Body-source short puts Cbd between drain and

source.

P
C bd

C bs

Source-body
depletion layer

Variations in drain-source voltage relatively

small, so changes in Cbd also relatively small.

Drain-body
depletion layer

Capacitances relatively independent of terminal

voltages

Cgs, Cbg, Cgd due to electrostatic

capacitance of gate oxide. Independent
of applied voltage

Consequently PSPICE MOSFET model has

voltage-independent capacitances.

Cbs and Cbd due to depletion layers.

Capacitance varies with junction voltage.
Copyright by John Wiley & Sons 2003

MOSFETs - 31

Vertical Power MOSFET

Bodysource
short

Cbs

gate

source
Cg s

Cbg

N+

Cg d

N+
P

Cb d

N
N+
drain

Drain-drift region and large drain-source

voltage variations cause large variations in
drain-body depletion layer thickness
Large changes in Cgd with changes in drain-source
voltage. 10 to 100:1 changes in Cgd measured in high
voltage MOSFETs.

drain-bodydepletion layer

MOSFET circuit simulation

models must take this variation
into account.

Moderate changes in Cgb and Cbs.

Copyright by John Wiley & Sons 2003
MOSFETs - 32

Inadequacies of PSPICE MOSFET Model

4
MTP3055E

C gd

= 0

GS

Cgs and Cgd in PSPICE model are

constant independent of terminal voltages

[nF]
SPICE model

In vertical power MOSFETs, Cgd varies

substantially with terminal voltages.

Motorola subcircuit model

0

0V

10V

V
DS

20V

30V

60V
MTP3055E V
DS

Comparison of transient response of drainsource voltage using PSPICE model and

an improved subcircuit model. Both
models used in same step-down converter
circuit.

40V
Motorola
subcircuit
model

20V
0V

0s

100ns

SPICE
model

Time

200ns

300ns

Copyright by John Wiley & Sons 2003

MOSFETs - 33

Example of an Improved MOSFET Model

Developed by Motorola for their TMOS line of
power MOSFETs

LDRAIN

M1 uses built-in PSPICE models to describe

dc MOSFET characteristics. Space charge
capacitances of intrinsic model set to zero.

RDRAIN1

Space charge capacitance of DGD models

voltage-dependent gate-drain capacitance.

Dr a in
DGD
CGDMAX
RGDMAX

RDRAIN2

LGATE RGATE

DBODY
M1

Gate

CGS

RDBODY

CGDMAX insures that gate-drain capacitance

does not get unrealistically large at very low
drain voltages.
DBODY models built-in anti-parallel diode
inherent in the MOSFET structure.

LSOURCE

CGS models gate-source capacitance of

MOSFET. Voltage dependence of this
capacitance ignored in this model.

Source

Resistances and inductances model parasitic

components due to packaging.

RSOURCE

Many other models described in literature. Too

numerous to list here.
Copyright by John Wiley & Sons 2003
MOSFETs - 34

Another Improved MOSFET Simulation Model

Drain
L

V offset

LG

M3

M2

Gate

M2 and M3 are SPICE level 2

MOSFETs used along with Voffset to
model voltage dependent behavior of
Cgd.

+
-

Dsub

Q
1
M1

G
RS
LS
Source

LG, RG, LS RS, LD, RD - parasitic

inductances and resistances

JFET Q1 and Rd account for voltage drop

in N- drain drift region
Dsub is built-in SPICE diode model used
to account for parasitic anti-parallel diode
in MOSFET structure.
Reference - "An Accurate Model for
Power DMOSFETs Including Interelectrode Capacitances", Robert Scott,
Gerhard A. Frantz, and Jennifer L.
Johnson, IEEE Trans. on Power
Electronics, Vol. 6, No. 2, pp. 192-198,
(April, 1991)

M1= intrinsic SPICE level 2 MOSFET with no

parasitic resistances or capacitances.
Copyright by John Wiley & Sons 2003
MOSFETs - 35