Mysc02 402

0.
35um CMOS Process Parameters
MYSC02-402
Rev 4.0
MIMOS Authorized Recipient Only
Date: 24/02/2011
Page 1 of 14
0.35um CMOS Process Parameters

MYSC02-402
Revision 4.0
Revision Author
Department
Document Location
Approval Committee
Confidentiality Status
Archive Requirement
Muhamad Amri Ismail

Wafer Fab Design Library
Department Document Center
Author Immediate Superior
Not Applicable
MYSC02-402
Rev 4.0
Date: 24/02/2011
Page 2 of 14
Revision History
Rev No
Date
Change History
Originator
1.0
16/01/2007 First Issue
Fairuz Niza
Abu Bakar
2.0
15/09/2008
Fairuz Niza
Abu Bakar
3.0
11/03/2009
4.0
New template
New template MIMOS Wafer fab 2009

New reviews and approval records due to
organizational changes.
24/02/2011 Updated silicon data
MIMOS INTERNAL USE ONLY
o
o
Robiah Hussin
Muhamad Amri
Ismail
Page 2 of 14
MYSC02-402
Rev 4.0
Date: 24/02/2011
Page 3 of 14
Review and Approval Records

Document Originator
Department
Name
Title
Muhamad Amri Ismail
Senior Engineer
Date
Signatory
Wafer Fab Design

Library
Document Review
Name
Title
Department
Sharifah Kamariah Wan

Sabli
Staff Engineer
Process and
Process Integration
Khairil Mazwan Mohd

Zaini
Senior Engineer Process Integration
Date
Signatory
Date
Signatory
Document Approval
Name
Title
Department
Iskhandar Md Nasir
Senior Staff
Engineer
Design Library
Page 3 of 14
MYSC02-402
Rev 4.0
Date: 24/02/2011
Page 4 of 14
TABLE OF CONTENTS
PAGE
1.0 INTRODUCTION ................................................................................................. 5

1.1 Confidential Proclamation ............................................................................. 5
2.0 GENERAL 6
2.1 Wafer Cross-Section6
3.0 PROCESS CONTROL PARAMETERS ............................................................... 7
3.1 Structural and Geometrical Parameters ........................................................ 7
3.1.1 Junction ................................................................................................. 7
3.1.2 Dielectric Thickness ............................................................................... 7
3.1.3 Interconnect Thickness .......................................................................... 7
3.2 MOS Electrical Parameters........................................................................... 8
3.2.1Short Channel NMOS (W=20um L=0.35um) ........................................... 8
3.2.2Short Channel PMOS (W=20um L=0.35um) ........................................... 8
3.2.3 Breakdown Voltage ................................................................................ 8
3.3 Technology Parameters for Typical Case ..................................................... 9
3.3.1 Conductor layers .................................................................................... 9
3.3.2 Dielectric layers...................................................................................... 9
3.3.3 Interconnection Line Line Capacitance ................................................ 9
3.3.4 Typical Interconnection Capacitance Table .......................................... 11
3.3.5 1mm Wiring Capacitance ..................................................................... 12
3.3.6 Sheet Resistance ................................................................................. 12
3.3.7 PIP Capacitor and Poly Resistor Module .............................................. 13
3.3.8 Contact Resistance .............................................................................. 13
3.3.9 Via Resistance ..................................................................................... 13
4.0 SUPPORT.. ......................................................................................... 14
Page 4 of 14
MYSC02-402
Rev 4.0
Date: 24/02/2011
Page 5 of 14
1.0 INTRODUCTION
This manual contains information on process parameters of 0.35um (Double Poly Triple Metal)
AMS CMOS process for 3.3V application. It is intended to be reference guide for users. The
information in this manual are intended for those who want to design and layout a circuit based on
MIMOS 0.35um AMS CMOS 3.3V process.
1.1 Confidential Proclamation
This document contains MIMOS confidential information and is intended for MIMOS
authorized recipient only. No part of this document may be reproduced or transmitted in
any form or by any means without the prior written permission from MIMOS.
Page 5 of 14
MYSC02-402
Rev 4.0
Date: 24/02/2011
Page 6 of 14
2.0 GENERAL
2.1 Wafer Cross-Section
Passivation
Pad
opening
M3
Via2
capacitor
resist
M2
Via1
M1
SiON
WSix
PMOS
a-Si
200
SiO2SiO2
p+
SiON
WSix
a-Si
N-well
Si substrate
Si substrate
NMOS
SiON
WSix
Poly1
LOCOS 3600
contact
p+
a-Si
LOCOS
n+
P-well
n+
Page 6 of 14
MYSC02-402
Rev 4.0
Date: 24/02/2011
Page 7 of 14
3.0 PROCESS CONTROL PARAMETERS
3.1 Structural and Geometrical Parameters

Parameter
Structure
Min.
Typ.
Max.
Unit
Substrate
P(100)
7.5
/cm
N-well (Junction Depth)
1.00
um
P-well (Junction Depth)
0.90
um
N+ (S / D)
0.11
um
P+ (S / D)
0.18
um
3.1.1 Junction
3.1.2 Dielectric Thickness

Gate Oxide
SiO2
nm
Poly-Si to Substrate
LOCOS
360
nm
M1 to Polygate
SiO2 @ USG Film @ BPSG
740
nm
M1 to Active Area
SiO2 @ Poly-Si Oxide
750
nm
M2 to M1
CVD SiOx @ O3-TEOS @ SOG

@ PECVD Oxide
1000
nm
M3 to M2
CVD SiOx @ O3-TEOS @ SOG

@ PECVD Oxide
760
nm
Passivation
PECVD oxide and PECVD Nitride
1000
nm
3.1.3 Interconnect Thickness

Polygate
Tungsten Polycide
285
nm
Metal-1
Ti/TiN/AlSiCu/TiN
624
nm
Metal-2
Ti/TiN/AlSiCu/TiN
612
nm
Metal-3
Ti/TiN/AlSiCu/TiN
877
nm
Page 7 of 14
MYSC02-402
Rev 4.0
Date: 24/02/2011
Page 8 of 14
3.2 MOS Electrical Parameters
3.2.1 Short Channel NMOS (W=20um L=0.35um)

Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
NMOS Threshold
Voltage
VTN
Vg at Vd = 0.1V, Vsub =
0V
0.59
NMOS Leakage
Current
ILTN
Id at Vd = 3.0V, Vg =
0V, Vsub = 0V
-1.0
pA/um
NMOS Saturation
Current
IDSN
Id at Vd = 3.3 V, Vg =
3.3V, Vsub = 0V
540
uA/um
3.2.2 Short Channel PMOS (W=20um L=0.35um)

Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
-0.72
PMOS Threshold
Voltage
VTP
Vg at Vd = -0.1V, Vsub =
0V
PMOS Leakage
Current
ILTP
Id at Vd = -3.0V, Vg =
0V, Vsub = 0V
-2
-1.2
pA/um
PMOS Saturation
Current
IDSP
Id at Vd = -3.3 V, Vg = 3.3V, Vsub = 0V
-240
uA/um
3.2.3 Breakdown Voltage

Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Punchthrough Voltage
(Poly Gate NMOS)
BVDGN
@ Ids = 1.0uA
7.8
7.85
7.9
Punchthrough Voltage
(Poly Gate PMOS)
BVDGP
@ Ids = -1.0uA
-9.4
-9.21
-8.3
NMOS S/D Breakdown

Voltage
BVDN
@ Ids = 1.0uA
PMOS S/D Breakdown

Voltage
BVDP
@ Ids = -1.0uA
-8
Page 8 of 14
MYSC02-402
Rev 4.0
Date: 24/02/2011
Page 9 of 14
3.3 Technology Parameters for Typical Case
3.3.1 Conductor layers

Conductor
Typical
Min. width
Min. space
Distance between
conductor and substrate
under FOX
Thickness
PO
115 m
0.65 m
0.50 m
0.357 m
PO2
285 m
0.35 m
0.45 m
0.357 m
M1
624 m
0.50 m
0.45 m
0.771 m
M2
612 m
0.60 m
0.50 m
1.854 m
M3
877 m
0.60 m
0.50 m
2.384 m
3.3.2 Dielectric layers

Dielectric
Typical
%Var
Dielectric constant
Thickness
TOX
0.007 m
10%
3.90
LOCOS
0.380 m
10%
4.60
PMD
0.710 m
10%
4.50
ILD1
0.720 m
10%
5.52
ILD2
0.660 m
10%
4.09
PSV1
0.300 m
10%
4.50
PSV2
0.700 m
10%
7.50
Page 9 of 14
MYSC02-402
Rev 4.0
Date: 24/02/2011
Page 10 of 14
3.3.3 Interconnection Line Line Capacitance

The interconnect capacitance simulation results using Raphael field solver are listed in this section.
The simulation structure is: Structure A Conductor array above the infinite plate:
Notes:
1. The condition line is using the minimum width of design rule.
2. For structure A, the top layer is used as a conduction line layer and the bottom conduction
layer are used as the infinite plate.
Page 10 of 14
MYSC02-402
Rev 4.0
Date: 24/02/2011
Page 11 of 14
3.3.4 Typical Interconnection Capacitance Table
Structure
PO-FOX
PO2-FOX
PO2-PO
M1-FOX
M1-OD
M1-PO
M1-PO2
M2-FOX
M2-OD
M2-PO
M2-PO2
M2-M1
M3-FOX
M3-OD
M3-PO
M3-PO2
M3-M1
M3-M2
Width
Space
(um)
(fF/um)
Csum
Ccoupli
(fF/um)
(fF/um)
Cgnd
Cfringe
(fF/um)
(fF/um2)
0.65
0.65
0.35
0.35
0.35
0.35
0.50
0.50
0.50
0.50
0.50
0.50
0.50
0.50
0.60
0.60
0.60
0.60
0.60
0.60
0.60
0.60
0.60
0.60
0.60
0.60
0.60
0.60
0.60
0.60
0.60
0.60
0.60
0.60
0.60
0.60
0.50
2.5
0.45
2.50
0.45
2.50
0.45
2.50
0.45
2.50
0.45
2.50
0.45
2.50
0.50
2.50
0.50
2.50
0.50
2.50
0.50
2.50
0.50
2.50
0.50
2.50
0.50
2.50
0.50
2.50
0.50
2.50
0.50
2.50
0.50
2.50
1.26E-01
1.24E-01
1.82E-01
1.47E-01
5.78E-01
5.67E-01
2.74E-01
1.48E-01
2.98E-01
1.75E-01
2.62E-01
1.43E-01
2.73E-01
1.50E-01
2.33E-01
1.32E-01
2.23E-01
1.30E-01
1.99E-01
1.03E-01
2.02E-01
1.04E-01
2.00E-01
1.20E-01
3.18E-01
1.65E-01
3.07E-01
1.60E-01
1.60E-01
9.50E-02
2.68E-01
1.22E-01
2.68E-01
1.32E-01
2.73E-01
1.57E-01
9.87E-03
1.44E-03
4.76E-02
3.87E-03
2.98E-02
2.15E-03
1.08E-01
1.45E-02
1.12E-01
1.74E-02
1.03E-01
1.75E-02
1.08E-01
1.84E-02
9.16E-02
1.72E-02
8.56E-02
1.45E-02
8.30E-02
1.81E-02
8.40E-02
1.83E-02
7.41E-02
1.03E-02
1.35E-01
3.82E-02
1.29E-01
3.54E-02
6.41E-02
1.95E-02
1.19E-01
3.21E-02
1.14E-01
2.74E-02
1.06E-01
2.46E-02
1.06E-01
1.21E-01
8.65E-02
1.39E-01
5.19E-01
5.62E-01
5.77E-02
1.19E-01
7.37E-02
1.41E-01
5.51E-02
1.08E-01
5.69E-02
1.13E-01
5.01E-02
9.78E-02
5.22E-02
1.01E-01
3.34E-02
6.64E-02
3.38E-02
6.73E-02
5.20E-02
9.91E-02
4.86E-02
8.87E-02
4.85E-02
8.93E-02
3.18E-02
5.60E-02
2.97E-02
5.75E-02
4.00E-02
7.73E-02
6.10E-02
1.08E-02
1.79E-02
2.54E-02
2.33E-02
4.96E-02
7.50E-02
9.67E-05
1.40E-02
4.49E-02
1.88E-02
5.22E-02
1.44E-02
4.10E-02
1.49E-02
4.29E-02
1.27E-02
3.65E-02
1.27E-02
3.71E-02
8.79E-03
2.53E-02
8.88E-03
2.56E-02
1.20E-02
3.55E-02
1.47E-02
3.47E-02
1.43E-02
3.48E-02
9.86E-03
2.20E-02
8.76E-03
2.27E-02
1.12E-02
2.98E-02
1.63E-02
3.98E-02
1.08E-01
1.08E-01
1.14E-01
1.14E-01
1.05E00
1.05E00
5.95E-02
5.95E-02
7.23E-02
7.23E-02
5.25E-02
5.25E-02
5.41E-02
5.41E-02
4.13E-02
4.13E-02
4.45E-02
4.45E-02
2.64E-02
2.64E-02
2.67E-02
2.67E-02
4.66E-02
4.66E-02
3.21E-02
3.21E-02
3.30E-02
3.30E-02
2.02E-02
2.02E-02
2.03E-02
2.03E-02
2.95E-02
2.95E-02
4.75E-02
4.75E-02
(um)
Carea
Page 11 of 14
MYSC02-402
Rev 4.0
Date: 24/02/2011
Page 12 of 14
3.3.5 1mm Wiring Capacitance
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Wiring Capacity M1
Wire width,
W=0.5um
280
fF/mm
Wiring Capacity M2
Wire width,
W=0.6um
210
fF/mm
Wiring Capacity M3
Wire width,
W=0.6um
265
fF/mm
Min.
Typ.
Max.
Unit
3.3.6 Sheet Resistance
Parameter
Symbol
Condition
Sheet Resistance of
N-Well
RSQW
Supplied
Voltage = 3.3V
1600
/sqr
Sheet Resistance of
n+
RSQN
Supplied
Voltage = 3.3V
100
/sqr
Sheet Resistance of
p+
RSQP
Supplied
Voltage = 3.3V
215
/sqr
Sheet Resistance of
Poly Silicon Gate
RSQG
Supplied
Voltage = 3.3V
10
/sqr
Sheet Resistance of
Metal 1
RSQM1
0.100
/sqr
Sheet Resistance of
Metal 2
RSQM2
0.100
/sqr
Sheet Resistance of
Metal 3
RSQM3
0.050
/sqr
Page 12 of 14
MYSC02-402
Rev 4.0
Date: 24/02/2011
Page 13 of 14
3.3.7 PIP Capacitor and Poly Resistor Module
Parameter
Symbol
Condition
Min.
Typical
Max.
Unit
Sheet resistance
high doped poly
RSQ_PW
1150
/sqr
Sheet resistance
poly resistor
RSQ_P1
100
/sqr
Capacitance double
poly (ONO)
C_ONO
1.2
fF/um2
Breakdown voltage
ONO
BV_ONO
15
3.3.8 Contact Resistance
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Contact Resistance
n+ ACT
RCON
Dimensions = 0.4 x
0.4 um
55
/contact
Contact Resistance
p+ ACT
RCOP
Dimensions = 0.4 x
0.4 um
145
/contact
Contact Resistance
poly
RCOG
Dimensions = 0.4 x
0.4 um
6.4
/contact
Min.
Typ.
Max.
Unit
3.3.9 Via Resistance
Parameter
Symbol
Condition
Via 1 Resistance
RCOTH1
Dimensions = 0.5 x
0.5 um
4.2
/via
Via 2 Resistance
RCOTH2
Dimensions = 0.5 x
0.5 um
3.5
/via
Page 13 of 14
MYSC02-402
Rev 4.0
Date: 24/02/2011
Page 14 of 14
4.0 SUPPORT
For questions or information, please contact

Iskhandar Md Nasir (Senior Staff Engineer)
Tel: +60 3 8995 5000 ext 5149, +60 3 8657 9907 (DL)
Email: iskhand@mimos.my
Muhamad Amri Ismail (Senior Engineer)
Tel: +60 3 8995 5000 ext 5520
Email: amris@mimos.my
Wafer Fab Design Library
Mimos Berhad, Technology Park Malaysia, 57000 Kuala Lumpur, Malaysia
Tel: +603 8995 5000
Page 14 of 14

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0.

35um CMOS Process Parameters

MIMOS Authorized Recipient Only

0.35um CMOS Process Parameters

Muhamad Amri Ismail

0.35um CMOS Process Parameters

MIMOS Authorized Recipient Only

16/01/2007 First Issue

New template MIMOS Wafer fab 2009

MIMOS INTERNAL USE ONLY

0.35um CMOS Process Parameters

MIMOS Authorized Recipient Only

Review and Approval Records

Muhamad Amri Ismail

Wafer Fab Design

Sharifah Kamariah Wan

Khairil Mazwan Mohd

Senior Engineer Process Integration

MIMOS INTERNAL USE ONLY

0.35um CMOS Process Parameters

MIMOS Authorized Recipient Only

1.0 INTRODUCTION ................................................................................................. 5

MIMOS INTERNAL USE ONLY

0.35um CMOS Process Parameters

MIMOS Authorized Recipient Only

1.1 Confidential Proclamation

MIMOS INTERNAL USE ONLY

0.35um CMOS Process Parameters

MIMOS Authorized Recipient Only

2.1 Wafer Cross-Section

MIMOS INTERNAL USE ONLY

0.35um CMOS Process Parameters

MIMOS Authorized Recipient Only

3.0 PROCESS CONTROL PARAMETERS

3.1 Structural and Geometrical Parameters

N-well (Junction Depth)

P-well (Junction Depth)

3.1.2 Dielectric Thickness

SiO2 @ USG Film @ BPSG

SiO2 @ Poly-Si Oxide

CVD SiOx @ O3-TEOS @ SOG

CVD SiOx @ O3-TEOS @ SOG

PECVD oxide and PECVD Nitride

3.1.3 Interconnect Thickness

MIMOS INTERNAL USE ONLY

0.35um CMOS Process Parameters

MIMOS Authorized Recipient Only

3.2 MOS Electrical Parameters

3.2.1 Short Channel NMOS (W=20um L=0.35um)

3.2.2 Short Channel PMOS (W=20um L=0.35um)

Id at Vd = -3.3 V, Vg = 3.3V, Vsub = 0V

3.2.3 Breakdown Voltage

NMOS S/D Breakdown

PMOS S/D Breakdown

MIMOS INTERNAL USE ONLY

0.35um CMOS Process Parameters

MIMOS Authorized Recipient Only

3.3 Technology Parameters for Typical Case

3.3.1 Conductor layers

3.3.2 Dielectric layers

MIMOS INTERNAL USE ONLY

0.35um CMOS Process Parameters

MIMOS Authorized Recipient Only