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[Nov-14]

[EUREE-502A]

B.Tech. Degree Examination


Electrical & Electronics Engineering
V SEMESTER
LINEAR INTEGRATED CIRCUITS AND APPLICATIONS
(Effective from the admitted batch 201213)
Time: 3 Hours
Max.Marks: 60
---------------------------------------------------------------------------------------------------Instructions: Each Unit carries 12 marks.
Answer all units choosing one question from each unit.
All parts of the unit must be answered in one place only.
Figures in the right hand margin indicate marks allotted.
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UNIT-I
1. a) Analyze the dual input balanced output configuration of
differential amplifier using DC
b) What are the advantages of current mirror circuit? Explain its
operation
OR
2. a) Why frequency compensation is required or an op-amp and
explain frequency compensation technique using suitable
diagrams
b) Explain non-ideal DC characteristics of op-amp
c) A square wave of peak to peak amplitude of 500m V has to be
amplified to a peak to peak amplitude of 3V, with a rise time
of 4s or less. Can a IC741 be used? Explain

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UNIT-II
3. a) Design a circuit using op-amp to generate a output
V o =0.1V 1 -V 2 +10V 3 where V 1 ,V 2 ,V 3 are input voltages
b) Explain the working of a transconductance amplifier with
floating and grounded loads. Is there any limitation on the
size of the load when grounded
R

OR
4. a) Construct a half wave rectifier using op-amps and explain the
operation using relevant waveforms
b) Draw the circuit of an anti-log amplifier and support with
appropriate derivation
UNIT-III
5. a) What are the different applications of IC555 timer in astable
mode? Explain any one applications with circuit diagram and
waveforms
b) Draw the circuit of PLL as frequency multiplier and explain its
working
OR
6. a) With circuit diagram and wave forms explain monostable
operation of IC555 timer. Derive an equation for time delay
for this circuit
b) Design a square waveform generator of frequency 1khz and
duty cycle of 75% using 555 timer

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UNIT-IV
7. a) Explain the working of the weighted resistor digital to analog
converter and state the features
b) LSB of 9-bit DAC is represented by 19.6 Volts. If an input of
9 zero bits is represented by 0 volts.
i) Find the output of the DAC for an input of 10111 1011 and
00101 1011
ii) What is the full scale reading (FSR) of this DAC

OR
8. a) Draw the circuit diagram of a 6 bit inverted R-2R ladder DAC.
For V(1)=8V, what is the maximum output voltage? What is
the minimum voltage that can be resolved?
b) Explain the operation of dual slope ADC

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UNIT-V
9. a) Draw the circuit diagram of a second order low-pass Butterworth
filter and write the design steps of such filter
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b) Design a first order low-pass Butterworth filter with a cutoff
frequency of 3 kHz and passband gain of 3
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OR
10. a) What is an all pass filter? Show that the magnitude response
of the all pass filter is 1
b) Design a first order high pass filter at cutoff frequency of
500Hz. And pas band gain of 1

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[5/V S/114]