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module functioncall(a,b.out);
input a,b;
output out;
reg out;
function andcall;
input x,y;
andcall = x & y;
endfunction
always@(a or b)
begin
out = andcall(a,b);
end
endmodule
Counting number of 1's
module countbits;
initial
$display("The number of 1's = %d",count_bits(7));
if(a[0])
count_bits = count_bits +1;
a = a >>1;
end
end
endfunction
endmodule
Priority Encoder
Priority Encoder using FOr loop starting with lowest priority bit
module priority_low_high(a,p,f);
parameter N =8;
parameter log2N =3;
input [N-1:0] a;
output [log2N-1:0]p;
output f;
reg [log2N-1:0] p;
reg f;
function [log2N:0] priority
input [N-1:0] a;
reg f;
integer i;
begin
f =1'b0;
priority = {3'b0,f};
for(i=0;i<N;i=i+1)
if(a[i]
begin
f=1'b1;
priority ={i,f};
end
end
endfunction
always@(a)
begin
{p.f} =priority (a);
end
Task Example(always block)
module taskcall(a,b,out);
input a,b;
output out;
reg out;
task andcall;
input x,y;
output z;
reg z;
z <= x & y;
endtask
always@(a or b)
begin
andcall(a,b,out);
end
endmodule
Task Example (initial block)
module hellot;
initial
say_hello;
task say_hello;
$display("Hello Verilog Task");
endtask
endmodule
Task with input and output (initial block)
module taskio;
integer a,b,c,d;
initial begin
a=3;b=4;d=12;
add(c,a,b);
$display("Final value for c = %d",c);
end
task add;
input [31:0] in1;
output [31:0] out;
input [31:0] in2;
out = in1 + in2;
endtask
endmodule
increment(a);
$display("a=%d",a);
increment(a);
$display("a=%d",a);
a=5;
increment(a);
$display("a=%d",a);
end
task increment;
inout [2:0] x;
x = x+1;
end task
endmodule
count.total =0;
count;
count;
$display("total = %d",count.total);
end
task count;
integer total;
total =total +1;
endtask
endmodule
Simulator Output
#total = x
#total = 2
$display($time,"a=%d",a);
initial begin
#2 increment(b);
$display($time,"b = %d",b);
end
task incrment;
inout [2:0] x;
#10 x = x + 1;
endtask
endmodule
Multi Invoking of task
Simulation result
#10 a =6
#12 b=7
$display($time,"a=%d",a);
end
initial
begin
#2 increment(b);
$display($time,"b=%d",b);
end
task automatic increment;
inout [2:0] x;
#10 x = x+1;
endtask
endmodule
Simulation result
# 10 a=2
#12 b=6
Example 1
module register #(parameter SIZE =4)(input rst_a,clk,
input [SIZE-1:0] d,
output [SIZE-1:0] q);
always@(posedge clk,posedge rst_a)
if(rst_a)
q <= 0;
else
q<= d;
endmodule
Example 2
module register (clk,rst_a,d,q);
parameter SIZE =4;
input rst_a,clk;
input [SIZE-1:0] d;
output [SIZE-1:0] q;
always@(posedge clk,posedge rst_a)
if(rst_a)
q <= 0;
else
q<= d;
endmodule
defparameter statement
module register_pipeline(rst_a,clk,d,q);
input rst_a,clk;
input [15:0] d;
output [15:0] q;
wire [15:0] stage_1;
defparam s1.SIZE=16,s2.SIZE=32;
register s1(.q(stage_1),.d(d),.clk(clk),.rst_a(rst_a));
register s2(.q(q),.d(stage_1),.clk(clk),.rst_a(rst_a));
endmodule
Compiler Directive
`timescale 10ns/1ns
module cd_time;
reg set;
parameter d =1.55;
initial begin
#d set =0;
#d set =1;
end
endmodule
Example 1
`timescale 1ns/100ps
module test();
assign #10.1678 out =in;
endmodule
simulation output
out is delayed by 10.2ns from in.
endmodule
`timescale 10fs/1fs
module b_dat;
c_dat c1();
endmodule
`timescale 1ns/1ns
module c_dat;
endmodule
Simulation Result
Time scale of (a_dat.b1.c1) is 1ns/1ns
Example 4
`timescale 10ns/100ps
module timeformat;
reg in1;
not m1(o1,in1);
initial begin
$timeformat(-9,5,"ns",10);
in1 =0;
#8 in1 =1;
#10 $display("%t %b %b ", $realtime,in1,o1);
#10 $finish;
end
endmodule
Example5
`define A_R
module and_op(a,b,c);
output a;
input b,c;
`ifdef A_R
wire a = b & c;
`else
or a1(a,b,c);
`endif
endmodule
Example 6
`include "parameter.v"
Parameter.v
`define ADD
input [`N-1:0] b,
output [`N-1:0] c);
`ifdef ADD
assign c = a +b;
`else
assign c= a-b;
`endif
endmodule
Example 7
module nested_if_def(out);
output out;
`define wow
`define N 5
`define nest_one
`define else_nest
`define nest_two
`ifdef wow
initial $display("wow is defined");
`ifdef nest_one
initial $display("I am in nest_one");
`ifdef nest_two
initial $display ("I am in nest_two");
`else
initial $display("nest_two is not defined");
`endif
`else
initial $display("nest_one is not defined");
`endif
`else
initial $display("wow is not defined");
`ifdef else_net
initial $display("else_nest is defined");
`else
initial $display("else_nest is not defined");
`endif
`endif
endmodule
Example 8 Distributed delay in gate-level
`timescale 1ns/1ns
module delay_dis(out,a,b,c,d);
output out;
input a,b,c,d;
wire e,f;
or #4 g1(e,a,b);
or #6 g2(f,c,d);
or #3 g3(out,e,f);
endmodule
or g1(e,a,b);
or g2(f,c,d);
or #9 g3(out,e,f);
endmodule
or g1(e,a,b);
or g2(f,c,d);
or g3(out,e,f);
endmodule
Exampe 12 Full connection
module delay_Full(out,a,b,c,d);
output out;
input a,b,c,d;
wire e,f;
specify
(a,b *> out) =7;
(c,d *> out)= 9;
endspecify
or g1(e,a,b);
or g2(f,c,d);
or g3(out,e,f);
endmodule
Example 13 specparam
module specify_blk(out,a,b,c);
input a,b,c;
output out;
specify
specparam ta_out=5,tb_out =3,tc_out =2;
(a *>out) = ta_out;
(b *>out) = tb_out;
(c *>out) = tc_out;
endspecify
endmodule
endtable
endprimitive
table
//clock data q q +
0 1 : ? : 1;
0 0 : ? : 0;
1 ? : ? :-;//no change
endtable
endprimitive
module memory();
reg [7:0] my_memory[0:255];
initial begin
$readmemh("memory.txt",my_memory);
end
endmodule
"memory.txt" File
1
@55