Professional Documents
Culture Documents
High Performance
Flat Panel / CRT
VGA Controllers
Data Sheet
Revision 1.2
October 1995
CopyrightNotice
Copyright 1995, Chips and Technologies, Inc. ALL RIGHTS RESERVED.
This manual is copyrighted by Chips and Technologies, Inc. You may not reproduce,
transmit, transcribe, store in a retrieval system, or translate into any language or
computer language, in any form or by any means, electronic, mechanical, magnetic,
optical, chemical, manual, or otherwise, any part of this publication without the express
written permission of Chips and Technologies, Inc.
RestrictedRightsLegend
Use, duplication, or disclosure by the Government is subject to restrictions set forth in
subparagraph (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at
252.277-7013.
Trademark
Acknowledgement
CHIPS Logotype, CHIPSlink, CHIPSPort, ELEAT, LeAPSet, NEAT, NEATsx, PEAK,
PRINTGINE, SCAT, SuperMathDX, SuperState, and WINGINE are registered trademarks
of Chips and Technologies, Incorporated.
CHIPSet, Super Math, WinPC, and XRAM Video Cache are trademarks of Chips and
Technologies,Incorporated.
IBM AT, XT, PS/2, Micro Channel, Personal System/2, Enhanced Graphics Adapter,
Color Graphics Adapter, Video Graphics Adapter, IBM Color Display, and IBM
Monochrome Display are trademarks of International Business Machines Corporation.
Hercules is a trademark of Hercules Computer Technology.
MS-DOS and Windows are trademarks of Microsoft Corporation.
MultiSync is a trademark of Nippon Electric Company (NEC).
Brooktree and RAMDAC are trademarks of Brooktree Corporation.
Inmos is a trademark of Inmos Corporation.
TRI-STATE is a registered trademark of National Semiconductor Corporation.
VESA is a registered trademark of Video Electronics Standards Association.
VL-Bus is a trademark of Video Electronics Standards Association.
All other trademarks are the property of their respective holders.
Disclaimer
This document is provided for the general information of the customer. Chips and
Technologies, Inc., reserves the right to modify the information contained herein as
necessary and the customer should ensure that it has the most recent revision of the data
sheet. CHIPS makes no warranty for the use of its products and bears no responsibility
for any errors which may appear in this document. The customer should be on notice that
the field of personal computers is the subject of many patents held by different parties.
Customers should ensure that they take appropriate action so that their use of the products
does not infringe upon any patents. It is the policy of Chips and Technologies, Inc. to
respect the valid patent rights of third parties and not to infringe upon or assist others to
infringe upon such rights.
65540 / 545
High Performance
Flat Panel / CRT VGA Controller
n
n
n
n
n
n
n
n
n
n
BIOS
ROM
32-bit 386/486
CPU Direct or VL
Local Bus, PCI
Bus, or 16-bit ISA
System Bus
28
32
Address
Data
Control
14.31818 MHz
65540
or
65545
RGB
H/V Sync
To CRT
Display
Panel Control
Panel Data
To Flat
Panel
Display
32
16/24
512KByte or
1MByte Video
Memory
Optional
PCVideo
Multi-Media
Interface
24
System Diagram
Revision 1.2
65540 / 545
Revision History
Revision History
Revision
Date
By
Comment
1.1
9/94
DH
1.2
7/95
BB/MP
Revision 1.2
65540 / 545
Table of Contents
Table of Contents
Section
Introduction / Overview ..................................
Minimum Chip Count / Board Space ..........
Display Memory Interface...........................
CPU Bus Interface .......................................
High Performance Features .........................
65545 Acceleration......................................
65545 Hardware Cursor...............................
PC Video / Overlay Support........................
Display Interface..........................................
Flat Panel Displays..................................
Panel Power Sequencing .............................
CRT Displays ..........................................
Simultaneous Flat Panel / CRT Display..
Display Enhancement Features ...................
"True-Gray" Gray Scale Algorithm ........
RGB Color to Gray Scale Reduction ......
SmartMap ............................................
Text Enhancement...................................
Vertical and Horizontal Compensation ...
Advanced Power Management....................
Normal Operating Mode .........................
Mixed 3.3V and 5V Operation................
Panel Off Mode .......................................
Standby Mode .........................................
CRT Power Management (DPMS) .........
CPU Activity Indicator / Timer ...................
Full Compatibility .......................................
Write Protection ......................................
Extension Registers .................................
Panel Interface Registers.........................
Alternate Panel Timing Registers ...........
Context Switching ...................................
Reset, Setup, and Test Modes......................
Reset Mode..............................................
Setup Mode .............................................
Tri-State Mode ........................................
ICT (In-Circuit-Test) Mode ....................
Chip Architecture ........................................
Sequencer ................................................
CRT Controller........................................
Graphics Controller .................................
Attribute Controller .................................
VGA / Color Palette DAC.......................
Clock Synthesizers ..................................
Configuration Inputs....................................
Virtual Switch Register ...............................
Light Pen Registers......................................
BIOS ROM Interface...................................
Package........................................................
Application Schematics ...............................
Revision 1.2
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65540 / 545
Table of Contents
Table of Contents
Section
Page
Section
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177
177
178
178
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178
195
195
197
198
Application Schematics...................................
System Bus Interface ...................................
VL-Bus / 486 CPU Local Bus Interface......
PCI Local Bus Interface ..............................
Display Memory / PC Video Interface ........
CRT / Panel Interface ..................................
209
210
211
212
213
214
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259
65540 / 545
List of Tables
List of Tables
Table
Feature Differences .........................................
Display Capabilities ........................................
Supported Video Modes - VGA......................
Supported Video Modes - Extended ...............
Supported Video Modes - High Refresh .........
Vcc Pin to Interface Pin Correspondence .......
Reset/Setup/Test/Standby/Panel-Off Modes...
Configuration Pin Summary............................
Page
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13
13
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21
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Revision 1.2
Table
241
241
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248
248
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250
252
253
254
256
257
257
258
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259
65540 / 545
List of Figures
List of Figures
Figure
Page
Figure
23
24
25
26
Functional Description
Clock Synthesizer Register Structure ..........
Clock Synthesizer PLL Block Diagram ......
Clock Filter Circuit......................................
Clock Power / Ground Layout Example......
VGA Color Palette DAC Data Flow ...........
Possible BitBLT Orientations With Overlap
Screen-to-Screen BitBLT ............................
BitBLT Data Transfer..................................
Differential Pitch BitBLT Data Transfer.....
167
167
169
169
170
171
172
173
174
Revision 1.2
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255
255
256
257
257
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261
65540 / 545
Introduction / Overview
Introduction / Overview
The 65540 / 545 High Performance Flat Panel /
CRT Controllers initiate a family of 208-pin, high
performance solutions for full-featured notebook /
sub-notebook and other portable applications that
require the highest graphics performance available.
The 65545 is pin-to-pin compatible with the 65540
and adds a sophisticated graphics hardware engine
for Bit Block Transfer (BitBLT), line drawing,
hardware cursor, and other functions intensively
used in Graphical User Interfaces (GUIs) such as
Microsoft Windows. The 65540 and 65545 also
use the same video BIOS, offering the system
manufacturer a wide range of price / performance
points while minimizing overhead for system
integration and improving time-to-market. The
following table indicates feature differences
between the 65540 and 65545:
Features
65540
Support for all flat panels
3
VESA Local Bus / 16-bit ISA Bus
3
32-bit PCI Bus
Linear Addressing
3
Hardware Accelerator
Hardware Cursor
Pin Compatible
3
BIOS Compatible
3
65545
3
3
3
3
3
3
3
3
Minimum
chip-count,
low-power
graphics
subsystem implementations are enabled through the
high integration level of the 65540 / 545 family.
These devices integrate the VGA-compatible
graphics controller, true color RAMDAC, and dual
PLL clock synthesizers. The entire graphics sub-
Revision 1.2
65540 / 545
Introduction / Overview
n
n
n
Revision 1.2
65540 / 545
Introduction / Overview
DD STN LCD
Colors 2, 3, 4
256 / 226,981
16 / 226,981
256 / 226,981
16 / 226,981
256 / 226,981
16 / 226,981
256 / 226,981
n/a
Video
Memory
512KB
512KB
512KB
512KB
512KB
512KB
1MB
1MB
Simultaneous
Display
Yes
Yes
Yes
Yes with 1MB
Yes with 1MB
Yes with 1MB
Yes
n/a
Notes:
1 Larger color palettes and simultaneous colors can be displayed on 12-bit, 18-bit, and 24-bit TFT panels via the 65540 / 545 video input port
2 Includes dithering
3 Includes frame rate control
4 Colors are described as number of simultaneous on-screen colors and number of unique colors available in the color palette
256K colors assumes DAC output mode is set to 6 bits of R, G, & B. If DAC is set to 8-bit output mode, the number of available colors is 16M
Revision 1.2
65540 / 545
Introduction / Overview
CPU BUS INTERFACE
32-bit VL-Bus
32-Bit 386/486 CPU local bus
EISA/ISA (PC/AT) 16-bit bus
PCI Bus (65545 only)
n
n
n
32 x 32
64 x 64
64 x 64
128 x 128
65545 ACCELERATION
Several functions traditionally performed by
software have been implemented in hardware in the
65545 to off load the CPU and further improve
performance.
Three-Operand BitBLT logic
supports all 256 logical combinations of Source,
Destination, and Pattern. All BitBLTs are executed
up to 32-bits per cycle, maximizing the efficiency
of memory accesses. A 32-bit color expansion
engine allows the host CPU to transfer
monochrome "maps" of color images over the
system bus at high speeds to the 65545, which
decodes the monochrome images into their color
form. Line drawing is also accelerated with
hardware assistance.
Revision 1.2
(and/xor)
(and/xor)
(4-color)
(2-color)
x 2bpp
x 2bpp
x 2bpp
x 1bpp
10
65540 / 545
Introduction / Overview
DISPLAY INTERFACE
Panel On
ENAVDD
TPO
12-bit
'4096-Color'
Dither FRC
4096 (163)
No
No
29,791 (313)
No Yes
226,981 (613)
Yes No
1,771,561 (1213) Yes Yes
TPO
ENABKL
Flat Panel
Control &
Data Signals
Valid
TPO
T PO
ENAVEE
Revision 1.2
Panel Off
11
65540 / 545
Introduction / Overview
CRT
A,B,C
A,B,C
A,B,C
A,B,C
A,B,C
A,B,C
A,B,C
A,B,C
A,B,C
A,B,C
A,B,C
A,B,C
A,B,C
In this case, the horizontal frequency becomes 40.000 KHz and the vertical frequency becomes 89 Hz.
(see XR33 bit-7 "ISO Mode Control" for selection of VGA dot clock frequencies)
Note: Not all above resolutions can be supported at both 3.3V and 5V.
Refer to Electrical Specifications section for maximum clock frequencies for 5V and 3.3V operation.
CRT Codes:
A PS/2 fixed frequency analog CRT monitor or equivalent (31.5 / 35.5 KHz Horizontal Frequency Specification)
B Multi-Frequency CRT monitor (37.5 KHz Minimum Horizontal Frequency Specification) (NEC MultiSync 3D or equivalent)
C Multi-Frequency High-Performance CRT Monitor (48.5 KHz Min H Freq Specification) (Nanao Flexscan 9070s, MultiSync 5D, or equivalent)
Revision 1.2
12
65540 / 545
Introduction / Overview
Supported Video Modes - Extended Resolution
Mode# Display
(Hex)
Mode
20
4 bit Linear
22
4 bit Linear
24
4 bit Linear
24 I 4 bit Linear
28I 4 bit Linear
30
8 bit Linear
32
8 bit Linear
34
8 bit Linear
34 I 8 bit Linear
40 15bit Linear
41 16bit Linear
50 24bit Linear
60
Text
61
Text
6A, 70
Planar
72,75
Planar
72, 75I
Planar
78 Packed Pixel
79 Packed Pixel
7C Packed Pixel
7E Packed Pixel
7E I Packed Pixel
76 I 4 bit Planar
Colors
16
16
16
16
16
256
256
256
256
32K
64K
16M
16
16
16
16
16
16
256
256
256
256
16
Text
Display
80 x 30
100 x 37
128 x 48
128 x 48
128 x 48
80 x 30
100 x 37
128 x 48
128 x 48
80 x 30
80 x 30
80 x 30
132 x 25
132 x 50
100 x 37
128 x 48
128 x 48
80 x 25
80 x 30
100 x 37
128 x 48
128 x 48
128 x 48
Font
Size
8x16
8x16
8x16
8x16
8x16
8x16
8x16
8x16
8x16
8x16
8x16
8x16
8x16
8x16
8x16
8x16
8x16
8x16
8x16
8x16
8x16
8x16
8x16
Pixel
DotClock
Resolution (MHz)
640x480
25.175
800x600
40.000
1024x768
65.000
1024x768
44.900
1280x1024
65.000
640x480
25.175
800x600
40.000
1024x768
65.000
1024x768
44.900
640x480
50.350
640x480
50.350
640x480
65.000
1056x400
40.000
1056x400
40.000
800x600
40.000
1024x768
65.000
1024x768
44.900
640x400
25.175
640x480
25.175
800x600
40.000
1024x768
65.000
1024x768
44.900
1280x1024 65.000
Horizontal Vertical
Frequency Frequency Video
(KHz)
(Hz)
Memory CRT
31.5
60
512 KB A,B,C
37.5
60
512 KB B,C
48.5
60
512 KB
C
35.5
43
512 KB B,C
42.5
39
1 MB
C
31.5
60
512 KB A,B,C
37.5
60
512 KB B,C
48.5
60
1 MB
C
35.5
43
1 MB
B,C
31.5
60
1 MB A,B,C
31.5
60
1 MB A,B,C
27.1
51.6
1 MB
B,C
30.5
68
256 KB A,B,C
30.5
68
256 KB A,B,C
38.0
60
256 KB B,C
48.5
60
512 KB
C
35.5
43
512 KB B,C
31.5
70
256 KB A,B,C
31.5
60
512 KB A,B,C
37.5
60
512 KB B,C
48.5
60
1 MB
C
35.5
43
1 MB
B,C
42.5
39
1 MB
C
Note: Support for the modes in the above table is included directly in the BIOS (both 32K and 40K versions).
The "I" in the mode # column indicates "Interlaced".
Horizontal Vertical
Frequency Frequency Video
(KHz)
(Hz)
Memory CRT
37.5
75
256 KB B,C
37.5
75
256 KB
C
37.5
75
512 KB
C
46.9
75
512 KB
C
46.9
75
1 MB
C
46.9
75
1 MB
C
Note: Not all above resolutions can be supported at both 3.3V and 5V.
Refer to Electrical Specifications section for maximum clock frequencies for 5V and 3.3V operation.
CRT Codes:
A PS/2 fixed frequency analog CRT monitor or equivalent (31.5 / 35.5 KHz Horizontal Frequency Specification)
B Multi-Frequency CRT monitor (37.5 KHz Minimum Horizontal Frequency Specification) (NEC MultiSync 3D or equivalent)
C Multi-Frequency High-Performance CRT Monitor (48.5 KHz Min H Freq Specification) (Nanao Flexscan 9070s, MultiSync 5D, or equivalent)
Revision 1.2
13
65540 / 545
Introduction / Overview
SmartMap
Revision 1.2
14
65540 / 545
Introduction / Overview
Text Enhancement
Vertical & Horizontal Compensation are programmable features that adjust the display to completely
fill the flat panel display. Vertical Compensation
increases the useable display area when running
lower resolution software on a higher resolution
panel. Unlike CRT monitors, flat panels have a
fixed number of scan lines (e.g., 200, 400, 480 or
768 lines). Lower resolution software displayed on
a higher resolution panel only partially fills the
useable display area. For instance, 350-line EGA
software displayed on a 480-line panel would leave
130 blank lines at the bottom of the display and
400-line VGA text or Mode 13 images would leave
80 blank lines at the bottom. The 65540 / 545
offers the following Vertical Compensation
techniques to increase the useable screen area:
n
n
n
n
Revision 1.2
15
65540 / 545
Introduction / Overview
Standby Mode
Revision 1.2
16
65540 / 545
Introduction / Overview
FULL COMPATIBILITY
The 65540 / 545 is fully compatible with the IBM
VGA standard at the hardware, register, and BIOS
level. The 65540 / 545 also provides enhanced
backward compatibility to EGA and CGA
standards without using NMIs. These controllers
include a variety of features to provide
compatibility on flat panel displays in addition to
CRT monitors. Internal compensation techniques
ensure that industry-standard software designed for
different displays can be executed on the single flat
panel used in an implementation.
Mode
initialization is supported at the BIOS and register
levels, ensuring compatibility with all application
software.
Context Switching
For support of multi-tasking, windowing, and
context switching, the entire state of the 65540 /
545 (internal registers) is readable and writable.
This feature is fully compatible with IBM's VGA.
Additional registers are provided to allow read back
of internal latches not readable in the IBM VGA.
Write Protection
The 65540 / 545 has the ability to write protect
most of the standard VGA registers. This feature is
used to provide backwards compatibility with
software written for older generation display types.
The write protection is grouped into register sets
and controlled by the Write Protect Register
(XR15).
Extension Registers
The 65540 / 545 employs an "Extension" Register
set to control its enhanced features.
These
Extension Registers provide control of the flat panel
interface, flat panel timing, vertical compensation,
SMARTMAP, and Backwards Compatibility.
These registers are always accessible as an
index/data register set at port addresses 3D6-3D7h.
None of the unused bits in the regular VGA
registers are used for extensions.
Revision 1.2
17
65540 / 545
Introduction / Overview
Reset Mode
When this mode is activated by pulling the RESET#
pin low, the 65540 / 545 is forced to VGA-compatible mode and the CRT is selected as the active display. In addition, the 65540 / 545 is disabled; it
must be enabled after deactivating the RESET# pin
by writing to the Global Enable Register (102h in
Setup Mode for ISA bus configurations or to port
3C3h or Local Bus configurations). Access to all
Extension Registers is always enabled after reset (at
3D6/3D7h). The RESET# pin must be active for at
least 64 clock cycles.
Setup Mode
In this mode, only the Global Enable register is
accessible. In IBM-compatible PC implementations, setup mode is entered by writing a 1 to bit-4
of port 46E8h. This port is incorporated in the
65540 / 545. While in Setup mode, the video
output is active if it was active prior to entering
Setup mode and inactive if it was inactive prior to
entering Setup mode. After power up, video BIOS
can optionally disable the video 46E8 or 3C3
registers (via XR70) for compatibility in case other
non-IBM-compatible peripheral devices use those
ports.
Tri-State Mode
In this mode, all output pins of the 65540 / 545 chip
may be disabled for testing of circuitry external to
the chip. The 65540 / 545 will enter Tri-State mode
if it sees a rising edge on XTALI during RESET
with one of the display memory data pins pulled
Mode of
Operation
Reset
Setup
Test
Standby
Panel-Off
RESET#
Pin
Low
--------High
High
STNDBY#
Pin
xxx
--------Low
High
Display
Memory
Access
----No
No
No
Yes
Video
Output
----Yes
Yes
No
No
It is illegal to go from Panel-Off Mode to Standby Mode. Panel-Off Mode must be exited first and a delay must
occur of twice the value programmed into XR5B[7-4] prior to entering Standby Mode.
In 65540 ES Silicon reset is active high (RESET); in all following revisions reset is active low (RESET#).
Revision 1.2
18
65540 / 545
Introduction / Overview
CHIP ARCHITECTURE
The 65540 / 545 integrates six major internal
modules:
Sequencer
The Sequencer generates all CPU and display
memory timing. It controls CPU access of display
memory by inserting cycles dedicated to CPU
access. It also contains mask registers which can
prevent writes to individual display memory planes.
CRT Controller
The CRT Controller generates all the sync and
timing signals for the display and also generates the
multiplexed row and column addresses used for
both display refresh and CPU access of display
memory.
Graphics Controller
The Graphics Controller interfaces the 8, 16, or 32bit CPU data bus to the 32-bit internal data bus used
by the four planes (Maps) of display memory. It
also latches and supplies display memory data to
the Attribute Controller for use in refreshing the
screen image. For text modes this data is supplied
in parallel form (character generator data and
attribute code); for graphics modes it is converted to
serial form (one bit from each of four bytes form a
single pixel). The Graphics Controller can also
perform any one of several types of logical
operations on data while reading it from or writing
it to display memory or the CPU data bus.
Attribute Controller
24
RGB5-6-5ExternalVideo
HighColorPixelData
Red
Green
Blue
LUTPixelData
Triple6-bit
LUT
18
19
65540 / 545
Introduction / Overview
Clock Synthesizers
Integrated clock synthesizers support all pixel clock
(VCLK) and memory clock (MCLK) frequencies
which may be required by the 65540 / 545. Each of
the two clock synthesizers may be programmed to
output frequencies ranging between 1MHz and the
maximum specified operating frequency for that
clock in increments not exceeding 0.5%. The
VCLKRegisterTable
VGA CLK0 = 25.175MHz
VGA CLK1 = 28.322MHz
21
VCLK Synthesizer
CLK2 = Programmable
XR32:30
MCLKRegisterTable
MCLK = Programmable
CLKSEL1:0
21
MCLK Synthesizer
Revision 1.2
20
65540 / 545
Introduction / Overview
CONFIGURATION INPUTS
The 65540 / 545 can read up to nine configuration
bits. These signals are sampled on memory address
bus AA0-AA8 on the trailing edge of Reset. The
65540 / 545 implements pull-up resistors on-chip
on all configuration input pins. If the user wishes to
force a certain option, then a 4.7K ohm resistor may
be used to pull-down the desired configuration pin.
65540 / 545
Pin #
Signal Active
145
146
147
148
149
150
151
152
153
Functionality
LB# Low
Bus Configuration
ISA# Low
Bus Configuration
2X# Low
2xCPU Clock Select
Low
Reserved
2X#
(AA2)
Pin 147
ISA#
(AA1)
Pin 146
Low
Low
Low
Low
High
High
High
High
Low
Low
High
High
Low
Low
High
High
LB#
(AA0)
Pin 145
Bus Functionality
Low
Reserved
High
Reserved
Low
Reserved
High 32-bit CPU Bus (2x clk)
Low
Reserved
High
16-bit ISA Bus
Low
PCI Bus (65545 only)
High 32-bit VL-Bus (1x clk)
Revision 1.2
21
65540 / 545
Introduction / Overview
Revision 1.2
22
65540 / 545
DRAM"B"
DisplayMemoryUpper512KB
RASA#
OEAB#
AA9
(VR0)
AA8
(CFG8)
AA7
(CFG7)
AA6
(CFG6)
AA5
(CFG5)
AA4
(CFG4)
AA3
(CFG3)
AA2
(CFG2)
AA1
(CFG1)
AA0
(CFG0)
MBD15
MBD14
MVCCB
MBD13
MBD12
MGNDB
MBD11
MBD10
MBD9
MBD8
MBD7
MBD6
MBD5
MBD4
MBD3
MBD2
MBD1
MBD0
CASBL#
CASBH#
WEB#
RASB#
MCD15 (VR5)
MCD14 (VR4)
MCD13 (VR3)
MCD12 (VR2)
MCD11 (VG7)
MCD10 (VG6)
MCD9 (VG5)
MCD8 (VG4)
MCD7 (VG3)
MCD6 (VG2)
MCD5 (VB7)
MCD4 (VB6)
MCD3 (VB5)
MCD2 (VB4)
MVCCC
MCD1 (VB3)
MCD0 (VB2)
MGNDC
(LV#)
(TS#)
(AD#)
(OS#)
(2X#)
(ISA#)
(LB#)
Pin Diagram
DRAM"A"
DisplayMemory
Lower512KB
DRAM"C"
FrameBuffer
or
24-Bit
PC-Video
Interface
156
155
(32KHZ) 154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
(WEBL#) 126
(CASB#) 125
(WEBH#) 124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
10/30/95
Panel 80
Interface 79
78
Group 77
76
Pin names shown indicate VL-Bus connections (Default)
75
Pin names in brackets <...> indicate ISA-Bus connections (ISA# = 0)
74
Pin names in parentheses indicate alternate functions
73
72
71
70
(DE)(BLANK#) 69
(DE)(BLANK#) 68
67
66
65
64
63
62
(ENABKL) 61
60
DAC 59
58
Group 57
56
55
54
53
Configuration Pins
2X# = 0 2X LCLK
OS# = 0 External Oscillator (1=Xtal)
AD# = 0 ENABKL & ACTI are A26,A27
TS# = 0 Enable Clock Test Mode
LV# = 0 Input Threshold Level Control
65540
(WECL#) (VR6)
(CASC#) (VR7)
(WECH#) (PCLK)
(KEY)
(VR1)
(VG0)
(VG1)
(P23)
(P22)
(P21)
(P20)
(P19)
(P18)
(P17)
(P16)
<A0>
<D7>
<D6>
<D5>
<D4>
<D3>
<D2>
<D1>
<D0>
<D9>
<D8>
<IORD#>
<LA23>
<ROMCS#> (VCLKOUT)
<IRQ>
(MCLKOUT)
<AEN>
<BHE#>
<D15>
<D14>
<D13>
<D12>
<D11>
<D10>
<A6>
<A7>
<A8>
<A9>
<A10>
<A11>
<A12>
<A13>
<A14>
<A15>
<A16>
<LA17>
<LA18>
<LA19>
<LA20>
<LA21>
<LA22>
<reserved>
<reserved>
<reserved>
<reserved>
<reserved>
<IOCS16#>
<MCS16#>
<ZWS#>
<A1>
<ALE>
<MEMW#> (CRESET)
<RDY>
<IOWR#>
<A4>
<A5>
<RFSH#>
<MEMR#>
<A2>
<A3>
<reserved>
<reserved>
<reserved>
<reserved>
<reserved>
<reserved>
<reserved>
<reserved>
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
CASCL#
CASCH#
WEC#
RASC#
OEC#
CA9
CA8
CA7
CA6
CA5
CA4
CA3
CA2
CA1
CA0
DGND
P15
P14
P13
P12
P11
P10
P9
P8
IVCC
P7
P6
IGND
P5
P4
P3
P2
P1
P0
SHFCLK
M
LP
FLM
DVCC
HSYNC
VSYNC
DGND
ENAVDD
ENAVEE
RED
AVCC
GREEN
BLUE
AGND
RSET
ENABKL
ACTI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
WEA#
MVCCA
(CASA#) CASAH#
(WEAL#) CASAL#
MGNDA
(TSENA#) MAD0
(ICTENA#) MAD1
MAD2
MAD3
MAD4
MAD5
MAD6
MAD7
MAD8
MAD9
MAD10
MAD11
MAD12
MAD13
MAD14
MAD15
STNDBY#
A2
A3
IVCC
A4
A5
IGND
A6
A7
Bus
A8
Interface
A9
A10
Group
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
CGND0
XTALI
Clock XTALO
Group CVCC0
CVCC1
RESET#
CGND1
[] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] []
(WEAH#)
[] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] []
[] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] []
D31
D30
D29
D28
D27
D26
D25
D24
BVCC
BE3#
W/R#
BGND
D23
D22
D21
D20
D19
D18
D17
D16
BE2#
ADS#
RDYRTN#
LRDY#
LDEV#
BGND
LCLK
A23
A24
A25
M/IO#
BE1#
D15
D14
D13
D12
D11
D10
BGND
D9
D8
BVCC
BE0#
D7
D6
D5
D4
D3
D2
D1
D0
BGND
[] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] []
Bus
Interface
Group
Revision 1.2
23
65540 / 545
DRAM"B"
DisplayMemoryUpper512KB
RASA#
OEAB#
AA9
(VR0)
AA8
(CFG8)
AA7
(CFG7)
AA6
(CFG6)
AA5
(CFG5)
AA4
(CFG4)
AA3
(CFG3)
AA2
(CFG2)
AA1
(CFG1)
AA0
(CFG0)
MBD15
MBD14
MVCCB
MBD13
MBD12
MGNDB
MBD11
MBD10
MBD9
MBD8
MBD7
MBD6
MBD5
MBD4
MBD3
MBD2
MBD1
MBD0
CASBL#
CASBH#
WEB#
RASB#
MCD15 (VR5)
MCD14 (VR4)
MCD13 (VR3)
MCD12 (VR2)
MCD11 (VG7)
MCD10 (VG6)
MCD9 (VG5)
MCD8 (VG4)
MCD7 (VG3)
MCD6 (VG2)
MCD5 (VB7)
MCD4 (VB6)
MCD3 (VB5)
MCD2 (VB4)
MVCCC
MCD1 (VB3)
MCD0 (VB2)
MGNDC
(LV#)
(TS#)
(AD#)
(OS#)
(2X#)
(ISA#)
(LB#)
Pin Diagram
DRAM"A"
DisplayMemory
Lower512KB
DRAM"C"
FrameBuffer
or
24-Bit
PC-Video
Interface
156
155
(32KHZ) 154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
(WEBL#) 126
(CASB#) 125
(WEBH#) 124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
Panel 82
81
10/30/95
Interface 80
Group 79
78
77
shown indicate VL-Bus connections (Default)
76
in brackets <...> indicate ISA-Bus connections (ISA# = 0)
75
74
in quotes "..." indicate PCI-Bus connections (LB# = 0)
73
in parentheses indicate alternate functions
72
71
70
(DE)(BLANK#) 69
(DE)(BLANK#) 68
67
66
65
64
63
62
(ENABKL) 61
60
DAC 59
Group 58
57
56
55
54
53
Configuration Pins
2X# = 0 2X LCLK
OS# = 0 External Oscillator (1=Xtal)
AD# = 0 ENABKL & ACTI are A26,A27
TS# = 0 Enable Clock Test Mode
LV# = 0 Input Threshold Level Control
65545
(WECL#) (VR6)
(CASC#) (VR7)
(WECH#) (PCLK)
(KEY)
(VR1)
(VG0)
(VG1)
(P23)
(P22)
(P21)
(P20)
(P19)
(P18)
(P17)
(P16)
<A0>
<D7>
<D6>
<D5>
<D4>
<D3>
<D2>
<D1>
<D0>
<IORD#>
<LA23>
<ROMCS#>
<IRQ>
<AEN>
<BHE#>
<D15>
<D14>
<D13>
<D12>
<D11>
<D10>
(CRESET)
names
names
names
names
<reserved>
<reserved>
<reserved>
<reserved>
<reserved>
<IOCS16#>
<MCS16#>
<ZWS#>
<A1>
<ALE>
<MEMW#>
<RDY>
<IOWR#>
Pin
Pin
Pin
Pin
<RFSH#>
<MEMR#>
<A6>
<A7>
<A8>
<A9>
<A10>
<A11>
<A12>
<A13>
<A14>
<A15>
<A16>
<LA17>
<LA18>
<LA19>
<LA20>
<LA21>
<LA22>
<D9>
<D8>
<A4>
<A5>
(VCLKOUT)
(MCLKOUT)
<reserved>
<reserved>
<reserved>
<reserved>
<reserved>
<reserved>
<reserved>
<reserved>
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
CASCL#
CASCH#
WEC#
RASC#
OEC#
CA9
CA8
CA7
CA6
CA5
CA4
CA3
CA2
CA1
CA0
DGND
P15
P14
P13
P12
P11
P10
P9
P8
IVCC
P7
P6
IGND
P5
P4
P3
P2
P1
P0
SHFCLK
M
LP
FLM
DVCC
HSYNC
VSYNC
DGND
ENAVDD
ENAVEE
RED
AVCC
GREEN
BLUE
AGND
RSET
ENABKL
ACTI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
WEA#
MVCCA
(CASA#) CASAH#
(WEAL#) CASAL#
MGNDA
(TSENA#) MAD0
(ICTENA#) MAD1
MAD2
MAD3
MAD4
MAD5
MAD6
MAD7
MAD8
MAD9
MAD10
MAD11
MAD12
MAD13
MAD14
MAD15
STNDBY#
"reserved"
A2
"reserved"
A3
IVCC
"reserved"
A4
"reserved"
A5
IGND
"reserved"
A6
"reserved"
A7
"reserved"
A8
"reserved"
A9
"reserved"
A10
"reserved"
A11
"reserved"
A12
"reserved"
A13
"reserved"
A14
"reserved"
A15
"reserved"
A16
"reserved"
A17
"reserved"
A18
"reserved"
A19
"reserved"
A20
"reserved"
A21
"CLK"
A22
CGND0
Clock XTALI
XTALO
Group CVCC0
CVCC1
RESET#
CGND1
[] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] []
(WEAH#)
[] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] []
[] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] []
"AD31"
"AD30"
"AD29"
"AD28"
"AD27"
"AD26"
"AD25"
"AD24"
D31
D30
D29
D28
D27
D26
D25
D24
BVCC
"C/BE3#"
BE3#
"IDSEL"
W/R#
BGND
"AD23"
D23
"AD22"
D22
"AD21"
D21
"AD20"
D20
"AD19"
D19
"AD18"
D18
"AD17"
D17
"AD16"
D16
"C/BE2#"
BE2#
"FRAME#"
ADS#
"IRDY#" RDYRTN#
"TRDY#"
LRDY#
"DEVSEL#"
LDEV#
BGND
"STOP#"
LCLK
"reserved"
A23
"PERR#"
A24
"SERR#"
A25
"PAR"
M/IO#
"C/BE1#"
BE1#
"AD15"
D15
"AD14"
D14
"AD13"
D13
"AD12"
D12
"AD11"
D11
"AD10"
D10
BGND
"AD9"
D9
"AD8"
D8
BVCC
"C/BE0#"
BE0#
"AD7"
D7
"AD6"
D6
"AD5"
D5
"AD4"
D4
"AD3"
D3
"AD2"
D2
"AD1"
D1
"AD0"
D0
BGND
[] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] []
Bus
Interface
Group
Revision 1.2
24
65540 / 545
Pin List
Pin Name
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
(LA17)
A18
(LA18)
A19
(LA19)
A20
(LA20)
A21
(LA21)
A22
(LA22) "CLK"
A23
(LA23)
A24 (ROMCS#) "PERR#"
A25
(IRQ)
"SERR#"
AA0
(CFG0) (LB#)
AA1
(CFG1) (ISA#)
AA2
(CFG2) (2X#)
AA3
(CFG3)
AA4
(CFG4)
AA5
(CFG5) (OS#)
AA6
(CFG6) (AD#)
AA7
(CFG7) (TS#)
AA8
(CFG8) (LV#)
AA9
(32KHZ) (VR0)
ACTI
(A26)
(VB0)
ADS#
(ALE) "FRAME#"
AGND
AVCC
BE0#
(A0)
"C/BE0#"
BE1#
(BHE#) "C/BE1#"
BE2#
(A1)
"C/BE2#"
BE3#
(RFSH#) "C/BE3#"
BLUE
BGND (Bus)
BGND (Bus)
BGND (Bus)
BGND (Bus)
BVCC (Bus)
BVCC (Bus)
CA0
(P16)
CA1
(P17)
CA2
(P18)
CA3
(P19)
CA4
(P20)
CA5
(P21)
CA6
(P22)
CA7
(P23)
CA8
(VG1)
CA9
(VG0)
CASAH# (CASA#)
CASAL# (WEAL#)
CASBH# (CASB#)
CASBL# (WEBL#)
CASCH# (CASC#) (VR7)
CASCL# (WECL#) (VR6)
CGND0 (Clock)
CGND1 (Clock)
CVCC0 (Clock)
CVCC1 (Clock)
Note: Drive = 5V low drive
Revision 1.2
25
Dir
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Out
Out
Out
Out
Out
In
I/O
Out
Out
Out
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Drive
8mA
8mA
8mA
8mA
8mA
8mA
8mA
8mA
8mA
8mA
8mA
8mA
8mA
8mA
8mA
8mA
8mA
8mA
8mA
8mA
8mA
8mA
8mA
8mA
8mA
8mA
8mA
8mA
8mA
8mA
8mA
8mA
8mA
8mA
8mA
8mA
12mA
12mA
12mA
8mA
8mA
2mA
2mA
2mA
2mA
2mA
2mA
2mA
2mA
2mA
2mA
2mA
2mA
2mA
2mA
2mA
2mA
2mA
2mA
2mA
2mA
Pin Name
Pin # Dir Drive
MBD4
131 I/O 2mA
MBD5
132 I/O 2mA
MBD6
133 I/O 2mA
MBD7
134 I/O 2mA
MBD8
135 I/O 2mA
MBD9
136 I/O 2mA
MBD10
137 I/O 2mA
MBD11
138 I/O 2mA
MBD12
140 I/O 2mA
MBD13
141 I/O 2mA
MBD14
143 I/O 2mA
MBD15
144 I/O 2mA
MCD0 (VB2)
106 I/O 2mA
MCD1 (VB3)
107 I/O 2mA
MCD2 (VB4)
109 I/O 2mA
MCD3 (VB5)
110 I/O 2mA
MCD4 (VB6)
111 I/O 2mA
MCD5 (VB7)
112 I/O 2mA
MCD6 (VG2)
113 I/O 2mA
MCD7 (VG3)
114 I/O 2mA
MCD8 (VG4)
115 I/O 2mA
MCD9 (VG5)
116 I/O 2mA
MCD10 (VG6)
117 I/O 2mA
MCD11 (VG7)
118 I/O 2mA
MCD12 (VR2)
119 I/O 2mA
MCD13 (VR3)
120 I/O 2mA
MCD14 (VR4)
121 I/O 2mA
MCD15 (VR5)
122 I/O 2mA
MGNDA (Memory A)
161
MGNDB (Memory B)
139
MGNDC (Memory C)
105
M/IO# (AEN) "PAR"
31 I/O 4mA
MVCCA (Memory A)
158
MVCCB (Memory B)
142
MVCCC (Memory C)
108
OEAB#
155 Out 4mA
OEC#
(VR1)
100 I/O 4mA
P0
71 Out 8mA
P1
72 Out 8mA
P2
73 Out 8mA
P3
74 Out 8mA
P4
75 Out 8mA
P5
76 Out 8mA
P6
78 Out 8mA
P7
79 Out 8mA
P8
81 Out 8mA
P9
82 Out 8mA
P10
83 Out 8mA
P11
84 Out 8mA
P12
85 Out 8mA
P13
86 Out 8mA
P14
87 Out 8mA
P15
88 Out 8mA
RASA#
156 Out 4mA
RASB#
123 Out 4mA
RASC# (KEY)
101 I/O 4mA
RRTN#<MEMW#>"IRDY#" 23
In
RED
60 Out
RESET# (540 Rev 0=RESET) 207 In
RSET
55
In
SHFCLK
70 Out 8mA
STNDBY#
178 In
VSYNC
64 Out 12mA
WEA# (WEAH#)
157 Out 4mA
WEB# (WEBH#)
124 Out 4mA
WEC# (WECH#)(PCLK)
102 Out 4mA
W/R#
(MEMR#) "IDSEL" 11
In
XTALI
203 In
XTALO
204 Out
I/O in 65545 only for PCI, In for 65540
65540 / 545
Pin Lists
RESET#
VL-Bus
RESET#
CPUDirectLB
RESET#
ISA Bus
RESET#
25
24
23
11
31
22
27
I/O
Out
In
I/O
I/O
In
In
Bus
Bus
Bus
Bus
Bus
Bus
Bus
12 12 150
12 12 150
4 4 150
4 4 150
DEVSEL#
TRDY#
IRDY#
IDSEL
PAR
FRAME#
STOP#
LDEV#
LRDY#
RDYRTN#
W/R#
M/IO#
ADS#
LCLK
LDEV#
LRDY#
CRESET
W/R#
M/IO#
ADS#
CLK2X
IOWR#
RDY
MEMW#
MEMR#
AEN
ALE
IORD#
32
10
43
21
179
180
182
183
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
28
29
30
53
54
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
I/O
I/O
I/O
I/O
Bus
Bus
Bus
Bus
Bus
Bus
Bus
Bus
Bus
Bus
Bus
Bus
Bus
Bus
Bus
Bus
Bus
Bus
Bus
Bus
Bus
Bus
Bus
Bus
Bus
Bus
Bus
Bus
Bus
Bus
8
8
8
8
C/BE1#
C/BE3#
C/BE0#
C/BE2#
CLK
PERR#
SERR#
ACTI
ENABKL
BE1#
BE3#
BE0#
BE2#
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
BE1#
BE3#
BE0#
BE2#
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
BHE#
RFSH#
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
LA17
LA18
LA19
LA20
LA21
LA22
LA23
ROMCS#
IRQ
ACTI
ENABKL
8
8
8
8
150
150
150
150
These two pins usually function as ACTI and ENABKL, but can be reconfigured as additional address msbs (for 386/486/VL-Bus
only) via configuration bit-6 (see other tables and pin descriptions for more details)
In internal clock synthesizer test mode, MCLK is output on A25 and VCLK is output on A24.
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Pin Lists
Bus
Bus
Bus
Bus
Bus
Bus
Bus
Bus
Bus
Bus
Bus
Bus
Bus
Bus
Bus
Bus
IOH IOL
8 8
8 8
8 8
8 8
8 8
8 8
8 8
8 8
8 8
8 8
8 8
8 8
8 8
8 8
8 8
8 8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
VL-Bus
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
CPUDirectLB
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
ISA Bus
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
ZWS#
MCS16#
IOCS16#
Note: I OL and IOH drive listed above indicates 5V low drive and 3.3V high drive (see also XR6C)
Note: I OL/IOH are specified in mA; Load is specified in pF
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Pin Lists
PIN LIST - DISPLAY MEMORY INTERFACE
Pin # Type IOH IOL Load Function Alt
Alt
145 I/O 4 4 50
AA0
CFG0
146 I/O 4 4 50
AA1
CFG1
147 I/O 4 4 50
AA2
CFG2
148 I/O 4 4 50
AA3
CFG3
149 I/O 4 4 50
AA4
CFG4
150 I/O 4 4 50
AA5
CFG5
151 I/O 4 4 50
AA6
CFG6
152 I/O 4 4 50
AA7
CFG7
153 I/O 4 4 50
AA8
CFG8
154 I/O 4 4 50
AA9 32KHZ VR0
90
91
92
93
94
95
96
97
98
99
Out
Out
Out
Out
Out
Out
Out
Out
I/O
I/O
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
50
50
50
50
50
50
50
50
50
50
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9
P16
P17
P18
P19
P20
P21
P22
P23
VG1
VG0
156 Out 4
123 Out 4
101 I/O 4
4
4
4
50
50
50
RASA#
RASB#
RASC#
KEY
160
159
126
125
104
103
4
4
4
4
4
4
4
4
4
4
4
4
50
50
50
50
50
50
CASAL#
CASAH#
CASBL#
CASBH#
CASCL#
CASCH#
157 Out 4
124 Out 4
102 Out 4
4
4
4
50
50
50
WEA# WEAH#
WEB# WEBH#
WEC# WECH# PCLK
155 Out 4
100 I/O 4
4
4
50
50
OEAB#
OEC#
Out
Out
Out
Out
I/O
I/O
Pin #
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
127
128
129
130
131
132
133
134
135
136
137
138
140
141
143
144
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
106
107
109
110
111
112
113
114
115
116
117
118
119
120
121
122
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
WEAL#
CASA#
WEBL#
CASB#
WECL# VR6
CASC# VR7
VR1
IOH IOL
2 2
2 2
2 2
2 2
2 2
2 2
2 2
2 2
2 2
2 2
2 2
2 2
2 2
2 2
2 2
2 2
Load
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
Function
MAD0
MAD1
MAD2
MAD3
MAD4
MAD5
MAD6
MAD7
MAD8
MAD9
MAD10
MAD11
MAD12
MAD13
MAD14
MAD15
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
MBD0
MBD1
MBD2
MBD3
MBD4
MBD5
MBD6
MBD7
MBD8
MBD9
MBD10
MBD11
MBD12
MBD13
MBD14
MBD15
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
MCD0
MCD1
MCD2
MCD3
MCD4
MCD5
MCD6
MCD7
MCD8
MCD9
MCD10
MCD11
MCD12
MCD13
MCD14
MCD15
Alt
Alt
VB2
VB3
VB4
VB5
VB6
VB7
VG2
VG3
VG4
VG5
VG6
VG7
VR2
VR3
VR4
VR5
Note: I OL and IOH drive listed above indicates 5V low drive and 3.3V high drive (see also XR6C)
Note: I OL/IOH are specified in mA; Load is specified in pF
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Pin Lists
Type
Out
Out
Out
Out
Out
Vcc
Gnd
RSET
RED
GREEN
BLUE
AVCC
AGND
IVCC
181 Vcc
IVCC
Type
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
IOH IOL
8 8
8 8
8 8
8 8
8 8
8 8
8 8
8 8
8 8
8 8
8 8
8 8
8 8
8 8
8 8
8 8
8 8
8 8
8 8
8 8
Load Function
Alt
Alt
80
FLM
80
LP
BLANK# DE
80
M
BLANK# DE
80 SHFCLK
80
P0
80
P1
80
P2
80
P3
80
P4
80
P5
80
P6
80
P7
80
P8
80
P9
80
P10
80
P11
80
P12
80
P13
80
P14
80
P15
77
184
Gnd
Gnd
IGND
IGND
9
42
Vcc
Vcc
BVCC
BVCC
12
26
39
52
Gnd
Gnd
Gnd
Gnd
BGND
BGND
BGND
BGND
158
142
108
Vcc
Vcc
Vcc
MVCCA
MVCCB
MVCCC
161
139
105
Gnd
Gnd
Gnd
MGNDA
MGNDB
MGNDC
66
Vcc
DVCC
63
89
Gnd
Gnd
DGND
DGND
Load Function
Alt
Alt
80 ENAVDD
80 ENAVEE ENABKL
80 ENABKL A27 VB1
80
ACTI
A26 VB0
STNDBY#
Type
In
Out
Vcc
Vcc
Gnd
Gnd
XTALI
2 2 50 XTALO
CVCC0
CVCC1
CGND0
CGND1
Alt
Note: I OL and IOH drive listed above indicates 5V low drive and 3.3V high drive (see also XR6C)
Note: I OL/IOH are specified in mA; Load is specified in pF
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Pin Descriptions
PIN DESCRIPTIONS
Pin #
Pin Name
207
RESET#
22
ADS#
Active
In
Low
(ALE)
In
In
Low
High
Address Strobe. In VL-Bus and CPU local bus interfaces indicates valid address and control signal information is present. It is used for all decodes and to
indicate the start of a bus cycle.
(AEN)
In
In
Both
High
(MEMR#)
In
In
Both
Low
23
Low
High
Low
24
LRDY#
Out/OC
Out/OC
Low
High
(IOWR#)
Out
In
Low
Low
(IORD#)
In
In
Both
Low
31
11
M/IO#
W/R#
(RDY)
25
27
LDEV#
LCLK
Description
Note: Pin names in parentheses (...) indicate alternate functions (in this case, ISA bus control)
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Pin Descriptions
PIN DESCRIPTIONS
Pin #
Pin Name
Type Active
Description
43
BE0#
(A0) (BLE#)
In
Low
32
BE1#
(BHE#)
In
Low
21
BE2#
(A1)
In
Low
10
BE3#
(RFSH#)
In
Low
Byte Enable 3. BE3# indicates that data is to be transferred over the data bus on D31:24 during the current
access. Refresh input in ISA interfaces. Disconnected
in 16-bit local bus interfaces.
179
180
182
183
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
28
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
29
30
A24 (ROMCS#)
A25 (IRQ)
53
54
(LA17)
(LA18)
(LA19)
(LA20)
(LA21)
(LA22)
(LA23)
(VOUT) I/O
(MOUT) I/O
I/O
I/O
High
High
High
High
Address inputs through A23 are always available; A2427 may be optionally used for other functions:
In internal clock synthesizer test mode (TS#=0 at
Reset), A24 becomes VCLK out and A25 becomes
MCLK out.
A25 may alternately be used as a programmable polarity
IRQ output. Set when interrupt on VSYNC is enabled.
Cleared by reprogramming register 11h in the CRT
Controller. See also XR14 bit7.
For 24-bit RGB Video input, A26-27 may be used as
the two lsbs of the Blue Video. Otherwise, A26 and
A27 may be used as General Purpose I/O pins or as
Activity Indicator and Enable Backlight respectively (see
panel interface pin descriptions and XR5C and XR72
for more details).
Revision 1.2
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Pin Descriptions
PIN DESCRIPTIONS
Pin #
Pin Name
Active
Description
System Data Bus.
51
50
49
48
47
46
45
44
D00
D01
D02
D03
D04
D05
D06
D07
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
High
High
High
High
High
High
High
High
41
40
38
37
36
35
34
33
D08
D09
D10
D11
D12
D13
D14
D15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
High
High
High
High
High
High
High
High
20
19
18
17
16
15
14
13
D16
D17
D18
D19
D20
D21
D22
D23
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
High
High
High
High
High
High
High
High
8
7
6
5
4
3
2
1
D24
D25
D26
D27
D28
D29
D30
D31
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
High
High
High
High
High
High
High
High
(ZWS#)
(MCS16#)
(IOCS16#)
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Pin Descriptions
PIN DESCRIPTIONS
Pin #
Pin Name
207
Active
Description
RESET#
In
Low
201
CLK
In
High
31
PAR
I/O
High
22
FRAME#
In
Low
23
IRDY#
In
Low
24
TRDY#
S/TS
Low
27
STOP#
S/TS
Low
25
DEVSEL#
S/TS
Low
Note: S/TS stands for "Sustained Tri-state". These signals are driven by only one device at a time, are driven high for one clock before
being released, and are not driven for at least one cycle after being released by the previous device. A pull-up provided by the
bus controller is used to maintain an inactive level between transactions.
Revision 1.2
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Pin Descriptions
PIN DESCRIPTIONS
Pin #
Pin Name
Type
Active
29
PERR#
(VCLKOUT)
S/TS
Low
30
SERR#
(MCLKOUT)
OD
Low
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
These pins are reserved for future use and should not be
connected. All the pins in this group are tri-stated at all
times in PCI interface mode.
28
179-180
182-183
185-200
Reserved
Reserved
Reserved
Reserved
Description
Note: S/TS stands for "Sustained Tri-state". These signals are driven by only one device at a time, are driven high for one clock before
being released, and are not driven for at least one cycle after being released by the previous device. A central pull-up provided by
the bus controller is used to maintain an inactive level between transactions.
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Pin Descriptions
PIN DESCRIPTIONS
Pin #
Pin Name
Active
Description
PCI Address / Data Bus
51
50
49
48
47
46
45
44
AD00
AD01
AD02
AD03
AD04
AD05
AD06
AD07
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
High
High
High
High
High
High
High
High
41
40
38
37
36
35
34
33
AD08
AD09
AD10
AD11
AD12
AD13
AD14
AD15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
High
High
High
High
High
High
High
High
20
19
18
17
16
15
14
13
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
High
High
High
High
High
High
High
High
8
7
6
5
4
3
2
1
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
High
High
High
High
High
High
High
High
43
32
21
10
C/BE0#
C/BE1#
C/BE2#
C/BE3#
In
In
In
In
Low
Low
Low
Low
11
IDSEL
In
High
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Pin Descriptions
PIN DESCRIPTIONS
Pin #
Pin Name
145
146
147
148
149
150
151
152
153
154
AA0
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
90
91
92
93
94
95
96
97
98
99
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9
156
123
101
RASA#
RASB#
RASC#
(LB#)
(CFG0)
(ISA#)
(CFG1)
(2X#)
(CFG2)
(Reserved)(CFG3)
(Reserved)(CFG4)
(OS#)
(CFG5)
(AD#)
(CFG6)
(TS#)
(CFG7)
(LV#)
(CFG8)
(32KHz) (VR0)
Description
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
High
High
High
High
High
High
High
High
High
High
(P16)
(P17)
(P18)
(P19)
(P20)
(P21)
(P22)
(P23)
(VG1)
(VG0)
Out
Out
Out
Out
Out
Out
Out
Out
I/O
I/O
High
High
High
High
High
High
High
High
High
High
(KEY)
Out
Out
Out
In
Low
Low
Low
High
160
159
126
125
104
103
CASAL# (WEAL#)
CASAH# (CASA#)
CASBL# (WEBL#)
CASBH# (CASB#)
CASCL# (WECL#) (VR6)
CASCH# (CASC#) (VR7)
Out
Out
Out
Out
I/O
I/O
Low
Low
Low
Low
Both
Both
157
124
102
WEA#
WEB#
WEC#
Out
Out
Out
Low
Low
Both
155
100
OEAB#
OEC#
Out
I/O
Low
Both
(WEAH#)
(WEBH#)
(WECH#) (PCLK)
(VR1)
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Pin Descriptions
PIN DESCRIPTIONS
Pin #
Pin Name
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
127
128
129
130
131
132
133
134
135
136
137
138
140
141
143
144
106
107
109
110
111
112
113
114
115
116
117
118
119
120
121
122
MAD0
MAD1
MAD2
MAD3
MAD4
MAD5
MAD6
MAD7
MAD8
MAD9
MAD10
MAD11
MAD12
MAD13
MAD14
MAD15
MBD0
MBD1
MBD2
MBD3
MBD4
MBD5
MBD6
MBD7
MBD8
MBD9
MBD10
MBD11
MBD12
MBD13
MBD14
MBD15
MCD0
MCD1
MCD2
MCD3
MCD4
MCD5
MCD6
MCD7
MCD8
MCD9
MCD10
MCD11
MCD12
MCD13
MCD14
MCD15
(TSENA#)
(ICTENA#)
(VB2)
(VB3)
(VB4)
(VB5)
(VB6)
(VB7)
(VG2)
(VG3)
(VG4)
(VG5)
(VG6)
(VG7)
(VR2)
(VR3)
(VR4)
(VR5)
Active
Description
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
Revision 1.2
38
65540 / 545
Pin Descriptions
PIN DESCRIPTIONS
Pin #
Pin Name
Active
Description
8, 9, 12, or 16-bit flat panel data output. 18-bit and 24bit panel interfaces may also be supported (see CA0-7
for P16-23). Refer to the table below for configurations
for various panel types.
71
72
73
74
75
76
78
79
81
82
83
84
85
86
87
88
70
67
68
69
P0
Out
P1
Out
P2
Out
P3
Out
P4
Out
P5
Out
P6
Out
P7
Out
P8
(SHFCLKU)
Out
P9
Out
P10
Out
P11
Out
P12
Out
P13
Out
P14
Out
P15
Out
SHFCLK (CL2) (SHFCLKL) Out
FLM
Out
LP (CL1) (DE) (BLANK#) Out
M
(DE) (BLANK#) Out
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
62
61
53
54
ENAVDD
ENAVEE
(ENABKL)
ACTI
(GP0)(VB0)(A26)
ENABKL (GP1)(VB1)(A27)
High
High
High
High
Out
Out
I/O
I/O
Mono
Mono
Mono
Color
Color
Color
6554x 6554x
SS
DD
DD
TFT
TFT TFT HR
Pin# Pin Name 8-bit
8-bit
16-bit 9/12/16-bit 18/24-bit 18/24-bit
71
P0
UD3
UD7
B0
B0
B00
72
P1
UD2
UD6
B1
B1
B01
73
P2
UD1
UD5
B2
B2
B02
74
P3
UD0
UD4
B3
B3
B03
75
P4
LD3
UD3
B4
B4
B10
76
P5
LD2
UD2
G0
B5
B11
78
P6
LD1
UD1
G1
B6
B12
79
P7
LD0
UD0
G2
B7
B13
81
P8
P0
LD7
G3
G0
G00
82
P9
P1
LD6
G4
G1
G01
83
P10
P2
LD5
G5
G2
G02
84
P11
P3
LD4
R0
G3
G03
85
P12
P4
LD3
R1
G4
G10
86
P13
P5
LD2
R2
G5
G11
87
P14
P6
LD1
R3
G6
G12
88
P15
P7
LD0
R4
G7
G13
90
P16
R0
R00
91
P17
R1
R01
92
P18
R2
R02
93
P19
R3
R03
94
P20
R4
R10
95
P21
R5
R11
96
P22
R6
R12
97
P23
R7
R13
70 SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK
Pixels / Clock:
8
8
16
1
1
2
Revision 1.2
39
Color STN
Color
Color
Color
STN SS
STN SS STN DD STN DD
8-bit (X4bP) 16-bit (4bP) 8-bit (4bP) 16-bit (4bP)
R1...
R1...
UR1...
UR0...
B1...
G1...
UG1...
UG0...
G2...
B1...
UB1...
UB0...
R3...
R2...
UR2...
UR1...
B3...
G2...
LR1...
LR0...
G4...
B2...
LG1...
LG0...
R5...
R3...
LB1...
LB0...
B5...
G3...
LR2...
LR1...
SHFCLKU
B3...
UG1...
R4...
UB1...
G4...
UR2...
B4...
UG2...
R5...
LG1...
G5...
LB1...
B5...
LR2...
R6...
LG2...
65540 / 545
Pin Descriptions
PINDESCRIPTIONS
Pin #
Pin Name
Type
Active
Description
65
HSYNC
Out
Both
64
VSYNC
Out
Both
60
58
57
RED
GREEN
BLUE
Out
Out
Out
High
High
High
55
RSET
In
n/a
59
56
AVCC
AGND
VCC
GND
---
203
XTALI
I/O
High
XTALO
Out
High
205
202
CVCC0
CGND0
VCC
GND
---
206
208
CVCC1
CGND1
VCC
GND
---
204
(MCLK)
40
65540 / 545
Pin Descriptions
CRT / Panel Output Signal Status During Standby Mode
6554x Pin # Signal Name Signal Status
67
FLM
Forced Low
68
LP
Forced Low
70
SHFCLK
Forced Low
69
M
Forced Low
71
P0
Forced Low
72
P1
Forced Low
73
P2
Forced Low
74
P3
Forced Low
75
P4
Forced Low
76
P5
Forced Low
78
P6
Forced Low
79
P7
Forced Low
81
P8
Forced Low
82
P9
Forced Low
83
P10
Forced Low
84
P11
Forced Low
85
P12
Forced Low
86
P13
Forced Low
87
P14
Forced Low
88
P15
Forced Low
90
P16/CA0
Forced Low
91
P17/CA1
Forced Low
92
P18/CA2
Forced Low
93
P19/CA3
Forced Low
94
P20/CA4
Forced Low
95
P21/CA5
Forced Low
96
P22/CA6
Forced Low
97
P23/CA7
Forced Low
62
ENAVDD
Forced Low
61
ENAVEE
Forced Low
54
ENABKL/A27 Forced Low
65
HSYNC
Forced Low
64
VSYNC
Forced Low
53
ACTI/A26
Forced Low
60,58,57
R,G,B
Forced Low
Signal Polarity
XR54 bit 7
XR54 bit 6
N/A
N/A
XR61 bit 7 (text); XR63 bit 7 (graphics)
XR61 bit 7 (text); XR63 bit 7 (graphics)
XR61 bit 7 (text); XR63 bit 7 (graphics)
XR61 bit 7 (text); XR63 bit 7 (graphics)
XR61 bit 7 (text); XR63 bit 7 (graphics)
XR61 bit 7 (text); XR63 bit 7 (graphics)
XR61 bit 7 (text); XR63 bit 7 (graphics)
XR61 bit 7 (text); XR63 bit 7 (graphics)
XR61 bit 7 (text); XR63 bit 7 (graphics)
XR61 bit 7 (text); XR63 bit 7 (graphics)
XR61 bit 7 (text); XR63 bit 7 (graphics)
XR61 bit 7 (text); XR63 bit 7 (graphics)
XR61 bit 7 (text); XR63 bit 7 (graphics)
XR61 bit 7 (text); XR63 bit 7 (graphics)
XR61 bit 7 (text); XR63 bit 7 (graphics)
XR61 bit 7 (text); XR63 bit 7 (graphics)
XR61 bit 7 (text); XR63 bit 7 (graphics)
XR61 bit 7 (text); XR63 bit 7 (graphics)
XR61 bit 7 (text); XR63 bit 7 (graphics)
XR61 bit 7 (text); XR63 bit 7 (graphics)
XR61 bit 7 (text); XR63 bit 7 (graphics)
XR61 bit 7 (text); XR63 bit 7 (graphics)
XR61 bit 7 (text); XR63 bit 7 (graphics)
XR61 bit 7 (text); XR63 bit 7 (graphics)
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Revision 1.2
41
65540 / 545
Pin Descriptions
PIN DESCRIPTIONS
Pin #
Pin Name
Type
Active
Description
178
STNDBY#
In
Low
80
77
IVCC
IGND
Vcc
Gnd
181
184
IVCC
IGND
Vcc
Gnd
9
12
26
BVCC
BGND
BGND
Vcc
Gnd
Gnd
42
39
52
BVCC
BGND
BGND
Vcc
Gnd
Gnd
66
63
89
DVCC
DGND
DGND
Vcc
Gnd
Gnd
158
161
MVCCA
MGNDA
Vcc
Gnd
142
139
MVCCB
MGNDB
Vcc
Gnd
108
105
MVCCC
MGNDC
Vcc
Gnd
Bus/ClockOutputSignalStatusDuringStandbyMode
6554x Pin #
204
29
30
53
54
24
25
51-44, 41-40,38-33
20
19
18
17-13, 8-1
Signal Status
Signal Name
VL-Bus
ISA Bus
XTALO
Driven (see note 1) Driven (see note 1)
ROMCS# / A24
N/A
Driven High
IRQ / A25
N/A
Tri-Stated
ACTI / A26
(see previous page)
N/A
ENABKL / A27 (see previous page)
N/A
LRDY# / RDY
Tri-Stated
Tri-Stated
LDEV#
Driven High
N/A
D0-15
Tri-Stated
Tri-Stated
D16 / ZWS#
Tri-Stated
Tri-Stated
D17 / MCS16#
Tri-Stated
Tri-Stated
D18 / IOCS16#
Tri-Stated
Tri-Stated
D19-31
Tri-Stated
Tri-Stated
Notes:
1 The XTALO pin will always be driven except when XR33 bit-2 is set to '1'.
Revision 1.2
42
65540 / 545
I/O Map
I/O Map
PortAddress Read
102
Global Enable (ISA Bus Only)
Write
Global Enable (ISA Bus Only)
3B0
3B1
3B2
3B3
3B4
3B5
3B6
3B7
3B8
3B9
3BA
3BB
3BC
3BD
3BE
3BF
3C0
3C1
3C2
3C3
3C4
3C5
3C6
3C7
3C8
3C9
3CA
3CB
3CC
3CD
3CE
3CF
n3D0
n3D1
n3D2
n3D3
03D4
03D5
03D6
03D7
03D8
03D9
03DA
03DB
03DC
46E8
--
32-Bit register addresses are of the form 'bnnn nn1b bbbb bb00' where 'bbbbbbbb' is
specified by I/O base register XR07 and 'nnnnn' specifies 1 of 32 DRxx 32-bit registers
Revision 1.2
43
65540 / 545
Register Summary
Register Name
Display Status
CLPEN
SLPEN
0
0
W(n/a)
W(n/a)
MODE
COLOR
HCFG
7
6
2
RX, R0-11
XRX, XR0-7F
'6845' Registers
Extension Registers
0-8
0-8
Comment
3BB(ignored)
3B9(ignored)
3DB(ignored)
3DC (ignored)
R/W
R/W
W
R
3B8
n/a
3BF
3D6-3D7 index 14
3D8
3D9
n/a
n/a
R/W
R/W
3B4-3B5
3D6-3D7
3D4-3D5
3D6-3D7
Register Name
Miscellaneous Output
Feature Control
Bits
7
3
ST00 (FEAT)
ST01 (STAT)
4
7
R
R
3C2
3BA
3C2
3DA
CLPEN
SLPEN
0
0
W(n/a)
W(n/a)
3BB(ignored)
3B9(ignored)
3DB(ignored)
3DC (ignored)
SRX, SR0-7
CRX, CR0-3F
GRX, GR0-8
ARX, AR0-14
XRX, XR0-7F
Sequencer
CRT Controller
Graphics Controller
Attributes Controller
Extension Registers
0-8
0-8
0-8
0-8
0-8
R/W
R/W
R/W
R/W
R/W
3C4-3C5
3B4-3B5
3CE-3CF
3C0-3C1
3D6-3D7
3C4-3C5
3D4-3D5
3CE-3CF
3C0-3C1
3D6-3D7
Comment
Register Name
Video Subsystem Enable
Setup Control
Global Enable
PCI Configuration
MSR
Miscellaneous Output
W
R
3C2
3CC
3C2
3CC
FCR
Feature Control
W
R
3BA
3CA
3DA
3CA
ST00 (FEAT)
ST01 (STAT)
4
6
R
R
3C2
3BA
3C2
3DA
CLPEN
SLPEN
0
0
W(n/a)
W(n/a)
3BB(ignored)
3B9(ignored)
3DB(ignored)
3DC (ignored)
DACMASK
DACSTATE
DACRX
DACWX
DACDATA
8
2
8
8
3x6
R/W
R
W
R/W
R/W
3C6
3C7
3C7
3C8
3C9
3C6
3C7
3C7
3C8
3C9
SRX, SR0-7
CRX, CR0-3F
GRX, GR0-8
ARX, AR0-14
XRX, XR0-7F
DR00-DR0C
Sequencer
CRT Controller
Graphics Controller
Attributes Controller
Extension Registers
32-Bit Extension Registers
0-8
0-8
0-8
0-8
0-8
32
R/W
R/W
R/W
R/W
R/W
R/W
3C4-3C5
3B4-3B5
3CE-3CF
3C0-3C1
3D6-3D7
n3D0-n3D3
3C4-3C5
3D4-3D5
3CE-3CF
3C0-3C1
3D6-3D7
n3D0-n3D3
Revision 1.2
Bits
Access I/O Port - Mono I/O Port - Color
Comment
1
W
3C3 if LB
3C3 if LB
Disabled by XR70 bit-7
2
W
46E8 if ISA
46E8 if ISA
Disabled by XR70 bit-7
1
R/W
102 if ISA
102 if ISA
Setup Only in ISA Bus
8, 16, 32 R/W System Dependent System Dependent
PCI Bus Only
44
65540 / 545
Register Summary
Register Name
SequencerIndex
Reset
Clocking Mode
Plane Mask
Character Map Select
Memory Mode
Reset Horizontal Character Counter
CRX
CR0
CR1
CR2
CR3
CR4
CR5
CR6
CR7
CR8
CR9
CRA
CRB
CRC
CRD
CRE
CRF
LPENH
LPENL
CR10
CR11
CR12
CR13
CR14
CR15
CR16
CR17
CR18
CR22
CR24
CRTC Index
Horizontal Total
Horizontal Display End
Horizontal Blanking Start
Horizontal Blanking End
Horizontal Retrace Start
Horizontal Retrace End
Vertical Total
Overflow
Preset Row Scan
Character Cell Height
Cursor Start
Cursor End
Start Address High
Start Address Low
Cursor Location High
Cursor Location Low
Light Pen High
Light Pen Low
Vertical Retrace Start
Vertical Retrace End
Vertical Display End
Offset
Underline Row Scan
Vertical Blanking Start
Vertical Blanking End
CRT Mode Control
Line Compare
Graphics Controller Data Latches
Attribute Controller Index/Data Latch
GRX
GR0
GR1
GR2
GR3
GR4
GR5
GR6
GR7
GR8
ARX
AR0-F
AR10
AR11
AR12
AR13
AR14
Bits
3
2
6
4
6
3
0
RegisterType
VGA/EGA
VGA/EGA
VGA/EGA
VGA/EGA
VGA/EGA
VGA/EGA
VGA
Access(VGA)
R/W
R/W
R/W
R/W
R/W
R/W
W
Access(EGA)
R/W
R/W
R/W
R/W
R/W
R/W
n/a
I/OPort
3C4
3C5
3C5
3C5
3C5
3C5
3C5
6
8
8
8
5+2+1
8
5+2+1
8
8
5+2
5+3
5+1
5+2
8
8
8
8
8
8
8
4+4
8
8
5+2
8
8
7
8
8
1
VGA/EGA
VGA/EGA
VGA/EGA
VGA/EGA
VGA/EGA
VGA/EGA
VGA/EGA
VGA/EGA
VGA/EGA
VGA/EGA
VGA/EGA
VGA/EGA
VGA/EGA
VGA/EGA
VGA/EGA
VGA/EGA
VGA/EGA
VGA/EGA
VGA/EGA
VGA/EGA
VGA/EGA
VGA/EGA
VGA/EGA
VGA/EGA
VGA/EGA
VGA/EGA
VGA/EGA
VGA/EGA
VGA
VGA
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
W
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
n/a
n/a
4
4
4
4
5
2
6
4
4
8
VGA/EGA
VGA/EGA
VGA/EGA
VGA/EGA
VGA/EGA
VGA/EGA
VGA/EGA
VGA/EGA
VGA/EGA
VGA/EGA
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
3CE
3CF
3CF
3CF
3CF
3CF
3CF
3CF
3CF
3CF
6
6
7
6
6
4
4
VGA/EGA
VGA/EGA
VGA/EGA
VGA/EGA
VGA/EGA
VGA/EGA
VGA
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
n/a
3C0
3C0
3C0
3C0
3C0
3C0
3C0
Revision 1.2
45
(3C1)
(3C1)
(3C1)
(3C1)
(3C1)
(3C1)
(3C1)
65540 / 545
Register Summary
Register Name
Bits Access
Extension Index Register
7 R/W
Chip Version (65540: v=0; 65545: v=1) 8 R/O
Configuration
8 R/O
CPU Interface Control 1
8 R/W
CPUInterfaceControl2 (ROM Intfc) 2 R/W
Memory Control 1
4 R/W
Memory Control 2 (Clock Control) 8 R/W
Palette Control
(DRAM Intfc) 8 R/W
I/O Base ( 65545 Only )
8 R/W
LinearAddressingBase (Linear Base L) 8 R/W
-reserved(Linear Base H) ---reserved(XRAM Mode) --CPU Paging
5 R/W
Start Address Top
2 R/W
Auxiliary Offset
2 R/W
Text Mode Control
6 R/W
Software Flags 0
8 R/W
Port
3D6
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
XR10
XR11
XR12
XR13
XR14
XR15
XR16
XR17
XR18
XR19
XR1A
XR1B
XR1C
XR1D
XR1E
XR1F
XR20
XR21
XR22
XR23
XR24
XR25
XR26
XR27
XR28
XR29
XR2A
XR2B
XR2C
XR2D
XR2E
XR2F
Single/Low Map
High Map
-reserved-reservedEmulation Mode
WriteProtect
Vertical Overflow
Horizontal Overflow
Alternate H Disp End
AlternateHSyncStart
(Half-line)
Alternate H Sync End
Alternate H Total
Alternate Blank Start / H Panel Size
Alternate H Blank End
Alternate Offset
Virtual EGA Switch Register
-reserved-reserved-reserved-reservedFP AltMaxScanline
FP AltTxtHVirtPanel Size
Alt HSync Start
-reservedVideo Interface
Half Line Compare
-reservedSoftware Flags 1
FLM Delay
LP Delay
LP Delay
LP Width
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
Reset Codes:
x
d
h
r
=
=
=
=
8
8
--8
8
5
7
8
8
8
8
8
8
8
5
----5
8
8
-5
8
-8
8
8
8
8
R/W
R/W
--R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
----R/W
R/W
R/W
-R/W
R/W
-R/W
R/W
R/W
R/W
R/W
Reset
-xxxxxxx
1101v r r r
dddddddd
00000000
- - - - - -0x
- -0 - -000
00000000
00000000
11110100
xxxxxxxx
0
x
-00
- - - - - - 0000
xxxx
000
-xx
-00
0 - xxx
xxxxxxxx
xxxxxxxx
.
.
0
0
x
x
x
x
x
0
x
0
000h
0000
0 0
0000
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
- - -x
.
.
3
3
.
.
.
.
.
.
.
.
.
.
.
.
.
.
0
x
x
x
x
.
.
0000 - -0 xxxxxxxx
000
xxx
xxx
xxx
xxx
.
.
h00
000
000
000
xxx
xxx
xxx
xxx
xxx
xxx
xxx
xxx
xxxxx
xxxxxxxx
xxxxxxxx
0000
xxxx
xxxx
xxxx
xxxx
.
.
.
.
.
.
.
.
.
.
.
.
.
.
3
3
3
3
.
.
.
.
.
.
.
3
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
3
3
3
3
Note: Check marks in the table above indicate the register listed to the left is implemented in the chip named at the top of the column
Note: 82C450 & 64xxx VGAs drive CRTs only, 65xxx VGAs drive both CRT and Flat Panel displays (Plasma, EL, and LCD)
Revision 1.2
46
65540 / 545
Register Summary
Register Name
Clock Divide Control
Clock M-Divisor
Clock N-Divisor
Clock Control
-reserved-reserved-reserved-reserved-reserved-reservedColor Key 0
Color Key 1
Color Key 2
Color Key Mask 0
Color Key Mask 1
Color Key Mask 2
XR40
XR41
XR42
XR43
XR44
XR45
XR46
XR47
XR48
XR49
XR4A
XR4B
XR4C
XR4D
XR4E
XR4F
2
---8
8
---------5
XR50
XR51
XR52
XR53
XR54
XR55
XR56
XR57
XR58
XR59
XR5A
XR5B
XR5C
XR5D
XR5E
XR5F
Panel Format 1
Display Type
Power Down Control
Panel Format 3
PanelInterface
H Compensation
H Centering
V Compensation
V Centering
V Line Insertion
V Line Replication
Power Sequencing Delay
Activity Indicator Control
FP Diagnostic
ACDCLK (M) Control
Power Down Mode Refresh
8
7
8
7
8
6
8
8
8
7
4
8
7
8
8
8
Reset Codes:
x
d
h
r
=
=
=
=
Bits Access
4 R/W
7 R/W
7 R/W
7 R/W
------------8 R/W
8 R/W
8 R/W
8 R/W
8 R/W
8 R/W
Port
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
Reset
xxxx
xxxxxxx
xxxxxxx
0000 000
R/W
---R/W
R/W
---------R/W
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
- - - - - - xx
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xx xxx
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
xxxxxxxx
000 0000
00000001
00000x0
xxxxxxxx
xxxx xx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxx xxxx
xxxx
10000001
0x xxxxx
00000000
xxxxxxxx
xxxxxxxx
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
xxxxxxxx
xxxxxxxx
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
3
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
3
.
.
.
3
3
Note: Check marks in the table above indicate the register listed to the left is implemented in the chip named at the top of the column
Note: 82C450 & 64xxx VGAs drive CRTs only, 65xxx VGAs drive both CRT and Flat Panel displays (Plasma, EL, and LCD)
Revision 1.2
47
65540 / 545
Register Summary
Register Name
Bits Access
Blink Rate Control
8 R/W
SmartMap Control
8 R/W
SmartMap Shift Parameter
8 R/W
SmartMapColorMappingControl
8 R/W
FP Alternate Vertical Total
8 R/W
FP Alternate Overflow
6 R/W
FP Alternate Vertical Sync Start 8 R/W
FP Alternate Vertical Sync End
4 R/W
FP Vertical Panel Size
8 R/W
-reserved---reserved---reserved--Programmable Output Drive
5 R/W
-reserved--Polynomial FRC Control
8 R/W
Frame Buffer Control
8 R/W
Port
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
Reset
10000011
xxxxxxxx
xxxxxxxx
x1xxxxxx
xxxxxxxx
xxx xxx
xxxxxxxx
xxxx
xxxxxxxx
XR70
XR71
XR72
XR73
XR74
XR75
XR76
XR77
XR78
XR79
XR7A
XR7B
XR7C
XR7D
XR7E
XR7F
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
3D7
0-------
Reset Codes:
x
d
h
r
=
=
=
=
1
-7
6
---------1
6
8
R/W
-R/W
R/W
---------R/W
R/W
R/W
0000d
10111101
00000000
0000000
00 - - 0000
0------
- - xxxxxx
00xxxx00
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
3
3
3
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
3
3
.
.
.
.
.
.
.
.
.
.
Note: Check marks in the table above indicate the register listed to the left is implemented in the chip named at the top of the column
Note: 82C450 & 64xxx VGAs drive CRTs only, 65xxx VGAs drive both CRT and Flat Panel displays (Plasma, EL, and LCD)
Revision 1.2
48
65540 / 545
Register Summary
Group
BitBLT
BitBLT
BitBLT
BitBLT
BitBLT
BitBLT
BitBLT
BitBLT
Register Name
BitBLT Offset
BitBLT Pattern ROP
BitBLT BG Color
BitBLT FG Color
BitBLT Control
BitBLT Source
BitBLT Destination
BitBLT Command
Bits
16/32
16/32
16/32
16/32
16/32
16/32
16/32
16/32
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port
83D0-3
87D0-3
8BD0-3
8FD0-3
93D0-3
97D0-3
9BD0-3
9FD0-3
- - - - xxxx
-------xxxxxxxx
xxxxxxxx
---------------------- - - - 0000
DR08
DR09
DR0A
DR0B
DR0C
Cursor
Cursor
Cursor
Cursor
Cursor
Cursor Control
Cursor Color 0-1
Cursor Color 2-3
Cursor Position
Cursor Base Address
16/32
16/32
16/32
16/32
16/32
R/W
R/W
R/W
R/W
R/W
A3D0-3
A7D0-3
ABD0-3
AFD0-3
B3D0-3
Reset Codes:
x
d
h
r
Revision 1.2
=
=
=
=
49
Reset
xxxxxxxx - - - - xxxx
- - - xxxxx xxxxxxxx
xxxxxxxx xxxxxxxx
xxxxxxxx xxxxxxxx
- - - 0xxxx xxxxxxxx
- - - xxxxx xxxxxxxx
- - - xxxxx xxxxxxxx
00000000 - - - - xxxx
0000
xxxxxxxx
xxxxxxxx
x - - - - xxx
xxxxxx - -
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
000 00
xxxxxxxx
xxxxxxxx
xxxxxxxx
--------
65540 / 545
Register Summary
Register Name
Vendor ID
Device ID
Device Control
Device Status
Bits Access
16
R
16
R
16
R/W
16
R/C
Offset
00h
02h
04h
06h
REV
PRG
SUB
BASE
Revision
Programming Interface
Sub Class Code
Base Class Code
8
8
8
8
R
R
R
R
08h
09h
0Ah
0Bh
MBASE
IOBASE
32
32
R/W
R/W
10h
14h
Reset
00010000
00000000
- - - - - - 10
00000000
00101100
11011000
10000000
0-----------rrr
00000000
00000000
00000011
- - - - 0000
- - - - - - 01
Note: R = Read, W = Write, C = Clear (1s written to specific bits will clear those bits)
Revision 1.2
50
65540 / 545
Registers
Registers
GLOBAL CONTROL (SETUP) REGISTERS
Revision 1.2
51
65540 / 545
Registers
The Attribute Controller Index Register contains a 5bit index to the Attribute Controller Registers which
consist of a 16-entry color lookup table with 6 bits
per entry plus five additional control registers. A
sixth index register bit is used to enable video. The
Attribute Controller Registers handle color lookup
table mapping, text/graphics mode control, overscan
color selection, and color plane enabling. One
register allows the display to be shifted left up to 8
pixels. Another register provides default values to
extend the 6-bit lookup table values to 8 bits for
modes providing less than 8 bits per pixel.
EXTENSION REGISTERS
The 65540 / 545 defines a set of extension registers
(called "XR's") which are addressed with the 7-bit
Extension Register Index. The I/O port address is
fixed at 3D6-3D7h and read/write access is always
enabled to improve software performance.
The extension registers handle a variety of interfacing, compatibility, and display functions as
discussed below. They are grouped into the
following logical groups for discussion purposes:
Note: The state of most of the standard VGA registers is undefined at reset. The state at Reset of all registers
specific to the 65540 / 545 (extension registers and 32-bit registers) is summarized in the register summary tables.
Revision 1.2
52
65540 / 545
Register Name
SETUP
VSE
ENAB
Setup Control
Video Subsystem Enable
Global Enable
Index
Access
I/O
I/O Address
Page
W
W
RW
53
53
54
VIDEOSUBSYSTEMENABLEREGISTER(VSE)
Write Only at I/O Address 3C3h
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
VGA Sleep
Reserved(0)
VGA Enable
VGA Setup
Reserved(0)
Reserved(0)
7-5
Reserved (0)
VGA Enable
0 VGA is disabled
1 VGA is enabled
Setup Mode
0 VGA is in Normal Mode
1 VGA is in Setup Mode
Reserved (0)
Revision 1.2
7-1
53
VGA Sleep
0 VGA is disabled
1 VGA is enabled
Reserved (0)
65540 / 545
Reserved(0)
7-1
VGA Sleep
0 VGA is disabled
1 VGA is enabled
Reserved (0)
Revision 1.2
54
65540 / 545
Register Name
VENID
DEVID
DEVCTL
DEVSTAT
REV
PRG
SUB
BASE
Vendor ID
DeviceID
DeviceControl
Device Status
Revision
Programming Interface
Sub Class Code
Base Class Code
00h
02h
04h
06h
08h
09h
0Ah
0Bh
R
R
R/W
R/C
R
R
R
R
MBASE
IOBASE
10h
14h
Offset Access
Reset State
Page
55
55
56
56
57
57
57
57
Note: 'Access' codes are R=Read, W=Write, and C=Clear (writing a 1 to a bit clears that bit)
15
15
Vendor ID
Device ID
150 Vendor ID
150 Device ID
Revision 1.2
55
65540 / 545
15
15
Undefined(0)
Always Reads 1
Always Reads 0
DEVSEL# Timing
(Always Reads 10)
Target Abort Sig'd
Always Reads 0
Always Reads 0
Sys Err Signaled
Parity Err Detected
Undefined(0)
2
3
4
5
7
8
60
7
11
PERR# Enable
Set to enable PERR# response for detected
data parity errors.
12
13
14
15
Undefined / Reserved ( 0 )
56
65540 / 545
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
2-0
7-3
Sub-Class Code
7-0
Sub-Class Code
This register always returns a value of 00h
to indicate "VGA Compatible Controller".
Reserved (0)
These bits are defined by the PCI 2.0
specification as additional revision code bits.
They always read zero.
PROGRAMMINGINTERFACEREGISTER(PRG)
Read/Only at PCI Configuration Offset 09h
ByteAccessible
Accessable in PCI Bus Configuration Only
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Programming
Interface
Code
7-0
7-0
Revision 1.2
57
65540 / 545
31
31
2322
4 32 1 0
10 9
2 1 0
0 (Memory Space)
1 (I/O Space)
0(Reserved)
00 (32-bit Address)
0 (No Prefetching)
0 (Address Mask)
(1KB Range)
0 (Address Mask)
(8MB Range)
9-2
Note:
Value
Programmed
000000h
000001h
000002h
000003h
000004h
...
Revision 1.2
0:
8MB:
16MB:
24MB:
32MB:
40MB:
...
Value
Programmed
000000000b
000000001b
000000010b
000000011b
000000100b
000000101b
...
58
Note:
Note:
Register Name
Index
Access
I/O
Address
Protect
Group
Page
ST00
ST01
FCR
Input Status 0
Input Status 1
Feature Control
59
59
60
MiscellaneousOutput
3C2h
3BAh/3DAh
3BAh/3DAh
3CAh
3C2h
3CCh
MSR
R
R
W
R
W
R
60
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
DE/Hsync Output
Reserved(0)
Reserved(0)
VerticalRetrace/Video
Reserved(0)
CRT Interrupt Pending
3-0
4
Reserved (0)
6-5
7
Reserved (0)
Reserved (0)
Vertical Retrace/Video
The functionality of this bit is controlled by
the Emulation Mode register (XR14 bit-5).
0 Indicates VSYNC or video inactive
1 Indicates VSYNC or video active
5-4
Video Feedback 1, 0
These are diagnostic video bits which are
selected via the Color Plane Enable Register.
6
7
Reserved (0)
VSync Output
The functionality of this bit is controlled by
the Emulation Mode register (XR14 bit-6).
It reflects the active status of the VSYNC
output: 0=inactive, 1=active.
Revision 1.2
59
65540 / 545
MISCELLANEOUSOUTPUTREGISTER(MSR)
Write at I/O Address 3C2h
Read at I/O Address 3CCh
Group 5 Protection
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Feature Control
Reserved(0)
VSync Control
Clock Select
Reserved(0)
Page Select
HSync Polarity
VSync Polarity
Reserved(0)
1-0
2
3
7-4
Feature Control
These bits are used internal to the chip in
conjunction with the Configuration Register
(XR01). When enabled by XR01 bits 2-3
and Misc Output Register bits 3-2 = 10,
these bits determine the pixel clock
frequency typically as follows:
FCR1:0 = 00 = 40.000 MHz
FCR1:0 = 01 = 50.350 MHz
FCR1:0 = 10 = User defined
FCR1:0 = 11 = 44.900 MHz
This preserves compatibility with drivers
developed for earlier generation Chips and
Technologies VGA controllers.
Reserved (0)
VSync Control
This bit is cleared by RESET.
0 VSync output on the VSYNC pin
1 Logical 'OR' of VSync and Display
Enable output on the VSYNC pin
This capability is not typically very useful,
but is provided for IBM compatibility.
Reserved (0)
60
65540 / 545
RegisterName
MODE
COLOR
HCFG
CGA/Hercules Mode
CGA Color Select
Hercules Configuration
Index
Access
I/O
Address
Protect
Group
Page
R/W
R/W
R/W
3D8h
3D9h
3BFh
61
62
62
D7 D6 D5 D4 D3 D2 D1 D0
0
1
Reserved (0)
HiRes Text
(CGA only)
Graphics Mode (0=Text)
Monochrome (CGA only)
Video Enable
HiRes Graphics (CGA only)
Text Blink Enable
Reserved(0)
Page Select
(Herc only)
Revision 1.2
61
65540 / 545
HERCULES CONFIGURATION
REGISTER ( HCFG )
Write only at I/O Address 3BFh
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Enable Graphics Mode
Enable Memory Page 1
Reserved(0)
Reserved(0)
Color
Enable Graphics
0
Text Mode:
320x200 4-color:
640x200 2-color:
5
Intensity Enable
Enables intensified
background colors
Enables intensified
colors 0-3
Don't care
7-6
0
1
0
1
Color Set
0
Color Set
1
7-2
Mode
Reserved (0)
Reserved(0)
Revision 1.2
62
65540 / 545
Sequencer Registers
Sequencer Registers
Register
Mnemonic
Register Name
SRX
SR00
SR01
SR02
SR03
SR04
SR07
Sequencer Index
Reset
Clocking Mode
Plane/MapMask
Character Font
Memory Mode
Horizontal Character Counter Reset
Index
Access
I/O
Address
00h
01h
02h
03h
04h
07h
R/W
R/W
R/W
R/W
R/W
R/W
W
3C4h
3C5h
3C5h
3C5h
3C5h
3C5h
3C5h
Protect
Group Page
1
1
1
1
1
1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
SequencerIndex
Async Reset
Sync Reset
Reserved(0)
Reserved(0)
Sequencer Index
These bits contain a 3-bit Sequencer Index
value used to access sequencer data registers
at indices 0 through 7.
7-3
Asynchronous Reset
0 Force asynchronous reset
1 Normal operation
Display memory data will be corrupted if
this bit is set to zero.
Reserved (0)
7-2
Revision 1.2
63
63
64
64
65
66
66
63
Synchronous Reset
0 Force synchronous reset
1 Normal operation
Display memory data is not corrupted if this
bit is set to zero for a short period of time (a
few tenths of a microsecond). See also
XR0E.
Reserved (0)
65540 / 545
Sequencer Registers
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
8/9 Dot Clocks
Reserved(0)
Shift Load
Input Clock Divide
Shift 4
Screen Off
Reserved(0)
Reserved(0)
3-0
Reserved (0)
Shift Load
0 Load video data shift registers every
characterclock
1 Load video data shift registers every
other character clock
Reserved (0)
Shift 4
0 Load video shift registers every 1 or 2
character clocks (depending on bit-2
of this register)
1 Load shift registers every 4th character
clock.
Screen Off
0 Normal Operation
1 Disable video output and assign all
display memory bandwidth for CPU
accesses
Reserved (0)
7-6
Revision 1.2
64
65540 / 545
Sequencer Registers
D7 D6 D5 D4 D3 D2 D1 D0
Font Select B bit-1
Font Select B bit-2
Font Select A bit-1
Font Select A bit-2
Font Select B bit-0
Font Select A bit-0
Reserved(0)
3-2
7-6
Reserved (0)
Revision 1.2
65
65540 / 545
Sequencer Registers
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Reserved(0)
ExtendedMemory
Odd/EvenMode
Quad Four Mode
Don't Care
Reserved(0)
Reserved (0)
Extended Memory
Odd/Even Mode
0 CPU accesses to Odd/Even addresses
are directed to corresponding odd/even
planes
1 All planes are accessed simultaneously
(IRGB color)
Bit-3 of this register must be 0 for this bit to
be effective. This bit affects only CPU write
accesses to display memory.
7-4
Reserved (0)
Revision 1.2
66
65540 / 545
Register Name
Index
Access
I/O
Address
CRX
CR00
CR01
CR02
CR03
CR04
CR05
CR06
CR07
CR08
CR09
CR0A
CR0B
CR0C
CR0D
CR0E
CR0F
CR10
CR11
CR10
CR11
CR12
CR13
CR14
CR15
CR16
CR17
CR18
CR22
CR24
CRTC Index
HorizontalTotal
Horizontal Display Enable End
Horizontal Blank Start
Horizontal Blank End
Horizontal Sync Start
Horizontal Sync End
VerticalTotal
Overflow
Preset Row Scan
Maximum Scan Line
Cursor Start Scan Line
Cursor End Scan Line
Start Address High
Start Address Low
Cursor Location High
Cursor Location Low
Vertical Sync Start (See Note 2)
Vertical Sync End (See Note 2)
Lightpen High (See Note 2)
Lightpen Low (See Note 2)
Vertical Display Enable End
Offset
Underline Row
Vertical Blank Start
Vertical Blank End
CRT Mode Control
Line Compare
Memory Data Latches
Attribute Controller Toggle
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
10h
11h
12h
13h
14h
15h
16h
17h
18h
22h
24h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W or R/W
W or R/W
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
3B4h/3D4h
3B5h/3D5h
3B5h/3D5h
3B5h/3D5h
3B5h/3D5h
3B5h/3D5h
3B5h/3D5h
3B5h/3D5h
3B5h/3D5h
3B5h/3D5h
3B5h/3D5h
3B5h/3D5h
3B5h/3D5h
3B5h/3D5h
3B5h/3D5h
3B5h/3D5h
3B5h/3D5h
3B5h/3D5h
3B5h/3D5h
3B5h/3D5h
3B5h/3D5h
3B5h/3D5h
3B5h/3D5h
3B5h/3D5h
3B5h/3D5h
3B5h/3D5h
3B5h/3D5h
3B5h/3D5h
3B5h/3D5h
3B5h/3D5h
Protect
Group Page
0
0
0
0
0
0
0
0/3
3
2/4
2
2
4
3/4
4
3
3
4
4
3/4
3
68
68
68
69
69
70
70
71
71
72
72
73
73
74
74
74
74
75
75
75
75
76
76
76
77
77
78
79
80
80
Note 1: When MDA or Hercules emulation is enabled, the CRTC I/O address should be set to 3B0h-3B7h by
setting the I/O address select bit in the Miscellaneous Output register (3C2h/3CCh bit-0) to zero. When
CGA emulation is enabled, the CRTC I/O address should be set to 3D0h-3D7h by setting Misc Output
Register bit-0 to 1.
Note 2: In the EGA, all CRTC registers except the cursor (CR0C-CR0F) and light pen (CR10 and CR11)
registers are write-only (i.e., no read back). In both the EGA and VGA, the light pen registers are at
index locations conflicting with the vertical sync registers. This would normally prevent reads and writes
from occurring at the same index. Since the light pen registers are not normally useful, the VGA
provides software control (CR03 bit-7) of whether the vertical sync or light pen registers are readable at
indices 10-11.
Revision 1.2
67
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D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
CRTC Index
Horizontal Display
Reserved(0)
5-0
7-6
Reserved (0)
This register is used for all VGA and EGA modes on
CRTs. It is also used for 640 column CGA modes
and MDA/Hercules text mode. In all 320 column
CGA modes and Hercules graphics mode, the
alternate register is used.
7-0
Horizontal Display
Number of Characters displayed per scan
line 1.
D7 D6 D5 D4 D3 D2 D1 D0
Horizontal Total
Horizontal Total
Total number of character clocks per line =
contents of this register + 5. This register
determines the horizontal sweep rate.
Revision 1.2
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65540 / 545
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
H Blank End
H Blank Start
DE Skew Control
Light Pen Register Enable
4-0
6-5
Revision 1.2
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65540 / 545
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
4-0
6-5
Revision 1.2
70
65540 / 545
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
V Total Bit 8
V DE End Bit 8
V Sync Start Bit 8
V Blank Start Bit 8
Line Compare Bit 8
V Total Bit 9
V DE End Bit 9
V Sync Start Bit 9
Vertical Total
Revision 1.2
71
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D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
4-0
4-0
Double Scan
Reserved (0)
Revision 1.2
0 Normal Operation
1 Enable scan line doubling
72
65540 / 545
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Cursor off
Cursor Delay
Reserved(0)
Reserved(0)
4-0
4-0
7-6
Cursor Off
0 Text Cursor On
1 Text Cursor Off
6-5
Cursor Delay
These bits define the number of character
clocks that the cursor is delayed to
compensate for internal pipeline delay.
Reserved (0)
7
Reserved (0)
Revision 1.2
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CURSORLOCATIONHIGHREGISTER(CR0E)
Read/Write at I/O Address 3B5h/3D5h
Index 0Eh
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
7-0
7-0
CURSORLOCATIONLOWREGISTER(CR0F)
Read/Write at I/O Address 3B5h/3D5h
Index 0Fh
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
7-0
7-0
Revision 1.2
74
65540 / 545
D7 D6 D5 D4 D3 D2 D1 D0
V Sync End
V Interrupt Clear
V Interrupt Enable
Select Refresh Type
Protect CRTC (Group 0)
D7 D6 D5 D4 D3 D2 D1 D0
V Sync Start
(Lower 8 bits)
Group Protect 0
Revision 1.2
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D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Underline Position
V Display Enable End
(Lower 8 bits)
7-0
Count by 4
DoublewordMode
Reserved(0)
4-0
Underline Position
These bits specify the underline's scan line
position within a character row.
D7 D6 D5 D4 D3 D2 D1 D0
Doubleword Mode
0 Frame Buffer Address is byte or word
address
1 Frame Buffer Address is doubleword
address
Revision 1.2
76
Reserved (0)
65540 / 545
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
V Blank Start
(Lower 8 bits)
V Blank End
(Lower 8 bits)
7-0
Revision 1.2
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D7 D6 D5 D4 D3 D2 D1 D0
Compatibility Mode
Select Row Scan Counter
VSync Select
Count by 2
Reserved(0)
AddressWrap
Word/ByteMode
CRTC Reset
Count By Two
0 Memory
address
counter
is
incremented every character clock
1 Memory
address
counter
is
incremented every two character
clocks, used in conjunction with bit 5
of 0Fh.
Note: This bit is used in conjunction with
CR14 bit-5. The net effect is as follows:
Increment
CR14 CR17 Addressing
Bit-5
Bit-3
Every
0
0
1 CCLK
0
1
2 CCLK
1
0
4 CCLK
1
1
2 CCLK
CR17
Bit-6
0
1
0
1
Addressing Mode
Word Mode
Byte Mode
Double Word Mode
Double Word Mode
CRTC Reset
0 Force HSYNC and VSYNC inactive.
No other registers or outputs affected.
1 Normal Operation
This bit is cleared by RESET.
Revision 1.2
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LINE COMPARE
REGISTER (CR18)
Read/Write at I/O Address 3B5h/3D5h
Index 18h
Group 3 Protection
D7 D6 D5 D4 D3 D2 D1 D0
7-0
Revision 1.2
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D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Data Latch n Bit 7
Data Latch n Bit 6
Data Latch n Bit 5
Data Latch n Bit 4
Data Latch n Bit 3
Data Latch n Bit 2
Data Latch n Bit 1
Data Latch n Bit 0
Reserved(0)
6-0
7
Reserved (0)
Index/Data
This bit may be used to read back the state of
the attribute controller index/data latch. This
latch indicates whether the next write to the
attribute controller at 3C0h will be to the
register index pointer or to an indexed
register.
Revision 1.2
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Register Name
GRX
GR00
GR01
GR02
GR03
GR04
GR05
GR06
GR07
GR08
Graphics Index
Set/Reset
EnableSet/Reset
Color Compare
DataRotate
Read Map Select
Graphics mode
Miscellaneous
Color Don't Care
Bit Mask
Index
Access
I/O
Address
Protect
Group
Page
00h
01h
02h
03h
04h
05h
06h
07h
08h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
3CEh
3CFh
3CFh
3CFh
3CFh
3CFh
3CFh
3CFh
3CFh
3CFh
1
1
1
1
1
1
1
1
1
1
81
81
82
82
83
83
84
86
86
87
GRAPHICSCONTROLLER
INDEX REGISTER (GRX)
Write only at I/O Address 3CEh
Group 1 Protection
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Index to Graphics
Controller Data
Registers
Set/Reset Bit 0
Set/Reset Bit 1
Set/Reset Bit 2
Set/Reset Bit 3
Reserved(0)
Reserved(0)
3-0
4-bitIndextoGraphicsControllerRegisters
7-4
Reserved (0)
7-4
Revision 1.2
81
Reserved (0)
65540 / 545
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
3-0
Reserved(0)
Reserved(0)
3-0
Reserved (0)
7-4
Revision 1.2
82
Reserved (0)
65540 / 545
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Rotate Count 0
Rotate Count 1
Rotate Count 2
Function Select
Reserved(0)
Reserved(0)
2-0
1-0
Function Select
These Function Select bits specify the logical
function performed on the contents of the
processor latches (loaded on a previous
CPU read cycle) before the data is written to
display memory. These bits operate as
follows:
Bit 4 Bit 3
0
0
0
1
7-5
Bit 1 Bit 0
0
0
0
1
1
0
1
1
7-2
MapSelected
Plane 0
Plane 1
Plane 2
Plane 3
Reserved (0)
Result
No change to the Data
Logical 'AND' between Data
and latched data
Logical 'OR' between Data
and latched data
Logical 'XOR' between Data
and latched data
Reserved (0)
Revision 1.2
83
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1
Write Mode
Reserved(0)
ReadMode
Odd/EvenMode
Shift Register Mode
Reserved(0)
1-0
Revision 1.2
0
0
Write Mode
1
0
Write Mode
Write mode 0. Each of the four
display memory planes is written
with the CPU data rotated by the
number of counts in the Rotate
Register, except when the
Set/Reset Register is enabled for
any of the four planes. When the
Set/Reset Register is enabled, the
corresponding plane is written
with the data stored in the
Set/Reset Register.
Reserved (0)
Read Mode
0
84
65540 / 545
Odd/Even Mode
0 All CPU addresses sequentially access all planes
1 Even CPU addresses access planes 0 and 2, while odd CPU addresses access planes 1 and 3. This
option is useful for compatibility with the IBM CGA memory organization.
6-5
65
Last Bit
Shifted
Out
Shift
Direction
Output
to:
00:
M0D0
M1D0
M2D0
M3D0
M0D1
M1D1
M2D1
M3D1
M0D2
M1D2
M2D2
M3D2
M0D3
M1D3
M2D3
M3D3
M0D4
M1D4
M2D4
M3D4
M0D5
M1D5
M2D5
M3D5
M0D6
M1D6
M2D6
M3D6
M0D7
M1D7
M2D7
M3D7
Bit 0
Bit 1
Bit 2
Bit 3
01:
M1D0
M1D1
M3D0
M3D1
M1D2
M1D3
M3D2
M3D3
M1D4
M1D5
M3D4
M3D5
M1D6
M1D7
M3D6
M3D7
M0D0
M0D1
M2D0
M2D1
M0D2
M0D3
M2D2
M2D3
M0D4
M0D5
M2D4
M2D5
M0D6
M0D7
M2D6
M2D7
Bit 0
Bit 1
Bit 2
Bit 3
1x:
M3D0
M3D1
M3D2
M3D3
M3D4
M3D5
M3D6
M3D7
M2D0
M2D1
M2D2
M2D3
M2D4
M2D5
M2D6
M2D7
M1D0
M1D1
M1D2
M1D3
M1D4
M1D5
M1D6
M1D7
M0D0
M0D1
M0D2
M0D3
M0D4
M0D5
M0D6
M0D7
Bit 0
Bit 1
Bit 2
Bit 3
Note:
If the Shift Register is not loaded every character clock (see SR01 bits 2&4) then the four 8-bit
shift registers are effectively 'chained' with the output of shift register 1 becoming the input to
shift register 0 and so on. This allows one to have a large monochrome (or 4 color) bit map and
display one portion thereof.
Note:
If XR28 bit-4 is set (8-bit video path), GR05 bit-6 must be set to 0:
1st Bit
Shifted
Out
M3D0
M3D1
M3D2
M3D3
M3D4
M3D5
M3D6
M3D7
M2D0
M2D1
M2D2
M2D3
M2D4
M2D5
M2D6
M2D7
M1D0
M1D1
M1D2
M1D3
M1D4
M1D5
M1D6
M1D7
M0D0
M0D1
M0D2
M0D3
M0D4
M0D5
M0D6
M0D7
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Reserved (0)
Revision 1.2
85
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D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Graphics/Text Mode
Chain Odd/Even Planes
Reserved(0)
Reserved(0)
Graphics/Text Mode
3-0
0 Text Mode
1 Graphics mode
1
7-4
Reserved (0)
7-4
Bit 2
0
1
0
1
CPU Address
A0000h-BFFFFh
A0000h-AFFFFh
B0000h-B7FFFh
B8000h-BFFFFh
Reserved (0)
Revision 1.2
86
65540 / 545
Bit Mask
0=Immune to change
1=Change permitted
7-0
Bit Mask
This bit mask is applicable to any data
written by the CPU, including that subject to
a rotate, logical function (AND, OR, XOR),
Set/Reset, and No Change. In order to
execute a proper read-modify-write cycle
into displayed memory, each byte must first
be read (and latched by the VGA), the Bit
Mask register set, and the new data then
written. The bit mask applies to all four
planes simultaneously.
0 The corresponding bit in each of the
four memory planes is written from
the corresponding bit in the latches
1 Unrestricted manipulation of the
corresponding data bit in each of the
four memory planes is permitted
Revision 1.2
87
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Revision 1.2
88
65540 / 545
Register Name
ARX
AR00-AR0F
AR10
AR11
AR12
AR13
AR14
DACMASK
DACSTATE
DACRX
DACX
DACDATA
Access
00-0Fh
10h
11h
12h
13h
14h
00-FFh
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
W
R/W
R/W
I/O
Protect
Address Group Page
3C0h
3C0h/3C1h
3C0h/3C1h
3C0h/3C1h
3C0h/3C1h
3C0h/3C1h
3C0h/3C1h
3C6h
3C7h
3C7h
3C8h
3C9h
1
1
1
1
1
1
1
6
6
6
6
89
90
90
91
91
92
92
93
93
94
94
94
ATTRIBUTE INDEX
REGISTER (ARX)
Read/Write at I/O Address 3C0h
Group 1 Protection
D7 D6 D5 D4 D3 D2 D1 D0
Index to
Attribute Controller
Data Registers
Enable Video
Reserved(0)
4-0
Index
7-6
89
Enable Video
0
Reserved (0)
65540 / 545
ATTRIBUTE CONTROLLER
COLOR REGISTERS (AR00-AR0F)
Read at I/O Address 3C1h
Write at I/O Address 3C0/1h
Index 00-0Fh
Group 1 Protection or XR63 bit-6
D7 D6 D5 D4 D3 D2 D1 D0
Blue
Green
Red
SecondaryBlue
SecondaryGreen
SecondaryRed
Color Value
Reserved (0)
Reserved (0)
ATTRIBUTE CONTROLLER
MODE CONTROL REGISTER (AR10)
Read at I/O Address 3C1h
Write at I/O Address 3C0/1h
Index 10h
Group 1 Protection
Text/Graphics Mode
Mono/Color Display
Select Background
Reserved(0)
Horizontal Split Screen
256 Color
Video Output 4-5 Select
Text/Graphics Mode
0 Select text mode
1 Select graphics mode
Monochrome/Color Display
0 Select color display attributes
1 Select mono display attributes
Revision 1.2
D7 D6 D5 D4 D3 D2 D1 D0
Reserved(0)
5-0
90
65540 / 545
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Color Plane 0 Enable
Color Plane 1 Enable
Color Plane 2 Enable
Color Plane 3 Enable
Overscan Color
Display Status Select
Reserved(0)
7-0
Overscan Color
3-0
5-4
7-6
Revision 1.2
91
Status Register 1
Bit 5 Bit 4
P2
P0
P5
P4
P3
P1
P7
P6
Reserved (0)
65540 / 545
ATTRIBUTE CONTROLLER
PIXEL PAD REGISTER (AR14)
Read at I/O Address 3C1h
Write At I/O Address 3C0/1h
Index 14h
Group 1 Protection
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
3-0
Horizontal
Pixel Panning
Reserved(0)
Reserved(0)
1-0
AR13
0
1
2
3
4
5
6
7
8
7-4
3-2
7-4
Reserved (0)
Reserved (0)
Revision 1.2
92
65540 / 545
COLOR PALETTE
PIXEL MASK REGISTER (DACMASK)
Read/Write at I/O Address 3C6h
Group 6 Protection
COLOR PALETTE
STATE REGISTER (DACSTATE)
Read only at I/O Address 3C7h
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Pixel Mask Bit-0
Pixel Mask Bit-1
Pixel Mask Bit-2
Pixel Mask Bit-3
Pixel Mask Bit-4
Pixel Mask Bit-5
Pixel Mask Bit-6
Pixel Mask Bit-7
Palette State 0
Palette State 1
Reserved(0)
1-0
7-2
Reserved (0)
Revision 1.2
93
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COLOR PALETTE
READ-MODE INDEX REGISTER (DACRX)
Write only at I/O Address 3C7h
Group 6 Protection
COLOR PALETTE
INDEX REGISTER (DACX)
Read/Write at I/O Address 3C8h
Group 6 Protection
D7 D6 D5 D4 D3 D2 D1 D0
Color Palette Index 0
Color Palette Index 1
Color Palette Index 2
Color Palette Index 3
Color Palette Index 4
Color Palette Index 5
Color Palette Index 6
Color Palette Index 7
COLOR PALETTE
DATA REGISTERS (DACDATA 00-FF)
Read/Write at I/O Address 3C9h Index 00h-FFh
Group 6 Protection
D7 D6 D5 D4 D3 D2 D1 D0
Access
1st
2nd
3rd
Red 0
Green 0
Blue 0
Red 1
Green 1
Blue 1
Red 2
Green 2
Blue 2
Red 3
Green 3
Blue 3
Red 4
Green 4
Blue 4
Red 5
Green 5
Blue 5
Reserved (0)
Revision 1.2
94
65540 / 545
Extension Registers
Extension Registers
Register
Mnemonic
XRX
Register
Group
--
Index
--
I/O
Access
R/W
XR00
XR01
XR02
XR03
XR04
XR05
XR06
XR0E
XR28
XR29
XR70
XR72
XR73
XR7D
XR7F
Misc
Misc
Misc
Misc
Misc
Misc
Misc
Misc
Misc
Misc
Misc
Misc
Misc
Misc
Misc
Chip Version
(65540: v=0; 65545: v=1)
Configuration
CPU Interface Control 1
CPU Interface Control 2
Memory Control 1
Memory Control 2
Palette Control
Text Mode Control
VideoInterface
Half Line Compare
Setup / Disable Control
External Device I/O
DPMS Control
Diagnostic (65545 Only)
Diagnostic
00h
01h
02h
03h
04h
05h
06h
0Eh
28h
29h
70h
72h
73h
7Dh
7Fh
RO
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
3D7h
3D7h
3D7h
3D7h
3D7h
3D7h
3D7h
3D7h
3D7h
3D7h
3D7h
3D7h
3D7h
3D7h
3D7h
1101v r r r
dddddddd
00000000
- - - - - - 0x
- - 0 - - 000
00000000
00000000
000000 - 0000 - - 0 xxxxxxxx
0------0000000
00 - - 0000
0------00xxxx00
97
98
99
100
101
102
103
106
117
117
150
151
152
152
153
XR07
XR08
XR0B
XR0C
XR10
XR11
Mapping
Mapping
Mapping
Mapping
Mapping
Mapping
07h
08h
0Bh
0Ch
10h
11h
R/W
R/W
R/W
R/W
R/W
R/W
3D7h
3D7h
3D7h
3D7h
3D7h
3D7h
11110100
xxxxxxxx
- - 00 000
- - - - - - xx
xxxxxxxx
xxxxxxxx
104
104
105
105
108
108
XR0F
XR2B
XR44
XR45
Software Flags
Software Flags
Software Flags
Software Flags
Software Flags 0
Software Flags 1
Software Flags 2
Software Flags 3
0Fh
2Bh
44h
45h
R/W
R/W
R/W
R/W
3D7h
3D7h
3D7h
3D7h
xxxxxxxx
00000000
xxxxxxxx
xxxxxxxx
107
118
127
127
XR14
XR15
XR1F
XR7E
Compatibility
Compatibility
Compatibility
Compatibility
Emulation Mode
Write Protect
Virtual EGA Switch
CGA/Hercules Color Select
14h
15h
1Fh
7Eh
R/W
R/W
R/W
R/W
3D7h
3D7h
3D7h
3D7h
0000hh00
00000000
0 - - - xxxx
- - xxxxxx
109
110
115
153
XR30
XR31
XR32
XR33
Clock
Clock
Clock
Clock
30h
31h
32h
33h
R/W
R/W
R/W
R/W
3D7h
3D7h
3D7h
3D7h
x
x
00
xx
xx
xx
00
121
122
122
123
XR3A
XR3B
XR3C
XR3D
XR3E
XR3F
MultiMedia
MultiMedia
MultiMedia
MultiMedia
MultiMedia
MultiMedia
Color Key 0
Color Key 1
Color Key 2
Color Key Mask 0
Color Key Mask 1
Color Key Mask 2
3Ah
3Bh
3Ch
3Dh
3Eh
3Fh
R/W
R/W
R/W
R/W
R/W
R/W
3D7h
3D7h
3D7h
3D7h
3D7h
3D7h
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
124
124
125
125
126
126
XR40
BitBLT
40h
R/W
3D7h
- - - - - - xx
127
Reset Codes:
x
d
h
r
Revision 1.2
=
=
=
=
95
State After
Address
Reset
3D6h - x x x x x x x
xx
xxxx
xxxx
00 0
Page
97
65540 / 545
Extension Registers
Register
Group
Alternate
Alternate
Alternate
Alternate
Alternate
Alternate
Alternate
Alternate
Alternate
Alternate
Alternate
Alternate
Alternate
Alternate
Alternate
Alternate
Alternate
Index
0Dh
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
24h
25h
26h
64h
65h
66h
67h
I/O
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XR2C
XR2D
XR2E
XR2F
XR4F
XR50
XR51
XR52
XR53
XR54
XR55
XR56
XR57
XR58
XR59
XR5A
XR5B
XR5C
XR5D
XR5E
XR5F
XR60
XR61
XR62
XR63
XR68
XR6C
XR6E
XR6F
Flat Panel
Flat Panel
Flat Panel
Flat Panel
Flat Panel
Flat Panel
Flat Panel
Flat Panel
Flat Panel
Flat Panel
Flat Panel
Flat Panel
Flat Panel
Flat Panel
Flat Panel
Flat Panel
Flat Panel
Flat Panel
Flat Panel
Flat Panel
Flat Panel
Flat Panel
Flat Panel
Flat Panel
Flat Panel
Flat Panel
Flat Panel
Flat Panel
Flat Panel
FLM Delay
LP Delay (Comp Enabled)
LP Delay (Comp Disabled)
LP Width
Panel Format 2
Panel Format 1
Display Type
Power Down Control
Panel Format 3
PanelInterface
Horizontal Compensation
Horizontal Centering
Vertical Compensation
Vertical Centering
Vertical Line Insertion
Vertical Line Replication
Panel Power Sequencing Delay
Activity Indicator Control
FP Diagnostic
M (ACDCLK) Control
Power Down Mode Refresh
Blink Rate Control
SmartMap Control
SmartMap Shift Parameter
SmartMap Color Mapping Control
Vertical Panel Size
Programmable Output Drive
Polynomial FRC Control
Frame Buffer Control
2Ch
2Dh
2Eh
2Fh
4Fh
50h
51h
52h
53h
54h
55h
56h
57h
58h
59h
5Ah
5Bh
5Ch
5Dh
5Eh
5Fh
60h
61h
62h
63h
68h
6Ch
6Eh
6Fh
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Codes:
x
d
h
r
Revision 1.2
=
=
=
=
96
State After
Address
Reset
3D7h - - - - - - x x
3D7h 0 0 0 0 0
3D7h 0 0 0 0 0 0 0
3D7h x x x x x x x x
3D7h x x x x x x x x
3D7h x x x x x x x x
3D7h x x x x x x x x
3D7h x x x x x x x x
3D7h 0 x x x x x x x
3D7h x x x x x x x x
3D7h x x x x x
3D7h x x x x x x x x
3D7h x x x x x x x x
3D7h x x x x x x x x
3D7h x x x x x x
3D7h x x x x x x x x
3D7h x x x x
3D7h
3D7h
3D7h
3D7h
3D7h
3D7h
3D7h
3D7h
3D7h
3D7h
3D7h
3D7h
3D7h
3D7h
3D7h
3D7h
3D7h
3D7h
3D7h
3D7h
3D7h
3D7h
3D7h
3D7h
3D7h
3D7h
3D7h
3D7h
3D7h
xx
xx
xx
xx
xx
xx
00
00
0
xx
xx
xx
xx
xx
xx
10
0x
00
xx
xx
10
xx
xx
x1
xx
10
00
xxxx
xxxx
xxxx
xxxx
x
xxxx
0 00
0000
0000
xxxx
x x
xxxx
xxxx
xxxx
x xx
xx
0000
xxx
0000
xxxx
xxxx
0000
xxxx
xxxx
xxxx
xxxx
0000
1111
0000
xx
xx
xx
xx
xx
xx
00
01
x0
xx
xx
xx
xx
xx
xx
xx
01
xx
00
xx
xx
11
xx
xx
xx
xx
d
01
00
Page
106
111
111
112
112
113
113
114
114
115
116
116
116
145
145
146
146
118
119
119
120
128
129
130
131
132
133
134
135
136
137
137
138
138
139
140
141
141
142
143
144
144
147
147
148
149
65540 / 545
Extension Registers
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Chip Revision
Index to
Extension Registers
- 0=65540, 1=65545
6-0
7
7-0
Reserved (0)
Revision 1.2
97
65540 / 545
Extension Registers
D7 D6 D5 D4 D3 D2 D1 D0
CFG0 / LB#: Bus Type
CFG1 / ISA#: Bus Type
CFG2 / 2X#: Bus Type
CFG3: Reserved
CFG4: Reserved (do not use)
CFG5 / OS#: Osc Src Select
CFG6 / AD#: A26-27 Ena
CFG7 / TS#: Clk Test Ena
L
L
H
H
L
H
L
H
Bus Type
Reserved
Reserved
Reserved
CPU Direct (2x LCLK)
(pin-23=CRESET)
Reserved
ISA Bus
PCI Bus (65545 only)
VL-Bus (1x clk)
(pin-23=RDYRTN#)
CFG3 - Reserved
The pin corresponding to this bit has no
internal hardware function so may be used
for sampling external conditions at reset.
CFG4 - Reserved
The pin corresponding to this bit must be
sampled high on reset so this bit will always
read back 1.
Revision 1.2
98
65540 / 545
Extension Registers
4-3
Revision 1.2
99
65540 / 545
Extension Registers
D7 D6 D5 D4 D3 D2 D1 D0
7-6
Reserved(0)
Palette RDY Response
Diagnostic (Set to 0)
Reserved(0)
3-2
4
100
65540 / 545
Extension Registers
D7 D6 D5 D4 D3 D2 D1 D0
2
Memory Configuration
Memory Wraparound Ctrl
Reserved(0)
Write Buffer Enable
4-3
Reserved(0)
1-0
Memory Configuration
00 32-bit memory data path. Memory
data bus is on MAD15-0 & MBD15-0
(DRAMs A and B). If frame acceleration is enabled and embedded frame
buffer is selected, the data will be
stored in both DRAMs A and B. An
external frame buffer can be enabled
on DRAM C with this setting.
01 16-bit data path (DRAM A only).
The memory data bus is on MAD15-0.
If frame acceleration is enabled and
embedded frame buffer is selected, the
data will be restricted to storage in
DRAM A only. An external frame
buffer can be enabled on DRAM C
with this setting.
10 32-bit memory data path. Memory
data bus is on MAD15-0 & MCD15-0
(DRAMs A & C). DRAM C cannot
be used as an external frame buffer
with this setting, but programming can
select between this setting and '01' to
switch the function of DRAM C
between use as display memory and
use as an external frame buffer.
11 Reserved
1
7-6
Reserved (0)
Revision 1.2
101
65540 / 545
Extension Registers
D7 D6 D5 D4 D3 D2 D1 D0
Disable Long CPU Cycles
CPU Access CAS# Ctrl
Display Access CAS# Ctrl
DRAM CAS# Address
Memory CAS/WE Select
Frame Buffr CAS/WE Slct
PC Video Interface Enable
PC Video Interface Width
0
1
6
1
2
102
65540 / 545
Extension Registers
D7 D6 D5 D4 D3 D2 D1 D0
Pixel Out Diagnostic Mode
Internal DAC Disable
7-6
3-2
Revision 1.2
103
65540 / 545
Extension Registers
LINEARADDRESSINGBASEREGISTER(XR08)
Read/Write at I/O Address 3B7h/3D7h
Index 08h
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
70
7-0
104
65540 / 545
Extension Registers
D7 D6 D5 D4 D3 D2 D1 D0
Memory Mapping Mode
Single/Dual Map
CPU Address Divide by 4
Extended Text Mode (545)
Linear Addressing Enable
7-5
Reserved(0)
Revision 1.2
Reserved(0)
1-0
7-2
105
Reserved (0)
65540 / 545
Extension Registers
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
LSB of Offset (CR13)
LSB of Alt Offset (XR1E)
Reserved(0)
Cursor Blink Disable
Cursor Style
Reserved(0)
Reserved (0)
Cursor Mode
0
1
7-2
1-0
Cursor Style
0
1
6-4
Reserved (0)
Revision 1.2
106
65540 / 545
Extension Registers
Memory Size
00 256KB
01 512KB
1x 1MB
2-3
4
Reserved (0)
Hi Color / True Color
0
1
Interlace Select
0
1
107
65540 / 545
Extension Registers
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Higher Map
Base Address Bits 17-10
7-0
Revision 1.2
Low Map
A0000-AFFFF
A0000-A7FFF
B0000-B7FFF Single mapping only
B8000-BFFFF Single mapping only
108
High Map
B0000-BFFFF
A8000-AFFFF
Don't care
Don't care
65540 / 545
Extension Registers
D7 D6 D5 D4 D3 D2 D1 D0
Emulation Mode
1-0
Emulation Mode
00
01
10
11
3-2
Bit-7=0
3-state
3-state
3-state
Bit-7=1
3-state
Low
High
Revision 1.2
109
65540 / 545
Extension Registers
D7 D6 D5 D4 D3 D2 D1 D0
Revision 1.2
110
65540 / 545
Extension Registers
HORIZONTALOVERFLOWREGISTER(XR17)
Read/Write at I/O Address 3D7h
Index 17h
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Vertical Total Bit 10
Vertical Display End Bit 10
Vertical Sync Start Bit 10
Reserved(R/W)
Vertical Blank Start Bit 10
Reserved(R/W)
Line Compare Bit 10
Reserved(R/W)
Reserved (R/W)
Reserved (R/W)
Reserved (R/W)
Reserved (R/W)
Revision 1.2
111
65540 / 545
Extension Registers
ALTERNATEHORIZONTAL
DISPLAY END REGISTER (XR18)
Read/Write at I/O Address 3D7h
Index 18h
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
FP HSync Start
7-0
Revision 1.2
112
65540 / 545
Extension Registers
ALTERNATEHORIZONTALTOTALREGISTER
(XR1B)
Read/Write at I/O Address 3D7h
Index 1Bh
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
FP H Sync End
FP H Total
7-0
Reserved (0)
Revision 1.2
113
65540 / 545
Extension Registers
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
H Blank End
H Blank Start
(Horizontal Panel Size)
DE Skew Control
Split Screen Enhance
4-0
CRTAlternateDisplayEnableSkewControl
See CR03 for description
or
7-0
Revision 1.2
114
65540 / 545
Extension Registers
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
3-0
Alternate Offset
See CR13 for description
Programmed Value = Actual Value 1
Misc 3-2
00
01
10
11
6-4
Reserved (0)
Sense Select
0
Revision 1.2
115
65540 / 545
Extension Registers
ALTERNATE MAXIMUM
SCANLINE REGISTER (XR24)
Read/Write at I/O Address 3D7h
Index 24h
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
4-0
Reserved (R/W)
AltText Mode
H Virtual Panel Size
Revision 1.2
116
65540 / 545
Extension Registers
D7 D6 D5 D4 D3 D2 D1 D0
Reserved(0)
Blank#/DE Select
Reserved(0)
256-Color Video Path
InterlaceMode
8-Bit Video Pixel Panning
Tall Font Replication
Reserved (0)
0
1
Half-Line Compare
Reserved (0)
Interlace Video
This bit is effective only for CRT graphics
mode. This bit should be programmed to 0
for flat panel. In interlace mode XR29 holds
the half-line positioning of VSync for odd
frames.
0 Non-interlaced video (default on reset)
1 Interlaced video
Revision 1.2
7-0
117
65540 / 545
Extension Registers
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Flag 0
Flag 1
Flag 2
FLM Delay
Flag 3
Flag 4
Flag 5
Flag 6
Flag 7
Display Mode
7-0
Revision 1.2
118
65540 / 545
Extension Registers
LPDELAY REGISTER(CMPRENABLED)(XR2D)
Read/Write at I/O Address 3D7h
Index 2Dh
LP
DELAYREGISTER (CMPRDISABLED)(XR2E)
Read/Write at I/O Address 3D7hIndex 2Eh
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
LP Delay
(graphics mode horizontal
compression enabled)
LP Delay
(graphics mode horizontal
compression disabled)
7-0
LP Delay
LP Delay
Revision 1.2
119
65540 / 545
Extension Registers
LP Width
LP Delay (XR2E) Bit-8
LP Delay (XR2D) Bit-8
LP Delay Disable
FLM Delay Disable
LP Width (HWidth)
These bits define the width of LP output
pulse in terms of number of character (8-dot
only) clocks in flat panel mode.
Programmed Value = Actual Value 1
LP Delay Disable
0 LP Delay Enable: XR2D and XR2F
bit-5 (or XR2E and XR2F bit-4) are
used to delay the LP active edge with
respect to the FP Blank inactive edge.
1 LP Delay Disable: LP active edge will
coincide with the FP Blank inactive
edge.
Revision 1.2
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Extension Registers
Reserved(R/W)
31
Divide by 4
Divide by 1
74
Divide by 1
Divide by 2
Divide by 4
Divide by 8
Divide by 16
Divide by 32
Divide by 64
Divide by 128
Reserved (R/W)
Revision 1.2
121
65540 / 545
Extension Registers
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
M-Divisor Value
N-Divisor
Reserved(R/W)
Reserved(R/W)
VCO M-Divisor
60
Reserved (R/W)
Revision 1.2
VCO N-Divisor
122
Reserved (R/W)
65540 / 545
Extension Registers
D7 D6 D5 D4 D3 D2 D1 D0
VCLK VCO Powerdown
MCLK VCO Powerdown
Oscillator Powerdown
Reserved(R/W)
Video Clock Select
CLK Reg Program Pointer
Power Sequencing Clock
Clock Mode Control
Oscillator Powerdown
Reserved (R/W)
Revision 1.2
123
65540 / 545
Extension Registers
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
7-0
7-0
These bits are compared to the least significant 8 bits of the background video stream.
If a match occurs on all enabled bits (see
Color Compare Mask Register XR3D) and
the key is enabled (XR06[4]), external
video is sent to the screen. External video is
input on the MCD15:0, CASCH# and
CASCL# pins (and CA8-9, ACTI,
ENABKL, AA9, and OEC# if 24-bit
external
video
input
is
enabled
(XR05[7]=1)). The logical masking and
compare operations are described in the
functional description.
The color comparison occurs before the
RAMDAC. In 4BPP and 8BPP modes
using palette LUT data, the LUT index is
used in the comparison, not the 18BPP LUT
data.
Revision 1.2
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Extension Registers
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
7-0
7-0
Revision 1.2
125
65540 / 545
Extension Registers
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
7-0
7-0
Revision 1.2
126
65540 / 545
Extension Registers
3-0
D7 D6 D5 D4 D3 D2 D1 D0
BitBLT Draw Mode
Reserved(0)
7-5
10
D7 D6 D5 D4 D3 D2 D1 D0
Flag 0
Reserved ( 0 )
Flag 1
Flag 2
Flag 3
Flag 4
Flag 5
Flag 6
Flag 7
D7 D6 D5 D4 D3 D2 D1 D0
7-0
Flags ( Reserved )
Reserved(0)
Revision 1.2
127
65540 / 545
Extension Registers
001
010
011
100
The setting programmed into this field determines how many most-significant color-bits
/ pixel are used to generate flat panel video
data. In general, 8 bits of monochrome data
or 8 bits/color of RGB color data enter the
flat panel logic for every dot clock. Not all
of these bits, however, are used to generate
output colors / gray scales, depending on the
type of panel used, graphics / text mode, and
the gray-scaling algorithm chosen (the actual
number of bits used is indicated in the table
above). If the VGA palette is used then a
maximum of 6 bits/pixel (bits 7-2) (setting
'110') should be used. If the VGA palette is
bypassed then a maximum of 8 bits/pixel
(bits 7-0) (setting '111) may be used. With
2-frame and 16-frame FRC, settings not
listed in the tables above are undefined.
Also note that settings which achieve higher
gray / color levels may not necessarily
produce acceptable display quality on some
(or any) currently available panels. This
document contains recommended settings
for various popular panels that Chips &
Technologies has found to produce
acceptable results with those panels.
Customers may modify these settings to
achieve a better match with their requirements.
Reserved(R/W)
M Functionality Select
LP Functionality Select
010
011
100
101
Revision 1.2
16-Frame FRC
(Color or Monochrome STN Panels)
# of msbs
Gray /
Gray /
Used
Color
Color
to Generate
Levels
Levels
Gray / Color without
with
Levels
Dithering Dithering
1
2
5
2
4
13
3
8
29
4
16
61
2-Frame FRC
(Color TFT or Monochrome Panels)
# of msbs
Gray /
Gray /
Used
Color
Color
to Generate
Levels
Levels
Gray / Color without
with
Levels
Dithering Dithering
1
3
9
2
5
25
3
15
57
4
31
121
3-5
128
Reserved (R/W)
M Pin Select
0 M signal goes to the M pin (default on
reset)
1 FP Display Enable (FP Blank#) signal
goes to the M pin. Polarity is
controlled by XR54[0].
LP Pin Select
0 FP HSync (LP) signal goes to the LP
pin.
Polarity is controlled by
XR54[6] (default on reset).
1 FP Display Enable (FP Blank#) signal
goes to the LP pin. Polarity is
controlled by XR54[0].
65540 / 545
Extension Registers
6-4
Clock Divide ( CD )
These bits specify the frequency ratio
between the dot clock and the flat panel shift
clock (SHFCLK) signal.
000 Shift Clock Freq = Dot Clock Freq.
This setting is used to output 1 pixel
per shift clock with a maximum of 8
bpp (bits/pixel) for single drive
monochrome panels. For double drive
color panels, this setting is used to
output 2 2/3 4-bit pack pixels. FRC
and dithering may be enabled.
001 Shift Clk Freq = 1/2 Dot Clock Freq.
This setting is used to output 2 pixels
per shift clock with a maximum of 8
bits/pixel for single drive monochrome
panels and 4 bpp for single drive color
panels. For double drive color panels,
this setting is used to output 5-1/3 4bit pack pixels. FRC and dithering
can be enabled.
010 Shift Clk Freq = 1/4 Dot Clock Freq.
This setting is used to output 4 pixels
per shift clock with a maximum of 4
bpp for single drive mono panels and
2 bits/pixel for single drive color
panels. For single drive color panels
this setting is used to output 5-1/3 4bit pack pixels. For double drive
monochrome panels, this setting is
used to output 8 pixels per shift clock
with 1 bit/pixel. FRC and dithering
can be enabled.
011 Shift Clk Freq = 1/8 Dot Clock Freq.
This setting is used to output 8 pixels
per shift clock with a maximum of 2
bpp for single drive mono panels and
1 bit/pixel for single drive color
panels.
For double drive mono
panels, this setting is also used to
output 16 pixels per shift clock with 1
bit/pixel. FRC and dithering can be
enabled.
100 Shift Clk Freq = 1/16 Dot Clock Freq.
This setting is used to output 16 pixels
per shift clock with maximum of 1
bit/pixel for single drive monochrome
panels. Dithering can also be enabled.
D7 D6 D5 D4 D3 D2 D1 D0
Frame Rate Control
Dither Enable
Clock Divide
TFT Panel Data Width
3-2
Revision 1.2
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Extension Registers
D7 D6 D5 D4 D3 D2 D1 D0
1
Panel Type
Display Type
Shift Clock Divide
Reserved(R/W)
Shift Clock Mask
Enable FP Compensation
LP During V Blank
1-0
0
1
7
Disable FP compensation
Enable FP compensation
Reserved (R/W)
Revision 1.2
130
65540 / 545
Extension Registers
D7 D6 D5 D4 D3 D2 D1 D0
2-0
These bits specify the number of memory refresh cycles to be performed per scanline. A
minimum value of 1 should be programmed
in this register.
3
Revision 1.2
131
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Extension Registers
FRC Option 3
This bit affects 2-frame FRC only
0
1
D7 D6 D5 D4 D3 D2 D1 D0
Reserved (R/W)
AlternateLineGraphicsCharacterControl
This bit is effective only if bit-0 = 1.
0
1
5-4
Revision 1.2
132
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Extension Registers
3-2
D7 D6 D5 D4 D3 D2 D1 D0
FP Blank Polarity
FP Blank Select
5-4
FP Feature Control
FP LP Polarity
FP FLM Polarity
0
1
FP Blank Polarity
7
0
1
FP Clock Select
Positive polarity
Negative polarity
Positive polarity
Negative polarity
Positive polarity
Negative polarity
FP Blank Select
This bit controls the BLANK# pin output in
flat panel mode. In CRT mode, XR28 bit-1
controls the BLANK# output. This bit also
affects operation of the flat panel video
logic, generation of the FP HSync (LP)
pulse signals, and masking of the Shift
Clock.
0
Revision 1.2
133
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Extension Registers
4-3
5
Reserved (R/W)
Enable Automatic Horizontal Doubling
(EAHD)(this bit is effective if bit-0 is 1)
0
D7 D6 D5 D4 D3 D2 D1 D0
Ena H Compensation
Ena H Auto Centering
Ena H Compression
Reserved(R/W)
Ena Auto H Doubling
Alternate HSync Polarity
Alternate VSync Polarity
0
1
1
EnableHorizontalCompensation(EHCP)
Positive
Negative
Positive
Negative
EnableTextModeHorizontalCompression
(ETHC)(this bit is effective only if bit-0 is 1
in flat panel text mode). Setting this bit will
turn on text mode horizontal compression regardless of horizontal display width or
horizontal panel size.
0
1
Revision 1.2
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Extension Registers
HORIZONTALCENTERINGREGISTER(XR56)
Read/Write at I/O Address 3D7h
Index 56h
D7 D6 D5 D4 D3 D2 D1 D0
LeftBorder
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Extension Registers
VERTICALCOMPENSATIONREGISTER(XR57)
Read/Write at I/O Address 3D7h
Index 57h
4-3
D7 D6 D5 D4 D3 D2 D1 D0
Enable V Compensation
Enable Auto V Centering
Enable Text V Stretching
Text V Stretch Method
Enable Gr V Stretching
Gr V Stretch Method
Disable Fast Centering
0
1
6
Enable
non-automatic
vertical
centering. The Vertical Centering
Register is used to specify the top
border. If no centering is desired then
the Vertical Centering Register can be
programmed to 0.
Enable automatic vertical centering.
Vertical top and bottom borders will
be computed automatically.
Revision 1.2
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Extension Registers
VERTICALLINEINSERTIONREGISTER(XR59)
Read/Write at I/O Address 3D7h
Index 59h
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Reserved(0)
Top Border Bits 8-9
Hardware Line Replication
3-0
Programmed value:
This register contains the eight least significant bits of the programmed value of the
Vertical Top Border (VTB). The two most
significant bits are in the Vertical Line
Insertion Register (XR59).
Reserved (0)
Vertical Top Border MSBs (VTB9-8)
This register contains the two most significant bits of the programmed value of the
Vertical Top Border (VTB). The eight least
significant bits are in the Vertical Centering
Register (XR58).
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Extension Registers
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Reserved(R/W)
Delay on Power Up
3-0
Reserved (R/W)
7-4
Power Up Delay
Programmable value of panel power
sequencing during power up. This value can
be programmed up to 54 milliseconds in
increments of 3.4 milliseconds. A value of
0 is undefined.
Revision 1.2
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Extension Registers
ACTIVITYTIMERCONTROLREGISTER(XR5C)
Read/Write at I/O Address 3D7h
Index 5Ch
D7 D6 D5 D4 D3 D2 D1 D0
Reserved(R/W)
Activity Timer Action
Enable Activity Timer
Reserved (R/W)
Revision 1.2
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Extension Registers
D7 D6 D5 D4 D3 D2 D1 D0
6
Enable Palette Powerdown
Enable Access in PNLOFF
Enable Activity Timer Test
Force 16-bit Local Bus
Disable Vertical Comp
18-bit Color Test Mode
HSync/VSync Deactivation
Enable Palette Powerdown
1
1
EnablePalettePowerdowninBypassMode
0
1
Revision 1.2
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Extension Registers
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
M (ACDCLK) Count
Power Down Refresh Freq
M (ACDCLK) Control
7-0
M ( ACDCLK ) Control
0
1
3210
0000
0001
0010
0011
0100
0101
0110
0111
1000
Revision 1.2
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Extension Registers
7-6
6
0
1
0
1
Character Blink
Duty Cycle
50%
25%
50%
(default on Reset)
75%
Revision 1.2
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Extension Registers
4-1
D7 D6 D5 D4 D3 D2 D1 D0
SmartMap Enable
SmartMap Threshold
SmartMap Saturation
Text Enhancement
Text Video Output Polarity
SmartMap Enable
0
Output
Out0
Out1
Out2
Out3
Out4
Out5
Text Enhancement
This bit is used only in flat panel text mode.
0
1
Normal text
Text attribute 07h and 0Fh are
reversed to maximize the brightness of
the normal DOS prompt
Revision 1.2
SmartMap Saturation
This bit is used only in flat panel text mode
when SmartMap is enabled (bit-0 = 1). It
selects the clamping level after the color
addition/subtraction.
SmartMap Threshold
Normal polarity
Inverted polarity
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Extension Registers
SMARTMAPCOLORMAPPINGCONTROL
REGISTER(XR63)
Read/Write at I/O Address 3D7h
Index 63h
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Foreground Shift
Color Threshold
Background Shift
New Text Enhancement
Gr Video Output Polarity
5-0
Foreground Shift
These bits define the number of levels that
the foreground color is shifted when the
foreground and background colors are closer
than the SmartMap Threshold (XR61 bits
1-4). If the foreground color is "greater"
than the background color, then this field is
added to the foreground color. If the
foreground color is "smaller" than the
background color, then this field is subtracted from the foreground color.
7-4
Background Shift
These bits define the number of levels that
the background color is shifted when the
foreground and background colors are closer
than the SmartMap Threshold (XR61 bits
1-4). If the background color is "greater"
than the foreground color, then this field is
added to the background color. If the
background color is "smaller" than the
foreground color, then this field is subtracted from the background color.
Revision 1.2
Color Threshold
Normal polarity
Inverted polarity
Note:
Text video output polarity is
controlled by XR61 bit-7 (TVP).
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Extension Registers
FP ALTERNATE OVERFLOW
REGISTER (XR65)
Read/Write at I/O Address 3D7h
Index 65h
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
FP Alt V Total Bit-8
FP V Panel Size Bit-8
FP Alt VSync Start Bit-8
Reserved (R/W)
FP Alternate V Total
Reserved (R/W)
FP Alt V Total Bit-9
FP Alt Panel Size Bit-9
FP Alt VSync Start Bit-9
Reserved (R/W)
Reserved (R/W)
Revision 1.2
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Extension Registers
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
3-0
Revision 1.2
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Reserved (R/W)
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Extension Registers
PROGRAMMABLEOUTPUTDRIVEREGISTER
(XR6C)
Read/Write at I/O Address 3B7h/3D7h
Index 6Ch
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Reserved(R/W)
CFG8/LV#: Vcc Select
Flat Panel Output Drive
Bus Interface Output Drive
Mem Intfc A&B Out Drive
Mem Intfc C Out Drive
Reserved(R/W)
Revision 1.2
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Extension Registers
7-4
Revision 1.2
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Extension Registers
FRAMEBUFFERCONTROLREGISTER(XR6F)
Read/Write at I/O Address 3D7h
Index 6Fh
D7 D6 D5 D4 D3 D2 D1 D0
Frame Buffer Enable
Frame Accelerator Enable
DRAM C Asym addr select
5-3
6
0
1
Revision 1.2
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Extension Registers
SETUP/DISABLECONTROLREGISTER(XR70)
Read/Write at I/O Address 3D7h
Index 70h
D7 D6 D5 D4 D3 D2 D1 D0
Reserved(0)
6-0
7
Reserved (0)
3C3 / 46E8 Register Disable
0
Revision 1.2
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Extension Registers
D7 D6 D5 D4 D3 D2 D1 D0
Reserved(R/W)
ENAVEE Pin Control
GPIO0 (ACTI) Data
7-6
Reserved (R/W)
4-3
Revision 1.2
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Extension Registers
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
HSYNC Data
HSYNC Control
VSYNC Data
VSYNC Control
Reserved(0)
Reserved(0)
BitBLT Clock Control
V
Active
Active
Inactive
Inactive
6-0
7
HSYNC Data
If bit-1 of this register is programmed to 1,
the state of this bit (XR73[0]) will be output
on HSYNC (pin 65).
HSYNC Control
Determines whether bit-0 of this register or
internal CRTC horizontal sync information
is output on HSYNC (pin 65).
Reserved (0)
VSYNC Data
If bit-3 of this register is programmed to 1,
the state of this bit (XR73[2]) will be output
on VSYNC (pin 64).
VSYNC Control
Determines whether bit-2 of this register or
internal CRTC vertical sync information is
output on VSYNC (pin 64).
0 CRTC VSYNC is output (Default)
1 XR73[2] is output
7-4
Reserved (0)
Revision 1.2
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Extension Registers
CGA/HERCCOLORSELECTREGISTER(XR7E)
Read/Write at I/O Address 3D7h
Index 7Eh
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Color Bit-0 (Blue)
Color Bit-1 (Green)
Color Bit-2 (Red)
Color Bit-3 (Intensity)
Intensity Enable
Color Set Select
3-State Control
Test Function
Test Function Enable
Special Test Function
Reserved(0)
7-6
Reserved (0)
5-2
Test Function
These bits are used for internal testing of the
chip when bit-6 = 1.
Revision 1.2
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Extension Registers
Revision 1.2
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32-Bit Registers
32-Bit Registers
( 65545 Only )
Register Register Extension
MnemonicGroup RegisterName
Access
I/O
Type Address
State After
Reset
Page
DR00
DR01
DR02
DR03
DR04
DR05
DR06
DR07
BitBLT
BitBLT
BitBLT
BitBLT
BitBLT
BitBLT
BitBLT
BitBLT
BitBLT Offset
16/32-bit
BitBLT Pattern ROP 16/32-bit
BitBLT BG Color 16/32-bit
BitBLT FG Color
16/32-bit
BitBLT Control
16/32-bit
BitBLT Source
16/32-bit
BitBLT Destination 16/32-bit
BitBLT Command 16/32-bit
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
83D0-3
87D0-3
8BD0-3
8FD0-3
93D0-3
97D0-3
9BD0-3
9FD0-3
- - - - xxxx
-------xxxxxxxx
xxxxxxxx
---------------------- - - - 0000
xxxxxxxx
- - - xxxxx
xxxxxxxx
xxxxxxxx
- - - 0xxxx
- - - xxxxx
- - - xxxxx
00000000
- - - - xxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
- - - - xxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
156
156
157
157
158
159
159
160
DR08
DR09
DR0A
DR0B
DR0C
Cursor
Cursor
Cursor
Cursor
Cursor
Cursor Control
Cursor Color 0-1
Cursor Color 2-3
Cursor Position
Cursor Base Address
R/W
R/W
R/W
R/W
R/W
A3D0-3
A7D0-3
ABD0-3
AFD0-3
B3D0-3
-------xxxxxxxx
xxxxxxxx
x - - - - xxx
--------
-------xxxxxxxx
xxxxxxxx
xxxxxxxx
- - - - xxxx
0000
xxxxxxxx
xxxxxxxx
x - - - - xxx
xxxxxx - -
000 00
xxxxxxxx
xxxxxxxx
xxxxxxxx
--------
161
162
162
163
164
Reset Codes:
x
d
h
r
Revision 1.2
=
=
=
=
16/32-bit
16/32-bit
16/32-bit
16/32-bit
16/32-bit
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32-Bit Registers
3128 27
31
16 1512 11
21 20
Source Offset
Pattern Pointer
Reserved(0)
Destination Offset
Reserved(0)
Reserved(0)
Revision 1.2
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32-Bit Registers
31
31
Background Color
Foreground Color
Revision 1.2
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32-Bit Registers
12
87
0
ROP
13
INC_X, INC_Y
Source Data
Source Depth
Pattern Depth
Background
BitBLT Src/Dst
Pattern Seed
Solid Pattern
BitBLT Status
Reserved(0)
Buffer Status
Reserved(0)
70
ROP
Raster Operation as defined by Microsoft
Windows. All logical operations of Source,
Pattern, and Destination Data are supported.
INC_Y
DeterminesBitBLTY-direction:
0 Decrement (Bottom to Top)
1 Increment (Top to Bottom)
INC_X
DeterminesBitBLTX-direction:
0 Decrement (Right to Left)
1 Increment (Left to Right)
10
Source Data
Selects variable data or color register data:
1 Source is FG Color Reg (DR03)
0 Source data selected by DR04[14]
11
1514
1816
19
20
Source Depth
Selects between monochrome and color
source data. This allows BitBLTs to either
transfer source data directly to the screen or
perform a font expansion (INC_X=1 only):
0 Source is Color
1 Source is Mono (Font expansion)
2321
2724
3125
Revision 1.2
158
Pattern Depth
Selects between monochrome and color
pattern data. This allows the pattern register
to operate either as a full pixel depth 8x8
pattern for use by the ROP, or as an 8x8
monochromepattern:
0 Pattern is Color
1 Pattern is Monochrome
Background
The 65540 / 545 supports both transparent
and opaque backgrounds for monochrome
patterns and font expansion:
0 BG is Opaque (BG Color Reg DR02)
1 BG is Transparent (Unchanged)
BitBLT Source / Destination
The 65540 / 545 only supports its local
display memory as the destination for
BitBLT operations. The source may be
either display memory or system memory
(CPU):
15 14 BitBLT Source > Dest
0 0 Screen > Screen (Dest)
0 1 System > Screen (Dest)
1 0 Reserved
1 1 Reserved
Pattern Seed
Determines the starting row of the 8x8
pattern for the current BitBLT. A pattern is
typically required to be destination aligned.
The 65540 / 545 can determine the xalignment from the destination address
however the y-alignment must be generated
by the programmer. These three bits
determine which row of the pattern is output
on the first line of the BitBLT. Incrementing
and decrementing are controlled by bit
DR04[8].
Solid Pattern
1 = Solid Pattern (Brush)
0 = Bitmap Pattern
BitBLT Status ( Read Only )
0 BitBLT Engine Idle
1 BitBLT Active - do not write BitBLT
regs
Reserved (0)
Buffer Status
# of DWords that can be written to the chip:
0000 Buffer Full
0001 1 Space available in the queue
...
...
1111 15 Spaces available in the queue
Reserved (0)
65540 / 545
32-BitRegisters
31
31
21 20
Destination Addr
Reserved(0)
Reserved(0)
200 DestinationAddress
Revision 1.2
SourceAddress
Warning:
21 20
Warning:
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32-Bit Registers
16 1512 11
Reserved(0)
Reserved(0)
Warning:
Revision 1.2
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32-Bit Registers
CURSOR/POP-UPCONTROLREGISTER(DR08)
7-6
Cursor Enable
Resrvd (must be 0)
ULC Select
10
Reserved(R/W)
11
Auto Zoom
0 Auto zoom off
1 Replicate pixels in high resolution
modes. No pixel replication takes
place in CRT interlace mode and for
32x32 cursor.
Both Disabled
32x32 Cursor Enable
64x64 Cursor Enable
Pop-Up Menu Enable
Reserved (R/W)
Must be programmed to 0.
5
Y Zoom (Manual)
0 No pixel replication.
1 Replicate pixels in the vertical
direction. No pixel replication takes
place in CRT mode and for 32x32
cursor.
Reserved(0)
42
X Zoom (Manual)
0 No pixel replication.
1 Replicate pixels in the horizontal
direction. No pixel replication takes
place in CRT interlace mode and for
32x32 cursor.
Test
Pop-up Width
X Zoom
Y Zoom
Auto Zoom
00
01
10
11
16 1512 1110 9 8 7 6 5 4 2 1 0
1-0
Test
Revision 1.2
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32-Bit Registers
CURSOR/POP-UPCOLOR0-1REGISTER(DR09)
CURSOR/POP-UPCOLOR2-3REGISTER(DR0A)
31
31
27 26
21 20
16 15
11 10 5 4 0
21 20
16 15
11 10 5 4 0
CC0 - Blue
CC2 - Blue
CC0 - Green
CC2 - Green
CC0 - Red
CC2 - Red
CC1 - Blue
CC3 - Blue
CC1 - Green
CC3 - Green
CC1 - Red
CC3 - Red
27 26
CC0 - Blue
40
CC2 - Blue
Cursor Color 2 Blue value
Revision 1.2
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32-Bit Registers
CURSOR/POP-UPPOSITIONREGISTER(DR0B)
2616 Y Offset
27 26
16 1514
11 10
X Offset
Reserved(0)
X SIGN
Y Offset
Reserved(0)
Y Sign
Sign associated with the Y OFFSET
magnitude which together form the signed
offset of the cursor in the Y direction.
Y SIGN
100 X Offset
X Sign
Sign associated with the X OFFSET
magnitude which together form the signed
offset of the cursor in the X direction.
Revision 1.2
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32-Bit Registers
20 19
10 9
Reserved(0)
BaseAddress
Reserved(0)
90
Reserved (0)
Revision 1.2
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Functional Description
System Interface
Functional Blocks
VL-Bus Interface
Bus Interface
Two major buses are directly supported by the 65540
and 65545: Industry Standard Architecture (ISA),
and VESA Local Bus (VL-Bus); the 65545 also
supports the PCI Bus. Direct interfaces to popular
80486DX, 80486DX2, 80486SX, and 80386DX
processors are supported by both chips. Connection
to 16-bit PI bus and other 32-bit system buses such
as EISA and Micro Channel (MC) are possible with
external logic but are not inherently supported.
ISA Interface
The 65540 / 545 operates as a 16-bit slave device on
the ISA bus. It maps its display memory into the
standard VGA address range (0A0000-0BFFFFh).
The VGA BIOS ROM is decoded in the 32KByte
space at 0C0000-0C7FFFh (an output is available on
the ROMCS# pin for ROM chip selection). Address
lines LA23:17 are required for decoding MEMCS16#
hence these addresses are latched internally by ALE.
The remaining addresses (SA16:0) are accepted from
the system without internal latching. The 65540 /
545 supports 16-bit memory and I/O cycles.
Whenever possible the 65540 / 545 executes zero
wait state memory cycles by asserting ZWS#. It
does not generate MEMCS16# or ZWS# on ROM
accesses. Memory may be mapped as a single linear
frame buffer anywhere in the 16 MByte ISA memory
space on a 512K/1MByte boundary (depending on
the amount of display memory installed - see
XR0B[4]). The 16-bit bus extension signals
MEMR# and MEMW# are used for memory control
since mapping above the 1MByte boundary is
permitted. For ISA compatibility the IRQ pin
operates as an active high level-triggered interrupt.
Revision 1.2
PCI Interface
The 65545 also supports a full 32-bit PCI bus
interface as defined by PCI Interface Specification
Revision 2.0. All features required of a non-busmaster 'target' device are implemented on-chip with
no external glue logic required. Read/Write cycles
are supported for Memory, I/O, and Configuration
address spaces. Burst accesses are not supported.
Interrupt capability is provided for vertical interrupts.
Refer to the PCI Pin Descriptions and Configuration
Registers sections for further information.
165
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Functional Description
Revision 1.2
DRAM Speed
100 ns
80 ns
70 ns
166
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Functional Description
Clock Synthesizer
An integrated clock synthesizer supports all pixel
clock (VCLK) and memory clock (MCLK)
frequencies which may be required by the 65540 /
545. Each of the two clock synthesizer phase lock
loops may be programmed to output frequencies
ranging between 1MHz and the maximum specified
operating frequency for that clock in increments not
exceeding 0.5%. The frequencies are generated by
an 18-bit divisor word. This value contains divisor
fields for the Phase Lock Loop (PLL), Voltage
Controlled Oscillator (VCO) and Pre/Post Divide
Control blocks.
The divisor word for both
synthesizers is programmable via Clock Control
Registers XR30-32.
MCLK Operation
Normal operational frequencies for MCLK are
between 50MHz and 68MHz. Refer to the Electrical
VCLKRegisterTable
VCLK Synthesizer
CLK2 = Programmable
XR32:30
MCLKRegisterTable
21
MCLK = Programmable
CLKSEL1:0
MCLK Synthesizer
XR30[0]
Reference
XR32[6:0]
PSN
Phase
Detector
Charge
Pump
VCO
2 P
CLK
Internal
Loop Filter
XR31[6:0]
XR30[3:1]
4M
7
3
post-VCO divider select
167
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Functional Description
VCLK Operation
Programming Constraints
There are five primary programming constraints the
programmer must be aware of:
4 MHz FREF 20 MHz
150 KHz F REF/(PSN * N) 2 MHz
48 MHz < FVCO 220 MHz
3 M 127
3 N 127
# Bits
XR30[0]
XR31[6:0]
XR32[6:0]
XR30[3:1]
(1 or 4)
(M' = M - 2)
(N' = N - 2)
(2P; 0 P 5)
FREF * 4 * M
PSN * N * 2 P
FREF * 4 * M
PSN * N
Post Divisor
000
001
010
011
100
101
1
2
4
8
16
32
Revision 1.2
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Functional Description
Programming Example
The result:
FVCO = 50.350 = (14.31818 x 4 x M/4 x N)
M/N = 3.51655
+5V
N
31
29
FVCO
50.344
50.360
10
CVCCn
Error
-0.00300
+0.00500
0.1F
CGNDn
The suggested method for layout assumes a multilayer board including VCC and GND planes. All
ground connections should be made as close to the
pin / component as possible. The CVCC trace
should route from the 65540/545 throughthepads of
the filter components. The trace should NOT be
connected to the filter components by a stub. All
components (particularly the initial 0.1F capacitor)
should be placed as close as possible to the
65540/545.
Prescaling PSN = 1
The result:
FVCO = 50.350 = (14.31818 x 4 x M/1 x N)
M/N = 0.879127
N
91
FVCO
50.349
0.1F
GND
M
80
47F
Error
-0.00050
FREF/(PSN x N) = 157.3KHz
A19
GND
VCC
A20
A21
GND
C2
C1
A22
R1
C3
CGND0
GND
XTALI
XTALO
GND
CVCC0
CVCC1
RESET#
CGND1
R2
Designator
C1,C3,C4,C6,C7
C2,C5
R1,R2
Value
0.1F
47F
10
NOTE: Do
not connect
Vcc here.
Force the
trace
through the
decoupling
cap pad.
C6
GND
C5
VCC
VCC
GND
C4
GND
C7
GND
Always pass the Vcc trace through the decoupling cap pad. Do not leave a stub as shown here.
Revision 1.2
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Functional Description
HighColorPixelData
Hardware
Cursor
ExternalRGBVideo
(565, 666, or 888)
LUTPixelData
24
Triple6-bit
LUT
Red
Triple
6/8-bit
DAC
Green
Blue
18
Revision 1.2
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Functional Description
destination screen widths are independently programmable. This permits expansion of a compressed offscreen bitmap transparent to the software driver. The
BitBLT Control Register (DR04) uses the same
raster-op format as the Microsoft Windows ROP so
no translation is required. All 256 Windows defined
ROPs are available.
The BitBLT and ROP subsystems have been architected for compatibility with the standard Microsoft
Windows BitBLT parameter block. The source and
Source
Dest
INC_X = X; INC_Y = 0
Source
Source
Source
Dest
INC_X = 0; INC_Y = X
Dest
Dest
INC_X = X; INC_Y = 0
Arrows indicate
appropriate direction for
BitBLT progression so
that destination overlap
does not corrupt data.
Dest
Dest
INC_X = X; INC_Y = 0
Dest
INC_X = 1; INC_Y = X
Dest
Source
Source
INC_X = X; INC_Y = 1
INC_X = X; INC_Y = 1
Source
Source
INC_X = X; INC_Y = 1
Revision 1.2
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Functional Description
1FFFFFh
25h,30h
52h
114h
Source
Line 52h
020425h
0C0000h
138h,81h
300h
(768)
020538h
Off-Screen
Memory
157h,153h
06926Ah
Dest
054D57h
Destination
26Ah, 1A4h
020538h
Source
00C025h
000000h
1024 x 768 x 8BPP
00C938h
Line 3
00C825h
2EDh
400h
00C538h
Line 2
00C425h
Line 1
00C138h
00C025h
Screen-to-Screen BitBLT
Revision 1.2
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Functional Description
In the present example the BitBLT source and destination blocks have the same width as the display. As
can be seen below each scan line is transferred from
source to destination. Alignment is handled by the
BitBLT engine without assistance from software.
1FFFFFh
020538h
Off-Screen
Memory
06926Ah
Line 52h
Line 52h
020425h
069157h
Off-Screen
Memory
1FFFFFh
0C0000h
0C0000h
069269h
Dest
054D57h
069269h
Dest
054D57h
020538h
Source
00C025h
000000h
00C938h
05566Ah
Line 3
Line 3
00C825h
055557h
020538h
Source
00C025h
000000h
2EDh
400h
00C538h
05526Ah
00C425h
055157h
00C138h
054E6Ah
00C025h
054D57h
Line 2
Line 1
Line 2
Line 1
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Functional Description
1FFFFFh
020538h
1FFFFFh
Line 52h
020425h
Off-Screen
Memory
Off-Screen
Memory
0C5867h
Line 52h
0C5754h
Dest
Dest
0C0000h
020538h
0C0000h
Source
00C938h
Line 3
00C025h
000000h
Source
0C0336h
0C0228h
0C0227h
0C0114h
0C0113h
00C825h
2EDh
400h
Line 3
020538h
Source
00C025h
Line 2
Line 1
000000h
0C0000h
00C538h
Destination
Line 2
00C425h
Line 1
00C138h
00C025h
Source
Differential Pitch BitBLT Data Transfer
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Functional
Similarly, the ULC of the destination register calculated as (Number of scan lines * Bytes per scan line):
300h * 400h = 0C0000h
BitBLT Destination Register (DR06) = 0C0000h
As in the previous example the Command Register
must be written to begin the BitBLT. This register
contains the size of the current BitBLT which must
be written for all BitBLT operations:
Lines per Block = 52h
Bytes per line = 114h (Current example 8bpp)
Command Register (DR07) = 00520114h
System-to-Screen BitBLTs
When performing a system-to-screen BitBLT the
source rotation information is passed in the BitBLT
Source Address and Source Offset registers. The 2
LSbits of the Source Address register indicate the
alignment. For example if the system data resides at
system address 0413456h then the processor pointer
should be set to 0413454h (doubleword aligned) and
the Source address register is written with xxxxx2h.
When the end of the scan line is reached (the number
of bytes programmed in the Command Register have
been written) any remaining bytes in the last
doubleword written to the 65545 are discarded. The
2 LSbits of the Source Offset Register are then added
to the 2 LSbits of the Source Address Register to
determine the starting byte alignment for the first
doubleword of the next scanline. This process is
continued until all scanlines are completed. The most
common case will be a doubleword aligned bitmap in
system memory in which case the 2 Lbits of the
Source Address Register are zero. It is also common
for bitmaps to be stored with each scanline
doubleword aligned (Source Offset Register =
xxxxx0h). Once the Command Register is written
and the BitBLT operation has begun the 65545 will
wait for data to be sent to its memory address space.
Any write to a valid 65545 memory address, either in
the VGA space or linear address space if enabled,
Revision 1.2
Description
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Functional Description
Revision 1.2
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Functional Description
x 2bpp
x 2bpp
x 2bpp
x 1bpp
(and/xor)
(and/xor)
(4-color)
(2-color)
Plane 3
X15-8
X31-24
X15-8
X31-24
...
X31-24
And/Xor Type
Color 0
Color 1
Transparent
Inverted
4-Color Type
Color 0
Color 1
Color 2
Color 3
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Revision 1.2
AL, [SI+1]
AH, [BX+1]
EAX,16
AL, [SI]
AH, [BX]
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Panel Size
The horizontal panel size register (XR1C) is an 8-bit
register programmed with panel width (minus one)
in units of 8-pixel characters (e.g., a 640x480 panel
is 80 'characters' wide so XR1C would be
programmed with 79 decimal). The vertical panel
size register is programmed with the panel height
(minus one) in scan lines (independent of single or
dual panel type). The programmed value is 10 bits
in size with the 8 lsbs in XR68 and the overflow in
XR65 bits 1 and 6. The maximum panel resolution
supported is 2048 x 1024.
Panel Type
The panel type (PT) is determined by XR51 bits 1-0:
00
11
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M Signal Timing
Register XR5E (M/ACDCLK Control) is provided to
control the timing of the M (sometimes called
ACDCLK) signal. XR5E bit-7 selects between two
types of timing control:
0
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Pixels Per
Pixels Per
Shift
Shift Clock
Shift Clock
Clock without Frm Acc with Frm Acc
000 Dot clk
1
2
001 Dclk / 2
2
4
010 Dclk / 4
4
8
011 Dclk / 8
8
16
100 Dclk / 16
16
n/a
Pixels 8-Bit
Valid
16-Bit Valid
Per Shift Panel
Outputs
Panel Outputs
Clock Interface
(8-bit)
Interface (16-bit)
1
8bpp
P8-15
8bpp
P8-15
2
4bpp P8-15 (8-11 1st) 8bpp
P0-15
4
2bpp P8-15 (8-9 1st) 4bpp
P0-15
8
1bpp P1,3,5,... (1 1st) 2bpp
P0-15
16
n/a
n/a
1bpp
P0-15
The pixel on the lowest numbered output pin is
always the first pixel output (the pixel shown first on
the left side of the screen). For example, for 8 pixels
per clock, 1bpp on an 8-bit interface, P1 is the first
pixel, P3 is the second, etc. For 16 pixels per clock,
1bpp on a 16-bit interface, P0 is the first pixel, P1 is
the second, etc. For 4 pixels per clock, 2bpp on an
8-bit interface, P8-9 is the first pixel, P10-11 is the
second, etc.
G0n
G4n
G6n
P1
B1n B5n B4n
G1n
G5n
G7n
P2
B2n B6n B5n
P17
R1n R5n
P18
R2n R6n
P19
R3n R7n
P20
R4n R4n+1
P21
R5n R5n+1
P22
R6n R6n+1
P23
R7n R7n+1
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CD Settings Allowable
SS: 000, 001, or 010
DD: 000, 001 (010 w/o FA)
01
4-Bit Pack
SS: 000, 001, or 010
DD: 000, 001 (010 w/o FA)
11 Ext'd 4-Bit Pack SS: 001 (8bit panels only)
00
Packing
3-Bit Pack
Upper:
P0
R1
P1
G1
P2
B1
P3
R2
Lower:
P4
R1
P5
G1
P6
B1
P7
R2
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P0
P1
P2
P3
P4
P5
P6
P7
...
...
...
...
G2
B2
R3
G3
B3
R4
G4
B4
...
...
...
...
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
STN-SS Panels
Shift Clock Edge
1st 2nd 3rd 4th
R1 G6 B11 ...
G1 B6 R12 ...
B1 R7 G12 ...
R2 G7 B12 ...
G2 B7 R13 ...
B2 R8 G13 ...
R3 G8 B13 ...
G3 B8 R14 ...
B3 R9 G14 ...
R4 G9 B14 ...
G4 B9 R15 ...
B4 R10 G15 ...
R5 G10 B15 ...
G5 B10R16 ...
B5 R11G16 ...
R6 G11B16 ...
STN-DD Panels
Shift Clock Edge
1st 2nd 3rd 4th
Upper:
P0
R1
P1
G1
P2
B1
P3
R2
P8
G2
P9
B2
P10 R3
P11 G3
Lower:
P4
R1
P5
G1
P6
B1
P7
R2
P12 G2
P13 B2
P14 R3
P15 G3
B3
R4
G4
B4
R5
G5
B5
R6
G6
B6
R7
G7
B7
R8
G8
B8
...
...
...
...
...
...
...
...
B3
R4
G4
B4
R5
G5
B5
R6
G6
B6
R7
G7
B7
R8
G8
B8
...
...
...
...
...
...
...
...
Revision 1.2
B3
R4
G4
B4
G2
B2
R3
G3
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LP Signal Timing
LP output polarity is controlled by XR54[6]
(0=positive, 1=negative). Setting XR4F bit-7,
however, causes the LP pin to output flat panel
BLANK# / DE instead of the normal LP signal (and
all other LP timing control parameters will be
ignored). Some panels (e.g., Plasma and EL)
require LP to be active during vertical blank time.
XR51[7] may be set to enable this. Otherwise LP
pulses are not generated during vertical blank.
1) SS Monochrome Plasma / EL
Single Panel-Single Drive (Panel Type = 00)
Plasma/EL Panel
2 pixels/shift clock, 4 bits/pixel (CD = 001)
2) DD Monochrome LCD
Dual Panel-Double Drive (Panel Type = 11)
Monochrome LCD Panel
8 pixels/shiftclk, 1bit/pixel, CD = 011
(010 with FB)
16 pixels/shiftclk, 1bit/pixel, CD = 100
(011 with FB)
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LP
BLANK#
SHFCLK
320 Clks / H
320 Clks / H
320 Clks / H
(1,1)...(640,1)
(1,2)...(640,2)
(1,480)...(640,480)
FLM
P8-15
SHFCLK
(Plasma)
SHFCLK
(EL )
P8
(1,1)
1
(3,1)
1
(637,1)
1
(639,1)
1
(637,480) (639,480)
1
1
P9
(1,1)
2
(3,1)
2
(637,1)
2
(639,1)
2
(637,480) (639,480)
2
2
P10
(1,1)
4
(3,1)
4
(637,1)
4
(639,1)
4
(637,480) (639,480)
4
4
P11
(1,1)
8
(3,1)
8
(637,1)
8
(639,1)
8
(637,480) (639,480)
8
8
P12
(2,1)
1
(4,1)
1
(638,1)
1
(640,1)
1
(638,480) (640,480)
1
1
P13
(2,1)
2
(4,1)
2
(638,1)
2
(640,1)
2
(638,480) (640,480)
2
2
P14
(2,1)
4
(4,1)
4
(638,1)
4
(640,1)
4
(638,480) (640,480)
4
4
P15
(2,1)
8
(4,1)
8
(638,1)
8
(640,1)
8
(638,480) (640,480)
8
8
EL panels use the rising edge of SHFCLK to clock in panel data, so the SHFCLK
output from the 65540 / 545 must be inverted prior to driving the panel
Panel Timing - Monochrome 16-Gray-Level EL / Plasma 8-Bit Interface
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Panel Output Timing - 640 x 480 Monochrome DD 8-Bit (1 Bit / Pixel, 8 Pixels / Shift Clock)
LP
BLANK#
SHFCLK
160 Clks / H
(640 x 480)
160 Clks / H
(640 x 480)
160 Clks / H
(640 x 480)
(1,1)...(640,1)
(1,241)...(640,241)
(1,2)...(640,2)
(1,242)...(640,242)
(1,240)...(640,240)
(1,480)...(640,480)
FLM
P0-7
(SHFCLK x 8)
CD = 011
(SHFCLK x 4)
CD = 010
(633,1)
(637,1)
(633,240) (637,240)
(634,1)
(638,1)
(634,240) (638,240)
(635,1)
(639,1)
(635,240) (639,240)
(636,1)
(640,1)
(636,240) (640,240)
(633,241) (637,241)
(633,480) (637,480)
(634,241) (638,241)
(634,480) (638,480)
(635,241) (639,241)
(635,480) (639,480)
(636,241) (640,241)
(636,480) (640,480)
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Panel Output Timing - 1024 x 768 Monochrome DD 16-Bit (1 Bit / Pixel, 16 Pixels / Shift Clock)
LP
BLANK#
SHFCLK
256 Clks / H
(1024 x 768)
256 Clks / H
(1024 x 768)
256 Clks / H
(1024 x 768)
(1,1)...(1024,1)
(1,385)...(1024,385)
(1,2)...(1024,2)
(1,386)...(1024,386)
(1,384)...(1024,384)
(1,768)...(1024,768)
FLM
P0-15
(SHFCLK x 16)
CD = 100
(SHFCLK x 8)
CD = 011
(9,1)
(1009,384)
(10,1)
(11,1)
(1010,384)
(12,1)
(1012,384)
(13,1)
(1013,384)
(14,1)
(1014,384)
(15,1)
(1015,384)
(16,1)
(1016,384)
(9,385)
(1009,768)
(10,385)
(1010,768)
(11,385)
(1011,768)
(12,385)
(1012,768)
(13,385)
(1013,768)
(14,385)
(1014,768)
(15,385)
(1015,768)
(16,385)
(1016,768)
(1011,384)
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DCLK
SHFCLK
P0
B0(0)
B1(0)
B0(0)
B2(0)
P1
B0(1)
B1(1)
B0(1)
B2(1)
P2
B0(2)
B1(2)
B0(2)
B2(2)
P3
B0(3)
B1(3)
B1(0)
B3(0)
P4
B0(4)
B1(4)
B1(1)
B3(1)
P5
G0(0)
G1(0)
B1(2)
B3(2)
P6
G0(1)
G1(1)
G0(0)
G2(0)
P7
G0(2)
G1(2)
G0(1)
G2(1)
P8
G0(3)
G1(3)
G0(2)
G2(2)
P9
G0(4)
G1(4)
G1(0)
G3(0)
P10
G0(5)
G1(5)
G1(1)
G3(1)
P11
R0(0)
R1(0)
G1(2)
G3(2)
P12
R0(1)
R1(1)
R0(0)
R2(0)
P13
R0(2)
R1(2)
R0(1)
R2(1)
P14
R0(3)
R1(3)
R1(0)
R3(0)
P15
R0(4)
R1(4)
R1(1)
R3(1)
CD:
FRC:
Bits / Pixel:
Pixel Format:
DataWidth:
Panels with 9 or 12-bit data interfaces would use this setting and only connect to the msbs of each color
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B0(0)
B1(0)
B0(0)
B2(0)
P1
B0(1)
B1(1)
B0(1)
B2(1)
P2
B0(2)
B1(2)
B0(2)
B2(2)
P3
B0(3)
B1(3)
B0(3)
B2(3)
P4
B0(4)
B1(4)
B1(0)
B3(0)
P5
B0(5)
B1(5)
B1(1)
B3(1)
P6
B0(6)
B1(6)
B1(2)
B3(2)
P7
B0(7)
B1(7)
B1(3)
B3(3)
P8
G0(0)
G1(0)
G0(0)
G2(0)
P9
G0(1)
G1(1)
G0(1)
G2(1)
P10
G0(2)
G1(2)
G0(2)
G2(2)
P11
G0(3)
G1(3)
G0(3)
G2(3)
P12
G0(4)
G1(4)
G1(0)
G3(0)
P13
G0(5)
G1(5)
G1(1)
G3(1)
P14
G0(6)
G1(6)
G1(2)
G3(2)
P15
G0(7)
G1(7)
G1(3)
G3(3)
P16
R0(0)
R1(0)
R0(0)
R2(0)
P17
R0(1)
R1(1)
R0(1)
R2(1)
P18
R0(2)
R1(2)
R0(2)
R2(2)
P19
R0(3)
R1(3)
R0(3)
R2(3)
P20
R0(4)
R1(4)
R1(0)
R3(0)
P21
R0(5)
R1(5)
R1(1)
R3(1)
P22
R0(6)
R1(6)
R1(2)
R3(2)
P23
R0(7)
R1(7)
R1(3)
R3(3)
CD:
FRC:
Bits / Pixel:
Pixel Format:
DataWidth:
Panels with 18-bit data interfaces would use this setting and only connect to the msbs of each color
Panel Timing - Color LCD TFT 18 / 24-Bit Interface
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DCLK
IDCLK
IDCLK/2
SHFCLKU
(Pin 70)
SHFCLKL
(Pin 81)
P0
R1
G1
G6
B6
B11
R12
P1
B1
R2
R7
G7
G12
B12
P2
G2
B2
B7
R8
R13
G13
P3
R3
G3
G8
B8
B13
R14
P4
B3
R4
R9
G9
G14
B14
P5
G4
B4
B9
R10
R15
G15
P6
R5
G5
G10
B10
B15
R16
P7
B5
R6
R11
G11
G16
B16
PT:
CD:
FRC:
Pixel Packing:
Bits / Pixel:
Frame Buffer / Acceleration:
00 (SS Panel)
010 (5-1/3 Pixels / Clock)
01 (16-Frame)
11 (Extended 4-Bit Pack)
100 (4 bits / pixel)
Disabled / Disabled
16 Pixels are
transferred
every 16 dot clocks
(6 shift clock edges)
Panel Timing - Color LCD STN 8-Bit ( Extended 4-Bit Pack ) Interface
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R1
G6
B11
R17
G22
B27
P1
G1
B6
R12
G17
B22
R28
P2
B1
R7
G12
B17
R23
G28
P3
R2
G7
B12
R18
G23
B28
P4
G2
B7
R13
G18
B23
R29
P5
B2
R8
G13
B18
R24
G29
P6
R3
G8
B13
R19
G24
B29
P7
G3
B8
R14
G19
B24
R30
P8
B3
R9
G14
B19
R25
G30
P9
R4
G9
B14
R20
G25
B30
P10
G4
B9
R15
G20
B25
R31
P11
B4
R10
G15
B20
R26
G31
P12
R5
G10
B15
R21
G26
B31
P13
G5
B10
R16
G21
B26
R32
P14
B5
R11
G16
B21
R27
G32
P15
R6
G11
B16
R22
G27
B32
PT:
CD:
FRC:
Pixel Packing:
Bits / Pixel:
Frame Buffer / Acceleration:
00 (SS Panel)
010 (5-1/3 Pixels / Clock)
01 (16-Frame)
01 (4-Bit Pack)
100 (4 bits / pixel)
Disabled / Disabled
Panel Pixel Timing - Color LCD STN 16-Bit ( 4-Bit Pack ) Interface
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DCLK
SHFCLK
(IDCLK)
P0
R(1,1)
G(2,1)
B(3,1)
R(5,1)
G(6,1)
P1
G(1,1)
B(2,1)
R(4,1)
G(5,1)
B(6,1)
P2
B(1,1)
R(3,1)
G(4,1)
B(5,1)
R(7,1)
P3
R(2,1)
G(3,1)
B(4,1)
R(6,1)
G(7,1)
P4
R(1,241)
G(2,241)
B(3,241)
R(5,241)
G(6,241)
P5
G(1,241)
B(2,241)
R(4,241)
G(5,241)
B(6,241)
P6
B(1,241)
R(3,241)
G(4,241)
B(5,241)
R(7,241)
P7
R(2,241)
G(3,241)
B(4,241)
R(6,241)
G(7,241)
PT:
CD:
FRC:
Bits / Pixel:
Pixel Packing:
FrameBuffer/Acceleration:
11 (DD Panel)
000 (2-2/3 Pixels / Clock)
01 (16-Frame)
100 (4 bits/pixel)
01 (4-Bit Pack)
Enabled/Enabled
8 Pixels (4 each for the upper and lower panels) are transferred every 4 Dot Clocks (3 Shift Clock Edges)
Panel Pixel Timing - Color LCD STN-DD 8-Bit ( 4-Bit Pack ) Interface - With Frame Acceleration
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DCLK
IDCLK
SHFCLK
(IDCLK/2)
P0
R(1,1)
G(2,1)
B(3,1)
R(5,1)
G(6,1)
P1
G(1,1)
B(2,1)
R(4,1)
G(5,1)
B(6,1)
P2
B(1,1)
R(3,1)
G(4,1)
B(5,1)
R(7,1)
P3
R(2,1)
G(3,1)
B(4,1)
R(6,1)
G(7,1)
P4
R(1,241)
G(2,241)
B(3,241)
R(5,241)
G(6,241)
P5
G(1,241)
B(2,241)
R(4,241)
G(5,241)
B(6,241)
P6
B(1,241)
R(3,241)
G(4,241)
B(5,241)
R(7,241)
P7
R(2,241)
G(3,241)
B(4,241)
R(6,241)
G(7,241)
PT:
CD:
FRC:
Bits / Pixel:
Pixel Packing:
FrameBuffer/Acceleration:
11 (DD Panel)
001 (2-2/3 Pixels / Clock)
01 (16-Frame)
100 (4 bits/pixel)
01 (4-Bit Pack)
Enabled/Disabled
8 Pixels (4 each for the upper and lower panels) are transferred every 8 Dot Clocks (3 Shift Clock Edges)
Panel Pixel Timing - Color LCD STN-DD 8-Bit ( 4-Bit Pack ) Interface - Without Frame Acceleration
Revision 1.2
192
65540 / 545
DCLK
IDCLK
SHFCLK
(IDCLK /2)
P0
R(1,1)
B(3,1)
G(6,1)
R(9,1)
B(11,1)
P1
G(1,1)
R(4,1)
B(6,1)
G(9,1)
R(12,1)
P2
B(1,1)
G(4,1)
R(7,1)
B(9,1)
G(12,1)
P3
R(2,1)
B(4,1)
G(7,1)
R(10,1)
B(12,1)
P4
R(1,241)
B(3,241)
G(6,241)
R(9,241)
B(11,241)
P5
G(1,241)
R(4,241)
B(6,241)
G(9,241)
R(12,241)
P6
B(1,241)
G(4,241)
R(7,241)
B(9,241)
G(12,241)
P7
R(2,241)
B(4,241)
G(7,241)
R(10,241)
B(12,241)
P8
G(2,1)
R(5,1)
B(7,1)
G(10,1)
R(13,1)
P9
B(2,1)
G(5,1)
R(8,1)
B(10,1)
G(13,1)
P10
R(3,1)
B(5,1)
G(8,1)
R(11,1)
B(13,1)
P11
G(3,1)
R(6,1)
B(8,1)
G(11,1)
R(14,1)
P12
G(2,241)
R(5,241)
B(7,241)
G(10,241)
R(13,241)
P13
B(2,241)
G(5,241)
R(8,241)
B(10,241)
G(13,241)
P14
R(3,241)
B(5,241)
G(8,241)
R(11,241)
B(13,241)
P15
G(3,241)
R(6,241)
B(8,241)
G(11,241)
R(14,241)
PT:
CD:
FRC:
Pixel Packing:
Bits / Pixel:
Frame Buffer / Acceleration:
11 (DD Panel)
001 (5-1/3 Pixels / Clock)
01 (16-Frame)
01 (4-Bit Pack)
100 (4 bits / pixel)
Enabled / Enabled
16 Pixels (8 each for the upper and lower panels) are transferred every 8 Dot Clocks (3 Shift Clock Edges)
Panel Pixel Timing - Color LCD STN-DD 16-Bit ( 4-Bit Pack ) Interface - With Frame Acceleration
Revision 1.2
193
65540 / 545
DCLK
IDCLK
IDCLK /2
SHFCLK
(IDCLK /4)
P0
R(1,1)
B(3,1)
G(6,1)
P1
G(1,1)
R(4,1)
B(6,1)
P2
B(1,1)
G(4,1)
R(7,1)
P3
R(2,1)
B(4,1)
G(7,1)
P4
R(1,241)
B(3,241)
G(6,241)
P5
G(1,241)
R(4,241)
B(6,241)
P6
B(1,241)
G(4,241)
R(7,241)
P7
R(2,241)
B(4,241)
G(7,241)
P8
G(2,1)
R(5,1)
B(7,1)
P9
B(2,1)
G(5,1)
R(8,1)
P10
R(3,1)
B(5,1)
G(8,1)
P11
G(3,1)
R(6,1)
B(8,1)
P12
G(2,241)
R(5,241)
B(7,241)
P13
B(2,241)
G(5,241)
R(8,241)
P14
R(3,241)
B(5,241)
G(8,241)
P15
G(3,241)
R(6,241)
B(8,241)
PT:
CD:
FRC:
Pixel Packing:
Bits / Pixel:
FrameBuffer/Acceleration:
11 (DD Panel)
010 (5-1/3 Pixels / Clock)
01 (16-Frame)
01 (4-Bit Pack)
100 (4 bits / pixel)
Enabled/Disabled
16 Pixels (8 each for the upper and lower panels) are transferred every 16 Dot Clocks (3 Shift Clock Edges)
Panel Pixel Timing - Color LCD STN-DD 16-Bit (4-Bit Pack) Interface - Without Frame Acceleration
Revision 1.2
194
65540 / 545
Programming
In order to program the 65540 / 545 for simultaneous display, two FLM signals are required. The
first shorter FLM will match the normal FLM
frequency as the data is displayed on the first half of
the CRT display data. The second FLM will be
longer to allow for the CRT blank time. The FLM
delay is programmed in XR2C and should be equal
to the CRT blank time FLM front porch FLM
width.
Revision 1.2
195
65540 / 545
Programming
Panels
#3
Additional
#4
Additional
#5
Additional
#6
Additional
#7
Additional
#8
Additional
#9
Additional
#10
#11
Additional
Additional
Table #1
specifies the minimum Extension Register values required for the 65540 / 545 to boot to VGA
mode on an analog CRT monitor.
Table #2
specifies the additional Extension Register values required for emulation of EGA, CGA, MDA
and Hercules backwards compatibility modes. The registers in Table #2 should be used in
conjunction with the registers specified in Table #1. For registers listed in both tables, use the
values in Table #2 (shown in bold text).
Tables #3-11 specify the additional Extension Register values required to support various panels. The registers
in Tables #3-11 should be used in conjunction with the registers specified in Table #1 (and
optionally Table #2). For registers listed in more than one table, use the values in Tables #3-11
(shown in bold text).
Revision 1.2
196
65540 / 545
Programming
01
A1
00
00
00
00
00
00
80
10
00
00
00
00
00
00
00
00
12
59
80
4C
00
03
6B
3C
20
03
4E
59
00
10
00
63
40
00
32
06
88
2E
07
41
80
24
Comments
Note 1
Note 2
Note 2
(Initialize Memory Clock)
(Initialize Memory Clock)
(Initialize Memory Clock)
(Initialize Memory Clock)
(Initialize Clock 2)
(Initialize Clock 2)
(Initialize Clock 2)
(Initialize Clock 2)
Note 2
Note 2
Note: 1) Memory Control Register 1 is automatically re-programmed with the proper display memory
configuration by the BIOS
2) The Software Flag Registers are used by the BIOS and should not be re-programmed
Revision 1.2
197
65540 / 545
Programming
00
18
Comments
Emulation Mode
Write Protect
EGA Emulation
EGA Emulation
01
0D
27
2B
A0
2D
28
10
14
30
Comments
Emulation Mode
Write Protect
Alternate Horizontal Display Enable End
Alternate Horizontal Retrace Start
Alternate Horizontal Retrace End
Alternate Horizontal Total
Alternate Horizontal Blanking Start
Alternate Horizontal Blanking End
Alternate Offset
CGA / Hercules Color Select
52
0D
0F
Comments
Emulation Mode
Write Protect
CGA / Hercules Color Select
02
52
0D
59
60
8F
6E
5C
31
16
0F
CGA Emulation
CGA Emulation
CGA Emulation
CGA Emulation
CGA Emulation
CGA Emulation
CGA Emulation
CGA Emulation
CGA Emulation
CGA Emulation
MDA Emulation
MDA Emulation
MDA Emulation
Comments
Auxiliary Offset
Emulation Mode
Write Protect
Alternate Horizontal Display Enable End
Alternate Horizontal Retrace Start
Alternate Horizontal Retrace End
Alternate Horizontal Total
Alternate Horizontal Blanking Start
Alternate Horizontal Blanking End
Alternate Offset
CGA / Hercules Color Select
Hercules Emulation
Hercules Emulation
Hercules Emulation
Hercules Emulation
Hercules Emulation
Hercules Emulation
Hercules Emulation
Hercules Emulation
Hercules Emulation
Hercules Emulation
Hercules Emulation
Note: 1) Bold text indicates registers with values different from those shown in Table #1
2) Non-bold text indicates additional registers (not included in Table #1)
Revision 1.2
198
65540 / 545
Programming
Table #3 - Parameters for 640x480 Monochrome LCD-DD Panels (Panel Mode Only)
Extension Register Values for Epson EG9005F-LS
Citizen G6481L-FF
Sharp LM64P80
Sanyo LCM-6494-24NTK
Hitachi LMG5364XUFC
Register Value (in Hex) Register
XR06
XR19
XR1A
XR1B
XR1C
XR2C
XR2D
XR2E
XR2F
XR4F
XR50
XR51
XR52
XR53
XR54
XR55
XR56
XR57
XR58
XR59
XR5A
XR5B
XR5D
XR5E
XR64
XR65
XR66
XR67
XR68
XR6C
XR6E
XR6F
02
57
19
59
4F
04
50
50
00
44
25
67
41
0C
3A
E5
00
1B
00
84
00
8F
10
80
E4
07
E0
01
DF
00
26
1B
Comments
Palette Control
Alternate Horizontal Sync Start
Alternate Horizontal Sync End
Alternate Horizontal Total
Horizontal Panel Size
FLM Delay
LP Delay (CMPR enabled)
LP Delay (CMPR disabled)
LP Width
Panel Format 2
Panel Format 1
Display Type
Power Down Control
Panel Format 3
Panel Interface
Horizontal Compensation
Horizontal Centering
Vertical Compensation
Vertical Centering
Vertical Line Insertion
Vertical Line Replication
Power Sequencing Delay
FP Diagnostic
M (ACDCLK) Control
Alternate Vertical Total
Alternate Overflow
Alternate Vertical Sync Start
Alternate Vertical Sync End
Vertical Panel Size
Programmable Output Drive
Polynomial FRC Control Register
Frame Buffer Control
Note: 1) Bold text indicates registers with values different from those shown in Table #1
2) Non-bold text indicates additional registers (not included in Table #1)
Revision 1.2
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65540 / 545
Programming
Table #4 - Parameters for 640x480 Monochrome LCD-DD Panels (Simultaneous Mode Display)
Extension Register Values for Epson EG9005F-LS
Citizen G6481L-FF
Sharp LM64P80
Sanyo LCM-6494-24NTK
Hitachi LMG5364XUFC
Register Value (in Hex) Register
XR19
XR1A
XR1B
XR1C
XR2C
XR2D
XR2E
XR2F
XR4F
XR50
XR51
XR52
XR53
XR54
XR55
XR56
XR57
XR58
XR59
XR5A
XR5B
XR5D
XR5E
XR64
XR65
XR66
XR67
XR68
XR6C
XR6E
XR6F
55
00
5F
4F
21
50
50
00
44
25
67
41
0C
3A
E5
00
1B
00
84
00
8F
10
80
0B
26
EA
0C
DF
02
26
1B
Comments
Note: 1) Bold text indicates registers with values different from those shown in Table #1
2) Non-bold text indicates additional registers (not included in Table #1)
Revision 1.2
200
65540 / 545
Programming
Table #5 - Parameters for 640x480 Color TFT Panels (Panel Mode Only)
Extension Register Values for Hitachi TX26D02VC2AA
Sharp LQ9D011 (set to accommodate the DE signal)
Toshiba LTM-09C015-1
Register Value (in Hex)
XR06
XR19
XR1A
XR1B
XR1C
XR2C
XR2D
XR2E
XR2F
XR4F
XR50
XR51
XR52
XR53
XR54
XR55
XR56
XR57
XR58
XR59
XR5A
XR5B
XR5D
XR5E
XR64
XR65
XR66
XR67
XR68
XR6C
XR6E
XR6F
C2
56
13
5F
4F
04
4F
4F
0F
44
02
C4
41
0C
FA
E5
00
1B
00
84
00
8F
10
80
01
26
DF
0C
DF
02
BD
00
Register
Comments
Palette Control
Alternate Horizontal Sync Start
Alternate Horizontal Sync End
Alternate Horizontal Total
Horizontal Panel Size
FLM Delay
LP Delay (CMPR enabled)
LP Delay (CMPR disabled)
LP Width
Panel Format 1
Panel Format 2
Display Type
Power Down Control
Panel Format 3
Panel Interface
Horizontal Compensation
Horizontal Centering
Vertical Compensation
Vertical Centering
Vertical Line Insertion
Vertical Line Replication
Power Sequencing Delay
FP Diagnostic
M(ACDCLK) Control
Alternate Vertical Total
Alternate Overflow
Alternate Vertical Sync Start
Alternate Vertical Sync End
Vertical Panel Size
Programmable Output Drive
Polynomial FRC Control
Frame Buffer Control
Color Reduction
Note: 1) Bold text indicates registers with values different from those shown in Table #1
2) Non-bold text indicates additional registers (not included in Table #1)
Revision 1.2
201
65540 / 545
Programming
Table
C0
55
00
5F
4F
00
4F
4F
0F
44
02
C4
41
0C
FA
E5
00
1B
00
84
00
8F
10
80
0C
26
EA
0C
DF
02
BD
00
Comments
Palette Control
Alternate Horizontal Sync Start
Alternate Horizontal Sync End
Alternate Horizontal Total
Horizontal Panel Size
FLM Delay
LP Delay (CMPR enabled)
LP Delay (CMPR disabled)
LP Width
Panel Format 2
Panel Format 1
Display Type
Power Down Control
Panel Format 3
Panel Interface
Horizontal Compensation
Horizontal Centering
Vertical Compensation
Vertical Centering
Vertical Line Insertion
Vertical Line Replication
Power Sequencing Delay
FP Diagnostic
M (ACDCLK) Control
Alternate Vertical Total
Alternate Overflow
Alternate Vertical Sync Start
Alternate Vertical Sync End
Vertical Panel Size
Programmable Output Drive
Polynomial FRC Control
Frame Buffer Control
Color Reduction
Note: 1) Bold text indicates registers with values different from those shown in Table #1
2) Non-bold text indicates additional registers (not included in Table #1)
Revision 1.2
202
65540 / 545
Programming
Table #7 - Parameters for 640x480 Color STN-SS Panels with 16-Bit Interface 4-Bit Pack
(Panel & Simultaneous Mode Display)
Extension Register Values for Sanyo LM-CK53-22NEZ
Sanyo LCM5327-24NAK
Sanyo LCM5330
Register Value (in Hex) Register
XR06
XR19
XR1A
XR1B
XR1C
XR2C
XR2D
XR2E
XR2F
XR4F
XR50
XR51
XR52
XR53
XR54
XR55
XR56
XR57
XR58
XR59
XR5A
XR5B
XR50
XR5E
XR64
XR65
XR66
XR67
XR68
XR6C
XR6E
XR6F
C2
56
19
59
4F
04
5C
5C
5C
44
25
C4
41
1C
3A
E5
00
1B
00
84
00
8F
10
80
E4
07
E1
02
DF
02
61
00
Comments
Palette Control
Alternate Horizontal Sync Start
Alternate Horizontal Sync End
Alternate Horizontal Total
Horizontal Panel Size
FLM Delay
LP Delay (CMPR enabled)
LP Delay (CMPR disabled)
LP Width
Panel Format 1
Panel Format 2
Display Type
Power Down Control
Panel Format 3
Panel Interface
Horizontal Compensation
Horizontal Centering
Vertical Compensation
Vertical Centering
Vertical Line Insertion
Vertical Line Replication
Power Sequencing Delay
Panel Format 1
M (ACDCLK) Control
Alternate Vertical Total
Alternate Overflow
Alternate Vertical Sync Start
Alternate Vertical Sync End
Vertical Panel Size
Programmable Output Drive
Polynomial FRC Control
Frame Buffer Control
Note: 1) Bold text indicates registers with values different from those shown in Table #1
2) Non-bold text indicates additional registers (not included in Table #1)
Revision 1.2
203
65540 / 545
Programming
Table #8 - Parameters for 640x480 Color STN-SS Panels with 8-Bit Interface (Extended 4-Bit Pack)
Extension Register Values for Sharp LM64C031
Register Value (in Hex) Register
XR06
XR19
XR1A
XR1B
XR1C
XR2C
XR2D
XR2E
XR2F
XR4F
XR50
XR51
XR52
XR53
XR54
XR55
XR56
XR57
XR58
XR59
XR5A
XR5B
XR5D
XR5E
XR64
XR65
XR66
XR67
XR68
XR6C
XR6E
XR6F
C2
56
00
59
4F
02
50
50
00
44
15
6C
41
3C
3A
E5
00
1B
00
84
00
8F
10
80
E8
07
E1
02
DF
02
36
00
Comments
Palette Control
Alternate Horizontal Sync Start
Alternate Horizontal Sync End
Alternate Horizontal Total
Horizontal Panel Size
FLM Delay
LP Delay (CMPR enabled)
LP Delay (CMPR disabled)
LP Width
Panel Format 2
Panel Format 1
Display Type
Power Down Control
Panel Format 3
Panel Interface
Horizontal Compensation
Horizontal Centering
Vertical Compensation
Vertical Centering
Vertical Line Insertion
Vertical Line Replication
Power Sequencing Delay
FP Diagnostic
M (ACDCLK) Control
Alternate Vertical Total
Alternate Overflow
Alternate Vertical Sync Start
Alternate Vertical Sync End
Vertical Panel Size
Programmable Output Drive
Polynomial FRC Control
Frame Buffer Control
C0 simultaneous mode
55 simultaneous mode
5F simultaneous mode
2B simultaneous mode
15 simultaneous mode
26 simultaneous mode
EA simultaneous mode
0C simultaneous mode
Optimize for best display quality
Note: 1) Bold text indicates registers with values different from those shown in Table #1
2) Non-bold text indicates additional registers (not included in Table #1)
Revision 1.2
204
65540 / 545
Programming
Table #9 - Parameters for 640x480 Color STN-DD Panels with 16-Bit Interface with Frame Acceleration
(Panel & Simultaneous Mode Display)
Extension Register Values for Sharp LM64C08P
Sanyo LCM5331-22NTK
Hitachi LMG9721XUFC
Toshiba TLX-8062S-C3X
Optrex DMF-50351NC-FW
Register Value (in Hex) Register
XR06
XR19
XR1A
XR1B
XR1C
XR2C
XR2D
XR2E
XR2F
XR4F
XR50
XR51
XR52
XR53
XR54
XR55
XR56
XR57
XR58
XR59
XR5A
XR5B
XR5D
XR5E
XR64
XR65
XR66
XR67
XR68
XR6C
XR6E
XR6F
C2
57
19
59
4F
15
50
50
00
04
25
67
41
1C
3A
E5
00
1B
00
1F
00
8F
10
80
0B
07
EA
0C
DF
02
33
1B
Comments
Palette Control
Alternate Horizontal Sync Start
Alternate Horizontal Sync End
Alternate Horizontal Total
Horizontal Panel Size
FLM Delay
LP Delay (CMPR enabled)
LP Delay (CMPR disabled)
LP Width
Panel Format 1
Panel Format 2
Display Type
Power Down Control
Panel Format 3
Panel Interface
Horizontal Compensation
Horizontal Centering
Vertical Compensation
Vertical Centering
Vertical Line Replication
Vertical Line Replication
Power Sequencing Delay
FP Diagnostic
M (ACDCLK) Control
Alternate Vertical Total
Alternate Overflow
Alternate Vertical Sync Start
Alternate Vertical Sync End
Vertical Panel Size
Programmable Output Drive
Polynomial FRC Control
Frame Buffer Control
Note: 1) Bold text indicates registers with values different from those shown in Table #1
2) Non-bold text indicates additional registers (not included in Table #1)
Revision 1.2
205
65540 / 545
Programming
Table #10 - Parameters for 640x480 Plasma Panels with 16 Internal Gray Levels
Extension Register Values for Matsushita S804
Register Value (in Hex) Register
XR19
XR1A
XR1B
XR1C
XR2C
XR2D
XR2E
XR2F
XR4F
XR50
XR51
XR52
XR53
XR54
XR55
XR56
XR57
XR58
XR59
XR5A
XR5B
XR5D
XR5E
XR64
XR65
XR66
XR67
XR68
XR6C
XR6E
XR6F
60
00
60
4F
04
62
6D
08
04
17
C4
41
0C
39
E5
00
1B
00
84
00
8F
10
80
0D
26
E8
0A
DF
02
0D
00
Comments
Note: 1) Bold text indicates registers with values different from those shown in Table #1
2) Non-bold text indicates additional registers (not included in Table #1)
Revision 1.2
206
65540 / 545
Programming
52
15
54
4F
0C
4F
4E
81
04
17
44
41
0C
F9
E5
00
1B
00
84
00
8F
10
80
F0
07
E5
05
DF
02
9D
00
Comments
Note: 1) Bold text indicates registers with values different from those shown in Table #1
2) Non-bold text indicates additional registers (not included in Table #1)
Revision 1.2
207
65540 / 545
Programming
Revision 1.2
208
65540 / 545
(16-bit)
(32-bit)
(32-bit)
Revision 1.2
209
65540 / 545
Revision 1.2
RESET 33 ohm
210
RESET#
(65545 Only)
XTALI
XTALO
ISA Bus
PCI Bus
ADS#
<ALE>
"FRAME#"
M/IO#
<AEN>
"PAR"
W/R#
<MEMR#> "IDSEL"
LCLK (2XCLK) <IORD#> "STOP#"
LRDY#
<RDY>
"TRDY#"
LDEV#
<IOWR#> "DEVSEL#"
RRTN# (CRST) <MEMW#> "IRDY#"
A27 (ENABKL)
A26
(ACTI)
A25
<IRQ>
"SERR#"
A24
<ROMCS#> "PERR#"
A23
<LA23>
"Reserved"
A22
<LA22>
"CLK"
A21
<LA21>
"Reserved"
A20
<LA20>
"Reserved"
A19
<LA19>
"Reserved"
A18
<LA18>
"Reserved"
A17
<LA17>
"Reserved"
A16
<A16>
"Reserved"
A15
<A15>
"Reserved"
Bus
A14 Interface <A14>
"Reserved"
A13
<A13>
"Reserved"
A12 Default
<A12>
"Reserved"
A11 Names
<A11>
"Reserved"
A10 Indicate
<A10>
"Reserved"
A9
<A9>
"Reserved"
VL-Bus
A8
"Reserved"
or 1x/2x <A8>
A7 486 CPU <A7>
"Reserved"
A6
<A6>
"Reserved"
Direct
A5 Local Bus <A5>
"Reserved"
A4
<A4>
"Reserved"
A3
<A3>
"Reserved"
A2
<A2>
"Reserved"
BE3#
<RFSH#> "C/BE3#"
BE2#
<A1>
"C/BE2#"
BE1#
<BHE#>
"C/BE1#"
BE0#
<A0>
"C/BE0#"
D31
<Reserved> "AD31"
D30
<Reserved> "AD30"
D29
<Reserved> "AD29"
D28
<Reserved> "AD28"
D27
<Reserved> "AD27"
D26
<Reserved> "AD26"
D25
<Reserved> "AD25"
D24
<Reserved> "AD24"
D23
<Reserved> "AD23"
D22
<Reserved> "AD22"
D21
<Reserved> "AD21"
D20
<Reserved> "AD20"
D19
<Reserved> "AD19"
D18
<IOCS16#> "AD18"
D17
<MCS16#> "AD17"
D16
<ZWS#>
"AD16"
D15
<D15>
"AD15"
D14
<D14>
"AD14"
D13
<D13>
"AD13"
D12
<D12>
"AD12"
D11
<D11>
"AD11"
D10
<D10>
"AD10"
D9
<D9>
"AD9"
D8
<D8>
"AD8"
D7
<D7>
"AD7"
D6
<D6>
"AD6"
D5
<D5>
"AD5"
D4
<D4>
"AD4"
D3
<D3>
"AD3"
D2
<D2>
"AD2"
D1
<D1>
"AD1"
D0
<D0>
"AD0"
65540
or
65545
65540 / 545
Revision 1.2
RESET#
VL-B42
14.31818 MHz
ADS#
VL-A45
VL-B44 M/IO#
VL-B45 W/R#
LCLK
VL-B56 LRDY#
VL-A48
LDEV#
VL-A49
VL-B48 RDYRTN#
A27
VL-B24
VL-A23 A26
A25
VL-B25
A24
VL-A25
VL-B26 A23
A22
VL-A26
A21
VL-B27 A20
VL-A28
A19
VL-B28
VL-A29 A18
A17
VL-B30 A16
VL-A30 A15
VL-B31 A14
VL-A31 A13
VL-B33 A12
VL-A32 A11
VL-B34 A10
VL-A33 A09
VL-B35 A08
VL-A34 A07
VL-B36 A06
VL-A36 A05
VL-B37 A04
VL-A37 A03
VL-B39 A02
VL-B40 BE3#
VL-A44 BE2#
VL-A42 BE1#
VL-A41 BE0#
VL-A39 D31
VL-A20 D30
VL-B19 D29
VL-A19 D28
VL-B18 D27
VL-A18 D26
VL-B17 D25
VL-A16 D24
VL-B16 D23
VL-A15 D22
VL-B15 D21
VL-A14 D20
VL-B13 D19
VL-A13 D18
VL-B12 D17
VL-A11 D16
VL-B11 D15
VL-A09 D14
VL-B10 D13
VL-A08 D12
VL-B08 D11
VL-A07 D10
VL-B07 D09
VL-A06 D08
VL-B05 D07
VL-A05 D06
VL-B04 D05
VL-A04 D04
VL-B03 D03
VL-A02 D02
VL-B02 D01
VL-A01 D00
VL-B01
211
207
203
204
22
31
11
27
24
25
23
54
53
30
29
28
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
183
182
180
179
10
21
32
43
1
2
3
4
5
6
7
8
13
14
15
16
17
18
19
20
33
34
35
36
37
38
40
41
44
45
46
47
48
49
50
51
RESET#
(65545 Only)
XTALI
XTALO
ISA Bus
PCI Bus
ADS#
<ALE>
"FRAME#"
M/IO#
<AEN>
"PAR"
W/R#
<MEMR#> "IDSEL"
LCLK (2XCLK) <IORD#> "STOP#"
LRDY#
<RDY>
"TRDY#"
LDEV#
<IOWR#> "DEVSEL#"
RRTN# (CRST) <MEMW#> "IRDY#"
A27 (ENABKL)
A26
(ACTI)
A25
<IRQ>
"SERR#"
A24
<ROMCS#> "PERR#"
A23
<LA23>
"Reserved"
A22
<LA22>
"CLK"
A21
<LA21>
"Reserved"
A20
<LA20>
"Reserved"
A19
<LA19>
"Reserved"
A18
<LA18>
"Reserved"
A17
<LA17>
"Reserved"
A16
<A16>
"Reserved"
A15
<A15>
"Reserved"
Bus
A14 Interface <A14>
"Reserved"
A13
<A13>
"Reserved"
A12 Default
<A12>
"Reserved"
A11 Names
<A11>
"Reserved"
A10 Indicate
<A10>
"Reserved"
A9
<A9>
"Reserved"
VL-Bus
A8
"Reserved"
or 1x/2x <A8>
A7 486 CPU <A7>
"Reserved"
A6
<A6>
"Reserved"
Direct
A5 Local Bus <A5>
"Reserved"
A4
<A4>
"Reserved"
A3
<A3>
"Reserved"
A2
<A2>
"Reserved"
BE3#
<RFSH#> "C/BE3#"
BE2#
<A1>
"C/BE2#"
BE1#
<BHE#>
"C/BE1#"
BE0#
<A0>
"C/BE0#"
D31
<Reserved> "AD31"
D30
<Reserved> "AD30"
D29
<Reserved> "AD29"
D28
<Reserved> "AD28"
D27
<Reserved> "AD27"
D26
<Reserved> "AD26"
D25
<Reserved> "AD25"
D24
<Reserved> "AD24"
D23
<Reserved> "AD23"
D22
<Reserved> "AD22"
D21
<Reserved> "AD21"
D20
<Reserved> "AD20"
D19
<Reserved> "AD19"
D18
<IOCS16#> "AD18"
D17
<MCS16#> "AD17"
D16
<ZWS#>
"AD16"
D15
<D15>
"AD15"
D14
<D14>
"AD14"
D13
<D13>
"AD13"
D12
<D12>
"AD12"
Circuit <D11>
Example "AD11"
D11
D10 6554x VL-Bus
<D10>/ 486 "AD10"
D9
<D9> Local "AD9"
CPU Direct
D8
<D8>
"AD8"
Bus
Interface
D7
<D7>
"AD7"
D6
<D6>
"AD6"
D5
<D5>
"AD5"
D4
<D4>
"AD4"
D3
<D3>
"AD3"
D2
<D2>
"AD2"
D1
<D1>
"AD1"
D0
<D0>
"AD0"
65540
or
65545
65540 / 545
INTA#
INTB#
INTC#
INTD#
n/c PRSNT1#
n/c PRSNT2#
n/c Reserved
n/c Reserved
n/c Reserved
n/c Reserved
n/c Reserved
n/c Reserved
+V-I/O
To
+V-I/O
65545
+V-I/O
IVcc
+V-I/O
+V-I/O
Pins
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+12V
12V
NOTE: Can use external
14.31818MHz
oscillator into
XTALI (with
XTALO not
connected)by
connecting pin
150 (AA5/OC#)
to GND via a
4.7K resistor.
CircuitExample
65545 Interface to
PCI Local Bus
Revision 1.2
PCI-B18
PCI-A17
PCI-A60
PCI-B60
PCI-A06
PCI-B07
PCI-A07
PCI-B08
PCI-B09
PCI-B11
PCI-A09
PCI-B10
PCI-A11
PCI-A14
PCI-B14
PCI-A19
PCI-A10
PCI-A16
PCI-B19
PCI-A59
PCI-B59
PCI-A05
PCI-B05
PCI-B06
PCI-A08
PCI-A61
PCI-B61
PCI-A62
PCI-B62
PCI-A21
PCI-B25
PCI-A27
PCI-B31
PCI-A33
PCI-B36
PCI-A39
PCI-B41
PCI-B43
PCI-A45
PCI-A53
PCI-B54
PCI-A02
PCI-B01
PCI-B03
PCI-B15
PCI-B17
PCI-A18
PCI-B22
PCI-A24
PCI-B28
PCI-A30
PCI-B34
PCI-A35
PCI-A37
PCI-B38
PCI-A42
PCI-B46
PCI-A48
PCI-B49
PCI-A56
PCI-B57
PCI-A15
RST#
14.318 MHz
FRAME#
PAR
IDSEL
STOP#
TRDY#
DEVSEL#
IRDY#
PCI-A34
PCI-A43
PCI-A26
PCI-A38
PCI-A36
PCI-B37
PCI-B35
Use as ACTI & ENABKL
SERR#
PCI-B42 PERR#
PCI-B40
PCI-B16
PCI-B39
PCI-A41
PCI-A40
PCI-A12
PCI-B12
PCI-A13
PCI-B13
PCI-A50
PCI-B50
PCI-A51
PCI-B51
PCI-A01
PCI-B02
PCI-A03
PCI-B04
PCI-A04
PCI-B26
PCI-B33
PCI-B44
PCI-A52
PCI-B20
PCI-A20
PCI-B21
PCI-A22
PCI-B23
PCI-A23
PCI-B24
PCI-A25
PCI-B27
PCI-A28
PCI-B29
PCI-A29
PCI-B30
PCI-A31
PCI-B32
PCI-A32
PCI-A44
PCI-B45
PCI-A46
PCI-B47
PCI-A47
PCI-B48
PCI-A49
PCI-B52
PCI-B53
PCI-A54
PCI-B55
PCI-A55
PCI-B56
PCI-A57
PCI-B58
PCI-A58
CLK
LOCK#
SBO#
SDONE
Keyway
Keyway
Keyway
Keyway
Keyway
Keyway
Keyway
Keyway
TRST#
TCK
TMS
TDO
TDI
C/BE3#
C/BE2#
C/BE1#
C/BE0#
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD09
AD08
AD07
AD06
AD05
AD04
AD03
AD02
AD01
AD00
212
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
207
203
204
22
31
11
27
24
25
23
54
53
30
29
28
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
183
182
180
179
10
21
32
43
1
2
3
4
5
6
7
8
13
14
15
16
17
18
19
20
33
34
35
36
37
38
40
41
44
45
46
47
48
49
50
51
RESET#
XTALI
XTALO
ISA Bus
ADS#
<ALE>
M/IO#
<AEN>
W/R#
<MEMR#>
LCLK (2XCLK) <IORD#>
LRDY#
<RDY>
LDEV#
<IOWR#>
RRTN# (CRST) <MEMW#>
A27 (ENABKL)
A26
(ACTI)
A25
<IRQ>
A24
<ROMCS#>
A23
<LA23>
A22
<LA22>
A21
<LA21>
A20
<LA20>
A19
<LA19>
A18
<LA18>
A17
<LA17>
Bus
A16 Interface <A16>
A15
<A15>
A14 Default
<A14>
A13 Names
<A13>
A12 Indicate
<A12>
A11 VL-Bus
<A11>
A10 or 1x/2x <A10>
A9 486 CPU <A9>
A8
<A8>
Direct
A7 Local Bus <A7>
A6
<A6>
A5
<A5>
A4
<A4>
A3
<A3>
A2
<A2>
BE3#
<RFSH#>
BE2#
<A1>
BE1#
<BHE#>
BE0#
<A0>
D31
<Reserved>
D30
<Reserved>
D29
<Reserved>
D28
<Reserved>
D27
<Reserved>
D26
<Reserved>
D25
<Reserved>
D24
<Reserved>
D23
<Reserved>
D22
<Reserved>
D21
<Reserved>
D20
<Reserved>
D19
<Reserved>
D18
<IOCS16#>
D17
<MCS16#>
D16
<ZWS#>
D15
<D15>
D14
<D14>
D13
<D13>
D12
<D12>
D11
<D11>
D10
<D10>
D9
<D9>
D8
<D8>
D7
<D7>
D6
<D6>
D5
<D5>
D4
<D4>
D3
<D3>
D2
<D2>
D1
<D1>
D0
<D0>
65545
PCI Bus
"FRAME#"
"PAR"
"IDSEL"
"STOP#"
"TRDY#"
"DEVSEL#"
"IRDY#"
"SERR#"
"PERR#"
"Reserved"
"CLK"
"Reserved"
"Reserved"
"Reserved"
"Reserved"
"Reserved"
"Reserved"
"Reserved"
"Reserved"
"Reserved"
"Reserved"
"Reserved"
"Reserved"
"Reserved"
"Reserved"
"Reserved"
"Reserved"
"Reserved"
"Reserved"
"Reserved"
"Reserved"
"C/BE3#"
"C/BE2#"
"C/BE1#"
"C/BE0#"
"AD31"
"AD30"
"AD29"
"AD28"
"AD27"
"AD26"
"AD25"
"AD24"
"AD23"
"AD22"
"AD21"
"AD20"
"AD19"
"AD18"
"AD17"
"AD16"
"AD15"
"AD14"
"AD13"
"AD12"
"AD11"
"AD10"
"AD9"
"AD8"
"AD7"
"AD6"
"AD5"
"AD4"
"AD3"
"AD2"
"AD1"
"AD0"
65540 / 545
J3 DK PCB
Panel
Connector
XR04[1-0] 00
01
10
11
Display Int
Ext
Mem
FB
FB
A&B A&B Opt
A
A
Opt
A&C
A
n/a
---- Reserved ----
XR6F[7]
XR6F[2]
XR05[3]
XR05[4]
XR05[5]
XR05[6]
XR05[7]
XR6C[4]
XR6C[5]
n/c
n/c
n/c
VG1
Revision 1.2
65
64
154
99
54
53
VB7
VB6
VB5
VB4
VB3
VB2
MAD15-0
AA8-0
RASA#
(CASA#) CASAH#
(WEAL#) CASAL#
(WEAH#)
WEA#
OEAB#
J349
J348
J346
J345
J343
J342
J340
J339
J22
J24
J242
J244
J246
J248
J250
J26
J28
J210
J212
J214
J216
J211
J213
J218
J220
J222
J224
J226
J228
J223
J225
J230
J232
J234
J236
J238
J240
J235
J237
Reserved n/c
J25
J27
J29
J2 DK PCB
PC-Video
Connector
J215
J217
J219
J221
J227
J229
J231
J233
J239
101
103
104
102
100
D15:0
A8:0
RAS 256K
CU x16
CL DRAM
WE
OE
DRAM
"C"
Optional
123
125
126
124
D15:0
A8:0
RAS 256K
CU x16
CL DRAM
WE
OE
DRAM
"B"
Optional
156
159
160
157
155
D15:0
A8:0
RAS 256K
CU x16
CL DRAM
WE
OE
DRAM
"A"
MBD15-0
RASB#
(CASB#) CASBH#
(WEBL#) CASBL#
(WEBL#)
WEB#
(CFG8-0)
VR7
VR6
VR5
VR4
VR3
VR2
VR1
VR0
VG7
VG6
VG5
VG4
VG3
VG2
VG1
VG0
VB7
VB6
VB5
VB4
VB3
VB2
VB1
VB0
VG7
VG6
VG5
VG4
VG3
VG2
65540 / 545
Reserved
Reserved
HSYNC
VSYNC
KEY
PCLK
Reserved
VR5
VR4
VR3
VR2
0=2C/1W (A/B)
1=1C/2W (A/B)
0=2C/1W (C)
1=1C/2W (C)
HSYNC
VSYNC
(VR0)
AA9
(VG0)
CA9
(VB1) (A27) (GPIO1) ENABKL
(VB0) (A26) (GPIO0)
ACTI
(VR5-2,VG7-2,VB7-2) MCD15-0
(VG1,P23-16)
CA8-0
(KEY)
RASC#
(VR7)
(CASC#) CASCH#
(VR6)
(WECL#) CASCL#
(PCLK)
(WECH#)
WEC#
(VR1)
OEC#
P23
P22
P21
P20
P19
P18
P17
P16
P23
P22
P21
P20
P19
P18
P17
P16
213
Circuit Example
Display Memory / PC-Video Circuit
Provides base 512KB embedded
frame buffer & display memory
65540 / 545
70
69
68
67
STNDBY# 178
ENAVDD
(ENABKL)
ENAVEE
(GPIO1)* (A27) ENABKL
(GPIO0)** (A26)
ACTI
SHFCLK
M
LP
FLM
DE
(BLANK#) (DE)
(BLANK#) (DE)
62
61
54
53
J5 = DK PCB
26-Pin Connector
J3-13
J3-7
J3-10
J3-11
J3-8
SHFCLK
M
LP
FLM
DE
J5-9
J5-1
J5-5
J5-3
J5-2
J3-4
J3-1
J3-3
J3-2
VDDSAFE
VEESAFE
12VSAFE
J5-6
J5-8
J5-12
J5-10
Circuitry
Reserved
VDDSAFE
VEESAFE
12VSAFE
ENABKL
J3-5
ENABKL
J5-4
65540
or
65545
FlatPanel
VGAController
CA7
CA6
CA5
CA4
CA3
CA2
CA1
CA0
P15
P14
P13
P12
P11
P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
P0
97
96
95
94
93
92
91
90
88
87
86
85
84
83
82
81
79
78
76
75
74
73
72
71
R 60
G 58
B 57
AVCC 59
RSET 55
AGND 56
P23
P22
P21
P20
P19
P18
P17
P16
P15
P14
P13
P12
P11
P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
P0
Rset 1%
22
uF
J3-49
J3-48
J3-46
J3-45
J3-43
J3-42
J3-40
J3-39
J3-37
J3-36
J3-34
J3-33
J3-31
J3-30
J3-28
J3-27
J3-25
J3-24
J3-22
J3-21
J3-19
J3-18
J3-16
J3-15
4.7 uH
+5V
P7
P6
P5
P4
P3
P2
P1
P0
(LD0)
(LD1)
(LD2)
(LD3)
(UD0)
(UD1)
(UD2)
(UD3)
150, 2%
FB
HSYNC 65
(DDC1CLK)VSYNC 64
Note: DDC2CLK* 5V
Digital Ground DDCDAT**
Analog Ground
15K
J5-19
J5-21
J5-23
J5-25
J5-11
J5-13
J5-15
J5-17
0.1 0.047
270
J5-7
J5-14
J5-16
J5-18
J5-20
J5-22
J5-24
J5-26
5V
220pF
HSYNC
VSYNC
.001uF
n/c
(MS3)ENABKL*
(MS2) n/c
(MS1)ACTI**
(MS0) n/c
J1-6
J1-7
J1-8
J1-13
J1-14
J1-9
J1-15
J1-4
J1-12
J1-11
214
65540 / 545
Plasma / EL Panels
Panel
Panel
Panel Panel
Resolution Technology Drive Interface
640x480
Plasma
SS
8-bit
640x480
EL
SS
8-bit
Panel Data
Transfer
2 Pixels/Clk
2 Pixels/Clk
Panel
Gray
Levels Page
16
217
16
218
Part Number
EG-9005F-LS
G6481L-FF
LM64P80
LCM-6494-24NTK
LMG5364XUFC
Panel
Panel
Panel Panel
Resolution Technology Drive Interface
640x480
LCD
DD
8-bit
640x480
LCD
DD
8-bit
640x480
LCD
DD
8-bit
640x480
LCD
DD
8-bit
640x480
LCD
DD
8-bit
Panel Data
Transfer
8 Pixels/Clk
8 Pixels/Clk
8 Pixels/Clk
8 Pixels/Clk
8 Pixels/Clk
Panel
Gray
Levels
2
2
2
2
2
Page
219
220
221
222
223
LCM-5491-24NAK
ECM-A9071
1024x768
1024x768
LCD
LCD
16 Pixels/Clk
16 Pixels/Clk
2
2
224
225
Part Number
TM26D50VC2AA
LQ9D011
LTM-09C015-1
LQ10D311
Panel
Resolution
640x480
640x480
640x480
640x480
Panel
Technology
TFT LCD
TFT LCD
TFT LCD
TFT LCD
Panel Data
Transfer
1 Pixel/Clk
1 Pixel/Clk
1 Pixel/Clk
1 Pixel/Clk
Panel
Colors
512
512
512
256K
Page
226
227
228
229
LQ10DX01
1024x768
TFT LCD
2 Pixels/Clk
512
230
Mfr
Part Number
1) Matsushita S804
2) Sharp
LJ64ZU50
3)
4)
5)
6)
7)
Mfr
Epson
Citizen
Sharp
Sanyo
Hitachi
8) Sanyo
9) Epson
Mfr
Hitachi
Sharp
Toshiba
Sharp
14) Sharp
Part Number
LM-CK53-22NEZ
LCM5327-24NAK
LM64C031
Panel
Resolution
640x480
640x480
640x480
Panel
Technology
STN LCD
STN LCD
STN LCD
18)
19)
20)
21)
22)
23)
24)
KCL6448
LMG9720XUFC
LM64C08P
LCM5331-22NTK
LMG9721XUFC
TLX-8062S-C3X
DMF-50351NC-FW
640x480
640x480
640x480
640x480
640x480
640x480
640x480
STN LCD
STN LCD
STN LCD
STN LCD
STN LCD
STN LCD
STN LCD
Kyocera
Hitachi
Sharp
Sanyo
Hitachi
Toshiba
Optrex
DD
DD
16-bit
16-bit
Panel Panel
Drive Interface
SS
9-bit
SS
9-bit
SS
9-bit
SS
18-bit
SS
18-bit
Panel Panel
Panel Data
Panel
Drive Interface
Transfer
Colors
SS
16-bit 5-1/3 Pixels/Clk 8
SS
16-bit 5-1/3 Pixels/Clk 8
SS
8-bit 2-2/3 Pixels/Clk 8
DD
DD
DD
DD
DD
DD
DD
8-bit
8-bit
16-bit
16-bit
16-bit
16-bit
16-bit
2-2/3 Pixels/Clk
2-2/3 Pixels/Clk
5-1/3 Pixels/Clk
5-1/3 Pixels/Clk
5-1/3 Pixels/Clk
5-1/3 Pixels/Clk
5-1/3 Pixels/Clk
8
8
8
8
8
8
8
Page
231
232
233
234
235
236
237
238
239
240
Glossary:
SS = Single Panel Single Scan
DD = Dual Panel Dual Scan
TFT = Thin Film Transistor ('Active Matrix')
STN = Super Twist Nematic ('Passive Matrix')
Revision 1.2
215
65540 / 545
UD3
UD7
B0
B0
B00
R1...
R1...
UR1... UR1...
72
P1
15
16
UD2
UD6
B1
B1
B01
B1...
G1...
UG1... UG1...
73
P2
13
18
UD1
UD5
B2
B2
B02
G2...
B1...
UB1... UB1...
74
P3
11
19
UD0
UD4
B3
B3
B03
R3...
R2...
UR2... UR2...
75
P4
25
21
LD3
UD3
B4
B4
B10
B3...
G2...
LR1... LR1...
76
P5
23
22
LD2
UD2
G0
B5
B11
G4...
B2...
LG1... LG1...
78
P6
21
24
LD1
UD1
G1
B6
B12
R5...
R3...
LB1... LB1...
79
P7
19
25
LD0
UD0
G2
B7
B13
B5...
G3...
LR2... LR2...
81
P8
27
P0
LD7
G3
G0
G00
SHFCLKU B3...
UG2...
82
P9
28
P1
LD6
G4
G1
G01
R4...
UB2...
83
P10
30
P2
LD5
G5
G2
G02
G4...
UR3...
84
P11
31
P3
LD4
R0
G3
G03
B4...
UG3...
85
P12
33
P4
LD3
R1
G4
G10
R5...
LG2...
86
P13
34
P5
LD2
R2
G5
G11
G5...
LB2...
87
P14
36
P6
LD1
R3
G6
G12
B5...
LR3...
88
P15
37
P7
LD0
R4
G7
G13
R6...
LG3...
90
P16
39
R0
R00
91
P17
40
R1
R01
92
P18
42
R2
R02
93
P19
43
R3
R03
94
P20
45
R4
R10
95
P21
46
R5
R11
96
P22
48
R6
R12
97
P23
49
R7
R13
54/61 ENABKL
4
5
ENABKLENABKLENABKL ENABKL ENABKL ENABKL ENABKL ENABKLENABKLENABKL
70
SHFCLK
9
13
SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK SHFCLKLSHFCLK SHFCLK SHFCLK
69
M
1
7
M
M
M
M
M
M
M
M
M
M
68
LP
5
10
LP
LP
LP
LP
LP
LP
LP
LP
LP
LP
67
FLM
3
11
FLM
FLM
FLM
FLM
FLM
FLM
FLM
FLM
FLM
FLM
68/69
DE
2
8
DE
DE
DE
DE
DE
DE
DE
DE
DE
DE
VDDSAFE 6, 8
1
+12VSAFE
10
2
VEESAFE
12
3
GND
7,14,
6,9,12,14,
16,18, 17,20,23,26,
20,22, 29,32,35,38,
24,26
41,44,47,50
M
FLM
LP
GND
SHFCLK
UD0
UD1
UD2
UD3
LD0
LD1
LD2
LD3
J
1
3
5
7
9
11
13
15
17
19
21
23
25
[+5V] VDDSAFE
VEESAFE
ENABKL
M
5
GND
2 DE
FLM
4 ENABKL
SHFCLK
6 VDDSAFE (+5V)
P0
8 VDDSAFE (+5V)
GND
P3
10 +12 VSAFE
P4
12 VEESAFE
GND
14 GND
P7
16 GND
(-12V TO -45V)
P8
18 GND
or
GND
P11
20 GND
(+12V TO +45V)
P12
22 GND
GND
24 GND
P15
26 GND
P16
GND
P19
P20
DevelopmentBoard
GND
Panel Connectors
P23
Revision 1.2
J3
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
216
+12 VSAFE
Reserved
GND
DE
LP
GND
GND
P1
P2
GND
P5
P6
GND
P9
P10
GND
P13
P14
GND
P17
P18
GND
P21
P22
GND
GND
GND
GND
GND
GND
VR1
VR0
GND
GND
GND
GND
VG1
VG0
GND
GND
GND
GND
VB1
VB0
GND
GND
[Reserved]
GND
GND
GND
J2
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
[DPCLK]
[BLANK#]
VR7
VR6
VR5
VR4
VR3
VR2
VG7
VG6
VG5
VG4 Development
VG3
Board
VG2
PC-Video
VB7
Connector
VB6
VB5
VB4
VB3
VB2
HSYNC
VSYNC
KEY
PCLK
[Reserved]
65540 / 545
Programming Recommendations/Requirements
ENABKL
Reserved
BLANK#/DE
M (ACDCLK)
GND
PNL23
PNL22
PNL21
PNL20
PNL19
PNL18
PNL17
PNL16
J3-37
J3-36
J3-34
J3-33
J3-31
J3-30
J3-28
J3-27
PNL15
PNL14
PNL13
PNL12
PNL11
PNL10
PNL9
PNL8
J3-25
J3-24
J3-22
J3-21
J3-19
J3-18
J3-16
J3-15
PNL7
PNL6
PNL5
PNL4
PNL3
PNL2
PNL1
PNL0
J3-1
J3-2
J3-3
n/c
n/c
n/c
SHFCLK
GND
LP
(HS)
GND
FLM
(VS)
GND
J3-49
J3-48
J3-46
J3-45
J3-43
J3-42
J3-40
J3-39
J3-17
J3-20
J3-23
J3-26
J3-29
J3-32
J3-35
J3-38
J3-41
J3-44
J3-47
J3-50
Parameter
Panel Width
Matsushita S804
Panel Height
Panel
Panel Type
Connector
Clock Divide (CD)
34
DISPTMG Shiftclk Div (SD)
27
GND
Gray/Color Levels
25
GND
TFT Data Width
STN Pixel Packing
23
CLOCK# Frame Accel Ena
24
30
29
32
28
GND
HSYNC
GND
VSYNC
GND
14
18
22
26
7
11
15
19
DATA-E0
DATA-E1
DATA-E2
DATA-E3
DATA-O0
DATA-O1
DATA-O2
DATA-O3
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDDSAFE (+5V)
+12VSAFE
VEESAFE (12 to 45)
n/c
n/c
1
3
NC
NC
Register
XR1C
XR65/68
XR51[1-0]
XR50[6-4]
XR51[3]
XR4F[2-0]
XR50[7]
XR53[5-4]
XR6F[1]
Value
4Fh
1DFh
00
001
0
100
0
00
0
XR51[5]
0
XR2F[6]
0
XR2F/2D 062h
XR2F/2E 06Dh
XR2F[3-0] 8h
XR54[6]
0
XR4F[7]
0
XR51[7]
1
XR2F[7]
0
XR2C
04h
XR54[7]
0
XR54[0]
1
XR54[1]
0
XR51[2]
1
Alt
Alt
Alt
Alt
Alt
Alt
Alt
Alt
XR19
XR1A
XR1B
XR65/64
XR65/66
XR67[3-0]
XR55[6]
XR55[7]
GND
GND
GND
GND
GND
GND
GND
GND
GND
31
33
+5V
+5V
8
6
4
2
+12V
+12V
+12V
+12V
XR57[7]
XR55[1]
XR57[1]
XR56
XR59/58
n/a
n/a
Disabled
60h
00h
60h
20Dh
1E8h
0Ah
1
1
M Phase Change
XR5E[7]
M Phase Change Count XR5E[6-0]
21
20
17
16
13
12
10
9
5
Comment
(640 / 8) 1
480 1
No FRC
Set to 1
Set to 1
n/a
n/a
n/a
1
1
0
0
1
00h
000h
Text Compression
XR55[2]
1
AutoDoubling
XR55[5]
1
Text Stretching
XR57[2]
1
Text Stretch Mode
XR57[4-3] 11
Stretching
XR57[5]
0
Stretching Mode
XR57[6]
0
Line Insertion Height XR59[3-0] 0Fh
H/W Line Replication XR59[7]
0
Line Repl Height
XR5A[3-0] 0
Revision 1.2
217
65540 / 545
Programming Recommendations/Requirements
ENABKL
Reserved
BLANK#/DE
M (ACDCLK)
GND
PNL23
PNL22
PNL21
PNL20
PNL19
PNL18
PNL17
PNL16
J3-37
J3-36
J3-34
J3-33
J3-31
J3-30
J3-28
J3-27
PNL15
PNL14
PNL13
PNL12
PNL11
PNL10
PNL9
PNL8
J3-25
J3-24
J3-22
J3-21
J3-19
J3-18
J3-16
J3-15
PNL7
PNL6
PNL5
PNL4
PNL3
PNL2
PNL1
PNL0
J3-1
J3-2
J3-3
n/c
n/c
n/c
SHFCLK
GND
LP
(HS) n/c
GND
FLM
(VS)
GND
J3-49
J3-48
J3-46
J3-45
J3-43
J3-42
J3-40
J3-39
J3-17
J3-20
J3-23
J3-26
J3-29
J3-32
J3-35
J3-38
J3-41
J3-44
J3-47
J3-50
Sharp LJ64ZU50
Panel
Connector
A8
H.D.
B8
GND
A7
B7
CKD
GND
A9
B9
V.D.
GND
A5
B5
A4
B4
A3
B3
A2
B2
D13
D12
D11
D10
D03
D02
D01
D00
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDDSAFE (+5V)
+12VSAFE
VEESAFE (12 to 45)
Parameter
Panel Width
Panel Height
Panel Type
Clock Divide (CD)
Shiftclk Div (SD)
Gray/Color Levels
TFT Data Width
STN Pixel Packing
Frame Accel Ena
Register
XR1C
XR65/68
XR51[1-0]
XR50[6-4]
XR51[3]
XR4F[2-0]
XR50[7]
XR53[5-4]
XR6F[1]
Value
4Fh
1DFh
00
001
0
100
0
00
0
XR51[5]
XR2F[6]
XR2F/2D
XR2F/2E
XR2F[3-0]
XR54[6]
XR4F[7]
XR51[7]
XR2F[7]
XR2C
XR54[7]
XR54[0]
XR54[1]
XR51[2]
0
0
04Fh
04Eh
01h
1
0
1
1
0Ch
1
1
0
1
Alt
Alt
Alt
Alt
Alt
Alt
Alt
Alt
XR19
XR1A
XR1B
XR65/64
XR65/66
XR67[3-0]
XR55[6]
XR55[7]
52h
15h
54h
1F0h
1E5h
0Eh
1
1
n/c
A1
NC
B10
A10
GND
GND
B12
A12
VL
VL
B13
A13
VD
VD
XR57[7]
XR55[1]
XR57[1]
XR56
XR59/58
Comment
(640 / 8) 1
480 1
n/a
n/a
Disabled
No FRC
Set to 1
Set to 1
n/a
n/a
n/a
1
1
0
0
0
00h
000h
Text Compression
XR55[2]
1
AutoDoubling
XR55[5]
1
Text Stretching
XR57[2]
0
Text Stretch Mode
XR57[4-3] 11
Stretching
XR57[5]
0
Stretching Mode
XR57[6]
0
Line Insertion Height XR59[3-0] 0Fh
H/W Line Replication XR59[7]
0
Line Repl Height
XR5A[3-0] 0
Revision 1.2
218
65540 / 545
Programming Recommendations/Requirements
ENABKL
Reserved
BLANK#/DE
M (ACDCLK)
GND
n/c
n/c
n/c
SHFCLK
GND
LP
(HS)
GND
FLM
(VS)
GND
J3-49
J3-48
J3-46
J3-45
J3-43
J3-42
J3-40
J3-39
PNL23
PNL22
PNL21
PNL20
PNL19
PNL18
PNL17
PNL16
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
J3-37
J3-36
J3-34
J3-33
J3-31
J3-30
J3-28
J3-27
PNL15
PNL14
PNL13
PNL12
PNL11
PNL10
PNL9
PNL8
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
J3-25
J3-24
J3-22
J3-21
J3-19
J3-18
J3-16
J3-15
PNL7
PNL6
PNL5
PNL4
PNL3
PNL2
PNL1
PNL0
J3-17
J3-20
J3-23
J3-26
J3-29
J3-32
J3-35
J3-38
J3-41
J3-44
J3-47
J3-50
J3-1
J3-2
J3-3
Epson EG-9005F-LS
Panel
Connector
5
FR
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
XSCL
4
7
8
LP
YSCL
DIN
15
16
17
18
11
12
13
14
LD0
LD1
LD2
LD3
UD0
UD1
UD2
UD3
Register
Value Comment
XR1C
4Fh (640 / 8) 1
XR65/68 1DFh 480 1
XR51[1-0]
XR50[6-4]
XR51[3]
XR4F[2-0]
XR50[7]
XR53[5-4]
XR6F[1]
XR51[5]
XR2F[6]
XR2F/2D
XR2F/2E
XR2F[3-0]
XR54[6]
XR4F[7]
XR51[7]
XR2F[7]
XR2C
XR54[7]
XR54[0]
XR54[1]
XR51[2]
Alt
Alt
Alt
Alt
Alt
Alt
Alt
Alt
XR19
XR1A
XR1B
XR65/64
XR65/66
XR67[3-0]
XR55[6]
XR55[7]
n/c
n/c
VDDSAFE (+5V)
+12VSAFE
VEESAFE (12 to 45)
Parameter
Panel Width
Panel Height
Panel Type
Clock Divide (CD)
Shiftclk Div (SD)
Gray/Color Levels
TFT Data Width
STN Pixel Packing
Frame Accel Ena
19V
10
6
NC
NC
VSS
1
19
20
VDD
EI
EO
VLCD
XR57[7]
XR55[1]
XR57[1]
XR56
XR59/58
Text Compression
XR55[2]
AutoDoubling
XR55[5]
Text Stretching
XR57[2]
Text Stretch Mode
XR57[4-3]
Stretching
XR57[5]
Stretching Mode
XR57[6]
Line Insertion Height XR59[3-0]
H/W Line Replication XR59[7]
Line Repl Height
XR5A[3-0]
Revision 1.2
219
65540 / 545
Programming Recommendations/Requirements
ENABKL
Reserved
BLANK#/DE
M (ACDCLK)
GND
n/c
n/c
n/c
SHFCLK
GND
LP
(HS)
GND
FLM
(VS)
GND
PNL23
PNL22
PNL21
PNL20
PNL19
PNL18
PNL17
PNL16
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
J3-37
J3-36
J3-34
J3-33
J3-31
J3-30
J3-28
J3-27
PNL15
PNL14
PNL13
PNL12
PNL11
PNL10
PNL9
PNL8
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
J3-25
J3-24
J3-22
J3-21
J3-19
J3-18
J3-16
J3-15
PNL7
PNL6
PNL5
PNL4
PNL3
PNL2
PNL1
PNL0
J3-1
J3-2
J3-3
CP
LOAD
10
J3-49
J3-48
J3-46
J3-45
J3-43
J3-42
J3-40
J3-39
J3-17
J3-20
J3-23
J3-26
J3-29
J3-32
J3-35
J3-38
J3-41
J3-44
J3-47
J3-50
Citizen G6481L-FF
Panel
Connector
9
DF
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
18
17
16
15
14
13
12
11
FRAME
LD0
LD1
LD2
LD3
UD0
UD1
UD2
UD3
Parameter
Panel Width
Panel Height
Panel Type
Clock Divide (CD)
Shiftclk Div (SD)
Gray/Color Levels
TFT Data Width
STN Pixel Packing
Frame Accel Ena
Register
Value Comment
XR1C
4Fh (640 / 8) 1
XR65/68 1DFh 480 1
XR51[1-0]
XR50[6-4]
XR51[3]
XR4F[2-0]
XR50[7]
XR53[5-4]
XR6F[1]
XR51[5]
XR2F[6]
XR2F/2D
XR2F/2E
XR2F[3-0]
XR54[6]
XR4F[7]
XR51[7]
XR2F[7]
XR2C
XR54[7]
XR54[0]
XR54[1]
XR51[2]
Alt
Alt
Alt
Alt
Alt
Alt
Alt
Alt
XR19
XR1A
XR1B
XR65/64
XR65/66
XR67[3-0]
XR55[6]
XR55[7]
n/c
n/c
n/c
VDDSAFE (+5V)
NC
NC
NC
VSS
5
4
DISPOFF# H AutoDoubling
V Text Stretching
VDD
1
2
VO
VAA
+12VSAFE
VEESAFE (12 to 45) +28V
6
19
20
XR57[7]
XR55[1]
XR57[1]
XR56
XR59/58
H Text Compression
V
V
V
V
V
V
XR55[2]
XR55[5]
XR57[2]
Text Stretch Mode
XR57[4-3]
Stretching
XR57[5]
Stretching Mode
XR57[6]
Line Insertion Height XR59[3-0]
H/W Line Replication XR59[7]
Line Repl Height
XR5A[3-0]
Revision 1.2
220
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Programming Recommendations/Requirements
ENABKL
Reserved
BLANK#/DE
M (ACDCLK)
GND
n/c
n/c
n/c
n/c
SHFCLK
GND
LP
(HS)
GND
FLM
(VS)
GND
J3-49
J3-48
J3-46
J3-45
J3-43
J3-42
J3-40
J3-39
PNL23
PNL22
PNL21
PNL20
PNL19
PNL18
PNL17
PNL16
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
J3-37
J3-36
J3-34
J3-33
J3-31
J3-30
J3-28
J3-27
PNL15
PNL14
PNL13
PNL12
PNL11
PNL10
PNL9
PNL8
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
J3-25
J3-24
J3-22
J3-21
J3-19
J3-18
J3-16
J3-15
PNL7
PNL6
PNL5
PNL4
PNL3
PNL2
PNL1
PNL0
J3-17
J3-20
J3-23
J3-26
J3-29
J3-32
J3-35
J3-38
J3-41
J3-44
J3-47
J3-50
J3-1
J3-2
J3-3
Sharp LM64P80
Panel
Connector
CP2
CP1
12
13
14
15
8
9
10
11
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DL0
DL1
DL2
DL3
DU0
DU1
DU2
DU3
Register
XR1C
XR65/68
XR51[1-0]
XR50[6-4]
XR51[3]
XR4F[2-0]
XR50[7]
XR53[5-4]
XR6F[1]
XR51[5]
XR2F[6]
0 Enabled
XR2F/2D 050h
XR2F/2E 050h
XR2F[3-0] 0h
XR54[6]
XR4F[7]
0
XR51[7]
XR2F[7]
0 Enabled
XR2C
04h 4 lines
XR54[7]
XR54[0]
XR54[1]
XR51[2]
Alt
Alt
Alt
Alt
Alt
Alt
Alt
Alt
XR19
XR1A
XR1B
XR65/64
XR65/66
XR67[3-0]
XR55[6]
XR55[7]
Value
4Fh
1DFh
11
010
100
0
0
1
Comment
(640 / 8) 1
480 1
DD
Dclk / 4
16Level (61w/dith)
n/a
n/a
Enabled
57h
19h
59h
1E4h
1E0h
1
1 Negative
1 Negative
16-Frame FRC
Set to 1
Set to 1
n/a
256-color modes
M Phase Change
XR5E[7]
1 Every other frame
M Phase Change Count XR5E[6-0] 00h n/a
Compensation Typical Settings
H Compensation
XR55[0]
V Compensation
XR57[0]
Fast Centering Disable
H AutoCentering
V AutoCentering
H Centering
V Centering
VDDSAFE (+5V)
+12VSAFE
VEESAFE (12 to 45)
Parameter
Panel Width
Panel Height
Panel Type
Clock Divide (CD)
Shiftclk Div (SD)
Gray/Color Levels
TFT Data Width
STN Pixel Packing
Frame Accel Ena
18V
VSS
5
4
VDD
DISP
VEE
H
H
V
V
V
V
V
V
V
XR57[7]
XR55[1]
XR57[1]
XR56
XR59/58
1
1
Enabled
Enabled
0
0
1
00h
000h
Enabled
Disabled
Enabled
No left border
No top border
Text Compression
XR55[2]
1
AutoDoubling
XR55[5]
1
Text Stretching
XR57[2]
0
Text Stretch Mode
XR57[4-3] 11
Stretching
XR57[5]
0
Stretching Mode
XR57[6]
0
Line Insertion Height XR59[3-0] 0Fh
H/W Line Replication XR59[7]
0
Line Repl Height
XR5A[3-0] 0
Enabled
Enabled
Disabled
DS+TF,TF,DS
Disabled
n/a
16 1
Disabled
n/a
Revision 1.2
221
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Programming Recommendations/Requirements
ENABKL
Reserved
BLANK#/DE
M (ACDCLK)
GND
n/c
n/c
n/c
SHFCLK
GND
LP
(HS)
GND
FLM
(VS)
GND
J3-49
J3-48
J3-46
J3-45
J3-43
J3-42
J3-40
J3-39
PNL23
PNL22
PNL21
PNL20
PNL19
PNL18
PNL17
PNL16
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
J3-37
J3-36
J3-34
J3-33
J3-31
J3-30
J3-28
J3-27
PNL15
PNL14
PNL13
PNL12
PNL11
PNL10
PNL9
PNL8
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
J3-25
J3-24
J3-22
J3-21
J3-19
J3-18
J3-16
J3-15
PNL7
PNL6
PNL5
PNL4
PNL3
PNL2
PNL1
PNL0
J3-17
J3-20
J3-23
J3-26
J3-29
J3-32
J3-35
J3-38
J3-41
J3-44
J3-47
J3-50
J3-1
J3-2
J3-3
Sanyo LCM-6494-24NTK
Panel
Connector
CN2-18 M
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
CN1-5
CL2
CN1-3
CL1
CN1-1
FLM
Parameter
Panel Width
Panel Height
Panel Type
Clock Divide (CD)
Shiftclk Div (SD)
Gray/Color Levels
TFT Data Width
STN Pixel Packing
Frame Accel Ena
Register
Value Comment
XR1C
4Fh (640 / 8) 1
XR65/68 1DFh 480 1
XR51[1-0]
XR50[6-4]
XR51[3]
XR4F[2-0]
XR50[7]
XR53[5-4]
XR6F[1]
XR51[5]
XR2F[6]
XR2F/2D
XR2F/2E
XR2F[3-0]
XR54[6]
XR4F[7]
XR51[7]
XR2F[7]
XR2C
XR54[7]
XR54[0]
XR54[1]
XR51[2]
Alt
Alt
Alt
Alt
Alt
Alt
Alt
Alt
XR19
XR1A
XR1B
XR65/64
XR65/66
XR67[3-0]
XR55[6]
XR55[7]
CN2-12
CN2-13
CN2-14
CN2-15
CN1-8
CN1-9
CN1-10
CN1-11
LD0
LD1
LD2
LD3
UD0
UD1
UD2
UD3
n/c
n/c
CN1-7
CN2-21
NC
NC
n/c
CN2-24
VO
CN2-20
CN2-19
CN1-6
CN1-4
CN1-2
VSS
VSS
VSS
VSS
VSS
CN2-16
CN2-17
CN2-25
H AutoDoubling
VDD
V Text Stretching
VDD
DISPOFF# V Text Stretch Mode
CN2-23
CN2-22
VEE
VEE
VDDSAFE (+5V)
+12VSAFE
VEESAFE (12 to 45) 23V
XR57[7]
XR55[1]
XR57[1]
XR56
XR59/58
H Text Compression
V
V
V
V
V
XR55[2]
XR55[5]
XR57[2]
XR57[4-3]
Stretching
XR57[5]
Stretching Mode
XR57[6]
Line Insertion Height XR59[3-0]
H/W Line Replication XR59[7]
Line Repl Height
XR5A[3-0]
Revision 1.2
222
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Programming Recommendations/Requirements
ENABKL
Reserved
BLANK#/DE
M (ACDCLK)
GND
n/c
n/c
n/c
n/c
SHFCLK
GND
LP
(HS)
GND
FLM
(VS)
GND
J3-49
J3-48
J3-46
J3-45
J3-43
J3-42
J3-40
J3-39
PNL23
PNL22
PNL21
PNL20
PNL19
PNL18
PNL17
PNL16
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
J3-37
J3-36
J3-34
J3-33
J3-31
J3-30
J3-28
J3-27
PNL15
PNL14
PNL13
PNL12
PNL11
PNL10
PNL9
PNL8
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
J3-25
J3-24
J3-22
J3-21
J3-19
J3-18
J3-16
J3-15
PNL7
PNL6
PNL5
PNL4
PNL3
PNL2
PNL1
PNL0
J3-17
J3-20
J3-23
J3-26
J3-29
J3-32
J3-35
J3-38
J3-41
J3-44
J3-47
J3-50
J3-1
J3-2
J3-3
Hitachi LMG5364XUFC
Panel
Connector
3
CP
LOAD
FRAME
12
13
14
15
8
9
10
11
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
LD0
LD1
LD2
LD3
UD0
UD1
UD2
UD3
Register
Value Comment
XR1C
4Fh (640 / 8) 1
XR65/68 1DFh 480 1
XR51[1-0]
XR50[6-4]
XR51[3]
XR4F[2-0]
XR50[7]
XR53[5-4]
XR6F[1]
XR19
XR1A
XR1B
XR65/64
XR65/66
XR67[3-0]
XR55[6]
XR55[7]
VDDSAFE (+5V)
+12VSAFE
Parameter
Panel Width
Panel Height
Panel Type
Clock Divide (CD)
Shiftclk Div (SD)
Gray/Color Levels
TFT Data Width
STN Pixel Packing
Frame Accel Ena
n/c
23V
VSS
5
4
H AutoDoubling
VDD
DISPOFF# V Text Stretching
VEE
XR57[7]
XR55[1]
XR57[1]
XR56
XR59/58
H Text Compression
V
V
V
V
V
V
XR55[2]
XR55[5]
XR57[2]
Text Stretch Mode
XR57[4-3]
Stretching
XR57[5]
Stretching Mode
XR57[6]
Line Insertion Height XR59[3-0]
H/W Line Replication XR59[7]
Line Repl Height
XR5A[3-0]
Revision 1.2
223
65540 / 545
Programming Recommendations/Requirements
ENABKL
Reserved
BLANK#/DE
M (ACDCLK)
GND
n/c
n/c
n/c
Sanyo LCM-5491-24NAK
Panel
Connector
2
M
SHFCLK
GND
LP
(HS)
GND
FLM
(VS)
GND
CL2
CL1
FLM
J3-49
J3-48
J3-46
J3-45
J3-43
J3-42
J3-40
J3-39
PNL23
PNL22
PNL21
PNL20
PNL19
PNL18
PNL17
PNL16
J3-37
J3-36
J3-34
J3-33
J3-31
J3-30
J3-28
J3-27
PNL15
PNL14
PNL13
PNL12
PNL11
PNL10
PNL9
PNL8
(LD0)
(LD1)
(LD2)
(LD3)
(LD4)
(LD5)
(LD6)
(LD7)
17
18
19
20
21
22
23
24
LD0
LD1
LD2
LD3
LD4
LD5
LD6
LD7
J3-25
J3-24
J3-22
J3-21
J3-19
J3-18
J3-16
J3-15
PNL7
PNL6
PNL5
PNL4
PNL3
PNL2
PNL1
PNL0
(UD0)
(UD1)
(UD2)
(UD3)
(UD4)
(UD5)
(UD6)
(UD7)
9
10
11
12
13
14
15
16
UD0
UD1
UD2
UD3
UD4
UD5
UD6
UD7
J3-17
J3-20
J3-23
J3-26
J3-29
J3-32
J3-35
J3-38
J3-41
J3-44
J3-47
J3-50
J3-1
J3-2
J3-3
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Register
Value Comment
XR1C
7Fh (1024 / 8) 1
XR65/68 2FFh 768 1
XR51[1-0]
XR50[6-4]
XR51[3]
XR4F[2-0]
XR50[7]
XR53[5-4]
XR6F[1]
XR51[5]
XR2F[6]
XR2F/2D
XR2F/2E
XR2F[3-0]
XR54[6]
XR4F[7]
XR51[7]
XR2F[7]
XR2C
XR54[7]
XR54[0]
XR54[1]
XR51[2]
Alt
Alt
Alt
Alt
Alt
Alt
Alt
Alt
XR19
XR1A
XR1B
XR65/64
XR65/66
XR67[3-0]
XR55[6]
XR55[7]
VDDSAFE (+5V)
26
27
5
8
VSS1
VSS1
VSS2
VSS2
25
VDD
28
29
VEE
VEE
+12VSAFE
VEESAFE (12 to 45)
Parameter
Panel Width
Panel Height
Panel Type
Clock Divide (CD)
Shiftclk Div (SD)
Gray/Color Levels
TFT Data Width
STN Pixel Packing
Frame Accel Ena
+36V
XR57[7]
XR55[1]
XR57[1]
XR56
XR59/58
Text Compression
XR55[2]
AutoDoubling
XR55[5]
Text Stretching
XR57[2]
Text Stretch Mode
XR57[4-3]
Stretching
XR57[5]
Stretching Mode
XR57[6]
Line Insertion Height XR59[3-0]
H/W Line Replication XR59[7]
Line Repl Height
XR5A[3-0]
Revision 1.2
224
65540 / 545
Programming Recommendations/Requirements
ENABKL
Reserved
BLANK#/DE
M (ACDCLK)
GND
n/c
n/c
n/c
n/c
SHFCLK
GND
LP
(HS)
GND
FLM
(VS)
GND
Epson ECM-A9071
Panel
Connector
A8
XSCL
A10
VSS
A6
LP
A5
VSS
A7
DIN
J3-49
J3-48
J3-46
J3-45
J3-43
J3-42
J3-40
J3-39
PNL23
PNL22
PNL21
PNL20
PNL19
PNL18
PNL17
PNL16
J3-37
J3-36
J3-34
J3-33
J3-31
J3-30
J3-28
J3-27
PNL15
PNL14
PNL13
PNL12
PNL11
PNL10
PNL9
PNL8
(LD0)
(LD1)
(LD2)
(LD3)
(LD4)
(LD5)
(LD6)
(LD7)
B12
B13
B14
B15
B17
B18
B19
B20
LD0
LD1
LD2
LD3
LD4
LD5
LD6
LD7
J3-25
J3-24
J3-22
J3-21
J3-19
J3-18
J3-16
J3-15
PNL7
PNL6
PNL5
PNL4
PNL3
PNL2
PNL1
PNL0
(UD0)
(UD1)
(UD2)
(UD3)
(UD4)
(UD5)
(UD6)
(UD7)
B2
B3
B4
B5
B7
B8
B9
B10
UD0
UD1
UD2
UD3
UD4
UD5
UD6
UD7
J3-17
J3-20
J3-23
J3-26
J3-29
J3-32
J3-35
J3-38
J3-41
J3-44
J3-47
J3-50
J3-1
J3-2
J3-3
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Parameter
Panel Width
Panel Height
Panel Type
Clock Divide (CD)
Shiftclk Div (SD)
Gray/Color Levels
TFT Data Width
STN Pixel Packing
Frame Accel Ena
Register
Value Comment
XR1C
7Fh (1024 / 8) 1
XR65/68 2FFh 768 1
XR51[1-0]
XR50[6-4]
XR51[3]
XR4F[2-0]
XR50[7]
XR53[5-4]
XR6F[1]
XR51[5]
XR2F[6]
XR2F/2D
XR2F/2E
XR2F[3-0]
XR54[6]
XR4F[7]
XR51[7]
XR2F[7]
XR2C
XR54[7]
XR54[0]
XR54[1]
XR51[2]
Alt
Alt
Alt
Alt
Alt
Alt
Alt
Alt
XR19
XR1A
XR1B
XR65/64
XR65/66
XR67[3-0]
XR55[6]
XR55[7]
VDDSAFE (+5V)
+12VSAFE
B1
B6
B11
B16
VSS
VSS
VSS
VSS
A3
A4
A9
VDD
VDD
DISP
A1
VDDH
A2
VDDH
Voltage not specified in panel data sheet; contact panel manufacturer
for more information.
XR57[7]
XR55[1]
XR57[1]
XR56
XR59/58
Text Compression
XR55[2]
AutoDoubling
XR55[5]
Text Stretching
XR57[2]
Text Stretch Mode
XR57[4-3]
Stretching
XR57[5]
Stretching Mode
XR57[6]
Line Insertion Height XR59[3-0]
H/W Line Replication XR59[7]
Line Repl Height
XR5A[3-0]
Revision 1.2
225
65540 / 545
Programming Recommendations/Requirements
ENABKL
Reserved
BLANK#/DE
M (ACDCLK)
GND
PNL23
PNL22
PNL21
PNL20
PNL19
PNL18
PNL17
PNL16
J3-37
J3-36
J3-34
J3-33
J3-31
J3-30
J3-28
J3-27
PNL15
PNL14
PNL13
PNL12
PNL11
PNL10
PNL9
PNL8
(R4)
(R3)
(R2)
(R1)
(R0)
(G5)
(G4)
(G3)
J3-25
J3-24
J3-22
J3-21
J3-19
J3-18
J3-16
J3-15
PNL7
PNL6
PNL5
PNL4
PNL3
PNL2
PNL1
PNL0
(G2)
(G1)
(G0)
(B4)
(B3)
(B2)
(B1)
(B0)
J3-1
J3-2
J3-3
n/c
SHFCLK
GND
LP
(HS)
GND
FLM
(VS)
GND
J3-49
J3-48
J3-46
J3-45
J3-43
J3-42
J3-40
J3-39
J3-17
J3-20
J3-23
J3-26
J3-29
J3-32
J3-35
J3-38
J3-41
J3-44
J3-47
J3-50
n/c
n/c
Hitachi TM26D50VC2AA
Panel
Connector
15
DTMG
16
GND
21
20
19
25
17
18
DCLK
GND
HSYNC
GND
VSYNC
GND
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
R3
R2
R1
R0
6
7
8
G3
G2
G1
G0
n/c
n/c
n/c
10
11
12
13
B3
B2
B1
B0
30
31
32
VR1
VR2
VR3
n/c
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
n/c
n/c
n/c
VDDSAFE (+5V)
+12VSAFE
2
3
4
5
n/c
29
14
DOTE
HREV
1
22
GND
GND
23
24
28
VDD
VDD
BLC
26
27
VEE
VEE
Parameter
Panel Width
Panel Height
Panel Type
Clock Divide (CD)
Shiftclk Div (SD)
Gray/Color Levels
TFT Data Width
STN Pixel Packing
Frame Accel Ena
Register
XR1C
XR65/68
XR51[1-0]
XR50[6-4]
XR51[3]
XR4F[2-0]
XR50[7]
XR53[5-4]
XR6F[1]
Value
4Fh
1DFh
00
000
0
100
0
00
0
XR51[5]
XR2F[6]
XR2F/2D
XR2F/2E
XR2F[3-0]
XR54[6]
XR4F[7]
XR51[7]
XR2F[7]
XR2C
XR54[7]
XR54[0]
XR54[1]
XR51[2]
0
0
04Fh
04Fh
0Fh
1
0
1
0
04h
1
1
1
1
Alt
Alt
Alt
Alt
Alt
Alt
Alt
Alt
XR19
XR1A
XR1B
XR65/64
XR65/66
XR67[3-0]
XR55[6]
XR55[7]
56h
13h
5Fh
201h
1DFh
5h
1
1
XR57[7]
XR55[1]
XR57[1]
XR56
XR59/58
Comment
(640 / 8) 1
480 1
n/a
n/a
Disabled
Set to 1
Set to 1
n/a
n/a
n/a
1
1
0
0
0
00h
000h
Text Compression
XR55[2]
1
AutoDoubling
XR55[5]
1
Text Stretching
XR57[2]
1
Text Stretch Mode
XR57[4-3] 11
Stretching
XR57[5]
0
Stretching Mode
XR57[6]
0
Line Insertion Height XR59[3-0] 0Fh
H/W Line Replication XR59[7]
0
Line Repl Height
XR5A[3-0] 0
Revision 1.2
226
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Programming Recommendations/Requirements
ENABKL
Reserved
BLANK#/DE
M (ACDCLK)
GND
PNL23
PNL22
PNL21
PNL20
PNL19
PNL18
PNL17
PNL16
J3-37
J3-36
J3-34
J3-33
J3-31
J3-30
J3-28
J3-27
PNL15
PNL14
PNL13
PNL12
PNL11
PNL10
PNL9
PNL8
(R4)
(R3)
(R2)
(R1)
(R0)
(G5)
(G4)
(G3)
J3-25
J3-24
J3-22
J3-21
J3-19
J3-18
J3-16
J3-15
PNL7
PNL6
PNL5
PNL4
PNL3
PNL2
PNL1
PNL0
(G2)
(G1)
(G0)
(B4)
(B3)
(B2)
(B1)
(B0)
J3-1
J3-2
J3-3
n/c
n/c
n/c
SHFCLK
GND
LP
(HS)
GND
FLM
(VS)
GND
J3-49
J3-48
J3-46
J3-45
J3-43
J3-42
J3-40
J3-39
J3-17
J3-20
J3-23
J3-26
J3-29
J3-32
J3-35
J3-38
J3-41
J3-44
J3-47
J3-50
Sharp LQ9D011
Panel
Connector
CN2-5
ENAB
CN1-8
GND
CN1-1
CN1-2
CN1-3
CN1-8
CN1-4
CN1-12
CK
GND
HSYNC
GND
VSYNC
GND
CN1-7
CN1-6
CN1-5
R2
R1
R0
CN1-11
CN1-10
CN1-9
G2
G1
G0
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
CN1-15
CN1-14
CN1-13
n/c
n/c
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Register
XR1C
XR65/68
XR51[1-0]
XR50[6-4]
XR51[3]
XR4F[2-0]
XR50[7]
XR53[5-4]
XR6F[1]
Value
4Fh
1DFh
00
000
0
100
0
00
0
XR51[5]
XR2F[6]
XR2F/2D
XR2F/2E
XR2F[3-0]
XR54[6]
XR4F[7]
XR51[7]
XR2F[7]
XR2C
XR54[7]
XR54[0]
XR54[1]
XR51[2]
0
0
04Fh
04Fh
0Fh
1
0
1
0
04h
1
1
1
1
Alt
Alt
Alt
Alt
Alt
Alt
Alt
Alt
XR19
XR1A
XR1B
XR65/64
XR65/66
XR67[3-0]
XR55[6]
XR55[7]
56h
13h
5Fh
201h
1DFh
5h
1
1
n/c
VDDSAFE (+5V)
+12VSAFE
B2
B1
B0
Parameter
Panel Width
Panel Height
Panel Type
Clock Divide (CD)
Shiftclk Div (SD)
Gray/Color Levels
TFT Data Width
STN Pixel Packing
Frame Accel Ena
n/c
CN2-6
TST
CN2-3
CN2-4
GND
GND
CN2-1
CN2-2
VCC
VCC
XR57[7]
XR55[1]
XR57[1]
XR56
XR59/58
Comment
(640 / 8) 1
480 1
n/a
n/a
Disabled
Set to 1
Set to 1
n/a
n/a
n/a
1
1
0
0
0
00h
000h
Text Compression
XR55[2]
1
AutoDoubling
XR55[5]
1
Text Stretching
XR57[2]
1
Text Stretch Mode
XR57[4-3] 11
Stretching
XR57[5]
0
Stretching Mode
XR57[6]
0
Line Insertion Height XR59[3-0] 0Fh
H/W Line Replication XR59[7]
0
Line Repl Height
XR5A[3-0] 0
Revision 1.2
227
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Programming Recommendations/Requirements
ENABKL
Reserved
BLANK#/DE
M (ACDCLK)
GND
n/c
n/c
n/c
SHFCLK
GND
LP
(HS) n/c
GND
FLM
(VS) n/c
GND
J3-49
J3-48
J3-46
J3-45
J3-43
J3-42
J3-40
J3-39
PNL23
PNL22
PNL21
PNL20
PNL19
PNL18
PNL17
PNL16
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
J3-37
J3-36
J3-34
J3-33
J3-31
J3-30
J3-28
J3-27
PNL15
PNL14
PNL13
PNL12
PNL11
PNL10
PNL9
PNL8
(R4)
(R3)
(R2)
(R1) n/c
(R0) n/c
(G5)
(G4)
(G3)
J3-25
J3-24
J3-22
J3-21
J3-19
J3-18
J3-16
J3-15
PNL7
PNL6
PNL5
PNL4
PNL3
PNL2
PNL1
PNL0
(G2)
(G1)
(G0)
(B4)
(B3)
(B2)
(B1)
(B0)
J3-17
J3-20
J3-23
J3-26
J3-29
J3-32
J3-35
J3-38
J3-41
J3-44
J3-47
J3-50
J3-1
J3-2
J3-3
Toshiba LTM-09C015-1
Panel
Connector
CN2-7
ENAB
GND
CN1-1
CN1-2
NCLK
GND
CN1-6
GND
CN1-12
GND
CN1-7
CN1-5
CN1-3
R2
R1
R0
CN1-13
CN1-11
CN1-9
G2
G1
G0
n/c
n/c
n/c
CN2-5
CN2-3
CN2-1
B2
B1
B0
n/c
n/c
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
n/c
VDDSAFE (+5V)
+12VSAFE
CN1-8
n/c
CN1-15 NC
CN2-8
CN2-6
GND
GND
CN1-14
GND
CN1-10
CN1-4
GND
GND
CN2-4
CN2-2
GND
GND
CN2-9 VDD
CN2-10 VDD
Parameter
Panel Width
Panel Height
Panel Type
Clock Divide (CD)
Shiftclk Div (SD)
Gray/Color Levels
TFT Data Width
STN Pixel Packing
Frame Accel Ena
Register
XR1C
XR65/68
XR51[1-0]
XR50[6-4]
XR51[3]
XR4F[2-0]
XR50[7]
XR53[5-4]
XR6F[1]
Value
4Fh
1DFh
00
000
0
100
0
00
0
XR51[5]
XR2F[6]
XR2F/2D
XR2F/2E
XR2F[3-0]
XR54[6]
XR4F[7]
XR51[7]
XR2F[7]
XR2C
XR54[7]
XR54[0]
XR54[1]
XR51[2]
0
0
04Fh
04Fh
0Fh
1
0
1
0
04h
1
1
0 Reqd for this panel
1
Alt
Alt
Alt
Alt
Alt
Alt
Alt
Alt
XR19
XR1A
XR1B
XR65/64
XR65/66
XR67[3-0]
XR55[6]
XR55[7]
56h
13h
5Fh
201h
1DFh
5h
1
1
XR57[7]
XR55[1]
XR57[1]
XR56
XR59/58
Comment
(640 / 8) 1
480 1
n/a
n/a
Disabled
Set to 1
Set to 1
n/a
n/a
n/a
1
1
0
0
0
00h
000h
Text Compression
XR55[2]
1
AutoDoubling
XR55[5]
1
Text Stretching
XR57[2]
1
Text Stretch Mode
XR57[4-3] 11
Stretching
XR57[5]
0
Stretching Mode
XR57[6]
0
Line Insertion Height XR59[3-0] 0Fh
H/W Line Replication XR59[7]
0
Line Repl Height
XR5A[3-0] 0
Revision 1.2
228
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Programming Recommendations/Requirements
ENABKL
Reserved
BLANK#/DE
M (ACDCLK)
GND
PNL23
PNL22
PNL21
PNL20
PNL19
PNL18
PNL17
PNL16
J3-37
J3-36
J3-34
J3-33
J3-31
J3-30
J3-28
J3-27
PNL15
PNL14
PNL13
PNL12
PNL11
PNL10
PNL9
PNL8
J3-25
J3-24
J3-22
J3-21
J3-19
J3-18
J3-16
J3-15
PNL7
PNL6
PNL5
PNL4
PNL3
PNL2
PNL1
PNL0
J3-1
J3-2
J3-3
n/c
n/c
n/c
SHFCLK
GND
LP
(HS)
GND
FLM
(VS)
GND
J3-49
J3-48
J3-46
J3-45
J3-43
J3-42
J3-40
J3-39
J3-17
J3-20
J3-23
J3-26
J3-29
J3-32
J3-35
J3-38
J3-41
J3-44
J3-47
J3-50
Sharp LQ10D311
Panel
Connector
CN2-5
ENAB
n/c
n/c
GND
CN1-1
CN1-2
CN1-3
CN1-8
CN1-4
CN1-12
CK
GND
HSYNC
GND
VSYNC
GND
CN1-7
CN1-6
CN1-5
CN3-3
CN3-2
CN3-1
R5
R4
R3
R2
R1
R0
CN1-11
CN1-10
CN1-9
CN3-7
CN3-6
CN3-5
G5
G4
G3
G2
G1
G0
CN1-15
CN1-14
CN1-13
CN3-11
CN3-10
CN3-9
B5
B4
B3
B2
B1
B0
CN3-14
CN3-13
CN3-12
CN2-6
TST
TST
TST
TST
n/c
n/c
n/c
n/c
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
n/c
n/c
n/c
n/c
VDDSAFE (+5V)
+12VSAFE
CN2-4
n/c
CN3-8
CN3-4
CN2-3
GND
GND
GND
CN2-1
CN2-2
VCC
VCC
Parameter
Panel Width
Panel Height
Panel Type
Clock Divide (CD)
Shiftclk Div (SD)
Gray/Color Levels
TFT Data Width
STN Pixel Packing
Frame Accel Ena
Register
Value Comment
XR1C
4Fh (640 / 8) 1
XR65/68 1DFh 480 1
XR51[1-0]
XR50[6-4]
XR51[3]
XR4F[2-0]
XR50[7]
XR53[5-4]
XR6F[1]
XR51[5]
XR2F[6]
XR2F/2D
XR2F/2E
XR2F[3-0]
XR54[6]
XR4F[7]
XR51[7]
XR2F[7]
XR2C
XR54[7]
XR54[0]
XR54[1]
XR51[2]
Alt
Alt
Alt
Alt
Alt
Alt
Alt
Alt
XR19
XR1A
XR1B
XR65/64
XR65/66
XR67[3-0]
XR55[6]
XR55[7]
XR57[7]
XR55[1]
XR57[1]
XR56
XR59/58
Text Compression
XR55[2]
AutoDoubling
XR55[5]
Text Stretching
XR57[2]
Text Stretch Mode
XR57[4-3]
Stretching
XR57[5]
Stretching Mode
XR57[6]
Line Insertion Height XR59[3-0]
H/W Line Replication XR59[7]
Line Repl Height
XR5A[3-0]
Revision 1.2
229
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Programming Recommendations/Requirements
ENABKL
Reserved
BLANK#/DE
M (ACDCLK)
GND
n/c
n/c
n/c
n/c
n/c
Sharp LQ10DX01
Panel
Connector
CN2-2
CK
CN2-1
GND
CN2-4
HSYNC
CN2-3
GND
CN2-6
VSYNC
CN2-5
GND
SHFCLK
GND
LP
(HS)
GND
FLM
(VS)
GND
J3-49
J3-48
J3-46
J3-45
J3-43
J3-42
J3-40
J3-39
PNL23
(even pixel red msb)
PNL22
PNL21
(even pixel red lsb)
PNL20 n/c
PNL19
(odd pixel red msb)
PNL18
PNL17
(odd pixel red lsb)
PNL16 n/c
CN1-7
CN1-6
CN1-5
R12
R11
R10
CN1-4
CN1-3
CN1-2
R02
R01
R00
J3-37
J3-36
J3-34
J3-33
J3-31
J3-30
J3-28
J3-27
PNL15
(even pixel green msb)
PNL14
PNL13
(even pixel green lsb)
PNL12 n/c
PNL11
(odd pixel green msb)
PNL10
PNL9
(odd pixel green lsb)
PNL8 n/c
CN1-14
CN1-13
CN1-12
G12
G11
G10
CN1-11
CN1-10
CN1-9
G02
G01
G00
J3-25
J3-24
J3-22
J3-21
J3-19
J3-18
J3-16
J3-15
PNL7
PNL6
PNL5
PNL4
PNL3
PNL2
PNL1
PNL0
CN1-21
CN1-20
CN1-19
B12
B11
B10
CN1-18
CN1-17
CN1-16
B02
B01
B00
J3-17
J3-20
J3-23
J3-26
J3-29
J3-32
J3-35
J3-38
J3-41
J3-44
J3-47
J3-50
J3-1
J3-2
J3-3
n/c
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Register
Value Comment
XR1C
7Fh (1024 / 8) 1
XR65/68 2FFh 768 1
XR51[1-0]
XR50[6-4]
XR51[3]
XR4F[2-0]
XR50[7]
XR53[5-4]
XR6F[1]
XR51[5]
XR2F[6]
XR2F/2D
XR2F/2E
XR2F[3-0]
XR54[6]
XR4F[7]
XR51[7]
XR2F[7]
XR2C
XR54[7]
XR54[0]
XR54[1]
XR51[2]
Alt
Alt
Alt
Alt
Alt
Alt
Alt
Alt
XR19
XR1A
XR1B
XR65/64
XR65/66
XR67[3-0]
XR55[6]
XR55[7]
n/c
n/c
VDDSAFE (+5V)
+12VSAFE
Parameter
Panel Width
Panel Height
Panel Type
Clock Divide (CD)
Shiftclk Div (SD)
Gray/Color Levels
TFT Data Width
STN Pixel Packing
Frame Accel Ena
+5V
n/c
n/c
CN2-8
CN2-7
TEST2
TEST1
CN1-1
CN1-8
CN1-15
GND
GND
GND
CN2-13
CN2-14
CN2-15
CN2-9
VCC
VCC
VCC
TEST3
CN2-10
CN2-11
CN2-12
VDD
VDD
VDD
XR57[7]
XR55[1]
XR57[1]
XR56
XR59/58
Text Compression
XR55[2]
AutoDoubling
XR55[5]
Text Stretching
XR57[2]
Text Stretch Mode
XR57[4-3]
Stretching
XR57[5]
Stretching Mode
XR57[6]
Line Insertion Height XR59[3-0]
H/W Line Replication XR59[7]
Line Repl Height
XR5A[3-0]
Revision 1.2
230
65540 / 545
Programming Recommendations/Requirements
ENABKL
Reserved
BLANK#/DE
M (ACDCLK)
GND
Sanyo
LM-CK53-22NEZ
(LCM 5330)
Panel
Connector
29
M
n/c
n/c
n/c
SHFCLK
GND
LP
(HS)
GND
FLM
(VS)
GND
25
CL2
27
CL1
30
FLM
J3-49
J3-48
J3-46
J3-45
J3-43
J3-42
J3-40
J3-39
PNL23
PNL22
PNL21
PNL20
PNL19
PNL18
PNL17
PNL16
J3-37
J3-36
J3-34
J3-33
J3-31
J3-30
J3-28
J3-27
PNL15
PNL14
PNL13
PNL12
PNL11
PNL10
PNL9
PNL8
(R6...)
(B5...)
(G5...)
(R5...)
(B4...)
(G4...)
(R4...)
(B3...)
15
23
14
22
13
21
12
20
LD0
UD0
LD1
UD1
LD2
UD2
LD3
UD3
J3-25
J3-24
J3-22
J3-21
J3-19
J3-18
J3-16
J3-15
PNL7
PNL6
PNL5
PNL4
PNL3
PNL2
PNL1
PNL0
(G3...)
(R3...)
(B2...)
(G2...)
(R2...)
(B1...)
(G1...)
(R1...)
11
19
10
18
9
17
8
16
LD4
UD4
LD5
UD5
LD6
UD6
LD7
UD7
J3-17
J3-20
J3-23
J3-26
J3-29
J3-32
J3-35
J3-38
J3-41
J3-44
J3-47
J3-50
J3-1
J3-2
J3-3
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Parameter
Panel Width
Panel Height
Panel Type
Clock Divide (CD)
Shiftclk Div (SD)
Gray/Color Levels
TFT Data Width
STN Pixel Packing
Frame Accel Ena
Register
Value Comment
XR1C
4Fh (640 / 8) 1
XR65/68 1DFh 480 1
XR51[1-0]
XR50[6-4]
XR51[3]
XR4F[2-0]
XR50[7]
XR53[5-4]
XR6F[1]
XR51[5]
XR2F[6]
XR2F/2D
XR2F/2E
XR2F[3-0]
XR54[6]
XR4F[7]
XR51[7]
XR2F[7]
XR2C
XR54[7]
XR54[0]
XR54[1]
XR51[2]
Alt
Alt
Alt
Alt
Alt
Alt
Alt
Alt
XR19
XR1A
XR1B
XR65/64
XR65/66
XR67[3-0]
XR55[6]
XR55[7]
n/c
VDDSAFE (+5V)
NC
26
24
VSS
VSS
6
5
GND
GND
7
28
VDD
DISP
+12VSAFE
VEESAFE (12 to 45) +38V
VO
4
3
VEE
VEE
XR57[7]
XR55[1]
XR57[1]
XR56
XR59/58
Text Compression
XR55[2]
AutoDoubling
XR55[5]
Text Stretching
XR57[2]
Text Stretch Mode
XR57[4-3]
Stretching
XR57[5]
Stretching Mode
XR57[6]
Line Insertion Height XR59[3-0]
H/W Line Replication XR59[7]
Line Repl Height
XR5A[3-0]
6554x Interface - Sanyo LM-CK53-22NEZ ( LCM 5330 ) ( 640x480 Color STN LCD Panel )
Revision 1.2
231
65540 / 545
Programming Recommendations/Requirements
ENABKL
Reserved
BLANK/DE#
M (ACDCLK)
GND
n/c
n/c
n/c
Sanyo LCM-5327-24NAK
Panel
Connector
2
M
SHFCLK
GND
LP
(HS)
GND
FLM
(VS)
GND
CL2
CL1
FLM
J3-49
J3-48
J3-46
J3-45
J3-43
J3-42
J3-40
J3-39
PNL23
PNL22
PNL21
PNL20
PNL19
PNL18
PNL17
PNL16
J3-37
J3-36
J3-34
J3-33
J3-31
J3-30
J3-28
J3-27
PNL15
PNL14
PNL13
PNL12
PNL11
PNL10
PNL9
PNL8
(R6...)
(B5...)
(G5...)
(R5...)
(B4...)
(G4...)
(R4...)
(B3...)
16
8
17
9
18
10
19
11
LD0
UD0
LD1
UD1
LD2
UD2
LD3
UD3
J3-25
J3-24
J3-22
J3-21
J3-19
J3-18
J3-16
J3-15
PNL7
PNL6
PNL5
PNL4
PNL3
PNL2
PNL1
PNL0
(G3...)
(R3...)
(B2...)
(G2...)
(R2...)
(B1...)
(G1...)
(R1...)
20
12
21
13
22
14
23
15
LD4
UD4
LD5
UD5
LD6
UD6
LD7
UD7
J3-17
J3-20
J3-23
J3-26
J3-29
J3-32
J3-35
J3-38
J3-41
J3-44
J3-47
J3-50
J3-1
J3-2
J3-3
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDDSAFE (+5V)
+12VSAFE
n/c
VEESAFE (12 to 45) +36V
Parameter
Panel Width
Panel Height
Panel Type
Clock Divide (CD)
Shiftclk Div (SD)
Gray/Color Levels
TFT Data Width
STN Pixel Packing
Frame Accel Ena
Register
Value Comment
XR1C
4Fh (640 / 8) 1
XR65/68 1DFh 480 1
XR51[1-0]
XR50[6-4]
XR51[3]
XR4F[2-0]
XR50[7]
XR53[5-4]
XR6F[1]
XR51[5]
XR2F[6]
XR2F/2D
XR2F/2E
XR2F[3-0]
XR54[6]
XR4F[7]
XR51[7]
XR2F[7]
XR2C
XR54[7]
XR54[0]
XR54[1]
XR51[2]
Alt
Alt
Alt
Alt
Alt
Alt
Alt
Alt
XR19
XR1A
XR1B
XR65/64
XR65/66
XR67[3-0]
XR55[6]
XR55[7]
26
27
5
8
VSS1
VSS1
VSS2
VSS2
25
3
VDD
DISPOFF
28
29
VEE
VEE
XR57[7]
XR55[1]
XR57[1]
XR56
XR59/58
Text Compression
XR55[2]
AutoDoubling
XR55[5]
Text Stretching
XR57[2]
Text Stretch Mode
XR57[4-3]
Stretching
XR57[5]
Stretching Mode
XR57[6]
Line Insertion Height XR59[3-0]
H/W Line Replication XR59[7]
Line Repl Height
XR5A[3-0]
Revision 1.2
232
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Programming Recommendations/Requirements
ENABKL
Reserved
BLANK#/DE
M (ACDCLK)
GND
n/c
n/c
n/c
n/c
SHFCLK (SCL)
GND
LP
(HS)
GND
FLM
(VS)
GND
J3-49
J3-48
J3-46
J3-45
J3-43
J3-42
J3-40
J3-39
PNL23
PNL22
PNL21
PNL20
PNL19
PNL18
PNL17
PNL16
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
J3-37
J3-36
J3-34
J3-33
J3-31
J3-30
J3-28
J3-27
PNL15
PNL14
PNL13
PNL12
PNL11
PNL10
PNL9
PNL8 (SCH)
n/c
n/c
n/c
n/c
n/c
n/c
n/c
J3-25
J3-24
J3-22
J3-21
J3-19
J3-18
J3-16
J3-15
PNL7
PNL6
PNL5
PNL4
PNL3
PNL2
PNL1
PNL0
J3-17
J3-20
J3-23
J3-26
J3-29
J3-32
J3-35
J3-38
J3-41
J3-44
J3-47
J3-50
J3-1
J3-2
J3-3
Sharp LM64C031
Panel
Connector
3
XCKL
2
LP
YD
(B5...)
(R5...)
(G4...)
(B3...)
(R3...)
(G2...)
(B1...)
(R1...)
17
16
15
14
13
12
11
10
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
XCKU
D7
D6
D5
D4
D3
D2
D1
D0
Parameter
Panel Width
Panel Height
Panel Type
Clock Divide (CD)
Shiftclk Div (SD)
Gray/Color Levels
TFT Data Width
STN Pixel Packing
Frame Accel Ena
Register
Value Comment
XR1C
4Fh (640 / 8) 1
XR65/68 1DFh 480 1
XR51[1-0]
XR50[6-4]
XR51[3]
XR4F[2-0]
XR50[7]
XR53[5-4]
XR6F[1]
XR51[5]
XR2F[6]
XR2F/2D
XR2F/2E
XR2F[3-0]
XR54[6]
XR4F[7]
XR51[7]
XR2F[7]
XR2C
XR54[7]
XR54[0]
XR54[1]
XR51[2]
Alt
Alt
Alt
Alt
Alt
Alt
Alt
Alt
XR19
XR1A
XR1B
XR65/64
XR65/66
XR67[3-0]
XR55[6]
XR55[7]
n/c
VDDSAFE (+5V)
+12VSAFE
NC
18
9
7
VSS
VSS
VSS
VDD
VEE
n/c
+32V
XR57[7]
XR55[1]
XR57[1]
XR56
XR59/58
Text Compression
XR55[2]
AutoDoubling
XR55[5]
Text Stretching
XR57[2]
Text Stretch Mode
XR57[4-3]
Stretching
XR57[5]
Stretching Mode
XR57[6]
Line Insertion Height XR59[3-0]
H/W Line Replication XR59[7]
Line Repl Height
XR5A[3-0]
Revision 1.2
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Programming Recommendations/Requirements
ENABKL
Reserved
BLANK#/DE
M (ACDCLK)
GND
SHFCLK
GND
LP
(HS)
GND
FLM
(VS)
GND
6
30
8
28
1
35
J3-49
J3-48
J3-46
J3-45
J3-43
J3-42
J3-40
J3-39
PNL23
PNL22
PNL21
PNL20
PNL19
PNL18
PNL17
PNL16
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
J3-37
J3-36
J3-34
J3-33
J3-31
J3-30
J3-28
J3-27
PNL15
PNL14
PNL13
PNL12
PNL11
PNL10
PNL9
PNL8
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
J3-25
J3-24
J3-22
J3-21
J3-19
J3-18
J3-16
J3-15
PNL7
PNL6
PNL5
PNL4
PNL3
PNL2
PNL1
PNL0
J3-17
J3-20
J3-23
J3-26
J3-29
J3-32
J3-35
J3-38
J3-41
J3-44
J3-47
J3-50
J3-1
J3-2
J3-3
Kyocera KCL6448
Panel
Connector
10
DF
26
DF
n/c
n/c
n/c
(LR2...)
(LB1...)
(LG1...)
(LR1...)
(UR2...)
(UB1...)
(UG1...)
(UR1...)
5
4
3
2
31
32
33
34
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
LD0
LD1
LD2
LD3
HD0
HD1
HD2
HD3
Register
Value Comment
XR1C
4Fh (640 / 8) 1
XR65/68 1DFh 480 1
XR51[1-0]
XR50[6-4]
XR51[3]
XR4F[2-0]
XR50[7]
XR53[5-4]
XR6F[1]
XR51[5]
XR2F[6]
XR2F/2D
XR2F/2E
XR2F[3-0]
XR54[6]
XR4F[7]
XR51[7]
XR2F[7]
XR2C
XR54[7]
XR54[0]
XR54[1]
XR51[2]
Alt
Alt
Alt
Alt
Alt
Alt
Alt
Alt
XR19
XR1A
XR1B
XR65/64
XR65/66
XR67[3-0]
XR55[6]
XR55[7]
VDDSAFE (+5V)
+12VSAFE
CP
CP
LOAD
LOAD
FRM
FRM
Parameter
Panel Width
Panel Height
Panel Type
Clock Divide (CD)
Shiftclk Div (SD)
Gray/Color Levels
TFT Data Width
STN Pixel Packing
Frame Accel Ena
n/c
18
GND
27
9
7
29
VDD
VDD
DISP#
DISP#
H
H
V
V
V
V
V
V
V
XR57[7]
XR55[1]
XR57[1]
XR56
XR59/58
Text Compression
XR55[2]
AutoDoubling
XR55[5]
Text Stretching
XR57[2]
Text Stretch Mode
XR57[4-3]
Stretching
XR57[5]
Stretching Mode
XR57[6]
Line Insertion Height XR59[3-0]
H/W Line Replication XR59[7]
Line Repl Height
XR5A[3-0]
Revision 1.2
234
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Programming Recommendations/Requirements
ENABKL
Reserved
BLANK#/DE
M (ACDCLK)
GND
n/c
n/c
n/c
n/c
SHFCLK
GND
LP
(HS)
GND
FLM
(VS)
GND
J3-49
J3-48
J3-46
J3-45
J3-43
J3-42
J3-40
J3-39
PNL23
PNL22
PNL21
PNL20
PNL19
PNL18
PNL17
PNL16
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
J3-37
J3-36
J3-34
J3-33
J3-31
J3-30
J3-28
J3-27
PNL15
PNL14
PNL13
PNL12
PNL11
PNL10
PNL9
PNL8
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
J3-25
J3-24
J3-22
J3-21
J3-19
J3-18
J3-16
J3-15
PNL7
PNL6
PNL5
PNL4
PNL3
PNL2
PNL1
PNL0
J3-17
J3-20
J3-23
J3-26
J3-29
J3-32
J3-35
J3-38
J3-41
J3-44
J3-47
J3-50
J3-1
J3-2
J3-3
Hitachi LMG9720XUFC
Panel
Connector
3
CL2
CL1
FLM
12
13
14
15
8
9
10
11
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
LD0
LD1
LD2
LD3
UD0
UD1
UD2
UD3
Register
Value Comment
XR1C
4Fh (640 / 8) 1
XR65/68 1DFh 480 1
XR51[1-0]
XR50[6-4]
XR51[3]
XR4F[2-0]
XR50[7]
XR53[5-4]
XR6F[1]
XR51[5]
XR2F[6]
XR2F/2D
XR2F/2E
XR2F[3-0]
XR54[6]
XR4F[7]
XR51[7]
XR2F[7]
XR2C
XR54[7]
XR54[0]
XR54[1]
XR51[2]
Alt
Alt
Alt
Alt
Alt
Alt
Alt
Alt
XR19
XR1A
XR1B
XR65/64
XR65/66
XR67[3-0]
XR55[6]
XR55[7]
VDDSAFE (+5V)
+12VSAFE
Parameter
Panel Width
Panel Height
Panel Type
Clock Divide (CD)
Shiftclk Div (SD)
Gray/Color Levels
TFT Data Width
STN Pixel Packing
Frame Accel Ena
n/c
+27V
VSS
5
4
H AutoDoubling
VDD
DISPOFF# V Text Stretching
VEE
XR57[7]
XR55[1]
XR57[1]
XR56
XR59/58
H Text Compression
V
V
V
V
V
V
XR55[2]
XR55[5]
XR57[2]
Text Stretch Mode
XR57[4-3]
Stretching
XR57[5]
Stretching Mode
XR57[6]
Line Insertion Height XR59[3-0]
H/W Line Replication XR59[7]
Line Repl Height
XR5A[3-0]
Revision 1.2
235
65540 / 545
Programming Recommendations/Requirements
ENABKL
Reserved
BLANK#/DE
M (ACDCLK)
GND
n/c
n/c
n/c
n/c
SHFCLK
GND
LP
(HS)
GND
FLM
(VS)
GND
Sharp LM64C08P
Panel
Connector
CN1-3 XCK
CN1-2
LP
CN1-1
YD
J3-49
J3-48
J3-46
J3-45
J3-43
J3-42
J3-40
J3-39
PNL23
PNL22
PNL21
PNL20
PNL19
PNL18
PNL17
PNL16
J3-37
J3-36
J3-34
J3-33
J3-31
J3-30
J3-28
J3-27
PNL15
PNL14
PNL13
PNL12
PNL11
PNL10
PNL9
PNL8
(LG3...)
(LR3...)
(LB2...)
(LG2...)
(UG3...)
(UR3...)
(UB2...)
(UG2...)
CN2-17
CN2-18
CN2-19
CN2-20
CN1-8
CN1-9
CN1-10
CN1-11
LD0
LD1
LD2
LD3
UD0
UD1
UD2
UD3
J3-25
J3-24
J3-22
J3-21
J3-19
J3-18
J3-16
J3-15
PNL7
PNL6
PNL5
PNL4
PNL3
PNL2
PNL1
PNL0
(LR2...)
(LB1...)
(LG1...)
(LR1...)
(UR2...)
(UB1...)
(UG1...)
(UR1...)
CN2-21
CN2-22
CN2-23
CN2-24
CN1-12
CN1-13
CN1-14
CN1-15
DL4
DL5
DL6
DL7
DU4
DU5
DU6
DU7
J3-17
J3-20
J3-23
J3-26
J3-29
J3-32
J3-35
J3-38
J3-41
J3-44
J3-47
J3-50
J3-1
J3-2
J3-3
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Register
Value Comment
XR1C
4Fh (640 / 8) 1
XR65/68 1DFh 480 1
XR51[1-0]
XR50[6-4]
XR51[3]
XR4F[2-0]
XR50[7]
XR53[5-4]
XR6F[1]
XR51[5]
XR2F[6]
XR2F/2D
XR2F/2E
XR2F[3-0]
XR54[6]
XR4F[7]
XR51[7]
XR2F[7]
XR2C
XR54[7]
XR54[0]
XR54[1]
XR51[2]
Alt
Alt
Alt
Alt
Alt
Alt
Alt
Alt
XR19
XR1A
XR1B
XR65/64
XR65/66
XR67[3-0]
XR55[6]
XR55[7]
VDDSAFE (+5V)
+12VSAFE
Parameter
Panel Width
Panel Height
Panel Type
Clock Divide (CD)
Shiftclk Div (SD)
Gray/Color Levels
TFT Data Width
STN Pixel Packing
Frame Accel Ena
n/c
+25V
CN1-6
CN2-1
CN2-10
CN2-16
CN2-25
VSS
VSS
VSS
VSS
VSS
CN1-5
CN1-4
VDD
DISP
CN1-7
VEE
XR57[7]
XR55[1]
XR57[1]
XR56
XR59/58
Text Compression
XR55[2]
AutoDoubling
XR55[5]
Text Stretching
XR57[2]
Text Stretch Mode
XR57[4-3]
Stretching
XR57[5]
Stretching Mode
XR57[6]
Line Insertion Height XR59[3-0]
H/W Line Replication XR59[7]
Line Repl Height
XR5A[3-0]
Revision 1.2
236
65540 / 545
Programming Recommendations/Requirements
ENABKL
Reserved
BLANK#/DE
M (ACDCLK)
GND
n/c
n/c
n/c
SHFCLK
GND
LP
(HS)
GND
FLM
(VS)
GND
Sanyo LCM-5331-22NTK
Panel
Single
Dual
Connector
Connector
(Panel Spec) (Prototypes)
29
CN1-2 M
25
26
27
24
30
CN1-6
CN1-7
CN1-4
CN1-5
CN1-1
J3-49
J3-48
J3-46
J3-45
J3-43
J3-42
J3-40
J3-39
J3-37
J3-36
J3-34
J3-33
J3-31
J3-30
J3-28
J3-27
PNL15
PNL14
PNL13
PNL12
PNL11
PNL10
PNL9
PNL8
15
14
13
12
23
22
21
20
CN2-16
CN2-17
CN2-18
CN2-19
CN1-8
CN1-9
CN1-10
CN1-11
LD0
LD1
LD2
LD3
UD0
UD1
UD2
UD3
J3-25
J3-24
J3-22
J3-21
J3-19
J3-18
J3-16
J3-15
PNL7
PNL6
PNL5
PNL4
PNL3
PNL2
PNL1
PNL0
11
10
9
8
19
18
17
16
CN2-20
CN2-21
CN2-22
CN2-23
CN1-12
CN1-13
CN1-14
CN1-15
LD4
LD5
LD6
LD7
UD4
UD5
UD6
UD7
J3-1
J3-3
J3-2
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
+12VSAFE
XR2F/2D
XR2F/2E
XR2F[3-0]
XR54[6]
XR4F[7]
XR51[7]
XR2F[7]
XR2C
XR54[7]
XR54[0]
XR54[1]
XR51[2]
Alt
Alt
Alt
Alt
Alt
Alt
Alt
Alt
XR19
XR1A
XR1B
XR65/64
XR65/66
XR67[3-0]
XR55[6]
XR55[7]
n/c
VDDSAFE (+5V)
VEESAFE
(12 to 45)
Register
Value Comment
XR1C
4Fh (640 / 8) 1
XR65/68 1DFh 480 1
XR51[1-0]
XR50[6-4]
XR51[3]
XR4F[2-0]
XR50[7]
XR53[5-4]
XR6F[1]
CL2
VSS
CL1 Output Signal Timing
VSS Shift Clock Mask (SM) XR51[5]
XR2F[6]
FLM LP Delay Disable
PNL23
PNL22
PNL21
PNL20
PNL19
PNL18
PNL17
PNL16
J3-17
J3-20
J3-23
J3-26
J3-29
J3-32
J3-35
J3-38
J3-41
J3-44
J3-47
J3-50
Parameter
Panel Width
Panel Height
Panel Type
Clock Divide (CD)
Shiftclk Div (SD)
Gray/Color Levels
TFT Data Width
STN Pixel Packing
Frame Accel Ena
+30V
NC
28
DISPOFF#
6
5
CN2-26
CN2-25
CN2-24
VDD H AutoDoubling
3
4
CN2-27
CN2-28
VEE V
VEE V
CN2-29
VO
VSS
XR57[7]
XR55[1]
XR57[1]
XR56
XR59/58
H Text Compression
V
V
V
V
V
XR55[2]
XR55[5]
Text Stretching
XR57[2]
Text Stretch Mode
XR57[4-3]
Stretching
XR57[5]
Stretching Mode
XR57[6]
Line Insertion Height XR59[3-0]
H/W Line Replication XR59[7]
Line Repl Height
XR5A[3-0]
Revision 1.2
237
65540 / 545
Programming Recommendations/Requirements
ENABKL
Reserved
BLANK#/DE
M (ACDCLK)
GND
n/c
n/c
n/c
n/c
SHFCLK
GND
LP
(HS)
GND
FLM
(VS)
GND
PNL23
PNL22
PNL21
PNL20
PNL19
PNL18
PNL17
PNL16
PNL7
PNL6
PNL5
PNL4
PNL3
PNL2
PNL1
PNL0
J3-17
J3-20
J3-23
J3-26
J3-29
J3-32
J3-35
J3-38
J3-41
J3-44
J3-47
J3-50
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
CN1-2
CL1
CN1-1
FLM
CN2-6
CN2-7
CN2-8
CN2-9
CN2-1
CN2-2
CN2-3
CN2-4
LD4
LD5
LD6
LD7
UD4
UD5
UD6
UD7
CN1-12
CN1-13
CN1-14
CN1-15
CN1-8
CN1-9
CN1-10
CN1-11
LD0
LD1
LD2
LD3
UD0
UD1
UD2
UD3
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
PNL15
PNL14
PNL13
PNL12
PNL11
PNL10
PNL9
PNL8
J3-25
J3-24
J3-22
J3-21
J3-19
J3-18
J3-16
J3-15
Hitachi LMG9721XUFC
Panel
Connector
CN1-3
CL2
Parameter
Panel Width
Panel Height
Panel Type
Clock Divide (CD)
Shiftclk Div (SD)
Gray/Color Levels
TFT Data Width
STN Pixel Packing
Frame Accel Ena
Register
Value Comment
XR1C
4Fh (640 / 8) 1
XR65/68 1DFh 480 1
XR51[1-0]
XR50[6-4]
XR51[3]
XR4F[2-0]
XR50[7]
XR53[5-4]
XR6F[1]
XR51[5]
XR2F[6]
XR2F/2D
XR2F/2E
XR2F[3-0]
XR54[6]
XR4F[7]
XR51[7]
XR2F[7]
XR2C
XR54[7]
XR54[0]
XR54[1]
XR51[2]
Alt
Alt
Alt
Alt
Alt
Alt
Alt
Alt
XR19
XR1A
XR1B
XR65/64
XR65/66
XR67[3-0]
XR55[6]
XR55[7]
CN2-10
CN2-5
CN1-6
VSS
VSS
VSS
H
H
J3-1
CN1-5
VDD
V
DISPOFF# V
CN1-4
+12VSAFE
n/c
J3-2
V
V
VEESAFE
(12
to
45)
+V
J3-3
CN1-7
VEE
V
Voltage not specified in panel data sheet; contact panel manufacturer V
V
VDDSAFE (+5V)
XR57[7]
XR55[1]
XR57[1]
XR56
XR59/58
Text Compression
XR55[2]
AutoDoubling
XR55[5]
Text Stretching
XR57[2]
Text Stretch Mode
XR57[4-3]
Stretching
XR57[5]
Stretching Mode
XR57[6]
Line Insertion Height XR59[3-0]
H/W Line Replication XR59[7]
Line Repl Height
XR5A[3-0]
Revision 1.2
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Programming Recommendations/Requirements
ENABKL
Reserved
BLANK#/DE
M (ACDCLK)
GND
n/c
n/c
n/c
n/c
SHFCLK
GND
LP
(HS)
GND
FLM
(VS)
GND
Toshiba TLX-8062S-C3X
Panel
Connector
CN1-3
SCP
CN1-2
LP
CN1-1
FP
J3-49
J3-48
J3-46
J3-45
J3-43
J3-42
J3-40
J3-39
PNL23
PNL22
PNL21
PNL20
PNL19
PNL18
PNL17
PNL16
J3-37
J3-36
J3-34
J3-33
J3-31
J3-30
J3-28
J3-27
PNL15
PNL14
PNL13
PNL12
PNL11
PNL10
PNL9
PNL8
CN2-2
CN2-3
CN2-4
CN2-5
CN1-8
CN1-9
CN1-10
CN1-11
LD0
LD1
LD2
LD3
UD0
UD1
UD2
UD3
J3-25
J3-24
J3-22
J3-21
J3-19
J3-18
J3-16
J3-15
PNL7
PNL6
PNL5
PNL4
PNL3
PNL2
PNL1
PNL0
CN2-6
CN2-7
CN2-8
CN2-9
CN1-12
CN1-13
CN1-14
CN1-15
LD4
LD5
LD6
LD7
UD4
UD5
UD6
UD7
J3-17
J3-20
J3-23
J3-26
J3-29
J3-32
J3-35
J3-38
J3-41
J3-44
J3-47
J3-50
J3-1
J3-2
J3-3
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Register
Value Comment
XR1C
4Fh (640 / 8) 1
XR65/68 1DFh 480 1
XR51[1-0]
XR50[6-4]
XR51[3]
XR4F[2-0]
XR50[7]
XR53[5-4]
XR6F[1]
XR51[5]
XR2F[6]
XR2F/2D
XR2F/2E
XR2F[3-0]
XR54[6]
XR4F[7]
XR51[7]
XR2F[7]
XR2C
XR54[7]
XR54[0]
XR54[1]
XR51[2]
Alt
Alt
Alt
Alt
Alt
Alt
Alt
Alt
XR19
XR1A
XR1B
XR65/64
XR65/66
XR67[3-0]
XR55[6]
XR55[7]
VDDSAFE (+5V)
+12VSAFE
Parameter
Panel Width
Panel Height
Panel Type
Clock Divide (CD)
Shiftclk Div (SD)
Gray/Color Levels
TFT Data Width
STN Pixel Packing
Frame Accel Ena
n/c
CN2-10
CN2-1
CN1-6
GND
GND
GND
CN1-5
CN1-4
VDD
DISP
CN1-7
VEE
XR57[7]
XR55[1]
XR57[1]
XR56
XR59/58
Text Compression
XR55[2]
AutoDoubling
XR55[5]
Text Stretching
XR57[2]
Text Stretch Mode
XR57[4-3]
Stretching
XR57[5]
Stretching Mode
XR57[6]
Line Insertion Height XR59[3-0]
H/W Line Replication XR59[7]
Line Repl Height
XR5A[3-0]
Revision 1.2
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Programming Recommendations/Requirements
ENABKL
Reserved
BLANK#/DE
M (ACDCLK)
GND
n/c
n/c
n/c
n/c
SHFCLK
GND
LP
(HS)
GND
FLM
(VS)
GND
Optrex DMF-50351NC-FW
Panel
Connector
CN1-3
CP
CN1-2
LP
CN1-1
FLM
J3-49
J3-48
J3-46
J3-45
J3-43
J3-42
J3-40
J3-39
PNL23
PNL22
PNL21
PNL20
PNL19
PNL18
PNL17
PNL16
J3-37
J3-36
J3-34
J3-33
J3-31
J3-30
J3-28
J3-27
PNL15
PNL14
PNL13
PNL12
PNL11
PNL10
PNL9
PNL8
CN2-2
CN2-3
CN2-4
CN2-5
CN1-8
CN1-9
CN1-10
CN1-11
DL0
DL1
DL2
DL3
DU0
DU1
DU2
DU3
J3-25
J3-24
J3-22
J3-21
J3-19
J3-18
J3-16
J3-15
PNL7
PNL6
PNL5
PNL4
PNL3
PNL2
PNL1
PNL0
CN2-6
CN2-7
CN2-8
CN2-9
CN1-12
CN1-13
CN1-14
CN1-15
DL4
DL5
DL6
DL7
DU4
DU5
DU6
DU7
J3-17
J3-20
J3-23
J3-26
J3-29
J3-32
J3-35
J3-38
J3-41
J3-44
J3-47
J3-50
J3-1
J3-2
J3-3
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Register
Value Comment
XR1C
4Fh (640 / 8) 1
XR65/68 1DFh 480 1
XR51[1-0]
XR50[6-4]
XR51[3]
XR4F[2-0]
XR50[7]
XR53[5-4]
XR6F[1]
XR51[5]
XR2F[6]
XR2F/2D
XR2F/2E
XR2F[3-0]
XR54[6]
XR4F[7]
XR51[7]
XR2F[7]
XR2C
XR54[7]
XR54[0]
XR54[1]
XR51[2]
Alt
Alt
Alt
Alt
Alt
Alt
Alt
Alt
XR19
XR1A
XR1B
XR65/64
XR65/66
XR67[3-0]
XR55[6]
XR55[7]
VDDSAFE (+5V)
+12VSAFE
Parameter
Panel Width
Panel Height
Panel Type
Clock Divide (CD)
Shiftclk Div (SD)
Gray/Color Levels
TFT Data Width
STN Pixel Packing
Frame Accel Ena
n/c
+V
CN2-10
CN2-1
CN1-6
VSS
VSS
VSS
CN1-5
CN1-4
H AutoDoubling
VCC
DISPOFF# V Text Stretching
CN1-7
VEE
XR57[7]
XR55[1]
XR57[1]
XR56
XR59/58
H Text Compression
V
V
V
V
V
V
XR55[2]
XR55[5]
XR57[2]
Text Stretch Mode
XR57[4-3]
Stretching
XR57[5]
Stretching Mode
XR57[6]
Line Insertion Height XR59[3-0]
H/W Line Replication XR59[7]
Line Repl Height
XR5A[3-0]
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Electrical Specifications
Electrical Specifications
65540 / 545 ABSOLUTE MAXIMUM CONDITIONS
Symbol
PD
VCC
VI
VO
TOP
TSTG
Parameter
Power Dissipation
Supply Voltage
Input Voltage
OutputVoltage
OperatingTemperature(Ambient)
StorageTemperature
Min
0.5
0.5
0.5
25
40
Typ
Max
1
7.0
VCC+0.5
VCC+0.5
85
125
Units
W
V
V
V
C
C
Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded.
Functional operation should be restricted to the conditions described under Normal Operating Conditions.
Parameter
Supply Voltage (5V 10%)
Supply Voltage (3.3V 10%)
Ambient Temperature
Min
4.5
3.1
0
Typ
5
3.3
Max
5.5
3.6
70
Units
V
V
C
Notes
IO 10 mA
VO 1V @ 37.5 Load
10% to 90%
Min
1.5
21
Typ
1.27
50
Max
28
6
200
Units
V
mA
%
%
LSB
nS
nS
pVsec
mV
Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz.
Electrical specifications contained herein are preliminary and subject to change without notice.
Revision 1.2
11/11/93
241
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Electrical Specifications
65540 / 545 DC CHARACTERISTICS
(Under Normal Operating Conditions Unless Noted Otherwise)
Symbol Parameter
Notes
Min
Typ
Max
Units
ICCDE Power Supply Current 0C, 5.5V, 68 MHz, DAC on, 65540
180
230
mA
ICCDO Power Supply Current 0C, 5.5V, 68 MHz, DAC off, 65540
140
200
mA
ICCDO Power Supply Current 0C, 3.3V, 62 MHz, DAC off, 65540
78
132
mA
ICCDE Power Supply Current 0C, 5.5V, 68 MHz, DAC on, 65545
TBD
TBD
mA
ICCDO Power Supply Current 0C, 5.5V, 68 MHz, DAC off, 65545
TBD
TBD
mA
ICCDO Power Supply Current 0C, 3.3V, 56 MHz, DAC off, 65545
TBD
TBD
mA
ICCS Power Supply Current 0C, 5.5V, Standby, 65540
200
A
ICCS Power Supply Current 0C, 5.5V, Standby, 65545
TBD
A
IIL
Input Leakage Current
100
+100
uA
IOZ
Output Leakage Current High Impedance
100
+100
uA
IOZ
Output Leakage Current High Impedance
100
+100
uA
VIL
Input Low Voltage
All input pins
0.5
0.8
V
VOL Output Low Voltage
Under max load per table below (5V)
0.5
V
VOL Output Low Voltage
Under max load per table below (3.3V)
0.5
V
VOH Output High Voltage
Under max load per table below (5V)
VCC 0.5
V
VOH Output High Voltage
Under max load per table below (3.3V)
2.4
V
VIH
Input High Voltage
All pins except XTALI
2.0
VCC+0.5
V
VIH
Input High Voltage
All pins except XTALI
2.0
VCC+0.5
V
65540 / 545 DC DRIVE CHARACTERISTICS
Symbol Parameter
OutputPins
IOL
Output Low Drive H/VSYNC, LDEV#, LRDY#, ROMCS#, IRQ
FLM, LP, M, P0-15, SHFCLK, D0-31
ENAVEE, ENAVDD, ENABKL, ACTI
RASA#, CASAH/L#, WEA#, PAR (65545 only)
RASB#, CASBH/L#, WEB#, OEAB#, AA0-9
RASC#, CASCH/L#, WEC#, OEC#, CA0-9
All other outputs
IOH
Output High Drive H/VSYNC, LDEV#, LRDY#, ROMCS#, IRQ
FLM, LP, M, P0-15, SHFCLK, D0-31
ENAVEE, ENAVDD, ENABKL, ACTI
RASA#, CASAH/L#, WEA#, PAR (65545 only)
RASB#, CASBH/L#, WEB#, OEAB#, AA0-9
RASC#, CASCH/L#, WEC#, OEC#, CA0-9
All other outputs
DCTestConditions
VOUT=VOL, VCC=4.5V
VOUT=VOL, VCC=4.5V
VOUT=VOL, VCC=4.5V
VOUT=VOL, VCC=4.5V
VOUT=VOL, VCC=4.5V
VOUT=VOL, VCC=4.5V
VOUT=VOL, VCC=4.5V
VOUT=VOH, VCC=4.5V
VOUT=VOL, VCC=4.5V
VOUT=VOH, VCC=4.5V
VOUT=VOH, VCC=4.5V
VOUT=VOH, VCC=4.5V
VOUT=VOH, VCC=4.5V
VOUT=VOH, VCC=4.5V
Min Units
12 mA
8 mA
8 mA
4 mA
4 mA
4 mA
2 mA
12 mA
8 mA
8 mA
4 mA
4 mA
4 mA
2 mA
Note: IOL and IOH drive listed above indicates 5V low drive and 3.3V high drive (see also XR6C)
Note: Standby power was measured using Self Refresh DRAMs with all chip inputs driven to inactive levels and outputs not
connected (or connected to typical external loads).
Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz.
Electrical specifications contained herein are preliminary and subject to change without notice.
Revision 1.2
242
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Electrical Specifications
Output
Output
Capacitive
LowVoltage HighVoltage
Load
VOL
2.4V
80pF
VOL
2.4V
50pF
VOL
2.4V
30pF
OutputPins
All 12mA and 8mA outputs plus PAR for PCI bus in the 65545
All Other 4mA output pads
All Other 2mA output pads
Parameter
Reference Frequency
Reference Clock Period
Reference Clock Duty Cycle
Notes
(100 ppm)
1/FREF
Min
Typ
Max Units
1
14.31818 60 MHz
16.6 69.84128 1000 nS
25
75
%
TREF
THI
Reference Clock Input
Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz.
Electrical specifications contained herein are preliminary and subject to change without notice.
Revision 1.2
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Electrical Specifications
65540 / 545 AC TIMING CHARACTERISTICS - CLOCK GENERATOR
Symbol Parameter
TC VCLK Period (5V)
TC VCLK Period (3.3V)
TCH VCLK High Time
TCL VCLK Low Time
TM MCLK Period (5V)
TM MCLK Period (3.3V)
TMH MCLK High Time
TML MCLK Low Time
TRF Clock Rise / Fall
Notes
68 MHz
56 MHz
Min
14.7
17.6
0.45T C
0.45T C
14.7
17.6
0.45T M
0.45T M
68 MHz
56 MHz
Typ
50.350
56.644
65
Max
0.55T C
0.55T C
0.55T M
0.55T M
5
Units
nS
nS
nS
nS
nS
nS
nS
nS
nS
MHz
MHz
MHz
TC
TCH
TCL
VCLK
TM
TMH
TML
MCLK
Clock Timing
Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz.
Electrical specifications contained herein are preliminary and subject to change without notice.
Revision 1.2
244
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Electrical Specifications
Parameter
Reset Active Time from Power Stable
Reset Active Time from Ext. Osc. Stable
Reset Active Time with Power Stable
Reset Rise Time
Reset Active to Output Float Delay
Configuration Setup Time
Configuration Hold Time
Notes
See Note 1
See Note 2
See Note 3
Reset fall time is non-critical
Min
5
0
2
20
5
See Note 4
Max
20
40
Units
mS
nS
mS
nS
nS
nS
nS
Note 1: This parameter includes time for internal voltage stabilization of all sections of the chip, startup and stabilization of the
internal clock synthesizer, and setting of all internal logic to a known state.
Note 2: The external oscillator input is optional, it may be selected by XR01 bit 5.
Note 3: This parameter includes time for the internal clock synthesizer to reset to its default frequency and time to set all internal logic
to a known state. It assumes power is stable and the internal clock synthesizer is already operating at some stable frequency.
Note 4: Setup time to latch the state of the configuration bits reliably into XR01 and XR6C is specified by this parameter. Changes
in some configuration bits may take longer to stabilize inside the chip (such as internal clock synthesizer-related bits 4 and 5).
It is therefore recommended that configuration bit setup time be TRES (2mS) to insure that the chip is in a completely stable
state when Reset goes inactive.
ResetwithChipOperating
andPowerStable
InitialPower-UpReset
VCC
TIPR
TORS
Valid
14.318 MHz
(from external oscillator)
TRES
RESET#
TRSR
TCSU
TRSR
TCHD
TCSU TCHD
Configuration Lines
AA0-AA8
Bus Output Pins
TRSO
Reset Timing
Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz.
Electrical specifications contained herein are preliminary and subject to change without notice.
Revision 1.2
245
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Electrical Specifications
Notes
0.1% stability at 2.0V / 0.8V
Min
30
12
12
1
2
5
Max
30
3
3
4
Units
nS
nS
nS
nS
nS
V / nS
nS
nS
TLCP
TLCH
CCLK / LCLK
TLCR
TLCL
TLCF
CCLK / LCLK
(2x Bus Clock
Configuration)
TCRH
TCRS
CRESET
65540/545 CRESET to CCLK timing should match CPU RESET to CLK2 timing of the CPU.
Revision 1.2
246
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Electrical Specifications
65540 / 65545 AC TIMING CHARACTERISTICS - LOCAL BUS INPUT SETUP & HOLD (33 MHz)
Symbol Parameter
TADS Setup Time - A2-31, BEn#, M/IO#, W/R#
TASS Setup Time - ADS#
TDWS Setup Time - D0-31 (Write)
TRRS Setup Time - RDYRTN#
TADH Hold Time - A2-31, BEn#, M/IO#, W/R#
TASH Hold Time - ADS#
TDWH Hold Time - D0-31 (Write)
TRRH Hold Time - RDYRTN#
Notes
Min
7
7
7
5
2
2
2
2
Max Units
nS
nS
nS
nS
nS
nS
nS
nS
CCLK / LCLK
TDWS
TDWH
TRRS
TRRH
TASS
TASH
TADS
TADH
D31-0 (Write)
RDYRTN#
ADS#
BEn#, A31-2
M/IO#, W/R#
Local Bus Input Setup & Hold Timing
Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz.
Electrical specifications contained herein are preliminary and subject to change without notice.
Revision 1.2
247
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Electrical Specifications
Notes
CLMax Min
125pF
3
100pF
3
Max Units
18
nS
14
nS
CCLK / LCLK
TDAV min
D31-0 (Read)
ValidN
Valid N+1
TRDV min
LRDY#
max
max
ValidN
Valid N+1
Max Units
20
nS
30
nS
CCLK / LCLK
TDAF
D31-0 (Read)
ValidN
TRDF
LRDY#
Local Bus Output Float Delay Timing
Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz.
Electrical specifications contained herein are preliminary and subject to change without notice.
Revision 1.2
248
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Electrical Specifications
Notes
Address
Min
3
Typ
Max
20
Units
nS
Valid
TLDV
TLDV
LDEV#
Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz.
Electrical specifications contained herein are preliminary and subject to change without notice.
Revision 1.2
249
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Electrical Specifications
Notes
Read Cycles
Write Cycles
Min
7
7
2
7
2
7
2
7
2
1
7
2
Max
11
11
11
11
1
11
11
1
Units
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
CLK
nS
nS
CLK
nS
nS
Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz.
Electrical specifications contained herein are preliminary and subject to change without notice.
Revision 1.2
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Electrical Specifications
CLK
TFRS
FRAME#
Hi-Z
Bus Hi-Z
Turnaround
TCMS TCMH
C/BE#[3:0]
Hi-Z
Command
TBES
Byte Enables
TADS TADH
Read AD[31:0] Hi-Z
Address
TADS TADH
WriteAD[31:0] Hi-Z
Address
Hi-Z
Bus
Hi-Z
Bus Hi-Z
Read
Turnaround
WriteData
TTZH
TRDY#
TBEH
Bus Hi-Z
WriteData Turnaround
TTHL
TTLH TTHZ
Bus
Turnaround
Hi-Z
TISC TIHC
IRDY#
Hi-Z
Bus
Turnaround
Hi-Z
TDZL
DEVSEL# Hi-Z
Bus
Turnaround
TDLH TDHZ
Hi-Z
Note: The above diagram shows a typical PCI bus cycle. PCI bus read cycles require a bus turn-around cycle between address output
and data input on AD31:0. PCI bus write cycles do not require this bus turnaround cycle so the write data is available from the
bus master immediately after address output (in clock cycle 2 instead of clock cycle 3).
Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz.
Electrical specifications contained herein are preliminary and subject to change without notice.
Revision 1.2
251
65540 / 545
Electrical Specifications
Notes
Min
Max
11
11
11
1
Units
nS
nS
nS
CLK
CLK
TSZH
STOP#
TSHL
TSLH
TSHZ
High Z
Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz.
Electrical specifications contained herein are preliminary and subject to change without notice.
Revision 1.2
252
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Electrical Specifications
Min
6Tm
0
3Tm
29
30
25
0
20
10
10
nS
nS
nS
nS
nS
2Tm
nS
nS
100Tm nS
nS
nS
30
nS
20
nS
nS
40
nS
55
nS
RFSH#, AEN,
A0-19, BHE#
TALE
ALE
TASC
Command Strobe
IORD#, IOWR#
MEMR#,MEMW#
RDY
TAHC
TRLC
TCPW
TRPW
TNXT
TCHR
TICS
IOCS16#, MCS16#
TRSR
TRDZ
TRDH
Data (Read)
TWDD
TWDH
Data(Write)
ISA Bus Timing
Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz.
Electrical specifications contained herein are preliminary and subject to change without notice.
Revision 1.2
253
65540 / 545
Electrical Specifications
Min
12Tm 5
8Tm 5
4Tm 3
4Tm 5
5Tm 2
3Tm 5
2Tm 5
Tm 5
2Tm 5
Tm 5
2Tm 8
Tm 2
Tm 2
Tm 5
Tm 2
3Tm 1
1Tm 5
2Tm 5
Max
2Tm 5
3Tm 5
5Tm 2
6Tm 2
Units
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz.
Electrical specifications contained herein are preliminary and subject to change without notice.
Revision 1.2
254
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Electrical Specifications
TRC
TRAS
TRP
RAS#
TCRP
TRCD
TPC
TCAS
TRSH
TCP
TCAS
CAS#
TCSH
TCAH
TASR TRAH
Address
Row
TCAH
TASC
Column
TASR
Column
Row
TASC
WE#
Data
TCAC
TCAC
TRAC
High Z
Read
High Z
High Z
Read
TRC
TRAS
TRP
RAS#
TCRP
TRCD
TRSH
TPC
TCAS
TCAS
CAS#
TASR TRAH TASC
Address
Row
TCSH
TCAH
TCP
TASC
Column
TCAH
Column
TWS
TASR
Row
TWH
WE#
TDS
Data
TDH
TDS
Write Data
TDH
Write Data
Note: The above diagrams represent typical page mode cycles. The number of actual CAS cycles may vary.
Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz.
Electrical specifications contained herein are preliminary and subject to change without notice.
Revision 1.2
255
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Electrical Specifications
Notes
Min
16Tm 5
6Tm 5
6Tm 8
7Tm 5
5Tm 5
Tm + 3
Max
Tm
2Tm 5
3Tm 5
Units
nS
nS
nS
nS
nS
nS
nS
nS
nS
TRRMW
RAS#
TCRP
TRCD
TCP
TCRMW
TCRMW
CAS#
TASR TRAH TASC TCAH
Address
Row
TRWD
TASC TCAH
Column
TAWD
Column
Row
TCPWD
WE#
TCAC
TCAC
OE#
TOER
TOEW
TOEZ
Data
Read
TOER
TOEW
TOEZ
TDS TDH
Write
Read
TDS TDH
Write
Note: The above diagrams represent typical page mode cycles. The number of actual CAS cycles may vary.
Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz.
Electrical specifications contained herein are preliminary and subject to change without notice.
Revision 1.2
256
65540 / 545
Electrical Specifications
Min
5Tm 5
Tm 5
2Tm 5
5Tm 5
Typ
Max
Units
nS
nS
nS
nS
TRAS
RAS#
TCSR
TCHR
CAS#
CAS-Before-RAS ( CBR ) DRAM Refresh Cycle Timing
65540 / 65545 AC TIMING CHARACTERISTICS - SELF REFRESH
Symbol Parameter
Notes
TRASS RAS# Pulse Width for Self-Refresh
TRP RAS# Precharge
TRPS RAS# Precharge for Self-Refresh
TRPC RAS# to CAS# Delay
TCSR CAS# to RAS# Delay
Normal Operation
Standby Mode
TCHS CAS# Hold Time
TCPN CAS# Precharge
TRP
RAS#
TRPC
Min
100
4Tm 3
10Tm
3Tm 5
Tm 5
2Tm 5
0
Tm 5
TRASS
TCSR
Typ
Max
Units
S
nS
nS
nS
nS
nS
nS
nS
TRPS
TCHS
TCPN
CAS#
Dout
High Z
Address
'Self-Refresh DRAM' Refresh Cycle Timing
Note: Upon exiting self-refresh mode, the 65540 / 65545 will perform a complete set of CBR refresh cycles before resuming normal
DRAM activity. The duration of the burst refresh will equal the panel power sequencing delay, programmed in XR5B bits 7-4.
Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz.
Electrical specifications contained herein are preliminary and subject to change without notice.
Revision 1.2
257
65540 / 545
Electrical Specifications
Notes
Min
Max
50
80
30
50
Units
nS
nS
nS
nS
Min
12
0
Max
Units
nS
nS
VCLK in
TSYN
HSYNC, VSYNC out
TSD
SHFCLK out
Notes
PCLK
TPVS
TPVH
VideoData
HSYNC
VSYNC
PC Video Timing
Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz.
Electrical specifications contained herein are preliminary and subject to change without notice.
Revision 1.2
258
65540 / 545
Electrical Specifications
Notes
Min
5
10
10
Tc
Tc
8 Tc
8 Tc
Max
Units
nS
nS
nS
nS
nS
nS
nS
LP
TS2L
TL2S
SHFCLK
TDSU
TDLY
TDH
Data
TFSU
TFSH
FLM
Last
Line
Data
Transfer
FLM
Panel Output Timing
Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz.
Electrical specifications contained herein are preliminary and subject to change without notice.
Revision 1.2
259
65540 / 545
Electrical Specifications
Revision 1.2
260
65540 / 545
Mechanical Specifications
Mechanical Specifications
Lead Length
0.5 0.2
(0.020 0.008)
Lead Pitch
0.50 (0.0197)
F6554x
R
XXXXXXX
YYWW CCCCCC
LLLLLLL
Footprint
208-Pin
Plastic Flat Pack
Body Size
Lead Width
0.20 0.10
(0.008 0.004)
DIMENSIONS:
mm (in)
Clearance
0.25 (0.010)
Minimum
Pin 1
Revision 1.2
Body Size
Footprint
261
Seating Plane
Height
4.07 (0.160)
Maximum
65540 / 545