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QSN) Let T1 be the time taken for a single instruction on a pipelined CPU and T2 be

the time take for a single instruction on a non-pipelined but identical CPU.
Comparing T1 and T2 we can say that

(A) T1=T2 + the time taken for one instruction fetch cycle
(B) T1<t2
(C) T1T2
(D) T1T2

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