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EEE342/ETE418_L10

Control Engineering
Dr. Abdur Razzak

Lecture 10

Discrete
Control
Systems

Objectives

To learn & study


the modeling & designing of
discrete control systems

EEE342/ETE418_L10

Discrete control system - example


Dr. Abdur Razzak

Fig: Digital antenna azimuth position control system

EEE342/ETE418_L10

Discrete control system block diagram


Dr. Abdur Razzak

Fig: (a) placement of the digital computer within the loop; (b) detailed block
diagram showing placement of A/D and D/A converters

EEE342/ETE418_L10

Advantages & Disadvantages


Dr. Abdur Razzak

Advantages
Improved sensitivity - high sensitivity can pick up low energy signals
better
Use digital components - less sensitive to noise
Flexibility in response to design changes - can easily change
parameters in algorithms to modify / adjust behavior
Many systems inherently digital - radar, satellite systems, etc. send info
in pulses
Reduced cost - in industry, a single digital computer can replace
numerous analog controllers thereby reducing the cost

Disadvantages

Develop complex math algorithms - time consuming and difficult to get


algorithm right
Lose information during conversions - quantization error, loss of
information between samples

EEE342/ETE418_L10

Continuous vs discrete controller


Dr. Abdur Razzak

EEE342/ETE418_L10

Digital to analog converter


Dr. Abdur Razzak

Digital-to-analog conversion is simple and effectively


instantaneous. Properly weighted voltages are summed together
to yield the analog output.
For example, in figure, three weighted voltages are summed. The
three-bit binary code is represented by the switches.
Thus, if the binary
number is 1102, the
bottom and center
switches are on, and
the analog output is
6 volts. In actual
use, the switches
are electronic and
are set by the input
binary code.

EEE342/ETE418_L10

Analog to digital conversion


Dr. Abdur Razzak

Analog-to-digital (A/D) conversion is a two-step process and is not


instantaneous (there is a delay between the analog input and digital
output: the analog signal is first converted to a sampled signal and then
converted to a sequence of binary numbers, the digital signal.
The sampling rate (Nyquist sampling rate) must be at least twice the
bandwidth of the signal, otherwise there will be distortion.
Analog signal sampled at periodic intervals and held over the sampling
interval by a device called a zero-order sample-and-hold (z.o.h.) that
yields a staircase approximation to the analog signal.
After sampling and holding, the dynamic range of the analog signal's
voltage is divided into discrete levels, and each level is assigned a
digital number.
The difference between levels is M/2n volts, where n is the number of
binary bits used for the analog-to-digital conversion.

EEE342/ETE418_L10

Analog to digital conversion (contd.)


Dr. Abdur Razzak

Fig: Steps in analog to digital


conversion: a. analog signal; b.
analog signal after sample-and-hold;
c. conversion of samples to digital
numbers

EEE342/ETE418_L10

Modeling the discrete controller


Dr. Abdur Razzak

If we are to analyze and design feedback control systems with


digital computers, we must be able to model the digital computer
and associated digital-to-analog and analog-to-digital converters.
Our goal is to represent the computer as a transfer function
similar to that for any subsystem.
In order to model digital control systems, we must come up with
a mathematical representation of sample-and-hold process.
1. Modeling the sampler
2. Modeling the zero-order hold

Represent D/A converter by zero-order hold equivalent


Samples input level and holds for sampling period T
Zero-order hold circuit represented by continuous system transfer
function in s-domain

EEE342/ETE418_L10

Modeling the sampler


Dr. Abdur Razzak

Model 1:
A switch turning on and off
at a uniform sampling rate

Model 2:
A product of the
time waveform to
be sampled, f(t)
and a sampling
function, s(t)

EEE342/ETE418_L10

Modeling the sampler (contd..)


Dr. Abdur Razzak

EEE342/ETE418_L10

Modeling the sampler (contd..)


Dr. Abdur Razzak

Thus, the sampler is divided into two parts: (1) an ideal sampler described by
the portion of above equation (the sum) that is not dependent upon the
sampling waveform characteristics, and (2) the portion dependent upon the
sampling waveform's characteristics, TW.

EEE342/ETE418_L10

Modeling the zero order hold


Dr. Abdur Razzak

Following figure summerizes the zero-order-hold which is to


hold the last sampled value of f(t).
If we assume an ideal sampler (TW = 1), then f*(t) is represented
by a sequence of delta functions.

EEE342/ETE418_L10

Modeling the zero order hold (contd..)


Dr. Abdur Razzak

The zero-order hold yields a staircase approximation to f(t).


Hence, the output from the hold is a sequence of step functions
whose amplitude is f(t) at the sampling instant, or f(kT).
The Laplace transform of a unit impulse or delta function input is
unity. Since a single impulse from the sampler yields a step over
the sampling interval, the Laplace transform of this step, Gh(s),
which is the impulse response of the zero-order hold, is the
transfer function of the zero-order hold.
Using an impulse at zero time, the transform of the resulting step
that starts at t = 0 and ends at t = T is

1 e Ts
Gh (s ) =
s

EEE342/ETE418_L10

Modeling the zero order hold (contd..)


Dr. Abdur Razzak

1 e Ts
Gh (s ) =
s

EEE342/ETE418_L10

The z-transform
Dr. Abdur Razzak

We have

f * (t ) =

f (kT ) (t kT )

k =

Taking the Laplace

F * (s ) = f (kT )e kTs
k =0

Then, the z-transform

F ( z ) = f (kT )z k
*

k =0

Relationship b/w s-plane and z-plane

z=e

sT

EEE342/ETE418_L10

Example-1
Dr. Abdur Razzak

Find the z-transform of f (kT ) = u (kT )

F ( z ) = f (kT )z k
k =0

= z k
k =0

( )

= z

1 k

k =0

1
1 z 1
z
=
z 1
=

Example-2

EEE342/ETE418_L10

Dr. Abdur Razzak

Find the z-transform of f (kT ) = kT

F ( z ) = f (kT )z
k =0

= kTz

k =0

= T z 1 + 2 z 2 + 3 z 3 +

= T kz k
k =0

zF ( z ) = T 1 + 2 z 1 + 3 z 2 +

(1)

(2)

Subtract (1) from (2)

zF ( z ) F ( z ) = T 1 + z 1 + z 2 +

=>

(z 1)F (z ) = T (1 + z

=>

Tz
Tz
=
F (z ) =
(z 1)(z 1) (z 1)2

+z

T
+ =
1 z 1

EEE342/ETE418_L10

Some common z-transform


Dr. Abdur Razzak

EEE342/ETE418_L10

Inverse z-transform
Dr. Abdur Razzak

Find the inverse z-transform of F (z ) =

0.5 z
(z 0.5)(z 0.7 )

0. 5
F (z )
=
(z 0.5)(z 0.7 )
z
2.5
2.5
=

(z 0.7 ) (z 0.5)
F (z ) =

2.5 z
2. 5 z

(z 0.7 ) (z 0.5)

f (kT ) = Z 1 [F ( z )] = 2.5(0.7 ) 2.5(0.5)


k

EEE342/ETE418_L10

Sampled data system


Dr. Abdur Razzak

Continuous

Sampled
input

Sampled
input & output

EEE342/ETE418_L10

Example-3
Dr. Abdur Razzak

Find the sampled data transfer function for the cascaded system. Given that T=0.5.

1 e Ts
Gh (s ) =
s

s+2
s +1

1 e Ts s + 2
s+2
Ts

= 1 e
G (s ) =
= G1 (s ) G2 (s )
s
s +1
s (s + 1)

z 1
G1 (z ) = 1 z =
z
1

1
2
kT
t
g 2 (t ) = L[G2 (s )] = L
=

e
2
(
)
=>
g
kT
=
2

e
2

s s + 1
2z
z
z
z
z ( z 0.213)

=
G2 ( z ) = Z [g 2 (kT )] =
T
0.5
(z 1)(z 0.6)
z 1 z e
z 1 z e

z 0.213
G ( z ) = G1 ( z )G2 ( z ) =
z 0.6

EEE342/ETE418_L10

Block diagram reduction


Dr. Abdur Razzak

EEE342/ETE418_L10

Example-4
Dr. Abdur Razzak

Find the z-transform of the system shown in Figure below.

Solution:

EEE342/ETE418_L10

Example-4 (contd..)
Dr. Abdur Razzak

EEE342/ETE418_L10

Stability
Dr. Abdur Razzak

In s-domain, system is stable if poles lie in left-hand plane.


In z-domain, system is stable if poles enclosed by unit circle.

Example-5

EEE342/ETE418_L10

Dr. Abdur Razzak

Determine the range of sampling interval, T, that will make the


system shown in figure stable.

Solution:

1 e Ts 10
G (s ) =

= 10 1 e Ts
s
s +1

z
z 1 z
z
z
z 1 z e T = 10 z z 1 z e T

( )
10(1 e )
=

G ( z ) = 10 1 z

z e T

1
1
s s + 1

EEE342/ETE418_L10

Example-5 (contd..)
Dr. Abdur Razzak

G(z )
10 1 e T
Closed loop transfer function: T ( z ) =
=
1 + G ( z ) z 11e T 10

Pole of the system:

11e T 10

For stability the poles of T(z) will be inside the unit circle.
For 11e T 10 = +1 , T = 0
T
For 11e 10 = 1 , T = 0.2

Therefore for stable system the range of sampling interval will be

0 < T < 0.2

EEE342/ETE418_L10

References
Dr. Abdur Razzak

1. Norman S Nise, Control System Engineering, John Wiley &


Sons, 5th Ed., pp. 692749.

EEE342/ETE418_L10

Next.

Good Luck
To
Final Exam

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