Clear and Preset Signals

A flip-flop could have clear and preset signals so it could

initialize its output Q
This is useful in the T flip-flop since the T flip-flop only toggles
the output; it cannot initialize it to a value
Clear and Preset are used as the following:

If Clear=1, Preset=0, the value of Q is initialized to 0

If Clear=0, Preset=1, the value of Q is initialized to 1
If Clear=1, Preset=1, the flip-flop will work as usual
In the case of T flip-flop, T=1 will toggle Q, T=0 will not change Q

The case when Clear=0, Preset=0, is not used.

T Flip-Flop with Clear and Preset Signals

This truth table corresponds to a positive edge trigger

T Flip-Flop with Clear and Preset

This one is a positive edge trigger
There is no bubble on the clock signal
Q

FF

Clear

CLK

Preset

Example: T Flip-Flop

With Clear and

Preset signals

* Fill the value of Q in the waveform

* The flip-flop is a positive edge trigger

CLK
Clear
Preset

Q
Equal to 1
because of Preset

Goes to 0 because
of toggle

Goes to 1 because
of toggle

Goes to 0 because
of Clear
4

Synchronized Adder
The D flip-flop is the simplest of all the flip-flop
D stands for delay because Q will be simply equal to D at the clock edge
Lets say we want to create a synchronized adder that give A+B at the edge
of the clock;
We simply give the result to a D flip-flop
X1 X0

S2

Y1 Y0

Adder
S1

S0

Clk

Clk
Q
S2

D
Q

Clk
Q
S1

D
Q

Clk
Q

D
Q

S0
5

Exercise

a)
b)
c)

Number 11.10 in the book

Convert by adding external gates:
a D flip-flop to a JK flip-flop
a T flip-flop to a D flip-flop
a T flip-flop to a D flip-flop with clock enable

Q+

1
1

D = JQ + KQ

a)
We fill the truth table of the
JK flip-flop and we make D
equal to Q+ .
D stands for delay flip-flop
because Q will be equal to D.

KQ J
0

Exercise

a)
b)
c)

Number 11.10 in the book

Convert by adding external gates:
a D flip-flop to a JK flip-flop
a T flip-flop to a D flip-flop
a T flip-flop to a D flip-flop with clock enable

We fill the truth table of the

D flip-flop. We then fill the
values of T to have the
correct Q-to-Q+ transitions.

T = D xor Q

Q+

To go from Q=0 to Q+=0, T=0

To go from Q=1 to Q+=0, T=1

To go from Q=0 to Q+=1, T=1

To go from Q=1 to Q+=1, T=0

b)

Look at Q and Q+, find T

7

Exercise

a)
b)
c)

Number 11.10 in the book

Convert by adding external gates:
a D flip-flop to a JK flip-flop
a T flip-flop to a D flip-flop
a T flip-flop to a D flip-flop with clock enable

CE

Q+

1
1

T = CE.D.Q + CE.D.Q
= CE (DQ + DQ)
= CE (D xor Q)

c)
We fill the truth table of the
D flip-flop with clock enable.
We then fill the values of T to
have the correct Q-to-Q+
transitions.

DQ

CE
0

Summary on Clock Levels and Edges

Positive Level Trigger
Negative Level Trigger

Q is updated
throughout the
clock level

Positive Edge Trigger

Negative Edge Trigger

Q is updated at
the edge only

In the book:
The positive and negative level trigger elements are called latches
The positive and negative edge trigger elements are called flip-flops

However, this definition is not universal

In the Lab 8 manual, the same element is called latch or flip-flop
When we are dealing with a latch or flip-flop, we need to know which
one of the four cases above it is (this information should be provided in
the problem)

Review
Examples and Exercises

Decoder with Enable Input

Active low logic
Usually IC decoders have an enable line and they are active low devices.

2-to-4 Decoder with enable.

Decoder Expansion
Smaller decoders can be used to build larger decoders.
e.g. using two 2-4 decoders we can build a 3-8 decoder or
using two 3-to-8 decoders we can build a 4-to-16 decoder

Major application of Decoder

The implementation of the full adder using a decoder
s = ( 1,2,4,7) and C= (3,5,6,7).

BCD to 7-Segment Decoder

A BCD to 7-Seg decoder is needed to properly address these seven

segments to display numbers

BCD to 7-Seg. Truth Table

mt

BCD Input BCD

x1 x2 x3 x4 Digit

7-Segment Display
a b c d e f g

0 0 0 0

1 1 1 1 1 1 0

0 0 0 1

0 1 1 0 0 0 0

0 0 1 0

1 1 0 1 1 0 1

0 0 1 1

1 1 1 1 0 0 1

0 1 0 0

0 1 1 0 0 1 1

0 1 0 1

1 0 1 1 0 1 1

0 1 1 0

1 0 1 1 1 1 1

0 1 1 1

1 1 1 0 0 0 0

BCD to 7-Seg. Truth Table

mt

BCD Input BCD

x1 x2 x3 x4 Digit

7-Segment Display
a b c d e f g

10

9
X

1 1 1 1 0 1 1
X X X X X X X

11

X X X X X X X

12

X X X X X X X

13

X X X X X X X

14

X X X X X X X

15

X X X X X X X

Outputs of the 7-Seg display expressed in minterm form

a = S m(0, 2, 3, 5, 6, 7, 8, 9 ) + S d ( 10-15 )
b = S m ( 0,1, 2, 3, 4, 7, 8, 9 )+ S d ( 10-15 )
c = S m( 0,1, 3-9 )+ S d ( 10-15 )
d = S m ( 0, 2, 3, 5, 6, 8, 9 )+ S d ( 10-15 )
e = S m ( 0, 2, 6, 8 )+ S d ( 10-15 )
f = S m ( 0, 4, 5, 6, 8, 9 )+ S d ( 10-15 )
g = S m ( 2, 3, 4, 5, 6, 8, 9 )+ S d ( 10-15 )

Output a
a = S m( 0, 2, 3, 5, 6, 7, 8, 9 )+ S d ( 10-15 )
x3x4
x1x2

00

00

01

a = x1 + x3 + x2 x4 + x2 x4

01

11

10

11

10

12

13

15

11

f(x1,x2,x3,x4)

14

10

Output b
B = S m( 0, 1, 2, 3, 4, 7, 8, 9 )+ S d ( 10-15 )
x3x4
x1x2

00

01

11

00

01

11

X
12

10

1
3

1
4

B x2 x 3 x 4 x 3 x 4

10

13

15

1
8

14

X
11

f(x1,x2,x3,x4)

10

Logic Equations for the 7-Seg outputs

a = x1 + x3 + x2 x4 + x2 x4
b = x2 + x3 x4 + x3 x4
c = x2 + x3 + x4
d = x1 + x2 x3 + x3 x4 + x2 x4 + x2 x3 x4
e = x2 x4 + x3 x4
f = x1 + x2 x3 + x3 x4 + x2 x4
g = x1 + x2 x3 + x2 x3 + x3 x4

Encoders
Performs the inverse
operation of a decoder
Has 2n input lines and n
output lines
The output generates
the binary code
corresponding to the
input value
Encoders can be
implemented directly
from the truth table
using OR gates

2n
Inputs

Encoder
Combinatio
nal Logic
Circuit

n
Outputs

21

Examples of Encoders
Octal to Binary Encoder
Only one input
has a value of 1
at a time
What If D3 and
D6 are both 1s
at the same
time?
An encoder
needs to
establish
priority

22

Examples of Encoders
Priority Encoder
Is an encoder that includes
a priority function, which
resolves the issue of having
two active inputs at the
same time
If two input are active at
the same time, the input
with higher priority takes
precedence.
D3 has the highest priority,
then D2 , D1, and D0.

Inputs

Outputs

D0 D1 D2 D3

Truth table of a 4-to-2 priority

encoder
23

Priority Encoder
Determining Boolean expressions for the 4-to-2 priority
encoders outputs

24

Similarly, K maps can be used to find the valid output indicator, v

V = D0+D1+D2+D4

4-to-2 priority encoders logic diagram

25

Multiplexers

Multiplexing means transmitting a

large number of information units
over a smaller number of channel
lines.
A multiplexer is a combinational
circuit that selects binary information
from one of many input lines and
directs the information to a single
output line.
The selection of binary information is
done by select lines.
n selecting lines are required to
select information from one of 2n
inputs

26

Example of a 2:1 Multiplexer

S
D0

D1

Y
D0

function table

Truth table

S
0
0
0
0
1
1
1
1

D1
0
0
1
1
0
0
1
1

Y = D0S + D1S

D0
0
1
0
1
0
1
0
1

Y
0
1
0
1
0
0
1
1

S
0
1

Y
D0
D1

S
D1

The output of the selected AND gate will be the same

as the input signal on the corresponding data input line
27

Internal Structure of a 4:1 Multiplexer

This function table lists the

input-output paths

AND gates and the Inverters

resemble a decoder.
Verify the operation of the MUX

28