IEEE JOURNAL OF SOLID-STATECIRCUITS,VOL. SC-6,NO.

6, DECEMBER

n-p-n transistor to monitor the emitter current of Q~A

and to limit the drive current to Qa~during the short circuit. In the new circuit, Q3A saturates when increased
current flows in R7 and then Q29 becomes a constant current source that accepts only 2 mA, The lower limiting
current is more desirable since it reduces dissipation.
There is a possibility that the inputs to an opamp will
be subjected to large rapidly changing voltages. The slewrate limitation at the emitters of the input transistors can
cause these devices to experience a transient emitterbase
breakdown when such an input is applied, and this could
produce a long-term degradation of the input super-/3
transistor characteristics. This mode is avoided by the
addition of diodes Dg and Dlo that shunt the input
emitterbase junctions under reverse bias.
Consideration must also be given to abnormal conditions imposed on the device. For instance, if the resistors
R10R13 were placed in an n island tied to the positive
supply and the positive supply were removed during
operation of the device, a parasitic substrate p-n-p (with
the resistors acting as emitters) would be turned on
causing large destructive currents to flow into the amplifier. This is avoided by tying the resistor islands to bias
points other than the supplies,

A Computer-Aided
BRUCE

A. WOOLEY,

357

1971
SUMMARYOF CHARACTERISTICS

The amplifier typically exhibits an open-loop voltage

gain of 500000, has an input bias current and offset
current of 8 and 1 nA, respectively, a voltage offset of
3 mV and an offset drift of 8 pV/C. The 40-V peak-topeak power bandwidth is 18 kHz, the small-signal bandwidth is 1 MHz, and the unity-gain voltage-follower
phase margin is 65. The amplifier is well behaved while
slewing and is quite stable under all feedback conditions.
One can arbitrarily sequence the power supplies, apply
input overvoltage, or output short circuit without damaging the device. Finally, the performance characteristics
remain essentially unchanged over a power-supply range
of ~5 to ~40 v.
RIWERENCES
[11 J. E. Solomon and G. R. Wilson, A highly desensitized,

wide-band monolithic amplifier, IEEE J. Solid-State Circuits,. vol. SC-1, Sept. 1966, pp. 1%28.
[21 L#l#rnan and H. Taub, Puke, Digital and Switching WaueNew York: McGraw-Hill, 1965, ch. 6.
[31 J. E. Solomon,. W. R. Davis, and P. L. Lee, (A self compensated monolithic operational amplifier with low input current
and high slew rate, ISSCC Digest Tech. Papers, Feb. 1969,
pp. 14-15.
[41 A. S. Grove, Physics and Technology oj Semrioaducto?Devices. New York: Wiley, 1967, ch. 11,

Evaluation of the 741 Amplifier

MEMBER,IEEE, SING-YUI J. WONG, STUDENTMEMBER,IEEE, AND

DONALD O. PEDERSON, FELLOW, IEEE

AbsfracfAlthough the basic operation of modern IC opamps

is well understood, no detailed evaluation has been published
concerning the characteristics of the transistors and the performance
limitations resulting from the devices and the individual stages of
the amplifier. In this paper, the results are given of an investigation
of a typical example of the 74l-type IC amplifier. Complete data
are given on the transistor characteristics and parameters. Computer
simulation is used to study the performance and limitations of the
stages and the overall amplifier.

Manuscript received August 9, 1971. This work was supported

by the U.S. Army Research Office, Durham, N. C., under Grant
DA-ARO-D-31-124-71 G-50 and the Joint Services Electronics Program under Contract F44620-71-C-0087. An earlier version of this
paper was presented at the 1969 IEEE NEREM, Boston, Mass.
B. A. Wooley was with the University of Cahfornia, Berkeley,
Calif. He is now with Bell Telephone Laboratories, Inc., Holmdel,
N.J. 07733.
S.-Y. J. Wong iswith the Department of Electrical Engineering
and Computer Sciences, University of California, Berkeley, Calif.
D. O. Pederson is with the Electronics Research I,aboratory
and the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, Calif. 94720.

I.

INTRODUCTION

HE 741-type amplifier is representative of many

presently available and widely used integratedcircuit operational amplifiers (IC opamps) [1],
[2]. Certainly, subsequent improvements in the design
have been made with respect to input current levels [3],
large-signal slew rate [4], and low quiescent power [5].
Nonetheless, the 741 exhibits many of the design decisions,
opportunities, and problems that are typical of generalpurpose IC opamps [6]. Although the basic operation of
this type of IC is well established, no detailed evaluation
has been published relating the performance limitations
to the various devices and stages, In addition, no detailed
information is generally available on the typical characteristics and parameters of the devices in this type of IC.
In this paper, such an evaluation is made for a representative example of the 741 amplifier. The results are based

+
I

IEEE JOURNAL OF SOLID-STATECIRCUITS.DECEMBER 1971

358

on experiments with actual amplifiers and devices and

on computer simulation of the amplifier and its stages.
Computer simulation of highly complex circuits can
now be readily accomplished using a number of recently
developed,
efficient computer-aided
circuit analysis
(CACA) programs [7]-[ 10]. These programs, together
with extensive experimental device characterization of
the parameters of the different types of bipolar transistors, have been used to make a thorough investigation of
the internal performance of the operational amplifier
shown in Fig. 1, This is the schematic diagram of the
ICL 8741, which is manufactured by Intersil, Inc. The
schematic is taken directly from photomicrographs of
chip samples. The circuit differs somewhat from the usual
741 circuit diagram that is shown in many manufacturers data sheets.
As indicated in Fig. 1, the 741-type operational amplifier can be separated into four subcircuits: a biasing
reference network, a differential input stage, an intermediate gain stage, and a single-ended output stage. In
Appendix 1, short explanations are included of the operation of the individual stages of the 741-type amplifier.
The salient features of the design approach employed in
the 741 are the extensive use of lateral p-n-p devices and
the active device loading of the gain stages to achieve the
required high gain with a minimum number of stages,
The latter also permits frequency compensation with a
single relatively small capacitance.
In the next section of this paper, the results of the
characterization of the devices in the ICL 8741 amplifier
are given, These data are used in the simulation of the
amplifier and of the individual stages. The results of this
simulation and a performance evaluation are included in
the succeeding section. In Appendix 11, the measurement
techniques used for device characterization are summarized.
11.

DEVICEMODELINGANDCHARACTERIZATION

In order to obtain an adequate simulation of the 741type amplifier, suitable device models and parameter
values must be established. In the ICL 8741 realization
of this amplifier there are six different types of transistors: the small n-p-n and lateral p-n-p devices that are
used throughout most of the amplifier, the large n-p-n
and substrate p-n-p output transistors Qll and QzO,the
double-collector lateral p-n-p Ql:;, and the double-emitter
substrate p-n-p Q2$. Plan views illustrating the planar
geometry of each of these devices are given in Fig. 2.
ivonlinear
For

DC

and

nonlinear

Time-Response

+15V

Q,2

Q8 14P
+ Ov
Q, Q2 _,N

Q9

14,U
)V +

0.732m

-IN

39k R5

Q3

Q4

+Vcc+14p

14p+124p
~

+27p -13.8

Q,,

Q,O

3k R4

BIASING

Q5

Q6

iiii 1 ,~2 50;k3

INPUT

REFERENCE
NETWORK
Fig.

Q7 -13.7

STAGE

1.

INTERMEDIATE

OUTPUT

STAGE

STAGE

Schematicdiagramof the ICL 8741 amplifier.

1,

B~

(b)

6.5

n
(c)

CollectorA

ot~
0.75

T
la,;,;,
?.25 9/16

~
1P!l
~3.25+

j/

(d)
f

(e)

Models

dc and time-response

analyses

of the

amplifier, the augmented EbersMoll two-diode model

as shown in Fig. 3(a) is used for the transistors. In the
model of Fig. 3 (a), the parameters /30 and ,~01represent
the short-circuit current gains of the ce connection for
normal and inverse operation, respectively, and 1. and 1~1
are the corresponding junction saturation currents.
It is assumed that the collected component of current

I_

(f)

Fig. 2. Plan views of the 741 transistors. All dimensions are

in mile,. (a) Small n-p-n. (b) Large n-p-n. (c) Lateral p-n-p.
(d) Large substrate p-n-p. (e) Dual-collector lateral p-n-p.
(f) Dual-emitter substrate p-n-p.

wooLEy et al.:EVALUATION OF THE 741 AMPLIFIER

359

Cj~

r-+---l

O.-O
Ic/Ipe.k

1.0

:
-a
<

-k.
0.05

(b)

(b)

b
c

~,k,
~.0316

0.1

0.316

1.0

3.16

Ic (mA)
,

EL
(c)

Ww
4

Fig, 4. Normalized plots of (a) (3, and (b) r, with collector current. (a) Curve a for small n-p-n, large n-p-n, and substrate
p-n-p; curve b for lateral p-n-p. (b) Curve a for large n-p-n;
curve b for small n-p-n and lateral p-n-p; curve c for specml
devices Q,, and Q=.

(d)
Fig. 3. Transistor circuit models. (a) Nonlinear model for an
n-p-n transistor. (b) Small-signal hybrid-r model for n-p-n
device. (c) Small-signal hybrid-~ model for lateral p-n-p demce. (d) Small-signal hybrid-m model for substrate p-n-p device.

in the normal mode can be characterized by

I cc = I, exp (qV~E/lcT).

(1)

IS1 is similarly defined. Charge-storage effects in the

model are included with the base-charge (diffusion)
capacitance g,., Tt (where Tt is the average base tranSit
time), the junction capacitances Cje and Cj,, and the
parasitic substrate capacitances. The ohmic base resistance rb, the collector saturation resistance r., and the
basewidth modulation resistance r~ are also included.
The model of Fig. 3(a) is inciuded as a built-in model
in the programs SLIC [7] and CANC~ [8]. For program
BIAS-3 [9], the built-in model is the intrinsic EbersMoll
model. For program TIME [10], the intrinsic model plus
the base-charge and junction capacitances are built in.
Element values for the transistor models are established through the experimental characterization of device parameters. Device samples for this characterization
were provided by Intersil, Inc., in the form of ICL 8741
amplifier chips for which metalization was altered to
permit the examination of individual devices. Several
samples of each device type have been characterized and
data representative of typical devices have been obtained. A brief description of the characterization procedure is given in Appendix II.
Device d,ata for the six transistors of Fig. 3 are summarized in Fig. 4 and Table I. In the first row of Table
I, values for the junction saturation current for normal
operation 1. are presented. For the 741 amplifier no transistors are in inverse or saturated operation. Thus, measured values of I.I are not needed.

In Fig. 4 (a), normalized plots of /30, the small-signal

common-emitter current gain for forward bias, are given
as functions of the dc collector current Ic. (When needed
for clarity, the subscript p is added for a p-n-p transistor, e.g., gPO.) The maximum values of ,/30 and the current at which it occurs are given in Table I. Note that
the variation of /30 and lc below the peak is the same for
all the transistor types. Above the peak, the ,~0 of the
lateral p-n-p drops off faster than the others. It is found
that the values of dc current gain I1 follow the same
variation with Ic as does ~n. The ratios of BI/pO are given
in Table I. Values for B1, the current gain for inverse
operation are also given in Table I. A single value of B1
with respect to lc has been found sufficient to characterize
both the dc and small-signal gain for all quiescent conditions.
The dependence of the normalized ohmic base resistance ?2)on collector current for the different transistors is illustrated by the curves of Fig. 4(b) and reference values are given in Table I.
The variation of junction and substrate capacitances
with junction voltage follows the relation:

c
=(+%+
c

(2)

where @z is the electrostatic potential of the junction,

V~ is the reverse bias voltage across the junction, and
Ck is a constant. From log-log plots of the experimental
results and best fit approximations with (2) it was
determined that C, = 0.7 pF (Values of 0.60.8 pF were
observed. It is to be noted that Ch is not Cpi. of Appendix
II, which has already been removed.) For the collector
junction of the n-p-ns (and both junctions of the lateral
p-n-ps) I#IC
& 0.45 V with nC = 3. For the emitter junction of the n-p-ns, O, = 0.6 V with n. = 3. For the sub-

360

IEEEJOURN.4L
OFSOLID-ST.lTE
CIRCUITS,
DECEMBER
1971
TABLE I
TRANSISTOR

Small
n-p-n
1.26

1.,(10-A)

290
03
072
2,5
670
300
1.45
1,15
405
0.65
().36
32

Do:..

I&~a,(mA)
B/(3,
B1

rblo 05mV(~)

rc(Q)

rl(lo+)
Tt(nS)
Tfr(ns)

C,.o(pF)
Cjc,(pF)
C,,(pF)

PARAMETERS

Large
n-p-n

Latera]
p-n-p

Substrate
p-n-p

0395
520
03
() 77
61
185
15
().97
O 76
243
28
1 55
7.8

3.15
95
(),11
().79
38
500
150
4,7
27 4
2540
0,1
1,05

17,6
130
0 11
0.90
4.8
80
156
4.47
26.5
2430
,-..
*. w)

strate junctions, ~, e 0.6 V with n, & 4. The placement

of the substrate capacitance for the lateral p-n-p is
illustrated in Fig. 3(c). Experimentally determined values
for C,ZOare given in Table I.
In program SLIC, n, = n. = 3 is assumed as well as
4. = 0.7 V and 4. = 0..5 V. Appropriate values of C,
are added external to the transistors. C, is assumed constant at a value appropriate for large reverse bias, Similarl y, for program TIME, the values of n, = ?1. =3
are used together with +. = 0.7 V> +. = 0..5 V. The elements rb, Ye{, and C, are added as separate elements.
It has been determined by use of the simulators that
precise values of O. and n. are not necessary for C,,
and C,., i.e., the error introduced is negligible for slight
clifferences.
Values of the ohmic collector resistance r, and the
basewidth modulation factor q are given in Table I
along with the normal and inverse transit times ~Land ~~~.
7~ and ri ~ represent the sum of the intrinsic base transit
time and the collector depletion layer transit time.
The value of r, falls off with IC due to high-level
injection effects. For simplicity, this nonlinearity has
been neglected and r, is taken as a constant [7]. The
value of transit, time is established from measurements
of the transistor f, as a function of current, using the
relationship
1

~~

2rf, qI.
Linear

Svtall-Signal

(c,. + c,.)

+ T.c, c + !-,.

0.9
0.4
0.03
0.95
1.4
1000

(3)

Models

For small-signal response analysis, a modified hybrid-~

transistor model is used [11]. Shown in Fig. 3 (b)-(d)
are the models for n-p-n, lateral p-n-p, and substrate
p-n-p devices. The intrinsic elements of the model are
I For the lateral p-n-p device used in the ICI, 8741, a
6 dB/octave (one-pole) rolloff is obtained for the gainfrequency response. Consecluently the lumped element model of
Fig. 3(c) is appropriate for modeling these devices. Special
modeling of distributed effects as might be necessary for lateral
devices with less than 6 dB/octave rolloff [12], is not required.

Double-Emitter
Substrate p-n;p
.4

0,79
94
0.015
0.85
1.5
1100
170

25

1.9

007
() 78
1,5
1600
120
3.1
27.4
220
0.1
(){)

80
2!,;
55

0.1
0.3
4,8

28

5.1

Q,,

Double%ollector
Lateral p-n-p
A
B

3.26
26.5
9550
1.1
2.4

4,8

00063
21
0.015
0.9
1.0
650
100
1,55
26,5
2120
;:

described by

(4)

r== Po
9.

(5)

1
7(J=
V9m

(6)

c. = C,e+ g.,,

(7)

where Ic is the quiescent collector current.

Special

Devices

As indicated in Fig. 2, the double collector lateral

p-n-p Ql:; is similar in structure to the other lateral
p-n-p devices except that the collector is split in two
sections. For the computer-aided analysis, this device
may be modeled as two devices with emitters and bases
connected in parallel. The resistors and capacitors of the
circuit model are appropriately adjusted. Particularly
important, since Q]s is used as a current source, are the
currents resulting at collectors A and B relative to the
current in the diode-connected transistor Q12. These relationships are indicated by the relative collector currents for normal operation:

I C13A
= 0.286
I C12

(8a)

I C13B
= 0,714.
I C12

(8b)

The double-emitter substrate p-n-p transistor Qz~ can

be modeled as two transistors with connected bases and
collectors. Emitter A corresponds to the emitterfollower
input of the output stage, while B is the normally inactive remote emitter.

WOOLEY et al.: EVALU.4TIONOF THE 741 .4MPLIFIER

361

III. SIMULATIONRESULTSAND COMPARISONS

150100-

Quiescent

Conditions

50-

The quiescent current and voltage conditions of the

amplifier were dete~mined using the nonlinear de analysis
program BIAS-3 [9]. The results are included in Fig. 1.
For the dc analysis, a feedback resistance of 100 k~ is
connected from the output to the inverting input together with source resistances of 1 k~ and a load resistance of 10 k~. The use of external feedback is necessary
to establish the proper dc levels in the output stage.
However, the internal do conditions are not very sensitive to the amounts of feedback applied. The total simulated dc current from the ~ 15-V supplies is 2.14 mA at
300 K, corresponding to a quiescent power dissipation
of 32 mW.
Gain

Frequency

Response

of the Complete

150,

:=
---

Simphfied

gom rmnver$[~n

i~Hz

100

Amplijier

---_..&

50

To obtain the gain-magnitude and gain-phase responses, it is necessary to simulate the complete openloop amplifier of Fig. 1 including a source resistance of
1 k~. For this simulation, the ac circuit model including
adequate device models is very large. To obtain the
desired type of results, three different CACA programs
were used. As a first step, the results of the dc state
simulation using BIAS-3 were used and the corresponding
transistor small-signal parameters were established using
the eauations of the last section. Next, the ac model of
the complete amplifier was analyzed using ROHRER,a
predecessor of the ac portion (for the sinusoidal steadystate response) of program CANCER[8].
This computer simulation verified that the smallsignal gain-frequency performance of the 741-type amplifier is determined almost entirely by the response of the
input and intermediate gain stages. This has been
checked by a simulation of only the first two stages. The
loading on the second stage by the output stage with the
short-circuit protection circuitry was modeled with a
simple emitterfollower. Further simulation runs also
showed that the p-n-p current sources could be replaced by ideal current sources in shunt with large resistors to represent the output resistance. Therefore,
further consideration of the gain-frequency response of
the amplifier could be carried out using a simplified
version of the first two stages as well as of the output
stage, This simplification permits additional analysis of
the response in terms of poles and zeros of the gain
function using program SLIC [7], which is limited at
present to circuits with less than 51 nodes. This program automatically establishes the small-signal device
model parameters after it has determined the dc state
of the circuit. The poles and zeros of the gain function
as well as the frequency response are then determined.
The results of the simulations using SLICare presented
in Fig. 5 and Table II. The amplifier provides a lowfrequency voltage gain of 111 dB. The unity gain frequency for the amplifier as compensated by the manu-

o%

\
,b,

,b,

Frequency

,b,

!
105 Hz

-D

(c)

Fig. 5. Gain frequency response. (a) Gurve a for open-loop

magnitude response without compensation; curve b for openIoop magnitude response with compensation,; curve c for open100P phase response without compensation; curve d for
open-loop phase response with compensation. (b) Curve a for
open-loop gain-magnitude response with frequency; curve b
for open-loop phase response. (:) CMR ver~s frequency;
curve a for 741; curve b for sirnphfied gain conversion network.

facturers suggested capacitance value of 30 pF is 1.54

MHz with a phase margin of 60. The phase crossover
frequency with compensation is 4.1 MHz. The frequency
response of the open-loop amplifier for a noninverting
input was found to be identical to that for the inverting
input.
In Table 11, the most dominant poles and zeroes are
listed corresponding to both the compensated and uncompensated open-loop responses of Fig. 5. As indicated
by these data, the addition of the 30-pF compensation
capacitor results in an extreme fpole-splitting action
between the first and second most dominant poles. The
compensated open-loop response has a dominant onepole rolloff to unity with 60 of excess phase at unity
gain. The location of this dominant pole in the compensated response, and consequently the compensated
unity-gain frequency, is determined indirectly by the
location of the remaining poles. These nondominant poles
establish how close the dominant pole must be brought
to the origin, through compensation, to achieve a 6
dB/octave rolloff to unity gain.
Balance-to-

Unbalance

Conversion

A double-to-single-ended
gain conversion network is
formed by transistors QE, Qe, and Q7 and provides approximately balanced transmission from either of the
two inputs to the single output. Consequently, excellent
common-mode rejection, which is the difference between

362

IB>!3E JOURNAL

TABLE
DOMINANT

OF SOLID-STATECIRCUITS,DECEMBER 1971

11

POLES AND ZEROS OF THE SIMULATED

OPEN-LOOP

GAIN FUNCTION

Zeros
(10 rad/s)

Poles

(10 rad/s)
Imaginary

Real
No compensation

Compensation

5.4!2278E
6.82301E
1.69079E
1 69079E
2,40549E
1 14400E

+
+
+
+

02
01
01
01
01
02

2 75826E 05
2.40085E
+ 01
8.24558E
+ 01
3,9S042E + 01
1.44745E
+ 01
1,44745E
+ 01

0
0
0
0
(1
j 2248$)E
3.22489E

the differential-mode gain and common-mode gain, is

expected since common-mode signals appearing at the
collectors of Q~ and QG are almost exactly cancelled at
the output.
The gain and common-mode rejection (CMR) as functions of frequency for the corn] )ensated amplifier are
presente~ in Fig. 5 (b) and (c) for two gain conversion
circuits, viz., the actual circuit and a simpler diocle
transistor load circuit for which Qs is diode connected, and R2 and Q7 are omitted. From Fig. 5 (b 1, it is
seen that the gain-frequency characteristics of the input
stage are not significantly influenced by the use of the
simpler gain conversion circuit. However, it is clear
from Fig. 5 (c) that the common-mode rejection characteristics are markedly inferior for the simpler network.
At dc, the common-mocle rejection is 83 dB for the
amplifier with the simplified network, while for the gain
conversion network actually used, a figure of 100 dB is
obtainecl,z The common-mode rejection falls off at higher
frequencies. This is due to the large amount of internal
local feedback, which is used to produce a very low
common-mode gain. Consequently, a large bandwidth is
achieved in the frequency response of the common-mode
gain, and in the case of the 741, there is peaking at the
band edge. Thus, the CMR falls off.
Improved

p-n-p

Performance

From the computer simulation runs, using various transistor parameter values, it has been established that the
second most dominant pole of the open-loop amplifier
gain function (compare Table II), can be associated to a
large extent with the charge storage in the lateral p-n-ps
Q, and Q,. The model element for these p-n-ps that procluces this effect is CT representing base charge.
The effect of replacing Q,+and Q~ in the 741 amplifier
z It must be noted that the common-mode rejection ratios of
Fig. 5(c) are for an idealized case where perfectly matched devices are assumed. For this aase, the rejection characteristics are
determined solely by the ci~cuit configuration. In an actual amplifier, common-mode rejection ratios somewhat lower than those
indicated are to be expected as a result of mismatched components in the input stage.

01

+ 01

Real
4,284 63E
6.556 20E
6 425 21E
8.386 15E
9.347 04E
1 368 57E
4,284 63E
6 844 47E
6.55620E
6 425 21E
8,386 15E
1.36857E

Imaginary

+
+
+
+
+
+
+
+
+
+
+
+

01
01
01
01
01
02
01
01
01
01
01
02

0
:
()
o
0
0
0
0
0

TABLE III
GAIN AND FREQUENCY
PERFORMANCE
OF 741 AMPLIFIERS
WITH LATERAL P-N+S AND IMPROVED P-N-IJS

Lateral
p-n-ps
Low-frequency gain
Uncom~ensated ~hase crossover
Compe&ation c~pacitance for
identical margin
Unity gain frequency when
compensated for identical
margin

111
dB
0.50 MHz
30

pF

1,54 MHz

HighPerformance
p-n-ps
112
dB
0.63 MHz
20

pF

2,87 MHz

with high-performance p-n-p devices is shown in Table

III. A technology for realizing improved p-n-p transistors, compatible with conventional n-p-n devices, has
been proposed [13 ]. For convenience, small-signal characteristics for the improved p-n-ps were assumed identical to those of the small n-p-n transistors. As indicated
in Table III, the use of the high-performance p-n-p clevices results in only a 8.5 percent increase in lowfrequency voltage gain and a 26 percent increase in the
uncompensated crossover frequency. For the same compensated unity-gain phase margin as maintained with
the lateral p-n-ps, a compensation capacitance Cy of
20 pF is required.
From Table III, note that the compensated unity-gain
frequency is only doubled. Clearly, the use of improved
p-n-p devices in the amplifier will not alone lead to a
major increase in bandwidth. In addition, as brought out
below, distortion in the output stage becomes significant
even for moderately large signals at frequencies on the
order of 4 MHz. Any improvement of the frequency
response of the first two stages above this frequency
will be dominated by the output stage response.
Output

Stage Characteristics

The class-AB output stage of the 741-type amplifier

has been investigated experimentally with actual output
stages from 741 chips and theoretically with computer

WOOLEY et Ill.:
EVALUATION OF THE 741 AMPLIFIER

v,,, (volts)

363

using TIMEverifies that the distortion seen in the 4-MHz

wh,veform is causdh mainly by the slow discharge of

15-

and
QN. BY changing the transistor parameters of
QZOsuch that they are identical to those of QIA, the distortion in the output becomes less noticeable. A mismatch
in the ~. of Q14 and Q20 has little effect in distorting the
output .
(h.

10

5-

-70
. .

10

15

15

20

IV. SUMMARY

(a)
Computer simulated

Expenmentol

The size of the circuit model of modern IC opamps is

so large that only recently have simulators become available to study and evaluate their performance. Tlie results
of the present investigation show that the new simulators
are not only adequate for the job but also present one
with a means to study effectively the limitations of the
stages and the limitations imposed by the devices.
For the 741-type amplifier, it has been verified that a
most efficient design has been made with respect to
differential-mode and common-mode gains and gain frequency response. Although the lateral p-n-ps appeared
to be the probable major cause of the frequency limitation, the output stage as well as other effects from the
first two gain stages also become important in the same
frequency range. The use of improved p-n-ps for the
present laterals will not produce significantly changed
behavior.
The new simulators also permit ready investigation of
problems of tolerance, the effects of modeling complexity,
and the effects of errors in device characterization.

(b)

Fig. 6. (a) Dc transfer characteristics of the output stage. (b)

Simulated and experimental input and output time responses
for the output stage at 0.5, 2, and 4 MHz, respectively.

BASIC AMPLIFIER OPERATION

Input Stage

simulation. For the latter, the nonlinear CACA programs

BIAS-3 [9] and TIME [10] were used. In Fig. 6 (a), the
dc transfer characteristic of the stage is given as obtained both experimentally and with the program BIAS-3.
An extremely linear characteristic with near-unity gain
is obtained for almost the full supply voltage range.
There is virtually no crossover distortion for the stage.
The dynamic response of the output stage is indicated in the simulation results and the experimental
waveforms shown in Fig. 6 (b). For a 4-V peak-to-peak
input signal at the base of Qz~~, the resulting output
voltage waveforms at frequencies of 500 kHz, 2 MHz,
and 4 MHz were computed using the nonlinear timeresponse analysis program TIME. As indicated in the
figure, at 2 MHz and above, phase shift and distortion
become increasingly noticeable in the response.
The distortion in the output waveform occurs primarily
during positive signal swings and appears to be caused
mainly by slow discharging at the base of the transistor
Q,,.. Both Qz3A and Ql~ turn on with negative input at
the base of Q2~A and both Q23A and Qzo turn off with
positive input. At a frequency close to the cutoff frequency of the substrate p-n-p transistors, the turnoff
delay of both Qz3~ and Qzo is significant. The simulation

The input stage of the amplifier as shown in Fig. 1

consists of a balanced pair of composite n-p-n-lateral
p-n-p devices. An active high-impedance load is used to
achieve high voltage gain. This load also includes a
double-to-single-ended gain conversion connection, which
leads to very high common-mode rejection.
The balanced composite-device input pair in Fig. 1
is formed by transistors QI-Q4. The differential-mode
equivalent half-circuit for this pair is the commoncollectorcommon-base
cascade. The full differential
transconductance of the input pair is approximately

where Icl is the quiescent collector current in the n-p-n

device, Z?l, and BI,O are the dc and incremental lowfrequency common-emitter current gains of the lateral
p-n-p transistors, respectively. The differential input
resistance of the input stage is twice the input resistance
of the half-circuit.

IEEE JOURN.4L OF SOLID-STATECIRCUITS,DECEMBER 1971

364

where p. is the incremental low-frequency

commonemitter current gain of the n-p-n devices. The high differential resistance of the stage is achieved by maintaining a low input stage quiescent current Icl.
The active load of the input stage, which includes the
double-to-single-ended gain conversion scheme, is formed
by transistors Qs, QG, and Q7, and resistors RI, Rz, and
Rs. The resistor R, is used to achieve a very high output
impedance for Q6. An identical RI is added to maintain
equal baseemitter voltages and consequently equal collector currents for Q5 and Q6. The resistor R2 is used to
bias the emitterfollower Q7 at a current comparable to
that in Qs and QG.
A description of the gain conversion scheme of the
active loads is simplified if a modified circuit arrangement is initially considered. In Fig. 1, let Q5 be diode
connected by shorting together the base and the collector
terminals. Q7 and Rz are deleted for the moment. Qs, Qe
and resistors RI and R3 constitute the familiar diode
transistor bias pair. When a differential input signal is
applied to this modified input stage, equal and opposite
current increments ( ~A~) result at the collectors of Q5
and Q6. The current change at QG is supplied directly to
the load of the stage, the base of Ql& If the base currents
of Qs and QG are neglected, the current increment from
Q3, at the collector of Qs, results in an identical increment in the collector current of Qs. Since Qs and Q6 are
driven by the same base-emitter voltage and since the
clevices are assumed matched, there is a corresponding
change in the collector current of Q6. This change is fed
to the load (Q16) in phase with the signal from QA, and
a total output current change of 2AI results.
If the transistor base currents are included, the incremental current transmission from the input of the gain
conversion current AI to the collector of Q6 for the simplified arrangement is
AICe
=
AI

(1 + 12/i30)

(11)

where ~() is the low-frequency common-emitter gain of

ideally matched devices Q5 and QG.
For the gain conversion network actually used in the
741-type amplifier, the deviation of (11) from unity is
reduced due to the introduction of the emitterfollower
Q, and the bias resistor R2. The current gain from the
inputs to the single-ended output is given by
A1cO/A~

= 1/(1

+ 2//30(30)

(12)

where ~() is the low-frequency

current gain of the
emitterf ollower.
The active load of the input stage (Q,, QG, et al.)
presents a severely unbalanced load to the preceding
p-n-p pair. The load impedance of QA is very large since
it is the output impedance of transistor Q6, as modified
by the series resistor R:3, in shunt with the input impedance of the intermediate gain stage. However, the
load impedance of Qa is essentially the relatively low

impedance of a diode-connected
transistor in series
with RI. This load imbalance for the composite input
pair results in a significant degradation in commonmode rejection, particularly at high frequencies. The
input voltage offset and offset drift of the amplifier may
also be adversely affected.
Intermediate

Gain Stage

of Fig. 1 consists of a
The intermediate gain stage
modified Darlington pair QIGQITwith an active current
source load Q13. Transistor QZZ is part of the output
short-circuit protection and is normally in an off condition.
The emitterfollower input QIGestablishes a high input
impedance for the stage, while the active load QR provides for large voltage gain. Because of large gain as well
as the fact that this stage is driven from the very high
output impedance of the first stage, unity-gain compensation of the complete amplifier can be achieved
through the Miller-effect multiplication of a relatively
small capacitance Cf.
The current level of the emitterfollower QIG is determined by the voltage drop across the 50-k~ resistance
Rq. The current-source transistor Ql~ is a dual-collector
lateral p-n-p biased from the biasing reference network.
Output

Stage

The output of the amplifier is a complementary classAB configuration with unity voltage gain. Transistors
QM and Q,,, establish a two-diode voltage drop between
the bases of the output emitterfollower QIA and QW
minimizing crossover distortion. The quiescent current
in Qls and Qlg is derived from collector A of the lateral
p-n-p current source Qls. The emitterfollower Q23 Provides a high load impedance for the intermediate gain
stage and isolates this stage from the amplifier output.
Q,, is a substrate p-n-p transistor with a second emitter
B added to prevent overdriving, and possible burnout,
of the intermediate gain stage. If QIG is driven hard
enough to saturate QIT, the emitter B of Qx, which is
normally inactive, begins to turn on and reduce the
input to Q16.
Short-circuit protection of the output stage during
positive output swings is provided by resistor R6 and
transistor Q15. If the output current through R6 becomes
excessive, Q15, which is normally off turns on and reduces
the drive to the base of the n-p-n output transistor Q14.
For negative output swings, short-circuit protection is
provided by R~, Qzl, QM, and Q2Z. When the negative
output current becomes excessive, the voltage drop across
R7 turns on the lateral p-n-p transistor Q~l. The resulting current in the diode-connected transistor QZ4 turns
on transistor QZZ and thereby reduces the input to QIG.
The voltage at the collector of Q17 rises correspondingly
and the drive to output substrate p-n-p Qz,o is reduced.
There is no internal provision in this amplifier to
ensure proper dc setup of the output stage. The external

wOOLEY

f?t
U/.
:EVALU.iTIONOF THE 741 AMPLIFIER

365

application of overall negative feedback is relied upon

to establish an insensitive zero-volt quiescent output
level.
Biasing

Reference

Network

The biasing stage of Fig. 1 establishes the current

levels in all three amplifier stages and provides a sink
for the base current of the p-n-p input devices Qs and
Q,. A reference current is set up in the resistor R5, which
is connected across the full supply voltage less two
diode voltage drops. This current is
~

_
.

~CC

VEE

(@n

412)

E5

(13)

R5

where @l1 and 412 denote the baseemitter voltages of

QII and Q,., respectively. The base voltage cjf Q12 then
establishes the current level in the double-co] lector current source Q13 determining the quiescent current available to the intermediate and output stages.
The baseemitter voltage of QII is used in conjunction
with the resistor Rz to establish a current in QIOthat is
significantly lower than the reference current l,~ts.Because
the geometry of QIO is identical to that of QI~, the collector current of Q,,, is given implicitly by
I.

~~ln~
R, q

(14)
Clo

where it is assumed that the base currents of Q1l and

Q,, may be neglected. The collector current of QIO in

turn defines the quiescent input stage current level

11 + 1C2 = lC [ 1 + BD +

1
2(1 +

l/B,,)

II

EXPERIMENTAL DEVICE CHARACTERIZATION

The experimental procedures used for device characterization are summarized briefly in this Appendix.
Current

Gain

The de and the small-signal low-frequency current

gains, B or Bn and /30or ~PO,are determined by imbedding
the test device in a single-stage common-emitter amplifier configuration. Measurements are taken with lo as
a parameter. For ac, the amplitude of the input source
is ad,justed to maintain a peak-to-peak
signal of less
than 10 mV at the input of the device.

Lollector
Saturation

Modulation

The effect of basewidth modulation is modeled by the

resistor r. [7],

(16)

Resistance

The series collector resistance r: is determined from

measurements of the transistor collectoremitter voltage in saturation, The slope of the Ic17c~ characteristic
presented on a curve tracer is used for approximate
values. For a more precise value, voltage and current
measurements are used.
Ohmic Base Resistance
The principal effect of the base resistance in this study
is its influence on the amplifier band-edge response.
Therefore, r?, is evaluated at a number of dc current
levels using high-frequency small-signal input impedance
measurements. Results from this method are appropriate
for evaluating band-edge performance and have been
found to agree closely with estimates of r~ based on
noise measurements.
The basic assumption establishing rb from input impedance measurements is that the transistor input impedance can be modeled by the series combination of
r~ and rr in parallel with a capacitance Ct [11]. The
input impedance of this circuit is given by
1 + j@(r,
II ?_T)c, .
1 + jlw. c,

Z,n(j(tl) = (7, + ?Z)

(17)

A plot of the real versus imaginary parts of (17) as a

function of frequency o results in a semicircular locus
with intercepts on the real axis of rb + r~ at w = O and
rbat~=
CO.
To determine rl: at a particular dc collector current, the
real and imaginary parts of the input impedance are
measured, e.g., with a WayneKerr admittance bridge,
at several frequency points through which a circular
locus is drawn. The base resistance is then estimated
by extrapolating the circle to the O) = w intercept of the
real axis. Because of the inductive effects, as well as
model inaccuracies, the measurements deviate from the
circle at very high frequencies. This deviation occurs
well above the band-edge frequency of the amplifiers
under consideration. However, care must be taken to
ensure that the circle is established from points corresponding to frequencies where the inductive effects are
not significant. A suitable check for the method is the
w= O intercept at rb + r~, which
should
be
consistent
with ~r as determined from (4) ancl (5).
Junction

Basewidth

l/qqm,

which is the reciprocal of the small-signal commonemitter output conductance. It is measured with a bridge,
with a low ac impedance at the transistor input. Measurements were made at several values of Ir to verify the
adequacy of (161.

(15)

where Icl and 102 are the collector currents of QI and Q2,
and 13p is the dc common-emitter current gain of the
lateral p-n-p devices, Q,3,Q~, QS, and QS. In establishing
(15) the base currents of Q, and Q2 are ignored with
regard to their contribution to the emitter currents of
these devices.
APPENDIX

r,, =

Capacitance

The junction capacitances are measured with an admittance bridge, such as the Boonton model 75C direct
capacitance bridge, at a frequency on the order of 100

.600
..

IEEE JOURNAL OF SOLID-STATECIRCUITS,VOL.SC-6,NO. 6, DECEMBER

1971

kHz; the signal level across the junction is held to less

than 10 mV peak-to-peak. At such a relatively low
measurement frequency, inductive effects can be neglected and the parasitic elements of principal concern
are the pin-to-header capacitances of the device package.
The pin capacitances have been measured with leads
broken at the chip and found to be approximately 0.7
pF for a typical 8-pin TO-5 can. For the baseemitter
junction,
the measured capacitance is approximately
C. F(measured) = C,. + C.i.

(18)

while for the basecollector and collector substrate junctions the measured capacitance is approximately
C,c(measured)

= C,. + 2Cpi.

(17)

and
CCS(measured) = C. + 3CP,.
Transit

(18)

Time

The transit time Tf is established through relationship

(3) from measurements of the transistor j~ as a function
of the dc collector current. To determine ft,the current
gain versus frequency response of the device is measured
with a very low load impedance. Points on the 6 dB/
octave rolloff of the response are established and extrapolated to unity gain. Alternately an ft meter can be used
that measures the gain magnitude IAII at frequency fl,
which is assumed to be well above corner frequency of
the gain response, again with a very low load impedance.
For a one-pole rolloff ft = IAII fl.
ACKNOWLEDGMENT

The authors are pleased to acknowledge the contribution of their present and former colleagues in the Integrated Circuit Group of the Electronics Research Laboratory, University of California, Berkeley. In particular,

A Five-Terminal

is to be noted that the initial phase of this investigation was the M.S. degree project of G. Pate] and
M. Schwartz. For the device characterization and for the
use and development of the simulators, we thank
I. Getreu, W. McCalla, and B. Rosario. The services of
the Computer Center of the Berkeley Campus of the
University are gratefully
acknowledged.
We thank
D. McDaniel for her assistance in the preparation of the
IC chip samples for device and stage characterizations.
Finally, we express our gratitude to D. Fullager and
Intersil, Inc., for making the 8741 IC available to us.
it

REFERENCES
[11 D. Fullager~ A new high performance monolithic operational amphtier, Fairchild Semiconductor, Tech. Paper.
[21 R. J. Widlar, A new monolithic operational amplifier design, National Semiconductorj Tech. Paper TP-2, June 1967.
[31 J. E. Solomon, W. R. Davis, and P. L. Lee, (A self-compensated monolithic operational amplifier with low input current and high slew rate, 1.969188CC Digest Tech. Papersl
vol. 12, pp. 1415.
[41 W. E. Hearn, Fast slewing monolithic operational amplifier,
IEEE J. Solid-State Circuits, vol. SC-6, Feb. 1971, pp. 20-24.
[51 W. R. Harden and M. J. Hellstrom, A triple-channel micronower operational amplifier. IEEE J. Solid-State Circuits.
iol. SC-~, Aug. 1970, Pp. 236240.
[61 R. J. Widlar. Desigm techniques for monolithic operational
amplifiers, IEEE J. Solid-State Circuits, vol. SC-4, Aug.
1969, pp. 184-191.
[71 T. E. Idleman, F. S. Jenkins, W. J. McCalla, and D. O.
Pederson, %LIC-A
simulator for linear integrated circuits, IEEE J. Solid-State Circuits, vol. SC-6, Aug. 1971,

PP. 188-203.

[81 L. Nagel and R. Rohrer{ (Computer analysisof nonlinear

circuits, excluding radiation (CANCER) , IEEE J. SolidState Circuits, vol. SC-6, Aug. 1971, pp. 166-182.
[91 W. J. McCalla and W. G. Howard? Jr., BIAS-3-A program
for the nonlinear dc analysis of bipolar transistor circuits.
IEEE J. Solid-State Circuzts, vol. SC-6, Feb. 1971, pp. 14-19.
nonlinear de and
[ 101 F. S. Jenkins and S.-P. Fan? TIME-A
time-domain circuit simulation program, IEEE J. SolidState Circuits, vol. SC-6, Aug. 1971,pp. 182-188.
[111 C. L. Searle et al., Elementary Cwcuit Properties of Transister.sj vol. 3. New York: Wiley, 1964.
[121 S. L. Chou, An investigation of lateral t~ansistors: I dc
characteristics; II small-signal characteristics, Solid-State
Electron., to be published.
[131 B. Polata, Compatible high performance complementary
bipolar transistors for integrated circuits, presented at
the 1969 Int. Device Electronics Meeting, Washington, D. C.

* 15-V Monolithic Voltage Regulator

WILLIAM

AbstractA five-terminal ~ 15-V monolithic voltage regulator

has been developed that incorporate internal frequency compensation and internally provides a &I percent output voltage tolerance.
In addition, a thermally symmetric layout design of the chip hae
been used to eliminate the detrimental effects of thermal feedback
Manuscript received May 26, 1971; revised August 9, 1971.
The author is with the Semiconductor Products Division, Motorola, Inc., Phoenix, Ariz. 85036.

F. DAVIS

on the die and ensure that the complementary tracking output

voltages will be independent of the power dissipation in the seriespass power transistors. Complete fault protection is accomplished
by providing the power transistors with good de safe operating area,
internally limiting the short-circuit output currents, and accurately
limiting the junction temperature to within 10C of the specified
maximum limit. Also, a new Zener-diode geometry is employed
that significantly reduces the noise associated with the reference
voltage. Other features include a maximum input voltage of *4O V,