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DATABOOK
Revision
: 1.4
Technology : SAED90nm
Process
: SAED90nm 1P9M 1.2v / 2.5v
Rev. 1.4
Page 1 of 100
Introduction .......................................................................................................................... 11
General Information ............................................................................................................. 11
Operating conditions ............................................................................................................ 16
Input signal slope, standard load and drive strengths .......................................................... 16
AC Characteristics ............................................................................................................... 17
5.1. Characterization corners .................................................................................................. 17
5.2. The values of Output Load and Input Slope ..................................................................... 19
6. Digital Standard Library Cells List ........................................................................................ 19
7. Digital Standard Cell Library Deliverables ............................................................................ 26
8. Physical structure of digital cell ............................................................................................ 26
9. Descriptions of Digital Standard Cells .................................................................................. 30
10. Revision history ................................................................................................................. 100
Rev. 1.4
Page 2 of 100
Rev. 1.4
Page 3 of 100
Rev. 1.4
Page 4 of 100
Rev. 1.4
Page 5 of 100
Rev. 1.4
Page 6 of 100
Rev. 1.4
Page 7 of 100
Rev. 1.4
Page 8 of 100
Rev. 1.4
Page 9 of 100
Rev. 1.4
Page 10 of 100
1. Introduction
This Databook describes possibilities, peculiarities of SAED_EDK90_CORE Digital Standard
Cell Library and technical parameters of separate cells included in it. The library is free from
intellectual property restrictions. It is one of the components of SAED_EDK90 Educational
Design Kit (EDK). SAED_EDK90 EDK is anticipated for the use of educational purposes aimed
at training highly qualified specialists in the area of microelectronics in:
SYNOPSYS Customer Education Services
Universities included in SYNOPSYS University Program
SAED_EDK90 is foreseen to support the trainees to better master:
Advanced design methodologies
Capabilities of SYNOPSYS tools.
For the use of EDK it is assumed that European or North American bundle of SYNOPSYS EDA
tools is available to trainees.
SAED_EDK90_CORE Digital Standard Cell Library is anticipated for designing different
integrated circuits (ICs) by the application of 90nm technology and SYNOPSYS EDA tools.
The SAED_EDK90_CORE Digital Standard Cell Library has been built using SAED90nm 1P9M
1.2V/2.5V design rules. The library has been created aimed at optimizing the main
characteristics of designed ICs by its help. The library includes typical miscellaneous
combinational and sequential logic cells for different drive strengths. Besides, the library
contains all the cells which are required for different styles of low power (multi-voltage,
multi-threshold)
designs
(www.synopsys.com/products/power/multivoltage_bkgrd.pdf,
www.synopsys.com/sps/pdf/optimum_sleep_transistor_vlsi_dat06.pdf). Those are the following:
Isolation Cells, Level Shifters, Retention Flip-Flops, Always-on Buffers and Power Gating Cells.
The presence of all these cells provides the support of IC design with different core voltages to
minimize dynamic and leakage power.
2. General Information
The used symbols of logic elements states are shown in Table 2.1.
Table 2.1. Symbols of logic elements states
Symbol
State
L (0)
H (1)
High-impedance State
LH (01)
HL (10)
Rev. 1.4
Page 11 of 100
Parameter
Unit
Symbol
Figure
VOUT
V DD
Voltage
Transfer
Characteristic
-
DC functional dependence
between input and output
voltages.
VTC
0
2
VDD
VOUT
VDD
Output high
level voltage
(nominal)
V
VOHN=VDD
VDD
VIN
VOUT
VDD
Output low
level voltage
(nominal)
V
VOLN=0
(VOLN=VSS)
V OLN= 0
0
4
V IN
V OHN =VDD
Definition
V DD
V IN
VOUT
V DD
Switching point
voltage
VSP
V SP
swp
Output high
level minimum
voltage
VOUT
V DD
V OHMIN
V
V SP V DD V IN
Highest output voltage at
slope= -1.
slope=-1
VOHMIN
0
VDD
V IN
Rev. 1.4
Page 12 of 100
Parameter
Unit
Symbol
Output low
level maximum
voltage
Figure
Definition
Lowest output voltage at
slope= -1
VOUT
V DD
V
VOLMAX
V OLMAX
slope=-1
0
7
V OUT
V DD
Input minimum
high
voltage
V
VIHMINVDD V IN
High state
noise
margin
V
slope=-1
V OHMIN
VILMAX
10
slope=- 1
VOUT
VDD
Input maximum
low
voltage
V
VIHMIN
V OMAX
8
VDD
NMH=
=VOHMINVIHMIN
V ILMAX V DD
NMH
Voltage
Undefined
V IN
V DD
V OHMIN
V IHMIN
VILMAX
NML=
=VILMAXVOLMAX
Voltage
Undefined
NML
VIHMIN
V ILMAX
V OLMAX
11
12
Static leakage
current
consumption at
output on high
state
Leakage power
consumption
(dissipation) at
output
uA
ILEAKH
None
uA
ILEAKL
None
pW
pW
PLEAKH=
=VDD x ILEAKH
PLEAKL=
=VDD x ILEAKL
None
None
Rev. 1.4
Page 13 of 100
Parameter
Unit
Symbol
Figure
Rise
transition
time
V DD
0.9VDD
ns
Definition
tR
0.1VDD
tR
V SS
2
VDD
Fall transition
time
ns
0.9VDD
tF
0.1VDD
VSS
tF
3
Propagation
delay
low-to-high
(Rise
propagation)
IN
0.5VDD
tPLH
(tPR)
ns
OUT
0.5VDD
t PLH
4
Propagation
delay
high-to-low
(Fall
propagation)
IN
0.5VDD
tPHL
(tPF)
ns
OUT
t PHL
5
Average
supply
current
Supply peak
current
Dynamic
power
dissipation
uA
uA
pW
Power-delay
product
nJ
Energy-delay
product
nJs
T
IV ( t )dt
AVG
DD
0 DD
IV
IVDDPEAK=
=max(IVDD(t))
t[0;T]
PDISDYN=
=IVDDAVG x
VDD
PD=PDISDYN x
x max
(tPHL,tPLH)
ED=PD x
x
max(tPHL,tPLH)
None
None
None
None
None
0.5VDD
Rev. 1.4
Page 14 of 100
11
12
13
Parameter
Switching fall
power
Switching rise
power
Minimum
clock pulse
(only for flipflops or
latches)
Setup time
(only for flipflops or
latches)
Unit
nJ
nJ
Symbol
Figure
PSWF =
=(CLOAD+COUT
F) x
2
x VDD /2
PSWR=
=(CLOAD+COUT
R) x
2
x VDD /2
Definition
The energy dissipated on a
fall transition. (COUTF is the
output fall capacitance)
None
None
DATA
ns
tPWH (tPWL)
CLOCK
t PWH
OUT
0.5VDD
DATA
ns
t SU
tSU
0.5VDD
CLOCK
14
Hold time
(only for flipflops or
latches)
0.5VDD
ns
tH
0.5VDD
tH
CLOCK
15
16
17
18
Clock-tooutput time
(only for flipflops or
latches)
Removal time
(only for flipflops or
latches with
asynchronous
Set or Reset).
Recovery time
(only for flipflops and
latches with
asynchronous
Set or Reset)
From high to
Z-state entry
time, (only for
tri-state output
cells)
DATA
DATA
ns
tCLKQ
CLOCK
OUT
0.5VDD
0.5VDD
SET (RESET)
ns
tREM
t CLKQ
0.5VDD
0.5VDD
CLOCK
t REM
0.5V DD
SET (RESET)
ns
ns
tREC
0.5VDD
CLOCK
tHZ
t REC
None
Rev. 1.4
Page 15 of 100
20
21
22
23
Parameter
From low to Zstate entry
time, (only for
tri-state output
cells)
From Z to
high-state exit
time
(only for tristate output
cells)
From Z to lowstate exit time
(only for tristate output
cells)
Input pin
capacitance
Maximum
capacitance
Unit
Symbol
ns
ns
Figure
tLZ
Definition
The amount of time that
takes the output to change
from low to Z-state after
control signal is applied
None
tZH
None
ns
tZL
None
pF
CIN
None
pF
CMAX
None
3. Operating conditions
SAED_EDK90_CORE Digital Standard Cell Library is anticipated for 1.2V operation. The used
process technology is SAED90nm 1P9M 1.2V/2.5V, but only the 1P1M option is used.
The operating conditions of SAED_EDK90_CORE Digital Standard Cell Library are shown in
Table 3.1.
Table 3.1. Operating conditions
Parameter
Min
Typ
Max
Units
0.7
-40
-
1.2
+25
300
1.32
+125
-
V
C
MHz
Rev. 1.4
Page 16 of 100
Cell Load
X0
X1
X2
X3
X4
X8
X12
X16
X24
X32
0.5x Csl
1x Csl
2x Csl
3x Csl
4x Csl
8x Csl
12x Csl
16x Csl
24x Csl
32x Csl
5. AC Characteristics
5.1. Characterization corners
Composite Current Source (CCS) modeling technology has been applied for characterization to
meet the contemporary methods of low power design. The application of that technology
supports timing, noise, and power analyses simultaneously with consideration of the relevant
nanometer dependencies. It allows meeting the requirements of variation-aware analysis.
The characterization results are given for 12 process/voltage/temperature (PVT) conditions
shown in Table 5.1.
Table 5.1. Characterization Corners
Corner
Name
TTNT1p20v
TTHT1p20v
TTLT1p20v
SSNT1p08v
SSHT1p08v
SSLT1p08v
FFNT1p32v
FFHT1p32v
FFLT1p32v
TTNT0p08v
TTHT0p08v
TTLT0p08v
SSNT0p07v
SSHT0p07v
SSLT0p07v
FFNT0p09v
FFHT0p09v
FFLT0p09v
Process
(NMOS proc. PMOS proc.)
Temperature
(0C)
Power
Supply (V)
Typical - Typical
25
1.2
Typical - Typical
125
1.2
Typical - Typical
-40
1.2
Slow - Slow
25
1.08
Slow - Slow
125
1.08
Slow - Slow
-40
1.08
Fast - Fast
25
1.32
Fast - Fast
125
1.32
Fast - Fast
-40
1.32
Low Voltage Operating Conditions
Typical - Typical
25
0.8
Typical - Typical
125
0.8
Typical - Typical
-40
0.8
Slow - Slow
25
0.7
Slow - Slow
125
0.7
Slow - Slow
-40
0.7
Fast - Fast
25
0.9
Fast - Fast
125
0.9
Fast - Fast
-40
0.9
Rev. 1.4
Notes
Typical corner
Typical corner
Typical corner
Slow corner
Slow corner
Slow corner
Fast corner
Fast corner
Fast corner
Typical corner
Typical corner
Typical corner
Slow corner
Slow corner
Slow corner
Fast corner
Fast corner
Fast corner
Page 17 of 100
Process
(NMOS proc. PMOS proc.)
Temperature
(0C)
Fast - Slow
125
Fast - Slow
-40
Fast - Slow
125
Fast - Slow
-40
Slow - Fast
125
Slow - Fast
-40
Slow - Fast
125
Slow - Fast
-40
Low Voltage Operating Conditions
Fast - Slow
125
Fast - Slow
-40
Fast - Slow
125
Fast - Slow
-40
Slow - Fast
125
Slow - Fast
-40
Slow - Fast
125
Slow - Fast
-40
Rev. 1.4
Power
Supply (V)
1.08
1.08
1.32
1.32
1.08
1.08
1.32
1.32
0.7
0.7
0.9
0.9
0.7
0.7
0.9
0.9
Page 18 of 100
Value
0
0.2*Tisl
0.5*Csl
0.4*Tisl
1*Csl
0.8*Tisl
2*Csl
1.6*Tisl
4*Csl
3.2*Tisl
8*Csl
6.4*Tisl
16*Csl
12.8*Tisl
The calculation of Setup/Hold times has been realized for 3 different values of Data and Input
Slopes shown in Table 5.4.
Table 5.4. The used values for calculating Setup/Hold Times
Parameter
0.5*Tisl
0.5*Tisl
1*Tisl
1*Tisl
5*Tisl
5*Tisl
Cell Description
Cell Name
Inverters, Buffers
Inverter
Inverter
Inverter
Inverter
Inverter
Inverter
Inverter
Inverting Buffer
Inverting Buffer
Inverting Buffer
Inverting Buffer
Inverting Buffer
Non-inverting Buffer
Non-inverting Buffer
Non-inverting Buffer
Non-inverting Buffer
Non-inverting Buffer
Tri-state Non-inverting Buffer w/ High-Active Enable
INVX0
INVX1
INVX2
INVX4
INVX8
INVX16
INVX32
IBUFFX2
IBUFFX4
IBUFFX8
IBUFFX16
IBUFFX32
NBUFFX2
NBUFFX4
NBUFFX8
NBUFFX16
NBUFFX32
TNBUFFX1
Rev. 1.4
Page 19 of 100
Cell Description
Cell Name
TNBUFFX2
TNBUFFX4
TNBUFFX8
TNBUFFX16
TNBUFFX32
AND2X1
AND2X2
AND2X4
AND3X1
AND3X2
AND3X4
AND4X1
AND4X2
AND4X4
NAND2X0
NAND2X1
NAND2X2
NAND2X4
NAND3X0
NAND3X1
NAND3X2
NAND3X4
NAND4X0
NAND4X1
OR2X1
OR2X2
OR2X4
OR3X1
OR3X2
OR3X4
OR4X1
OR4X2
OR4X4
NOR2X0
NOR2X1
NOR2X2
NOR2X4
NOR3X0
NOR3X1
NOR3X2
NOR3X4
Rev. 1.4
Page 20 of 100
Cell Description
Cell Name
NOR 4-input
NOR 4-input
XOR 2-input
XOR 2-input
XOR 3-input
XOR 3-input
XNOR 2-input
XNOR 2-input
XNOR 3-input
XNOR 3-input
Complex Logic Gates
AND-OR 2/1
AND-OR 2/1
AND-OR 2/2
AND-OR 2/2
AND-OR 2/2/1
AND-OR 2/2/1
AND-OR 2/2/2
AND-OR 2/2/2
AND-OR-Invert 2/1
AND-OR Invert 2/1
AND-OR-Invert 2/2
AND-OR-Invert 2/2
AND-OR-Invert 2/2/1
AND-OR-Invert 2/2/1
AND-OR-Invert 2/2/2
AND-OR-Invert 2/2/2
OR-AND 2/1
OR-AND 2/1
OR-AND 2/2
OR-AND 2/2
OR-AND 2/2/1
OR-AND 2/2/1
OR-AND 2/2/2
OR-AND 2/2/2
OR-AND-Invert 2/1
OR-AND-Invert 2/1
OR-AND-Invert 2/2
OR-AND-Invert 2/2
OR-AND-Invert 2/2/1
OR-AND-Invert 2/2/1
OR-AND-Invert 2/2/2
NOR4X0
NOR4X1
XOR2X1
XOR2X2
XOR3X1
XOR3X2
XNOR2X1
XNOR2X2
XNOR3X1
XNOR3X2
AO21X1
AO21X2
AO22X1
AO22X2
AO221X1
AO221X2
AO222X1
AO222X2
AOI21X1
AOI21X2
AOI22X1
AOI22X2
AOI221X1
AOI221X2
AOI222X1
AOI222X2
OA21X1
OA21X2
OA22X1
OA22X2
OA221X1
OA221X2
OA222X1
OA222X2
OAI21X1
OAI21X2
OAI22X1
OAI22X2
OAI221X1
OAI221X2
OAI222X1
Rev. 1.4
Page 21 of 100
Cell Description
Cell Name
OR-AND-Invert 2/2/2
Multiplexers
Multiplexer 2 to 1
Multiplexer 2 to 1
Multiplexer 4 to 1
Multiplexer 4 to 1
Decoders
Decoder 2 to 4
Decoder 2 to 4
Adders and Subtractors
Half Adder 1 bit
Half Adder 1 bit
Full Adder 1 bit
Full Adder 1 bit
D Flip-Flops
Pos Edge DFF
Pos Edge DFF
Pos Edge DFF, w/ Async Low-Active Set
Pos Edge DFF, w/ Async Low-Active Set
Pos Edge DFF, w/ Async Low-Active Reset
Pos Edge DFF, w/ Async Low-Active Reset
Pos Edge DFF, w/ Async Low-Active Set & Reset
Pos Edge DFF, w/ Async Low-Active Set & Reset
Pos Edge DFF, w/ Sync Low-Active Set & Reset
Pos Edge DFF, w/ Sync Low-Active Set & Reset
Neg Edge DFF
Neg Edge DFF
Neg Edge DFF, w/ Async Low-Active Set
Neg Edge DFF, w/ Async Low-Active Set
Neg Edge DFF, w/ Async Low-Active Reset
Neg Edge DFF, w/ Async Low-Active Reset
Neg Edge DFF, w/ Async Low-Active Set & Reset
Neg Edge DFF, w/ Async Low-Active Set & Reset
Neg Edge DFF, w/ Async Low-Active Set & Reset, Only Q out
Neg Edge DFF, w/ Async Low-Active Set & Reset, Only Q out
Neg Edge DFF, w/ Async Low-Active Set & Reset, Only QN out
Neg Edge DFF, w/ Async Low-Active Set & Reset, Only QN out
Scan D Flip-Flops
Scan Pos Edge DFF
Scan Pos Edge DFF
Scan Pos Edge DFF w/ Async Low-Active Set
Scan Pos Edge DFF w/ Async Low-Active Set
Rev. 1.4
OAI222X2
MUX21X1
MUX21X2
MUX41X1
MUX41X2
DEC24X1
DEC24X2
HADDX1
HADDX2
FADDX1
FADDX2
DFFX1
DFFX2
DFFASX1
DFFASX2
DFFARX1
DFFARX2
DFFASRX1
DFFASRX2
DFFSSRX1
DFFSSRX2
DFFNX1
DFFNX2
DFFNASX1
DFFNASX2
DFFNARX1
DFFNARX2
DFFNASRX1
DFFNASRX2
DFFNASRQX1
DFFNASRQX2
DFFNASRNX1
DFFNASRNX2
SDFFX1
SDFFX2
SDFFASX1
SDFFASX2
Page 22 of 100
Cell Description
Cell Name
Rev. 1.4
SDFFARX1
SDFFARX2
SDFFASRX1
SDFFASRX2
SDFFASRSX1
SDFFASRSX2
SDFFSSRX1
SDFFSSRX2
SDFFNX1
SDFFNX2
SDFFNASX1
SDFFNASX2
SDFFNARX1
SDFFNARX2
SDFFNASRX1
SDFFNASRX2
LNANDX1
LNANDX2
LATCHX1
LATCHX2
LASX1
LASX2
LARX1
LARX2
LASRX1
LASRX2
LASRQX1
LASRQX2
LASRNX1
LASRNX2
CGLPPSX2
CGLPPSX4
CGLPPSX8
CGLPPSX16
CGLNPSX2
CGLNPSX4
CGLNPSX8
CGLNPSX16
CGLPPRX2
CGLPPRX8
Page 23 of 100
Cell Description
Cell Name
CGLNPRX2
CGLNPRX8
DELLN1X2
DELLN2X2
DELLN3X2
PGX1
PGX2
PGX4
BSLEX1
BSLEX2
BSLEX4
ISOLANDX1
ISOLANDX2
ISOLANDX4
ISOLANDX8
ISOLORX1
ISOLORX2
ISOLORX4
ISOLORX8
LSUPX1
LSUPX2
LSUPX4
LSUPX8
LSDNX1
LSDNX2
LSDNX4
LSDNX8
LSUPENX1
LSUPENX2
LSUPENX4
LSUPENX8
LSDNENX1
LSDNENX2
LSDNENX4
LSDNENX8
RDFFX1
Rev. 1.4
Page 24 of 100
Cell Description
Cell Name
Rev. 1.4
RDFFX2
RSDFFX1
RSDFFX2
RDFFNX1
RDFFNX2
RSDFFNX1
RSDFFNX2
HEADX2
HEADX4
HEADX8
HEADX16
HEADX32
AOINVX1
AOINVX2
AOINVX4
AOBUFX1
AOBUFX2
AOBUFX4
AODFFARX1
AODFFARX2
AODFFNARX1
AODFFNARX2
BUSKP
PMT1
PMT2
PMT3
NMT1
NMT2
NMT3
TIEH
TIEL
ANTENNA
DCAP
CLOAD1
SHFILL2
DHFILLHLH2
DHFILLLHL2
DHFILLHLHLS11
Page 25 of 100
N
1
2
3
4
5
6
7
8
9
10
11
12
Type
Description
.doc, .txt
.sdb, .slib
.db, .lib
.v
.vhd
.sp
.rcx
.gds
.drc, .lvs, .erc
.lef
.fram, .cel
.plib
W4
W2
W3
W1
VSS
Rev. 1.4
Page 26 of 100
W2
W3
VDDG
H
W4
W1
VDD
W4
W2
W3
H
VDDG
W1
VSS
Figure 8.2. Physical structure of double height (low-high-low) digital standard cells (for Always
on Cells)
Rev. 1.4
Page 27 of 100
W5
W4
W2
W3
W1
VSS
W2
W3
H
W4
W1
VDDH
Figure 8.3. Physical structure of double height (high-low-high) digital standard cells (for LevelShifter cells: Low-High
Rev. 1.4
Page 28 of 100
W4
W2
W3
W1
VSS
Figure 8.4. Physical structure of single height digital standard cells (for Level-shifter cells:
High-Low)
VDD
W1
VDDG
W2
W4
H
W3
W1
VSS
Figure 8.5. Physical structure of single height digital standard cells (for Retention Flip-Flops and
scan Flip-Flops)
Rev. 1.4
Page 29 of 100
Symbol
Value
Cell height
Power rail width
Vertical grid
Horizontal grid
NWell height
VDDH to VDDL height (Fig. 8.3)
H
W1
W2
W3
W4
W5
2.88 um
0.16 um
0.32 um
0.32 um
1.68 um
0.72 um
dtrack is the minimum center-to-center distance for metal2 layers (with VIA12
d1
d2
Minimum spacing
Minimum width
dtrack=d1+d2
Figure 8.6. Definition of dtrack
IN
QN
Rev. 1.4
Page 30 of 100
QN
0
1
1
0
Cload
ps
INVX1
INVX8
INVX32
1 x Csl
8 x Csl
32 x Csl
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
38
39
41
Area
Dynamic
88
582
2510
nW/MHz
(um )
12
78
358
6.4512
14.7456
47.0016
QN
Buf
QN
0
1
1
0
IBUFFX2
IBUFFX8
IBUFFX32
2 x Csl
8 x Csl
32 x Csl
98
131
205
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
223
833
3315
Rev. 1.4
Area
Dynamic
2
nW/MHz
(um )
92
339
2090
10.1376
18.4320
56.2176
Page 31 of 100
Buf
0
1
0
1
Cell Name
Cload
NBUFFX2
NBUFFX8
NBUFFX32
2 x Csl
8 x Csl
32 x Csl
77
101
168
201
742
3125
Area
Dynamic
2
nW/MHz
(um )
79
330
1284
5.5296
14.7456
55.2960
IN
Buf
IN
0
0
1
1
0
1
0
1
Z
Z
0
1
Rev. 1.4
Page 32 of 100
Cload
ps
TNBUFFX1
TNBUFFX8
TNBUFFX32
1 x Csl
8 x Csl
32 x Csl
101
141
138
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
450
1110
4100
Area
Dynamic
2
nW/MHz
(um )
63
337
3672
13.8240
23.9616
68.1984
AND: AND2X1, AND2X2, AND2X4, AND3X1, AND3X2, AND3X4, AND4X1, AND4X2, AND4X4
IN1
Q
INn
IN2
...
INn
0
X
...
X
1
X
0
...
X
1
...
...
...
...
1
X
X
...
0
1
0
0
0
0
1
AND2X1
AND2X2
AND3X1
AND3X2
AND4X1
AND4X2
1 x Csl
2 x Csl
1 x Csl
2 x Csl
1 x Csl
2 x Csl
85
96
119
135
129
147
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
298
568
297
562
299
574
Rev. 1.4
Area
Dynamic
2
nW/MHz
(um )
19
36
34
55
42
75
7.3728
8.2944
8.2944
10.1376
10.1376
11.9808
Page 33 of 100
IN2
...
INn
QN
0
X
...
X
1
X
0
...
X
1
...
...
...
...
1
X
X
...
0
1
1
1
1
1
0
NAND2X1
NAND2X2
NAND3X1
NAND3X2
NAND4X0
NAND4X1
1 x Csl
2 x Csl
1 x Csl
2 x Csl
0.5 x Csl
1 x Csl
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
51
51
130
142
66
127
336
673
492
770
400
716
Area
Dynamic
2
nW/MHz
(um )
15
28
38
59
22
57
5.5296
9.2160
11.9808
12.9024
8.2944
12.9024
OR: OR2X1, OR2X2, OR2X4, OR3X1, OR3X2, OR3X4, OR4X1, OR4X2, OR4X4
IN1
Q
INn
Rev. 1.4
Page 34 of 100
IN2
...
INn
0
1
...
X
X
0
X
...
1
X
...
...
...
...
X
0
X
...
X
1
0
1
1
1
1
Cload
ps
OR2X1
OR2X2
OR3X1
OR3X2
OR4X1
OR4X2
1 x Csl
2 x Csl
1 x Csl
2 x Csl
1 x Csl
2 x Csl
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
85
94
114
121
137
153
226
409
250
435
261
449
Area
Dynamic
2
nW/MHz
(um )
23
37
39
62
56
93
7.3728
9.2160
9.2160
11.0592
10.1376
11.9808
IN2
...
INn
QN
0
1
...
X
X
0
X
...
1
X
...
...
...
...
X
0
X
...
X
1
1
0
0
0
0
Rev. 1.4
Page 35 of 100
Cload
ps
NOR2X1
NOR2X2
NOR3X1
NOR3X2
NOR4X0
NOR4X1
1 x Csl
2 x Csl
1 x Csl
2 x Csl
0.5 x Csl
1 x Csl
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
64
66
136
147
95
124
170
340
374
558
168
414
Area
Dynamic
2
nW/MHz
(um )
15
29
45
67
27
50
6.4512
9.2160
11.9808
13.8240
9.2160
15.6672
IN2
...
INn
0
...
0
Odd number of 1s
Even number of 1s
0
1
0
XOR2X1
XOR2X2
XOR3X1
XOR3X2
1 x Csl
2 x Csl
1 x Csl
2 x Csl
133
144
218
253
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
454
723
852
1154
Rev. 1.4
Area
Dynamic
2
nW/MHz
(um )
26
37
77
127
13.8240
15.6672
22.1184
23.9616
Page 36 of 100
IN2
...
INn
QN
0
...
0
Odd number of 1s
Even number of 1s
1
0
1
Cload
ps
XNOR2X1
XNOR2X2
XNOR3X1
XNOR3X2
1 x Csl
2 x Csl
1 x Csl
2 x Csl
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
136
151
229
252
933
706
909
1196
Area
Dynamic
2
nW/MHz
(um )
25
9
81
94
13.8240
15.6672
22.1184
23.9616
IN2
IN3
1
X
0
X
1
X
X
0
X
1
0
0
1
1
0
0
Rev. 1.4
Page 37 of 100
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
Cload
ps
AO21X1
AO21X2
1 x Csl
2 x Csl
109
131
322
595
Area
Dynamic
2
nW/MHz
(um )
35
67
10.1376
11.9808
IN4
IN2
IN3
IN4
X
1
0
X
0
X
X
1
X
0
X
0
1
X
0
0
X
X
1
X
X
X
0
0
1
1
0
0
0
0
Cload
ps
AO22X1
AO22X2
1 x Csl
2 x Csl
119
141
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
333
608
Rev. 1.4
Area
Dynamic
2
nW/MHz
(um )
42
80
11.9808
12.9024
Page 38 of 100
IN3
IN4
IN5
IN2
IN3
IN4
IN5
1
X
X
0
X
0
X
1
X
X
X
0
X
0
X
1
X
0
0
X
X
X
1
X
X
X
0
0
X
X
1
0
0
0
0
1
1
1
0
0
0
0
Cload
ps
AO221X1
AO221X2
1 x Csl
2 x Csl
150
168
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
353
629
Rev. 1.4
Area
Dynamic
2
nW/MHz
(um )
53
89
12.9024
14.7456
Page 39 of 100
Q
IN4
IN5
IN6
IN2
IN3
IN4
IN5
IN6
1
X
X
0
1
X
X
0
X
1
X
0
X
1
X
0
X
X
1
0
X
X
1
0
1
1
1
0
Cload
ps
AO222X1
AO222X2
1 x Csl
2 x Csl
162
176
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
Area
Dynamic
2
nW/MHz
(um )
53
85
14.7456
15.6672
365
642
QN
IN3
Rev. 1.4
Page 40 of 100
IN2
IN3
QN
1
X
0
X
1
X
X
0
X
1
0
0
0
0
1
1
Cload
ps
AOI21X1
AOI21X2
1 x Csl
2 x Csl
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
136
146
Area
Dynamic
2
nW/MHz
(um )
47
72
11.9808
12.9024
437
708
QN
IN4
IN2
IN3
IN4
QN
X
1
0
X
0
X
X
1
X
0
X
0
1
X
0
0
X
X
1
X
X
X
0
0
0
0
1
1
1
1
Rev. 1.4
Page 41 of 100
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
Cload
ps
AOI22X1
AOI22X2
1 x Csl
2 x Csl
154
175
Area
Dynamic
2
nW/MHz
(um )
45
71
12.9024
14.7456
435
708
QN
IN3
IN4
IN5
IN2
IN3
IN4
IN5
QN
1
X
X
0
X
0
X
1
X
X
X
0
X
0
X
1
X
0
0
X
X
X
1
X
X
X
0
0
X
X
1
0
0
0
0
0
0
0
1
1
1
1
Rev. 1.4
Page 42 of 100
Cload
ps
AOI221X1
AOI221X2
1 x Csl
2 x Csl
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
183
192
Area
Dynamic
2
nW/MHz
(um )
57
81
14.7456
15.6672
507
779
IN2
IN3
IN4
IN5
IN6
QN
1
X
X
0
1
X
X
0
X
1
X
0
X
1
X
0
X
X
1
0
X
X
1
0
0
0
0
1
Cload
ps
AOI222X1
AOI222X2
1 x Csl
2 x Csl
182
199
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
527
799
Rev. 1.4
Area
Dynamic
2
nW/MHz
(um )
57
79
15.6672
17.5104
Page 43 of 100
IN3
IN2
IN3
0
X
1
X
0
X
X
1
X
0
1
1
0
0
1
1
Cload
ps
OA21X1
OA21X2
1 x Csl
2 x Csl
118
120
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
302
584
Area
Dynamic
2
nW/MHz
(um )
34
62
9.2160
11.0592
IN3
IN4
Rev. 1.4
Page 44 of 100
IN2
IN3
IN4
0
X
1
X
1
X
0
X
X
1
X
1
X
0
1
1
X
X
X
0
X
X
1
1
0
0
1
1
1
1
Cload
ps
OA22X1
OA22X2
1 x Csl
2 x Csl
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
115
130
332
606
Area
Dynamic
2
nW/MHz
(um )
45
74
11.0592
12.9024
IN3
IN4
IN5
IN2
IN3
IN4
IN5
0
X
X
1
X
1
X
0
X
X
X
1
X
1
X
0
X
1
1
X
X
X
0
X
X
X
1
1
X
X
0
1
1
1
1
0
0
0
1
1
1
1
Rev. 1.4
Page 45 of 100
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
Cload
ps
OA221X1
OA221X2
1 x Csl
2 x Csl
145
164
350
590
Area
Dynamic
2
nW/MHz
(um )
53
90
12.9024
14.7456
IN2
IN3
IN4
IN5
IN6
0
X
X
1
1
1
1
X
X
X
X
0
X
X
X
X
X
X
1
1
1
1
X
0
X
1
1
X
X
1
1
X
X
X
0
X
X
X
1
1
X
X
1
1
X
X
0
1
X
1
X
1
X
1
X
X
X
0
X
1
X
1
X
1
X
1
0
0
0
1
1
1
1
1
1
1
1
Rev. 1.4
Page 46 of 100
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
Cload
ps
OA222X1
OA222X2
1 x Csl
2 x Csl
168
192
Area
Dynamic
2
nW/MHz
(um )
59
102
14.7456
15.6672
375
608
QN
IN3
IN2
IN3
QN
0
X
1
X
0
X
X
1
X
0
1
1
1
1
0
0
Cload
ps
OAI21X1
OAI21X2
1 x Csl
2 x Csl
138
148
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
443
715
Rev. 1.4
Area
Dynamic
2
nW/MHz
(um )
48
72
11.0592
11.9808
Page 47 of 100
QN
IN3
IN4
IN2
IN3
IN4
QN
0
X
1
X
1
X
0
X
X
1
X
1
X
0
1
1
X
X
X
0
X
X
1
1
1
1
0
0
0
0
Cload
ps
OAI22X1
OAI22X2
1 x Csl
2 x Csl
159
169
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
498
770
Area
Dynamic
2
nW/MHz
(um )
50
77
12.9024
13.8240
QN
IN3
IN4
IN5
Rev. 1.4
Page 48 of 100
IN2
IN3
IN4
IN5
QN
0
X
X
1
X
1
X
0
X
X
X
1
X
1
X
0
X
1
1
X
X
X
0
X
X
X
1
1
X
X
0
1
1
1
1
1
1
1
0
0
0
0
Cload
ps
OAI221X1
OAI221X2
1 x Csl
2 x Csl
194
210
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
499
771
Area
Dynamic
2
nW/MHz
(um )
57
88
14.7456
15.6672
Rev. 1.4
Page 49 of 100
IN2
IN3
IN4
IN5
IN6
QN
0
X
X
1
1
1
1
X
X
X
X
0
X
X
X
X
X
X
1
1
1
1
X
0
X
1
1
X
X
1
1
X
X
X
0
X
X
X
1
1
X
X
1
1
X
X
0
1
X
1
X
1
X
1
X
X
X
0
X
1
X
1
X
1
X
1
1
1
1
0
0
0
0
0
0
0
0
Cload
ps
OAI222X1
OAI222X2
1 x Csl
2 x Csl
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
235
252
475
737
Area
Dynamic
2
nW/MHz
(um )
62
93
15.6672
17.5104
Q
IN2
S
0
1
IN1
IN2
Rev. 1.4
Page 50 of 100
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
Cload
ps
MUX21X1
MUX21X2
1 x Csl
2 x Csl
107
120
815
881
Area
Dynamic
2
nW/MHz
(um )
43
70
11.0592
12.9024
S1
S0
0
0
1
1
0
1
0
1
IN1
IN2
IN3
IN4
Cload
ps
MUX41X1
MUX41X2
1 x Csl
2 x Csl
168
189
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
827
1138
Rev. 1.4
Area
Dynamic
2
nW/MHz
(um )
58
98
23.0400
24.8832
Page 51 of 100
Q2
IN1
Q1
Q0
IN1
Q0
Q1
Q2
Q3
0
0
1
1
0
1
0
1
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
Output
DEC24X1
1 x Csl
DEC24X1
2 x Csl
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
119
119
83
79
156
154
117
115
Area
Dynamic
2
nW/MHz
(um )
1238
66
29.4912
2112
161
36.8640
B0
S0
C1
Rev. 1.4
Page 52 of 100
B0
S0 (sum)
C1 (carry)
0
0
1
1
0
1
0
1
0
1
1
0
0
0
0
1
Output
HADDX1
1 x Csl
HADDX2
2 x Csl
S0
C1
S0
C1
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
98
125
107
130
Area
Dynamic
2
nW/MHz
(um )
645
65
15.6672
1188
106
18.4320
CO
B
CI
CI
S (sum)
CO (carry)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
0
0
1
0
1
1
1
Rev. 1.4
Page 53 of 100
Output
FADDX1
1 x Csl
FADDX2
2 x Csl
S
CO
S
CO
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
166
125
185
138
Area
Dynamic
2
nW/MHz
(um )
31
105
29.4912
56
165
31.3344
CLK
QN
CLK
QN
X
1
0
Inactive
Rise
Rise
No change
1
0
No change
0
1
Output
DFFX1
1 x Csl
DFFX2
2 x Csl
Q
QN
Q
QN
213
167
253
179
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
Area
Dynamic
2
nW/MHz
(um )
670
170
24.8832
1040
330
31.3344
Rev. 1.4
Page 54 of 100
CLK
QN
Figure 9.33. Logic Symbol of Pos Edge DFF w/Async Low-Active Set
Table 9.65. Pos Edge DFF w/Async Low-Active Set Transition Table
D
SETB
CLK
QN
X
X
1
0
0
1
1
1
X
Inactive
Rise
Rise
1
No change
1
0
0
No change
0
1
Table 9.66. Pos Edge DFF w/Async Low-Active Set Electrical Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload
Output
DFFASX1
1 x Csl
DFFASX2
2 x Csl
Q
QN
Q
QN
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
253
204
281
204
Area
Dynamic
2
nW/MHz
(um )
680
120
31.3344
1040
160
34.0992
CLK
QN
RSTB
Figure 9.34. Logic Symbol of Pos Edge DFF w/Async Low-Active Reset
Rev. 1.4
Page 55 of 100
RSTB
CLK
QN
X
X
1
0
0
1
1
1
X
Inactive
Rise
Rise
0
No change
1
0
1
No change
0
1
Table 9.68. Pos Edge DFF w/Async Low-Active Reset Electrical Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload
Output
DFFARX1
1 x Csl
DFFARX2
2 x Csl
Q
QN
Q
QN
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
217
162
264
179
Area
Dynamic
2
nW/MHz
(um )
620
100
32.2560
970
130
34.0992
Pos Edge DFF w/Async Low-Active Set & Reset: DFFASRX1, DFFASRX2
SETB
D
CLK
QN
RSTB
Figure 9.35. Logic Symbol of Pos Edge DFF w/Async Low-Active Set & Reset
Table 9.69. Pos Edge DFF w/Async Low-Active Set & Reset Transition Table
D
SETB
RSTB
CLK
QN
Notes
X
X
X
X
1
0
0
0
1
1
1
1
0
1
0
1
1
1
X
X
X
Inactive
Rise
Rise
X
1
0
No change
1
0
X
0
1
No change
0
1
Not Allowed
Rev. 1.4
Page 56 of 100
Output
DFFASRX1
1 x Csl
DFFASRX2
2 x Csl
Q
QN
Q
QN
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
251
190
302
215
Area
Dynamic
2
nW/MHz
(um )
680
80
35.0208
1030
110
36.8640
Pos Edge DFF w/ Sync Low-Active Set & Reset: DFFSSRX1, DFFSSRX2
SETB
D
CLK
QN
RSTB
Figure 9.36. Logic Symbol of Pos Edge DFF w/ Sync Low-Active Set & Reset
Table 9.71. Pos Edge DFF w/ Sync Low-Active Set & Reset Transition Table
D
SETB
RSTB
CLK
QN
Notes
X
0
1
X
X
X
X
1
1
0
1
0
X
1
1
1
0
0
Inactive
Rise
Rise
Rise
Rise
Rise
No change
0
1
1
0
X
No change
1
0
0
1
X
Not Allowed
Rev. 1.4
Page 57 of 100
Output
DFFSSRX1
1 x Csl
DFFSSRX2
2 x Csl
Q
QN
Q
QN
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
208
166
257
191
Area
Dynamic
2
nW/MHz
(um )
950
238
33.1776
1300
396
37.7856
CLK
QN
CLK
QN
X
1
0
Inactive
Fall
Fall
No change
1
0
No change
0
1
Output
DFFNX1
1 x Csl
DFFNX2
2 x Csl
Q
QN
Q
QN
233
189
296
223
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
Area
Dynamic
2
nW/MHz
(um )
805
96
28.5696
1742
154
31.3344
Rev. 1.4
Page 58 of 100
CLK
QN
Figure 9.38. Logic Symbol of Neg Edge DFF w/Async Low-Active Set
Table 9.75. Neg Edge DFF w/Async Low-Active Set Transition Table
D
SETB
CLK
QN
X
X
1
0
0
1
1
1
X
Inactive
Fall
Fall
1
No change
1
0
0
No change
0
1
Table 9.76. Neg Edge DFF w/Async Low-Active Set Electrical Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload
Output
DFFNASX1
1 x Csl
DFFNASX2
2 x Csl
Q
QN
Q
QN
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
298
245
340
256
Area
Dynamic
2
nW/MHz
(um )
640
90
30.4128
1010
150
34.0992
CLK
QN
RSTB
Figure 9.39. Logic Symbol of Neg Edge DFF w/Async Low-Active Reset
Rev. 1.4
Page 59 of 100
RSTB
CLK
QN
X
X
1
0
0
1
1
1
X
Inactive
Fall
Fall
0
No change
1
0
1
No change
0
1
Table 9.78. Neg Edge DFF w/Async Low-Active Reset Electrical Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload
Output
DFFNARX1
1 x Csl
DFFNARX2
2 x Csl
Q
QN
Q
QN
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
268
206
306
208
Area
Dynamic
2
nW/MHz
(um )
626
101
32.2560
999
145
34.0992
Neg Edge DFF w/Async Low-Active Set & Reset: DFFNASRX1, DFFNASRX2
SETB
D
CLK
QN
RSTB
Figure 9.40. Logic Symbol of Neg Edge DFF w/Async Low-Active Set & Reset
Table 9.79. Neg Edge DFF w/Async Low-Active Set & Reset Transition Table
D
SETB
RSTB
CLK
QN
Notes
X
X
X
X
1
0
0
0
1
1
1
1
0
1
0
1
1
1
X
X
X
Inactive
Fall
Fall
X
1
0
No change
1
0
X
0
1
No change
0
1
Not Allowed
Rev. 1.4
Page 60 of 100
Output
DFFNASRX1
1 x Csl
DFFNASRX2
2 x Csl
Q
QN
Q
QN
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
314
248
344
253
Area
Dynamic
2
nW/MHz
(um )
620
103
35.0208
1040
162
36.8640
Neg Edge DFF w/Async Low-Active Set & Reset, Only Q out: DFFNASRQX1, DFFNASRQX2
SETB
D
CLK
RSTB
Figure 9.41. Logic Symbol of Neg Edge DFF w/Async Low-Active Set & Reset, Only Q out
Table 9.81. Neg Edge DFF w/Async Low-Active Set & Reset, Only Q out Transition Table
D
SETB
RSTB
CLK
Notes
X
X
X
X
0
1
0
0
1
1
1
1
0
1
0
1
1
1
X
X
X
Inactive
Fall
Fall
X
1
0
No change
0
1
Not Allowed
Rev. 1.4
Page 61 of 100
Output
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
Area
Dynamic
2
nW/MHz
(um )
DFFNASRQX1
1 x Csl
289
110
67
32.2560
DFFNASRQX2
2 x Csl
256
400
110
34.0992
Neg Edge DFF w/Async Low-Active Set & Reset, Only QN out: DFFNASRNX1, DFFNASRNX2
SETB
CLK
QN
RSTB
Figure 9.42. Logic Symbol of Neg Edge DFF w/Async Low-Active Set & Reset, Only QN out
Table 9.83. Neg Edge DFF w/Async Low-Active Set & Reset, Only QN out Transition Table
D
SETB
RSTB
CLK
QN
Notes
X
X
X
X
0
1
0
0
1
1
1
1
0
1
0
1
1
1
X
X
X
Inactive
Fall
Fall
X
0
1
No change
1
0
Not Allowed
Rev. 1.4
Page 62 of 100
Output
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
Area
Dynamic
2
nW/MHz
(um )
DFFNASRNX1
1 x Csl
QN
229
430
98
32.2560
DFFNASRNX2
2 x Csl
QN
230
550
110
34.0992
QN
SI
SE
CLK
QN
X
1
0
X
X
X
X
X
1
0
X
0
0
1
1
Inactive
Rise
Rise
Rise
Rise
No change
1
0
1
0
No change
0
1
0
1
Table 9.86. Scan Pos Edge DFF Electrical Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload
Output
SDFFX1
1 x Csl
SDFFX2
2 x Csl
Q
QN
Q
QN
209
166
248
179
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
Area
Dynamic
2
nW/MHz
(um )
720
160
30.4128
1100
260
33.1776
Rev. 1.4
Page 63 of 100
QN
Figure 9.44. Logic Symbol of Scan Pos Edge DFF w/Async Low-Active Set
Table 9.87. Scan Pos Edge DFF w/Async Low-Active Set Transition Table
D
SI
SE
SETB
CLK
QN
X
X
1
0
X
X
X
X
X
X
1
0
X
X
0
0
1
1
0
1
1
1
1
1
X
Inactive
Rise
Rise
Rise
Rise
1
No change
1
0
1
0
0
No change
0
1
0
1
Table 9.88. Scan Pos Edge DFF w/Async Low-Active Set Electrical Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload
Output
SDFFASX1
1 x Csl
SDFFASX2
2 x Csl
Q
QN
Q
QN
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
232
186
282
203
Area
Dynamic
2
nW/MHz
(um )
580
100
36.8640
1090
140
39.6288
QN
RSTB
Figure 9.45. Logic Symbol of Scan Pos Edge DFF w/Async Low-Active Reset
2008 SYNOPSYS ARMENIA Educational Department
Rev. 1.4
Page 64 of 100
SI
SE
RSTB
CLK
QN
X
X
1
0
X
X
X
X
X
X
1
0
X
X
0
0
1
1
0
1
1
1
1
1
X
Inactive
Rise
Rise
Rise
Rise
0
No change
1
0
1
0
1
No change
0
1
0
1
Table 9.90. Scan Pos Edge DFF w/Async Low-Active Reset Electrical Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload
Output
SDFFARX1
1 x Csl
SDFFARX2
2 x Csl
Q
QN
Q
QN
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
216
161
263
180
Area
Dynamic
2
nW/MHz
(um )
660
90
37.7856
950
120
39.6288
Scan Pos Edge DFF w/Async Low-Active Set & Reset: SDFFASRX1, SDFFASRX2
SETB
D
Q
SE
SI
CLK
QN
RSTB
Figure 9.46. Logic Symbol of Scan Pos Edge DFF w/Async Low-Active Set & Reset
Rev. 1.4
Page 65 of 100
SI
SE
SETB
RSTB
CLK
QN
Notes
X
X
X
X
1
0
X
X
X
X
X
X
X
X
1
0
X
X
X
X
0
0
1
1
0
0
1
1
1
1
1
1
0
1
0
1
1
1
1
1
X
X
X
Inactive
Rise
Rise
Rise
Rise
X
1
0
No change
1
0
X
X
X
0
1
No change
0
1
1
0
Not Allowed
Table 9.92. Scan Pos Edge DFF w/Async Low-Active Set & Reset Electrical Parameters and
Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload
Output
SDFFASRX1
1 x Csl
SDFFASRX2
2 x Csl
Q
QN
Q
QN
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
258
197
313
225
Area
Dynamic
2
nW/MHz
(um )
730
90
40.5504
1090
120
42.3936
Scan Pos Edge DFF w/Async Low-Active Set & Reset, Q, QN & S0 outs: SDFFASRSX1,
SDFFASRSX2
SETB
D
Q
SE
S0
SI
CLK
QN
RSTB
Figure 9.47. Logic Symbol of Scan Pos Edge DFF w/Async Low-Active Set & Reset, Q, QN &
S0 outs
Rev. 1.4
Page 66 of 100
SI
SE
SETB
RSTB
X
X
X
X
1
0
X
X
X
X
X
X
X
X
1
0
X
X
X
X
0
0
1
1
0
0
1
1
1
1
1
1
0
1
0
1
1
1
1
1
CLK
QN
S0
Notes
X
X
X
X
Not Allowed
X
1
0
1
X
0
1
0
Inactive No change No change No change
Rise
1
0
1
Rise
0
1
0
Rise
1
0
1
Rise
0
1
0
Table 9.94. Scan Pos Edge DFF w/Async Low-Active Set & Reset, Q, QN & S0 outs Electrical
Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload
Output
SDFFASRSX1
1 x Csl
SDFFASRSX2
2 x Csl
Q
QN
S0
Q
QN
S0
Power
Leakage
(VDD=1.32 V
DC, Temp=25
Dec.C)
nW
275
194
279
360
222
361
Area
Dynamic
2
nW/MHz
(um )
860
110
42.3936
1260
170
45.1584
Scan Pos Edge DFF w/ Sync Low-Active Set & Reset: SDFFSSRX1, SDFFSSRX2
SETB
D
Q
SE
SI
CLK
QN
RSTB
Figure 9.48. Logic Symbol of Scan Pos Edge DFF w/Async Low-Active Set & Reset
Rev. 1.4
Page 67 of 100
SI
SE
SETB
RSTB
CLK
QN
Notes
X
X
X
X
1
0
X
X
X
X
X
X
X
X
1
0
0
0
0
X
0
0
1
1
0
0
1
X
1
1
1
1
0
1
0
X
1
1
1
1
Rise
Rise
Rise
Inactive
Rise
Rise
Rise
Rise
X
1
0
No change
1
0
1
0
X
0
1
No change
0
1
0
1
Not Allowed
Table 9.96. Scan Pos Edge DFF w/ Sync Low-Active Set & Reset Electrical Parameters and
Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload
Output
SDFFSSRX1
1 x Csl
SDFFSSRX2
2 x Csl
Q
QN
Q
QN
208
190
255
190
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
Area
Dynamic
2
nW/MHz
(um )
1120
404
39.6288
1480
546
43.3152
QN
SI
SE
CLK
QN
X
1
0
X
X
X
X
X
1
0
X
0
0
1
1
Inactive
Fall
Fall
Fall
Fall
No change
1
0
1
0
No change
0
1
0
1
Rev. 1.4
Page 68 of 100
Output
SDFFNX1
1 x Csl
SDFFNX2
2 x Csl
Q
QN
Q
QN
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
239
192
286
227
Area
Dynamic
2
nW/MHz
(um )
730
98
34.0992
1138
150
36.8640
QN
Figure 9.50. Logic Symbol of Scan Neg Edge DFF w/Async Low-Active Set
Table 9.99. Scan Neg Edge DFF w/Async Low-Active Set Transition Table
D
SI
SE
SETB
CLK
QN
X
X
1
0
X
X
X
X
X
X
1
0
X
X
0
0
1
1
0
1
1
1
1
1
X
Inactive
Fall
Fall
Fall
Fall
1
No change
1
0
1
0
0
No change
0
1
0
1
Rev. 1.4
Page 69 of 100
Output
SDFFNASX1
1 x Csl
SDFFNASX2
2 x Csl
Q
QN
Q
QN
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
263
223
233
189
Area
Dynamic
2
nW/MHz
(um )
690
110
36.8640
1100
140
39.6288
QN
RSTB
Figure 9.51. Logic Symbol of Scan Neg Edge DFF w/Async Low-Active Reset
Table 9.101. Scan Neg Edge DFF w/Async Low-Active Reset Transition Table
D
SI
SE
RSTB
CLK
QN
X
X
1
0
X
X
X
X
X
X
1
0
X
X
0
0
1
1
0
1
1
1
1
1
X
Inactive
Fall
Fall
Fall
Fall
0
No change
1
0
1
0
1
No change
0
1
0
1
Rev. 1.4
Page 70 of 100
Output
SDFFNARX1
1 x Csl
SDFFNARX2
2 x Csl
Q
QN
Q
QN
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
273
210
306
235
Area
Dynamic
2
nW/MHz
(um )
706
107
37.7856
1185
153
39.6288
Scan Neg Edge DFF w/Async Low-Active Set & Reset: SDFFNASRX1, SDFFNASRX2
SETB
D
SE
SI
CLK
QN
RSTB
Figure 9.52. Logic Symbol of Scan Neg Edge DFF w/Async Low-Active Set & Reset
Table 9.103. Scan Neg Edge DFF w/Async Low-Active Set & Reset Transition Table
D
SI
SE
SETB
RSTB
CLK
QN
Notes
X
X
X
X
1
0
X
X
X
X
X
X
X
X
1
0
X
X
X
X
0
0
1
1
0
0
1
1
1
1
1
1
0
1
0
1
1
1
1
1
X
X
X
Inactive
Fall
Fall
Fall
Fall
X
1
0
No change
1
0
X
X
X
0
1
No change
0
1
1
0
Not Allowed
Rev. 1.4
Page 71 of 100
Output
SDFFNASRX1
1 x Csl
SDFFNASRX2
2 x Csl
Q
QN
Q
QN
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
308
239
337
276
Area
Dynamic
2
nW/MHz
(um )
860
160
40.5504
1130
323
42.3936
QN
SIN
SIN
QN
0
0
1
1
0
1
0
1
X
1
0
No change
X
0
1
No change
Output
LNANDX1
1 x Csl
LNANDX2
2 x Csl
Q
QN
Q
QN
122
122
121
121
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
Area
Dynamic
2
nW/MHz
(um )
257
11
10.1376
517
21
18.4320
Rev. 1.4
Page 72 of 100
CLK
QN
CLK
QN
X
0
1
0
1
1
No change
0
1
No change
1
0
Output
LATCHX1
1 x Csl
LATCHX1
2 x Csl
Q
QN
Q
QN
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
123
166
142
206
Area
Dynamic
2
nW/MHz
(um )
813
158
22.1184
1125
201
25.8048
CLK
QN
Rev. 1.4
Page 73 of 100
SETB
CLK
QN
X
X
1
0
1
0
1
1
0
X
1
1
No change
1
1
0
No change
0
0
1
Table 9.110. High-Active Latch w/ Async Low-Active Set Electrical Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload
Output
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
LASX1
1 x Csl
LASX2
2 x Csl
Q
QN
Q
QN
228
178
254
184
Area
Dynamic
2
nW/MHz
(um )
713
66
24.8832
1139
129
29.5696
CLK
QN
RSTB
RSTB
CLK
QN
X
X
1
0
1
0
1
1
0
X
1
1
No change
0
1
0
No change
1
0
1
Rev. 1.4
Page 74 of 100
Output
LARX1
1 x Csl
LARX2
2 x Csl
Q
QN
Q
QN
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
232
159
275
178
Area
Dynamic
2
nW/MHz
(um )
790
68
25.8048
1150
116
29.4912
CLK
QN
RSTB
Figure 9.57. Logic Symbol of High-Active Latch w/ Async Low-Active Set & Reset
Table 9.113. High-Active Latch w/ Async Low-Active Set & Reset Transition Table
D
SETB
RSTB
CLK
QN
Notes
X
X
X
X
1
0
1
0
1
1
1
1
1
1
0
1
1
1
X
X
X
0
1
1
X
1
0
No change
1
0
X
0
1
No change
0
1
Not Allowed
Rev. 1.4
Page 75 of 100
Output
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
LASRX1
1 x Csl
LASRX2
2 x Csl
Q
QN
Q
QN
254
176
301
197
Area
Dynamic
2
fW/MHz
(um )
554
73
26.7264
980
125
31.3344
High-Active Latch w/ Async Low-Active Set & Reset only Q out: LASRQX1, LASRQX2
SETB
D
CLK
RSTB
Figure 9.58. Logic Symbol of High-Active Latch w/ Async Low-Active Set & Reset only Q out
Table 9.115. High-Active Latch w/ Async Low-Active Set & Reset only Q out Transition Table
D
SETB
RSTB
CLK
Notes
X
X
X
X
1
0
0
0
1
1
1
1
0
1
0
1
1
1
X
X
X
0
1
1
X
1
0
No change
1
0
Not Allowed
Rev. 1.4
Page 76 of 100
Cload
ps
LASRQX1
LASRQX2
1 x Csl
2 x Csl
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
227
246
428
517
Area
Dynamic
2
nW/MHz
(um )
62
97
25.8048
26.7264
High-Active Latch w/ Async Low-Active Set & Reset only QN out: LASRNX1, LASRNX2
SETB
D
CLK
QN
RSTB
Figure 9.59. Logic Symbol of High-Active Latch w/ Async Low-Active Set & Reset only QN out
Table 9.117. High-Active Latch w/ Async Low-Active Set & Reset only QN out Transition Table
D
SETB
RSTB
CLK
QN
Notes
X
X
X
X
1
0
0
0
1
1
1
1
0
1
0
1
1
1
X
X
X
0
1
1
X
0
1
No change
0
1
Not Allowed
Rev. 1.4
Page 77 of 100
Cell Name
Cload
LASRNX1
LASRNX2
1 x Csl
2 x Csl
176
198
Area
Dynamic
2
nW/MHz
(um )
44
51
25.8048
27.6480
345
418
Clock Gating cell w/ Latched Pos Edge Control Post: CGLPPSX2, CGLPPSX4, CGLPPSX8,
CGLPPSX16
SE
ENL
OBS
LATCH
EN
GCLK
CLK
Figure 9.60. Logic Symbol of Clock Gating cell w/ Latched Pos Edge Control Post
Table 9.119. Clock Gating cell w/ Latched Pos Edge Control Post Truth Table
SE
EN
CLK
GCLK
1
1
0
0
0
0
X
X
0
0
1
1
0
1
0
1
0
1
0
1
0
OBS
0
1
Rev. 1.4
Page 78 of 100
Cell Name
Cload
CGLPPSX2
CGLPPSX8
CGLPPSX16
2 x Csl
8 x Csl
16 x Csl
181
200
118
Area
Dynamic
2
nW/MHz
(um )
66
185
397
25.8048
33.1776
47.0016
1073
2889
5346
Clock Gating cell w/ Latched Neg Edge Control Post: CGLNPSX2, CGLNPSX4, CGLNPSX8,
CGLNPSX16
SE
ENL
OBS
LATCH
EN
GCLK
CLK
Figure 9.61. Logic Symbol of Clock Gating cell w/ Latched Neg Edge Control Post
Table 9.121. Clock Gating cell w/ Latched Neg Edge Control Post Truth Table
SE
EN
CLK
GCLK
1
1
0
0
0
0
X
X
0
0
1
1
0
1
0
1
0
1
0
1
!OBS
1
0
1
Rev. 1.4
Page 79 of 100
Cload
ps
CGLNPSX2
CGLNPSX8
CGLNPSX16
2 x Csl
8 x Csl
16 x Csl
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
185
267
246
915
2697
5049
Area
Dynamic
2
nW/MHz
(um )
79
304
488
23.0400
31.3344
44.2368
Clock Gating cell w/ Latched Pos Edge Control Pre: CGLPPRX2, CGLPPRX8
SE
LATCH
EN
GCLK
CLK
Figure 9.62. Logic Symbol of Clock Gating cell w/ Latched Pos Edge Control Pre
Table 9.123. Clock Gating cell w/ Latched Pos Edge Control Pre Truth Table
SE
EN
CLK
ENL
1
X
0
X
X
1
0
X
0
0
0
1
1
1
1
No change
ENL
CLK
GCLK
0
0
1
1
0
1
0
1
0
0
0
1
Rev. 1.4
Page 80 of 100
CGLPPRX2
CGLPPRX8
2 x Csl
8 x Csl
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
Area
Dynamic
2
ps
nW
nW/MHz
(um )
185
205
919
2668
66
185
21.1968
29.4912
Clock Gating cell w/ Latched Neg Edge Control Pre: CGLNPRX2, CGLNPRX8
SE
LATCH
EN
GCLK
CLK
Figure 9.63. Logic Symbol of Clock Gating cell w/ Latched Neg Edge Control Pre
Table 9.125. Clock Gating cell w/ Latched Neg Edge Control Pre Truth Table
SE
EN
CLK
ENL
1
X
0
X
X
1
0
X
1
1
1
0
1
1
1
No change
ENL
CLK
GCLK
0
0
1
1
0
1
0
1
1
1
0
1
Rev. 1.4
Page 81 of 100
Cload
ps
CGLNPRX2
CGLNPRX8
2 x Csl
8 x Csl
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
178
220
Area
Dynamic
2
nW/MHz
(um )
66
198
23.0400
32.2560
714
1350
IN
IN
DELLN1X2
DELLN2X2
DELLN3X2
2 x Csl
2 x Csl
2 x Csl
254
509
754
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
385
445
668
Rev. 1.4
Area
Dynamic
2
nW/MHz
(um )
125
135
156
14.7456
15.6672
22.1184
Page 82 of 100
INQ1
INQ2
INN
INN
INP
INQ2
Notes
X
X
X
X
0
X
1
1
1
0
X
0
Z
X
X
INQ1
Not Allowed
Not Allowed
PGX1
PGX2
PGX4
1 x Csl
2 x Csl
4 x Csl
35
37
39
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
160
325
618
Area
Dynamic
2
nW/MHz
(um )
11
20
38
7.3728
8.2944
10.1376
INOUT1
INOUT2
Rev. 1.4
Page 83 of 100
ENB
INOUT2
X
X
0
1
INOUT1
Z
Table 9.132. Bi-directional Switch w/ Active Low Enable Electrical Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload
BSLEX1
BSLEX2
BSLEX4
1 x Csl
2 x Csl
4 x Csl
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
36
38
40
315
610
1150
Area
Dynamic
2
nW/MHz
(um )
10
19
39
7.3728
10.1376
12.9024
ISO
ISO
0
X
1
X
0
1
0
0
1
Table 9.134. Hold 0 Isolation Cell (Logic AND) Electrical Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload
ISOLANDX1
ISOLANDX2
ISOLANDX8
1 x Csl
2 x Csl
8 x Csl
111
129
165
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
366
644
2354
Rev. 1.4
Area
Dynamic
2
nW/MHz
(um )
20
26
50
7.3728
9.2016
18.4320
Page 84 of 100
ISO
ISO
ISO
0
X
1
0
1
X
0
1
1
Table 9.136. Hold 1 Isolation Cell (Logic OR) Electrical Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
Cell Name
Cload
ISOLORX1
ISOLORX2
ISOLORX8
1 x Csl
2 x Csl
8 x Csl
84
82
162
330
611
2305
Area
Dynamic
2
nW/MHz
(um )
45
76
326
7.3728
9.2160
17.5104
VDDH
LSUP
D
VSS
Rev. 1.4
Page 85 of 100
0
X
1
0
1
1
Table 9.138. Low to High Level Shifter Electrical Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
LSUPX1
LSUPX2
LSUPX8
1 x Csl
2 x Csl
8 x Csl
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
Area
Dynamic
2
ps
nW
nW/MHz
(um )
262
301
500
450
733
2376
112
158
465
22.1184
22.1184
36.8640
LSDN
D
VSS
0
X
1
0
1
1
Rev. 1.4
Page 86 of 100
Cell Name
Cload
LSDNX1
LSDNX2
LSDNX8
1 x Csl
2 x Csl
8 x Csl
69
78
143
306
585
2639
Area
Dynamic
2
nW/MHz
(um )
31
58
231
5.5296
7.3728
23.0400
Low to High Level Shifter/ Active Low Enable: LSUPENX1, LSUPENX2, LSUPENX4,
LSUPENX8
VDDL
VDDH
ENB
LSUPEN
D
VSS
Figure 9.71. Logic Symbol of Low to High Level Shifter/Active Low Enable
Table 9.141. Low to High Level Shifter /Active Low Enable Truth Table
D
ENB
X
0
1
0
1
1
1
0
1
Rev. 1.4
Page 87 of 100
LSUPENX1
LSUPENX2
LSUPENX8
1 x Csl
2 x Csl
8 x Csl
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
Area
Dynamic
2
ps
nW
nW/MHz
(um )
280
285
608
787
923
3125
450
975
1680
27.3880
31.1328
42.9410
High to Low Level Shifter/ Active Low Enable: LSDNENX1, LSDNENX2, LSDNENX4,
LSDNENX8
VDD
ENB
LSDNEN
Q
VSS
Figure 9.72. Logic Symbol of High to Low Level Shifter/Active Low Enable
Table 9.143. High to Low Level Shifter / Active Low Enable Truth Table
D
ENB
X
0
1
0
1
1
1
0
1
Rev. 1.4
Page 88 of 100
Cell Name
Prop Delay (Avg)
Cload
ps
LSDNENX1
LSDNENX2
LSDNENX8
1 x Csl
2 x Csl
8 x Csl
69
82
218
28
30
457
Area
Dynamic
2
nW/MHz
(um )
200
220
800
10.9250
18.4000
29.4400
VDDG
RETN
D
CLK
QN
VSS
CLK
Q[n+1]
QN[n+1]
Mode
1
1
1
0
Rise
X
0
1
X
X
X
X
Rise
Rise
Fall
X
0
X
0
1
Q[n]
X
Q[n]
X
1
0
QN[n]
X
QN[n]
X
Rev. 1.4
Page 89 of 100
Output
RDFFX1
1 x Csl
RDFFX2
2 x Csl
Q
QN
Q
QN
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
173
251
195
293
Area
Dynamic
2
fW/MHz
(um )
1056
134
58.0608
1188
246
58.9824
VDDG
SI
SE
CLK
QN
VSS
SI
SE
Q[n+1]
QN[n+1]
Mode
Normal mode reset
Normal mode write 0
Scan mode write 0
Scan mode write 1
Normal mode write 1
Normal mode latch state
Retention mode
Restore mode
Power down no
retention
1
1
1
1
1
1
0
Rise
X
0
X
X
1
X
X
X
X
Rise
Rise
Rise
Rise
Fall
X
0
X
X
0
1
X
X
X
0
X
0
1
1
0
X
X
0
0
0
0
1
1
Q[n]
X
Q[n]
1
1
1
0
0
QN[n]
X
QN[n]
Rev. 1.4
Page 90 of 100
Output
RSDFFX1
1 x Csl
RSDFFX2
2 x Csl
Q
QN
Q
QN
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
177
255
194
290
Area
Dynamic
2
fW/MHz
(um )
1258
110
66.3552
1374
185
68.1984
VDDG
RETN
D
CLK
QN
VSS
CLK
1
1
1
0
Rise
X
0
1
X
X
X
X
Fall
Fall
Rise
X
0
X
Q[n+1] QN[n+1]
0
1
Q[n]
X
Q[n]
X
1
0
QN[n]
X
QN[n]
X
Mode
Normal mode write 0
Normal mode write 1
Normal mode latch state
Retention mode
Restore mode
Power down no retention
Rev. 1.4
Page 91 of 100
Output
RDFFNX1
1 x Csl
RDFFNX2
2 x Csl
Q
QN
Q
QN
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
202
297
214
310
Area
Dynamic
2
fW/MHz
(um )
1168
110
57.1392
1536
195
58.9824
VDDG
RETN
D
SI
SE
CLK
QN
VSS
X
X
0 Fall
X Fall
X Fall
1 Fall
X Rise
X
X
X
0
X
X
SI
SE
Q[n+1]
QN[n+1]
Mode
X
X
0
1
X
X
X
0
X
X
0
1
1
0
X
X
0
X
0
0
0
1
1
Q[n]
X
Q[n]
X
1
1
1
0
0
QN[n]
X
QN[n]
X
Rev. 1.4
Page 92 of 100
Output
RSDFFNX1
1 x Csl
RSDFFNX2
2 x Csl
Q
QN
Q
QN
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
206
301
212
310
Area
Dynamic
2
fW/MHz
(um )
1374
127
66.3552
1742
241
68.1984
VDD
SLEEP
1
1
1
hi-z
0
1
HEADX2
HEADX8
HEADX32
2 x Csl
8 x Csl
32 x Csl
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
0.74
3
13.2
Rev. 1.4
Area
Dynamic
2
nW/MHz
(um )
0.312
1.6
7.2
27.6480
44.2368
112.4352
Page 93 of 100
IN
AOn
VSS
VDDG
VSS
0
1
1
1
0
0
0
1
AOINVX1
AOINVX2
AOINVX4
1 x Csl
2 x Csl
4 x Csl
66
76
98
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
306
585
1071
Area
Dynamic
2
nW/MHz
(um )
28
60
112
22.1184
22.1184
27.6480
IN
AOn
VSS
Rev. 1.4
Page 94 of 100
VDDG
VSS
0
1
1
1
0
0
0
1
Cload
ps
AOBUFX1
AOBUFX2
AOBUFX4
1 x Csl
2 x Csl
4 x Csl
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
66
76
98
306
585
1071
Area
Dynamic
2
nW/MHz
(um )
28
60
112
22.1184
22.1184
27.6480
AOn
CLK
QN
RSTB
Figure 9.80. Logic Symbol of Always on Pos Edge DFF, w/ Async Low-Active Reset
Table 9.159. Always on Pos Edge DFF, w/ Async Low-Active Reset Transition Table
RSTB
CLK
QN
0
1
1
1
1
X
Rise
Rise
0
1
X
0
1
X
X
0
0
1
Q
Q
1
1
0
QN
QN
Rev. 1.4
Page 95 of 100
Output
AODFFARX1
1 x Csl
AODFFARX2
2 x Csl
Q
QN
Q
QN
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
255
186
290
197
Area
Dynamic
2
nW/MHz
(um )
970
96
46.0800
1120
122
49.7664
AOn
CLK
QN
RSTB
Figure 9.81. Logic Symbol of Always on Neg Edge DFF, w/ Async Low-Active Reset
Table 9.161. Always on Neg Edge DFF, w/ Async Low-Active Reset Transition Table
RSTB
CLK
QN
0
1
1
1
1
X
Fall
Fall
0
1
X
0
1
X
X
0
0
1
Q
Q
1
1
0
QN
QN
Rev. 1.4
Page 96 of 100
Output
AODFFNARX1
1 x Csl
AODFFNARX2
2 x Csl
Q
QN
Q
QN
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
287
213
322
227
Area
Dynamic
2
nW/MHz
(um )
620
100
47.9232
970
132
47.9232
IN
Rev. 1.4
Page 97 of 100
VSS
Rev. 1.4
Page 98 of 100
VSS
DCAP
VSS
CLOAD
VSS
Rev. 1.4
Page 99 of 100
A1.2
A.1.3
A.1.4
Date
Change
Rev. 1.4