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System Partitioning
Siamak Mohammadi
University of Tehran
Constraints
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Outline
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Task
Structure
Register transfers
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The transfers between registers for each machine state are described
A structural interconnection of physical components
Often called a netlist
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Computation of Metrics
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computation time in an
iterative algorithm is spent
evaluating large numbers of
partitions
Iterative algorithms differ from
one another primarily in the
ways in which they modify the
partition and in which they
accept or reject bad
modifications
The goal is to find global
minimum while performing as
little computation as possible
(A: local minimum)
Iterative algorithms
The
Constructive algorithms
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Hierarchical Clustering
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Simulated Annealing
Iterative algorithm modeled after physical annealing
process
Overview
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BUD Example
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Closeness metrics:
Interconnecting wires
Concurrency
Shared hardware
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BUD Example
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Closeness metrics:
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Goal
Definition
Greedy [GD92]
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Aparty Example
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Hardware implementation
Partitioning Approaches
Software implementation
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With system-level partitioning, a critical loop which took up 90% of the software
execution time for a HDTV Chromakey algorithm was implemented in hardware (as a
17,000 gate ASIC) leading to a 3X speedup
[DeMicheli94]
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Vulcan I
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Behaviors to processors/ASICs
Variables to memories
Communication channels to buses
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Profiling techniques
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Can be used only with a fully specified model with all data
dependencies removed and all component costs known
Result in very good partitions
Cosyma
Vulcan II
Partitioning Metrics
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Associated metrics:
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Each
line represents a
different vendors chip set
Each
point represents an
allocation and partition
Many
designs quickly
examined
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Summary
Future Directions
Automation
Exploration
Documentation
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Tabu Search
Tabu Search
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