SSN COLLEGE OF ENGINEERING

KALAVAKKAM- 603 110

DEPARTMENT OF ELECTRICAL & ELECTRONICS ENGINEERING

LAB MANUAL
EC 6361 ELECTRONICS LABORATORY
JUNE 2015-NOV 2015

NAME: _____________________________________.
REGISTER NO.: ______________________.
YEAR:

II

SEM:3

SEC: A / B

DEPT: EEE

ANNA UNIVERSITY
SYLLABUS-R 2013
EC 6361 ELECTRONICS LAB

1. Characteristics of Semi conductor diode and Zener diode

2. Characteristics of a NPN Transistor under common emitter, common
Collector and common base configurations
3. Characteristics of JFET (Draw the equivalent circuit)
4. Characteristics of UJT and generation of saw tooth waveforms
5. Design and Frequency response characteristics of a common emitter amplifier
6. Characteristics of photo diode & photo transistor, Study of light activated
Relay circuit
7. Design and testing of RC phase shift, LC oscillators
8. Single Phase half-wave and full wave rectifiers with inductive and capacitive
filters
9. Differential amplifiers using FET
10. Study of CRO for frequency and phase measurements
11. Astable and Monostable multivibrators
12. Realization of passive filters

LIST OF EXPERIMENTS
Sl.
NO.

1.

DATE

EXPERIMENT

10.
11.

Astable and Monostable multivibrators

12.

Design and testing of RC phase shift, LC

oscillators
Realization of passive filters

3.
4.
5.
6.

7.

8.
9.

13.
14.

MARKS/
EXPT.
(10)

A. Characteristics of Semiconductor
diode.
B. Characteristics of Zener diode.
Characteristics of BJT in CE &CC
Configurations
Characteristics of BJT in CB
Configurations & determination of h
parameters
Characteristics of JFET &its Parameters
determination
Characteristics of UJT and sawtooth
waveform generation
Single phase half wave and full wave
rectifiers with inductive and capacitive
filters
Characteristics of photo diode & photo
transistor, Study of light activated relay
circuit
Design and Frequency response
characteristics of a Common Emitter
amplifier
Design and testing of RC phase shift, LC
oscillators
Differential Amplifier using FET

2.

Page
No.

Study of CRO for frequency and phase

measurements Study of CRO

TOTAL MARKS:

SIGNATURE OF THE FACULTY:

Faculty
Signature

EXPT NO:
DATE:
STATIC CHARACTERISTICS OF
(A) SEMICONDUCTOR DIODE AND (B) ZENER DIODE
(A) STATIC CHARACTERISTICS OF SEMICONDUCTOR DIODE
AIM:
To determine the static characteristics of semiconductor diode under forward and
reverse biased conditions and to calculate its dc and ac resistance values.
APPARATUS REQUIRED:
S.No
1
2
3
4
5
6
7
8
9

Apparatus
Regulated power supply
Voltmeter
Voltmeter
Ammeter
Ammeter
Diode
Resistor
Bread board
Connecting wires

Range
(0-30) V
(0-1) V
(0-30) V
(0-1) mA
(0-100) mA
1N4007
1K

Type
MC
MC
MC
MC

Quantity
1
1
1
1
1
1
1
1

FORMULAE:
D.C (or) static resistance, rdc = VF / IF (At any point in the linear region of
forward bias characteristics)
A.C (or) Dynamic resistance, rac =VR/IR (In the linear region of forward bias
characteristics)
THEORY:
Forward Bias:
The positive terminal of the voltage source is connected to the anode of the
diode and negative terminal to the cathode. When forward voltage (V F) is increased in
steps of 0.1, there is a particular voltage at which diode starts conducting is called knee
voltage (or) cut-in voltage. Below the cut in voltage, VK, current is zero. After the cut in
voltage, VK, current is sharply increased.
REVERSE BIAS:
In the case of reverse biased condition, there is little flow of current through the
diode with increase in reverse voltage VR , until a particular point called breakdown
voltage VBR is reached. Beyond VBR, IR increases for a constant value of VR.

PROCEDURE:
Forward Bias:
1. Connections are given as per the circuit diagram.
2. The power supply is switched ON.
3. The supply voltage is varied in steps and corresponding voltmeter and
ammeter readings are tabulated.
Reverse Bias:
1. Connections are given as per the circuit diagram.(polarity of the diode is
reversed and meters are replaced suitably)
2. The power supply is switched ON.
3. The supply voltage is varied in steps and corresponding voltmeter and
ammeter readings are tabulated.

PIN DIAGRAM:

Cathode

CIRCUIT DIAGRAM:
Forward Bias:

Anode

Reverse Bias:

MODEL GRAPH:

CALCULATION:

D.C (or) static resistance, rdc =

A.C (or) Dynamic resistance, rac =

TABULATION:
Forward Bias:
S.No

Reverse Bias:

Forward
voltage (VF)

Forward
current (IF)

(V)

(mA)

S.No

1.

1.

2.

2.

3.

3.

4.

4.

5.

5.

6.

6.

7.

7.

8.

8.

9.

9.

Reverse
voltage (VR)

Reverse
current (IR)

(V)

(A)

RESULT:
Thus the forward and reverse bias characteristics of PN junction diodes are
drawn. Also the dc and ac resistance have found out.
D.C (or) static resistance, rdc = -------A.C (or) Dynamic resistance, rac = -------

(B) STATIC CHARACTERISTICS OF ZENER DIODE

AIM:
To determine the static characteristics of Zener diode under forward and reverse
biased conditions and calculate the dynamic impedance value.
APPARATUS REQUIRED:
S.No
1
2
3
5
6
7
8
9

Apparatus
Regulated power supply
Voltmeter
Voltmeter
Ammeter
Diode
Resistor
Bread board
Connecting wires

FORMULAE:
Dynamic impedance, Z R = VZ/IZ

Range
(0-30) V
(0-1) V
(0-30) V
(0-100) mA
1Z6.2
1K

Type
MC
MC
MC

Qty
1
1
1
1
1
1
1
Req

(At any point in the breakdown region)

THEORY:
The Zener diode is a silicon PN junction diode which operates in the breakdown
region. The breakdown voltage is set by controlling the doping level during manufacture.
The behavior of zener diode under forward bias condition is same as PN junction diode.
In the case of reverse bias condition, with the increase of reverse voltage across
a diode, the reverse current remains negligibly small up to the knee of the curve. At this
point the effect of breakdown begins. The critical voltage is called breakdown voltage.
From this value the voltage remains constant. This ability of the diode is called
regulating ability.
.
PROCEDURE:
Forward Bias:
1. Connections are given as per the circuit diagram.
2. The power supply is switched ON.
3. The supply voltage is varied in steps and corresponding voltmeter and ammeter
readings are tabulated.
Reverse Bias:
1. Connections are given as per the circuit diagram. (polarity of the diode is
reversed and meters are replaced suitably)

2. The power supply is switched ON.

3. The supply voltage is varied in steps and corresponding voltmeter and ammeter
readings are tabulated.

DEVICE SYMBOL:

CIRCUIT DIAGRAM:
Forward Bias:

Reverse Bias:

MODEL GRAPH:

TABULATION:
Forward Bias:
S.No

Forward
voltage (VF)
(V)

Reverse Bias:
Forward
current (IF)
(mA)

S.No Reverse
voltage (VR)
(V)

1.

1.

2.

2.

3.

3.

4.

4.

5.

5.

6.

6.

7.

7.

8.

8.

9.

9.

Reverse
current (IR)
(mA)

CALCULATION:
Dynamic impedance value, ZR =

RESULT:
Thus the forward and reverse bias characteristics of PN junction diodes are
drawn. Also the dynamic impedance is calculated.
Dynamic impedance value, ZR =

EXPT NO:
DATE:
STATIC CHARACTERISTICS OF BJT UNDER COMMON EMITTER
CONFIGURATION & DETERMINATION OF h PARAMETERS
AIM:
To determine the input and output characteristics of the given NPN transistor
under common emitter configuration and calculate their h-parameters.
APPARATUS REQUIRED:
S.No
1
2
3
4
5
6
7
8
910

Apparatus
Regulated power supply
Voltmeter
Voltmeter
Ammeter
Ammeter
Transistor
Resistor
Bread board
Connecting wires

Range
(0-30) V
(0-10) V
(0-30) V
(0-50) mA
(0-100) mA
BC 107
1K

Type
MC
MC
MC
MC

Qty
2
1
1
1
1
1
2
1
Req

THEORY:
COMMON EMITTER CONFIGURATION:
Input Characteristics:
1. There exists a threshold (or) knee voltage (Vk) below which base current is
very small.
2. Beyond the knee, IB increases with the increase in base to emitter voltage,
VBE , for a constant collector to emitter voltage, VCE . Since the input
resistance is high for CE configuration than CB mode, the value of IB does not
increase as rapidly as that of input characteristics of common base.
3. When collector to emitter voltage, VCE is increased above 1V, curve shift
downwards. It occurs because of the fact, that as V CE is increased, the
depletion width in base region increases. The effective width of base
decreases, which in turn reduces IB .
4. With the help of input characteristics, ac input resistance can be calculated.
Ri = VBE / IB
Output Characteristics:
1. There are 3 regions namely saturation region, active region and cut-off region.
2. As the collector to emitter voltage, VCE, is increased above zero,the collector
current, IC increases rapidly to a saturation value ,depending upon the value of

base current.
3. When VCE is increased further,the IC slightly increases. It is due to the fact that
increase in VCE, will decrease the IB and hence IC increases. This phenomenon is
called early effect.
4. When IB is zero, small IC exists. This is called leakage current.
5. With the help of output characteristics, ac input resistance can be calculated.
RO= VCE / IC
HYBRID PARAMETERS:
COMMON EMITTER CONFIGURATION :
Input resistance, hie = VBE / IB

at constant VCE.

Reverse voltage transfer ratio, hre = VBE / VCE

Forward current transfer ratio, hfe = IC / IB
Output conductance,hoe = IC / VCE

at constant IB

at constant VCE.

at constant IB

PROCEDURE:
Input Characteristics:
1. Connections are given as per the circuit diagram.
2. Voltage VCE (VEC for CC) is kept constant at a particular value.
3. Voltage VBE (VBC for CC ) is varied in steps and corresponding current IB is noted
down and the readings are tabulated.
4. The same procedure is repeated for different VCE (VEC for CC) but constant values of
VCE (VEC for CC).
Output Characteristics:
1. Connections are given as per the circuit diagram.
2. Base current IB is kept constant at a particular value.
3. Voltage VCE (VEC for CC) is varied in steps and corresponding current IC
(IE for CC) is noted down and the readings are tabulated.
4. The same procedure is repeated for different VCE but constant values of IB.
PIN DIAGRAM:

CIRCUIT DIAGRAM:
COMMON EMITTER CONFIGURATION:

COMMON EMITTER CONFIGURATION:

TABULATION:

Sl.No

1.
2.
3.
4.
5.
6.
7.
8.
9.

Input Characteristics:
Collector Emitter voltage
VCE =0V
Base to Emitter
Base Current,IB
Voltage,VBE
(mA)
(V)

Collector Emitter voltage

VCE = 5V
Base to Emitter
Base current,
Voltage ,VBE
IB
(V)
(mA)

Output Characteristics:

S.No

Base Current
IB = 20 A
Collector Emitter
Collector Current,
Voltage ,VCE
IC
(V)
(mA)

Base Current
IB = 40 A
Collector
Collector Current,
emitter Voltage,
IC
VCE
(V)
(mA)

1.
2.
3.
4.
5.
6.
7.
8.
9.

MODEL GRAPH:

Output characteristics

CALCULATION:

RESULT:
Thus the input and output characteristics of common emitter configuration of BJT
are drawn and their h parameters are determined from the graph.
hi

Common
emitter

hr

hf

ho

1/

EXPT NO:
DATE:
STATIC CHARACTERISTICS OF BJT IN COMMON BASE CONFIGURATIONS &
DETERMINATION OF h PARAMETERS
AIM:
To determine the input and output characteristics of a transistor under common
base mode and common collector mode and calculate their h-parameters.
APPARATUS REQUIRED:
S.No
1
2
3
4
5
6
7
8
910

Apparatus
Regulated power supply
Voltmeter
Voltmeter
Ammeter
Ammeter
Transistor
Resistor
Bread board
Connecting wires

Range
(0-30) V
(0-10) V
(0-30) V
(0-50) mA
(0-100) mA
BC 107
1K

Type
MC
MC
MC
MC

Qty
2
1
1
1
1
1
2
1
Req

THEORY:
.
COMMON BASE CONFIGURATION:
Input Characteristics:
1. With VCB=0 for different Emitter to Base voltage VEB find the values of
Emitter current IE.
2. Fix VCB to a slightly greater value as indicated in the Table I and find the
values of Emitter current IE for different Emitter to Base voltage VEB.
3. Repeat step b with different VCB.
The input resistance,.Ri = VBC / IB
Output Characteristics:
4. With IE=0 for different Collector to Base voltage VCB find the values of
collector current IC.
5. Fix IE to a slightly greater value as indicated in the Table II and find the
values of Collector current IC for different Collector to Base voltage VCB.
6. Repeat step b with different IE.
7. Finally from the graph plotted, Output and Input characteristics find the Hybrid
parameters.

HYBRID PARAMETERS:
COMMON BASE CONFIGURATION:
Input resistance, hic=VEB/ IE at constant VCB.
Reverse voltage transfer ratio, hrc= VEB/ VCB at constant IE
Forward current transfer ratio, hfc = IC / IE at constant VCB.
Output conductance, hoc= IC /VCB at constant IE.
PIN DIAGRAM:

CIRCUIT DIAGRAM:
COMMON BASE CONFIGURATION:

MODEL GRAPH:

Output characteristics

TABULATION:

Sl.No

1.
2.
3.
4.
5.
6.
7.
8.
9.

Input Characteristics:
Collector Base voltage
VCE =0V
Base Emitter
Emitter Current, IB
Voltage,VBE (V)
(mA)

Collector Base voltage

VCE = 5V
Base Emitter
Emitter current,
Voltage ,VBE (V) IB
(mA)

Output Characteristics:

S.No

Emitter Current
IE = 5 mA
Collector Base
Collector Current,
Voltage ,VCB (V)
IC
(mA)

Emitter Current
IE = 10 mA
Collector Base
Collector
Voltage ,VCB
Current, IC (mA)
(V)

1.
2.
3.
4.
5.
6.
7.
8.

CALCULATION:

RESULT:
Thus the input and output characteristics of common base configuration of BJT
are drawn and their h parameters are determined from the graph.
hi

Common base

hr

hf

ho

1/

EXPT No:
Date:
STATIC CHARACTERISTICS OF JFET AND ITS PARAMETER DETERMINATION
AIM:
To determine the static characteristics of JFET and draw its equivalent circuit.
APPARATUS REQUIRED:
S.No
1
2
3
4
5
6
6
7

Apparatus
Regulated power supply
JFET
Voltmeter
Voltmeter
Ammeter
Resistor
Breadboard
Connecting wires

Range
(0-30)V
BFW10
(0-10)V
(0-30)V
(0-100) mA
1K

Type

MC
MC
MC

Qty
2
1
1
1
1
2
1
Req

THEORY:
Drain Characteristics:
There are 3 regions in the curve.
1. Ohmic Region:
It is shown as a curve OA in the figure. In this region, drain current
increases linearly with the increase in drain to source voltage (V DS) by obeying
the ohms law. The linear increase in drain current is due to the fact that N-type
semiconductor bar acts like a simple resistor.
2. Curve AB:
In this region, the drain current increases at the reverse square law rate
with increase in drain to source voltage, VDS. Here, ID increases slowly when
compared to the ohmic region. VDS increases, ID increases. This in turn increases the
reverse bias voltage across gate-source junction. As a result of this ,depletion region
grows in size, thereby reducing the effective width of channel. For VDS corresponding
to point B, channel width is reduced to a minimum value and is known as Pinch-off. So
the value of VDS at which the channel pinch-off occurs is known as pinch-off voltage
(VP).
3. Pinch-off region:

It is shown by curve BC. It is also called saturation region or constant

current region. Here ID remains constant at its maximum value IDSS.
4. Breakdown region:
In this region, ID increases rapidly as VDS is increased. This is due to the
breakdown of gate to source junction due to avalanche effect.
Transfer Characteristics:
It is a plot of ID versus VGS.The upper end of curve is shown by drain current
value equal to IDSS. While the lower end is indicated by a voltage equal to VGS (off).
JFET parameters:
1. A.C drain resistance, rDS = VDS/ID. (in the pinch of region)
2. Transconductance, gm = ID/VGS at constant VDS.
3. Amplification factor, = rDS X gm
PROCEDURE:
Drain Characteristics
1. Connections are given as per the circuit diagram.
2. The voltage VGS is kept constant at a particular value.
3. The voltage VDS is varied in steps and corresponding current ID is noted down
and the readings are tabulated.
4. The same procedure is repeated for different but constant values of V GS.
Transfer Characteristics
1. Connections are given as per the circuit diagram.
2. The voltage VDS is kept constant at a particular value.
3. The voltage VGS is varied in steps and corresponding current ID is noted down
and the readings are tabulated.
4. The same procedure is repeated for different but constant values of V DS.
DEVICE SYMBOL:

CIRCUIT DIAGRAM:

TABULATION:

S.No

1.
2.
3.
4.
5.
6.
7.
8.
9.

Drain Characteristics:
Gate -source Voltage
VGS =0V
Drain-to-source
Drain Current,
Voltage, VDS
ID
(V)
(mA)

Gate -source Voltage

VGS = 1V
Drain-to-source Drain Current,
Voltage, VDS
ID
(V)
(mA)

Transfer Characteristics:
Drain - source Voltage
VDS =5V
Sl.No Gate-to-source
Drain Current,
Voltage, VGS
ID
(V)
(mA)

Drain- source Voltage

VDS =8V
Gate-to-source
Drain Current,
Voltage, VGS
ID
(V)
(mA)

1.
2.
3.
4.
5.
6.
7.
8.
9.
10.

MODEL GRAPH:
Drain Characteristics

Transfer Characteristics

CALCULATION:

EQUIVALENT CIRCUIT:

RESULT:
Thus the drain and transfer characteristics of JFET are drawn.
From graph,
1. Drain resistance, rd =----------2. Transconductance, gm=---------3. Amplification factor,=
4. Pinchoff voltage, VP=

EXPT NO:
DATE:
STATIC CHARACTERISTICS OF UJT AND SAW TOOTH WAVEFORM
GENERATION
AIM:
To determine the characteristics of UJT and also calculate the intrinsic standoff ratio
APPARATUS REQUIRED:
S.No
1
2
3
4
5
6
7
8

Apparatus
Regulated power supply
Voltmeter
Voltmeter
Ammeter
UJT
Resistor
Bread board
Connecting wires

Range
(0-30) V
(0-10) V
(0-30) V
(0-50) mA
2N2646
1K

Type
MC
MC
MC

Qty
2
1
1
1
1
2
1

THEORY:
UJT consists of a bar of lightly doped N type silicon with a small piece of heavily
doped P-type material joined to one side. The end terminal of the bar is designated
base1 (B1) and base 2 (B2) and the P-type region is termed as emitter (E). The silicon
bar is lightly doped it has a high resistance and can be represented as high resistors as
shown in equivalent circuit. The P-type emitter forms a PN-junction with the N- type
silicon bar and this junction are represented by a diode in the equivalent circuit. When a
voltage is applied between two bases, it divides between two resistances in the ratio of
their values. Let V1 be the Voltage across the resistor RB1. Now, when the emitter is
forward biased and if the forward biased voltage is less than V1 then the diode is
actually reverse biased and the device will be in Cut-off. If the emitter voltage is
increased above V1, then the emitter current flows. The voltage at which the device
starts conduction is called Peak voltage (VP). When the emitter voltage is increased
beyond Vp, the charge carriers are injected into the N-region and the resistance starts
decreasing since the resistance depends on doping. Now the device enters the
negative resistance region. In this region, as voltage decreases, the current will
increase. If current increases, the resistance decreases and when the current reaches a
certain limit the resistance R is saturated. The voltage falls to a low value called Valley
voltage Vv. If current increases, the resistance decreases and when the current
reaches a certain limit the resistance R is saturated. The voltage falls to a low value
called Valley voltage (Vv). After this valley point if forward voltage is increased further
the emitter current increases rapidly with slight increase in emitter voltage, similar to
forward biased diode.

PROCEDURE:
1. Connections are given as per the circuit diagram.
2. VBB is kept constant and VE is varied.
3. As VE is increased, for a particular value of VE the voltmeter reading will come
down suddenly. This indicates that the UJT has started conducting. The voltage
at which the reversal takes place is called the peak voltage.
4. Afterwards the needle will settle down at a given value giving the valley voltage.
The corresponding current is the valley current. After this point, the current IE
increases rapidly even for a small increase in voltage.
5. Readings are noted and tabulated.
6. The procedure is repeated for different values of VBB
DEVICE SYMBOL:

CIRCUIT DIAGRAM:

MODEL GRAPH:

SAW TOOTH GENERATOR:

THEORY:
The UJT has negative resistance characteristic because of this character the UJT
provides trigger pulse. Any one of the three terminals can be taken for triggering pulse.
The UJT can be used as relaxation oscillator i.e. it produces non-sinusoidal waves.First
the capacitor C starts charging through the resistor R when VBB is switched on. During
the charging of the capacitor, the voltage across it increases exponentially until it reaches
to the peak point voltage VP. Up to now, the UJT is in off state, i.e nonconducting state at
which RB1 value is high. When the voltage across the capacitor reaches to peak point
voltage (VP) then, UJT comes into conducting state as the junction is forward biased and

RB1 falls to low value (50_). Then the capacitor C quickly discharges through UJT that
means the discharging time is very less as the capacitor discharges through the low
resistance UJT. When the voltage across the capacitor decreases to valley point voltage
(VV) then the UJT shifts to off state and once again the capacitor gets charged through
the resistor R and this process is repeated. This generates saw-tooth wave form across
the capacitor which can be viewed on the CRO screen.

PROCEDURE:

1. The connections are given as shown in circuit diagram.

2. VBB Supply is switched on.
3. Observe the saw-tooth waveform on CRO
4. The amplitude of the saw-tooth waveform and time taken by the capacitor to
Charge from VEB (sat) to VP is measured and tabulated.
5. From the tabulated values, output waveform is drawn.
6. The frequency of the saw-tooth waveform is calculated.
DESIGN:

Frequency, f=

TABULATION:
Inter base Voltage ,VBB =3V
S.No Emitter voltage,
Emitter
Current,IE
VE
(mA)

Inter base Voltage,VBB=5 V

Emitter voltage,
Emitter
VE
Current,IE
(V)
(mA)

(V)
1.
2.
3.
4.
5.
6.
7.

RESULT:
Thus the characteristics of UJT are drawn and intrinsic stand off ratio has been
found out and UJT relaxation oscillator output is observed.

EXPT NO:
DATE:
SINGLE PHASE HALF WAVE AND FULL WAVE RECTIFIER WITH & WITHOUT
FILTERS
AIM:
To construct half wave rectifier and full wave rectifier with and without filter and
draw their input and output waveforms.
APPARATUS REQUIRED:
S.No
1
2
3
4
5
6
7
8
9
10
11

Apparatus
Diode
Voltmeter
Milliammeter
Resistor
Capacitor
Inductor
Cathode ray
oscilloscope
Audio frequency
oscillator
Center tapped stepdown transformer
Breadboard
Connecting wires

Range
1N4007
(0-30) V
(0 100) mA
1 K
100 F
1H

1
1
Req

HALF WAVE RECTIFIER:

D.C output voltage, average value Vdc = Vm / V.
D.C output current , Idc = Im /

Vrms = Vm / 2

A.

Ripple factor, = [(Vrms/Vdc)2-1]

FULL WAVE RECTIFIER:
D.C output voltage, average value Vdc = 2Vm / V.
rms value ,
D.C output current , Idc = 2Im /

Vrms = Vm / (2 )1/2 V
A.

MC
MC

Qty
2
1
1
1
1
1
1
1

FORMULAE:

rms value ,

Type

Ripple factor, = [(Vrms/Vdc)2-1] 1/2

With filter,
Ripple factor, = 1 / 6(2)1/22LC
(or)
Ripple factor, = V(r)rms /Vdc .
Ripple component, V(r)

=----------------- (from graph)

V(r)rms =V(r) /2(3)1/2

DESIGN:

THEORY:
Half wave Rectifier:
During positive half cycle of the a.c input voltage,the diode is forward biased and
conducts for all instantaneous volatages greater than the offset voltage(0.3V for Ge and
0.7V for Si).
During negative half cycle ,the diode is reverse biased and hence it does not
conduct. Thus there is no current flow.The net result that only the positive half cycle of
the a.c input voltage appears across the load resistor.The output voltage is a steady d.c
voltage but pulsating d.c wave having a ripple frequency equal to the input voltage
frequency.
Full Wave Rectifier:
A full wave rectifier is a circuit , which allows a unidirectional current flow through the
load during the entire input cycle. There are two types of full wave rectifiers namely
centre tapped and bridge rectifier.
In a centre tapped full wave rectifier circuit, two diodes are present. The input
signal is applied to the primary winding of the transformer. The centre tap is usually
taken as ground or zero voltage reference point. During positive cycle of the input
voltage ,the diode D1 is forward biased and Diode D2 is reverse biased.During the
negative input half cycle,the diode the diode D2 is forward biased and Diode D1 is
reverse biased.the currnet through the load flows in the same direction during both half
cycles.
The output of a rectifier is a pulsating DC (i.e.) AC as well as DC components
are present at the rectifier output. The presence of an AC component is most
undesirable and therefore it must be removed from the rectifier output. It is achieved by
means of a filter circuit. The Filter circuit may be inductor , capacitor or LC filter.

PROCEDURE:
1. Connections are given as per the circuit diagram.
2. Readings are noted down from the CRO and tabulated.
3. The performance is repeated for both half and full wave rectifier with and without
filter cases.

Half Wave Rectifier

CIRCUIT DIAGRAM:
Without Filter

With Filter:

MODEL GRAPH:

Full Wave Rectifier

CIRCUIT DIAGRAM
Without Filter:

With Filter

MODEL GRAPH:

TABULATION:
HALF WAVE RECTIFIER:
From CRO,
Input voltage , peak value Vm =-----------V
VAC =

Out put voltage

Vdc
(V)
Without filter
With filter

Frequency= --------------Hz

Output current
Idc (mA)

Ripple factor

Efficiency
(VDC * IDC)/(V AC * IAC)

FULL WAVE RECTIFIER:

From CRO,
Input voltage, peak value, Vm =-----------V
VAC =

Out put voltage

Vdc
(V)

Frequency=--------------Hz

Output current
Idc (mA)

Ripple factor

Efficiency
(VDC * IDC)/(V AC * IAC)

Without filter
With filter

CALCULATION:

RESULT:
Thus the single-phase half wave and full wave rectifier with filter and without filter were
studied and their output characteristics curves were drawn.

EXPT NO:
DATE
:

STATIC CHARACTERISTICS OF PHOTO DIODE AND PHOTO TRANSISTOR

A. STATIC CHARACTERISTICS OF PHOTO DIODE
AIM:
To obtain the static characteristics of photo diode.
APPARATUS REQUIRED:
S.
No
1
2
3
4
5
6
7
8

APPARATUS
Photo diode
Voltmeter
Resistor
Ammeter
Lamp
Bread board
Regulated power supply
Connecting wires

RANGE

TYPE

(0-15)v
10ohm
(0-50)mA
100W
(0-15) V

QTY

1
1
1
1
1
1

THEORY:
If a PN junction is illuminated, hole- electron pairs are generated y the incident
light energy. Minority charge carriers are swept across the junction. Increasing the level
of illumination increases the number of charge carriers generated and thus increases
the amount of reverse current flowing. When the reverse bias voltage across a photodiode is removed, minority charge carriers will continue to be swept across the junction
while the diode is illuminated.
PROCEDURE:

Connections are given as per the circuit diagram.

Light source is placed at a certain distance from photo diode.

Supply voltage is varied from 0V and corresponding ammeter readings are

noted.

Voltage is reduced to zero and the corresponding ammeter reading is noted.

Readings are tabulated and characteristics curves are drawn.

CIRCUIT DIAGRAM:

TABULATION:
S.No

Reverse voltage (VR) in volts

Reverse current (IR) in mA

CHARACTERISTICS:

RESULT:
Thus the static characteristics of photo-diode are obtained.

B.STATIC CHARACTERISTICS OF PHOTO TRANSISTOR

AIM:
To obtain the static characteristics of photo transistor.
APPARATUS REQUIRED:
S.N
o
1
2
3
4
5
6
7
8

APPARATUS
Photo transistor
Voltmeter
Resistor
Ammeter
Lamp
Bread board
Regulated power supply
Connecting wires

RANGE

(0-30)v
220ohm
(0-100)mA
100W
(0-30) V

TYPE QTY

1
1
1
1
1
1

THEORY:
If a collector-base junction in a photo transistor is illuminated, hole- electron pairs
are generated y the incident light energy. Minority charge carriers are swept across the
junction, ICBO increases. Increasing the level of illumination, increases the number of
charge carriers generated and thus increases the amount of collector current flowing.
Photo transistor provides a much larger output current than photo diode.

PROCEDURE:

Connections are given as per the circuit diagram.

Light source is placed nearer to the base of the photo transistor.
Supply voltage is varied from 0V and corresponding ammeter readings are
noted.
Readings are tabulated and characteristics curves are drawn.

RESULT:
Thus the static characteristic of photo-transistor is obtained.

EXPT NO:
DATE:

FREQUENCY RESPONSE OF COMMON EMITTER AMPLIFIER

AIM:
To design a Common Emitter amplifier, and to draw its frequency
response.

APPARATUS REQUIRED:
S.No APPARATUS
1.
BJT
2.
Regulated power Supply
3.
Function Generator
4.
Capacitor
5.
Resistor
6.
Bread board
7.
CRO
8.
Digital multi-meter
9.
Connecting wires

RANGE

TYPE
BC 107

(0-30)V
(0-1) MHZ

(0-20) MHz

QTY
1
1
1
1 (each)
1 (each)
1
1

FORMULA USED:
Voltage Gain (dB)=20 log (Vo/Vin)
where Vo = Output Voltage (Volts) ,Vin = Input Voltage (Volts)
THEORY:
The resistor (R) and capacitor (C) forms the coupling network. The capacitor C in
couples the input signal to the base of the transistor whereas C out couples to the output
signal to the load resistor (RL). The resistors R1 and R2 provide the DC biasing. The
input signal is amplified by Q1 and appears across RC. The output of first stage is
coupled to the input of second stage/ load resistance (RL).
The voltage gain of the amplifier varies with signal frequency due to the effect of
variations in circuit capacitive reactance with signal frequency on the output voltage. If
the curve is drawn between voltage gain and signal frequency of an amplifier, it is
known as frequency response. If the input frequency of an amplifier is varied with
constant input voltage, it is observed that the amplifiers gain,

Remains constant over range of mid-frequency

Falls off at low as well as high frequencies

The falloff in amplifier gain at low frequencies is due to the effect of

coupling and bypass capacitors. At medium and high frequencies, the capacitive
reactance Xc is very small and therefore all coupling and bypass capacitors behave as
short circuits. At low frequencies, capacitive reactance increases and some of the signal
voltage is lost across the capacitors. Thus with the increase in frequency, the reactance
of the capacitor increases and therefore the gain in the circuit falls. The CE
configuration is capable of obtaining the voltage gain greater than the unity and this
configuration is the most versatile and widely used.
Low frequency roll off is determined by the coupling capacitor C in and bypass
capacitor CE. The higher frequency cut off is determined by the stray capacitance of a
transistor.
PROCEDURE:
1. The connections are given as shown in circuit diagram.
2. Sinusoidal signal is given from function generator.
3. Set the magnitude of the input as 1V (Peak to Peak) using function generator.
4. Vary the frequency in steps and note down the corresponding output voltage.
5. The measured output voltages are tabulated.
6. Calculate the voltage gain (Av) in DB using the formula.
7. Plot the graph between the frequency and gain in semi log graph sheet.
8. Draw the -3 dB line and find the bandwidth from the graph.
CIRCUIT DIAGRAM:

Design of CE amplifier
1. Choose transistor: As before, the transistor type should be chosen according to the
anticipated performance requirements.
2. Calculate collector resistor: It is necessary to determine the current flow required to
adequately drive the following stage. Knowing the current flow required in the resistor,
choose a collector voltage of around half the supply voltage to enable equal excursions of
the signal up and down. This will define the resistor value using Ohms law.
3. Calculate the emitter resistor: generally a voltage of around 1 volt or 10% of the rail
value is chosen for the emitter voltage. This gives a good level of DC stability to the
circuit. Calculate the resistance from knowledge of the collector current (effectively the
same as the emitter current) and the emitter voltage.
4. Determine base current: It is possible to determine the base current by dividing the
collector current by (or hfe which is essentially the same). If a range for is specified,
work on the cautious side.
5. Determine the base voltage: This is easy to calculate because the base voltage is simply
the emitter voltage plus the base emitter junction voltage. This is taken to be 0.6 volts for
silicon and 0.2 volts for germanium transistors.
6. Determine base resistor values: Assume a current flowing through the chain R1 + R2
of around ten times that of the base current required. Then select the correct ratio of the
resistors to provide the voltage required at the base.
7. Emitter bypass capacitor: The gain of the circuit without a capacitor across the emitter
resistor is approximately R3/R4. TO increase the gain for AC signals the emitter resistor
bypass capacitor C3 is added. This should be calculated to have a reactance equal to R4
at the lowest frequency of operation.
8. Determine value of input capacitor value: The value of the input capacitor should
equal the resistance of the input circuit at the lowest frequency to give a -3dB fall at this
frequency. The total impedance of the circuit will be times R3 plus any resistance
external to the circuit, i.e. the source impedance. The external resistance is often ignored
as this is likely to not to affect the circuit unduly.
9. Determine output capacitor value: Again, the output capacitor is generally chosen to
equal the circuit resistance at the lowest frequency of operation. The circuit resistance is
the emitter follower output resistance plus the resistance of the load, i.e. the circuit
following.
10. Re-evaluate assumptions: In the light of the way the circuit has developed, re-assess
any circuit assumptions to ensure they still hold valid. Aspects such as the transistor
choice, current consumption values, etc.

Take VCC = 10 V
I C = 4 mA (It may vary based on the requirement)
Following the steps,
1.
BC107
V
2.
VC E = CC ;
2
VC VCE VE ;
VE = 1V;
I C R C = VCC - VC ;
RC =

3.

VCC - VC
;
IC

VE = 1V;
VE = I E R E ;
IE = IC ;
R E = VE /I C ;

4.

VBE = VB - VE ;

5.

VB = VE + VBE ;

6.

VB =

VCC x R 2
;
R1 + R 2

R 1 R2 VCC
=
;
R2
VB

R2 =

VB
x (R1 + R 2 );
VCC

TABULATION:
Frequency
(HZ)

Input Signal
(mV)

Output Signal
(V)

Voltage Gain

Voltage Gain
(dB)

MODEL GRAPH:

RESULT:
Thus the frequency response of the CE amplifier has been obtained and the bandwidth
is found to be-----------------------------------.

EXPT NO:
DATE:

TRANSISTOR RC PHASE SHIFT OSCILLATOR

AIM:
To design a RC phase shift oscillator and find the frequency of oscillation.

APPARATUS REQUIRED:
S.No APPARATUS
1.
Transistor
2.
Cathode Ray Oscilloscope
3.
Resistor
4.

Resistor

5.

Capacitor

6.

Capacitor

7.
8.
9.

Bread board
Regulated power Supply
Connecting wires

RANGE

TYPE
BC 107

(0-30) MHz

QTY
1
1

(0-15)V

1
1

THEORY
The RC phase shift oscillator consists of an amplifier with 3-lead network in the
feedback path. Since an amplifier introduces 180 phase shift between input and output,
the remaining 180 phase shift is provided by connecting 3 RC combinations. Each
section produces a phase shift of 60. The phase shift oscillator finds its application in a
low frequency range.When the circuit is energized by switching on the supply, the circuit
starts oscillating. The oscillator may start due to the minor variation in dc supply. The
variation in the base current is amplified in the collector circuit. Then it is feedback
through the phase shift network and finally applied to the base. The oscillations will be
maintained if the loop gain (i.e) AV is at least equal to unity. However to start the
oscillations loop gain must be greater than unity. However to start the oscillations loop
gain must be greater than unity.
Frequency of oscillation, fO= 1/26 RC
Feedback fraction of the RC phase shift network, =1/29
PROCEDURE:
1. The connections are given as shown in circuit diagram.
2. Switch on the power supply and observe the output of oscillator circuit on a CRO.
3. Note down the practical frequency and compare it with its theoretical frequency.
4. The output waveform is plotted.

CIRCUIT DIAGRAM:

MODEL GRAPH:

Design Of RC Phase shift Oscillator

Specifications:
VCC = 12V, ICQ =1mA, =100, VCEQ = 5V, f = 1 KHz, S=10, C=0.01 f, hfe= 330, AV= 29

Following the steps,

1.

BC107
1
2. f
1000 Hz
2RC 6
Let
C 0.01F ;
R

2.

VCC
;
2
VC VCE VE ;

VCE =

VE = 1V;
I C R C = VCC - VC ;
RC =

3.

VCC - VC
;
IC

VE = 1V;
VE = I E R E ;
IE = IC ;
R E = VE /I C ;

4.

VBE = VB - VE ;

5.

VB = VE + VBE ;

6.

VB =

VCC x R 2
;
R1 + R 2

R 1 R2 VCC
=
;
R2
VB

R2 =

VB
x (R1 + R 2 );
VCC

TABULATION:
X-Axis
No.of
Time/div
divisions

Y-axis
No.of
Amp/div
divisions

Time
Period (T)

Amplitude

CALCULATION:
1. Theoretical frequency, fO= 1/26 RC

2. Practical frequency, f=1/T

RESULT:
Thus the performance of RC phase shift oscillator was tested and its output waveform
was drawn.

EXPT NO:
DATE:

HARTLEY OSCILLATOR

AIM:
To design and construct a Hartley oscillator at the given operating frequency.

APPARATUS REQUIRED:
S.No APPARATUS
1.
Transistor
2.
Cathode Ray Oscilloscope
3.
Resistor

4.
5.

Decade Inductance Box

(DIB)
Capacitor

6.

Capacitor

7.
8.
9.

Bread board
Regulated power Supply
Connecting wires

RANGE
(0-30) MHz

(0-30)V

TYPE
BC 107
(0-30)MHZ

QTY
1
1

1
1

THEORY
Hartley oscillators are widely used in radio receivers. The tuned circuit consists of
L1, L2 and C. The biasing is provided by R1 and R2. The collector current charges the
capacitor C which later on discharges through L1 and L2. The oscillations across L1 and
L2 are given to the base circuit, which are amplified by the transistor. The output of the
transistor supplies for the losses occurring in the oscillatory circuit, thus the circuit
produces undamped oscillations
Frequency of oscillation, fO= 1/2LTC
Where LT=L1+L2
PROCEDURE:
1. The connections are given as shown in circuit diagram.
2. Switch on the power supply and observe the output of oscillator circuit on a CRO.
3. Note down the practical frequency and compare it with its theoretical frequency.
4. The output waveform is plotted.

CIRCUIT DIAGRAM:

MODEL GRAPH:

Design of LC Oscillator
Design of feed back Network :
Given L1 L 2 10mH, f 20 KHz, VCC 12V, I C 3mA,
f

1
2 (L1 L 2 )C

Amplifier Design
Following the steps,
1.
BC107
2.

VCC
;
2
VC VCE VE ;

VCE =

VE = 1V;
I C R C = VCC - VC ;
RC =

3.

VCC - VC
;
IC

VE = 1V;
VE = I E R E ;
IE = IC ;
R E = VE /I C ;

4.

VBE = VB - VE ;

5.

VB = VE + VBE ;

6.

VB =

VCC x R 2
;
R1 + R 2

R 1 R2 VCC
=
;
R2
VB

R2 =

VB
x (R 1 + R 2 );
VCC

TABULATION:

No.of
divisions

X-Axis
Time/div

No.of
divisions

Y-axis
Amp/div

Time
Period (T)

Amplitude

CALCULATION:

1. Theoretical frequency, fO= 1/2LTC

2. Practical frequency, f = 1/T

RESULT:
Thus the performance of Hartley oscillator was tested and its output waveform was
drawn.

EXPT. NO.:
DATE:

DIFFERENTIAL AMPLIFIER

AIM:
To design a differential amplifier circuit and also to obtain differential mode and
its common mode gain .
APPARATUS REQUIRED:
S.No

APPARATUS

Range

Quantity

1.
2.

BC 107
(0-12) V

2
1

3.
4.
5.
5
6.
7.

Transistor
Regulated Power Supply
(Dual)
Resistor
Resistor
Resistor
Function generator
Bread board
Cathode ray oscilloscope,

22
1.5k
100
(0-1) MHz

2
2
2
2
1
1

8.

Multi-meter

Connecting wires

As req

25 MHz

FORMULA USED:
Ad = Voltage gain of the amplifier for differential signals.
Ac = Voltage gain of the amplifier for common mode signals
Differential mode gain,Ad = VO / Vd ,
Where, VO =VO1 VO2
Vd = Vin1 Vin2
Common mode gain,AC = VO / VC
Where, VO =VO1 VO2
VC = (Vin1 + Vin2) / 2
Common mode rejection ratio, CMRR = Ad / Ac

CMRR (dB) = 20 log (Ad / Ac

THEORY:
An amplifier, which is designed to give the difference between the two input
signals, is called the differential amplifier. There are two inputs and two outputs in the
circuit. Inputs are applied essentially to each base of the two separate transistors T1 &
T2. However the transistor emitters are connected to a common emitter resistor so that
the two output terminalsV1out & V2out are affected by either or both input signals.
There are two supply voltages in the circuit and it should be carefully noted that no
ground terminal is indicated within the circuit although the opposite points of both
positive and negative voltage supplies are to be connected to the ground. The amplifier
could also operate using a single voltage supply.
The advantage of the differential amplifier is that hum and noise signal, called the
common mode signal, which is common to both inputs is cancelled out in the output.
Practically, a differential amplifier does not have perfect balance because two
transistors can never be perfectly identical. This means that some common mode will
appear at the output. The ability of rejecting the common mode signal is given by the
common mode rejection ratio (CMRR). It is given by the ratio of voltage gain of amplifier
for differential signals (Ad) to voltage gain of amplifier for common mode signals (Ac).
CMRR = Ad / Ac
PROCEDURE:
1. Give the connections as per the circuit diagram.
2. Apply Input signals 1 and 2 in the common mode (both inputs are connected to
same source) and obtain the corresponding output signal in CRO.
3. Calculate the gain of the amplifier in the common mode.
4. Apply the input signals 1 and 2 in differential mode and obtain the corresponding
signal in CRO.(only one input at a time)
5. Calculate the gain of the amplifier in differential mode.
6. Calculate CMRR.
7. The input and output waveforms (common mode & differential mode) are drawn
on the graph.

CIRCUIT DIAGRAM:

CALCULATION:
Differential mode component : Vd = (V1-V2)
Common mode component : Vcm = (V1+V2)/2
Adm =Vo / Vd =

Acm

=--------------

CMRR = 20 log (Ad/Acm)

RESULT:
The differential amplifier has been designed and its CMRR is obtained as ----------dB.

EXPT NO:
DATE:

ASTABLE MULTIVIBRATOR

AIM:
To design an astable multivibrator and to determine the frequency of oscillation of the
output waveform.

APPARATUS REQUIRED:
S.No APPARATUS
1.
Transistor
2.
Cathode Ray Oscilloscope
3.
Resistor

4.

Capacitor

5.
6.
7.

Bread board
Regulated power Supply
Connecting wires

RANGE
(0-30) MHz

TYPE
BC 107

QTY
2
1
Each 2

(0-15)V

1
2

THEORY
The astable multivibrator has two quasi-stable states. It is also called as a freerunning relaxation oscillator and is commonly used to generate square waveform. The
transistor Q1 is forward biased by the VCC supply through R1 and transistor Q2 by R2.
The output of Q1 is coupled to the input of Q2 through the capacitor C1 and vice versa
through the capacitor C2. It may be thought of as two common emitter amplifying
stages. Each stage provides a feedback through a capacitor at the input of the other.
Since the amplifying stage introduces a 180 phase shift, another 180 phase shift is
introduced by a capacitor therefore a total of 360 or 0.
PROCEDURE:
1. The connections are given as shown in circuit diagram.
2. Observe the output waveform of the astable multivibrator on CRO.
3. The amplitude and time period values of the output waveforms (V C1 and VC2) are
noted from CRO.
4. The practical frequency is calculated and compared with the theoretical
frequency.
5. The output waveforms are plotted.

Design example:
Given specifications:
VCC= 10V; hfe = 100; f =1 KHz; IC = 2 mA; VCE (sat) = 0.2 V;
To design RC:
RC = VCC VCE (Sat) / IC
= 4.9 k
Since R hFE RC
Therefore R 100 x 4.9 x103 = 490 k

To Design C:
Since T= 1.38RC
1x10-3 = 1.38x 490x103x C

Therefore C = 0.01F

CIRCUIT DIAGRAM:

MODEL GRAPH:

TABULATION:

No.of
divisions

X-Axis
Time/div

No.of
divisions

Y-axis
Amp/div

Time
Period (T)

Amplitude

CALCULATION:
The practical frequency, f = 1/T

RESULT:
Thus the astable multivibrator was constructed and its output waveform was
obtained.

EXPT NO:
DATE:

MONOSTABLE MULTIVIBRATOR

AIM:
To construct a monostable multivibrator and to obtain its output waveform
APPARATUS REQUIRED:
S.No APPARATUS
1.
Transistor
2.
Cathode Ray Oscilloscope
3.
Resistor

RANGE
(0-30) MHz

TYPE
BC 107

QTY
2
1
Each 1

4.

Resistor

5.

Capacitor

Each 1

6.
7.
8.
9.

Function generator
Bread board
Regulated power Supply
Connecting wires

1 MHZ
(0-15)V

1
1
2

THEORY
The monostable multivibrator has one stable state (i.e) when T 1 is conducting. During
this period, the transistor T2 does not conduct. In order to make T 2 to conduct, an
external trigger pulse is required which will make T2 forward biased. Again T2 will remain
in conducting state, unless the pulse is again applied which make T 1 forward biased and
drives T1 into the conducting state. In this way, pulse is required to bring a transistor into
conducting state. And the other transistor becomes OFF after a predetermined period.
The external triggering pulse is supplied from the terminal.

PROCEDURE:
1. The connections are given as shown in circuit diagram.
2. Switch on the power supply and negative triggering pulse is given through a
pulse generator.

3. Observe the output waveform of the monostable multivibrator on CRO.

4. The amplitude and time period values are noted from CRO ( for both trigger
pulse and VC2 waveforms)
5. The output waveforms are plotted.

CIRCUIT DIAGRAM:

Design Example:
Given specifications:
VCC= 12V; hfe = 200; f =1 KHz; IC = 2mA; VCE (sat) = 0.2 V; VBB= 2 V;
(i)To calculate RC:
RC = VCC - VCE (sat) / IC
RC = 12 0.2 / 2x10-3=5.9K

(ii) To calculate R:
IB2(min) = IC2 / hfe= 2x10-3 / 200 = 10 A
Select IB2 > IB1(min) (say 25 A)
Then R = VCC V BE (sat) / IB2
Therefore R= 12 0.7/25 x 10-6=452 K
(iii) To calculate C:
T=0.69RC
1x10-3= 0.69 x 452 x 103 x C
C=3.2nf
MODEL GRAPH:

TABULATION:

No.of
divisions

X-Axis
Time/div

No.of
divisions

Y-axis
Amp/div

Time
Period (T)

Amplitude

CALCULATION:
The width of the pulse is given by
tp = 0.69 RC

RESULT:
Thus the monostable multivibrator was constructed and its output waveform
was obtained.

EXPT NO:
DATE:
REALIZATION OF PASSIVE FILTERS

AIM:
To realize the passive filters and also to determine the resonant frequency from
the obtained frequency response.
APPARATUS REQUIRED:
S.No
APPARATUS
1.
Function Generator
2.
CRO
3.
DRB (Decade Resistance
Box)
4.
DCB (Decade
Capacitance Box)
5.
DIB( Decade Inductance
Box)
6.
Bread Board
7.
Connecting Wires

RANGE
(0-1) MHz
20 MHz

TYPE

QTY
1
1
1
1
1
1
As required

THEORY:
(a)High Pass Filter (HPF)
HPF allows only high frequency signals of AC voltage to the output and rejects
the low frequency components. XC (1/f).
At low frequency, reactance is very high. So HPF doesnt allow any signal to the
output.
But at high frequency, reactance is very low. Hence HPF allows all the high
frequency signals to the output.
(b) Low Pass Filter (LPF)
LPF allows only low frequency signals of AC voltage to the output and rejects the
high frequency components. XL f

At low frequency, reactance is very low. So LPF allows all low frequency signals
to the output.
But at high frequency, reactance is very high. Hence LPF doesnt allow any signal
to the output.

FORMULA USED:
Voltage Gain, AV=V0/Vin= AV= 20 log 10 (V0/Vin) (dB)
Vo= Output Voltage
Vin=Input Voltage

PROCEDURE:
1. Connections are given as per the circuit diagram.
2. Function generator is adjusted to get a sine wave whose magnitude is 2V.
3. The frequency is varied and the output voltage is noted down from the CRO.
4. Graph is plotted and cut-off frequency is calculated.

CIRCUIT DIAGRAM
LOW PASS FILTER

HIGH PASS FILTER

R = 10 k

C = 1000 pF

MODEL GRAPH
LOW PASS FILTER

HIGH PASS FILTER

TABULATION
LOW PASS FILTER
S.No Frequency (Hz) Output
Voltage
V0 (V)

Vin=
Voltage
Gain,
AV=Vo/Vin

Gain (dB)
=20 log 10 AV

HIGH PASS FILTER

S.No Frequency (Hz) Output
Voltage
V0 (V)

RESULT:

Vin=
Voltage
Gain,
AV=Vo/Vin

Gain (dB)
=20 log 10 AV