7 Registers and Counters

Chapter 7 REGISTERS AND COUNTERS

7.1 Registers
In general, a register is used for storing and shifting digital data (0s
and 1s). In some cases, it may be used as a counter. The basic
element of a register is a flip-flop. Remember that a flip-flop stores
a 1-bit data (either a 0 or a 1)? If we group a few flip-flops together,
we form a register. An n-bit register stores n bits of data and
consists on n flip-flops connected together.
The storage capability of a register makes it an important type of
memory device. The diagram below shows how a positive edgetriggered D flip-flop stores data.
0 is stored
1 is stored
1

When D = 1, then Q = 1 at the triggering edge of CLK. Q remains

at 1 indefinitely unless D becomes 0. When D = 0, then Q = 0 at
the triggering edge of CLK. Q remains at 0 indefinitely until D
becomes 1. Instead of using D flip-flops to implement the above,
we can also use JK flip-flops. The idea is to convert the JK flipflop into a D flip-flop by letting J = D and K = D.
The shifting capability of a register refers to its ability to move
data within the register. There are a variety of implementations
used to shift data in and out of a register. The figures below show a
few implementations in a 4-bit register.

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Data in

Data out

Data in

Data out

Serial in / Serial out

Serial in / Parallel out
Data in

Rotate right
Data out

Parallel in / Parallel out

7.1.1 Shift Registers
The term shift register is used to highlight that the register also
moves data. Shift registers are used in digital systems where there
is only one input data line and that the registers cannot be loaded in
parallel. Instead, the bits are shifted in one at a time, from the right
or from the left.
7.1.1.1 Serial in / Serial out Shift Register
The serial in / serial out shift register accepts data serially, that is,
one bit at a time on a single line. The diagram below shows a 4-bit
device implement with D flip-flops. With four stages, this register
can store up to 4 bits of data.
Serial
data input

FF0
D
CLK

FF1

Q0

D
CLK

FF2

Q1

D
CLK

FF3

Q2

Q3

Serial
data

CLK

CLK
2

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Suppose we want to store the 4 bit data 1010 into the register,
beginning with the right-most bit. Assume the register is initially
clear (Q0 = Q1 = Q2 = Q3 = 0).
The 0 is put onto the data input line, making D = 0 for FF0. When
the first clock pulse is applied, FF0 is reset, thus storing the 0. The
second bit, which is a 1, is applied next to the data input. When the
second clock pulse occurs, the 1 on the data input is shifted into
FF0, causing FF0 to set, and the 0 that was in FF0 is now shifted
into FF1.
The third bit, a 0, is now put onto the data-input line, and the clock
pulse is applied. The 0 is entered into FF0, the 1 stored in FF0 is
shifted into FF1, and the 0 stored in FF1 is shifted into FF2. Do
you see why it is called a shift register now?
The last bit, a 1, is now applied to the data input, and a clock pulse
is applied. This time the 1 is entered into FF0, the 0 stored in FF0
is shifted to FF1, the 1 stored in FF1 is shifted into FF2, and the 0
stored in FF2 is shifted into FF3. This completes the serial entry of
the 4 bits into the shift register, where they can be stored as long as
the flip-flops have dc power.
Note that data is stored in the register on each CLK edge (rising in
this case). In summary, the storage and shifting process can be
summarized as:
input at D0 output at Q0 output at Q1 output at Q2 output at Q3
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
1
1
0
1
0

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To get the data out of the register, the bits must be shifted out
serially and taken off the Q3 output. If we apply a CLK pulse, the
right-most bit, 0, appears on the Q3 output. In the second CLK
pulse, the second bit appears at Q3 output. The third CLK pulse
shifts the third bit to the output, and the fourth CLK pulse shifts the
fourth bit to the output.
output at Q0 output at Q1 output at Q2 output at Q3
1
0
1
0
0
1
0
1
0
0
1
0
0
0
0
1
0
0
0
0

Output
0
1
0
1

The logic block diagram of a 4-bit serial in / serial out shift register
is shown below.
Data in

SRG 4

Q3

CLK

Q3

7.1.1.2 Serial in / Parallel out Shift Register

The figure below shows a 4-bit serial in / parallel out shift register.
Q1

Q0

Data
input

D
CLK

D
CLK

Q2

D
CLK

Q3

D
CLK

CLK

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The operation of the serial in / parallel out shift register is the same
as that of the serial in / serial out register except that the data out is
Q0, Q1, Q2, Q3. Whereas the data out for the serial in / serial out
register is Q3 only.
The logic block diagram of a 4-bit serial in / parallel out shift
register is shown below.
Data in

SRG 4

CLK

Q1 Q2 Q3 Q4
7.1.2 Data Transfers between Register
It is common to transfer data from one register to another in a
digital system. The data is usually sent through common data lines
called the data bus. A bus is a group of wires that perform a
common function.
To prevent damage to outputs of inactive registers, the outputs of
the registers are connected to tri-state buffers. The diagram below
shows a 4-bit parallel in / parallel out register with tri-state outputs:

7 Registers and Counters

The operation of the parallel in / parallel out shift register is

straight-forward. When the rising clock edge is detected, the
outputs become equal to the inputs, all at the same time.
The whole register can be represented as:

The slash with a number beside it indicates the number of bits that
the wire carries. Several registers can be connected to a data bus as
shown:
Data bus has
inputs / outputs

7.1.3 Parallel Adder with Accumulator

In computer circuits, it is often desirable to store one number in a
register (called known as an accumulator) and add a second
number to it. The sum is then stored back in the accumulator.

7 Registers and Counters

We use a parallel adder to perform the summing process. One way

to build a parallel adder with an accumulator is to add a register to
the adder. The diagram below shows a 4-bit parallel adder with
accumulator:

Suppose that the number X = x3x2x1x0 is stored in the accumulator.

Then the number Y = y3y2y1y0 is applied to the full adder, and after
the carry has propagated through the adders, the sum of X and Y
appears at the adder outputs, S = X + Y. An Add signal is used to
load the adder outputs into the accumulator flip-flops on the rising
clock edge. For example, if s1 = 1, the next state of the flip-flop x1
will be 1. If s1 = 0, the next state of the flip-flop x1 will be 0.
Note: CE is the same as EN(able). When CE = 0, the D flip-flop is
off. When CE = 1, the D flip-flop is on and acts as normal.
Observe that the adder with accumulator consists of a number of
identical cells. Each cell contains a full adder and an associated
accumulator flip-flop. Cell 0, for example, has inputs c0, x0, y0 and
output c1 and s0.
7.1.4 Shift-Register Counters
A shift register counter is basically a shift register with the serial
output connected back to the serial input to produce special
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7 Registers and Counters

sequences. These devices are often classified as counters because

they exhibit a specified sequence of states.
7.1.4.1 Ring Counters
A ring counter is a circular shift register with only one of the flipflops in state 1 at any particular time to produce a sequence of
timing signals. In a circular shift register, the registers output is
fed back to the input.
For a ring counter with 4 states, logic 1 circles through the shift
register every 4 clock pulses.

In the diagram above, T0 is the LSB and T3 is the MSB. When the
input Initialize is set to 1, the first flip-flop is preset (T0 = 1) and
the rest of the flip-flops are cleared (T1 = T2 = T3 = 0) on the first
CLK pulse. Because T3 is fed back to the input of the first flip-flop,
on the second CLK pulse, T0 = 0 because T3 = 0. And T1 = 1, T2 =
0. On the third CLK pulse, T2 = 1 (T0 = T1 = T3 = 0). On the fourth
CLK pulse, T3 = 1 (T0 = T1 = T2 = 0). After that, the process
repeats.
T3 T2 T1 T0
4-bit ring counter sequence
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
1 and repeats.
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7 Registers and Counters

7.1.4.2 Johnson Counters (Twisted-Ring Counters)

In a Johnson counter, the complement of the output of the last flipflop is connected back to the D input of the first flip-flop. Because
of this connection, an n-bit Johnson counter produces 2n outputs.
For a 4-bit device, there are a total of eight states for its output.
The diagram below shows a 4-bit Johnson counter.

Suppose the initial state is 0000. Because E = 1 and is fed back to

the input of the first flip-flop, A = 1 on the next CLK pulse. It will
sequence through 1000, 1100, 1110, 1111 on the subsequent CLK
pulses. Now, since E = 1, E = 0, on the next CLK pulse, the input
of the first flip-flop becomes A = 0, i.e., 0111. Then, the sequence
0011, 0001, 0000 follows and the process repeats itself again.
A
0
1
1
1
1
0
0
0

B
0
0
1
1
1
1
0
0

C
0
0
0
1
1
1
1
0

E
0
0
0
0
1
1
1
1

and repeats

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7.2 Asynchronous Counters

An asynchronous counter or a ripple counter, is a counter where
the state changes are not controlled by a common clock pulse.
Below is a 3-bit asynchronous binary counter. Notice that the clock
signal, CLK is applied only to the first flip-flop (LSB). The CLK
of the second and third flip-flop depends on the Q output of the
previous flip-flop.
Q2

Q0

Q1

1
Q
Q

CLR

CLR

J
CLR

CLK
CLR

As a result, the three flip-flops are never triggered simultaneously

due to propagation delay time through each flip-flop. Also note
that the J and K inputs to each flip-flop are set to HIGH. This turns
each JK flip-flop into a T flip-flop. Hence, each time the CLK edge
is falling, the output of the T flip-flop toggles. We use CLR (clear)
to initialize the counter to the 0 state.
Toggles on each
falling CLK edge
CLK
Q0 (LSB)
Toggles on each
rising Q0 edge
or on each
falling Q0 edge

Q1
Q2 (MSB)
7

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7 Registers and Counters

Count sequence is 7,6,5,4,3,2,1,0 repeats. Hence, this is a binary

down counter.
One disadvantage of an asynchronous counter is that the
cumulative delay in an asynchronous counter limits the rate the
counter can be clocked. The maximum delay must not be more
than the period of CLK.
7.3 Synchronous Counters
In synchronous counters, all the flip-flops are clocked
simultaneously with a common clock pulse. That is, all flip-flops
have a common CLK input.
counts from 0 to 7
and repeats
Below is a 3-bit synchronous binary counter.

Again, each JK flip-flop is turned into a T flip-flop. Consider that

initially Q2Q1Q0 = 000. And J0 = K0 = 1, J1 = K1 = 0 because Q0 =
0 and J2 = K2 = 0 because Q0 = Q1 = 0.
On the first rising edge of CLK, Q0 toggles to 1 while Q1 and Q2
remain at 0. Hence, the output is Q2Q1Q0 = 001. And now, J1 = K1
= 1 because Q0 = 1 and J2 = K2 = 0 because Q0 = 1 but Q1 = 0.
On the second rising edge of CLK, Q0 toggles to 0. Q1 toggles to 1.
And Q2 remains 0. Hence, the output is Q2Q1Q0 = 010. And J1 = K1
= 0 because Q0 = 0 and J2 = K2 = 0 because Q0 = 0 but Q1 = 1.

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7 Registers and Counters

On the third rising edge of CLK, Q0 toggles to 1. Q1 remains at 1

(because previous Q0 = 0). And Q2 remains at 0. Hence, the output
is Q2Q1Q0 = 011. And J1 = K1 = 1 because Q0 = 1 and J2 = K2 = 1
because Q0 = 1 and Q1 = 1.
On the fourth rising edge of CLK, Q0 toggles to 0. Q1 toggles to 0.
And Q2 toggles to 1. Hence, the output is Q2Q1Q0 = 100. And J1 =
K1 = 0 because Q0 = 0 and J2 = K2 = 0 because Q0 = 0 and Q1 = 0.
And so on
Q1
Q2 Q0Q1 Q0+
Q1+ Q2+ Q2+Q1+Q0+
CLK Q0
1
0
0
0
0
1
0
0
001
2
1
0
0
0
0
1
0
010
3
0
1
0
0
1
1
0
011
4
1
1
0
1
0
0
1
100
5
0
0
1
0
1
0
1
101
6
1
0
1
0
0
1
1
110
7
0
1
1
0
1
1
1
111
8
1
1
1
1
0
0
0
000
Summary:
1) Q0+ toggles on every rising edge of CLK.
J0 = K0 = 1 Q0 toggles on rising CLK
2) Q1+ toggles when Q0 = 1.
+
J1 = K1 = Q0 Q1 toggles if Q0 = 1 and
3) Q2 toggles when Q0Q1 = 1.
The timing diagram is shown below.

on rising CLK
J2 = K2 = Q0Q1 Q2 toggles if Q0Q1 = 1
and on rising CLK

Q1 pulse lasts
for 2 CLK
pulses

7.3.1 Modulo-N Counters

1
2
3

Q2 pulse
lasts for 4
CLK pulses

0
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7 Registers and Counters

Counters that can count from state 0 through state (N - 1) and then
cycle back to state 0 are called modulo-N counters. However, for
binary counters with n flip-flops, there can be a maximum number
of 2n states. Hence, if we want an N that is less than 2n, we need to
reset the counter once the Nth state is reached.
For example, if N = 10, we have a decade (modulo-10) counter. To
build this counter, we need four flip-flops since 24 = 16 (three flipflops are not enough since it counts only to 23 = 8 states). Hence, a
decade counter is a counter whereby it will be reset to state 0 (0000)
after state 9 (1001) is reached.

To summarize the operation of the mod-10 counter:

a) Q0 toggles on each rising edge of the clock, CLK as J0 = K0 = 1.
b) Q1 changes on the next rising edge of CLK (to Q1+) when Q0 = 1
and Q3 = 0.
c) Q2 changes on the next rising edge of CLK (to Q2+) when both
Q0 and Q1 equal 1.
d) Q3 changes to the opposite state on the next rising edge of CLK
(to Q3+) when Q0 = Q1 = Q2 = 1 (state 7) or when Q0 = Q3 = 1
(state 9).

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7 Registers and Counters

7.3.2 Up/Down counters

An up/down counter or bi-directional counter can count in either
direction through any specified sequence of states.
For example, an up/down 3-bit binary counter can go through the
following sequence
0,1,2,3,4,5,4,3,2,3,4,5,6,7,6,5 ..etc

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7 Registers and Counters

Refer to Floyd p476 or Roth p335 for explanation.

7.4 Design of Synchronous Binary Counters
Counter design is a good start for you to understand the design of
finite state machines.
There are various counters such as those that can count up and
down, and those that produces sequences of binary numbers
neither in ascending or descending order. These counters can be
built from D, T, S-R and J-K flip-flops. A systematic way to
design such counters is to use state tables, which relate the next
output to the present output.
General Steps to Counter Design:
1. Specify the counter sequence and draw a state diagram.
2. Derive a next-state table.
3. Develop the flip-flop transition table showing the excitation
inputs required for each transition.
4. Derive the Karnaugh maps for each input of each flip-flop in
the counter.
5. Use K-maps to obtain the logic expressions for flip-flop
inputs.
6. Realize the counter.
Consider the three T flip-flops connected as shown below:

Assume all flip-flops are at 0 initially.

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7 Registers and Counters

This is the 3-bit synchronous counter discussed earlier.

a) Since TA = 1, output A toggles at every rising edge of the clock,
forming the sequence 0, 1, 0, 1, 0, 1, 0, 1, .
b) Since TB = A, output B toggles at every other rising edge of the
clock, forming 0, 0, 1, 1, 0, 0, 1, 1, .
c) Since TC = AB, output C toggles at the rising edge after every 4
note the order
clock pulses, forming 0, 0, 0, 0, 1, 1, 1, 1, .
of variables
Thus it can be seen that the sequence of outputs CBA is 000, 001,
010, 011, 100, 101, 110, 111 and the sequence repeats.
To design the above counter using T flip-flops, we first set up the
state table of the counter from the sequence. State table and flipflop inputs required are shown below.
Present

Flip-flop
inputs

Next state

where the inputs for T flip-flop are given by the truth table below:
Q
0
0
1
1

Q+
0
1
0
1

T
0
1
1
0

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7 Registers and Counters

By inspection of the state table, TA = 1. The K-maps for TB and TC

are shown below:

See how TA = 1, TB = A and TC = AB are connected to the outputs

in the circuit above?
If the counter were to be redesigned using D flip-flops, one easy
way is to replace each T flip-flop with a D flip-flop and an XOR
gate as shown (refer to Chap 6):

We can also start with the state table. Since Q+ = D (output follows
input), we have

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7 Registers and Counters

where the inputs for D flip-flop are given by the truth table below:
Q
0
0
1
1

Q+
0
1
0
1

D
0
1
0
1

By inspection, we see that DA = A. The K-maps for DC and DB are

DC

DC

= CBA+CB+CA
= CBA+C(BA)
= C BA

DB

DB

= BA+BA
=BA

Example 7.1
Design a counter using T flip-flops that counts in the following
way:

The state table is

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7 Registers and Counters

In the truth table above, there are no T flip-flop inputs. So, how
do we construct the K-maps for the T flip-flops? For details,
refer to Roth p338. Here, I will give you an outline. First, we
construct the truth table for C+, B+ and A+ using A, B, C as
inputs. Then, we can convert these truth tables into TC, TB and
TA truth tables as follows:
For the C+ Karnaugh map, a 1 is placed on the cell where there
is a toggle, i.e., if C = 0 and C+ = 1 or if C = 1 and C+ = 0. If
C = C+, there is no toggle and the cell has a value of 0.
Similarly, for the B+ Karnaugh map, look for a toggle in the B
variable and for A+ Karnaugh map, toggle in A. For example,
the K-map of C+ is
C
BA

00

01

11

10

X
C+

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7 Registers and Counters

Note that for Q+ Q (toggling), T = 1. The K-maps for TC, TB

and TA:

Draw the logic circuit yourself.

Counter Design Using S-R Flip-Flops
The table below shows S and R inputs necessary for the various
output changes:

If we want to design the counter in Example 7.1 that produces

outputs 000 100 111 010 011 000 using S-R
flip-flops, we can set up the state table and develop the required
flip-flop inputs.
+

+ +

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7 Registers and Counters

The K-maps are

Draw the logic circuit yourself.

Counter Design Using J-K Flip-Flops
The table of J and K values needed to change Q to Q+ is shown
below:

State table for a counter made of J-K flip-flops producing the

sequence 000 100 111 010 011 000 is

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7 Registers and Counters

The K-maps are

Draw the logic circuit yourself.

7.5 Self-starting Counters
When a circuit is first powered-up, the initial states of the flip-flops
are undefined. They could be 1 or 0. This leads to a problem
especially for counters that do not use all state combinations.
What would happen if for example the counter in Example 7.1 had
entered state 001 or 101 or 110 on start-up?

The counter may never enter the designed sequence at all or the
sequence transition eventually leads into the main counting
sequence. This will depends on how dont cares have been mapped
into 0s and 1s by the implementation procedure.
A self-starting counters is one where every possible state including
those not in the desired count sequence, has a sequence of
transitions that eventually leads to a valid counter state. So, no

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7 Registers and Counters

matter how the counter starts up, it will eventually enter the desired
counter sequence.
To check whether a counter is self-starting:
Replace the dont cares in the K-maps with the actually assigned
1s and 0s. Remap the K-maps to obtain the effects on each flipflops state.

TC
C0
BA
00 1
01 1
11 0
10 0
Present State

TB

C0
BA
00 0

1
1

01 1

TA
C0
BA
00 0
01 0

11 1

11 1

10 0

10 1

1
0

C + B+

A+

0
0
0
0
1
1
1
1

1
1
0
0
1
1
0
0

0
1
1
0
1
0
1
0

0
1
0
1
0
1
0
1

Next State

C B A
0
0
1
1
0
0
1
1

1
1

0
1
1
0
1
1
1
1

110
001
101

23