THC HNH SOC

Bi 1 - GII THIU

1. MC CH
Thng qua bi thc hnh ny, sinh vin s hiu r
o Cch thit k mt my tnh hon chnh t vic xy dng phn cng n phn mm.
o Cch s dng cng c Quartus II v Qsys to phn cng my tnh, tng hp v np
xung FPGA.
o Cch s dng cng c NIOS II tng hp v np phn mm xung my tnh.

2. NI DUNG
2.1. H thng phn cng
2.1.1. To project Quartus

ng dn th mc cha project khng c c khong trng

Nu s dng board DE2-115, chn Family l Cyclone IV E, device l EP4CE115F29C8

Nu s dng board DE2, chn Family l Cyclone II, device l EP2C35F672C6

2.1.2. Xy dng h thng SoPC s dng Qsys

Cc thnh phn h thng

Th vin

Hin th thng bo

Trong ca s th vin, g vo tm kim On-chip memory, chn on-chip memory

(RAM or ROM), click Add

Cu hnh nh bn di, click Finish

Tm Nios II processor v thm vo h thng

 tab Core Nios II, chn Nios II/e, click Finish

Tm kim JTAG UART v thm vo h thng

Click Finish

H thng hon chnh nh hnh bn di

Kt ni tn hiu clk t module clk_0 n cc module khc

Kt ni tn hiu clk_reset t module clk_0 n cc module khc

Kt ni interface data master t module nios2_qsys_0 n cc interface khc

Kt ni interface instruction master t module nios2_qsys_0 n cc interface khc

Kt ni interface jtag_debug_module_reset t module nios2_qsys_0 n cc

interface khc

Kt ni tn hiu irq t module jtag_uart_0 n module nios_qsys_0

Sau khi kt ni xong s c h thng nh bn di

Gn a ch cho cc module

Sa li cu hnh ca module nios_qsys_0

Click Finish

H thng phn cng hon thnh, khng cn thng bo li. Save li h thng vi tn
nios_sys

Chuyn sang tab Generation, click Generate

2.1.3. Tch hp h thng vo project Quatus

G ng dn nios_sys/synthesis/nios_sys.qip vo File name v click Add, click

OK

To file top module, t tn l lab1.v

Ni dung ca file lab1.v nh hnh bn di

Gn pin cho cc tn hiu (Assignment > Import asignments) v build project Quartus.

Download h thng phn cng xung board

Click Start

2.2. Lp trnh phn mm

Khi ng chng trnh Nios II EDS t Qsys

Chn th mc workspace, khng c c khong trng trong ng dn th mc

To project NIOS II EDS

mc SOPC Information File name, chn file nios_sys. sopcinfo. t tn project l

lab1. Chn Templates l Blank project. Click Finish

Click chut phi vo lab1, chn New, Source File

t tn file l lab1.c, click Finish

Ni dung ca file lab1.c nh bn di

Vo menu Project, chn Build all

Dowload phn mm xung board

Ca s debug hin ra nh bn di

BO CO THC HNH
BI 1: GII THIU
Sinh vin:
...
Lp: Nhm: ......

Bi 1: Cho bit ngha v phm tt ca cc biu tng sau trong ca s debug ca NIOS
II EDS

Bi 2: Bin dch v debug on code sau

Ph lc Ci t Quartus II, Altera Modelsim, NIOS 2 IDE (version 13.0.1)

* Yu cu
- Window 32-bit/64-bit
- cng trng ti thiu 10GB

* Cc bc ci t
Chy file ci t QuartusSetupWeb-13.0.1.232

ng dn th mc ci t khng c c khong trng

Sau khi ci t xong, khi ng Quartus 2 v chn nh bn di